This is an archive of the discontinued LLVM Phabricator instance.

	Show First 20 Lines • Show All 1,747 Lines • ▼ Show 20 Lines
	defm vnsrl : RVVUnsignedNShiftBuiltinSet;			defm vnsrl : RVVUnsignedNShiftBuiltinSet;
	defm vnsra : RVVSignedNShiftBuiltinSet;			defm vnsra : RVVSignedNShiftBuiltinSet;
	}			}
	defm vncvt_x_x_w : RVVPseudoVNCVTBuiltin<"vnsrl", "vncvt_x", "csi",			defm vncvt_x_x_w : RVVPseudoVNCVTBuiltin<"vnsrl", "vncvt_x", "csi",
	[["v", "vw"],			[["v", "vw"],
	["Uv", "UvUw"]]>;			["Uv", "UvUw"]]>;

	// 12.8. Vector Integer Comparison Instructions			// 12.8. Vector Integer Comparison Instructions
	let MaskedPolicyScheme = NonePolicy in {			let MaskedPolicyScheme = HasPassthruOperand,
				HasTailPolicy = false in {
	defm vmseq : RVVIntMaskOutBuiltinSet;			defm vmseq : RVVIntMaskOutBuiltinSet;
	defm vmsne : RVVIntMaskOutBuiltinSet;			defm vmsne : RVVIntMaskOutBuiltinSet;
	defm vmsltu : RVVUnsignedMaskOutBuiltinSet;			defm vmsltu : RVVUnsignedMaskOutBuiltinSet;
	defm vmslt : RVVSignedMaskOutBuiltinSet;			defm vmslt : RVVSignedMaskOutBuiltinSet;
	defm vmsleu : RVVUnsignedMaskOutBuiltinSet;			defm vmsleu : RVVUnsignedMaskOutBuiltinSet;
	defm vmsle : RVVSignedMaskOutBuiltinSet;			defm vmsle : RVVSignedMaskOutBuiltinSet;
	defm vmsgtu : RVVUnsignedMaskOutBuiltinSet;			defm vmsgtu : RVVUnsignedMaskOutBuiltinSet;
	defm vmsgt : RVVSignedMaskOutBuiltinSet;			defm vmsgt : RVVSignedMaskOutBuiltinSet;
	▲ Show 20 Lines • Show All 189 Lines • ▼ Show 20 Lines
	defm vfsgnj : RVVFloatingBinBuiltinSet;			defm vfsgnj : RVVFloatingBinBuiltinSet;
	defm vfsgnjn : RVVFloatingBinBuiltinSet;			defm vfsgnjn : RVVFloatingBinBuiltinSet;
	defm vfsgnjx : RVVFloatingBinBuiltinSet;			defm vfsgnjx : RVVFloatingBinBuiltinSet;
	}			}
	defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "xfd">;			defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "xfd">;
	defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "xfd">;			defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "xfd">;

	// 14.13. Vector Floating-Point Compare Instructions			// 14.13. Vector Floating-Point Compare Instructions
	let MaskedPolicyScheme = NonePolicy in {			let MaskedPolicyScheme = HasPassthruOperand,
				HasTailPolicy = false in {
	defm vmfeq : RVVFloatingMaskOutBuiltinSet;			defm vmfeq : RVVFloatingMaskOutBuiltinSet;
	defm vmfne : RVVFloatingMaskOutBuiltinSet;			defm vmfne : RVVFloatingMaskOutBuiltinSet;
	defm vmflt : RVVFloatingMaskOutBuiltinSet;			defm vmflt : RVVFloatingMaskOutBuiltinSet;
	defm vmfle : RVVFloatingMaskOutBuiltinSet;			defm vmfle : RVVFloatingMaskOutBuiltinSet;
	defm vmfgt : RVVFloatingMaskOutBuiltinSet;			defm vmfgt : RVVFloatingMaskOutBuiltinSet;
	defm vmfge : RVVFloatingMaskOutBuiltinSet;			defm vmfge : RVVFloatingMaskOutBuiltinSet;
	}			}

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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c

	Show First 20 Lines • Show All 355 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f64.f64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], double [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f64.f64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], double [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmfeq_vf_f64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,			vbool8_t test_vmfeq_vf_f64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,
	vfloat64m8_t op1, double op2, size_t vl) {			vfloat64m8_t op1, double op2, size_t vl) {
	return vmfeq(mask, maskedoff, op1, op2, vl);			return vmfeq(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmfeq_vv_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfeq_vv_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfeq_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfeq_vf_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfeq_vf_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfeq_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfeq_vv_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfeq_vv_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfeq_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfeq_vf_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfeq_vf_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfeq_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c

	Show First 20 Lines • Show All 323 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f64.f64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], double [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f64.f64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], double [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmfge_vf_f64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vfloat64m8_t op1, double op2, size_t vl) {			vbool8_t test_vmfge_vf_f64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vfloat64m8_t op1, double op2, size_t vl) {
	return vmfge(mask, maskedoff, op1, op2, vl);			return vmfge(mask, maskedoff, op1, op2, vl);
	}			}


				// CHECK-RV64-LABEL: @test_vmfge_vv_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfge_vv_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfge_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfge_vf_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfge_vf_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfge_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfge_vv_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfge_vv_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfge_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfge_vf_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfge_vf_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfge_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c

	Show First 20 Lines • Show All 323 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f64.f64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], double [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f64.f64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], double [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmfgt_vf_f64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vfloat64m8_t op1, double op2, size_t vl) {			vbool8_t test_vmfgt_vf_f64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vfloat64m8_t op1, double op2, size_t vl) {
	return vmfgt(mask, maskedoff, op1, op2, vl);			return vmfgt(mask, maskedoff, op1, op2, vl);
	}			}


				// CHECK-RV64-LABEL: @test_vmfgt_vv_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfgt_vv_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfgt_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfgt_vf_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfgt_vf_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfgt_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfgt_vv_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfgt_vv_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfgt_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfgt_vf_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfgt_vf_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfgt_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c

	Show First 20 Lines • Show All 355 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f64.f64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], double [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f64.f64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], double [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmfle_vf_f64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,			vbool8_t test_vmfle_vf_f64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,
	vfloat64m8_t op1, double op2, size_t vl) {			vfloat64m8_t op1, double op2, size_t vl) {
	return vmfle(mask, maskedoff, op1, op2, vl);			return vmfle(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmfle_vv_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfle_vv_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfle_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfle_vf_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfle_vf_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfle_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfle_vv_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfle_vv_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfle_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfle_vf_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfle_vf_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfle_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c

	Show First 20 Lines • Show All 355 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f64.f64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], double [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f64.f64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], double [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmflt_vf_f64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,			vbool8_t test_vmflt_vf_f64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,
	vfloat64m8_t op1, double op2, size_t vl) {			vfloat64m8_t op1, double op2, size_t vl) {
	return vmflt(mask, maskedoff, op1, op2, vl);			return vmflt(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmflt_vv_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmflt_vv_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmflt_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmflt_vf_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmflt_vf_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmflt_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmflt_vv_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmflt_vv_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmflt_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmflt_vf_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmflt_vf_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmflt_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c

	Show First 20 Lines • Show All 355 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f64.f64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], double [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f64.f64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], double [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmfne_vf_f64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,			vbool8_t test_vmfne_vf_f64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,
	vfloat64m8_t op1, double op2, size_t vl) {			vfloat64m8_t op1, double op2, size_t vl) {
	return vmfne(mask, maskedoff, op1, op2, vl);			return vmfne(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmfne_vv_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfne_vv_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfne_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfne_vf_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfne_vf_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfne_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfne_vv_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfne_vv_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfne_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfne_vf_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfne_vf_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfne_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c

	Show First 20 Lines • Show All 1,693 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmseq_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,			vbool8_t test_vmseq_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,
	vuint64m8_t op1, uint64_t op2, size_t vl) {			vuint64m8_t op1, uint64_t op2, size_t vl) {
	return vmseq(mask, maskedoff, op1, op2, vl);			return vmseq(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmseq_vv_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmseq_vv_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmseq_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmseq_vx_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmseq_vx_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmseq_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmseq_vv_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmseq_vv_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmseq_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmseq_vx_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmseq_vx_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmseq_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmseq_vv_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmseq_vv_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmseq_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmseq_vx_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmseq_vx_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmseq_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmseq_vv_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmseq_vv_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmseq_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmseq_vx_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmseq_vx_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmseq_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsge.c

	Show First 20 Lines • Show All 1,582 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmsgeu_vx_u64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) {			vbool8_t test_vmsgeu_vx_u64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) {
	return vmsgeu(mask, maskedoff, op1, op2, vl);			return vmsgeu(mask, maskedoff, op1, op2, vl);
	}			}


				// CHECK-RV64-LABEL: @test_vmsge_vv_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsge_vv_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmsge_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsge_vx_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsge_vx_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmsge_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgeu_vv_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgeu_vv_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsgeu_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgeu_vx_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgeu_vx_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsgeu_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsge_vv_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsge_vv_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmsge_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsge_vx_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsge_vx_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmsge_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgeu_vv_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgeu_vv_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsgeu_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgeu_vx_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgeu_vx_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsgeu_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c

	Show First 20 Lines • Show All 1,582 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmsgtu_vx_u64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) {			vbool8_t test_vmsgtu_vx_u64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) {
	return vmsgtu(mask, maskedoff, op1, op2, vl);			return vmsgtu(mask, maskedoff, op1, op2, vl);
	}			}


				// CHECK-RV64-LABEL: @test_vmsgt_vv_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgt_vv_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmsgt_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgt_vx_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgt_vx_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmsgt_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgtu_vv_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgtu_vv_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsgtu_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgtu_vx_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgtu_vx_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsgtu_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgt_vv_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgt_vv_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmsgt_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgt_vx_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgt_vx_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmsgt_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgtu_vv_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgtu_vv_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsgtu_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgtu_vx_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgtu_vx_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsgtu_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c

	Show First 20 Lines • Show All 1,708 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmsleu_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,			vbool8_t test_vmsleu_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,
	vuint64m8_t op1, uint64_t op2, size_t vl) {			vuint64m8_t op1, uint64_t op2, size_t vl) {
	return vmsleu(mask, maskedoff, op1, op2, vl);			return vmsleu(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmsle_vv_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsle_vv_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmsle_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsle_vx_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsle_vx_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmsle_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsleu_vv_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsleu_vv_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsleu_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsleu_vx_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsleu_vx_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsleu_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsle_vv_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsle_vv_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmsle_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsle_vx_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsle_vx_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmsle_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsleu_vv_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsleu_vv_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsleu_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsleu_vx_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsleu_vx_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsleu_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c

	Show First 20 Lines • Show All 1,708 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmsltu_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,			vbool8_t test_vmsltu_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,
	vuint64m8_t op1, uint64_t op2, size_t vl) {			vuint64m8_t op1, uint64_t op2, size_t vl) {
	return vmsltu(mask, maskedoff, op1, op2, vl);			return vmsltu(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmslt_vv_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmslt_vv_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmslt_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmslt_vx_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmslt_vx_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmslt_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsltu_vv_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsltu_vv_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsltu_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsltu_vx_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsltu_vx_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsltu_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmslt_vv_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmslt_vv_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmslt_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmslt_vx_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmslt_vx_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmslt_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsltu_vv_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsltu_vv_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsltu_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsltu_vx_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsltu_vx_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsltu_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c

	Show First 20 Lines • Show All 1,693 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmsne_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,			vbool8_t test_vmsne_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,
	vuint64m8_t op1, uint64_t op2, size_t vl) {			vuint64m8_t op1, uint64_t op2, size_t vl) {
	return vmsne(mask, maskedoff, op1, op2, vl);			return vmsne(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmsne_vv_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsne_vv_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmsne_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsne_vx_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsne_vx_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmsne_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsne_vv_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsne_vv_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsne_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsne_vx_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsne_vx_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsne_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsne_vv_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsne_vv_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmsne_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsne_vx_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsne_vx_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmsne_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsne_vv_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsne_vv_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsne_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsne_vx_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsne_vx_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsne_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c

	Show First 20 Lines • Show All 572 Lines • ▼ Show 20 Lines
	// CHECK-RV64-LABEL: @test_vmfeq_vf_f16m8_b2_m(			// CHECK-RV64-LABEL: @test_vmfeq_vf_f16m8_b2_m(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i1> @llvm.riscv.vmfeq.mask.nxv32f16.f16.i64(<vscale x 32 x i1> [[MASKEDOFF:%.]], <vscale x 32 x half> [[OP1:%.]], half [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i1> @llvm.riscv.vmfeq.mask.nxv32f16.f16.i64(<vscale x 32 x i1> [[MASKEDOFF:%.]], <vscale x 32 x half> [[OP1:%.]], half [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
	//			//
	vbool2_t test_vmfeq_vf_f16m8_b2_m (vbool2_t mask, vbool2_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {			vbool2_t test_vmfeq_vf_f16m8_b2_m (vbool2_t mask, vbool2_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {
	return vmfeq_vf_f16m8_b2_m(mask, maskedoff, op1, op2, vl);			return vmfeq_vf_f16m8_b2_m(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmfeq_vv_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfeq_vv_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfeq_vv_f32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfeq_vf_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfeq_vf_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfeq_vf_f32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfeq_vv_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfeq_vv_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfeq_vv_f32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfeq_vf_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfeq_vf_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfeq_vf_f32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c

	Show First 20 Lines • Show All 539 Lines • ▼ Show 20 Lines
	// CHECK-RV64-LABEL: @test_vmfge_vf_f16m8_b2_m(			// CHECK-RV64-LABEL: @test_vmfge_vf_f16m8_b2_m(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i1> @llvm.riscv.vmfge.mask.nxv32f16.f16.i64(<vscale x 32 x i1> [[MASKEDOFF:%.]], <vscale x 32 x half> [[OP1:%.]], half [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i1> @llvm.riscv.vmfge.mask.nxv32f16.f16.i64(<vscale x 32 x i1> [[MASKEDOFF:%.]], <vscale x 32 x half> [[OP1:%.]], half [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
	//			//
	vbool2_t test_vmfge_vf_f16m8_b2_m (vbool2_t mask, vbool2_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {			vbool2_t test_vmfge_vf_f16m8_b2_m (vbool2_t mask, vbool2_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {
	return vmfge_vf_f16m8_b2_m(mask, maskedoff, op1, op2, vl);			return vmfge_vf_f16m8_b2_m(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmfge_vv_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfge_vv_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfge_vv_f32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfge_vf_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfge_vf_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfge_vf_f32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfge_vv_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfge_vv_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfge_vv_f32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfge_vf_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfge_vf_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfge_vf_f32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c

	Show First 20 Lines • Show All 539 Lines • ▼ Show 20 Lines
	// CHECK-RV64-LABEL: @test_vmfgt_vf_f16m8_b2_m(			// CHECK-RV64-LABEL: @test_vmfgt_vf_f16m8_b2_m(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i1> @llvm.riscv.vmfgt.mask.nxv32f16.f16.i64(<vscale x 32 x i1> [[MASKEDOFF:%.]], <vscale x 32 x half> [[OP1:%.]], half [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i1> @llvm.riscv.vmfgt.mask.nxv32f16.f16.i64(<vscale x 32 x i1> [[MASKEDOFF:%.]], <vscale x 32 x half> [[OP1:%.]], half [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
	//			//
	vbool2_t test_vmfgt_vf_f16m8_b2_m (vbool2_t mask, vbool2_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {			vbool2_t test_vmfgt_vf_f16m8_b2_m (vbool2_t mask, vbool2_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {
	return vmfgt_vf_f16m8_b2_m(mask, maskedoff, op1, op2, vl);			return vmfgt_vf_f16m8_b2_m(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmfgt_vv_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfgt_vv_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfgt_vv_f32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfgt_vf_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfgt_vf_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfgt_vf_f32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfgt_vv_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfgt_vv_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfgt_vv_f32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfgt_vf_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfgt_vf_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfgt_vf_f32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c

	Show First 20 Lines • Show All 572 Lines • ▼ Show 20 Lines
	// CHECK-RV64-LABEL: @test_vmfle_vf_f16m8_b2_m(			// CHECK-RV64-LABEL: @test_vmfle_vf_f16m8_b2_m(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i1> @llvm.riscv.vmfle.mask.nxv32f16.f16.i64(<vscale x 32 x i1> [[MASKEDOFF:%.]], <vscale x 32 x half> [[OP1:%.]], half [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i1> @llvm.riscv.vmfle.mask.nxv32f16.f16.i64(<vscale x 32 x i1> [[MASKEDOFF:%.]], <vscale x 32 x half> [[OP1:%.]], half [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
	//			//
	vbool2_t test_vmfle_vf_f16m8_b2_m (vbool2_t mask, vbool2_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {			vbool2_t test_vmfle_vf_f16m8_b2_m (vbool2_t mask, vbool2_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {
	return vmfle_vf_f16m8_b2_m(mask, maskedoff, op1, op2, vl);			return vmfle_vf_f16m8_b2_m(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmfle_vv_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfle_vv_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfle_vv_f32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfle_vf_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfle_vf_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfle_vf_f32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfle_vv_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfle_vv_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfle_vv_f32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfle_vf_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfle_vf_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfle_vf_f32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c

	Show First 20 Lines • Show All 572 Lines • ▼ Show 20 Lines
	// CHECK-RV64-LABEL: @test_vmflt_vf_f16m8_b2_m(			// CHECK-RV64-LABEL: @test_vmflt_vf_f16m8_b2_m(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i1> @llvm.riscv.vmflt.mask.nxv32f16.f16.i64(<vscale x 32 x i1> [[MASKEDOFF:%.]], <vscale x 32 x half> [[OP1:%.]], half [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i1> @llvm.riscv.vmflt.mask.nxv32f16.f16.i64(<vscale x 32 x i1> [[MASKEDOFF:%.]], <vscale x 32 x half> [[OP1:%.]], half [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
	//			//
	vbool2_t test_vmflt_vf_f16m8_b2_m (vbool2_t mask, vbool2_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {			vbool2_t test_vmflt_vf_f16m8_b2_m (vbool2_t mask, vbool2_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {
	return vmflt_vf_f16m8_b2_m(mask, maskedoff, op1, op2, vl);			return vmflt_vf_f16m8_b2_m(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmflt_vv_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmflt_vv_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmflt_vv_f32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmflt_vf_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmflt_vf_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmflt_vf_f32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmflt_vv_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmflt_vv_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmflt_vv_f32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmflt_vf_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmflt_vf_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmflt_vf_f32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c

	Show First 20 Lines • Show All 572 Lines • ▼ Show 20 Lines
	// CHECK-RV64-LABEL: @test_vmfne_vf_f16m8_b2_m(			// CHECK-RV64-LABEL: @test_vmfne_vf_f16m8_b2_m(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i1> @llvm.riscv.vmfne.mask.nxv32f16.f16.i64(<vscale x 32 x i1> [[MASKEDOFF:%.]], <vscale x 32 x half> [[OP1:%.]], half [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i1> @llvm.riscv.vmfne.mask.nxv32f16.f16.i64(<vscale x 32 x i1> [[MASKEDOFF:%.]], <vscale x 32 x half> [[OP1:%.]], half [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
	//			//
	vbool2_t test_vmfne_vf_f16m8_b2_m (vbool2_t mask, vbool2_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {			vbool2_t test_vmfne_vf_f16m8_b2_m (vbool2_t mask, vbool2_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {
	return vmfne_vf_f16m8_b2_m(mask, maskedoff, op1, op2, vl);			return vmfne_vf_f16m8_b2_m(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmfne_vv_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfne_vv_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfne_vv_f32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfne_vf_f32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32.i64(<vscale x 1 x i1> undef, <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfne_vf_f32mf2_b64_ma (vbool64_t mask, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfne_vf_f32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfne_vv_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfne_vv_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
				return vmfne_vv_f32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmfne_vf_f32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmfne_vf_f32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vfloat32mf2_t op1, float op2, size_t vl) {
				return vmfne_vf_f32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c

	Show First 20 Lines • Show All 1,693 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmseq_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,			vbool8_t test_vmseq_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,
	vuint64m8_t op1, uint64_t op2, size_t vl) {			vuint64m8_t op1, uint64_t op2, size_t vl) {
	return vmseq_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl);			return vmseq_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmseq_vv_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmseq_vv_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmseq_vv_i32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmseq_vx_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmseq_vx_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmseq_vx_i32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmseq_vv_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmseq_vv_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmseq_vv_u32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmseq_vx_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmseq_vx_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmseq_vx_u32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmseq_vv_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmseq_vv_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmseq_vv_i32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmseq_vx_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmseq_vx_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmseq_vx_i32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmseq_vv_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmseq_vv_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmseq_vv_u32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmseq_vx_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmseq_vx_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmseq_vx_u32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vmsge.c

	Show First 20 Lines • Show All 1,582 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmsgeu_vx_u64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) {			vbool8_t test_vmsgeu_vx_u64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) {
	return vmsgeu_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl);			return vmsgeu_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl);
	}			}


				// CHECK-RV64-LABEL: @test_vmsge_vv_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsge_vv_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmsge_vv_i32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsge_vx_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsge_vx_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmsge_vx_i32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgeu_vv_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgeu_vv_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsgeu_vv_u32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgeu_vx_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgeu_vx_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsgeu_vx_u32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsge_vv_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsge_vv_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmsge_vv_i32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsge_vx_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsge_vx_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmsge_vx_i32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgeu_vv_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgeu_vv_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsgeu_vv_u32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgeu_vx_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgeu_vx_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsgeu_vx_u32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c

	Show First 20 Lines • Show All 1,582 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmsgtu_vx_u64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) {			vbool8_t test_vmsgtu_vx_u64m8_b8_m (vbool8_t mask, vbool8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) {
	return vmsgtu_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl);			return vmsgtu_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl);
	}			}


				// CHECK-RV64-LABEL: @test_vmsgt_vv_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgt_vv_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmsgt_vv_i32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgt_vx_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgt_vx_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmsgt_vx_i32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgtu_vv_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgtu_vv_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsgtu_vv_u32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgtu_vx_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgtu_vx_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsgtu_vx_u32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgt_vv_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgt_vv_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmsgt_vv_i32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgt_vx_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgt_vx_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmsgt_vx_i32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgtu_vv_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgtu_vv_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsgtu_vv_u32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsgtu_vx_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsgtu_vx_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsgtu_vx_u32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c

	Show First 20 Lines • Show All 1,708 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmsleu_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,			vbool8_t test_vmsleu_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,
	vuint64m8_t op1, uint64_t op2, size_t vl) {			vuint64m8_t op1, uint64_t op2, size_t vl) {
	return vmsleu_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl);			return vmsleu_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmsle_vv_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsle_vv_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmsle_vv_i32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsle_vx_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsle_vx_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmsle_vx_i32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsleu_vv_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsleu_vv_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsleu_vv_u32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsleu_vx_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsleu_vx_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsleu_vx_u32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsle_vv_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsle_vv_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmsle_vv_i32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsle_vx_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsle_vx_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmsle_vx_i32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsleu_vv_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsleu_vv_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsleu_vv_u32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsleu_vx_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsleu_vx_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsleu_vx_u32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c

	Show First 20 Lines • Show All 1,708 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmsltu_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,			vbool8_t test_vmsltu_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,
	vuint64m8_t op1, uint64_t op2, size_t vl) {			vuint64m8_t op1, uint64_t op2, size_t vl) {
	return vmsltu_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl);			return vmsltu_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmslt_vv_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmslt_vv_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmslt_vv_i32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmslt_vx_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmslt_vx_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmslt_vx_i32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsltu_vv_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsltu_vv_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsltu_vv_u32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsltu_vx_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsltu_vx_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsltu_vx_u32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmslt_vv_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmslt_vv_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmslt_vv_i32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmslt_vx_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmslt_vx_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmslt_vx_i32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsltu_vv_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsltu_vv_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsltu_vv_u32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsltu_vx_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsltu_vx_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsltu_vx_u32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c

	Show First 20 Lines • Show All 1,693 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
	//			//
	vbool8_t test_vmsne_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,			vbool8_t test_vmsne_vx_u64m8_b8_m(vbool8_t mask, vbool8_t maskedoff,
	vuint64m8_t op1, uint64_t op2, size_t vl) {			vuint64m8_t op1, uint64_t op2, size_t vl) {
	return vmsne_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl);			return vmsne_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vmsne_vv_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsne_vv_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmsne_vv_i32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsne_vx_i32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsne_vx_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmsne_vx_i32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsne_vv_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsne_vv_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsne_vv_u32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsne_vx_u32mf2_b64_ma(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32.i64(<vscale x 1 x i1> undef, <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsne_vx_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsne_vx_u32mf2_b64_ma(mask, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsne_vv_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsne_vv_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
				return vmsne_vv_i32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsne_vx_i32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsne_vx_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
				return vmsne_vx_i32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsne_vv_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsne_vv_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
				return vmsne_vv_u32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

				// CHECK-RV64-LABEL: @test_vmsne_vx_u32mf2_b64_mu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MERGE:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
				//
				vbool64_t test_vmsne_vx_u32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vuint32mf2_t op1, uint32_t op2, size_t vl) {
				return vmsne_vx_u32mf2_b64_mu(mask, merge, op1, op2, vl);
				}

This is an archive of the discontinued LLVM Phabricator instance.

[RISCV][Clang] Support policy functions for Vector Comparison Instructions.ClosedPublic

Details

Diff Detail

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Revision Contents

Diff 433264

clang/include/clang/Basic/riscv_vector.td

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsge.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmsge.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c

[RISCV][Clang] Support policy functions for Vector Comparison Instructions.
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