[WIP] Very early work to enable isel of fixed length vector extracts from scalable vectors.

[paulwalker-arm]

llvm/include/llvm/Target/TargetSelectionDAG.td

698

Created new variant because SDTSubVecExtract does not support missed datatypes. Changing SDTSubVecExtract causes LLVM not to build because many isel patterns need updating. Not 100% sure this is the way to go, just depends on how many isel patterns need to be changed.

[david-arm]

llvm/include/llvm/Target/TargetSelectionDAG.td

698

I imagine you'll need a new ISD enum too, i.e. ISD::EXTRACT_SUBVECTOR2 because otherwise it may alias with def extract_subvector?

[paulwalker-arm]

llvm/include/llvm/Target/TargetSelectionDAG.td

698

To be honest I think updating SDTSubVecExtract is the way to go, but if I do continue with the current route it shouldn't matter because the two definitions will have mutually exclusive type requirements [1] so a 1-1 mapping will be maintained.

[1] extract_subvector requires A.isScalable() == B.isScalable(), whereas the new def will require A.isScalable() != B.isScalable()

[Allen]

llvm/include/llvm/Target/TargetSelectionDAG.td

272

hi @paulwalker-arm:

I'm not familiar with the def, do you mean **SDTCisVec<0>** and **SDTCisInt<2>** have different type, so this is guard with **A.isScalable() != B.isScalable() **? thanks.

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

1425

hi, @paulwalker-arm:

do you still working on it, may be it need more pattern to match above commented pattten?

[paulwalker-arm]

llvm/include/llvm/Target/TargetSelectionDAG.td

272

Yes, specially <2> is the index to extract from which is a scalar integer.

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

1425

I've not done anything since this initial version. Especially since concluding we can probably use vector_extract_subvec. I can pick this up if you want. I'm kind of interested anyway as a way to remove the original support code from AArch64ISelDAGToDAG.cpp.

[Allen]

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

1425

That would be perfect. Thank you so much.

llvm/include/llvm/Target/TargetSelectionDAG.td

 
 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
   SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
 ]>;
 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert
   SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
 ]>;
 
+def SDTSubVecExtract2 : SDTypeProfile<1, 2, [// subvector extract
+    SDTCisVec<0>, SDTCisVec<1>, SDTCisInt<2>
+]>;
+
 def SDTPrefetch : SDTypeProfile<0, 4, [     // prefetch
   SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1>
 ]>;
 
 def SDTMemBarrier : SDTypeProfile<0, 5, [   // memory barrier
   SDTCisSameAs<0,1>,  SDTCisSameAs<0,2>,  SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
   SDTCisInt<0>
 ]>;

 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
     SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,
     []>;
 
 // This operator does subvector type checking.
 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
 
+// Extract/Insert fixed length subvector form scalable vector.
+def extract_subvector2 : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract2, []>;
+
 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
 // these internally.  Don't reference these directly.
 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
                             SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
                             [SDNPHasChain]>;
 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
                                SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
                                [SDNPHasChain]>;

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

case ISD::EXTRACT_SUBVECTOR: {
     if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue() != 0)
       break;
 
     // Bail when normal isel can do the job.
     EVT InVT = Node->getOperand(0).getValueType();
     if (VT.isScalableVector() || InVT.isFixedLengthVector())
       break;
 
+    // Bail when extracting from unpacked vector types.
+    if (InVT.isScalableVector() &&
+        InVT.getSizeInBits().getKnownMinValue() != AArch64::SVEBitsPerBlock)
+      break;
+
     // NOTE: We can only get here when doing fixed length SVE code generation.
     // We do manual selection because the types involved are not linked to real
     // registers (despite being legal) and must be coerced into SVE registers.
     //
     // NOTE: If the above changes, be aware that selection will still not work
     // because the td definition of extract_vector does not support extracting
     // a fixed length vector from a scalable vector.
 

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
   unsigned Size = Op.getValueSizeInBits();
 
   // If we don't have legal types yet, do nothing
   if (!DAG.getTargetLoweringInfo().isTypeLegal(InVT))
     return SDValue();
 
   if (InVT.isScalableVector()) {
     // This will be matched by custom code during ISelDAGToDAG.
-    if (Idx == 0 && isPackedVectorType(InVT, DAG))
+    if (Idx == 0)// && isPackedVectorType(InVT, DAG))
       return Op;
 
     return SDValue();
   }
 
   // This will get lowered to an appropriate EXTRACT_SUBREG in ISel.
   if (Idx == 0 && InVT.getSizeInBits() <= 128)
     return Op;

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
                              (v16i8 (REV32v16i8 FPR128:$src))>;
 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
                              (v16i8 (REV16v16i8 FPR128:$src))>;
 def : Pat<(v16i8 (bitconvert (v8bf16 FPR128:$src))),
                              (v16i8 (REV16v16i8 FPR128:$src))>;
 }
 
-def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 0))),
-           (EXTRACT_SUBREG V128:$Rn, dsub)>;
-def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 0))),
-           (EXTRACT_SUBREG V128:$Rn, dsub)>;
-def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 0))),
-           (EXTRACT_SUBREG V128:$Rn, dsub)>;
-def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 0))),
-           (EXTRACT_SUBREG V128:$Rn, dsub)>;
-def : Pat<(v4bf16 (extract_subvector V128:$Rn, (i64 0))),
-           (EXTRACT_SUBREG V128:$Rn, dsub)>;
-def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 0))),
-           (EXTRACT_SUBREG V128:$Rn, dsub)>;
-def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 0))),
-           (EXTRACT_SUBREG V128:$Rn, dsub)>;
-def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 0))),
-           (EXTRACT_SUBREG V128:$Rn, dsub)>;
+//def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 0))),
+//           (EXTRACT_SUBREG V128:$Rn, dsub)>;
+//def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 0))),
+//           (EXTRACT_SUBREG V128:$Rn, dsub)>;
+//def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 0))),
+//           (EXTRACT_SUBREG V128:$Rn, dsub)>;
+//def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 0))),
+//           (EXTRACT_SUBREG V128:$Rn, dsub)>;
+//def : Pat<(v4bf16 (extract_subvector V128:$Rn, (i64 0))),
+//           (EXTRACT_SUBREG V128:$Rn, dsub)>;
+//def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 0))),
+//           (EXTRACT_SUBREG V128:$Rn, dsub)>;
+//def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 0))),
+//           (EXTRACT_SUBREG V128:$Rn, dsub)>;
+//def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 0))),
+//           (EXTRACT_SUBREG V128:$Rn, dsub)>;
 
 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
           (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
           (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
           (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

def : Pat<(nxv2bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 0))),
             (UUNPKLO_ZZ_D (UUNPKLO_ZZ_S ZPR:$Zs))>;
   def : Pat<(nxv2bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 2))),
             (UUNPKHI_ZZ_D (UUNPKLO_ZZ_S ZPR:$Zs))>;
   def : Pat<(nxv2bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 4))),
             (UUNPKLO_ZZ_D (UUNPKHI_ZZ_S ZPR:$Zs))>;
   def : Pat<(nxv2bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 6))),
             (UUNPKHI_ZZ_D (UUNPKHI_ZZ_S ZPR:$Zs))>;
 
+  // Extract fixed length subvector from FP SVE vectors
+  def : Pat<(v2f32 (extract_subvector2 (nxv2f32 ZPR:$Zs), (i64 0))),
+            (XTNv2i32 (v2f64 (EXTRACT_SUBREG ZPR:$Zs, zsub)))>;
+
   // Concatenate two predicates.
   def : Pat<(nxv4i1 (concat_vectors nxv2i1:$p1, nxv2i1:$p2)),
             (UZP1_PPP_S $p1, $p2)>;
   def : Pat<(nxv8i1 (concat_vectors nxv4i1:$p1, nxv4i1:$p2)),
             (UZP1_PPP_H $p1, $p2)>;
   def : Pat<(nxv16i1 (concat_vectors nxv8i1:$p1, nxv8i1:$p2)),
             (UZP1_PPP_B $p1, $p2)>;