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[WIP] Very early work to enable isel of fixed length vector extracts from scalable vectors.
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Authored by paulwalker-arm on May 23 2022, 6:56 AM.
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paulwalker-arm created this revision.May 23 2022, 6:56 AM
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paulwalker-arm added inline comments.May 23 2022, 7:25 AM
llvm/include/llvm/Target/TargetSelectionDAG.td
698

Created new variant because SDTSubVecExtract does not support missed datatypes. Changing SDTSubVecExtract causes LLVM not to build because many isel patterns need updating. Not 100% sure this is the way to go, just depends on how many isel patterns need to be changed.

david-arm added inline comments.
llvm/include/llvm/Target/TargetSelectionDAG.td
698

I imagine you'll need a new ISD enum too, i.e. ISD::EXTRACT_SUBVECTOR2 because otherwise it may alias with def extract_subvector?

paulwalker-arm added inline comments.May 23 2022, 7:33 AM
llvm/include/llvm/Target/TargetSelectionDAG.td
698

To be honest I think updating SDTSubVecExtract is the way to go, but if I do continue with the current route it shouldn't matter because the two definitions will have mutually exclusive type requirements [1] so a 1-1 mapping will be maintained.

[1] extract_subvector requires A.isScalable() == B.isScalable(), whereas the new def will require A.isScalable() != B.isScalable()

Allen added a subscriber: Allen.May 24 2022, 3:41 AM
Matt added a subscriber: Matt.Jun 1 2022, 7:29 PM
Allen added inline comments.Jun 14 2022, 1:45 AM
llvm/include/llvm/Target/TargetSelectionDAG.td
272

hi @paulwalker-arm:

I'm not familiar with the def, do you mean **SDTCisVec<0>** and **SDTCisInt<2>** have different type, so this is guard with **A.isScalable() != B.isScalable() **? thanks.
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
1425

hi, @paulwalker-arm:

do you still working on it, may be it need more pattern to match above commented pattten?
paulwalker-arm added inline comments.Jun 20 2022, 8:32 AM
llvm/include/llvm/Target/TargetSelectionDAG.td
272

Yes, specially <2> is the index to extract from which is a scalar integer.

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
1425

I've not done anything since this initial version. Especially since concluding we can probably use vector_extract_subvec. I can pick this up if you want. I'm kind of interested anyway as a way to remove the original support code from AArch64ISelDAGToDAG.cpp.

Allen added inline comments.Jun 21 2022, 12:13 AM
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
1425

That would be perfect. Thank you so much.