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Differential D125238

[X86] Prefer MOVHLPS for shuffle(x,1,-1) extraction patterns (PR26515)
Changes PlannedPublic

Authored by RKSimon on May 9 2022, 8:23 AM.

Details

Reviewers
craig.topper
spatel
pengfei
sjarus
Summary

We currently lower to UNPCKH but that means the source vector must match the destination vector causing an additional move, which MOVHLPS can avoid.

Fixes #26889

Diff Detail

Event Timeline

RKSimon created this revision.May 9 2022, 8:23 AM
Herald added a reviewer: sjarus. · View Herald TranscriptMay 9 2022, 8:23 AM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: armkevincheng, eric-k256, StephenFan, hiraditya. · View Herald Transcript
RKSimon requested review of this revision.May 9 2022, 8:23 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 9 2022, 8:23 AM
Harbormaster completed remote builds in B163492: Diff 428094.May 9 2022, 9:14 AM
craig.topper added a comment.May 9 2022, 9:15 AM

Are you planning to do anything about the false dependency? I don't think we'll pick a "long dead" register as the original bug report suggested.

RKSimon added a comment.May 9 2022, 9:29 AM

Any suggestions?

RKSimon added a comment.May 9 2022, 9:36 AM

I'll see if we can improve hasUndefRegUpdate

RKSimon updated this revision to Diff 428119.May 9 2022, 10:07 AM

Add hasUndefRegUpdate handling

RKSimon added inline comments.May 9 2022, 10:10 AM
llvm/test/CodeGen/X86/vector-reduce-fadd.ll
54

TBH I'm not convinced any of these need dependency breaks.

craig.topper added inline comments.May 9 2022, 10:39 AM
llvm/test/CodeGen/X86/vector-reduce-fadd.ll
54

Will it always insert a dependency break because it can't rewrite the tied dest?

Harbormaster completed remote builds in B163510: Diff 428119.May 9 2022, 11:48 AM
RKSimon planned changes to this revision.Jun 12 2022, 5:22 AM
Herald added a subscriber: jsji. · View Herald TranscriptJun 12 2022, 5:22 AM
RKSimon updated this revision to Diff 448869.Jul 31 2022, 9:56 AM

rebase - isTargetShuffleEquivalent doesn't allow undef target shuffle elements anymore

Harbormaster completed remote builds in B178461: Diff 448869.Jul 31 2022, 10:34 AM
RKSimon updated this revision to Diff 448874.Jul 31 2022, 11:20 AM

hasUndefRegUpdate - handle dependencies in ether operand

Harbormaster completed remote builds in B178466: Diff 448874.Jul 31 2022, 12:09 PM
RKSimon planned changes to this revision.Nov 3 2022, 5:45 AM

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Diff 428119

llvm/lib/Target/X86/X86ISelLowering.cpp

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if (MaskVT.is128BitVector()) { if (MaskVT.is128BitVector()) {
if (isTargetShuffleEquivalent(MaskVT, Mask, {0, 0}) && AllowFloatDomain) { if (isTargetShuffleEquivalent(MaskVT, Mask, {0, 0}) && AllowFloatDomain) {
V2 = V1; V2 = V1;
V1 = (SM_SentinelUndef == Mask[0] ? DAG.getUNDEF(MVT::v4f32) : V1); V1 = (SM_SentinelUndef == Mask[0] ? DAG.getUNDEF(MVT::v4f32) : V1);
Shuffle = Subtarget.hasSSE2() ? X86ISD::UNPCKL : X86ISD::MOVLHPS; Shuffle = Subtarget.hasSSE2() ? X86ISD::UNPCKL : X86ISD::MOVLHPS;
SrcVT = DstVT = Subtarget.hasSSE2() ? MVT::v2f64 : MVT::v4f32; SrcVT = DstVT = Subtarget.hasSSE2() ? MVT::v2f64 : MVT::v4f32;
return true; return true;
} }
if (isTargetShuffleEquivalent(MaskVT, Mask, {1, -1}) && AllowFloatDomain) {
V2 = V1;
V1 = DAG.getUNDEF(MVT::v4f32);
Shuffle = X86ISD::MOVHLPS;
SrcVT = DstVT = MVT::v4f32;
return true;
}
if (isTargetShuffleEquivalent(MaskVT, Mask, {1, 1}) && AllowFloatDomain) { if (isTargetShuffleEquivalent(MaskVT, Mask, {1, 1}) && AllowFloatDomain) {
V2 = V1; V2 = V1;
Shuffle = Subtarget.hasSSE2() ? X86ISD::UNPCKH : X86ISD::MOVHLPS; Shuffle = Subtarget.hasSSE2() ? X86ISD::UNPCKH : X86ISD::MOVHLPS;
SrcVT = DstVT = Subtarget.hasSSE2() ? MVT::v2f64 : MVT::v4f32; SrcVT = DstVT = Subtarget.hasSSE2() ? MVT::v2f64 : MVT::v4f32;
return true; return true;
} }
if (isTargetShuffleEquivalent(MaskVT, Mask, {0, 3}) && if (isTargetShuffleEquivalent(MaskVT, Mask, {0, 3}) &&
Subtarget.hasSSE2() && (AllowFloatDomain || !Subtarget.hasSSE41())) { Subtarget.hasSSE2() && (AllowFloatDomain || !Subtarget.hasSSE41())) {
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llvm/lib/Target/X86/X86InstrInfo.cpp

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Show First 20 Lines • Show All 5,270 Lines • ▼ Show 20 Linesstatic bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
// Set the OpNum parameter to the first source operand. // Set the OpNum parameter to the first source operand.
switch (Opcode) { switch (Opcode) {
case X86::MMX_PUNPCKHBWrr: case X86::MMX_PUNPCKHBWrr:
case X86::MMX_PUNPCKHWDrr: case X86::MMX_PUNPCKHWDrr:
case X86::MMX_PUNPCKHDQrr: case X86::MMX_PUNPCKHDQrr:
case X86::MMX_PUNPCKLBWrr: case X86::MMX_PUNPCKLBWrr:
case X86::MMX_PUNPCKLWDrr: case X86::MMX_PUNPCKLWDrr:
case X86::MMX_PUNPCKLDQrr: case X86::MMX_PUNPCKLDQrr:
case X86::MOVHLPSrr:
case X86::PACKSSWBrr: case X86::PACKSSWBrr:
case X86::PACKUSWBrr: case X86::PACKUSWBrr:
case X86::PACKSSDWrr: case X86::PACKSSDWrr:
case X86::PACKUSDWrr: case X86::PACKUSDWrr:
case X86::PUNPCKHBWrr: case X86::PUNPCKHBWrr:
case X86::PUNPCKLBWrr: case X86::PUNPCKLBWrr:
case X86::PUNPCKHWDrr: case X86::PUNPCKHWDrr:
case X86::PUNPCKLWDrr: case X86::PUNPCKLWDrr:
case X86::PUNPCKHDQrr: case X86::PUNPCKHDQrr:
case X86::PUNPCKLDQrr: case X86::PUNPCKLDQrr:
case X86::PUNPCKHQDQrr: case X86::PUNPCKHQDQrr:
case X86::PUNPCKLQDQrr: case X86::PUNPCKLQDQrr:
case X86::SHUFPDrri: case X86::SHUFPDrri:
case X86::SHUFPSrri: case X86::SHUFPSrri:
// These instructions are sometimes used with an undef first or second // These instructions are sometimes used with an undef first or second
// source. Return true here so BreakFalseDeps will assign this source to the // source. Return true here so BreakFalseDeps will assign this source to the
// same register as the first source to avoid a false dependency. // same register as the first source to avoid a false dependency.
// Operand 1 of these instructions is tied so they're separate from their // Operand 1 of these instructions is tied so they're separate from their
// VEX counterparts. // VEX counterparts.
return OpNum == 2 && !ForLoadFold; return OpNum == 2 && !ForLoadFold;
// MOVHLPSrr is used as a fake move of the upper 64-bits of the second
// source into the lower 64-bits of the destination. So the first source is
// often set to undef.
case X86::MOVHLPSrr:
return OpNum == 1;
case X86::VMOVLHPSrr: case X86::VMOVLHPSrr:
case X86::VMOVLHPSZrr: case X86::VMOVLHPSZrr:
case X86::VPACKSSWBrr: case X86::VPACKSSWBrr:
case X86::VPACKUSWBrr: case X86::VPACKUSWBrr:
case X86::VPACKSSDWrr: case X86::VPACKSSDWrr:
case X86::VPACKUSDWrr: case X86::VPACKUSDWrr:
case X86::VPACKSSWBZ128rr: case X86::VPACKSSWBZ128rr:
case X86::VPACKUSWBZ128rr: case X86::VPACKUSWBZ128rr:
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llvm/lib/Target/X86/X86InstrSSE.td

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} }
let Predicates = [UseSSE2] in { let Predicates = [UseSSE2] in {
// MOVHPD patterns // MOVHPD patterns
def : Pat<(v2f64 (X86Unpckl VR128:$src1, (X86vzload64 addr:$src2))), def : Pat<(v2f64 (X86Unpckl VR128:$src1, (X86vzload64 addr:$src2))),
(MOVHPDrm VR128:$src1, addr:$src2)>; (MOVHPDrm VR128:$src1, addr:$src2)>;
def : Pat<(store (f64 (extractelt def : Pat<(store (f64 (extractelt
(v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))), (bc_v2f64 (v4f32 (X86Movhlps undef, VR128:$src))),
(iPTR 0))), addr:$dst), (iPTR 0))), addr:$dst),
(MOVHPDmr addr:$dst, VR128:$src)>; (MOVHPDmr addr:$dst, VR128:$src)>;
// MOVLPD patterns // MOVLPD patterns
def : Pat<(v2f64 (X86Movsd VR128:$src1, (X86vzload64 addr:$src2))), def : Pat<(v2f64 (X86Movsd VR128:$src1, (X86vzload64 addr:$src2))),
(MOVLPDrm VR128:$src1, addr:$src2)>; (MOVLPDrm VR128:$src1, addr:$src2)>;
} }
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llvm/test/CodeGen/X86/cast-vsel.ll

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; ;
; SSE41-LABEL: fpext: ; SSE41-LABEL: fpext:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: cmpltpd %xmm3, %xmm1 ; SSE41-NEXT: cmpltpd %xmm3, %xmm1
; SSE41-NEXT: cmpltpd %xmm2, %xmm0 ; SSE41-NEXT: cmpltpd %xmm2, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm5 ; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm5
; SSE41-NEXT: cvtps2pd %xmm5, %xmm0 ; SSE41-NEXT: cvtps2pd %xmm5, %xmm0
; SSE41-NEXT: movhlps {{.*#+}} xmm5 = xmm5[1,1] ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: cvtps2pd %xmm5, %xmm1 ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm5[1],xmm1[1]
; SSE41-NEXT: cvtps2pd %xmm1, %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: fpext: ; AVX-LABEL: fpext:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vcmpltpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vcmpltpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vcvtps2pd %xmm2, %ymm1 ; AVX-NEXT: vcvtps2pd %xmm2, %ymm1
; AVX-NEXT: vcvtps2pd %xmm3, %ymm2 ; AVX-NEXT: vcvtps2pd %xmm3, %ymm2
; AVX-NEXT: vblendvpd %ymm0, %ymm1, %ymm2, %ymm0 ; AVX-NEXT: vblendvpd %ymm0, %ymm1, %ymm2, %ymm0
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llvm/test/CodeGen/X86/combine-fcopysign.ll

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%2 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> %1) %2 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> %1)
ret <4 x float> %2 ret <4 x float> %2
} }
; copysign(x, fp_extend(y)) -> copysign(x, y) ; copysign(x, fp_extend(y)) -> copysign(x, y)
define <4 x double> @combine_vec_fcopysign_fpext_sgn(<4 x double> %x, <4 x float> %y) { define <4 x double> @combine_vec_fcopysign_fpext_sgn(<4 x double> %x, <4 x float> %y) {
; SSE-LABEL: combine_vec_fcopysign_fpext_sgn: ; SSE-LABEL: combine_vec_fcopysign_fpext_sgn:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: cvtps2pd %xmm2, %xmm3 ; SSE-NEXT: movhlps {{.*#+}} xmm3 = xmm2[1],xmm3[1]
; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: cvtps2pd %xmm3, %xmm3
; SSE-NEXT: cvtps2pd %xmm2, %xmm2 ; SSE-NEXT: cvtps2pd %xmm2, %xmm2
; SSE-NEXT: movaps {{.*#+}} xmm4 = [NaN,NaN] ; SSE-NEXT: movaps {{.*#+}} xmm4 = [NaN,NaN]
; SSE-NEXT: andps %xmm4, %xmm0 ; SSE-NEXT: andps %xmm4, %xmm0
; SSE-NEXT: movaps %xmm4, %xmm5 ; SSE-NEXT: movaps %xmm4, %xmm5
; SSE-NEXT: andnps %xmm3, %xmm5 ; SSE-NEXT: andnps %xmm2, %xmm5
; SSE-NEXT: orps %xmm5, %xmm0 ; SSE-NEXT: orps %xmm5, %xmm0
; SSE-NEXT: andps %xmm4, %xmm1 ; SSE-NEXT: andps %xmm4, %xmm1
; SSE-NEXT: andnps %xmm2, %xmm4 ; SSE-NEXT: andnps %xmm3, %xmm4
; SSE-NEXT: orps %xmm4, %xmm1 ; SSE-NEXT: orps %xmm4, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: combine_vec_fcopysign_fpext_sgn: ; AVX-LABEL: combine_vec_fcopysign_fpext_sgn:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vcvtps2pd %xmm1, %ymm1 ; AVX-NEXT: vcvtps2pd %xmm1, %ymm1
; AVX-NEXT: vbroadcastsd {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN] ; AVX-NEXT: vbroadcastsd {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN]
; AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 ; AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
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llvm/test/CodeGen/X86/complex-fastmath.ll

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%9 = insertelement <2 x float> undef, float %8, i32 0 %9 = insertelement <2 x float> undef, float %8, i32 0
%10 = insertelement <2 x float> %9, float %5, i32 1 %10 = insertelement <2 x float> %9, float %5, i32 1
ret <2 x float> %10 ret <2 x float> %10
} }
define <2 x double> @complex_square_f64(<2 x double>) #0 { define <2 x double> @complex_square_f64(<2 x double>) #0 {
; SSE-LABEL: complex_square_f64: ; SSE-LABEL: complex_square_f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: movapd %xmm0, %xmm2
; SSE-NEXT: addsd %xmm0, %xmm2 ; SSE-NEXT: addsd %xmm0, %xmm2
; SSE-NEXT: mulsd %xmm1, %xmm2 ; SSE-NEXT: mulsd %xmm1, %xmm2
; SSE-NEXT: mulsd %xmm0, %xmm0 ; SSE-NEXT: mulsd %xmm0, %xmm0
; SSE-NEXT: mulsd %xmm1, %xmm1 ; SSE-NEXT: mulsd %xmm1, %xmm1
; SSE-NEXT: subsd %xmm1, %xmm0 ; SSE-NEXT: subsd %xmm1, %xmm0
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
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%13 = insertelement <2 x float> undef, float %12, i32 0 %13 = insertelement <2 x float> undef, float %12, i32 0
%14 = insertelement <2 x float> %13, float %9, i32 1 %14 = insertelement <2 x float> %13, float %9, i32 1
ret <2 x float> %14 ret <2 x float> %14
} }
define <2 x double> @complex_mul_f64(<2 x double>, <2 x double>) #0 { define <2 x double> @complex_mul_f64(<2 x double>, <2 x double>) #0 {
; SSE-LABEL: complex_mul_f64: ; SSE-LABEL: complex_mul_f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm2 ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm3 = xmm1[1],xmm3[1]
; SSE-NEXT: movapd %xmm1, %xmm3 ; SSE-NEXT: movaps %xmm3, %xmm4
; SSE-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm1[1]
; SSE-NEXT: movapd %xmm3, %xmm4
; SSE-NEXT: mulsd %xmm0, %xmm4 ; SSE-NEXT: mulsd %xmm0, %xmm4
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: mulsd %xmm2, %xmm1 ; SSE-NEXT: mulsd %xmm2, %xmm1
; SSE-NEXT: addsd %xmm4, %xmm1 ; SSE-NEXT: addsd %xmm4, %xmm1
; SSE-NEXT: mulsd %xmm2, %xmm3 ; SSE-NEXT: mulsd %xmm2, %xmm3
; SSE-NEXT: subsd %xmm3, %xmm0 ; SSE-NEXT: subsd %xmm3, %xmm0
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: retq ; SSE-NEXT: retq
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llvm/test/CodeGen/X86/extractelement-load.ll

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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE2-NEXT: movaps 16(%ecx), %xmm0 ; X32-SSE2-NEXT: movaps 16(%ecx), %xmm0
; X32-SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; X32-SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; X32-SSE2-NEXT: xorps %xmm1, %xmm1 ; X32-SSE2-NEXT: xorps %xmm1, %xmm1
; X32-SSE2-NEXT: cmpltss %xmm0, %xmm1 ; X32-SSE2-NEXT: cmpltss %xmm0, %xmm1
; X32-SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; X32-SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; X32-SSE2-NEXT: andps %xmm1, %xmm2 ; X32-SSE2-NEXT: andps %xmm1, %xmm2
; X32-SSE2-NEXT: andnps %xmm0, %xmm1 ; X32-SSE2-NEXT: andnps %xmm0, %xmm1
; X32-SSE2-NEXT: orps %xmm2, %xmm1 ; X32-SSE2-NEXT: orps %xmm1, %xmm2
; X32-SSE2-NEXT: movss %xmm1, (%eax) ; X32-SSE2-NEXT: movss %xmm2, (%eax)
; X32-SSE2-NEXT: retl ; X32-SSE2-NEXT: retl
; ;
; X64-SSSE3-LABEL: PR43971: ; X64-SSSE3-LABEL: PR43971:
; X64-SSSE3: # %bb.0: # %entry ; X64-SSSE3: # %bb.0: # %entry
; X64-SSSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X64-SSSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSSE3-NEXT: xorps %xmm1, %xmm1 ; X64-SSSE3-NEXT: xorps %xmm1, %xmm1
; X64-SSSE3-NEXT: cmpltss %xmm0, %xmm1 ; X64-SSSE3-NEXT: cmpltss %xmm0, %xmm1
; X64-SSSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; X64-SSSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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llvm/test/CodeGen/X86/fma.ll

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; FMA64-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x71,0xa8,0xc2] ; FMA64-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x71,0xa8,0xc2]
; FMA64-NEXT: ## xmm0 = (xmm1 * xmm0) + xmm2 ; FMA64-NEXT: ## xmm0 = (xmm1 * xmm0) + xmm2
; FMA64-NEXT: retq ## encoding: [0xc3] ; FMA64-NEXT: retq ## encoding: [0xc3]
; ;
; FMACALL64-LABEL: test_v4f32: ; FMACALL64-LABEL: test_v4f32:
; FMACALL64: ## %bb.0: ## %entry ; FMACALL64: ## %bb.0: ## %entry
; FMACALL64-NEXT: subq $88, %rsp ## encoding: [0x48,0x83,0xec,0x58] ; FMACALL64-NEXT: subq $88, %rsp ## encoding: [0x48,0x83,0xec,0x58]
; FMACALL64-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x54,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x54,0x24,0x20]
; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x10]
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x20]
; FMACALL64-NEXT: shufps $255, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0xff]
; FMACALL64-NEXT: ## xmm0 = xmm0[3,3,3,3]
; FMACALL64-NEXT: shufps $255, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0xff]
; FMACALL64-NEXT: ## xmm1 = xmm1[3,3,3,3]
; FMACALL64-NEXT: shufps $255, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0xff]
; FMACALL64-NEXT: ## xmm2 = xmm2[3,3,3,3]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x04,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x04,0x24]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x20]
; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0] ; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10]
; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9] ; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x30]
; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2] ; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: unpcklps (%rsp), %xmm0 ## 16-byte Folded Reload ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x14,0x04,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x30]
; FMACALL64-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; FMACALL64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x04,0x24]
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x04,0x24] ; FMACALL64-NEXT: shufps $255, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0xff]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: ## xmm0 = xmm0[3,3,3,3]
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x20]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10]
; FMACALL64-NEXT: shufps $255, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0xff]
; FMACALL64-NEXT: ## xmm1 = xmm1[3,3,3,3]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x20]
; FMACALL64-NEXT: shufps $255, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0xff]
; FMACALL64-NEXT: ## xmm2 = xmm2[3,3,3,3]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30]
; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x30]
; FMACALL64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x04,0x24]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x20]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x40]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x04,0x24]
; FMACALL64-NEXT: shufps $85, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0x55] ; FMACALL64-NEXT: shufps $85, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0x55]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1,1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1,1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10]
; FMACALL64-NEXT: shufps $85, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0x55] ; FMACALL64-NEXT: shufps $85, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0x55]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1,1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1,1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x20]
; FMACALL64-NEXT: shufps $85, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0x55] ; FMACALL64-NEXT: shufps $85, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0x55]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1,1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1,1,1]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x40]
; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8] ; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; FMACALL64-NEXT: unpcklpd (%rsp), %xmm1 ## 16-byte Folded Reload ; FMACALL64-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload
; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x0c,0x24] ; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x4c,0x24,0x30]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],mem[0] ; FMACALL64-NEXT: ## xmm1 = xmm1[0],mem[0]
; FMACALL64-NEXT: movaps %xmm1, %xmm0 ## encoding: [0x0f,0x28,0xc1] ; FMACALL64-NEXT: movaps %xmm1, %xmm0 ## encoding: [0x0f,0x28,0xc1]
; FMACALL64-NEXT: addq $88, %rsp ## encoding: [0x48,0x83,0xc4,0x58] ; FMACALL64-NEXT: addq $88, %rsp ## encoding: [0x48,0x83,0xc4,0x58]
; FMACALL64-NEXT: retq ## encoding: [0xc3] ; FMACALL64-NEXT: retq ## encoding: [0xc3]
; ;
; AVX512-LABEL: test_v4f32: ; AVX512-LABEL: test_v4f32:
; AVX512: ## %bb.0: ## %entry ; AVX512: ## %bb.0: ## %entry
; AVX512-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x71,0xa8,0xc2] ; AVX512-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x71,0xa8,0xc2]
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; FMA64-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0xa8,0xc2] ; FMA64-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0xa8,0xc2]
; FMA64-NEXT: ## ymm0 = (ymm1 * ymm0) + ymm2 ; FMA64-NEXT: ## ymm0 = (ymm1 * ymm0) + ymm2
; FMA64-NEXT: retq ## encoding: [0xc3] ; FMA64-NEXT: retq ## encoding: [0xc3]
; ;
; FMACALL64-LABEL: test_v8f32: ; FMACALL64-LABEL: test_v8f32:
; FMACALL64: ## %bb.0: ## %entry ; FMACALL64: ## %bb.0: ## %entry
; FMACALL64-NEXT: subq $136, %rsp ## encoding: [0x48,0x81,0xec,0x88,0x00,0x00,0x00] ; FMACALL64-NEXT: subq $136, %rsp ## encoding: [0x48,0x81,0xec,0x88,0x00,0x00,0x00]
; FMACALL64-NEXT: movaps %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x6c,0x24,0x50] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x6c,0x24,0x40]
; FMACALL64-NEXT: movaps %xmm4, (%rsp) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x24,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x64,0x24,0x10]
; FMACALL64-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x5c,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x5c,0x24,0x30]
; FMACALL64-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x54,0x24,0x60] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x54,0x24,0x60]
; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x20]
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x50]
; FMACALL64-NEXT: shufps $255, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0xff] ; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0]
; FMACALL64-NEXT: ## xmm0 = xmm0[3,3,3,3] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1]
; FMACALL64-NEXT: movaps %xmm2, %xmm1 ## encoding: [0x0f,0x28,0xca] ; FMACALL64-NEXT: xorps %xmm1, %xmm1 ## encoding: [0x0f,0x57,0xc9]
; FMACALL64-NEXT: shufps $255, %xmm2, %xmm1 ## encoding: [0x0f,0xc6,0xca,0xff] ; FMACALL64-NEXT: movhlps %xmm2, %xmm1 ## encoding: [0x0f,0x12,0xca]
; FMACALL64-NEXT: ## xmm1 = xmm1[3,3],xmm2[3,3] ; FMACALL64-NEXT: ## xmm1 = xmm2[1],xmm1[1]
; FMACALL64-NEXT: movaps %xmm4, %xmm2 ## encoding: [0x0f,0x28,0xd4] ; FMACALL64-NEXT: xorps %xmm2, %xmm2 ## encoding: [0x0f,0x57,0xd2]
; FMACALL64-NEXT: shufps $255, %xmm4, %xmm2 ## encoding: [0x0f,0xc6,0xd4,0xff] ; FMACALL64-NEXT: movhlps %xmm4, %xmm2 ## encoding: [0x0f,0x12,0xd4]
; FMACALL64-NEXT: ## xmm2 = xmm2[3,3],xmm4[3,3] ; FMACALL64-NEXT: ## xmm2 = xmm4[1],xmm2[1]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x04,0x24]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x50]
; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0] ; FMACALL64-NEXT: shufps $255, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0xff]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[3,3,3,3]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x60] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x60]
; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9] ; FMACALL64-NEXT: shufps $255, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0xff]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[3,3,3,3]
; FMACALL64-NEXT: movaps (%rsp), %xmm2 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x14,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x10]
; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2] ; FMACALL64-NEXT: shufps $255, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0xff]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[3,3,3,3]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload ; FMACALL64-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x14,0x44,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x0c,0x24]
; FMACALL64-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8]
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x70] ; FMACALL64-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x0c,0x24]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x50]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x60] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x60]
; FMACALL64-NEXT: movaps (%rsp), %xmm2 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x14,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x10]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x70]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x50]
; FMACALL64-NEXT: shufps $85, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0x55] ; FMACALL64-NEXT: shufps $85, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0x55]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1,1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1,1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x60] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x60]
; FMACALL64-NEXT: shufps $85, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0x55] ; FMACALL64-NEXT: shufps $85, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0x55]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1,1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1,1,1]
; FMACALL64-NEXT: movaps (%rsp), %xmm2 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x14,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x10]
; FMACALL64-NEXT: shufps $85, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0x55] ; FMACALL64-NEXT: shufps $85, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0x55]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1,1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1,1,1]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x70]
; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8] ; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; FMACALL64-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload ; FMACALL64-NEXT: unpcklpd (%rsp), %xmm1 ## 16-byte Folded Reload
; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x4c,0x24,0x70] ; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x0c,0x24]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],mem[0] ; FMACALL64-NEXT: ## xmm1 = xmm1[0],mem[0]
; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x70]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x30]
; FMACALL64-NEXT: shufps $255, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0xff]
; FMACALL64-NEXT: ## xmm0 = xmm0[3,3,3,3]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x40]
; FMACALL64-NEXT: shufps $255, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0xff]
; FMACALL64-NEXT: ## xmm1 = xmm1[3,3,3,3]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x50]
; FMACALL64-NEXT: shufps $255, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0xff]
; FMACALL64-NEXT: ## xmm2 = xmm2[3,3,3,3]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x04,0x24]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x20]
; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0] ; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30]
; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9] ; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x50] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x40]
; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2] ; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: unpcklps (%rsp), %xmm0 ## 16-byte Folded Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x14,0x04,0x24]
; FMACALL64-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; FMACALL64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x04,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x04,0x24]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x20]
; FMACALL64-NEXT: shufps $255, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0xff]
; FMACALL64-NEXT: ## xmm0 = xmm0[3,3,3,3]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30]
; FMACALL64-NEXT: shufps $255, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0xff]
; FMACALL64-NEXT: ## xmm1 = xmm1[3,3,3,3]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x40]
; FMACALL64-NEXT: shufps $255, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0xff]
; FMACALL64-NEXT: ## xmm2 = xmm2[3,3,3,3]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x0c,0x24]
; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; FMACALL64-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x0c,0x24]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x20]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x50] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x40]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x10]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x20]
; FMACALL64-NEXT: shufps $85, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0x55] ; FMACALL64-NEXT: shufps $85, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0x55]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1,1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1,1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30]
; FMACALL64-NEXT: shufps $85, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0x55] ; FMACALL64-NEXT: shufps $85, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0x55]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1,1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1,1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x50] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x40]
; FMACALL64-NEXT: shufps $85, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0x55] ; FMACALL64-NEXT: shufps $85, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0x55]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1,1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1,1,1]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10]
; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8] ; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; FMACALL64-NEXT: unpcklpd (%rsp), %xmm1 ## 16-byte Folded Reload ; FMACALL64-NEXT: unpcklpd (%rsp), %xmm1 ## 16-byte Folded Reload
; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x0c,0x24] ; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x0c,0x24]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],mem[0] ; FMACALL64-NEXT: ## xmm1 = xmm1[0],mem[0]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x70]
; FMACALL64-NEXT: addq $136, %rsp ## encoding: [0x48,0x81,0xc4,0x88,0x00,0x00,0x00] ; FMACALL64-NEXT: addq $136, %rsp ## encoding: [0x48,0x81,0xc4,0x88,0x00,0x00,0x00]
; FMACALL64-NEXT: retq ## encoding: [0xc3] ; FMACALL64-NEXT: retq ## encoding: [0xc3]
; ;
; AVX512-LABEL: test_v8f32: ; AVX512-LABEL: test_v8f32:
; AVX512: ## %bb.0: ## %entry ; AVX512: ## %bb.0: ## %entry
; AVX512-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0xa8,0xc2] ; AVX512-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0xa8,0xc2]
; AVX512-NEXT: ## ymm0 = (ymm1 * ymm0) + ymm2 ; AVX512-NEXT: ## ymm0 = (ymm1 * ymm0) + ymm2
; AVX512-NEXT: retq ## encoding: [0xc3] ; AVX512-NEXT: retq ## encoding: [0xc3]
▲ Show 20 Lines • Show All 189 Lines • ▼ Show 20 Lines
; FMA64-NEXT: vfmadd213ps %ymm5, %ymm3, %ymm1 ## encoding: [0xc4,0xe2,0x65,0xa8,0xcd] ; FMA64-NEXT: vfmadd213ps %ymm5, %ymm3, %ymm1 ## encoding: [0xc4,0xe2,0x65,0xa8,0xcd]
; FMA64-NEXT: ## ymm1 = (ymm3 * ymm1) + ymm5 ; FMA64-NEXT: ## ymm1 = (ymm3 * ymm1) + ymm5
; FMA64-NEXT: retq ## encoding: [0xc3] ; FMA64-NEXT: retq ## encoding: [0xc3]
; ;
; FMACALL64-LABEL: test_v16f32: ; FMACALL64-LABEL: test_v16f32:
; FMACALL64: ## %bb.0: ## %entry ; FMACALL64: ## %bb.0: ## %entry
; FMACALL64-NEXT: subq $168, %rsp ## encoding: [0x48,0x81,0xec,0xa8,0x00,0x00,0x00] ; FMACALL64-NEXT: subq $168, %rsp ## encoding: [0x48,0x81,0xec,0xa8,0x00,0x00,0x00]
; FMACALL64-NEXT: movaps %xmm7, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm7, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0xbc,0x24,0x80,0x00,0x00,0x00] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x7c,0x24,0x70]
; FMACALL64-NEXT: movaps %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x74,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x74,0x24,0x20]
; FMACALL64-NEXT: movaps %xmm5, (%rsp) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x2c,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x6c,0x24,0x10]
; FMACALL64-NEXT: movaps %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x64,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x64,0x24,0x30]
; FMACALL64-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x5c,0x24,0x70] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x5c,0x24,0x60]
; FMACALL64-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x54,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x54,0x24,0x50]
; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x0c,0x24]
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x50] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x84,0x24,0x80,0x00,0x00,0x00]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xb0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xb0,0x00,0x00,0x00]
; FMACALL64-NEXT: shufps $255, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0xff] ; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0]
; FMACALL64-NEXT: ## xmm0 = xmm0[3,3,3,3] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1]
; FMACALL64-NEXT: movaps %xmm4, %xmm1 ## encoding: [0x0f,0x28,0xcc] ; FMACALL64-NEXT: xorps %xmm1, %xmm1 ## encoding: [0x0f,0x57,0xc9]
; FMACALL64-NEXT: shufps $255, %xmm4, %xmm1 ## encoding: [0x0f,0xc6,0xcc,0xff] ; FMACALL64-NEXT: movhlps %xmm4, %xmm1 ## encoding: [0x0f,0x12,0xcc]
; FMACALL64-NEXT: ## xmm1 = xmm1[3,3],xmm4[3,3] ; FMACALL64-NEXT: ## xmm1 = xmm4[1],xmm1[1]
; FMACALL64-NEXT: shufps $255, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0xff] ; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2]
; FMACALL64-NEXT: ## xmm2 = xmm2[3,3,3,3] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x60] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x40]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x50] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x84,0x24,0x80,0x00,0x00,0x00]
; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0] ; FMACALL64-NEXT: shufps $255, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0xff]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[3,3,3,3]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30]
; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9] ; FMACALL64-NEXT: shufps $255, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0xff]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[3,3,3,3]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xb0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xb0,0x00,0x00,0x00]
; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2] ; FMACALL64-NEXT: shufps $255, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0xff]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[3,3,3,3]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x14,0x44,0x24,0x60] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x40]
; FMACALL64-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8]
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x84,0x24,0x90,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x40]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x50] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x84,0x24,0x80,0x00,0x00,0x00]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xb0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xb0,0x00,0x00,0x00]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x60] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x84,0x24,0x90,0x00,0x00,0x00]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x50] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x84,0x24,0x80,0x00,0x00,0x00]
; FMACALL64-NEXT: shufps $85, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0x55] ; FMACALL64-NEXT: shufps $85, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0x55]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1,1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1,1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30]
; FMACALL64-NEXT: shufps $85, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0x55] ; FMACALL64-NEXT: shufps $85, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0x55]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1,1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1,1,1]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xb0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xb0,0x00,0x00,0x00]
; FMACALL64-NEXT: shufps $85, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0x55] ; FMACALL64-NEXT: shufps $85, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0x55]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1,1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1,1,1]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x60] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x8c,0x24,0x90,0x00,0x00,0x00]
; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8] ; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; FMACALL64-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload ; FMACALL64-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload
; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x8c,0x24,0x90,0x00,0x00,0x00] ; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x4c,0x24,0x40]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],mem[0] ; FMACALL64-NEXT: ## xmm1 = xmm1[0],mem[0]
; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x60] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x8c,0x24,0x90,0x00,0x00,0x00]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x04,0x24]
; FMACALL64-NEXT: shufps $255, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0xff]
; FMACALL64-NEXT: ## xmm0 = xmm0[3,3,3,3]
; FMACALL64-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x0c,0x24]
; FMACALL64-NEXT: shufps $255, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0xff]
; FMACALL64-NEXT: ## xmm1 = xmm1[3,3,3,3]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xc0,0x00,0x00,0x00]
; FMACALL64-NEXT: shufps $255, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0xff]
; FMACALL64-NEXT: ## xmm2 = xmm2[3,3,3,3]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x10]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x30]
; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0] ; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1]
; FMACALL64-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x0c,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10]
; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9] ; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xc0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xc0,0x00,0x00,0x00]
; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2] ; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x14,0x44,0x24,0x10]
; FMACALL64-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x50] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x30]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x04,0x24]
; FMACALL64-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: shufps $255, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0xff]
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x0c,0x24] ; FMACALL64-NEXT: ## xmm0 = xmm0[3,3,3,3]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10]
; FMACALL64-NEXT: shufps $255, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0xff]
; FMACALL64-NEXT: ## xmm1 = xmm1[3,3,3,3]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xc0,0x00,0x00,0x00]
; FMACALL64-NEXT: shufps $255, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0xff]
; FMACALL64-NEXT: ## xmm2 = xmm2[3,3,3,3]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30]
; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x30]
; FMACALL64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x04,0x24]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xc0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xc0,0x00,0x00,0x00]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x40]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x04,0x24]
; FMACALL64-NEXT: shufps $85, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0x55] ; FMACALL64-NEXT: shufps $85, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0x55]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1,1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1,1,1]
; FMACALL64-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x0c,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10]
; FMACALL64-NEXT: shufps $85, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0x55] ; FMACALL64-NEXT: shufps $85, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0x55]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1,1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1,1,1]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xc0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xc0,0x00,0x00,0x00]
; FMACALL64-NEXT: shufps $85, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0x55] ; FMACALL64-NEXT: shufps $85, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0x55]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1,1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1,1,1]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x40]
; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8] ; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; FMACALL64-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload ; FMACALL64-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload
; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x4c,0x24,0x50] ; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x4c,0x24,0x30]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],mem[0] ; FMACALL64-NEXT: ## xmm1 = xmm1[0],mem[0]
; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x40]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x50]
; FMACALL64-NEXT: shufps $255, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0xff] ; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0]
; FMACALL64-NEXT: ## xmm0 = xmm0[3,3,3,3] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x20]
; FMACALL64-NEXT: shufps $255, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0xff] ; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9]
; FMACALL64-NEXT: ## xmm1 = xmm1[3,3,3,3] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xd0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xd0,0x00,0x00,0x00]
; FMACALL64-NEXT: shufps $255, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0xff] ; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2]
; FMACALL64-NEXT: ## xmm2 = xmm2[3,3,3,3] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x04,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x04,0x24]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x50]
; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0] ; FMACALL64-NEXT: shufps $255, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0xff]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[3,3,3,3]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x20]
; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9] ; FMACALL64-NEXT: shufps $255, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0xff]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[3,3,3,3]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xd0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xd0,0x00,0x00,0x00]
; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2] ; FMACALL64-NEXT: shufps $255, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0xff]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[3,3,3,3]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: unpcklps (%rsp), %xmm0 ## 16-byte Folded Reload ; FMACALL64-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x14,0x04,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x0c,0x24]
; FMACALL64-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8]
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x30] ; FMACALL64-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x0c,0x24]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x50]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x20]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xd0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xd0,0x00,0x00,0x00]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x04,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x10]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x50]
; FMACALL64-NEXT: shufps $85, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0x55] ; FMACALL64-NEXT: shufps $85, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0x55]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1,1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1,1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x20]
; FMACALL64-NEXT: shufps $85, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0x55] ; FMACALL64-NEXT: shufps $85, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0x55]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1,1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1,1,1]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xd0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xd0,0x00,0x00,0x00]
; FMACALL64-NEXT: shufps $85, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0x55] ; FMACALL64-NEXT: shufps $85, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0x55]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1,1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1,1,1]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x0c,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10]
; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8] ; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; FMACALL64-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload ; FMACALL64-NEXT: unpcklpd (%rsp), %xmm1 ## 16-byte Folded Reload
; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x4c,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x0c,0x24]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],mem[0] ; FMACALL64-NEXT: ## xmm1 = xmm1[0],mem[0]
; FMACALL64-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x0c,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x10]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x70]
; FMACALL64-NEXT: shufps $255, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0xff]
; FMACALL64-NEXT: ## xmm0 = xmm0[3,3,3,3]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x8c,0x24,0x80,0x00,0x00,0x00]
; FMACALL64-NEXT: shufps $255, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0xff]
; FMACALL64-NEXT: ## xmm1 = xmm1[3,3,3,3]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xe0,0x00,0x00,0x00]
; FMACALL64-NEXT: shufps $255, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0xff]
; FMACALL64-NEXT: ## xmm2 = xmm2[3,3,3,3]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x20]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x70] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x60]
; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0] ; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x8c,0x24,0x80,0x00,0x00,0x00] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x70]
; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9] ; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xe0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xe0,0x00,0x00,0x00]
; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2] ; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x14,0x44,0x24,0x20]
; FMACALL64-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x20]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x70] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x60]
; FMACALL64-NEXT: shufps $255, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0xff]
; FMACALL64-NEXT: ## xmm0 = xmm0[3,3,3,3]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x70]
; FMACALL64-NEXT: shufps $255, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0xff]
; FMACALL64-NEXT: ## xmm1 = xmm1[3,3,3,3]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xe0,0x00,0x00,0x00]
; FMACALL64-NEXT: shufps $255, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0xff]
; FMACALL64-NEXT: ## xmm2 = xmm2[3,3,3,3]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x20]
; FMACALL64-NEXT: unpcklps %xmm0, %xmm1 ## encoding: [0x0f,0x14,0xc8]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x20]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x60]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x8c,0x24,0x80,0x00,0x00,0x00] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x70]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xe0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xe0,0x00,0x00,0x00]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x50]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x70] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x60]
; FMACALL64-NEXT: shufps $85, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0x55] ; FMACALL64-NEXT: shufps $85, %xmm0, %xmm0 ## encoding: [0x0f,0xc6,0xc0,0x55]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1,1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1,1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x8c,0x24,0x80,0x00,0x00,0x00] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x70]
; FMACALL64-NEXT: shufps $85, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0x55] ; FMACALL64-NEXT: shufps $85, %xmm1, %xmm1 ## encoding: [0x0f,0xc6,0xc9,0x55]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1,1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1,1,1]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xe0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xe0,0x00,0x00,0x00]
; FMACALL64-NEXT: shufps $85, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0x55] ; FMACALL64-NEXT: shufps $85, %xmm2, %xmm2 ## encoding: [0x0f,0xc6,0xd2,0x55]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1,1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1,1,1]
; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x5c,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x5c,0x24,0x50]
; FMACALL64-NEXT: unpcklps %xmm0, %xmm3 ## encoding: [0x0f,0x14,0xd8] ; FMACALL64-NEXT: unpcklps %xmm0, %xmm3 ## encoding: [0x0f,0x14,0xd8]
; FMACALL64-NEXT: ## xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1] ; FMACALL64-NEXT: ## xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
; FMACALL64-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 ## 16-byte Folded Reload ; FMACALL64-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 ## 16-byte Folded Reload
; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x5c,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x5c,0x24,0x20]
; FMACALL64-NEXT: ## xmm3 = xmm3[0],mem[0] ; FMACALL64-NEXT: ## xmm3 = xmm3[0],mem[0]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x60] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x84,0x24,0x90,0x00,0x00,0x00]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x40]
; FMACALL64-NEXT: movaps (%rsp), %xmm2 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x14,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x10]
; FMACALL64-NEXT: addq $168, %rsp ## encoding: [0x48,0x81,0xc4,0xa8,0x00,0x00,0x00] ; FMACALL64-NEXT: addq $168, %rsp ## encoding: [0x48,0x81,0xc4,0xa8,0x00,0x00,0x00]
; FMACALL64-NEXT: retq ## encoding: [0xc3] ; FMACALL64-NEXT: retq ## encoding: [0xc3]
; ;
; AVX512-LABEL: test_v16f32: ; AVX512-LABEL: test_v16f32:
; AVX512: ## %bb.0: ## %entry ; AVX512: ## %bb.0: ## %entry
; AVX512-NEXT: vfmadd213ps %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x48,0xa8,0xc2] ; AVX512-NEXT: vfmadd213ps %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x48,0xa8,0xc2]
; AVX512-NEXT: ## zmm0 = (zmm1 * zmm0) + zmm2 ; AVX512-NEXT: ## zmm0 = (zmm1 * zmm0) + zmm2
; AVX512-NEXT: retq ## encoding: [0xc3] ; AVX512-NEXT: retq ## encoding: [0xc3]
▲ Show 20 Lines • Show All 323 Lines • ▼ Show 20 Lines
; FMA64-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0xf1,0xa8,0xc2] ; FMA64-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0xf1,0xa8,0xc2]
; FMA64-NEXT: ## xmm0 = (xmm1 * xmm0) + xmm2 ; FMA64-NEXT: ## xmm0 = (xmm1 * xmm0) + xmm2
; FMA64-NEXT: retq ## encoding: [0xc3] ; FMA64-NEXT: retq ## encoding: [0xc3]
; ;
; FMACALL64-LABEL: test_v2f64: ; FMACALL64-LABEL: test_v2f64:
; FMACALL64: ## %bb.0: ; FMACALL64: ## %bb.0:
; FMACALL64-NEXT: subq $72, %rsp ## encoding: [0x48,0x83,0xec,0x48] ; FMACALL64-NEXT: subq $72, %rsp ## encoding: [0x48,0x83,0xec,0x48]
; FMACALL64-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x54,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x54,0x24,0x10]
; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x20]
; FMACALL64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x04,0x24]
; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x30]
; FMACALL64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x04,0x24]
; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0] ; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10]
; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9] ; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x20]
; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2] ; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1]
; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x04,0x24]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x30]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x20]
; FMACALL64-NEXT: movlhps %xmm0, %xmm1 ## encoding: [0x0f,0x16,0xc8] ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x10]
; FMACALL64-NEXT: movaps %xmm1, %xmm0 ## encoding: [0x0f,0x28,0xc1] ; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: unpcklpd (%rsp), %xmm0 ## 16-byte Folded Reload
; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x04,0x24]
; FMACALL64-NEXT: ## xmm0 = xmm0[0],mem[0]
; FMACALL64-NEXT: addq $72, %rsp ## encoding: [0x48,0x83,0xc4,0x48] ; FMACALL64-NEXT: addq $72, %rsp ## encoding: [0x48,0x83,0xc4,0x48]
; FMACALL64-NEXT: retq ## encoding: [0xc3] ; FMACALL64-NEXT: retq ## encoding: [0xc3]
; ;
; AVX512-LABEL: test_v2f64: ; AVX512-LABEL: test_v2f64:
; AVX512: ## %bb.0: ; AVX512: ## %bb.0:
; AVX512-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0xf1,0xa8,0xc2] ; AVX512-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0xf1,0xa8,0xc2]
; AVX512-NEXT: ## xmm0 = (xmm1 * xmm0) + xmm2 ; AVX512-NEXT: ## xmm0 = (xmm1 * xmm0) + xmm2
; AVX512-NEXT: retq ## encoding: [0xc3] ; AVX512-NEXT: retq ## encoding: [0xc3]
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; FMA64-NEXT: ## ymm0 = (ymm1 * ymm0) + ymm2 ; FMA64-NEXT: ## ymm0 = (ymm1 * ymm0) + ymm2
; FMA64-NEXT: retq ## encoding: [0xc3] ; FMA64-NEXT: retq ## encoding: [0xc3]
; ;
; FMACALL64-LABEL: test_v4f64: ; FMACALL64-LABEL: test_v4f64:
; FMACALL64: ## %bb.0: ## %entry ; FMACALL64: ## %bb.0: ## %entry
; FMACALL64-NEXT: subq $120, %rsp ## encoding: [0x48,0x83,0xec,0x78] ; FMACALL64-NEXT: subq $120, %rsp ## encoding: [0x48,0x83,0xec,0x78]
; FMACALL64-NEXT: movaps %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x6c,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x6c,0x24,0x40]
; FMACALL64-NEXT: movaps %xmm4, (%rsp) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x24,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x64,0x24,0x60]
; FMACALL64-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x5c,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x5c,0x24,0x30]
; FMACALL64-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm2, (%rsp) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x54,0x24,0x60] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x14,0x24]
; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x20]
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x10]
; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1]
; FMACALL64-NEXT: xorps %xmm1, %xmm1 ## encoding: [0x0f,0x57,0xc9]
; FMACALL64-NEXT: movhlps %xmm2, %xmm1 ## encoding: [0x0f,0x12,0xca]
; FMACALL64-NEXT: ## xmm1 = xmm2[1],xmm1[1]
; FMACALL64-NEXT: xorps %xmm2, %xmm2 ## encoding: [0x0f,0x57,0xd2]
; FMACALL64-NEXT: movhlps %xmm4, %xmm2 ## encoding: [0x0f,0x12,0xd4]
; FMACALL64-NEXT: ## xmm2 = xmm4[1],xmm2[1]
; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x50] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x50]
; FMACALL64-NEXT: movaps %xmm2, %xmm1 ## encoding: [0x0f,0x28,0xca] ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: movaps %xmm4, %xmm2 ## encoding: [0x0f,0x28,0xd4] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x10]
; FMACALL64-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x0c,0x24]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x60]
; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload
; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x44,0x24,0x50]
; FMACALL64-NEXT: ## xmm0 = xmm0[0],mem[0]
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x10]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x50] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x20]
; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0] ; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x60] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30]
; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9] ; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1]
; FMACALL64-NEXT: movaps (%rsp), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x14,0x24]
; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1]
; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10]
; FMACALL64-NEXT: movlhps %xmm0, %xmm1 ## encoding: [0x0f,0x16,0xc8]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0]
; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x10]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x20]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x40]
; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1]
; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x04,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x04,0x24]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x20]
; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30]
; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x40]
; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1]
; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps %xmm0, %xmm1 ## encoding: [0x0f,0x28,0xc8]
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x0c,0x24] ; FMACALL64-NEXT: unpcklpd (%rsp), %xmm1 ## 16-byte Folded Reload
; FMACALL64-NEXT: movlhps %xmm0, %xmm1 ## encoding: [0x0f,0x16,0xc8] ; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x0c,0x24]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0] ; FMACALL64-NEXT: ## xmm1 = xmm1[0],mem[0]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x10]
; FMACALL64-NEXT: addq $120, %rsp ## encoding: [0x48,0x83,0xc4,0x78] ; FMACALL64-NEXT: addq $120, %rsp ## encoding: [0x48,0x83,0xc4,0x78]
; FMACALL64-NEXT: retq ## encoding: [0xc3] ; FMACALL64-NEXT: retq ## encoding: [0xc3]
; ;
; AVX512-LABEL: test_v4f64: ; AVX512-LABEL: test_v4f64:
; AVX512: ## %bb.0: ## %entry ; AVX512: ## %bb.0: ## %entry
; AVX512-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0xf5,0xa8,0xc2] ; AVX512-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0xf5,0xa8,0xc2]
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines
; FMA64-NEXT: retq ## encoding: [0xc3] ; FMA64-NEXT: retq ## encoding: [0xc3]
; ;
; FMACALL64-LABEL: test_v8f64: ; FMACALL64-LABEL: test_v8f64:
; FMACALL64: ## %bb.0: ## %entry ; FMACALL64: ## %bb.0: ## %entry
; FMACALL64-NEXT: subq $152, %rsp ## encoding: [0x48,0x81,0xec,0x98,0x00,0x00,0x00] ; FMACALL64-NEXT: subq $152, %rsp ## encoding: [0x48,0x81,0xec,0x98,0x00,0x00,0x00]
; FMACALL64-NEXT: movaps %xmm7, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm7, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x7c,0x24,0x70] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x7c,0x24,0x70]
; FMACALL64-NEXT: movaps %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x74,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x74,0x24,0x30]
; FMACALL64-NEXT: movaps %xmm5, (%rsp) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x2c,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x6c,0x24,0x10]
; FMACALL64-NEXT: movaps %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x64,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x64,0x24,0x40]
; FMACALL64-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x5c,0x24,0x60] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x5c,0x24,0x60]
; FMACALL64-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x54,0x24,0x50] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x54,0x24,0x20]
; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x0c,0x24]
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x84,0x24,0x80,0x00,0x00,0x00] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x50]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xa0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xa0,0x00,0x00,0x00]
; FMACALL64-NEXT: movaps %xmm4, %xmm1 ## encoding: [0x0f,0x28,0xcc] ; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1]
; FMACALL64-NEXT: xorps %xmm1, %xmm1 ## encoding: [0x0f,0x57,0xc9]
; FMACALL64-NEXT: movhlps %xmm4, %xmm1 ## encoding: [0x0f,0x12,0xcc]
; FMACALL64-NEXT: ## xmm1 = xmm4[1],xmm1[1]
; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1]
; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x84,0x24,0x80,0x00,0x00,0x00]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x84,0x24,0x80,0x00,0x00,0x00] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x50]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x40]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xa0,0x00,0x00,0x00]
; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload
; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x84,0x24,0x80,0x00,0x00,0x00]
; FMACALL64-NEXT: ## xmm0 = xmm0[0],mem[0]
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x50]
; FMACALL64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x04,0x24]
; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0] ; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10]
; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9] ; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xa0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xb0,0x00,0x00,0x00]
; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2] ; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1]
; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x40]
; FMACALL64-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x04,0x24]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10]
; FMACALL64-NEXT: movlhps %xmm0, %xmm1 ## encoding: [0x0f,0x16,0xc8]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0]
; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x30]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x40]
; FMACALL64-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x0c,0x24]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xb0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xb0,0x00,0x00,0x00]
; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload
; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x44,0x24,0x40]
; FMACALL64-NEXT: ## xmm0 = xmm0[0],mem[0]
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x10]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x40] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x20]
; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0] ; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1]
; FMACALL64-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x0c,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30]
; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9] ; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xb0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xc0,0x00,0x00,0x00]
; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2] ; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1]
; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x04,0x24]
; FMACALL64-NEXT: movlhps %xmm0, %xmm1 ## encoding: [0x0f,0x16,0xc8]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0]
; FMACALL64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x4c,0x24,0x10]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x50] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x20]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x30]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xc0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xc0,0x00,0x00,0x00]
; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; FMACALL64-NEXT: unpcklpd (%rsp), %xmm0 ## 16-byte Folded Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x04,0x24] ; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x04,0x24]
; FMACALL64-NEXT: ## xmm0 = xmm0[0],mem[0]
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x30]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x50] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x60]
; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0] ; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1] ; FMACALL64-NEXT: ## xmm0 = xmm0[1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x70]
; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9] ; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1] ; FMACALL64-NEXT: ## xmm1 = xmm1[1,1]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xc0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xd0,0x00,0x00,0x00]
; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2] ; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1] ; FMACALL64-NEXT: ## xmm2 = xmm2[1,1]
; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x0c,0x24]
; FMACALL64-NEXT: movlhps %xmm0, %xmm1 ## encoding: [0x0f,0x16,0xc8]
; FMACALL64-NEXT: ## xmm1 = xmm1[0],xmm0[0]
; FMACALL64-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x0c,0x24]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x60]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x70]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xd0,0x00,0x00,0x00]
; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; FMACALL64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x20] ; FMACALL64-NEXT: ## encoding: [0x0f,0x29,0x44,0x24,0x20]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x60] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x60]
; FMACALL64-NEXT: movhlps %xmm0, %xmm0 ## encoding: [0x0f,0x12,0xc0]
; FMACALL64-NEXT: ## xmm0 = xmm0[1,1]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x70] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x70]
; FMACALL64-NEXT: movhlps %xmm1, %xmm1 ## encoding: [0x0f,0x12,0xc9]
; FMACALL64-NEXT: ## xmm1 = xmm1[1,1]
; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xd0,0x00,0x00,0x00] ; FMACALL64-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2 ## encoding: [0x0f,0x28,0x94,0x24,0xd0,0x00,0x00,0x00]
; FMACALL64-NEXT: movhlps %xmm2, %xmm2 ## encoding: [0x0f,0x12,0xd2]
; FMACALL64-NEXT: ## xmm2 = xmm2[1,1]
; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A] ; FMACALL64-NEXT: callq _fma ## encoding: [0xe8,A,A,A,A]
; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel ; FMACALL64-NEXT: ## fixup A - offset: 1, value: _fma-4, kind: reloc_branch_4byte_pcrel
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 ## 16-byte Reload ; FMACALL64-NEXT: movaps %xmm0, %xmm3 ## encoding: [0x0f,0x28,0xd8]
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x5c,0x24,0x20] ; FMACALL64-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 ## 16-byte Folded Reload
; FMACALL64-NEXT: movlhps %xmm0, %xmm3 ## encoding: [0x0f,0x16,0xd8] ; FMACALL64-NEXT: ## encoding: [0x66,0x0f,0x14,0x5c,0x24,0x20]
; FMACALL64-NEXT: ## xmm3 = xmm3[0],xmm0[0] ; FMACALL64-NEXT: ## xmm3 = xmm3[0],mem[0]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x30] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x44,0x24,0x50]
; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x4c,0x24,0x10]
; FMACALL64-NEXT: movaps (%rsp), %xmm2 ## 16-byte Reload ; FMACALL64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x14,0x24] ; FMACALL64-NEXT: ## encoding: [0x0f,0x28,0x54,0x24,0x30]
; FMACALL64-NEXT: addq $152, %rsp ## encoding: [0x48,0x81,0xc4,0x98,0x00,0x00,0x00] ; FMACALL64-NEXT: addq $152, %rsp ## encoding: [0x48,0x81,0xc4,0x98,0x00,0x00,0x00]
; FMACALL64-NEXT: retq ## encoding: [0xc3] ; FMACALL64-NEXT: retq ## encoding: [0xc3]
; ;
; AVX512-LABEL: test_v8f64: ; AVX512-LABEL: test_v8f64:
; AVX512: ## %bb.0: ## %entry ; AVX512: ## %bb.0: ## %entry
; AVX512-NEXT: vfmadd213pd %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x48,0xa8,0xc2] ; AVX512-NEXT: vfmadd213pd %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x48,0xa8,0xc2]
; AVX512-NEXT: ## zmm0 = (zmm1 * zmm0) + zmm2 ; AVX512-NEXT: ## zmm0 = (zmm1 * zmm0) + zmm2
; AVX512-NEXT: retq ## encoding: [0xc3] ; AVX512-NEXT: retq ## encoding: [0xc3]
▲ Show 20 Lines • Show All 197 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/fp-intrinsics-fma.ll

Show First 20 Lines • Show All 524 Lines • ▼ Show 20 Lines
; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; NOFMA-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; NOFMA-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; NOFMA-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; NOFMA-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; NOFMA-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3] ; NOFMA-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
; NOFMA-NEXT: callq fmaf@PLT ; NOFMA-NEXT: callq fmaf@PLT
; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; NOFMA-NEXT: xorps %xmm1, %xmm1
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload ; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; NOFMA-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1] ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: xorps %xmm2, %xmm2
; NOFMA-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; NOFMA-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; NOFMA-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = mem[2,3,2,3] ; NOFMA-NEXT: # xmm0 = mem[2,3,2,3]
; NOFMA-NEXT: callq fmaf@PLT ; NOFMA-NEXT: callq fmaf@PLT
; NOFMA-NEXT: punpckldq (%rsp), %xmm0 # 16-byte Folded Reload ; NOFMA-NEXT: punpckldq (%rsp), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; NOFMA-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
Show All 39 Lines
; NOFMA-NEXT: subq $72, %rsp ; NOFMA-NEXT: subq $72, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 80 ; NOFMA-NEXT: .cfi_def_cfa_offset 80
; NOFMA-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: callq fma@PLT ; NOFMA-NEXT: callq fma@PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; NOFMA-NEXT: xorps %xmm1, %xmm1
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload ; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; NOFMA-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1] ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: xorps %xmm2, %xmm2
; NOFMA-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; NOFMA-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; NOFMA-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = mem[2,3,2,3] ; NOFMA-NEXT: # xmm0 = mem[2,3,2,3]
; NOFMA-NEXT: callq fma@PLT ; NOFMA-NEXT: callq fma@PLT
; NOFMA-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; NOFMA-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; NOFMA-NEXT: movdqa %xmm1, %xmm0 ; NOFMA-NEXT: movdqa %xmm1, %xmm0
; NOFMA-NEXT: addq $72, %rsp ; NOFMA-NEXT: addq $72, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 8 ; NOFMA-NEXT: .cfi_def_cfa_offset 8
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
define <4 x float> @f23(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 { define <4 x float> @f23(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-LABEL: f23: ; NOFMA-LABEL: f23:
; NOFMA: # %bb.0: # %entry ; NOFMA: # %bb.0: # %entry
; NOFMA-NEXT: subq $88, %rsp ; NOFMA-NEXT: subq $88, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 96 ; NOFMA-NEXT: .cfi_def_cfa_offset 96
; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movdqa {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] ; NOFMA-NEXT: movdqa {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
; NOFMA-NEXT: pxor %xmm3, %xmm0 ; NOFMA-NEXT: pxor %xmm3, %xmm0
; NOFMA-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: pxor %xmm3, %xmm2 ; NOFMA-NEXT: pxor %xmm3, %xmm2
; NOFMA-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3] ; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; NOFMA-NEXT: pshufd {{.*#+}} xmm2 = xmm2[3,3,3,3] ; NOFMA-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; NOFMA-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
; NOFMA-NEXT: callq fmaf@PLT ; NOFMA-NEXT: callq fmaf@PLT
; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; NOFMA-NEXT: pshufd $255, (%rsp), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = mem[2,3,2,3] ; NOFMA-NEXT: # xmm0 = mem[3,3,3,3]
; NOFMA-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload ; NOFMA-NEXT: pshufd $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm2 = mem[2,3,2,3] ; NOFMA-NEXT: # xmm2 = mem[3,3,3,3]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; NOFMA-NEXT: callq fmaf@PLT ; NOFMA-NEXT: callq fmaf@PLT
; NOFMA-NEXT: punpckldq (%rsp), %xmm0 # 16-byte Folded Reload ; NOFMA-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; NOFMA-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; NOFMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; NOFMA-NEXT: callq fmaf@PLT ; NOFMA-NEXT: callq fmaf@PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: pshufd $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; NOFMA-NEXT: pshufd $85, (%rsp), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = mem[1,1,1,1] ; NOFMA-NEXT: # xmm0 = mem[1,1,1,1]
; NOFMA-NEXT: pshufd $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload ; NOFMA-NEXT: pshufd $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm2 = mem[1,1,1,1] ; NOFMA-NEXT: # xmm2 = mem[1,1,1,1]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1] ; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
; NOFMA-NEXT: callq fmaf@PLT ; NOFMA-NEXT: callq fmaf@PLT
; NOFMA-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; NOFMA-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NOFMA-NEXT: punpcklqdq (%rsp), %xmm1 # 16-byte Folded Reload ; NOFMA-NEXT: punpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm1 = xmm1[0],mem[0] ; NOFMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NOFMA-NEXT: movdqa %xmm1, %xmm0 ; NOFMA-NEXT: movdqa %xmm1, %xmm0
; NOFMA-NEXT: addq $88, %rsp ; NOFMA-NEXT: addq $88, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 8 ; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq ; NOFMA-NEXT: retq
; ;
; FMA-LABEL: f23: ; FMA-LABEL: f23:
; FMA: # %bb.0: # %entry ; FMA: # %bb.0: # %entry
Show All 14 Lines
} }
define <2 x double> @f24(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 { define <2 x double> @f24(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 {
; NOFMA-LABEL: f24: ; NOFMA-LABEL: f24:
; NOFMA: # %bb.0: # %entry ; NOFMA: # %bb.0: # %entry
; NOFMA-NEXT: subq $72, %rsp ; NOFMA-NEXT: subq $72, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 80 ; NOFMA-NEXT: .cfi_def_cfa_offset 80
; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0] ; NOFMA-NEXT: movdqa {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0]
; NOFMA-NEXT: xorps %xmm3, %xmm0 ; NOFMA-NEXT: pxor %xmm3, %xmm0
; NOFMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: xorps %xmm3, %xmm2 ; NOFMA-NEXT: pxor %xmm3, %xmm2
; NOFMA-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; NOFMA-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; NOFMA-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
; NOFMA-NEXT: callq fma@PLT ; NOFMA-NEXT: callq fma@PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: pshufd $238, (%rsp), %xmm0 # 16-byte Folded Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: # xmm0 = mem[2,3,2,3]
; NOFMA-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm2 = mem[2,3,2,3]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; NOFMA-NEXT: callq fma@PLT ; NOFMA-NEXT: callq fma@PLT
; NOFMA-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; NOFMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NOFMA-NEXT: movdqa %xmm1, %xmm0
; NOFMA-NEXT: addq $72, %rsp ; NOFMA-NEXT: addq $72, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 8 ; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq ; NOFMA-NEXT: retq
; ;
; FMA-LABEL: f24: ; FMA-LABEL: f24:
; FMA: # %bb.0: # %entry ; FMA: # %bb.0: # %entry
; FMA-NEXT: vfnmsub213pd {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2 ; FMA-NEXT: vfnmsub213pd {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2
; FMA-NEXT: retq ; FMA-NEXT: retq
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define <4 x float> @f25(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 { define <4 x float> @f25(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-LABEL: f25: ; NOFMA-LABEL: f25:
; NOFMA: # %bb.0: # %entry ; NOFMA: # %bb.0: # %entry
; NOFMA-NEXT: subq $88, %rsp ; NOFMA-NEXT: subq $88, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 96 ; NOFMA-NEXT: .cfi_def_cfa_offset 96
; NOFMA-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; NOFMA-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; NOFMA-NEXT: callq fmaf@PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NOFMA-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; NOFMA-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; NOFMA-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; NOFMA-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; NOFMA-NEXT: callq fmaf@PLT ; NOFMA-NEXT: callq fmaf@PLT
; NOFMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; NOFMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload ; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1] ; NOFMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NOFMA-NEXT: callq fmaf@PLT
; NOFMA-NEXT: unpcklps (%rsp), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; NOFMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; NOFMA-NEXT: callq fmaf@PLT ; NOFMA-NEXT: callq fmaf@PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; NOFMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NOFMA-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; NOFMA-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1] ; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; NOFMA-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; NOFMA-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; NOFMA-NEXT: callq fmaf@PLT ; NOFMA-NEXT: callq fmaf@PLT
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; NOFMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NOFMA-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload ; NOFMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm1 = xmm1[0],mem[0] ; NOFMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; NOFMA-NEXT: movaps %xmm1, %xmm0 ; NOFMA-NEXT: movaps %xmm1, %xmm0
; NOFMA-NEXT: addq $88, %rsp ; NOFMA-NEXT: addq $88, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 8 ; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq ; NOFMA-NEXT: retq
; ;
; FMA-AVX1-LABEL: f25: ; FMA-AVX1-LABEL: f25:
Show All 24 Lines
define <2 x double> @f26(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 { define <2 x double> @f26(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 {
; NOFMA-LABEL: f26: ; NOFMA-LABEL: f26:
; NOFMA: # %bb.0: # %entry ; NOFMA: # %bb.0: # %entry
; NOFMA-NEXT: subq $72, %rsp ; NOFMA-NEXT: subq $72, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 80 ; NOFMA-NEXT: .cfi_def_cfa_offset 80
; NOFMA-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: callq fma@PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; NOFMA-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1] ; NOFMA-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; NOFMA-NEXT: callq fma@PLT ; NOFMA-NEXT: callq fma@PLT
; NOFMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; NOFMA-NEXT: callq fma@PLT
; NOFMA-NEXT: movaps %xmm1, %xmm0 ; NOFMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; NOFMA-NEXT: addq $72, %rsp ; NOFMA-NEXT: addq $72, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 8 ; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq ; NOFMA-NEXT: retq
; ;
; FMA-LABEL: f26: ; FMA-LABEL: f26:
; FMA: # %bb.0: # %entry ; FMA: # %bb.0: # %entry
; FMA-NEXT: vfmadd213pd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2 ; FMA-NEXT: vfmadd213pd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
; FMA-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; FMA-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
Show All 15 Lines
define <4 x float> @f27(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 { define <4 x float> @f27(<4 x float> %0, <4 x float> %1, <4 x float> %2) #0 {
; NOFMA-LABEL: f27: ; NOFMA-LABEL: f27:
; NOFMA: # %bb.0: # %entry ; NOFMA: # %bb.0: # %entry
; NOFMA-NEXT: subq $88, %rsp ; NOFMA-NEXT: subq $88, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 96 ; NOFMA-NEXT: .cfi_def_cfa_offset 96
; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movdqa {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] ; NOFMA-NEXT: movdqa {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
; NOFMA-NEXT: pxor %xmm3, %xmm0 ; NOFMA-NEXT: pxor %xmm3, %xmm0
; NOFMA-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: pxor %xmm3, %xmm2 ; NOFMA-NEXT: pxor %xmm3, %xmm2
; NOFMA-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3] ; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; NOFMA-NEXT: pshufd {{.*#+}} xmm2 = xmm2[3,3,3,3] ; NOFMA-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; NOFMA-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
; NOFMA-NEXT: callq fmaf@PLT ; NOFMA-NEXT: callq fmaf@PLT
; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; NOFMA-NEXT: pshufd $255, (%rsp), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = mem[2,3,2,3] ; NOFMA-NEXT: # xmm0 = mem[3,3,3,3]
; NOFMA-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload ; NOFMA-NEXT: pshufd $255, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm2 = mem[2,3,2,3] ; NOFMA-NEXT: # xmm2 = mem[3,3,3,3]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; NOFMA-NEXT: callq fmaf@PLT ; NOFMA-NEXT: callq fmaf@PLT
; NOFMA-NEXT: punpckldq (%rsp), %xmm0 # 16-byte Folded Reload ; NOFMA-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; NOFMA-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; NOFMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; NOFMA-NEXT: callq fmaf@PLT ; NOFMA-NEXT: callq fmaf@PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: pshufd $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; NOFMA-NEXT: pshufd $85, (%rsp), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm0 = mem[1,1,1,1] ; NOFMA-NEXT: # xmm0 = mem[1,1,1,1]
; NOFMA-NEXT: pshufd $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload ; NOFMA-NEXT: pshufd $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm2 = mem[1,1,1,1] ; NOFMA-NEXT: # xmm2 = mem[1,1,1,1]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1] ; NOFMA-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
; NOFMA-NEXT: callq fmaf@PLT ; NOFMA-NEXT: callq fmaf@PLT
; NOFMA-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; NOFMA-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NOFMA-NEXT: punpcklqdq (%rsp), %xmm1 # 16-byte Folded Reload ; NOFMA-NEXT: punpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm1 = xmm1[0],mem[0] ; NOFMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NOFMA-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; NOFMA-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; NOFMA-NEXT: movdqa %xmm1, %xmm0 ; NOFMA-NEXT: movdqa %xmm1, %xmm0
; NOFMA-NEXT: addq $88, %rsp ; NOFMA-NEXT: addq $88, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 8 ; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq ; NOFMA-NEXT: retq
; ;
; FMA-AVX1-LABEL: f27: ; FMA-AVX1-LABEL: f27:
Show All 25 Lines
} }
define <2 x double> @f28(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 { define <2 x double> @f28(<2 x double> %0, <2 x double> %1, <2 x double> %2) #0 {
; NOFMA-LABEL: f28: ; NOFMA-LABEL: f28:
; NOFMA: # %bb.0: # %entry ; NOFMA: # %bb.0: # %entry
; NOFMA-NEXT: subq $72, %rsp ; NOFMA-NEXT: subq $72, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 80 ; NOFMA-NEXT: .cfi_def_cfa_offset 80
; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movaps {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0] ; NOFMA-NEXT: movdqa {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0]
; NOFMA-NEXT: xorps %xmm3, %xmm0 ; NOFMA-NEXT: pxor %xmm3, %xmm0
; NOFMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: xorps %xmm3, %xmm2 ; NOFMA-NEXT: pxor %xmm3, %xmm2
; NOFMA-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; NOFMA-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; NOFMA-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
; NOFMA-NEXT: callq fma@PLT ; NOFMA-NEXT: callq fma@PLT
; NOFMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; NOFMA-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
; NOFMA-NEXT: pshufd $238, (%rsp), %xmm0 # 16-byte Folded Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NOFMA-NEXT: # xmm0 = mem[2,3,2,3]
; NOFMA-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Folded Reload
; NOFMA-NEXT: # xmm2 = mem[2,3,2,3]
; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; NOFMA-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; NOFMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; NOFMA-NEXT: callq fma@PLT ; NOFMA-NEXT: callq fma@PLT
; NOFMA-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; NOFMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NOFMA-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; NOFMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NOFMA-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; NOFMA-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; NOFMA-NEXT: movdqa %xmm1, %xmm0
; NOFMA-NEXT: addq $72, %rsp ; NOFMA-NEXT: addq $72, %rsp
; NOFMA-NEXT: .cfi_def_cfa_offset 8 ; NOFMA-NEXT: .cfi_def_cfa_offset 8
; NOFMA-NEXT: retq ; NOFMA-NEXT: retq
; ;
; FMA-LABEL: f28: ; FMA-LABEL: f28:
; FMA: # %bb.0: # %entry ; FMA: # %bb.0: # %entry
; FMA-NEXT: vfnmsub213pd {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2 ; FMA-NEXT: vfnmsub213pd {{.*#+}} xmm0 = -(xmm1 * xmm0) - xmm2
; FMA-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; FMA-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
Show All 29 Lines

llvm/test/CodeGen/X86/fp-round.ll

Show First 20 Lines • Show All 145 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
ret double %a ret double %a
} }
define <4 x float> @round_v4f32(<4 x float> %x) { define <4 x float> @round_v4f32(<4 x float> %x) {
; SSE2-LABEL: round_v4f32: ; SSE2-LABEL: round_v4f32:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: subq $56, %rsp ; SSE2-NEXT: subq $56, %rsp
; SSE2-NEXT: .cfi_def_cfa_offset 64 ; SSE2-NEXT: .cfi_def_cfa_offset 64
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: unpcklps (%rsp), %xmm0 ## 16-byte Folded Reload ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: unpcklpd (%rsp), %xmm1 ## 16-byte Folded Reload ; SSE2-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0] ; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0]
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: addq $56, %rsp ; SSE2-NEXT: addq $56, %rsp
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: round_v4f32: ; SSE41-LABEL: round_v4f32:
; SSE41: ## %bb.0: ; SSE41: ## %bb.0:
; SSE41-NEXT: movaps {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
Show All 22 Lines; AVX512-NEXT: retq
ret <4 x float> %a ret <4 x float> %a
} }
define <2 x double> @round_v2f64(<2 x double> %x) { define <2 x double> @round_v2f64(<2 x double> %x) {
; SSE2-LABEL: round_v2f64: ; SSE2-LABEL: round_v2f64:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: subq $40, %rsp ; SSE2-NEXT: subq $40, %rsp
; SSE2-NEXT: .cfi_def_cfa_offset 48 ; SSE2-NEXT: .cfi_def_cfa_offset 48
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: callq _round
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _round ; SSE2-NEXT: callq _round
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: callq _round
; SSE2-NEXT: unpcklpd (%rsp), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0]
; SSE2-NEXT: addq $40, %rsp ; SSE2-NEXT: addq $40, %rsp
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: round_v2f64: ; SSE41-LABEL: round_v2f64:
; SSE41: ## %bb.0: ; SSE41: ## %bb.0:
; SSE41-NEXT: movapd {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0] ; SSE41-NEXT: movapd {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0]
; SSE41-NEXT: andpd %xmm0, %xmm1 ; SSE41-NEXT: andpd %xmm0, %xmm1
; SSE41-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE41-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
Show All 21 Lines
} }
define <8 x float> @round_v8f32(<8 x float> %x) { define <8 x float> @round_v8f32(<8 x float> %x) {
; SSE2-LABEL: round_v8f32: ; SSE2-LABEL: round_v8f32:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: subq $72, %rsp ; SSE2-NEXT: subq $72, %rsp
; SSE2-NEXT: .cfi_def_cfa_offset 80 ; SSE2-NEXT: .cfi_def_cfa_offset 80
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload ; SSE2-NEXT: unpcklpd (%rsp), %xmm1 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0] ; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: unpcklps (%rsp), %xmm0 ## 16-byte Folded Reload ; SSE2-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
Show All 38 Lines
} }
define <4 x double> @round_v4f64(<4 x double> %x) { define <4 x double> @round_v4f64(<4 x double> %x) {
; SSE2-LABEL: round_v4f64: ; SSE2-LABEL: round_v4f64:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: subq $56, %rsp ; SSE2-NEXT: subq $56, %rsp
; SSE2-NEXT: .cfi_def_cfa_offset 64 ; SSE2-NEXT: .cfi_def_cfa_offset 64
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: callq _round
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _round ; SSE2-NEXT: callq _round
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _round ; SSE2-NEXT: callq _round
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; SSE2-NEXT: unpcklpd (%rsp), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0]
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _round ; SSE2-NEXT: callq _round
; SSE2-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _round
; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpcklpd (%rsp), %xmm1 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0]
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: addq $56, %rsp ; SSE2-NEXT: addq $56, %rsp
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: round_v4f64: ; SSE41-LABEL: round_v4f64:
; SSE41: ## %bb.0: ; SSE41: ## %bb.0:
; SSE41-NEXT: movapd {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0] ; SSE41-NEXT: movapd {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0]
; SSE41-NEXT: movapd %xmm0, %xmm3 ; SSE41-NEXT: movapd %xmm0, %xmm3
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define <16 x float> @round_v16f32(<16 x float> %x) { define <16 x float> @round_v16f32(<16 x float> %x) {
; SSE2-LABEL: round_v16f32: ; SSE2-LABEL: round_v16f32:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: subq $104, %rsp ; SSE2-NEXT: subq $104, %rsp
; SSE2-NEXT: .cfi_def_cfa_offset 112 ; SSE2-NEXT: .cfi_def_cfa_offset 112
; SSE2-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundf
; SSE2-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload ; SSE2-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0] ; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: unpcklps (%rsp), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: unpcklpd (%rsp), %xmm1 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0]
; SSE2-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: unpcklpd (%rsp), %xmm1 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE2-NEXT: callq _roundf ; SSE2-NEXT: callq _roundf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 ## 16-byte Reload ; SSE2-NEXT: movaps (%rsp), %xmm3 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
; SSE2-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 ## 16-byte Folded Reload ; SSE2-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm3 = xmm3[0],mem[0] ; SSE2-NEXT: ## xmm3 = xmm3[0],mem[0]
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: movaps (%rsp), %xmm2 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; SSE2-NEXT: addq $104, %rsp ; SSE2-NEXT: addq $104, %rsp
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: round_v16f32: ; SSE41-LABEL: round_v16f32:
; SSE41: ## %bb.0: ; SSE41: ## %bb.0:
; SSE41-NEXT: movaps {{.*#+}} xmm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] ; SSE41-NEXT: movaps {{.*#+}} xmm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
; SSE41-NEXT: movaps %xmm0, %xmm5 ; SSE41-NEXT: movaps %xmm0, %xmm5
; SSE41-NEXT: andps %xmm4, %xmm5 ; SSE41-NEXT: andps %xmm4, %xmm5
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
define <8 x double> @round_v8f64(<8 x double> %x) { define <8 x double> @round_v8f64(<8 x double> %x) {
; SSE2-LABEL: round_v8f64: ; SSE2-LABEL: round_v8f64:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: subq $88, %rsp ; SSE2-NEXT: subq $88, %rsp
; SSE2-NEXT: .cfi_def_cfa_offset 96 ; SSE2-NEXT: .cfi_def_cfa_offset 96
; SSE2-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: callq _round
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _round ; SSE2-NEXT: callq _round
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _round ; SSE2-NEXT: callq _round
; SSE2-NEXT: unpcklpd (%rsp), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0]
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _round ; SSE2-NEXT: callq _round
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _round ; SSE2-NEXT: callq _round
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; SSE2-NEXT: unpcklpd (%rsp), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0]
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _round ; SSE2-NEXT: callq _round
; SSE2-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE2-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _round ; SSE2-NEXT: callq _round
; SSE2-NEXT: unpcklpd (%rsp), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0]
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _round ; SSE2-NEXT: callq _round
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 ## 16-byte Reload ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm0[0] ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _round
; SSE2-NEXT: movaps %xmm0, %xmm3
; SSE2-NEXT: unpcklpd (%rsp), %xmm3 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm3 = xmm3[0],mem[0]
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: movaps (%rsp), %xmm2 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; SSE2-NEXT: addq $88, %rsp ; SSE2-NEXT: addq $88, %rsp
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: round_v8f64: ; SSE41-LABEL: round_v8f64:
; SSE41: ## %bb.0: ; SSE41: ## %bb.0:
; SSE41-NEXT: movapd {{.*#+}} xmm4 = [-0.0E+0,-0.0E+0] ; SSE41-NEXT: movapd {{.*#+}} xmm4 = [-0.0E+0,-0.0E+0]
; SSE41-NEXT: movapd %xmm0, %xmm5 ; SSE41-NEXT: movapd %xmm0, %xmm5
; SSE41-NEXT: andpd %xmm4, %xmm5 ; SSE41-NEXT: andpd %xmm4, %xmm5
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/fp-roundeven.ll

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
ret double %a ret double %a
} }
define <4 x float> @roundeven_v4f32(<4 x float> %x) { define <4 x float> @roundeven_v4f32(<4 x float> %x) {
; SSE2-LABEL: roundeven_v4f32: ; SSE2-LABEL: roundeven_v4f32:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: subq $56, %rsp ; SSE2-NEXT: subq $56, %rsp
; SSE2-NEXT: .cfi_def_cfa_offset 64 ; SSE2-NEXT: .cfi_def_cfa_offset 64
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: unpcklps (%rsp), %xmm0 ## 16-byte Folded Reload ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: unpcklpd (%rsp), %xmm1 ## 16-byte Folded Reload ; SSE2-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0] ; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0]
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: addq $56, %rsp ; SSE2-NEXT: addq $56, %rsp
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: roundeven_v4f32: ; SSE41-LABEL: roundeven_v4f32:
; SSE41: ## %bb.0: ; SSE41: ## %bb.0:
; SSE41-NEXT: roundps $8, %xmm0, %xmm0 ; SSE41-NEXT: roundps $8, %xmm0, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: roundeven_v4f32: ; AVX-LABEL: roundeven_v4f32:
; AVX: ## %bb.0: ; AVX: ## %bb.0:
; AVX-NEXT: vroundps $8, %xmm0, %xmm0 ; AVX-NEXT: vroundps $8, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%a = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %x) %a = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %x)
ret <4 x float> %a ret <4 x float> %a
} }
define <2 x double> @roundeven_v2f64(<2 x double> %x) { define <2 x double> @roundeven_v2f64(<2 x double> %x) {
; SSE2-LABEL: roundeven_v2f64: ; SSE2-LABEL: roundeven_v2f64:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: subq $40, %rsp ; SSE2-NEXT: subq $40, %rsp
; SSE2-NEXT: .cfi_def_cfa_offset 48 ; SSE2-NEXT: .cfi_def_cfa_offset 48
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundeven ; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: unpcklpd (%rsp), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0]
; SSE2-NEXT: addq $40, %rsp ; SSE2-NEXT: addq $40, %rsp
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: roundeven_v2f64: ; SSE41-LABEL: roundeven_v2f64:
; SSE41: ## %bb.0: ; SSE41: ## %bb.0:
; SSE41-NEXT: roundpd $8, %xmm0, %xmm0 ; SSE41-NEXT: roundpd $8, %xmm0, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: roundeven_v2f64: ; AVX-LABEL: roundeven_v2f64:
; AVX: ## %bb.0: ; AVX: ## %bb.0:
; AVX-NEXT: vroundpd $8, %xmm0, %xmm0 ; AVX-NEXT: vroundpd $8, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%a = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %x) %a = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %x)
ret <2 x double> %a ret <2 x double> %a
} }
define <8 x float> @roundeven_v8f32(<8 x float> %x) { define <8 x float> @roundeven_v8f32(<8 x float> %x) {
; SSE2-LABEL: roundeven_v8f32: ; SSE2-LABEL: roundeven_v8f32:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: subq $72, %rsp ; SSE2-NEXT: subq $72, %rsp
; SSE2-NEXT: .cfi_def_cfa_offset 80 ; SSE2-NEXT: .cfi_def_cfa_offset 80
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload ; SSE2-NEXT: unpcklpd (%rsp), %xmm1 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0] ; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: unpcklps (%rsp), %xmm0 ## 16-byte Folded Reload ; SSE2-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
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} }
define <4 x double> @roundeven_v4f64(<4 x double> %x) { define <4 x double> @roundeven_v4f64(<4 x double> %x) {
; SSE2-LABEL: roundeven_v4f64: ; SSE2-LABEL: roundeven_v4f64:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: subq $56, %rsp ; SSE2-NEXT: subq $56, %rsp
; SSE2-NEXT: .cfi_def_cfa_offset 64 ; SSE2-NEXT: .cfi_def_cfa_offset 64
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundeven ; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundeven ; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; SSE2-NEXT: unpcklpd (%rsp), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0]
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundeven ; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpcklpd (%rsp), %xmm1 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0]
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: addq $56, %rsp ; SSE2-NEXT: addq $56, %rsp
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: roundeven_v4f64: ; SSE41-LABEL: roundeven_v4f64:
; SSE41: ## %bb.0: ; SSE41: ## %bb.0:
; SSE41-NEXT: roundpd $8, %xmm0, %xmm0 ; SSE41-NEXT: roundpd $8, %xmm0, %xmm0
; SSE41-NEXT: roundpd $8, %xmm1, %xmm1 ; SSE41-NEXT: roundpd $8, %xmm1, %xmm1
Show All 9 Lines
define <16 x float> @roundeven_v16f32(<16 x float> %x) { define <16 x float> @roundeven_v16f32(<16 x float> %x) {
; SSE2-LABEL: roundeven_v16f32: ; SSE2-LABEL: roundeven_v16f32:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: subq $104, %rsp ; SSE2-NEXT: subq $104, %rsp
; SSE2-NEXT: .cfi_def_cfa_offset 112 ; SSE2-NEXT: .cfi_def_cfa_offset 112
; SSE2-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload ; SSE2-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0] ; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: unpcklps (%rsp), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: unpcklpd (%rsp), %xmm1 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0]
; SSE2-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: unpcklpd (%rsp), %xmm1 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm1 = xmm1[0],mem[0]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE2-NEXT: callq _roundevenf ; SSE2-NEXT: callq _roundevenf
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 ## 16-byte Reload ; SSE2-NEXT: movaps (%rsp), %xmm3 ## 16-byte Reload
; SSE2-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
; SSE2-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 ## 16-byte Folded Reload ; SSE2-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm3 = xmm3[0],mem[0] ; SSE2-NEXT: ## xmm3 = xmm3[0],mem[0]
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: movaps (%rsp), %xmm2 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; SSE2-NEXT: addq $104, %rsp ; SSE2-NEXT: addq $104, %rsp
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: roundeven_v16f32: ; SSE41-LABEL: roundeven_v16f32:
; SSE41: ## %bb.0: ; SSE41: ## %bb.0:
; SSE41-NEXT: roundps $8, %xmm0, %xmm0 ; SSE41-NEXT: roundps $8, %xmm0, %xmm0
; SSE41-NEXT: roundps $8, %xmm1, %xmm1 ; SSE41-NEXT: roundps $8, %xmm1, %xmm1
; SSE41-NEXT: roundps $8, %xmm2, %xmm2 ; SSE41-NEXT: roundps $8, %xmm2, %xmm2
Show All 16 Lines
define <8 x double> @roundeven_v8f64(<8 x double> %x) { define <8 x double> @roundeven_v8f64(<8 x double> %x) {
; SSE2-LABEL: roundeven_v8f64: ; SSE2-LABEL: roundeven_v8f64:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: subq $88, %rsp ; SSE2-NEXT: subq $88, %rsp
; SSE2-NEXT: .cfi_def_cfa_offset 96 ; SSE2-NEXT: .cfi_def_cfa_offset 96
; SSE2-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundeven ; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundeven ; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: unpcklpd (%rsp), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0]
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps (%rsp), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundeven ; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundeven ; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill ; SSE2-NEXT: unpcklpd (%rsp), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0]
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundeven ; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE2-NEXT: movaps %xmm1, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundeven ; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: unpcklpd (%rsp), %xmm0 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm0 = xmm0[0],mem[0]
; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill ; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: callq _roundeven ; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 ## 16-byte Reload ; SSE2-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; SSE2-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm0[0] ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: callq _roundeven
; SSE2-NEXT: movaps %xmm0, %xmm3
; SSE2-NEXT: unpcklpd (%rsp), %xmm3 ## 16-byte Folded Reload
; SSE2-NEXT: ## xmm3 = xmm3[0],mem[0]
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Reload
; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 ## 16-byte Reload
; SSE2-NEXT: movaps (%rsp), %xmm2 ## 16-byte Reload ; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 ## 16-byte Reload
; SSE2-NEXT: addq $88, %rsp ; SSE2-NEXT: addq $88, %rsp
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: roundeven_v8f64: ; SSE41-LABEL: roundeven_v8f64:
; SSE41: ## %bb.0: ; SSE41: ## %bb.0:
; SSE41-NEXT: roundpd $8, %xmm0, %xmm0 ; SSE41-NEXT: roundpd $8, %xmm0, %xmm0
; SSE41-NEXT: roundpd $8, %xmm1, %xmm1 ; SSE41-NEXT: roundpd $8, %xmm1, %xmm1
; SSE41-NEXT: roundpd $8, %xmm2, %xmm2 ; SSE41-NEXT: roundpd $8, %xmm2, %xmm2
Show All 26 Lines

llvm/test/CodeGen/X86/fp128-extract.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx -enable-legalize-types-checking | FileCheck %s ; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx -enable-legalize-types-checking | FileCheck %s
; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx -enable-legalize-types-checking | FileCheck %s ; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx -enable-legalize-types-checking | FileCheck %s
; Test the softened result of extractelement op code. ; Test the softened result of extractelement op code.
define fp128 @TestExtract(<2 x double> %x) nounwind { define fp128 @TestExtract(<2 x double> %x) nounwind {
; CHECK-LABEL: TestExtract: ; CHECK-LABEL: TestExtract:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $40, %rsp ; CHECK-NEXT: subq $40, %rsp
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: callq __extenddftf2@PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq __extenddftf2@PLT ; CHECK-NEXT: callq __extenddftf2@PLT
; CHECK-NEXT: movaps %xmm0, %xmm1 ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: callq __extenddftf2@PLT
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: addq $40, %rsp ; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: jmp __multf3@PLT # TAILCALL ; CHECK-NEXT: jmp __multf3@PLT # TAILCALL
entry: entry:
; Simplified instruction pattern from the output of llvm before r289042, ; Simplified instruction pattern from the output of llvm before r289042,
; for a boost function ...::insert<...>::traverse<...>(). ; for a boost function ...::insert<...>::traverse<...>().
%a = fpext <2 x double> %x to <2 x fp128> %a = fpext <2 x double> %x to <2 x fp128>
%0 = extractelement <2 x fp128> %a, i32 0 %0 = extractelement <2 x fp128> %a, i32 0
%1 = extractelement <2 x fp128> %a, i32 1 %1 = extractelement <2 x fp128> %a, i32 1
%2 = fmul fp128 %0, %1 %2 = fmul fp128 %0, %1
ret fp128 %2 ret fp128 %2
} }

llvm/test/CodeGen/X86/fpclamptosat_vec.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; i32 saturate ; i32 saturate
define <2 x i32> @stest_f64i32(<2 x double> %x) { define <2 x i32> @stest_f64i32(<2 x double> %x) {
; CHECK-LABEL: stest_f64i32: ; CHECK-LABEL: stest_f64i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttsd2si %xmm0, %rax ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: cvttsd2si %xmm1, %rax
; CHECK-NEXT: movq %rax, %xmm1 ; CHECK-NEXT: movq %rax, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: cvttsd2si %xmm0, %rax ; CHECK-NEXT: cvttsd2si %xmm0, %rax
; CHECK-NEXT: movq %rax, %xmm0 ; CHECK-NEXT: movq %rax, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648]
; CHECK-NEXT: movdqa %xmm1, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: pxor %xmm0, %xmm2 ; CHECK-NEXT: pxor %xmm1, %xmm2
; CHECK-NEXT: movdqa {{.*#+}} xmm3 = [4294967295,4294967295] ; CHECK-NEXT: movdqa {{.*#+}} xmm3 = [4294967295,4294967295]
; CHECK-NEXT: movdqa %xmm3, %xmm4 ; CHECK-NEXT: movdqa %xmm3, %xmm4
; CHECK-NEXT: pcmpgtd %xmm2, %xmm4 ; CHECK-NEXT: pcmpgtd %xmm2, %xmm4
; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm3, %xmm2 ; CHECK-NEXT: pcmpeqd %xmm3, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-NEXT: pand %xmm5, %xmm2 ; CHECK-NEXT: pand %xmm5, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; CHECK-NEXT: por %xmm2, %xmm3 ; CHECK-NEXT: por %xmm2, %xmm3
; CHECK-NEXT: pand %xmm3, %xmm1 ; CHECK-NEXT: pand %xmm3, %xmm0
; CHECK-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 ; CHECK-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; CHECK-NEXT: por %xmm1, %xmm3 ; CHECK-NEXT: por %xmm0, %xmm3
; CHECK-NEXT: pxor %xmm3, %xmm0 ; CHECK-NEXT: pxor %xmm3, %xmm1
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [18446744069414584320,18446744069414584320] ; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [18446744069414584320,18446744069414584320]
; CHECK-NEXT: movdqa %xmm0, %xmm2 ; CHECK-NEXT: movdqa %xmm1, %xmm2
; CHECK-NEXT: pcmpgtd %xmm1, %xmm2 ; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2] ; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-NEXT: pcmpeqd %xmm0, %xmm1
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
; CHECK-NEXT: pand %xmm4, %xmm0 ; CHECK-NEXT: pand %xmm4, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm0, %xmm1
; CHECK-NEXT: pand %xmm1, %xmm3 ; CHECK-NEXT: pand %xmm1, %xmm3
; CHECK-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: por %xmm3, %xmm1 ; CHECK-NEXT: por %xmm3, %xmm1
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%conv = fptosi <2 x double> %x to <2 x i64> %conv = fptosi <2 x double> %x to <2 x i64>
%0 = icmp slt <2 x i64> %conv, <i64 2147483647, i64 2147483647> %0 = icmp slt <2 x i64> %conv, <i64 2147483647, i64 2147483647>
%spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647> %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647>
%1 = icmp sgt <2 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648> %1 = icmp sgt <2 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648>
%spec.store.select7 = select <2 x i1> %1, <2 x i64> %spec.store.select, <2 x i64> <i64 -2147483648, i64 -2147483648> %spec.store.select7 = select <2 x i1> %1, <2 x i64> %spec.store.select, <2 x i64> <i64 -2147483648, i64 -2147483648>
%conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32> %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>
ret <2 x i32> %conv6 ret <2 x i32> %conv6
} }
define <2 x i32> @utest_f64i32(<2 x double> %x) { define <2 x i32> @utest_f64i32(<2 x double> %x) {
; CHECK-LABEL: utest_f64i32: ; CHECK-LABEL: utest_f64i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: cvttsd2si %xmm1, %rax
; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: sarq $63, %rcx
; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; CHECK-NEXT: movapd %xmm0, %xmm1
; CHECK-NEXT: subsd %xmm2, %xmm1 ; CHECK-NEXT: subsd %xmm2, %xmm1
; CHECK-NEXT: cvttsd2si %xmm1, %rax ; CHECK-NEXT: cvttsd2si %xmm1, %rdx
; CHECK-NEXT: cvttsd2si %xmm0, %rcx ; CHECK-NEXT: andq %rcx, %rdx
; CHECK-NEXT: movq %rcx, %rdx ; CHECK-NEXT: orq %rax, %rdx
; CHECK-NEXT: sarq $63, %rdx
; CHECK-NEXT: andq %rax, %rdx
; CHECK-NEXT: orq %rcx, %rdx
; CHECK-NEXT: movq %rdx, %xmm1 ; CHECK-NEXT: movq %rdx, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: cvttsd2si %xmm0, %rax ; CHECK-NEXT: cvttsd2si %xmm0, %rax
; CHECK-NEXT: subsd %xmm2, %xmm0 ; CHECK-NEXT: subsd %xmm2, %xmm0
; CHECK-NEXT: cvttsd2si %xmm0, %rcx ; CHECK-NEXT: cvttsd2si %xmm0, %rcx
; CHECK-NEXT: movq %rax, %rdx ; CHECK-NEXT: movq %rax, %rdx
; CHECK-NEXT: sarq $63, %rdx ; CHECK-NEXT: sarq $63, %rdx
; CHECK-NEXT: andq %rcx, %rdx ; CHECK-NEXT: andq %rcx, %rdx
; CHECK-NEXT: orq %rax, %rdx ; CHECK-NEXT: orq %rax, %rdx
; CHECK-NEXT: movq %rdx, %xmm0 ; CHECK-NEXT: movq %rdx, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [9223372039002259456,9223372039002259456] ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [9223372039002259456,9223372039002259456]
; CHECK-NEXT: pxor %xmm1, %xmm0 ; CHECK-NEXT: pxor %xmm0, %xmm1
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259455,9223372039002259455] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259455,9223372039002259455]
; CHECK-NEXT: movdqa %xmm2, %xmm3 ; CHECK-NEXT: movdqa %xmm2, %xmm3
; CHECK-NEXT: pcmpgtd %xmm0, %xmm3 ; CHECK-NEXT: pcmpgtd %xmm1, %xmm3
; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] ; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm2, %xmm0 ; CHECK-NEXT: pcmpeqd %xmm2, %xmm1
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-NEXT: pand %xmm4, %xmm0 ; CHECK-NEXT: pand %xmm4, %xmm1
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,3,3]
; CHECK-NEXT: por %xmm0, %xmm2
; CHECK-NEXT: pand %xmm2, %xmm1
; CHECK-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; CHECK-NEXT: por %xmm1, %xmm2 ; CHECK-NEXT: por %xmm1, %xmm2
; CHECK-NEXT: pand %xmm2, %xmm0
; CHECK-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; CHECK-NEXT: por %xmm0, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%conv = fptoui <2 x double> %x to <2 x i64> %conv = fptoui <2 x double> %x to <2 x i64>
%0 = icmp ult <2 x i64> %conv, <i64 4294967295, i64 4294967295> %0 = icmp ult <2 x i64> %conv, <i64 4294967295, i64 4294967295>
%spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295> %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>
%conv6 = trunc <2 x i64> %spec.store.select to <2 x i32> %conv6 = trunc <2 x i64> %spec.store.select to <2 x i32>
ret <2 x i32> %conv6 ret <2 x i32> %conv6
} }
define <2 x i32> @ustest_f64i32(<2 x double> %x) { define <2 x i32> @ustest_f64i32(<2 x double> %x) {
; CHECK-LABEL: ustest_f64i32: ; CHECK-LABEL: ustest_f64i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttsd2si %xmm0, %rax ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: cvttsd2si %xmm1, %rax
; CHECK-NEXT: movq %rax, %xmm1 ; CHECK-NEXT: movq %rax, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: cvttsd2si %xmm0, %rax ; CHECK-NEXT: cvttsd2si %xmm0, %rax
; CHECK-NEXT: movq %rax, %xmm0 ; CHECK-NEXT: movq %rax, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648]
; CHECK-NEXT: movdqa %xmm1, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: pxor %xmm0, %xmm2 ; CHECK-NEXT: pxor %xmm1, %xmm2
; CHECK-NEXT: movdqa {{.*#+}} xmm3 = [2147483647,2147483647] ; CHECK-NEXT: movdqa {{.*#+}} xmm3 = [2147483647,2147483647]
; CHECK-NEXT: movdqa %xmm3, %xmm4 ; CHECK-NEXT: movdqa %xmm3, %xmm4
; CHECK-NEXT: pcmpgtd %xmm2, %xmm4 ; CHECK-NEXT: pcmpgtd %xmm2, %xmm4
; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm3, %xmm2 ; CHECK-NEXT: pcmpeqd %xmm3, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-NEXT: pand %xmm5, %xmm2 ; CHECK-NEXT: pand %xmm5, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; CHECK-NEXT: por %xmm2, %xmm3 ; CHECK-NEXT: por %xmm2, %xmm3
; CHECK-NEXT: pand %xmm3, %xmm1 ; CHECK-NEXT: pand %xmm3, %xmm0
; CHECK-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 ; CHECK-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; CHECK-NEXT: por %xmm1, %xmm3 ; CHECK-NEXT: por %xmm0, %xmm3
; CHECK-NEXT: movdqa %xmm3, %xmm1 ; CHECK-NEXT: movdqa %xmm3, %xmm0
; CHECK-NEXT: pxor %xmm0, %xmm1 ; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: pcmpgtd %xmm0, %xmm2 ; CHECK-NEXT: pcmpgtd %xmm1, %xmm2
; CHECK-NEXT: pcmpeqd %xmm0, %xmm1 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; CHECK-NEXT: pand %xmm2, %xmm0 ; CHECK-NEXT: pand %xmm2, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm0, %xmm1
; CHECK-NEXT: pand %xmm3, %xmm1 ; CHECK-NEXT: pand %xmm3, %xmm1
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%conv = fptosi <2 x double> %x to <2 x i64> %conv = fptosi <2 x double> %x to <2 x i64>
%0 = icmp slt <2 x i64> %conv, <i64 4294967295, i64 4294967295> %0 = icmp slt <2 x i64> %conv, <i64 4294967295, i64 4294967295>
%spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295> %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>
%1 = icmp sgt <2 x i64> %spec.store.select, zeroinitializer %1 = icmp sgt <2 x i64> %spec.store.select, zeroinitializer
%spec.store.select7 = select <2 x i1> %1, <2 x i64> %spec.store.select, <2 x i64> zeroinitializer %spec.store.select7 = select <2 x i1> %1, <2 x i64> %spec.store.select, <2 x i64> zeroinitializer
%conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32> %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>
ret <2 x i32> %conv6 ret <2 x i32> %conv6
} }
define <4 x i32> @stest_f32i32(<4 x float> %x) { define <4 x i32> @stest_f32i32(<4 x float> %x) {
; CHECK-LABEL: stest_f32i32: ; CHECK-LABEL: stest_f32i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: cvttss2si %xmm1, %rax
; CHECK-NEXT: movq %rax, %xmm2
; CHECK-NEXT: movaps %xmm0, %xmm1 ; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3] ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
; CHECK-NEXT: cvttss2si %xmm1, %rax ; CHECK-NEXT: cvttss2si %xmm1, %rax
; CHECK-NEXT: movq %rax, %xmm1 ; CHECK-NEXT: movq %rax, %xmm1
; CHECK-NEXT: movaps %xmm0, %xmm2
; CHECK-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; CHECK-NEXT: cvttss2si %xmm2, %rax
; CHECK-NEXT: movq %rax, %xmm2
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; CHECK-NEXT: cvttss2si %xmm0, %rax ; CHECK-NEXT: cvttss2si %xmm0, %rax
; CHECK-NEXT: movq %rax, %xmm4 ; CHECK-NEXT: movq %rax, %xmm4
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: cvttss2si %xmm0, %rax ; CHECK-NEXT: cvttss2si %xmm0, %rax
; CHECK-NEXT: movq %rax, %xmm0 ; CHECK-NEXT: movq %rax, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm0[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm0[0]
; CHECK-NEXT: movdqa {{.*#+}} xmm8 = [2147483647,2147483647] ; CHECK-NEXT: movdqa {{.*#+}} xmm8 = [2147483647,2147483647]
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; CHECK-NEXT: subss %xmm2, %xmm3 ; CHECK-NEXT: subss %xmm2, %xmm3
; CHECK-NEXT: cvttss2si %xmm3, %rcx ; CHECK-NEXT: cvttss2si %xmm3, %rcx
; CHECK-NEXT: movq %rax, %rdx ; CHECK-NEXT: movq %rax, %rdx
; CHECK-NEXT: sarq $63, %rdx ; CHECK-NEXT: sarq $63, %rdx
; CHECK-NEXT: andq %rcx, %rdx ; CHECK-NEXT: andq %rcx, %rdx
; CHECK-NEXT: orq %rax, %rdx ; CHECK-NEXT: orq %rax, %rdx
; CHECK-NEXT: movq %rdx, %xmm3 ; CHECK-NEXT: movq %rdx, %xmm3
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
; CHECK-NEXT: movaps %xmm0, %xmm3 ; CHECK-NEXT: xorps %xmm3, %xmm3
; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3],xmm0[3,3] ; CHECK-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; CHECK-NEXT: cvttss2si %xmm3, %rax ; CHECK-NEXT: cvttss2si %xmm3, %rax
; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: sarq $63, %rcx
; CHECK-NEXT: subss %xmm2, %xmm3 ; CHECK-NEXT: subss %xmm2, %xmm3
; CHECK-NEXT: cvttss2si %xmm3, %rcx ; CHECK-NEXT: cvttss2si %xmm3, %rdx
; CHECK-NEXT: movq %rax, %rdx
; CHECK-NEXT: sarq $63, %rdx
; CHECK-NEXT: andq %rcx, %rdx ; CHECK-NEXT: andq %rcx, %rdx
; CHECK-NEXT: orq %rax, %rdx ; CHECK-NEXT: orq %rax, %rdx
; CHECK-NEXT: movq %rdx, %xmm3 ; CHECK-NEXT: movq %rdx, %xmm3
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; CHECK-NEXT: cvttss2si %xmm0, %rax ; CHECK-NEXT: cvttss2si %xmm0, %rax
; CHECK-NEXT: subss %xmm2, %xmm0 ; CHECK-NEXT: subss %xmm2, %xmm0
; CHECK-NEXT: cvttss2si %xmm0, %rcx ; CHECK-NEXT: cvttss2si %xmm0, %rcx
; CHECK-NEXT: movq %rax, %rdx ; CHECK-NEXT: movq %rax, %rdx
; CHECK-NEXT: sarq $63, %rdx ; CHECK-NEXT: sarq $63, %rdx
; CHECK-NEXT: andq %rcx, %rdx ; CHECK-NEXT: andq %rcx, %rdx
; CHECK-NEXT: orq %rax, %rdx ; CHECK-NEXT: orq %rax, %rdx
; CHECK-NEXT: movq %rdx, %xmm0 ; CHECK-NEXT: movq %rdx, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0]
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [4294967295,4294967295] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [4294967295,4294967295]
; CHECK-NEXT: movdqa {{.*#+}} xmm3 = [9223372039002259456,9223372039002259456] ; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [9223372039002259456,9223372039002259456]
; CHECK-NEXT: movdqa %xmm0, %xmm4 ; CHECK-NEXT: movdqa %xmm3, %xmm4
; CHECK-NEXT: pxor %xmm3, %xmm4 ; CHECK-NEXT: pxor %xmm0, %xmm4
; CHECK-NEXT: movdqa {{.*#+}} xmm5 = [9223372039002259455,9223372039002259455] ; CHECK-NEXT: movdqa {{.*#+}} xmm5 = [9223372039002259455,9223372039002259455]
; CHECK-NEXT: movdqa %xmm5, %xmm6 ; CHECK-NEXT: movdqa %xmm5, %xmm6
; CHECK-NEXT: pcmpgtd %xmm4, %xmm6 ; CHECK-NEXT: pcmpgtd %xmm4, %xmm6
; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] ; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm5, %xmm4 ; CHECK-NEXT: pcmpeqd %xmm5, %xmm4
; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; CHECK-NEXT: pand %xmm7, %xmm4 ; CHECK-NEXT: pand %xmm7, %xmm4
; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; CHECK-NEXT: por %xmm4, %xmm6 ; CHECK-NEXT: por %xmm4, %xmm6
; CHECK-NEXT: pand %xmm6, %xmm0 ; CHECK-NEXT: pand %xmm6, %xmm3
; CHECK-NEXT: pandn %xmm2, %xmm6 ; CHECK-NEXT: pandn %xmm2, %xmm6
; CHECK-NEXT: por %xmm0, %xmm6 ; CHECK-NEXT: por %xmm3, %xmm6
; CHECK-NEXT: pxor %xmm1, %xmm3 ; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm5, %xmm0 ; CHECK-NEXT: movdqa %xmm5, %xmm3
; CHECK-NEXT: pcmpgtd %xmm3, %xmm0 ; CHECK-NEXT: pcmpgtd %xmm0, %xmm3
; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,0,2,2] ; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm5, %xmm3 ; CHECK-NEXT: pcmpeqd %xmm5, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm0[1,1,3,3]
; CHECK-NEXT: pand %xmm4, %xmm3 ; CHECK-NEXT: pand %xmm4, %xmm5
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3]
; CHECK-NEXT: por %xmm3, %xmm0 ; CHECK-NEXT: por %xmm5, %xmm0
; CHECK-NEXT: pand %xmm0, %xmm1 ; CHECK-NEXT: pand %xmm0, %xmm1
; CHECK-NEXT: pandn %xmm2, %xmm0 ; CHECK-NEXT: pandn %xmm2, %xmm0
; CHECK-NEXT: por %xmm1, %xmm0 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm6[0,2] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm6[0,2]
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%conv = fptoui <4 x float> %x to <4 x i64> %conv = fptoui <4 x float> %x to <4 x i64>
%0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> %0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
%spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
%conv6 = trunc <4 x i64> %spec.store.select to <4 x i32> %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>
ret <4 x i32> %conv6 ret <4 x i32> %conv6
} }
define <4 x i32> @ustest_f32i32(<4 x float> %x) { define <4 x i32> @ustest_f32i32(<4 x float> %x) {
; CHECK-LABEL: ustest_f32i32: ; CHECK-LABEL: ustest_f32i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: cvttss2si %xmm1, %rax
; CHECK-NEXT: movq %rax, %xmm2
; CHECK-NEXT: movaps %xmm0, %xmm1 ; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3] ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
; CHECK-NEXT: cvttss2si %xmm1, %rax ; CHECK-NEXT: cvttss2si %xmm1, %rax
; CHECK-NEXT: movq %rax, %xmm1 ; CHECK-NEXT: movq %rax, %xmm1
; CHECK-NEXT: movaps %xmm0, %xmm2
; CHECK-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; CHECK-NEXT: cvttss2si %xmm2, %rax
; CHECK-NEXT: movq %rax, %xmm2
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; CHECK-NEXT: cvttss2si %xmm0, %rax ; CHECK-NEXT: cvttss2si %xmm0, %rax
; CHECK-NEXT: movq %rax, %xmm4 ; CHECK-NEXT: movq %rax, %xmm4
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: cvttss2si %xmm0, %rax ; CHECK-NEXT: cvttss2si %xmm0, %rax
; CHECK-NEXT: movq %rax, %xmm0 ; CHECK-NEXT: movq %rax, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm0[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm0[0]
; CHECK-NEXT: movdqa {{.*#+}} xmm8 = [4294967295,4294967295] ; CHECK-NEXT: movdqa {{.*#+}} xmm8 = [4294967295,4294967295]
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; CHECK-NEXT: .cfi_def_cfa_offset 24 ; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: subq $24, %rsp ; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset %rbx, -24 ; CHECK-NEXT: .cfi_offset %rbx, -24
; CHECK-NEXT: .cfi_offset %r14, -16 ; CHECK-NEXT: .cfi_offset %r14, -16
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq __fixdfti@PLT ; CHECK-NEXT: callq __fixdfti@PLT
; CHECK-NEXT: movq %rax, %r14 ; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: movq %rdx, %rbx ; CHECK-NEXT: movq %rdx, %r14
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: callq __fixdfti@PLT ; CHECK-NEXT: callq __fixdfti@PLT
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF ; CHECK-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
; CHECK-NEXT: cmpq %rsi, %rbx
; CHECK-NEXT: movq %r14, %rdi
; CHECK-NEXT: sbbq $0, %rdi
; CHECK-NEXT: cmovgeq %rcx, %r14
; CHECK-NEXT: cmovgeq %rsi, %rbx
; CHECK-NEXT: cmpq %rsi, %rax ; CHECK-NEXT: cmpq %rsi, %rax
; CHECK-NEXT: movq %rdx, %rdi ; CHECK-NEXT: movq %rdx, %rdi
; CHECK-NEXT: sbbq $0, %rdi ; CHECK-NEXT: sbbq $0, %rdi
; CHECK-NEXT: cmovgeq %rcx, %rdx ; CHECK-NEXT: cmovlq %rdx, %rcx
; CHECK-NEXT: cmovgeq %rsi, %rax ; CHECK-NEXT: cmovlq %rax, %rsi
; CHECK-NEXT: cmpq %rsi, %r14 ; CHECK-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
; CHECK-NEXT: movq %rbx, %rdi ; CHECK-NEXT: cmpq %rbx, %rax
; CHECK-NEXT: sbbq $0, %rdi ; CHECK-NEXT: movq $-1, %rdx
; CHECK-NEXT: cmovlq %rbx, %rcx
; CHECK-NEXT: cmovlq %r14, %rsi
; CHECK-NEXT: movabsq $-9223372036854775808, %r8 # imm = 0x8000000000000000
; CHECK-NEXT: cmpq %rsi, %r8
; CHECK-NEXT: movq $-1, %rbx
; CHECK-NEXT: movq $-1, %rdi ; CHECK-NEXT: movq $-1, %rdi
; CHECK-NEXT: sbbq %rcx, %rdi ; CHECK-NEXT: sbbq %r14, %rdi
; CHECK-NEXT: cmovgeq %r8, %rsi ; CHECK-NEXT: cmovgeq %rax, %rbx
; CHECK-NEXT: cmpq %rax, %r8 ; CHECK-NEXT: cmpq %rsi, %rax
; CHECK-NEXT: sbbq %rdx, %rbx ; CHECK-NEXT: sbbq %rcx, %rdx
; CHECK-NEXT: cmovgeq %r8, %rax ; CHECK-NEXT: cmovgeq %rax, %rsi
; CHECK-NEXT: movq %rax, %xmm0 ; CHECK-NEXT: movq %rbx, %xmm1
; CHECK-NEXT: movq %rsi, %xmm1 ; CHECK-NEXT: movq %rsi, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 24 ; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: popq %r14 ; CHECK-NEXT: popq %r14
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
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; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 24 ; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: subq $24, %rsp ; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset %rbx, -24 ; CHECK-NEXT: .cfi_offset %rbx, -24
; CHECK-NEXT: .cfi_offset %r14, -16 ; CHECK-NEXT: .cfi_offset %r14, -16
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq __fixunsdfti@PLT ; CHECK-NEXT: callq __fixunsdfti@PLT
; CHECK-NEXT: movq %rax, %rbx ; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: movq %rdx, %r14 ; CHECK-NEXT: movq %rdx, %r14
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq __fixunsdfti@PLT ; CHECK-NEXT: callq __fixunsdfti@PLT
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: cmovneq %rcx, %rax
; CHECK-NEXT: testq %r14, %r14 ; CHECK-NEXT: testq %r14, %r14
; CHECK-NEXT: cmovneq %rcx, %rbx ; CHECK-NEXT: cmovneq %rcx, %rbx
; CHECK-NEXT: movq %rbx, %xmm0 ; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: movq %rax, %xmm1 ; CHECK-NEXT: cmovneq %rcx, %rax
; CHECK-NEXT: movq %rax, %xmm0
; CHECK-NEXT: movq %rbx, %xmm1
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 24 ; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: popq %r14 ; CHECK-NEXT: popq %r14
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
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; i32 saturate ; i32 saturate
define <2 x i32> @stest_f64i32_mm(<2 x double> %x) { define <2 x i32> @stest_f64i32_mm(<2 x double> %x) {
; CHECK-LABEL: stest_f64i32_mm: ; CHECK-LABEL: stest_f64i32_mm:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttsd2si %xmm0, %rax ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: cvttsd2si %xmm1, %rax
; CHECK-NEXT: movq %rax, %xmm1 ; CHECK-NEXT: movq %rax, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: cvttsd2si %xmm0, %rax ; CHECK-NEXT: cvttsd2si %xmm0, %rax
; CHECK-NEXT: movq %rax, %xmm0 ; CHECK-NEXT: movq %rax, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648]
; CHECK-NEXT: movdqa %xmm1, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: pxor %xmm0, %xmm2 ; CHECK-NEXT: pxor %xmm1, %xmm2
; CHECK-NEXT: movdqa {{.*#+}} xmm3 = [4294967295,4294967295] ; CHECK-NEXT: movdqa {{.*#+}} xmm3 = [4294967295,4294967295]
; CHECK-NEXT: movdqa %xmm3, %xmm4 ; CHECK-NEXT: movdqa %xmm3, %xmm4
; CHECK-NEXT: pcmpgtd %xmm2, %xmm4 ; CHECK-NEXT: pcmpgtd %xmm2, %xmm4
; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm3, %xmm2 ; CHECK-NEXT: pcmpeqd %xmm3, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-NEXT: pand %xmm5, %xmm2 ; CHECK-NEXT: pand %xmm5, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; CHECK-NEXT: por %xmm2, %xmm3 ; CHECK-NEXT: por %xmm2, %xmm3
; CHECK-NEXT: pand %xmm3, %xmm1 ; CHECK-NEXT: pand %xmm3, %xmm0
; CHECK-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 ; CHECK-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; CHECK-NEXT: por %xmm1, %xmm3 ; CHECK-NEXT: por %xmm0, %xmm3
; CHECK-NEXT: pxor %xmm3, %xmm0 ; CHECK-NEXT: pxor %xmm3, %xmm1
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [18446744069414584320,18446744069414584320] ; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [18446744069414584320,18446744069414584320]
; CHECK-NEXT: movdqa %xmm0, %xmm2 ; CHECK-NEXT: movdqa %xmm1, %xmm2
; CHECK-NEXT: pcmpgtd %xmm1, %xmm2 ; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2] ; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-NEXT: pcmpeqd %xmm0, %xmm1
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
; CHECK-NEXT: pand %xmm4, %xmm0 ; CHECK-NEXT: pand %xmm4, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm0, %xmm1
; CHECK-NEXT: pand %xmm1, %xmm3 ; CHECK-NEXT: pand %xmm1, %xmm3
; CHECK-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: por %xmm3, %xmm1 ; CHECK-NEXT: por %xmm3, %xmm1
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%conv = fptosi <2 x double> %x to <2 x i64> %conv = fptosi <2 x double> %x to <2 x i64>
%spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647>) %spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647>)
%spec.store.select7 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %spec.store.select, <2 x i64> <i64 -2147483648, i64 -2147483648>) %spec.store.select7 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %spec.store.select, <2 x i64> <i64 -2147483648, i64 -2147483648>)
%conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32> %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>
ret <2 x i32> %conv6 ret <2 x i32> %conv6
} }
define <2 x i32> @utest_f64i32_mm(<2 x double> %x) { define <2 x i32> @utest_f64i32_mm(<2 x double> %x) {
; CHECK-LABEL: utest_f64i32_mm: ; CHECK-LABEL: utest_f64i32_mm:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: cvttsd2si %xmm1, %rax
; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: sarq $63, %rcx
; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; CHECK-NEXT: movapd %xmm0, %xmm1
; CHECK-NEXT: subsd %xmm2, %xmm1 ; CHECK-NEXT: subsd %xmm2, %xmm1
; CHECK-NEXT: cvttsd2si %xmm1, %rax ; CHECK-NEXT: cvttsd2si %xmm1, %rdx
; CHECK-NEXT: cvttsd2si %xmm0, %rcx ; CHECK-NEXT: andq %rcx, %rdx
; CHECK-NEXT: movq %rcx, %rdx ; CHECK-NEXT: orq %rax, %rdx
; CHECK-NEXT: sarq $63, %rdx
; CHECK-NEXT: andq %rax, %rdx
; CHECK-NEXT: orq %rcx, %rdx
; CHECK-NEXT: movq %rdx, %xmm1 ; CHECK-NEXT: movq %rdx, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: cvttsd2si %xmm0, %rax ; CHECK-NEXT: cvttsd2si %xmm0, %rax
; CHECK-NEXT: subsd %xmm2, %xmm0 ; CHECK-NEXT: subsd %xmm2, %xmm0
; CHECK-NEXT: cvttsd2si %xmm0, %rcx ; CHECK-NEXT: cvttsd2si %xmm0, %rcx
; CHECK-NEXT: movq %rax, %rdx ; CHECK-NEXT: movq %rax, %rdx
; CHECK-NEXT: sarq $63, %rdx ; CHECK-NEXT: sarq $63, %rdx
; CHECK-NEXT: andq %rcx, %rdx ; CHECK-NEXT: andq %rcx, %rdx
; CHECK-NEXT: orq %rax, %rdx ; CHECK-NEXT: orq %rax, %rdx
; CHECK-NEXT: movq %rdx, %xmm0 ; CHECK-NEXT: movq %rdx, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [9223372039002259456,9223372039002259456] ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [9223372039002259456,9223372039002259456]
; CHECK-NEXT: pxor %xmm1, %xmm0 ; CHECK-NEXT: pxor %xmm0, %xmm1
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259455,9223372039002259455] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259455,9223372039002259455]
; CHECK-NEXT: movdqa %xmm2, %xmm3 ; CHECK-NEXT: movdqa %xmm2, %xmm3
; CHECK-NEXT: pcmpgtd %xmm0, %xmm3 ; CHECK-NEXT: pcmpgtd %xmm1, %xmm3
; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] ; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm2, %xmm0 ; CHECK-NEXT: pcmpeqd %xmm2, %xmm1
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-NEXT: pand %xmm4, %xmm0 ; CHECK-NEXT: pand %xmm4, %xmm1
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,3,3]
; CHECK-NEXT: por %xmm0, %xmm2
; CHECK-NEXT: pand %xmm2, %xmm1
; CHECK-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; CHECK-NEXT: por %xmm1, %xmm2 ; CHECK-NEXT: por %xmm1, %xmm2
; CHECK-NEXT: pand %xmm2, %xmm0
; CHECK-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; CHECK-NEXT: por %xmm0, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%conv = fptoui <2 x double> %x to <2 x i64> %conv = fptoui <2 x double> %x to <2 x i64>
%spec.store.select = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>) %spec.store.select = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>)
%conv6 = trunc <2 x i64> %spec.store.select to <2 x i32> %conv6 = trunc <2 x i64> %spec.store.select to <2 x i32>
ret <2 x i32> %conv6 ret <2 x i32> %conv6
} }
define <2 x i32> @ustest_f64i32_mm(<2 x double> %x) { define <2 x i32> @ustest_f64i32_mm(<2 x double> %x) {
; CHECK-LABEL: ustest_f64i32_mm: ; CHECK-LABEL: ustest_f64i32_mm:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttsd2si %xmm0, %rax ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: cvttsd2si %xmm1, %rax
; CHECK-NEXT: movq %rax, %xmm1 ; CHECK-NEXT: movq %rax, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: cvttsd2si %xmm0, %rax ; CHECK-NEXT: cvttsd2si %xmm0, %rax
; CHECK-NEXT: movq %rax, %xmm0 ; CHECK-NEXT: movq %rax, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648]
; CHECK-NEXT: movdqa %xmm1, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: pxor %xmm0, %xmm2 ; CHECK-NEXT: pxor %xmm1, %xmm2
; CHECK-NEXT: movdqa {{.*#+}} xmm3 = [2147483647,2147483647] ; CHECK-NEXT: movdqa {{.*#+}} xmm3 = [2147483647,2147483647]
; CHECK-NEXT: movdqa %xmm3, %xmm4 ; CHECK-NEXT: movdqa %xmm3, %xmm4
; CHECK-NEXT: pcmpgtd %xmm2, %xmm4 ; CHECK-NEXT: pcmpgtd %xmm2, %xmm4
; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm3, %xmm2 ; CHECK-NEXT: pcmpeqd %xmm3, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-NEXT: pand %xmm5, %xmm2 ; CHECK-NEXT: pand %xmm5, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; CHECK-NEXT: por %xmm2, %xmm3 ; CHECK-NEXT: por %xmm2, %xmm3
; CHECK-NEXT: pand %xmm3, %xmm1 ; CHECK-NEXT: pand %xmm3, %xmm0
; CHECK-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 ; CHECK-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; CHECK-NEXT: por %xmm1, %xmm3 ; CHECK-NEXT: por %xmm0, %xmm3
; CHECK-NEXT: movdqa %xmm3, %xmm1 ; CHECK-NEXT: movdqa %xmm3, %xmm0
; CHECK-NEXT: pxor %xmm0, %xmm1 ; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: pcmpgtd %xmm0, %xmm2 ; CHECK-NEXT: pcmpgtd %xmm1, %xmm2
; CHECK-NEXT: pcmpeqd %xmm0, %xmm1 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; CHECK-NEXT: pand %xmm2, %xmm0 ; CHECK-NEXT: pand %xmm2, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm0, %xmm1
; CHECK-NEXT: pand %xmm3, %xmm1 ; CHECK-NEXT: pand %xmm3, %xmm1
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%conv = fptosi <2 x double> %x to <2 x i64> %conv = fptosi <2 x double> %x to <2 x i64>
%spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>) %spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>)
%spec.store.select7 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %spec.store.select, <2 x i64> zeroinitializer) %spec.store.select7 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %spec.store.select, <2 x i64> zeroinitializer)
%conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32> %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>
ret <2 x i32> %conv6 ret <2 x i32> %conv6
} }
define <4 x i32> @stest_f32i32_mm(<4 x float> %x) { define <4 x i32> @stest_f32i32_mm(<4 x float> %x) {
; CHECK-LABEL: stest_f32i32_mm: ; CHECK-LABEL: stest_f32i32_mm:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: cvttss2si %xmm1, %rax
; CHECK-NEXT: movq %rax, %xmm2
; CHECK-NEXT: movaps %xmm0, %xmm1 ; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3] ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
; CHECK-NEXT: cvttss2si %xmm1, %rax ; CHECK-NEXT: cvttss2si %xmm1, %rax
; CHECK-NEXT: movq %rax, %xmm1 ; CHECK-NEXT: movq %rax, %xmm1
; CHECK-NEXT: movaps %xmm0, %xmm2
; CHECK-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; CHECK-NEXT: cvttss2si %xmm2, %rax
; CHECK-NEXT: movq %rax, %xmm2
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; CHECK-NEXT: cvttss2si %xmm0, %rax ; CHECK-NEXT: cvttss2si %xmm0, %rax
; CHECK-NEXT: movq %rax, %xmm3 ; CHECK-NEXT: movq %rax, %xmm3
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: cvttss2si %xmm0, %rax ; CHECK-NEXT: cvttss2si %xmm0, %rax
; CHECK-NEXT: movq %rax, %xmm0 ; CHECK-NEXT: movq %rax, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0]
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
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; CHECK-NEXT: subss %xmm2, %xmm3 ; CHECK-NEXT: subss %xmm2, %xmm3
; CHECK-NEXT: cvttss2si %xmm3, %rcx ; CHECK-NEXT: cvttss2si %xmm3, %rcx
; CHECK-NEXT: movq %rax, %rdx ; CHECK-NEXT: movq %rax, %rdx
; CHECK-NEXT: sarq $63, %rdx ; CHECK-NEXT: sarq $63, %rdx
; CHECK-NEXT: andq %rcx, %rdx ; CHECK-NEXT: andq %rcx, %rdx
; CHECK-NEXT: orq %rax, %rdx ; CHECK-NEXT: orq %rax, %rdx
; CHECK-NEXT: movq %rdx, %xmm3 ; CHECK-NEXT: movq %rdx, %xmm3
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
; CHECK-NEXT: movaps %xmm0, %xmm3 ; CHECK-NEXT: xorps %xmm3, %xmm3
; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3],xmm0[3,3] ; CHECK-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; CHECK-NEXT: cvttss2si %xmm3, %rax ; CHECK-NEXT: cvttss2si %xmm3, %rax
; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: sarq $63, %rcx
; CHECK-NEXT: subss %xmm2, %xmm3 ; CHECK-NEXT: subss %xmm2, %xmm3
; CHECK-NEXT: cvttss2si %xmm3, %rcx ; CHECK-NEXT: cvttss2si %xmm3, %rdx
; CHECK-NEXT: movq %rax, %rdx
; CHECK-NEXT: sarq $63, %rdx
; CHECK-NEXT: andq %rcx, %rdx ; CHECK-NEXT: andq %rcx, %rdx
; CHECK-NEXT: orq %rax, %rdx ; CHECK-NEXT: orq %rax, %rdx
; CHECK-NEXT: movq %rdx, %xmm3 ; CHECK-NEXT: movq %rdx, %xmm3
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; CHECK-NEXT: cvttss2si %xmm0, %rax ; CHECK-NEXT: cvttss2si %xmm0, %rax
; CHECK-NEXT: subss %xmm2, %xmm0 ; CHECK-NEXT: subss %xmm2, %xmm0
; CHECK-NEXT: cvttss2si %xmm0, %rcx ; CHECK-NEXT: cvttss2si %xmm0, %rcx
; CHECK-NEXT: movq %rax, %rdx ; CHECK-NEXT: movq %rax, %rdx
; CHECK-NEXT: sarq $63, %rdx ; CHECK-NEXT: sarq $63, %rdx
; CHECK-NEXT: andq %rcx, %rdx ; CHECK-NEXT: andq %rcx, %rdx
; CHECK-NEXT: orq %rax, %rdx ; CHECK-NEXT: orq %rax, %rdx
; CHECK-NEXT: movq %rdx, %xmm0 ; CHECK-NEXT: movq %rdx, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0]
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] ; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [9223372039002259456,9223372039002259456]
; CHECK-NEXT: movdqa %xmm0, %xmm3 ; CHECK-NEXT: movdqa %xmm3, %xmm2
; CHECK-NEXT: pxor %xmm2, %xmm3 ; CHECK-NEXT: pxor %xmm0, %xmm2
; CHECK-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259455,9223372039002259455] ; CHECK-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259455,9223372039002259455]
; CHECK-NEXT: movdqa %xmm4, %xmm5 ; CHECK-NEXT: movdqa %xmm4, %xmm5
; CHECK-NEXT: pcmpgtd %xmm3, %xmm5 ; CHECK-NEXT: pcmpgtd %xmm2, %xmm5
; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] ; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm4, %xmm3
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; CHECK-NEXT: pand %xmm6, %xmm3
; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; CHECK-NEXT: por %xmm3, %xmm5
; CHECK-NEXT: movdqa {{.*#+}} xmm3 = [4294967295,4294967295]
; CHECK-NEXT: pand %xmm5, %xmm0
; CHECK-NEXT: pandn %xmm3, %xmm5
; CHECK-NEXT: por %xmm0, %xmm5
; CHECK-NEXT: pxor %xmm1, %xmm2
; CHECK-NEXT: movdqa %xmm4, %xmm0
; CHECK-NEXT: pcmpgtd %xmm2, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm0[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm4, %xmm2 ; CHECK-NEXT: pcmpeqd %xmm4, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-NEXT: pand %xmm6, %xmm2 ; CHECK-NEXT: pand %xmm6, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; CHECK-NEXT: por %xmm2, %xmm0 ; CHECK-NEXT: por %xmm2, %xmm5
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [4294967295,4294967295]
; CHECK-NEXT: pand %xmm5, %xmm3
; CHECK-NEXT: pandn %xmm2, %xmm5
; CHECK-NEXT: por %xmm3, %xmm5
; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm4, %xmm3
; CHECK-NEXT: pcmpgtd %xmm0, %xmm3
; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm3[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm4, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
; CHECK-NEXT: pand %xmm6, %xmm4
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3]
; CHECK-NEXT: por %xmm4, %xmm0
; CHECK-NEXT: pand %xmm0, %xmm1 ; CHECK-NEXT: pand %xmm0, %xmm1
; CHECK-NEXT: pandn %xmm3, %xmm0 ; CHECK-NEXT: pandn %xmm2, %xmm0
; CHECK-NEXT: por %xmm1, %xmm0 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm5[0,2] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm5[0,2]
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%conv = fptoui <4 x float> %x to <4 x i64> %conv = fptoui <4 x float> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>) %spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
%conv6 = trunc <4 x i64> %spec.store.select to <4 x i32> %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>
ret <4 x i32> %conv6 ret <4 x i32> %conv6
} }
define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) { define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) {
; CHECK-LABEL: ustest_f32i32_mm: ; CHECK-LABEL: ustest_f32i32_mm:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: cvttss2si %xmm1, %rax
; CHECK-NEXT: movq %rax, %xmm2
; CHECK-NEXT: movaps %xmm0, %xmm1 ; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3] ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
; CHECK-NEXT: cvttss2si %xmm1, %rax ; CHECK-NEXT: cvttss2si %xmm1, %rax
; CHECK-NEXT: movq %rax, %xmm1 ; CHECK-NEXT: movq %rax, %xmm1
; CHECK-NEXT: movaps %xmm0, %xmm2
; CHECK-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; CHECK-NEXT: cvttss2si %xmm2, %rax
; CHECK-NEXT: movq %rax, %xmm2
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; CHECK-NEXT: cvttss2si %xmm0, %rax ; CHECK-NEXT: cvttss2si %xmm0, %rax
; CHECK-NEXT: movq %rax, %xmm3 ; CHECK-NEXT: movq %rax, %xmm3
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: cvttss2si %xmm0, %rax ; CHECK-NEXT: cvttss2si %xmm0, %rax
; CHECK-NEXT: movq %rax, %xmm0 ; CHECK-NEXT: movq %rax, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0]
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
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; CHECK-NEXT: cmovnsq %rdi, %rdx ; CHECK-NEXT: cmovnsq %rdi, %rdx
; CHECK-NEXT: cmpq %rcx, %rbx ; CHECK-NEXT: cmpq %rcx, %rbx
; CHECK-NEXT: movq %rcx, %rsi ; CHECK-NEXT: movq %rcx, %rsi
; CHECK-NEXT: cmovbq %rbx, %rsi ; CHECK-NEXT: cmovbq %rbx, %rsi
; CHECK-NEXT: testq %r14, %r14 ; CHECK-NEXT: testq %r14, %r14
; CHECK-NEXT: cmovsq %rbx, %rcx ; CHECK-NEXT: cmovsq %rbx, %rcx
; CHECK-NEXT: cmoveq %rsi, %rcx ; CHECK-NEXT: cmoveq %rsi, %rcx
; CHECK-NEXT: cmovsq %r14, %rdi ; CHECK-NEXT: cmovsq %r14, %rdi
; CHECK-NEXT: testq %rdi, %rdi
; CHECK-NEXT: movabsq $-9223372036854775808, %rbx # imm = 0x8000000000000000 ; CHECK-NEXT: movabsq $-9223372036854775808, %rbx # imm = 0x8000000000000000
; CHECK-NEXT: movq %rbx, %rsi
; CHECK-NEXT: cmovnsq %rcx, %rsi
; CHECK-NEXT: cmpq %rbx, %rcx ; CHECK-NEXT: cmpq %rbx, %rcx
; CHECK-NEXT: cmovbeq %rbx, %rcx ; CHECK-NEXT: movq %rbx, %rsi
; CHECK-NEXT: cmovaq %rcx, %rsi
; CHECK-NEXT: testq %rdi, %rdi
; CHECK-NEXT: cmovsq %rbx, %rcx
; CHECK-NEXT: cmpq $-1, %rdi ; CHECK-NEXT: cmpq $-1, %rdi
; CHECK-NEXT: cmovneq %rsi, %rcx ; CHECK-NEXT: cmoveq %rsi, %rcx
; CHECK-NEXT: testq %rdx, %rdx ; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: movq %rbx, %rsi ; CHECK-NEXT: movq %rbx, %rsi
; CHECK-NEXT: cmovnsq %rax, %rsi ; CHECK-NEXT: cmovnsq %rax, %rsi
; CHECK-NEXT: cmpq %rbx, %rax ; CHECK-NEXT: cmpq %rbx, %rax
; CHECK-NEXT: cmovbeq %rbx, %rax ; CHECK-NEXT: cmovbeq %rbx, %rax
; CHECK-NEXT: cmpq $-1, %rdx ; CHECK-NEXT: cmpq $-1, %rdx
; CHECK-NEXT: cmovneq %rsi, %rax ; CHECK-NEXT: cmovneq %rsi, %rax
; CHECK-NEXT: movq %rax, %xmm0 ; CHECK-NEXT: movq %rax, %xmm0
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; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 24 ; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: subq $24, %rsp ; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset %rbx, -24 ; CHECK-NEXT: .cfi_offset %rbx, -24
; CHECK-NEXT: .cfi_offset %r14, -16 ; CHECK-NEXT: .cfi_offset %r14, -16
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq __fixunsdfti@PLT ; CHECK-NEXT: callq __fixunsdfti@PLT
; CHECK-NEXT: movq %rax, %rbx ; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: movq %rdx, %r14 ; CHECK-NEXT: movq %rdx, %r14
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq __fixunsdfti@PLT ; CHECK-NEXT: callq __fixunsdfti@PLT
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: cmovneq %rcx, %rax
; CHECK-NEXT: cmpq $1, %rdx
; CHECK-NEXT: cmoveq %rcx, %rax
; CHECK-NEXT: testq %r14, %r14 ; CHECK-NEXT: testq %r14, %r14
; CHECK-NEXT: cmovneq %rcx, %rbx ; CHECK-NEXT: cmovneq %rcx, %rbx
; CHECK-NEXT: cmpq $1, %r14 ; CHECK-NEXT: cmpq $1, %r14
; CHECK-NEXT: cmoveq %rcx, %rbx ; CHECK-NEXT: cmoveq %rcx, %rbx
; CHECK-NEXT: movq %rbx, %xmm0 ; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: movq %rax, %xmm1 ; CHECK-NEXT: cmovneq %rcx, %rax
; CHECK-NEXT: cmpq $1, %rdx
; CHECK-NEXT: cmoveq %rcx, %rax
; CHECK-NEXT: movq %rax, %xmm0
; CHECK-NEXT: movq %rbx, %xmm1
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 24 ; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: popq %r14 ; CHECK-NEXT: popq %r14
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
▲ Show 20 Lines • Show All 415 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll

Show All 9 Lines
declare <4 x i16> @llvm.fptosi.sat.v4i16.v4f32(<4 x float>) declare <4 x i16> @llvm.fptosi.sat.v4i16.v4f32(<4 x float>)
declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float>) declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float>)
declare <4 x i64> @llvm.fptosi.sat.v4i64.v4f32(<4 x float>) declare <4 x i64> @llvm.fptosi.sat.v4i64.v4f32(<4 x float>)
declare <4 x i128> @llvm.fptosi.sat.v4i128.v4f32(<4 x float>) declare <4 x i128> @llvm.fptosi.sat.v4i128.v4f32(<4 x float>)
define <4 x i1> @test_signed_v4i1_v4f32(<4 x float> %f) nounwind { define <4 x i1> @test_signed_v4i1_v4f32(<4 x float> %f) nounwind {
; CHECK-LABEL: test_signed_v4i1_v4f32: ; CHECK-LABEL: test_signed_v4i1_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movaps %xmm0, %xmm1 ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: ucomiss %xmm1, %xmm1 ; CHECK-NEXT: ucomiss %xmm1, %xmm1
; CHECK-NEXT: maxss %xmm2, %xmm1 ; CHECK-NEXT: maxss %xmm2, %xmm1
; CHECK-NEXT: xorps %xmm3, %xmm3 ; CHECK-NEXT: xorps %xmm4, %xmm4
; CHECK-NEXT: minss %xmm3, %xmm1 ; CHECK-NEXT: minss %xmm4, %xmm1
; CHECK-NEXT: cvttss2si %xmm1, %ecx ; CHECK-NEXT: cvttss2si %xmm1, %ecx
; CHECK-NEXT: cmovpl %eax, %ecx ; CHECK-NEXT: cmovpl %eax, %ecx
; CHECK-NEXT: movd %ecx, %xmm1 ; CHECK-NEXT: movd %ecx, %xmm3
; CHECK-NEXT: movaps %xmm0, %xmm4 ; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1] ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
; CHECK-NEXT: ucomiss %xmm4, %xmm4 ; CHECK-NEXT: ucomiss %xmm1, %xmm1
; CHECK-NEXT: maxss %xmm2, %xmm4 ; CHECK-NEXT: maxss %xmm2, %xmm1
; CHECK-NEXT: minss %xmm3, %xmm4 ; CHECK-NEXT: minss %xmm4, %xmm1
; CHECK-NEXT: cvttss2si %xmm4, %ecx ; CHECK-NEXT: cvttss2si %xmm1, %ecx
; CHECK-NEXT: cmovpl %eax, %ecx ; CHECK-NEXT: cmovpl %eax, %ecx
; CHECK-NEXT: movd %ecx, %xmm4 ; CHECK-NEXT: movd %ecx, %xmm1
; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] ; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; CHECK-NEXT: movaps %xmm0, %xmm1 ; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: maxss %xmm2, %xmm1 ; CHECK-NEXT: maxss %xmm2, %xmm1
; CHECK-NEXT: minss %xmm3, %xmm1 ; CHECK-NEXT: minss %xmm4, %xmm1
; CHECK-NEXT: cvttss2si %xmm1, %ecx ; CHECK-NEXT: cvttss2si %xmm1, %ecx
; CHECK-NEXT: ucomiss %xmm0, %xmm0 ; CHECK-NEXT: ucomiss %xmm0, %xmm0
; CHECK-NEXT: cmovpl %eax, %ecx ; CHECK-NEXT: cmovpl %eax, %ecx
; CHECK-NEXT: movd %ecx, %xmm1 ; CHECK-NEXT: movd %ecx, %xmm1
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: ucomiss %xmm0, %xmm0 ; CHECK-NEXT: ucomiss %xmm0, %xmm0
; CHECK-NEXT: maxss %xmm2, %xmm0 ; CHECK-NEXT: maxss %xmm2, %xmm0
; CHECK-NEXT: minss %xmm3, %xmm0 ; CHECK-NEXT: minss %xmm4, %xmm0
; CHECK-NEXT: cvttss2si %xmm0, %ecx ; CHECK-NEXT: cvttss2si %xmm0, %ecx
; CHECK-NEXT: cmovpl %eax, %ecx ; CHECK-NEXT: cmovpl %eax, %ecx
; CHECK-NEXT: movd %ecx, %xmm0 ; CHECK-NEXT: movd %ecx, %xmm0
; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm4[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = call <4 x i1> @llvm.fptosi.sat.v4i1.v4f32(<4 x float> %f) %x = call <4 x i1> @llvm.fptosi.sat.v4i1.v4f32(<4 x float> %f)
ret <4 x i1> %x ret <4 x i1> %x
} }
define <4 x i8> @test_signed_v4i8_v4f32(<4 x float> %f) nounwind { define <4 x i8> @test_signed_v4i8_v4f32(<4 x float> %f) nounwind {
; CHECK-LABEL: test_signed_v4i8_v4f32: ; CHECK-LABEL: test_signed_v4i8_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movaps %xmm0, %xmm1 ; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3] ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; CHECK-NEXT: movaps %xmm2, %xmm3 ; CHECK-NEXT: movaps %xmm2, %xmm3
; CHECK-NEXT: maxss %xmm1, %xmm3 ; CHECK-NEXT: maxss %xmm1, %xmm3
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: movaps %xmm1, %xmm4 ; CHECK-NEXT: movaps %xmm1, %xmm4
; CHECK-NEXT: minss %xmm3, %xmm4 ; CHECK-NEXT: minss %xmm3, %xmm4
; CHECK-NEXT: cvttss2si %xmm4, %eax ; CHECK-NEXT: cvttss2si %xmm4, %eax
; CHECK-NEXT: shll $8, %eax ; CHECK-NEXT: shll $8, %eax
; CHECK-NEXT: movaps %xmm0, %xmm3 ; CHECK-NEXT: xorps %xmm3, %xmm3
; CHECK-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1] ; CHECK-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; CHECK-NEXT: movaps %xmm2, %xmm4 ; CHECK-NEXT: movaps %xmm2, %xmm4
; CHECK-NEXT: maxss %xmm3, %xmm4 ; CHECK-NEXT: maxss %xmm3, %xmm4
; CHECK-NEXT: movaps %xmm1, %xmm3 ; CHECK-NEXT: movaps %xmm1, %xmm3
; CHECK-NEXT: minss %xmm4, %xmm3 ; CHECK-NEXT: minss %xmm4, %xmm3
; CHECK-NEXT: cvttss2si %xmm3, %ecx ; CHECK-NEXT: cvttss2si %xmm3, %ecx
; CHECK-NEXT: movzbl %cl, %ecx ; CHECK-NEXT: movzbl %cl, %ecx
; CHECK-NEXT: orl %eax, %ecx ; CHECK-NEXT: orl %eax, %ecx
; CHECK-NEXT: movaps %xmm2, %xmm3 ; CHECK-NEXT: movaps %xmm2, %xmm3
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; CHECK-NEXT: cvttss2si %xmm1, %eax ; CHECK-NEXT: cvttss2si %xmm1, %eax
; CHECK-NEXT: movaps %xmm2, %xmm1 ; CHECK-NEXT: movaps %xmm2, %xmm1
; CHECK-NEXT: maxss %xmm0, %xmm1 ; CHECK-NEXT: maxss %xmm0, %xmm1
; CHECK-NEXT: movaps %xmm4, %xmm3 ; CHECK-NEXT: movaps %xmm4, %xmm3
; CHECK-NEXT: minss %xmm1, %xmm3 ; CHECK-NEXT: minss %xmm1, %xmm3
; CHECK-NEXT: cvttss2si %xmm3, %ecx ; CHECK-NEXT: cvttss2si %xmm3, %ecx
; CHECK-NEXT: movd %ecx, %xmm1 ; CHECK-NEXT: movd %ecx, %xmm1
; CHECK-NEXT: pinsrw $1, %eax, %xmm1 ; CHECK-NEXT: pinsrw $1, %eax, %xmm1
; CHECK-NEXT: movaps %xmm0, %xmm3 ; CHECK-NEXT: xorps %xmm3, %xmm3
; CHECK-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1] ; CHECK-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; CHECK-NEXT: movaps %xmm2, %xmm5 ; CHECK-NEXT: movaps %xmm2, %xmm5
; CHECK-NEXT: maxss %xmm3, %xmm5 ; CHECK-NEXT: maxss %xmm3, %xmm5
; CHECK-NEXT: movaps %xmm4, %xmm3 ; CHECK-NEXT: movaps %xmm4, %xmm3
; CHECK-NEXT: minss %xmm5, %xmm3 ; CHECK-NEXT: minss %xmm5, %xmm3
; CHECK-NEXT: cvttss2si %xmm3, %eax ; CHECK-NEXT: cvttss2si %xmm3, %eax
; CHECK-NEXT: pinsrw $2, %eax, %xmm1 ; CHECK-NEXT: pinsrw $2, %eax, %xmm1
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; CHECK-NEXT: maxss %xmm0, %xmm2 ; CHECK-NEXT: maxss %xmm0, %xmm2
; CHECK-NEXT: minss %xmm2, %xmm4 ; CHECK-NEXT: minss %xmm2, %xmm4
; CHECK-NEXT: cvttss2si %xmm4, %eax ; CHECK-NEXT: cvttss2si %xmm4, %eax
; CHECK-NEXT: pinsrw $3, %eax, %xmm1 ; CHECK-NEXT: pinsrw $3, %eax, %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f32(<4 x float> %f) %x = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f32(<4 x float> %f)
ret <4 x i16> %x ret <4 x i16> %x
} }
define <4 x i32> @test_signed_v4i32_v4f32(<4 x float> %f) nounwind { define <4 x i32> @test_signed_v4i32_v4f32(<4 x float> %f) nounwind {
; CHECK-LABEL: test_signed_v4i32_v4f32: ; CHECK-LABEL: test_signed_v4i32_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movaps %xmm0, %xmm1 ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
; CHECK-NEXT: cvttss2si %xmm1, %edx ; CHECK-NEXT: cvttss2si %xmm1, %edx
; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; CHECK-NEXT: ucomiss %xmm2, %xmm1 ; CHECK-NEXT: ucomiss %xmm3, %xmm1
; CHECK-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF ; CHECK-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
; CHECK-NEXT: cmoval %eax, %edx ; CHECK-NEXT: cmoval %eax, %edx
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: ucomiss %xmm1, %xmm1 ; CHECK-NEXT: ucomiss %xmm1, %xmm1
; CHECK-NEXT: cmovpl %ecx, %edx ; CHECK-NEXT: cmovpl %ecx, %edx
; CHECK-NEXT: movd %edx, %xmm1 ; CHECK-NEXT: movd %edx, %xmm2
; CHECK-NEXT: movaps %xmm0, %xmm3 ; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1] ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
; CHECK-NEXT: cvttss2si %xmm3, %edx ; CHECK-NEXT: cvttss2si %xmm1, %edx
; CHECK-NEXT: ucomiss %xmm2, %xmm3 ; CHECK-NEXT: ucomiss %xmm3, %xmm1
; CHECK-NEXT: cmoval %eax, %edx ; CHECK-NEXT: cmoval %eax, %edx
; CHECK-NEXT: ucomiss %xmm3, %xmm3 ; CHECK-NEXT: ucomiss %xmm1, %xmm1
; CHECK-NEXT: cmovpl %ecx, %edx ; CHECK-NEXT: cmovpl %ecx, %edx
; CHECK-NEXT: movd %edx, %xmm3 ; CHECK-NEXT: movd %edx, %xmm1
; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1] ; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-NEXT: cvttss2si %xmm0, %edx ; CHECK-NEXT: cvttss2si %xmm0, %edx
; CHECK-NEXT: ucomiss %xmm2, %xmm0 ; CHECK-NEXT: ucomiss %xmm3, %xmm0
; CHECK-NEXT: cmoval %eax, %edx ; CHECK-NEXT: cmoval %eax, %edx
; CHECK-NEXT: ucomiss %xmm0, %xmm0 ; CHECK-NEXT: ucomiss %xmm0, %xmm0
; CHECK-NEXT: cmovpl %ecx, %edx ; CHECK-NEXT: cmovpl %ecx, %edx
; CHECK-NEXT: movd %edx, %xmm1 ; CHECK-NEXT: movd %edx, %xmm1
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: cvttss2si %xmm0, %edx ; CHECK-NEXT: cvttss2si %xmm0, %edx
; CHECK-NEXT: ucomiss %xmm2, %xmm0 ; CHECK-NEXT: ucomiss %xmm3, %xmm0
; CHECK-NEXT: cmoval %eax, %edx ; CHECK-NEXT: cmoval %eax, %edx
; CHECK-NEXT: ucomiss %xmm0, %xmm0 ; CHECK-NEXT: ucomiss %xmm0, %xmm0
; CHECK-NEXT: cmovpl %ecx, %edx ; CHECK-NEXT: cmovpl %ecx, %edx
; CHECK-NEXT: movd %edx, %xmm0 ; CHECK-NEXT: movd %edx, %xmm0
; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %f) %x = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %f)
ret <4 x i32> %x ret <4 x i32> %x
} }
define <4 x i64> @test_signed_v4i64_v4f32(<4 x float> %f) nounwind { define <4 x i64> @test_signed_v4i64_v4f32(<4 x float> %f) nounwind {
; CHECK-LABEL: test_signed_v4i64_v4f32: ; CHECK-LABEL: test_signed_v4i64_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: cvttss2si %xmm0, %rdx ; CHECK-NEXT: cvttss2si %xmm0, %rdx
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; CHECK-NEXT: ucomiss %xmm1, %xmm0 ; CHECK-NEXT: ucomiss %xmm3, %xmm0
; CHECK-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF ; CHECK-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
; CHECK-NEXT: cmovaq %rax, %rdx ; CHECK-NEXT: cmovaq %rax, %rdx
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: ucomiss %xmm0, %xmm0 ; CHECK-NEXT: ucomiss %xmm0, %xmm0
; CHECK-NEXT: cmovpq %rcx, %rdx ; CHECK-NEXT: cmovpq %rcx, %rdx
; CHECK-NEXT: movq %rdx, %xmm2 ; CHECK-NEXT: movq %rdx, %xmm2
; CHECK-NEXT: movaps %xmm0, %xmm3 ; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm0[1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; CHECK-NEXT: cvttss2si %xmm3, %rdx ; CHECK-NEXT: cvttss2si %xmm1, %rdx
; CHECK-NEXT: ucomiss %xmm1, %xmm3 ; CHECK-NEXT: ucomiss %xmm3, %xmm1
; CHECK-NEXT: cmovaq %rax, %rdx ; CHECK-NEXT: cmovaq %rax, %rdx
; CHECK-NEXT: ucomiss %xmm3, %xmm3 ; CHECK-NEXT: ucomiss %xmm1, %xmm1
; CHECK-NEXT: cmovpq %rcx, %rdx ; CHECK-NEXT: cmovpq %rcx, %rdx
; CHECK-NEXT: movq %rdx, %xmm3 ; CHECK-NEXT: movq %rdx, %xmm1
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; CHECK-NEXT: movaps %xmm0, %xmm3 ; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3],xmm0[3,3] ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: cvttss2si %xmm3, %rdx ; CHECK-NEXT: cvttss2si %xmm1, %rdx
; CHECK-NEXT: ucomiss %xmm1, %xmm3 ; CHECK-NEXT: ucomiss %xmm3, %xmm1
; CHECK-NEXT: cmovaq %rax, %rdx ; CHECK-NEXT: cmovaq %rax, %rdx
; CHECK-NEXT: ucomiss %xmm3, %xmm3 ; CHECK-NEXT: ucomiss %xmm1, %xmm1
; CHECK-NEXT: cmovpq %rcx, %rdx ; CHECK-NEXT: cmovpq %rcx, %rdx
; CHECK-NEXT: movq %rdx, %xmm3 ; CHECK-NEXT: movq %rdx, %xmm1
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; CHECK-NEXT: cvttss2si %xmm0, %rdx ; CHECK-NEXT: cvttss2si %xmm0, %rdx
; CHECK-NEXT: ucomiss %xmm1, %xmm0 ; CHECK-NEXT: ucomiss %xmm3, %xmm0
; CHECK-NEXT: cmovaq %rax, %rdx ; CHECK-NEXT: cmovaq %rax, %rdx
; CHECK-NEXT: ucomiss %xmm0, %xmm0 ; CHECK-NEXT: ucomiss %xmm0, %xmm0
; CHECK-NEXT: cmovpq %rcx, %rdx ; CHECK-NEXT: cmovpq %rcx, %rdx
; CHECK-NEXT: movq %rdx, %xmm1 ; CHECK-NEXT: movq %rdx, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movdqa %xmm2, %xmm0 ; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = call <4 x i64> @llvm.fptosi.sat.v4i64.v4f32(<4 x float> %f) %x = call <4 x i64> @llvm.fptosi.sat.v4i64.v4f32(<4 x float> %f)
ret <4 x i64> %x ret <4 x i64> %x
} }
define <4 x i128> @test_signed_v4i128_v4f32(<4 x float> %f) nounwind { define <4 x i128> @test_signed_v4i128_v4f32(<4 x float> %f) nounwind {
; CHECK-LABEL: test_signed_v4i128_v4f32: ; CHECK-LABEL: test_signed_v4i128_v4f32:
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declare <2 x i16> @llvm.fptosi.sat.v2i16.v2f64(<2 x double>) declare <2 x i16> @llvm.fptosi.sat.v2i16.v2f64(<2 x double>)
declare <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double>) declare <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double>)
declare <2 x i64> @llvm.fptosi.sat.v2i64.v2f64(<2 x double>) declare <2 x i64> @llvm.fptosi.sat.v2i64.v2f64(<2 x double>)
declare <2 x i128> @llvm.fptosi.sat.v2i128.v2f64(<2 x double>) declare <2 x i128> @llvm.fptosi.sat.v2i128.v2f64(<2 x double>)
define <2 x i1> @test_signed_v2i1_v2f64(<2 x double> %f) nounwind { define <2 x i1> @test_signed_v2i1_v2f64(<2 x double> %f) nounwind {
; CHECK-LABEL: test_signed_v2i1_v2f64: ; CHECK-LABEL: test_signed_v2i1_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; CHECK-NEXT: movapd %xmm0, %xmm1 ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: ucomisd %xmm1, %xmm1
; CHECK-NEXT: maxsd %xmm2, %xmm1 ; CHECK-NEXT: maxsd %xmm2, %xmm1
; CHECK-NEXT: xorpd %xmm3, %xmm3 ; CHECK-NEXT: xorpd %xmm3, %xmm3
; CHECK-NEXT: minsd %xmm3, %xmm1 ; CHECK-NEXT: minsd %xmm3, %xmm1
; CHECK-NEXT: cvttsd2si %xmm1, %rax ; CHECK-NEXT: cvttsd2si %xmm1, %rcx
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: cmovpq %rax, %rcx
; CHECK-NEXT: ucomisd %xmm0, %xmm0 ; CHECK-NEXT: movq %rcx, %xmm1
; CHECK-NEXT: cmovpq %rcx, %rax
; CHECK-NEXT: movq %rax, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: ucomisd %xmm0, %xmm0 ; CHECK-NEXT: ucomisd %xmm0, %xmm0
; CHECK-NEXT: maxsd %xmm2, %xmm0 ; CHECK-NEXT: maxsd %xmm2, %xmm0
; CHECK-NEXT: minsd %xmm3, %xmm0 ; CHECK-NEXT: minsd %xmm3, %xmm0
; CHECK-NEXT: cvttsd2si %xmm0, %rax ; CHECK-NEXT: cvttsd2si %xmm0, %rcx
; CHECK-NEXT: cmovpq %rcx, %rax ; CHECK-NEXT: cmovpq %rax, %rcx
; CHECK-NEXT: movq %rax, %xmm0 ; CHECK-NEXT: movq %rcx, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = call <2 x i1> @llvm.fptosi.sat.v2i1.v2f64(<2 x double> %f) %x = call <2 x i1> @llvm.fptosi.sat.v2i1.v2f64(<2 x double> %f)
ret <2 x i1> %x ret <2 x i1> %x
} }
define <2 x i8> @test_signed_v2i8_v2f64(<2 x double> %f) nounwind { define <2 x i8> @test_signed_v2i8_v2f64(<2 x double> %f) nounwind {
; CHECK-LABEL: test_signed_v2i8_v2f64: ; CHECK-LABEL: test_signed_v2i8_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
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; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = call <2 x i8> @llvm.fptosi.sat.v2i8.v2f64(<2 x double> %f) %x = call <2 x i8> @llvm.fptosi.sat.v2i8.v2f64(<2 x double> %f)
ret <2 x i8> %x ret <2 x i8> %x
} }
define <2 x i16> @test_signed_v2i16_v2f64(<2 x double> %f) nounwind { define <2 x i16> @test_signed_v2i16_v2f64(<2 x double> %f) nounwind {
; CHECK-LABEL: test_signed_v2i16_v2f64: ; CHECK-LABEL: test_signed_v2i16_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; CHECK-NEXT: movapd %xmm2, %xmm3
; CHECK-NEXT: maxsd %xmm1, %xmm3
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: movapd %xmm1, %xmm2 ; CHECK-NEXT: movapd %xmm1, %xmm4
; CHECK-NEXT: maxsd %xmm0, %xmm1 ; CHECK-NEXT: minsd %xmm3, %xmm4
; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: cvttsd2si %xmm4, %eax
; CHECK-NEXT: maxsd %xmm0, %xmm2 ; CHECK-NEXT: maxsd %xmm0, %xmm2
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: minsd %xmm2, %xmm1
; CHECK-NEXT: movapd %xmm0, %xmm3 ; CHECK-NEXT: cvttsd2si %xmm1, %ecx
; CHECK-NEXT: minsd %xmm2, %xmm3
; CHECK-NEXT: cvttsd2si %xmm3, %eax
; CHECK-NEXT: minsd %xmm1, %xmm0
; CHECK-NEXT: cvttsd2si %xmm0, %ecx
; CHECK-NEXT: movd %ecx, %xmm0 ; CHECK-NEXT: movd %ecx, %xmm0
; CHECK-NEXT: pinsrw $1, %eax, %xmm0 ; CHECK-NEXT: pinsrw $1, %eax, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = call <2 x i16> @llvm.fptosi.sat.v2i16.v2f64(<2 x double> %f) %x = call <2 x i16> @llvm.fptosi.sat.v2i16.v2f64(<2 x double> %f)
ret <2 x i16> %x ret <2 x i16> %x
} }
define <2 x i32> @test_signed_v2i32_v2f64(<2 x double> %f) nounwind { define <2 x i32> @test_signed_v2i32_v2f64(<2 x double> %f) nounwind {
; CHECK-LABEL: test_signed_v2i32_v2f64: ; CHECK-LABEL: test_signed_v2i32_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; CHECK-NEXT: movapd %xmm0, %xmm1 ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: ucomisd %xmm1, %xmm1
; CHECK-NEXT: maxsd %xmm2, %xmm1 ; CHECK-NEXT: maxsd %xmm2, %xmm1
; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
; CHECK-NEXT: minsd %xmm3, %xmm1 ; CHECK-NEXT: minsd %xmm3, %xmm1
; CHECK-NEXT: cvttsd2si %xmm1, %eax ; CHECK-NEXT: cvttsd2si %xmm1, %ecx
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: cmovpl %eax, %ecx
; CHECK-NEXT: ucomisd %xmm0, %xmm0 ; CHECK-NEXT: movd %ecx, %xmm1
; CHECK-NEXT: cmovpl %ecx, %eax
; CHECK-NEXT: movd %eax, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: ucomisd %xmm0, %xmm0 ; CHECK-NEXT: ucomisd %xmm0, %xmm0
; CHECK-NEXT: maxsd %xmm2, %xmm0 ; CHECK-NEXT: maxsd %xmm2, %xmm0
; CHECK-NEXT: minsd %xmm3, %xmm0 ; CHECK-NEXT: minsd %xmm3, %xmm0
; CHECK-NEXT: cvttsd2si %xmm0, %eax ; CHECK-NEXT: cvttsd2si %xmm0, %ecx
; CHECK-NEXT: cmovpl %ecx, %eax ; CHECK-NEXT: cmovpl %eax, %ecx
; CHECK-NEXT: movd %eax, %xmm0 ; CHECK-NEXT: movd %ecx, %xmm0
; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double> %f) %x = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double> %f)
ret <2 x i32> %x ret <2 x i32> %x
} }
define <2 x i64> @test_signed_v2i64_v2f64(<2 x double> %f) nounwind { define <2 x i64> @test_signed_v2i64_v2f64(<2 x double> %f) nounwind {
; CHECK-LABEL: test_signed_v2i64_v2f64: ; CHECK-LABEL: test_signed_v2i64_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: cvttsd2si %xmm0, %rax ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: cvttsd2si %xmm1, %rax
; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; CHECK-NEXT: ucomisd %xmm2, %xmm0 ; CHECK-NEXT: ucomisd %xmm2, %xmm1
; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF ; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
; CHECK-NEXT: cmovaq %rcx, %rax ; CHECK-NEXT: cmovaq %rcx, %rax
; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: ucomisd %xmm0, %xmm0 ; CHECK-NEXT: ucomisd %xmm1, %xmm1
; CHECK-NEXT: cmovpq %rdx, %rax ; CHECK-NEXT: cmovpq %rdx, %rax
; CHECK-NEXT: movq %rax, %xmm1 ; CHECK-NEXT: movq %rax, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: cvttsd2si %xmm0, %rax ; CHECK-NEXT: cvttsd2si %xmm0, %rax
; CHECK-NEXT: ucomisd %xmm2, %xmm0 ; CHECK-NEXT: ucomisd %xmm2, %xmm0
; CHECK-NEXT: cmovaq %rcx, %rax ; CHECK-NEXT: cmovaq %rcx, %rax
; CHECK-NEXT: ucomisd %xmm0, %xmm0 ; CHECK-NEXT: ucomisd %xmm0, %xmm0
; CHECK-NEXT: cmovpq %rdx, %rax ; CHECK-NEXT: cmovpq %rdx, %rax
; CHECK-NEXT: movq %rax, %xmm0 ; CHECK-NEXT: movq %rax, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f64(<2 x double> %f) %x = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f64(<2 x double> %f)
ret <2 x i64> %x ret <2 x i64> %x
} }
define <2 x i128> @test_signed_v2i128_v2f64(<2 x double> %f) nounwind { define <2 x i128> @test_signed_v2i128_v2f64(<2 x double> %f) nounwind {
; CHECK-LABEL: test_signed_v2i128_v2f64: ; CHECK-LABEL: test_signed_v2i128_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
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llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll

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; CHECK-NEXT: movaps %xmm0, %xmm1 ; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3] ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
; CHECK-NEXT: xorps %xmm2, %xmm2 ; CHECK-NEXT: xorps %xmm2, %xmm2
; CHECK-NEXT: maxss %xmm2, %xmm1 ; CHECK-NEXT: maxss %xmm2, %xmm1
; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; CHECK-NEXT: minss %xmm3, %xmm1 ; CHECK-NEXT: minss %xmm3, %xmm1
; CHECK-NEXT: cvttss2si %xmm1, %eax ; CHECK-NEXT: cvttss2si %xmm1, %eax
; CHECK-NEXT: movd %eax, %xmm1 ; CHECK-NEXT: movd %eax, %xmm1
; CHECK-NEXT: movaps %xmm0, %xmm4 ; CHECK-NEXT: movhlps {{.*#+}} xmm4 = xmm0[1],xmm4[1]
; CHECK-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1]
; CHECK-NEXT: maxss %xmm2, %xmm4 ; CHECK-NEXT: maxss %xmm2, %xmm4
; CHECK-NEXT: minss %xmm3, %xmm4 ; CHECK-NEXT: minss %xmm3, %xmm4
; CHECK-NEXT: cvttss2si %xmm4, %eax ; CHECK-NEXT: cvttss2si %xmm4, %eax
; CHECK-NEXT: movd %eax, %xmm4 ; CHECK-NEXT: movd %eax, %xmm4
; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] ; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
; CHECK-NEXT: movaps %xmm0, %xmm1 ; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: maxss %xmm2, %xmm1 ; CHECK-NEXT: maxss %xmm2, %xmm1
; CHECK-NEXT: minss %xmm3, %xmm1 ; CHECK-NEXT: minss %xmm3, %xmm1
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; CHECK-NEXT: xorps %xmm2, %xmm2 ; CHECK-NEXT: xorps %xmm2, %xmm2
; CHECK-NEXT: xorps %xmm3, %xmm3 ; CHECK-NEXT: xorps %xmm3, %xmm3
; CHECK-NEXT: maxss %xmm1, %xmm3 ; CHECK-NEXT: maxss %xmm1, %xmm3
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: movaps %xmm1, %xmm4 ; CHECK-NEXT: movaps %xmm1, %xmm4
; CHECK-NEXT: minss %xmm3, %xmm4 ; CHECK-NEXT: minss %xmm3, %xmm4
; CHECK-NEXT: cvttss2si %xmm4, %eax ; CHECK-NEXT: cvttss2si %xmm4, %eax
; CHECK-NEXT: shll $8, %eax ; CHECK-NEXT: shll $8, %eax
; CHECK-NEXT: movaps %xmm0, %xmm3 ; CHECK-NEXT: xorps %xmm3, %xmm3
; CHECK-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1] ; CHECK-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; CHECK-NEXT: xorps %xmm4, %xmm4 ; CHECK-NEXT: xorps %xmm4, %xmm4
; CHECK-NEXT: maxss %xmm3, %xmm4 ; CHECK-NEXT: maxss %xmm3, %xmm4
; CHECK-NEXT: movaps %xmm1, %xmm3 ; CHECK-NEXT: movaps %xmm1, %xmm3
; CHECK-NEXT: minss %xmm4, %xmm3 ; CHECK-NEXT: minss %xmm4, %xmm3
; CHECK-NEXT: cvttss2si %xmm3, %ecx ; CHECK-NEXT: cvttss2si %xmm3, %ecx
; CHECK-NEXT: movzbl %cl, %ecx ; CHECK-NEXT: movzbl %cl, %ecx
; CHECK-NEXT: orl %eax, %ecx ; CHECK-NEXT: orl %eax, %ecx
; CHECK-NEXT: xorps %xmm3, %xmm3 ; CHECK-NEXT: xorps %xmm3, %xmm3
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; CHECK-NEXT: cvttss2si %xmm1, %eax ; CHECK-NEXT: cvttss2si %xmm1, %eax
; CHECK-NEXT: xorps %xmm1, %xmm1 ; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: maxss %xmm0, %xmm1 ; CHECK-NEXT: maxss %xmm0, %xmm1
; CHECK-NEXT: movaps %xmm4, %xmm3 ; CHECK-NEXT: movaps %xmm4, %xmm3
; CHECK-NEXT: minss %xmm1, %xmm3 ; CHECK-NEXT: minss %xmm1, %xmm3
; CHECK-NEXT: cvttss2si %xmm3, %ecx ; CHECK-NEXT: cvttss2si %xmm3, %ecx
; CHECK-NEXT: movd %ecx, %xmm1 ; CHECK-NEXT: movd %ecx, %xmm1
; CHECK-NEXT: pinsrw $1, %eax, %xmm1 ; CHECK-NEXT: pinsrw $1, %eax, %xmm1
; CHECK-NEXT: movaps %xmm0, %xmm3 ; CHECK-NEXT: xorps %xmm3, %xmm3
; CHECK-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1] ; CHECK-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; CHECK-NEXT: xorps %xmm5, %xmm5 ; CHECK-NEXT: xorps %xmm5, %xmm5
; CHECK-NEXT: maxss %xmm3, %xmm5 ; CHECK-NEXT: maxss %xmm3, %xmm5
; CHECK-NEXT: movaps %xmm4, %xmm3 ; CHECK-NEXT: movaps %xmm4, %xmm3
; CHECK-NEXT: minss %xmm5, %xmm3 ; CHECK-NEXT: minss %xmm5, %xmm3
; CHECK-NEXT: cvttss2si %xmm3, %eax ; CHECK-NEXT: cvttss2si %xmm3, %eax
; CHECK-NEXT: pinsrw $2, %eax, %xmm1 ; CHECK-NEXT: pinsrw $2, %eax, %xmm1
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; CHECK-NEXT: maxss %xmm0, %xmm2 ; CHECK-NEXT: maxss %xmm0, %xmm2
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; CHECK-NEXT: xorps %xmm2, %xmm2 ; CHECK-NEXT: xorps %xmm2, %xmm2
; CHECK-NEXT: ucomiss %xmm2, %xmm1 ; CHECK-NEXT: ucomiss %xmm2, %xmm1
; CHECK-NEXT: cmovbl %eax, %edx ; CHECK-NEXT: cmovbl %eax, %edx
; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; CHECK-NEXT: ucomiss %xmm3, %xmm1 ; CHECK-NEXT: ucomiss %xmm3, %xmm1
; CHECK-NEXT: movl $-1, %ecx ; CHECK-NEXT: movl $-1, %ecx
; CHECK-NEXT: cmoval %ecx, %edx ; CHECK-NEXT: cmoval %ecx, %edx
; CHECK-NEXT: movd %edx, %xmm1 ; CHECK-NEXT: movd %edx, %xmm1
; CHECK-NEXT: movaps %xmm0, %xmm4 ; CHECK-NEXT: movhlps {{.*#+}} xmm4 = xmm0[1],xmm4[1]
; CHECK-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1]
; CHECK-NEXT: cvttss2si %xmm4, %rdx ; CHECK-NEXT: cvttss2si %xmm4, %rdx
; CHECK-NEXT: ucomiss %xmm2, %xmm4 ; CHECK-NEXT: ucomiss %xmm2, %xmm4
; CHECK-NEXT: cmovbl %eax, %edx ; CHECK-NEXT: cmovbl %eax, %edx
; CHECK-NEXT: ucomiss %xmm3, %xmm4 ; CHECK-NEXT: ucomiss %xmm3, %xmm4
; CHECK-NEXT: cmoval %ecx, %edx ; CHECK-NEXT: cmoval %ecx, %edx
; CHECK-NEXT: movd %edx, %xmm4 ; CHECK-NEXT: movd %edx, %xmm4
; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] ; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
; CHECK-NEXT: cvttss2si %xmm0, %rdx ; CHECK-NEXT: cvttss2si %xmm0, %rdx
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; CHECK-NEXT: subss %xmm1, %xmm2 ; CHECK-NEXT: subss %xmm1, %xmm2
; CHECK-NEXT: cvttss2si %xmm2, %rax ; CHECK-NEXT: cvttss2si %xmm2, %rax
; CHECK-NEXT: cvttss2si %xmm0, %rcx ; CHECK-NEXT: cvttss2si %xmm0, %rcx
; CHECK-NEXT: movq %rcx, %rdx ; CHECK-NEXT: movq %rcx, %rdx
; CHECK-NEXT: sarq $63, %rdx ; CHECK-NEXT: sarq $63, %rdx
; CHECK-NEXT: andq %rax, %rdx ; CHECK-NEXT: andq %rax, %rdx
; CHECK-NEXT: orq %rcx, %rdx ; CHECK-NEXT: orq %rcx, %rdx
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: xorps %xmm3, %xmm3 ; CHECK-NEXT: xorps %xmm2, %xmm2
; CHECK-NEXT: ucomiss %xmm3, %xmm0 ; CHECK-NEXT: ucomiss %xmm2, %xmm0
; CHECK-NEXT: cmovbq %rax, %rdx ; CHECK-NEXT: cmovbq %rax, %rdx
; CHECK-NEXT: movss {{.*#+}} xmm4 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; CHECK-NEXT: ucomiss %xmm4, %xmm0 ; CHECK-NEXT: ucomiss %xmm3, %xmm0
; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: movq $-1, %rcx
; CHECK-NEXT: cmovaq %rcx, %rdx ; CHECK-NEXT: cmovaq %rcx, %rdx
; CHECK-NEXT: movq %rdx, %xmm2 ; CHECK-NEXT: movaps %xmm0, %xmm4
; CHECK-NEXT: movaps %xmm0, %xmm5 ; CHECK-NEXT: movhlps {{.*#+}} xmm5 = xmm0[1],xmm5[1]
; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,1],xmm0[1,1] ; CHECK-NEXT: movaps %xmm0, %xmm6
; CHECK-NEXT: movaps %xmm5, %xmm6 ; CHECK-NEXT: shufps {{.*#+}} xmm6 = xmm6[1,1],xmm0[1,1]
; CHECK-NEXT: subss %xmm1, %xmm6 ; CHECK-NEXT: movaps %xmm6, %xmm0
; CHECK-NEXT: subss %xmm1, %xmm0
; CHECK-NEXT: cvttss2si %xmm0, %rsi
; CHECK-NEXT: movq %rdx, %xmm0
; CHECK-NEXT: cvttss2si %xmm6, %rdx ; CHECK-NEXT: cvttss2si %xmm6, %rdx
; CHECK-NEXT: cvttss2si %xmm5, %rsi ; CHECK-NEXT: movq %rdx, %rdi
; CHECK-NEXT: movq %rsi, %rdi
; CHECK-NEXT: sarq $63, %rdi ; CHECK-NEXT: sarq $63, %rdi
; CHECK-NEXT: andq %rdx, %rdi ; CHECK-NEXT: andq %rsi, %rdi
; CHECK-NEXT: orq %rsi, %rdi ; CHECK-NEXT: orq %rdx, %rdi
; CHECK-NEXT: ucomiss %xmm3, %xmm5 ; CHECK-NEXT: ucomiss %xmm2, %xmm6
; CHECK-NEXT: cmovbq %rax, %rdi ; CHECK-NEXT: cmovbq %rax, %rdi
; CHECK-NEXT: ucomiss %xmm4, %xmm5 ; CHECK-NEXT: ucomiss %xmm3, %xmm6
; CHECK-NEXT: cmovaq %rcx, %rdi ; CHECK-NEXT: cmovaq %rcx, %rdi
; CHECK-NEXT: movq %rdi, %xmm5 ; CHECK-NEXT: movq %rdi, %xmm6
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm5[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm6[0]
; CHECK-NEXT: movaps %xmm0, %xmm5 ; CHECK-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm0[3,3] ; CHECK-NEXT: movaps %xmm4, %xmm6
; CHECK-NEXT: movaps %xmm5, %xmm6
; CHECK-NEXT: subss %xmm1, %xmm6 ; CHECK-NEXT: subss %xmm1, %xmm6
; CHECK-NEXT: cvttss2si %xmm6, %rdx ; CHECK-NEXT: cvttss2si %xmm6, %rdx
; CHECK-NEXT: cvttss2si %xmm5, %rsi ; CHECK-NEXT: cvttss2si %xmm4, %rsi
; CHECK-NEXT: movq %rsi, %rdi ; CHECK-NEXT: movq %rsi, %rdi
; CHECK-NEXT: sarq $63, %rdi ; CHECK-NEXT: sarq $63, %rdi
; CHECK-NEXT: andq %rdx, %rdi ; CHECK-NEXT: andq %rdx, %rdi
; CHECK-NEXT: orq %rsi, %rdi ; CHECK-NEXT: orq %rsi, %rdi
; CHECK-NEXT: ucomiss %xmm3, %xmm5 ; CHECK-NEXT: ucomiss %xmm2, %xmm4
; CHECK-NEXT: cmovbq %rax, %rdi ; CHECK-NEXT: cmovbq %rax, %rdi
; CHECK-NEXT: ucomiss %xmm4, %xmm5 ; CHECK-NEXT: ucomiss %xmm3, %xmm4
; CHECK-NEXT: cmovaq %rcx, %rdi ; CHECK-NEXT: cmovaq %rcx, %rdi
; CHECK-NEXT: movq %rdi, %xmm5 ; CHECK-NEXT: movq %rdi, %xmm4
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: cvttss2si %xmm5, %rdx
; CHECK-NEXT: movaps %xmm0, %xmm6 ; CHECK-NEXT: movq %rdx, %rsi
; CHECK-NEXT: sarq $63, %rsi
; CHECK-NEXT: movaps %xmm5, %xmm6
; CHECK-NEXT: subss %xmm1, %xmm6 ; CHECK-NEXT: subss %xmm1, %xmm6
; CHECK-NEXT: cvttss2si %xmm6, %rdx ; CHECK-NEXT: cvttss2si %xmm6, %rdi
; CHECK-NEXT: cvttss2si %xmm0, %rsi ; CHECK-NEXT: andq %rsi, %rdi
; CHECK-NEXT: movq %rsi, %rdi ; CHECK-NEXT: orq %rdx, %rdi
; CHECK-NEXT: sarq $63, %rdi ; CHECK-NEXT: ucomiss %xmm2, %xmm5
; CHECK-NEXT: andq %rdx, %rdi
; CHECK-NEXT: orq %rsi, %rdi
; CHECK-NEXT: ucomiss %xmm3, %xmm0
; CHECK-NEXT: cmovbq %rax, %rdi ; CHECK-NEXT: cmovbq %rax, %rdi
; CHECK-NEXT: ucomiss %xmm4, %xmm0 ; CHECK-NEXT: ucomiss %xmm3, %xmm5
; CHECK-NEXT: cmovaq %rcx, %rdi ; CHECK-NEXT: cmovaq %rcx, %rdi
; CHECK-NEXT: movq %rdi, %xmm1 ; CHECK-NEXT: movq %rdi, %xmm1
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm5[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm4[0]
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = call <4 x i64> @llvm.fptoui.sat.v4i64.v4f32(<4 x float> %f) %x = call <4 x i64> @llvm.fptoui.sat.v4i64.v4f32(<4 x float> %f)
ret <4 x i64> %x ret <4 x i64> %x
} }
define <4 x i128> @test_unsigned_v4i128_v4f32(<4 x float> %f) nounwind { define <4 x i128> @test_unsigned_v4i128_v4f32(<4 x float> %f) nounwind {
; CHECK-LABEL: test_unsigned_v4i128_v4f32: ; CHECK-LABEL: test_unsigned_v4i128_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
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declare <2 x i16> @llvm.fptoui.sat.v2i16.v2f64(<2 x double>) declare <2 x i16> @llvm.fptoui.sat.v2i16.v2f64(<2 x double>)
declare <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double>) declare <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double>)
declare <2 x i64> @llvm.fptoui.sat.v2i64.v2f64(<2 x double>) declare <2 x i64> @llvm.fptoui.sat.v2i64.v2f64(<2 x double>)
declare <2 x i128> @llvm.fptoui.sat.v2i128.v2f64(<2 x double>) declare <2 x i128> @llvm.fptoui.sat.v2i128.v2f64(<2 x double>)
define <2 x i1> @test_unsigned_v2i1_v2f64(<2 x double> %f) nounwind { define <2 x i1> @test_unsigned_v2i1_v2f64(<2 x double> %f) nounwind {
; CHECK-LABEL: test_unsigned_v2i1_v2f64: ; CHECK-LABEL: test_unsigned_v2i1_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xorpd %xmm2, %xmm2 ; CHECK-NEXT: xorpd %xmm1, %xmm1
; CHECK-NEXT: movapd %xmm0, %xmm1 ; CHECK-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; CHECK-NEXT: maxsd %xmm2, %xmm1 ; CHECK-NEXT: maxsd %xmm1, %xmm0
; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
; CHECK-NEXT: minsd %xmm3, %xmm1
; CHECK-NEXT: cvttsd2si %xmm1, %rax
; CHECK-NEXT: movq %rax, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: maxsd %xmm2, %xmm0
; CHECK-NEXT: minsd %xmm3, %xmm0 ; CHECK-NEXT: minsd %xmm3, %xmm0
; CHECK-NEXT: cvttsd2si %xmm0, %rax ; CHECK-NEXT: cvttsd2si %xmm0, %rax
; CHECK-NEXT: movq %rax, %xmm0 ; CHECK-NEXT: movq %rax, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: maxsd %xmm1, %xmm2
; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: minsd %xmm3, %xmm2
; CHECK-NEXT: cvttsd2si %xmm2, %rax
; CHECK-NEXT: movq %rax, %xmm1
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = call <2 x i1> @llvm.fptoui.sat.v2i1.v2f64(<2 x double> %f) %x = call <2 x i1> @llvm.fptoui.sat.v2i1.v2f64(<2 x double> %f)
ret <2 x i1> %x ret <2 x i1> %x
} }
define <2 x i8> @test_unsigned_v2i8_v2f64(<2 x double> %f) nounwind { define <2 x i8> @test_unsigned_v2i8_v2f64(<2 x double> %f) nounwind {
; CHECK-LABEL: test_unsigned_v2i8_v2f64: ; CHECK-LABEL: test_unsigned_v2i8_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
Show All 15 Lines
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = call <2 x i8> @llvm.fptoui.sat.v2i8.v2f64(<2 x double> %f) %x = call <2 x i8> @llvm.fptoui.sat.v2i8.v2f64(<2 x double> %f)
ret <2 x i8> %x ret <2 x i8> %x
} }
define <2 x i16> @test_unsigned_v2i16_v2f64(<2 x double> %f) nounwind { define <2 x i16> @test_unsigned_v2i16_v2f64(<2 x double> %f) nounwind {
; CHECK-LABEL: test_unsigned_v2i16_v2f64: ; CHECK-LABEL: test_unsigned_v2i16_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xorpd %xmm1, %xmm1 ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: maxsd %xmm0, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: xorpd %xmm2, %xmm2 ; CHECK-NEXT: xorpd %xmm2, %xmm2
; CHECK-NEXT: xorpd %xmm3, %xmm3
; CHECK-NEXT: maxsd %xmm1, %xmm3
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: movapd %xmm1, %xmm4
; CHECK-NEXT: minsd %xmm3, %xmm4
; CHECK-NEXT: cvttsd2si %xmm4, %eax
; CHECK-NEXT: maxsd %xmm0, %xmm2 ; CHECK-NEXT: maxsd %xmm0, %xmm2
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: minsd %xmm2, %xmm1
; CHECK-NEXT: movapd %xmm0, %xmm3 ; CHECK-NEXT: cvttsd2si %xmm1, %ecx
; CHECK-NEXT: minsd %xmm2, %xmm3
; CHECK-NEXT: cvttsd2si %xmm3, %eax
; CHECK-NEXT: minsd %xmm1, %xmm0
; CHECK-NEXT: cvttsd2si %xmm0, %ecx
; CHECK-NEXT: movd %ecx, %xmm0 ; CHECK-NEXT: movd %ecx, %xmm0
; CHECK-NEXT: pinsrw $1, %eax, %xmm0 ; CHECK-NEXT: pinsrw $1, %eax, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = call <2 x i16> @llvm.fptoui.sat.v2i16.v2f64(<2 x double> %f) %x = call <2 x i16> @llvm.fptoui.sat.v2i16.v2f64(<2 x double> %f)
ret <2 x i16> %x ret <2 x i16> %x
} }
define <2 x i32> @test_unsigned_v2i32_v2f64(<2 x double> %f) nounwind { define <2 x i32> @test_unsigned_v2i32_v2f64(<2 x double> %f) nounwind {
Show All 36 Lines
; CHECK-NEXT: ucomisd %xmm3, %xmm0 ; CHECK-NEXT: ucomisd %xmm3, %xmm0
; CHECK-NEXT: cmovbq %rax, %rdx ; CHECK-NEXT: cmovbq %rax, %rdx
; CHECK-NEXT: movsd {{.*#+}} xmm4 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm4 = mem[0],zero
; CHECK-NEXT: ucomisd %xmm4, %xmm0 ; CHECK-NEXT: ucomisd %xmm4, %xmm0
; CHECK-NEXT: movq $-1, %rcx ; CHECK-NEXT: movq $-1, %rcx
; CHECK-NEXT: cmovaq %rcx, %rdx ; CHECK-NEXT: cmovaq %rcx, %rdx
; CHECK-NEXT: movq %rdx, %xmm1 ; CHECK-NEXT: movq %rdx, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: cvttsd2si %xmm0, %rdx
; CHECK-NEXT: movq %rdx, %rsi
; CHECK-NEXT: sarq $63, %rsi
; CHECK-NEXT: movapd %xmm0, %xmm5 ; CHECK-NEXT: movapd %xmm0, %xmm5
; CHECK-NEXT: subsd %xmm2, %xmm5 ; CHECK-NEXT: subsd %xmm2, %xmm5
; CHECK-NEXT: cvttsd2si %xmm5, %rdx ; CHECK-NEXT: cvttsd2si %xmm5, %rdi
; CHECK-NEXT: cvttsd2si %xmm0, %rsi ; CHECK-NEXT: andq %rsi, %rdi
; CHECK-NEXT: movq %rsi, %rdi ; CHECK-NEXT: orq %rdx, %rdi
; CHECK-NEXT: sarq $63, %rdi
; CHECK-NEXT: andq %rdx, %rdi
; CHECK-NEXT: orq %rsi, %rdi
; CHECK-NEXT: ucomisd %xmm3, %xmm0 ; CHECK-NEXT: ucomisd %xmm3, %xmm0
; CHECK-NEXT: cmovbq %rax, %rdi ; CHECK-NEXT: cmovbq %rax, %rdi
; CHECK-NEXT: ucomisd %xmm4, %xmm0 ; CHECK-NEXT: ucomisd %xmm4, %xmm0
; CHECK-NEXT: cmovaq %rcx, %rdi ; CHECK-NEXT: cmovaq %rcx, %rdi
; CHECK-NEXT: movq %rdi, %xmm0 ; CHECK-NEXT: movq %rdi, %xmm0
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
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llvm/test/CodeGen/X86/ftrunc.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; SSE2-NEXT: sarq $63, %rcx ; SSE2-NEXT: sarq $63, %rcx
; SSE2-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: cvttsd2si %xmm0, %rdx ; SSE2-NEXT: cvttsd2si %xmm0, %rdx
; SSE2-NEXT: andq %rcx, %rdx ; SSE2-NEXT: andq %rcx, %rdx
; SSE2-NEXT: orq %rax, %rdx ; SSE2-NEXT: orq %rax, %rdx
; SSE2-NEXT: movq %rdx, %xmm1 ; SSE2-NEXT: movq %rdx, %xmm1
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
; SSE2-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movapd %xmm1, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSE2-NEXT: addsd %xmm1, %xmm0 ; SSE2-NEXT: addsd %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: trunc_unsigned_f64: ; SSE41-LABEL: trunc_unsigned_f64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: roundsd $11, %xmm0, %xmm0 ; SSE41-NEXT: roundsd $11, %xmm0, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines; X32_AVX1-NEXT: retl
%i = fptoui <4 x float> %x to <4 x i32> %i = fptoui <4 x float> %x to <4 x i32>
%r = uitofp <4 x i32> %i to <4 x float> %r = uitofp <4 x i32> %i to <4 x float>
ret <4 x float> %r ret <4 x float> %r
} }
define <2 x double> @trunc_unsigned_v2f64(<2 x double> %x) #0 { define <2 x double> @trunc_unsigned_v2f64(<2 x double> %x) #0 {
; SSE2-LABEL: trunc_unsigned_v2f64: ; SSE2-LABEL: trunc_unsigned_v2f64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: cvttsd2si %xmm1, %rax
; SSE2-NEXT: movq %rax, %rcx
; SSE2-NEXT: sarq $63, %rcx
; SSE2-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero ; SSE2-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; SSE2-NEXT: movapd %xmm0, %xmm1
; SSE2-NEXT: subsd %xmm2, %xmm1 ; SSE2-NEXT: subsd %xmm2, %xmm1
; SSE2-NEXT: cvttsd2si %xmm1, %rax ; SSE2-NEXT: cvttsd2si %xmm1, %rdx
; SSE2-NEXT: cvttsd2si %xmm0, %rcx ; SSE2-NEXT: andq %rcx, %rdx
; SSE2-NEXT: movq %rcx, %rdx ; SSE2-NEXT: orq %rax, %rdx
; SSE2-NEXT: sarq $63, %rdx
; SSE2-NEXT: andq %rax, %rdx
; SSE2-NEXT: orq %rcx, %rdx
; SSE2-NEXT: movq %rdx, %xmm1 ; SSE2-NEXT: movq %rdx, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: cvttsd2si %xmm0, %rax ; SSE2-NEXT: cvttsd2si %xmm0, %rax
; SSE2-NEXT: subsd %xmm2, %xmm0 ; SSE2-NEXT: subsd %xmm2, %xmm0
; SSE2-NEXT: cvttsd2si %xmm0, %rcx ; SSE2-NEXT: cvttsd2si %xmm0, %rcx
; SSE2-NEXT: movq %rax, %rdx ; SSE2-NEXT: movq %rax, %rdx
; SSE2-NEXT: sarq $63, %rdx ; SSE2-NEXT: sarq $63, %rdx
; SSE2-NEXT: andq %rcx, %rdx ; SSE2-NEXT: andq %rcx, %rdx
; SSE2-NEXT: orq %rax, %rdx ; SSE2-NEXT: orq %rax, %rdx
; SSE2-NEXT: movq %rdx, %xmm0 ; SSE2-NEXT: movq %rdx, %xmm0
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [4294967295,4294967295] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [4294967295,4294967295]
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlq $32, %xmm1
; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: psrlq $32, %xmm0
; SSE2-NEXT: addpd %xmm0, %xmm1 ; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movapd %xmm1, %xmm0 ; SSE2-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: addpd %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: trunc_unsigned_v2f64: ; SSE41-LABEL: trunc_unsigned_v2f64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: roundpd $11, %xmm0, %xmm0 ; SSE41-NEXT: roundpd $11, %xmm0, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; X64_AVX1-LABEL: trunc_unsigned_v2f64: ; X64_AVX1-LABEL: trunc_unsigned_v2f64:
; X64_AVX1: # %bb.0: ; X64_AVX1: # %bb.0:
; X64_AVX1-NEXT: vroundpd $11, %xmm0, %xmm0 ; X64_AVX1-NEXT: vroundpd $11, %xmm0, %xmm0
; X64_AVX1-NEXT: retq ; X64_AVX1-NEXT: retq
; ;
; X32_AVX1-LABEL: trunc_unsigned_v2f64: ; X32_AVX1-LABEL: trunc_unsigned_v2f64:
; X32_AVX1: # %bb.0: ; X32_AVX1: # %bb.0:
; X32_AVX1-NEXT: vroundpd $11, %xmm0, %xmm0 ; X32_AVX1-NEXT: vroundpd $11, %xmm0, %xmm0
; X32_AVX1-NEXT: retl ; X32_AVX1-NEXT: retl
%i = fptoui <2 x double> %x to <2 x i64> %i = fptoui <2 x double> %x to <2 x i64>
%r = uitofp <2 x i64> %i to <2 x double> %r = uitofp <2 x i64> %i to <2 x double>
ret <2 x double> %r ret <2 x double> %r
} }
define <4 x double> @trunc_unsigned_v4f64(<4 x double> %x) #0 { define <4 x double> @trunc_unsigned_v4f64(<4 x double> %x) #0 {
; SSE2-LABEL: trunc_unsigned_v4f64: ; SSE2-LABEL: trunc_unsigned_v4f64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movapd %xmm1, %xmm2 ; SSE2-NEXT: movhlps {{.*#+}} xmm3 = xmm1[1],xmm3[1]
; SSE2-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero ; SSE2-NEXT: cvttsd2si %xmm3, %rax
; SSE2-NEXT: subsd %xmm3, %xmm1 ; SSE2-NEXT: movq %rax, %rcx
; SSE2-NEXT: sarq $63, %rcx
; SSE2-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; SSE2-NEXT: subsd %xmm2, %xmm3
; SSE2-NEXT: cvttsd2si %xmm3, %rdx
; SSE2-NEXT: andq %rcx, %rdx
; SSE2-NEXT: orq %rax, %rdx
; SSE2-NEXT: movq %rdx, %xmm3
; SSE2-NEXT: cvttsd2si %xmm1, %rax ; SSE2-NEXT: cvttsd2si %xmm1, %rax
; SSE2-NEXT: cvttsd2si %xmm2, %rcx ; SSE2-NEXT: subsd %xmm2, %xmm1
; SSE2-NEXT: movq %rcx, %rdx ; SSE2-NEXT: cvttsd2si %xmm1, %rcx
; SSE2-NEXT: sarq $63, %rdx
; SSE2-NEXT: andq %rax, %rdx
; SSE2-NEXT: orq %rcx, %rdx
; SSE2-NEXT: movq %rdx, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; SSE2-NEXT: cvttsd2si %xmm2, %rax
; SSE2-NEXT: subsd %xmm3, %xmm2
; SSE2-NEXT: cvttsd2si %xmm2, %rcx
; SSE2-NEXT: movq %rax, %rdx ; SSE2-NEXT: movq %rax, %rdx
; SSE2-NEXT: sarq $63, %rdx ; SSE2-NEXT: sarq $63, %rdx
; SSE2-NEXT: andq %rcx, %rdx ; SSE2-NEXT: andq %rcx, %rdx
; SSE2-NEXT: orq %rax, %rdx ; SSE2-NEXT: orq %rax, %rdx
; SSE2-NEXT: movq %rdx, %xmm2 ; SSE2-NEXT: movq %rdx, %xmm1
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
; SSE2-NEXT: movapd %xmm0, %xmm2 ; SSE2-NEXT: xorps %xmm3, %xmm3
; SSE2-NEXT: subsd %xmm3, %xmm2 ; SSE2-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; SSE2-NEXT: cvttsd2si %xmm2, %rax ; SSE2-NEXT: cvttsd2si %xmm3, %rax
; SSE2-NEXT: cvttsd2si %xmm0, %rcx ; SSE2-NEXT: movq %rax, %rcx
; SSE2-NEXT: movq %rcx, %rdx ; SSE2-NEXT: sarq $63, %rcx
; SSE2-NEXT: sarq $63, %rdx ; SSE2-NEXT: subsd %xmm2, %xmm3
; SSE2-NEXT: andq %rax, %rdx ; SSE2-NEXT: cvttsd2si %xmm3, %rdx
; SSE2-NEXT: orq %rcx, %rdx ; SSE2-NEXT: andq %rcx, %rdx
; SSE2-NEXT: movq %rdx, %xmm2 ; SSE2-NEXT: orq %rax, %rdx
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movq %rdx, %xmm3
; SSE2-NEXT: cvttsd2si %xmm0, %rax ; SSE2-NEXT: cvttsd2si %xmm0, %rax
; SSE2-NEXT: subsd %xmm3, %xmm0 ; SSE2-NEXT: subsd %xmm2, %xmm0
; SSE2-NEXT: cvttsd2si %xmm0, %rcx ; SSE2-NEXT: cvttsd2si %xmm0, %rcx
; SSE2-NEXT: movq %rax, %rdx ; SSE2-NEXT: movq %rax, %rdx
; SSE2-NEXT: sarq $63, %rdx ; SSE2-NEXT: sarq $63, %rdx
; SSE2-NEXT: andq %rcx, %rdx ; SSE2-NEXT: andq %rcx, %rdx
; SSE2-NEXT: orq %rax, %rdx ; SSE2-NEXT: orq %rax, %rdx
; SSE2-NEXT: movq %rdx, %xmm0 ; SSE2-NEXT: movq %rdx, %xmm0
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [4294967295,4294967295] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [4294967295,4294967295]
; SSE2-NEXT: movdqa %xmm2, %xmm3 ; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: pand %xmm2, %xmm3
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200] ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200]
; SSE2-NEXT: por %xmm4, %xmm3 ; SSE2-NEXT: por %xmm4, %xmm3
; SSE2-NEXT: psrlq $32, %xmm2 ; SSE2-NEXT: psrlq $32, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [4985484787499139072,4985484787499139072] ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [4985484787499139072,4985484787499139072]
; SSE2-NEXT: por %xmm5, %xmm2 ; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: movapd {{.*#+}} xmm6 = [1.9342813118337666E+25,1.9342813118337666E+25] ; SSE2-NEXT: movapd {{.*#+}} xmm6 = [1.9342813118337666E+25,1.9342813118337666E+25]
; SSE2-NEXT: subpd %xmm6, %xmm2 ; SSE2-NEXT: subpd %xmm6, %xmm0
; SSE2-NEXT: addpd %xmm3, %xmm2 ; SSE2-NEXT: addpd %xmm3, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: por %xmm4, %xmm0 ; SSE2-NEXT: por %xmm4, %xmm2
; SSE2-NEXT: psrlq $32, %xmm1 ; SSE2-NEXT: psrlq $32, %xmm1
; SSE2-NEXT: por %xmm5, %xmm1 ; SSE2-NEXT: por %xmm5, %xmm1
; SSE2-NEXT: subpd %xmm6, %xmm1 ; SSE2-NEXT: subpd %xmm6, %xmm1
; SSE2-NEXT: addpd %xmm0, %xmm1 ; SSE2-NEXT: addpd %xmm2, %xmm1
; SSE2-NEXT: movapd %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: trunc_unsigned_v4f64: ; SSE41-LABEL: trunc_unsigned_v4f64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: roundpd $11, %xmm0, %xmm0 ; SSE41-NEXT: roundpd $11, %xmm0, %xmm0
; SSE41-NEXT: roundpd $11, %xmm1, %xmm1 ; SSE41-NEXT: roundpd $11, %xmm1, %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
▲ Show 20 Lines • Show All 372 Lines • ▼ Show 20 Lines; X32_AVX1-NEXT: retl
%i = fptosi <4 x float> %x to <4 x i32> %i = fptosi <4 x float> %x to <4 x i32>
%r = sitofp <4 x i32> %i to <4 x float> %r = sitofp <4 x i32> %i to <4 x float>
ret <4 x float> %r ret <4 x float> %r
} }
define <2 x double> @trunc_signed_v2f64_nsz(<2 x double> %x) #0 { define <2 x double> @trunc_signed_v2f64_nsz(<2 x double> %x) #0 {
; SSE2-LABEL: trunc_signed_v2f64_nsz: ; SSE2-LABEL: trunc_signed_v2f64_nsz:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: cvttsd2si %xmm0, %rax ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: cvttsd2si %xmm1, %rax
; SSE2-NEXT: cvttsd2si %xmm0, %rcx ; SSE2-NEXT: cvttsd2si %xmm0, %rcx
; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: cvtsi2sd %rax, %xmm1
; SSE2-NEXT: xorps %xmm0, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: cvtsi2sd %rax, %xmm0 ; SSE2-NEXT: cvtsi2sd %rcx, %xmm0
; SSE2-NEXT: cvtsi2sd %rcx, %xmm1
; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: trunc_signed_v2f64_nsz: ; SSE41-LABEL: trunc_signed_v2f64_nsz:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: roundpd $11, %xmm0, %xmm0 ; SSE41-NEXT: roundpd $11, %xmm0, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
Show All 9 Lines; X32_AVX1-NEXT: retl
%i = fptosi <2 x double> %x to <2 x i64> %i = fptosi <2 x double> %x to <2 x i64>
%r = sitofp <2 x i64> %i to <2 x double> %r = sitofp <2 x i64> %i to <2 x double>
ret <2 x double> %r ret <2 x double> %r
} }
define <4 x double> @trunc_signed_v4f64_nsz(<4 x double> %x) #0 { define <4 x double> @trunc_signed_v4f64_nsz(<4 x double> %x) #0 {
; SSE2-LABEL: trunc_signed_v4f64_nsz: ; SSE2-LABEL: trunc_signed_v4f64_nsz:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: cvttsd2si %xmm1, %rax ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE2-NEXT: cvttsd2si %xmm2, %rax
; SSE2-NEXT: cvttsd2si %xmm1, %rcx ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: cvttsd2si %xmm0, %rdx ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: cvttsd2si %xmm2, %rcx
; SSE2-NEXT: cvttsd2si %xmm1, %rdx
; SSE2-NEXT: cvttsd2si %xmm0, %rsi ; SSE2-NEXT: cvttsd2si %xmm0, %rsi
; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: cvtsi2sd %rdx, %xmm0
; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: cvtsi2sd %rsi, %xmm1 ; SSE2-NEXT: cvtsi2sd %rcx, %xmm1
; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: cvtsi2sd %rsi, %xmm0
; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: cvtsi2sd %rax, %xmm2
; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: cvtsi2sd %rax, %xmm1 ; SSE2-NEXT: cvtsi2sd %rdx, %xmm1
; SSE2-NEXT: cvtsi2sd %rcx, %xmm2
; SSE2-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; SSE2-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: trunc_signed_v4f64_nsz: ; SSE41-LABEL: trunc_signed_v4f64_nsz:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: roundpd $11, %xmm0, %xmm0 ; SSE41-NEXT: roundpd $11, %xmm0, %xmm0
; SSE41-NEXT: roundpd $11, %xmm1, %xmm1 ; SSE41-NEXT: roundpd $11, %xmm1, %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
▲ Show 20 Lines • Show All 152 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/haddsub-2.ll

Show First 20 Lines • Show All 879 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%sub12 = sub i32 %vecext10, %vecext11 %sub12 = sub i32 %vecext10, %vecext11
%vecinit13 = insertelement <4 x i32> %vecinit9, i32 %sub12, i32 3 %vecinit13 = insertelement <4 x i32> %vecinit9, i32 %sub12, i32 3
ret <4 x i32> %vecinit13 ret <4 x i32> %vecinit13
} }
define <4 x float> @not_a_hsub_2(<4 x float> %A, <4 x float> %B) { define <4 x float> @not_a_hsub_2(<4 x float> %A, <4 x float> %B) {
; SSE-LABEL: not_a_hsub_2: ; SSE-LABEL: not_a_hsub_2:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm0, %xmm2 ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE-NEXT: movaps %xmm0, %xmm3 ; SSE-NEXT: movaps %xmm0, %xmm3
; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3],xmm0[3,3] ; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3],xmm0[3,3]
; SSE-NEXT: subss %xmm3, %xmm2 ; SSE-NEXT: subss %xmm3, %xmm2
; SSE-NEXT: movshdup {{.*#+}} xmm3 = xmm0[1,1,3,3] ; SSE-NEXT: movshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
; SSE-NEXT: subss %xmm3, %xmm0 ; SSE-NEXT: subss %xmm3, %xmm0
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; SSE-NEXT: movaps %xmm1, %xmm2 ; SSE-NEXT: movaps %xmm1, %xmm2
; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3],xmm1[3,3] ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3],xmm1[3,3]
; SSE-NEXT: movaps %xmm1, %xmm3 ; SSE-NEXT: xorps %xmm3, %xmm3
; SSE-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm1[1] ; SSE-NEXT: movhlps {{.*#+}} xmm3 = xmm1[1],xmm3[1]
; SSE-NEXT: subss %xmm3, %xmm2 ; SSE-NEXT: subss %xmm3, %xmm2
; SSE-NEXT: movshdup {{.*#+}} xmm3 = xmm1[1,1,3,3] ; SSE-NEXT: movshdup {{.*#+}} xmm3 = xmm1[1,1,3,3]
; SSE-NEXT: subss %xmm3, %xmm1 ; SSE-NEXT: subss %xmm3, %xmm1
; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: not_a_hsub_2: ; AVX-LABEL: not_a_hsub_2:
Show All 29 Lines; AVX-NEXT: retq
%sub12 = fsub float %vecext10, %vecext11 %sub12 = fsub float %vecext10, %vecext11
%vecinit13 = insertelement <4 x float> %vecinit9, float %sub12, i32 2 %vecinit13 = insertelement <4 x float> %vecinit9, float %sub12, i32 2
ret <4 x float> %vecinit13 ret <4 x float> %vecinit13
} }
define <2 x double> @not_a_hsub_3(<2 x double> %A, <2 x double> %B) { define <2 x double> @not_a_hsub_3(<2 x double> %A, <2 x double> %B) {
; SSE-LABEL: not_a_hsub_3: ; SSE-LABEL: not_a_hsub_3:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm1, %xmm2 ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1]
; SSE-NEXT: subsd %xmm2, %xmm1 ; SSE-NEXT: subsd %xmm2, %xmm1
; SSE-NEXT: movapd %xmm0, %xmm2 ; SSE-NEXT: xorps %xmm2, %xmm2
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE-NEXT: subsd %xmm0, %xmm2 ; SSE-NEXT: subsd %xmm0, %xmm2
; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm1[0] ; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; SSE-NEXT: movapd %xmm2, %xmm0 ; SSE-NEXT: movapd %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: not_a_hsub_3: ; AVX-LABEL: not_a_hsub_3:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm1[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm1[1,0]
▲ Show 20 Lines • Show All 466 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/haddsub-3.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=SSSE3,SSSE3-SLOW ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=SSSE3,SSSE3-SLOW
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3,fast-hops | FileCheck %s --check-prefixes=SSSE3,SSSE3-FAST ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3,fast-hops | FileCheck %s --check-prefixes=SSSE3,SSSE3-FAST
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX1,AVX1-SLOW ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX1,AVX1-SLOW
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx,fast-hops | FileCheck %s --check-prefixes=AVX1,AVX1-FAST ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx,fast-hops | FileCheck %s --check-prefixes=AVX1,AVX1-FAST
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX2
define float @pr26491(<4 x float> %a0) { define float @pr26491(<4 x float> %a0) {
; SSE2-LABEL: pr26491: ; SSE2-LABEL: pr26491:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3]
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-SLOW-LABEL: pr26491: ; SSSE3-SLOW-LABEL: pr26491:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSSE3-SLOW-NEXT: xorps %xmm1, %xmm1
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: pr26491: ; SSSE3-FAST-LABEL: pr26491:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSSE3-FAST-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSSE3-FAST-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSSE3-FAST-NEXT: addss %xmm1, %xmm0 ; SSSE3-FAST-NEXT: addss %xmm1, %xmm0
▲ Show 20 Lines • Show All 143 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/haddsub-shuf.ll

Show First 20 Lines • Show All 166 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%hop = fsub <8 x float> %a0, %a1 %hop = fsub <8 x float> %a0, %a1
%shuf = shufflevector <8 x float> %hop, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5> %shuf = shufflevector <8 x float> %hop, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5>
ret <8 x float> %shuf ret <8 x float> %shuf
} }
define <2 x double> @hadd_v2f64(<2 x double> %a) { define <2 x double> @hadd_v2f64(<2 x double> %a) {
; SSE_SLOW-LABEL: hadd_v2f64: ; SSE_SLOW-LABEL: hadd_v2f64:
; SSE_SLOW: # %bb.0: ; SSE_SLOW: # %bb.0:
; SSE_SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE_SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE_SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE_SLOW-NEXT: addsd %xmm0, %xmm1 ; SSE_SLOW-NEXT: addsd %xmm0, %xmm1
; SSE_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0] ; SSE_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
; SSE_SLOW-NEXT: retq ; SSE_SLOW-NEXT: retq
; ;
; SSE_FAST-LABEL: hadd_v2f64: ; SSE_FAST-LABEL: hadd_v2f64:
; SSE_FAST: # %bb.0: ; SSE_FAST: # %bb.0:
; SSE_FAST-NEXT: haddpd %xmm0, %xmm0 ; SSE_FAST-NEXT: haddpd %xmm0, %xmm0
; SSE_FAST-NEXT: retq ; SSE_FAST-NEXT: retq
Show All 26 Lines; AVX2_FAST-NEXT: retq
%hop = fadd <2 x double> %a0, %a1 %hop = fadd <2 x double> %a0, %a1
%shuf = shufflevector <2 x double> %hop, <2 x double> undef, <2 x i32> <i32 0, i32 0> %shuf = shufflevector <2 x double> %hop, <2 x double> undef, <2 x i32> <i32 0, i32 0>
ret <2 x double> %shuf ret <2 x double> %shuf
} }
define <2 x double> @hadd_v2f64_scalar_splat(<2 x double> %a) { define <2 x double> @hadd_v2f64_scalar_splat(<2 x double> %a) {
; SSE_SLOW-LABEL: hadd_v2f64_scalar_splat: ; SSE_SLOW-LABEL: hadd_v2f64_scalar_splat:
; SSE_SLOW: # %bb.0: ; SSE_SLOW: # %bb.0:
; SSE_SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE_SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE_SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE_SLOW-NEXT: addsd %xmm0, %xmm1 ; SSE_SLOW-NEXT: addsd %xmm0, %xmm1
; SSE_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0] ; SSE_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
; SSE_SLOW-NEXT: retq ; SSE_SLOW-NEXT: retq
; ;
; SSE_FAST-LABEL: hadd_v2f64_scalar_splat: ; SSE_FAST-LABEL: hadd_v2f64_scalar_splat:
; SSE_FAST: # %bb.0: ; SSE_FAST: # %bb.0:
; SSE_FAST-NEXT: haddpd %xmm0, %xmm0 ; SSE_FAST-NEXT: haddpd %xmm0, %xmm0
; SSE_FAST-NEXT: retq ; SSE_FAST-NEXT: retq
Show All 27 Lines; AVX2_FAST-NEXT: retq
%ins = insertelement <2 x double> undef, double %hop, i32 0 %ins = insertelement <2 x double> undef, double %hop, i32 0
%shuf = shufflevector <2 x double> %ins, <2 x double> undef, <2 x i32> <i32 0, i32 0> %shuf = shufflevector <2 x double> %ins, <2 x double> undef, <2 x i32> <i32 0, i32 0>
ret <2 x double> %shuf ret <2 x double> %shuf
} }
define <4 x double> @hadd_v4f64_scalar_splat(<4 x double> %a) { define <4 x double> @hadd_v4f64_scalar_splat(<4 x double> %a) {
; SSE_SLOW-LABEL: hadd_v4f64_scalar_splat: ; SSE_SLOW-LABEL: hadd_v4f64_scalar_splat:
; SSE_SLOW: # %bb.0: ; SSE_SLOW: # %bb.0:
; SSE_SLOW-NEXT: movapd %xmm0, %xmm2 ; SSE_SLOW-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE_SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE_SLOW-NEXT: addsd %xmm0, %xmm2 ; SSE_SLOW-NEXT: addsd %xmm0, %xmm2
; SSE_SLOW-NEXT: movapd %xmm1, %xmm3 ; SSE_SLOW-NEXT: movhlps {{.*#+}} xmm3 = xmm1[1],xmm3[1]
; SSE_SLOW-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm1[1]
; SSE_SLOW-NEXT: addsd %xmm1, %xmm3 ; SSE_SLOW-NEXT: addsd %xmm1, %xmm3
; SSE_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm2[0,0] ; SSE_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm2[0,0]
; SSE_SLOW-NEXT: movddup {{.*#+}} xmm1 = xmm3[0,0] ; SSE_SLOW-NEXT: movddup {{.*#+}} xmm1 = xmm3[0,0]
; SSE_SLOW-NEXT: retq ; SSE_SLOW-NEXT: retq
; ;
; SSE_FAST-LABEL: hadd_v4f64_scalar_splat: ; SSE_FAST-LABEL: hadd_v4f64_scalar_splat:
; SSE_FAST: # %bb.0: ; SSE_FAST: # %bb.0:
; SSE_FAST-NEXT: haddpd %xmm0, %xmm0 ; SSE_FAST-NEXT: haddpd %xmm0, %xmm0
Show All 14 Lines; AVX-NEXT: retq
%ins2 = insertelement <4 x double> %ins, double %hop1, i32 2 %ins2 = insertelement <4 x double> %ins, double %hop1, i32 2
%shuf = shufflevector <4 x double> %ins2, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2> %shuf = shufflevector <4 x double> %ins2, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
ret <4 x double> %shuf ret <4 x double> %shuf
} }
define <4 x double> @hadd_v4f64_scalar_broadcast(<4 x double> %a) { define <4 x double> @hadd_v4f64_scalar_broadcast(<4 x double> %a) {
; SSE_SLOW-LABEL: hadd_v4f64_scalar_broadcast: ; SSE_SLOW-LABEL: hadd_v4f64_scalar_broadcast:
; SSE_SLOW: # %bb.0: ; SSE_SLOW: # %bb.0:
; SSE_SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE_SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE_SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE_SLOW-NEXT: addsd %xmm0, %xmm1 ; SSE_SLOW-NEXT: addsd %xmm0, %xmm1
; SSE_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0] ; SSE_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
; SSE_SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE_SLOW-NEXT: movapd %xmm0, %xmm1
; SSE_SLOW-NEXT: retq ; SSE_SLOW-NEXT: retq
; ;
; SSE_FAST-LABEL: hadd_v4f64_scalar_broadcast: ; SSE_FAST-LABEL: hadd_v4f64_scalar_broadcast:
; SSE_FAST: # %bb.0: ; SSE_FAST: # %bb.0:
; SSE_FAST-NEXT: haddpd %xmm0, %xmm0 ; SSE_FAST-NEXT: haddpd %xmm0, %xmm0
Show All 36 Lines; AVX2_FAST-NEXT: retq
%ins2 = insertelement <4 x double> %ins, double %hop1, i32 2 %ins2 = insertelement <4 x double> %ins, double %hop1, i32 2
%shuf = shufflevector <4 x double> %ins2, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 0> %shuf = shufflevector <4 x double> %ins2, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
ret <4 x double> %shuf ret <4 x double> %shuf
} }
define <4 x double> @hadd_v4f64(<4 x double> %a) { define <4 x double> @hadd_v4f64(<4 x double> %a) {
; SSE_SLOW-LABEL: hadd_v4f64: ; SSE_SLOW-LABEL: hadd_v4f64:
; SSE_SLOW: # %bb.0: ; SSE_SLOW: # %bb.0:
; SSE_SLOW-NEXT: movapd %xmm0, %xmm2 ; SSE_SLOW-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE_SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE_SLOW-NEXT: addsd %xmm0, %xmm2 ; SSE_SLOW-NEXT: addsd %xmm0, %xmm2
; SSE_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm2[0,0] ; SSE_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm2[0,0]
; SSE_SLOW-NEXT: movapd %xmm1, %xmm2 ; SSE_SLOW-NEXT: xorps %xmm2, %xmm2
; SSE_SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE_SLOW-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE_SLOW-NEXT: addsd %xmm1, %xmm2 ; SSE_SLOW-NEXT: addsd %xmm1, %xmm2
; SSE_SLOW-NEXT: movddup {{.*#+}} xmm1 = xmm2[0,0] ; SSE_SLOW-NEXT: movddup {{.*#+}} xmm1 = xmm2[0,0]
; SSE_SLOW-NEXT: retq ; SSE_SLOW-NEXT: retq
; ;
; SSE_FAST-LABEL: hadd_v4f64: ; SSE_FAST-LABEL: hadd_v4f64:
; SSE_FAST: # %bb.0: ; SSE_FAST: # %bb.0:
; SSE_FAST-NEXT: haddpd %xmm0, %xmm0 ; SSE_FAST-NEXT: haddpd %xmm0, %xmm0
; SSE_FAST-NEXT: haddpd %xmm1, %xmm1 ; SSE_FAST-NEXT: haddpd %xmm1, %xmm1
; SSE_FAST-NEXT: retq ; SSE_FAST-NEXT: retq
; ;
; AVX-LABEL: hadd_v4f64: ; AVX-LABEL: hadd_v4f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vhaddpd %ymm0, %ymm0, %ymm0 ; AVX-NEXT: vhaddpd %ymm0, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%a0 = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef> %a0 = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>
%a1 = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef> %a1 = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>
%hop = fadd <4 x double> %a0, %a1 %hop = fadd <4 x double> %a0, %a1
%shuf = shufflevector <4 x double> %hop, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2> %shuf = shufflevector <4 x double> %hop, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
ret <4 x double> %shuf ret <4 x double> %shuf
} }
define <2 x double> @hsub_v2f64(<2 x double> %a) { define <2 x double> @hsub_v2f64(<2 x double> %a) {
; SSE_SLOW-LABEL: hsub_v2f64: ; SSE_SLOW-LABEL: hsub_v2f64:
; SSE_SLOW: # %bb.0: ; SSE_SLOW: # %bb.0:
; SSE_SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE_SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE_SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE_SLOW-NEXT: subsd %xmm1, %xmm0 ; SSE_SLOW-NEXT: subsd %xmm1, %xmm0
; SSE_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0] ; SSE_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
; SSE_SLOW-NEXT: retq ; SSE_SLOW-NEXT: retq
; ;
; SSE_FAST-LABEL: hsub_v2f64: ; SSE_FAST-LABEL: hsub_v2f64:
; SSE_FAST: # %bb.0: ; SSE_FAST: # %bb.0:
; SSE_FAST-NEXT: hsubpd %xmm0, %xmm0 ; SSE_FAST-NEXT: hsubpd %xmm0, %xmm0
; SSE_FAST-NEXT: retq ; SSE_FAST-NEXT: retq
Show All 26 Lines; AVX2_FAST-NEXT: retq
%hop = fsub <2 x double> %a0, %a1 %hop = fsub <2 x double> %a0, %a1
%shuf = shufflevector <2 x double> %hop, <2 x double> undef, <2 x i32> <i32 undef, i32 0> %shuf = shufflevector <2 x double> %hop, <2 x double> undef, <2 x i32> <i32 undef, i32 0>
ret <2 x double> %shuf ret <2 x double> %shuf
} }
define <4 x double> @hsub_v4f64(<4 x double> %a) { define <4 x double> @hsub_v4f64(<4 x double> %a) {
; SSE_SLOW-LABEL: hsub_v4f64: ; SSE_SLOW-LABEL: hsub_v4f64:
; SSE_SLOW: # %bb.0: ; SSE_SLOW: # %bb.0:
; SSE_SLOW-NEXT: movapd %xmm0, %xmm2 ; SSE_SLOW-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE_SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE_SLOW-NEXT: subsd %xmm2, %xmm0 ; SSE_SLOW-NEXT: subsd %xmm2, %xmm0
; SSE_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0] ; SSE_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
; SSE_SLOW-NEXT: movapd %xmm1, %xmm2 ; SSE_SLOW-NEXT: xorps %xmm2, %xmm2
; SSE_SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE_SLOW-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE_SLOW-NEXT: subsd %xmm2, %xmm1 ; SSE_SLOW-NEXT: subsd %xmm2, %xmm1
; SSE_SLOW-NEXT: movddup {{.*#+}} xmm1 = xmm1[0,0] ; SSE_SLOW-NEXT: movddup {{.*#+}} xmm1 = xmm1[0,0]
; SSE_SLOW-NEXT: retq ; SSE_SLOW-NEXT: retq
; ;
; SSE_FAST-LABEL: hsub_v4f64: ; SSE_FAST-LABEL: hsub_v4f64:
; SSE_FAST: # %bb.0: ; SSE_FAST: # %bb.0:
; SSE_FAST-NEXT: hsubpd %xmm0, %xmm0 ; SSE_FAST-NEXT: hsubpd %xmm0, %xmm0
; SSE_FAST-NEXT: hsubpd %xmm1, %xmm1 ; SSE_FAST-NEXT: hsubpd %xmm1, %xmm1
▲ Show 20 Lines • Show All 982 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/haddsub-undef.ll

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines; AVX-FAST-NEXT: retq
%add = fadd float %vecext, %vecext1 %add = fadd float %vecext, %vecext1
%vecinit = insertelement <4 x float> undef, float %add, i32 0 %vecinit = insertelement <4 x float> undef, float %add, i32 0
ret <4 x float> %vecinit ret <4 x float> %vecinit
} }
define <2 x double> @test5_undef(<2 x double> %a, <2 x double> %b) { define <2 x double> @test5_undef(<2 x double> %a, <2 x double> %b) {
; SSE-SLOW-LABEL: test5_undef: ; SSE-SLOW-LABEL: test5_undef:
; SSE-SLOW: # %bb.0: ; SSE-SLOW: # %bb.0:
; SSE-SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE-SLOW-NEXT: addsd %xmm1, %xmm0 ; SSE-SLOW-NEXT: addsd %xmm1, %xmm0
; SSE-SLOW-NEXT: retq ; SSE-SLOW-NEXT: retq
; ;
; SSE-FAST-LABEL: test5_undef: ; SSE-FAST-LABEL: test5_undef:
; SSE-FAST: # %bb.0: ; SSE-FAST: # %bb.0:
; SSE-FAST-NEXT: haddpd %xmm0, %xmm0 ; SSE-FAST-NEXT: haddpd %xmm0, %xmm0
; SSE-FAST-NEXT: retq ; SSE-FAST-NEXT: retq
; ;
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
ret <4 x float> %vecinit5 ret <4 x float> %vecinit5
} }
define <4 x float> @test8_undef(<4 x float> %a, <4 x float> %b) { define <4 x float> @test8_undef(<4 x float> %a, <4 x float> %b) {
; SSE-SLOW-LABEL: test8_undef: ; SSE-SLOW-LABEL: test8_undef:
; SSE-SLOW: # %bb.0: ; SSE-SLOW: # %bb.0:
; SSE-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE-SLOW-NEXT: addss %xmm0, %xmm1 ; SSE-SLOW-NEXT: addss %xmm0, %xmm1
; SSE-SLOW-NEXT: movaps %xmm0, %xmm2 ; SSE-SLOW-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE-SLOW-NEXT: addss %xmm2, %xmm0 ; SSE-SLOW-NEXT: addss %xmm2, %xmm0
; SSE-SLOW-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE-SLOW-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE-SLOW-NEXT: movaps %xmm1, %xmm0 ; SSE-SLOW-NEXT: movaps %xmm1, %xmm0
; SSE-SLOW-NEXT: retq ; SSE-SLOW-NEXT: retq
; ;
; SSE-FAST-LABEL: test8_undef: ; SSE-FAST-LABEL: test8_undef:
; SSE-FAST: # %bb.0: ; SSE-FAST: # %bb.0:
▲ Show 20 Lines • Show All 258 Lines • ▼ Show 20 Lines
; AVX-FAST-NEXT: vhaddpd %xmm0, %xmm0, %xmm0 ; AVX-FAST-NEXT: vhaddpd %xmm0, %xmm0, %xmm0
; AVX-FAST-NEXT: retq ; AVX-FAST-NEXT: retq
%l = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 1, i32 0> %l = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 1, i32 0>
%add = fadd <2 x double> %l, %x %add = fadd <2 x double> %l, %x
ret <2 x double> %add ret <2 x double> %add
} }
define <2 x double> @add_pd_010(<2 x double> %x) { define <2 x double> @add_pd_010(<2 x double> %x) {
; SSE-LABEL: add_pd_010: ; SSE-SLOW-LABEL: add_pd_010:
; SSE: # %bb.0: ; SSE-SLOW: # %bb.0:
; SSE-NEXT: haddpd %xmm0, %xmm0 ; SSE-SLOW-NEXT: movddup {{.*#+}} xmm1 = xmm0[0,0]
; SSE-NEXT: retq ; SSE-SLOW-NEXT: addpd %xmm1, %xmm0
; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; SSE-SLOW-NEXT: retq
;
; SSE-FAST-LABEL: add_pd_010:
; SSE-FAST: # %bb.0:
; SSE-FAST-NEXT: haddpd %xmm0, %xmm0
; SSE-FAST-NEXT: retq
; ;
; AVX-SLOW-LABEL: add_pd_010: ; AVX-SLOW-LABEL: add_pd_010:
; AVX-SLOW: # %bb.0: ; AVX-SLOW: # %bb.0:
; AVX-SLOW-NEXT: vmovddup {{.*#+}} xmm1 = xmm0[0,0] ; AVX-SLOW-NEXT: vmovddup {{.*#+}} xmm1 = xmm0[0,0]
; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX-SLOW-NEXT: vaddpd %xmm0, %xmm1, %xmm0 ; AVX-SLOW-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; AVX-SLOW-NEXT: retq ; AVX-SLOW-NEXT: retq
; ;
▲ Show 20 Lines • Show All 185 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
%add = fadd <4 x float> %l, %r %add = fadd <4 x float> %l, %r
%shuffle2 = shufflevector <4 x float> %add, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 undef> %shuffle2 = shufflevector <4 x float> %add, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 undef>
ret <4 x float> %shuffle2 ret <4 x float> %shuffle2
} }
define <4 x double> @add_pd_011(<4 x double> %0, <4 x double> %1) { define <4 x double> @add_pd_011(<4 x double> %0, <4 x double> %1) {
; SSE-SLOW-LABEL: add_pd_011: ; SSE-SLOW-LABEL: add_pd_011:
; SSE-SLOW: # %bb.0: ; SSE-SLOW: # %bb.0:
; SSE-SLOW-NEXT: movapd %xmm2, %xmm1 ; SSE-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE-SLOW-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; SSE-SLOW-NEXT: movapd %xmm0, %xmm3
; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; SSE-SLOW-NEXT: addpd %xmm3, %xmm0 ; SSE-SLOW-NEXT: addpd %xmm3, %xmm0
; SSE-SLOW-NEXT: addpd %xmm2, %xmm1 ; SSE-SLOW-NEXT: addpd %xmm2, %xmm1
; SSE-SLOW-NEXT: retq ; SSE-SLOW-NEXT: retq
; ;
; SSE-FAST-LABEL: add_pd_011: ; SSE-FAST-LABEL: add_pd_011:
; SSE-FAST: # %bb.0: ; SSE-FAST: # %bb.0:
; SSE-FAST-NEXT: movapd %xmm2, %xmm1 ; SSE-FAST-NEXT: movapd %xmm2, %xmm1
; SSE-FAST-NEXT: haddpd %xmm0, %xmm0 ; SSE-FAST-NEXT: haddpd %xmm0, %xmm0
▲ Show 20 Lines • Show All 271 Lines • ▼ Show 20 Lines; AVX-FAST-NEXT: retq
%t1 = fadd <4 x float> %t0, %a %t1 = fadd <4 x float> %t0, %a
%shuffle = shufflevector <4 x float> %t1, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 undef> %shuffle = shufflevector <4 x float> %t1, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 undef>
ret <4 x float> %shuffle ret <4 x float> %shuffle
} }
define <4 x float> @PR45747_2(<4 x float> %a, <4 x float> %b) nounwind { define <4 x float> @PR45747_2(<4 x float> %a, <4 x float> %b) nounwind {
; SSE-SLOW-LABEL: PR45747_2: ; SSE-SLOW-LABEL: PR45747_2:
; SSE-SLOW: # %bb.0: ; SSE-SLOW: # %bb.0:
; SSE-SLOW-NEXT: movaps %xmm1, %xmm0 ; SSE-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE-SLOW-NEXT: addps %xmm1, %xmm0 ; SSE-SLOW-NEXT: addps %xmm1, %xmm0
; SSE-SLOW-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-SLOW-NEXT: retq ; SSE-SLOW-NEXT: retq
; ;
; SSE-FAST-LABEL: PR45747_2: ; SSE-FAST-LABEL: PR45747_2:
; SSE-FAST: # %bb.0: ; SSE-FAST: # %bb.0:
; SSE-FAST-NEXT: haddps %xmm1, %xmm1 ; SSE-FAST-NEXT: haddps %xmm1, %xmm1
; SSE-FAST-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE-FAST-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
; SSE-FAST-NEXT: retq ; SSE-FAST-NEXT: retq
; ;
▲ Show 20 Lines • Show All 146 Lines • ▼ Show 20 Lines; AVX-FAST-NEXT: retq
%9 = shufflevector <4 x float> %6, <4 x float> %8, <4 x i32> <i32 0, i32 1, i32 4, i32 undef> %9 = shufflevector <4 x float> %6, <4 x float> %8, <4 x i32> <i32 0, i32 1, i32 4, i32 undef>
ret <4 x float> %9 ret <4 x float> %9
} }
define <4 x double> @PR34724_add_v4f64_u123(<4 x double> %0, <4 x double> %1) { define <4 x double> @PR34724_add_v4f64_u123(<4 x double> %0, <4 x double> %1) {
; SSE-SLOW-LABEL: PR34724_add_v4f64_u123: ; SSE-SLOW-LABEL: PR34724_add_v4f64_u123:
; SSE-SLOW: # %bb.0: ; SSE-SLOW: # %bb.0:
; SSE-SLOW-NEXT: haddpd %xmm2, %xmm1 ; SSE-SLOW-NEXT: haddpd %xmm2, %xmm1
; SSE-SLOW-NEXT: movapd %xmm3, %xmm2 ; SSE-SLOW-NEXT: xorps %xmm2, %xmm2
; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm3[1] ; SSE-SLOW-NEXT: movhlps {{.*#+}} xmm2 = xmm3[1],xmm2[1]
; SSE-SLOW-NEXT: addsd %xmm3, %xmm2 ; SSE-SLOW-NEXT: addsd %xmm3, %xmm2
; SSE-SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0] ; SSE-SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
; SSE-SLOW-NEXT: shufpd {{.*#+}} xmm1 = xmm1[1],xmm2[0] ; SSE-SLOW-NEXT: shufpd {{.*#+}} xmm1 = xmm1[1],xmm2[0]
; SSE-SLOW-NEXT: retq ; SSE-SLOW-NEXT: retq
; ;
; SSE-FAST-LABEL: PR34724_add_v4f64_u123: ; SSE-FAST-LABEL: PR34724_add_v4f64_u123:
; SSE-FAST: # %bb.0: ; SSE-FAST: # %bb.0:
; SSE-FAST-NEXT: movapd %xmm1, %xmm0 ; SSE-FAST-NEXT: movapd %xmm1, %xmm0
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines; AVX512-FAST-NEXT: retq
%13 = insertelement <4 x double> %9, double %12, i32 3 %13 = insertelement <4 x double> %9, double %12, i32 3
ret <4 x double> %13 ret <4 x double> %13
} }
define <4 x double> @PR34724_add_v4f64_0u23(<4 x double> %0, <4 x double> %1) { define <4 x double> @PR34724_add_v4f64_0u23(<4 x double> %0, <4 x double> %1) {
; SSE-SLOW-LABEL: PR34724_add_v4f64_0u23: ; SSE-SLOW-LABEL: PR34724_add_v4f64_0u23:
; SSE-SLOW: # %bb.0: ; SSE-SLOW: # %bb.0:
; SSE-SLOW-NEXT: haddpd %xmm2, %xmm0 ; SSE-SLOW-NEXT: haddpd %xmm2, %xmm0
; SSE-SLOW-NEXT: movapd %xmm3, %xmm2 ; SSE-SLOW-NEXT: xorps %xmm2, %xmm2
; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm3[1] ; SSE-SLOW-NEXT: movhlps {{.*#+}} xmm2 = xmm3[1],xmm2[1]
; SSE-SLOW-NEXT: addsd %xmm3, %xmm2 ; SSE-SLOW-NEXT: addsd %xmm3, %xmm2
; SSE-SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE-SLOW-NEXT: movapd %xmm0, %xmm1
; SSE-SLOW-NEXT: shufpd {{.*#+}} xmm1 = xmm1[1],xmm2[0] ; SSE-SLOW-NEXT: shufpd {{.*#+}} xmm1 = xmm1[1],xmm2[0]
; SSE-SLOW-NEXT: retq ; SSE-SLOW-NEXT: retq
; ;
; SSE-FAST-LABEL: PR34724_add_v4f64_0u23: ; SSE-FAST-LABEL: PR34724_add_v4f64_0u23:
; SSE-FAST: # %bb.0: ; SSE-FAST: # %bb.0:
; SSE-FAST-NEXT: movapd %xmm2, %xmm1 ; SSE-FAST-NEXT: movapd %xmm2, %xmm1
Show All 29 Lines; AVX-FAST-NEXT: retq
%13 = insertelement <4 x double> %9, double %12, i32 3 %13 = insertelement <4 x double> %9, double %12, i32 3
ret <4 x double> %13 ret <4 x double> %13
} }
define <4 x double> @PR34724_add_v4f64_01u3(<4 x double> %0, <4 x double> %1) { define <4 x double> @PR34724_add_v4f64_01u3(<4 x double> %0, <4 x double> %1) {
; SSE-SLOW-LABEL: PR34724_add_v4f64_01u3: ; SSE-SLOW-LABEL: PR34724_add_v4f64_01u3:
; SSE-SLOW: # %bb.0: ; SSE-SLOW: # %bb.0:
; SSE-SLOW-NEXT: haddpd %xmm1, %xmm0 ; SSE-SLOW-NEXT: haddpd %xmm1, %xmm0
; SSE-SLOW-NEXT: movapd %xmm3, %xmm1 ; SSE-SLOW-NEXT: xorps %xmm1, %xmm1
; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1] ; SSE-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE-SLOW-NEXT: addsd %xmm3, %xmm1 ; SSE-SLOW-NEXT: addsd %xmm3, %xmm1
; SSE-SLOW-NEXT: movddup {{.*#+}} xmm1 = xmm1[0,0] ; SSE-SLOW-NEXT: movddup {{.*#+}} xmm1 = xmm1[0,0]
; SSE-SLOW-NEXT: retq ; SSE-SLOW-NEXT: retq
; ;
; SSE-FAST-LABEL: PR34724_add_v4f64_01u3: ; SSE-FAST-LABEL: PR34724_add_v4f64_01u3:
; SSE-FAST: # %bb.0: ; SSE-FAST: # %bb.0:
; SSE-FAST-NEXT: haddpd %xmm1, %xmm0 ; SSE-FAST-NEXT: haddpd %xmm1, %xmm0
; SSE-FAST-NEXT: haddpd %xmm3, %xmm3 ; SSE-FAST-NEXT: haddpd %xmm3, %xmm3
Show All 36 Lines; AVX512-FAST-NEXT: retq
%13 = insertelement <4 x double> %9, double %12, i32 3 %13 = insertelement <4 x double> %9, double %12, i32 3
ret <4 x double> %13 ret <4 x double> %13
} }
define <4 x double> @PR34724_add_v4f64_012u(<4 x double> %0, <4 x double> %1) { define <4 x double> @PR34724_add_v4f64_012u(<4 x double> %0, <4 x double> %1) {
; SSE-SLOW-LABEL: PR34724_add_v4f64_012u: ; SSE-SLOW-LABEL: PR34724_add_v4f64_012u:
; SSE-SLOW: # %bb.0: ; SSE-SLOW: # %bb.0:
; SSE-SLOW-NEXT: haddpd %xmm1, %xmm0 ; SSE-SLOW-NEXT: haddpd %xmm1, %xmm0
; SSE-SLOW-NEXT: movapd %xmm2, %xmm1 ; SSE-SLOW-NEXT: xorps %xmm1, %xmm1
; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE-SLOW-NEXT: addsd %xmm2, %xmm1 ; SSE-SLOW-NEXT: addsd %xmm2, %xmm1
; SSE-SLOW-NEXT: retq ; SSE-SLOW-NEXT: retq
; ;
; SSE-FAST-LABEL: PR34724_add_v4f64_012u: ; SSE-FAST-LABEL: PR34724_add_v4f64_012u:
; SSE-FAST: # %bb.0: ; SSE-FAST: # %bb.0:
; SSE-FAST-NEXT: haddpd %xmm1, %xmm0 ; SSE-FAST-NEXT: haddpd %xmm1, %xmm0
; SSE-FAST-NEXT: haddpd %xmm2, %xmm2 ; SSE-FAST-NEXT: haddpd %xmm2, %xmm2
; SSE-FAST-NEXT: movapd %xmm2, %xmm1 ; SSE-FAST-NEXT: movapd %xmm2, %xmm1
Show All 31 Lines

llvm/test/CodeGen/X86/haddsub.ll

Show All 37 Lines; AVX-NEXT: retq
%b = shufflevector <2 x double> %y, <2 x double> %x, <2 x i32> <i32 2, i32 1> %b = shufflevector <2 x double> %y, <2 x double> %x, <2 x i32> <i32 2, i32 1>
%r = fadd <2 x double> %a, %b %r = fadd <2 x double> %a, %b
ret <2 x double> %r ret <2 x double> %r
} }
define <2 x double> @haddpd3(<2 x double> %x) { define <2 x double> @haddpd3(<2 x double> %x) {
; SSE3-SLOW-LABEL: haddpd3: ; SSE3-SLOW-LABEL: haddpd3:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addpd %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addpd %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: haddpd3: ; SSE3-FAST-LABEL: haddpd3:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: haddpd %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddpd %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%b = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 3> %b = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 3>
%r = fsub <2 x double> %a, %b %r = fsub <2 x double> %a, %b
ret <2 x double> %r ret <2 x double> %r
} }
define <2 x double> @hsubpd2(<2 x double> %x) { define <2 x double> @hsubpd2(<2 x double> %x) {
; SSE3-SLOW-LABEL: hsubpd2: ; SSE3-SLOW-LABEL: hsubpd2:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: subpd %xmm1, %xmm0 ; SSE3-SLOW-NEXT: subpd %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: hsubpd2: ; SSE3-FAST-LABEL: hsubpd2:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: hsubpd %xmm0, %xmm0 ; SSE3-FAST-NEXT: hsubpd %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
▲ Show 20 Lines • Show All 257 Lines • ▼ Show 20 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <4 x float> %x, i32 1 %x1 = extractelement <4 x float> %x, i32 1
%x01 = fadd float %x0, %x1 %x01 = fadd float %x0, %x1
ret float %x01 ret float %x01
} }
define float @extract_extract23_v4f32_fadd_f32(<4 x float> %x) { define float @extract_extract23_v4f32_fadd_f32(<4 x float> %x) {
; SSE3-SLOW-LABEL: extract_extract23_v4f32_fadd_f32: ; SSE3-SLOW-LABEL: extract_extract23_v4f32_fadd_f32:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract23_v4f32_fadd_f32: ; SSE3-FAST-LABEL: extract_extract23_v4f32_fadd_f32:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSE3-FAST-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE3-FAST-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <4 x float> %x, i32 1 %x1 = extractelement <4 x float> %x, i32 1
%x01 = fadd float %x1, %x0 %x01 = fadd float %x1, %x0
ret float %x01 ret float %x01
} }
define float @extract_extract23_v4f32_fadd_f32_commute(<4 x float> %x) { define float @extract_extract23_v4f32_fadd_f32_commute(<4 x float> %x) {
; SSE3-SLOW-LABEL: extract_extract23_v4f32_fadd_f32_commute: ; SSE3-SLOW-LABEL: extract_extract23_v4f32_fadd_f32_commute:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract23_v4f32_fadd_f32_commute: ; SSE3-FAST-LABEL: extract_extract23_v4f32_fadd_f32_commute:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSE3-FAST-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE3-FAST-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
Show All 15 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <4 x float> %x, i32 3 %x1 = extractelement <4 x float> %x, i32 3
%x01 = fadd float %x1, %x0 %x01 = fadd float %x1, %x0
ret float %x01 ret float %x01
} }
define double @extract_extract01_v2f64_fadd_f64(<2 x double> %x) { define double @extract_extract01_v2f64_fadd_f64(<2 x double> %x) {
; SSE3-SLOW-LABEL: extract_extract01_v2f64_fadd_f64: ; SSE3-SLOW-LABEL: extract_extract01_v2f64_fadd_f64:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addsd %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addsd %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract01_v2f64_fadd_f64: ; SSE3-FAST-LABEL: extract_extract01_v2f64_fadd_f64:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: haddpd %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddpd %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
Show All 11 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <2 x double> %x, i32 1 %x1 = extractelement <2 x double> %x, i32 1
%x01 = fadd double %x0, %x1 %x01 = fadd double %x0, %x1
ret double %x01 ret double %x01
} }
define double @extract_extract01_v2f64_fadd_f64_commute(<2 x double> %x) { define double @extract_extract01_v2f64_fadd_f64_commute(<2 x double> %x) {
; SSE3-SLOW-LABEL: extract_extract01_v2f64_fadd_f64_commute: ; SSE3-SLOW-LABEL: extract_extract01_v2f64_fadd_f64_commute:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addsd %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addsd %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract01_v2f64_fadd_f64_commute: ; SSE3-FAST-LABEL: extract_extract01_v2f64_fadd_f64_commute:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: haddpd %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddpd %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
Show All 39 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <4 x float> %x, i32 1 %x1 = extractelement <4 x float> %x, i32 1
%x01 = fsub float %x0, %x1 %x01 = fsub float %x0, %x1
ret float %x01 ret float %x01
} }
define float @extract_extract23_v4f32_fsub_f32(<4 x float> %x) { define float @extract_extract23_v4f32_fsub_f32(<4 x float> %x) {
; SSE3-SLOW-LABEL: extract_extract23_v4f32_fsub_f32: ; SSE3-SLOW-LABEL: extract_extract23_v4f32_fsub_f32:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE3-SLOW-NEXT: subss %xmm0, %xmm1 ; SSE3-SLOW-NEXT: subss %xmm0, %xmm1
; SSE3-SLOW-NEXT: movaps %xmm1, %xmm0 ; SSE3-SLOW-NEXT: movaps %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract23_v4f32_fsub_f32: ; SSE3-FAST-LABEL: extract_extract23_v4f32_fsub_f32:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: hsubps %xmm0, %xmm0 ; SSE3-FAST-NEXT: hsubps %xmm0, %xmm0
Show All 35 Lines; AVX-NEXT: retq
%x1 = extractelement <4 x float> %x, i32 1 %x1 = extractelement <4 x float> %x, i32 1
%x01 = fsub float %x1, %x0 %x01 = fsub float %x1, %x0
ret float %x01 ret float %x01
} }
define float @extract_extract23_v4f32_fsub_f32_commute(<4 x float> %x) { define float @extract_extract23_v4f32_fsub_f32_commute(<4 x float> %x) {
; SSE3-LABEL: extract_extract23_v4f32_fsub_f32_commute: ; SSE3-LABEL: extract_extract23_v4f32_fsub_f32_commute:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movaps %xmm0, %xmm1 ; SSE3-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE3-NEXT: subss %xmm1, %xmm0 ; SSE3-NEXT: subss %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: extract_extract23_v4f32_fsub_f32_commute: ; AVX-LABEL: extract_extract23_v4f32_fsub_f32_commute:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; AVX-NEXT: vsubss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vsubss %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%x0 = extractelement <4 x float> %x, i32 2 %x0 = extractelement <4 x float> %x, i32 2
%x1 = extractelement <4 x float> %x, i32 3 %x1 = extractelement <4 x float> %x, i32 3
%x01 = fsub float %x1, %x0 %x01 = fsub float %x1, %x0
ret float %x01 ret float %x01
} }
define double @extract_extract01_v2f64_fsub_f64(<2 x double> %x) { define double @extract_extract01_v2f64_fsub_f64(<2 x double> %x) {
; SSE3-SLOW-LABEL: extract_extract01_v2f64_fsub_f64: ; SSE3-SLOW-LABEL: extract_extract01_v2f64_fsub_f64:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: subsd %xmm1, %xmm0 ; SSE3-SLOW-NEXT: subsd %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract01_v2f64_fsub_f64: ; SSE3-FAST-LABEL: extract_extract01_v2f64_fsub_f64:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: hsubpd %xmm0, %xmm0 ; SSE3-FAST-NEXT: hsubpd %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
Show All 11 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <2 x double> %x, i32 1 %x1 = extractelement <2 x double> %x, i32 1
%x01 = fsub double %x0, %x1 %x01 = fsub double %x0, %x1
ret double %x01 ret double %x01
} }
define double @extract_extract01_v2f64_fsub_f64_commute(<2 x double> %x) { define double @extract_extract01_v2f64_fsub_f64_commute(<2 x double> %x) {
; SSE3-LABEL: extract_extract01_v2f64_fsub_f64_commute: ; SSE3-LABEL: extract_extract01_v2f64_fsub_f64_commute:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movapd %xmm0, %xmm1 ; SSE3-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-NEXT: subsd %xmm0, %xmm1 ; SSE3-NEXT: subsd %xmm0, %xmm1
; SSE3-NEXT: movapd %xmm1, %xmm0 ; SSE3-NEXT: movapd %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: extract_extract01_v2f64_fsub_f64_commute: ; AVX-LABEL: extract_extract01_v2f64_fsub_f64_commute:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vsubsd %xmm0, %xmm1, %xmm0 ; AVX-NEXT: vsubsd %xmm0, %xmm1, %xmm0
Show All 34 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <8 x float> %x, i32 1 %x1 = extractelement <8 x float> %x, i32 1
%x01 = fadd float %x0, %x1 %x01 = fadd float %x0, %x1
ret float %x01 ret float %x01
} }
define float @extract_extract23_v8f32_fadd_f32(<8 x float> %x) { define float @extract_extract23_v8f32_fadd_f32(<8 x float> %x) {
; SSE3-SLOW-LABEL: extract_extract23_v8f32_fadd_f32: ; SSE3-SLOW-LABEL: extract_extract23_v8f32_fadd_f32:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract23_v8f32_fadd_f32: ; SSE3-FAST-LABEL: extract_extract23_v8f32_fadd_f32:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSE3-FAST-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE3-FAST-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
Show All 17 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <8 x float> %x, i32 3 %x1 = extractelement <8 x float> %x, i32 3
%x01 = fadd float %x0, %x1 %x01 = fadd float %x0, %x1
ret float %x01 ret float %x01
} }
define float @extract_extract67_v8f32_fadd_f32(<8 x float> %x) { define float @extract_extract67_v8f32_fadd_f32(<8 x float> %x) {
; SSE3-SLOW-LABEL: extract_extract67_v8f32_fadd_f32: ; SSE3-SLOW-LABEL: extract_extract67_v8f32_fadd_f32:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm1, %xmm0 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract67_v8f32_fadd_f32: ; SSE3-FAST-LABEL: extract_extract67_v8f32_fadd_f32:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: haddps %xmm1, %xmm1 ; SSE3-FAST-NEXT: haddps %xmm1, %xmm1
; SSE3-FAST-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE3-FAST-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <8 x float> %x, i32 1 %x1 = extractelement <8 x float> %x, i32 1
%x01 = fadd float %x1, %x0 %x01 = fadd float %x1, %x0
ret float %x01 ret float %x01
} }
define float @extract_extract23_v8f32_fadd_f32_commute(<8 x float> %x) { define float @extract_extract23_v8f32_fadd_f32_commute(<8 x float> %x) {
; SSE3-SLOW-LABEL: extract_extract23_v8f32_fadd_f32_commute: ; SSE3-SLOW-LABEL: extract_extract23_v8f32_fadd_f32_commute:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract23_v8f32_fadd_f32_commute: ; SSE3-FAST-LABEL: extract_extract23_v8f32_fadd_f32_commute:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSE3-FAST-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE3-FAST-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
Show All 17 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <8 x float> %x, i32 3 %x1 = extractelement <8 x float> %x, i32 3
%x01 = fadd float %x1, %x0 %x01 = fadd float %x1, %x0
ret float %x01 ret float %x01
} }
define float @extract_extract67_v8f32_fadd_f32_commute(<8 x float> %x) { define float @extract_extract67_v8f32_fadd_f32_commute(<8 x float> %x) {
; SSE3-SLOW-LABEL: extract_extract67_v8f32_fadd_f32_commute: ; SSE3-SLOW-LABEL: extract_extract67_v8f32_fadd_f32_commute:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm1, %xmm0 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract67_v8f32_fadd_f32_commute: ; SSE3-FAST-LABEL: extract_extract67_v8f32_fadd_f32_commute:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: haddps %xmm1, %xmm1 ; SSE3-FAST-NEXT: haddps %xmm1, %xmm1
; SSE3-FAST-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE3-FAST-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
Show All 19 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <8 x float> %x, i32 7 %x1 = extractelement <8 x float> %x, i32 7
%x01 = fadd float %x1, %x0 %x01 = fadd float %x1, %x0
ret float %x01 ret float %x01
} }
define double @extract_extract01_v4f64_fadd_f64(<4 x double> %x) { define double @extract_extract01_v4f64_fadd_f64(<4 x double> %x) {
; SSE3-SLOW-LABEL: extract_extract01_v4f64_fadd_f64: ; SSE3-SLOW-LABEL: extract_extract01_v4f64_fadd_f64:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addsd %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addsd %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract01_v4f64_fadd_f64: ; SSE3-FAST-LABEL: extract_extract01_v4f64_fadd_f64:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: haddpd %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddpd %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
Show All 13 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <4 x double> %x, i32 1 %x1 = extractelement <4 x double> %x, i32 1
%x01 = fadd double %x0, %x1 %x01 = fadd double %x0, %x1
ret double %x01 ret double %x01
} }
define double @extract_extract23_v4f64_fadd_f64(<4 x double> %x) { define double @extract_extract23_v4f64_fadd_f64(<4 x double> %x) {
; SSE3-SLOW-LABEL: extract_extract23_v4f64_fadd_f64: ; SSE3-SLOW-LABEL: extract_extract23_v4f64_fadd_f64:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movapd %xmm1, %xmm0 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: addsd %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addsd %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract23_v4f64_fadd_f64: ; SSE3-FAST-LABEL: extract_extract23_v4f64_fadd_f64:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: movapd %xmm1, %xmm0 ; SSE3-FAST-NEXT: movapd %xmm1, %xmm0
; SSE3-FAST-NEXT: haddpd %xmm1, %xmm0 ; SSE3-FAST-NEXT: haddpd %xmm1, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
Show All 16 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <4 x double> %x, i32 3 %x1 = extractelement <4 x double> %x, i32 3
%x01 = fadd double %x0, %x1 %x01 = fadd double %x0, %x1
ret double %x01 ret double %x01
} }
define double @extract_extract01_v4f64_fadd_f64_commute(<4 x double> %x) { define double @extract_extract01_v4f64_fadd_f64_commute(<4 x double> %x) {
; SSE3-SLOW-LABEL: extract_extract01_v4f64_fadd_f64_commute: ; SSE3-SLOW-LABEL: extract_extract01_v4f64_fadd_f64_commute:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addsd %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addsd %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract01_v4f64_fadd_f64_commute: ; SSE3-FAST-LABEL: extract_extract01_v4f64_fadd_f64_commute:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: haddpd %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddpd %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
Show All 13 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <4 x double> %x, i32 1 %x1 = extractelement <4 x double> %x, i32 1
%x01 = fadd double %x1, %x0 %x01 = fadd double %x1, %x0
ret double %x01 ret double %x01
} }
define double @extract_extract23_v4f64_fadd_f64_commute(<4 x double> %x) { define double @extract_extract23_v4f64_fadd_f64_commute(<4 x double> %x) {
; SSE3-SLOW-LABEL: extract_extract23_v4f64_fadd_f64_commute: ; SSE3-SLOW-LABEL: extract_extract23_v4f64_fadd_f64_commute:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movapd %xmm1, %xmm0 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: addsd %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addsd %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract23_v4f64_fadd_f64_commute: ; SSE3-FAST-LABEL: extract_extract23_v4f64_fadd_f64_commute:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: movapd %xmm1, %xmm0 ; SSE3-FAST-NEXT: movapd %xmm1, %xmm0
; SSE3-FAST-NEXT: haddpd %xmm1, %xmm0 ; SSE3-FAST-NEXT: haddpd %xmm1, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <8 x float> %x, i32 1 %x1 = extractelement <8 x float> %x, i32 1
%x01 = fsub float %x0, %x1 %x01 = fsub float %x0, %x1
ret float %x01 ret float %x01
} }
define float @extract_extract23_v8f32_fsub_f32(<8 x float> %x) { define float @extract_extract23_v8f32_fsub_f32(<8 x float> %x) {
; SSE3-SLOW-LABEL: extract_extract23_v8f32_fsub_f32: ; SSE3-SLOW-LABEL: extract_extract23_v8f32_fsub_f32:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE3-SLOW-NEXT: subss %xmm0, %xmm1 ; SSE3-SLOW-NEXT: subss %xmm0, %xmm1
; SSE3-SLOW-NEXT: movaps %xmm1, %xmm0 ; SSE3-SLOW-NEXT: movaps %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract23_v8f32_fsub_f32: ; SSE3-FAST-LABEL: extract_extract23_v8f32_fsub_f32:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: hsubps %xmm0, %xmm0 ; SSE3-FAST-NEXT: hsubps %xmm0, %xmm0
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%x1 = extractelement <8 x float> %x, i32 1 %x1 = extractelement <8 x float> %x, i32 1
%x01 = fsub float %x1, %x0 %x01 = fsub float %x1, %x0
ret float %x01 ret float %x01
} }
define double @extract_extract01_v4f64_fsub_f64(<4 x double> %x) { define double @extract_extract01_v4f64_fsub_f64(<4 x double> %x) {
; SSE3-SLOW-LABEL: extract_extract01_v4f64_fsub_f64: ; SSE3-SLOW-LABEL: extract_extract01_v4f64_fsub_f64:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: subsd %xmm1, %xmm0 ; SSE3-SLOW-NEXT: subsd %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract01_v4f64_fsub_f64: ; SSE3-FAST-LABEL: extract_extract01_v4f64_fsub_f64:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: hsubpd %xmm0, %xmm0 ; SSE3-FAST-NEXT: hsubpd %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
Show All 15 Lines; AVX-FAST-NEXT: retq
ret double %x01 ret double %x01
} }
; Negative test...or get hoppy and negate? ; Negative test...or get hoppy and negate?
define double @extract_extract01_v4f64_fsub_f64_commute(<4 x double> %x) { define double @extract_extract01_v4f64_fsub_f64_commute(<4 x double> %x) {
; SSE3-LABEL: extract_extract01_v4f64_fsub_f64_commute: ; SSE3-LABEL: extract_extract01_v4f64_fsub_f64_commute:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movapd %xmm0, %xmm1 ; SSE3-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-NEXT: subsd %xmm0, %xmm1 ; SSE3-NEXT: subsd %xmm0, %xmm1
; SSE3-NEXT: movapd %xmm1, %xmm0 ; SSE3-NEXT: movapd %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: extract_extract01_v4f64_fsub_f64_commute: ; AVX-LABEL: extract_extract01_v4f64_fsub_f64_commute:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vsubsd %xmm0, %xmm1, %xmm0 ; AVX-NEXT: vsubsd %xmm0, %xmm1, %xmm0
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <16 x float> %x, i32 1 %x1 = extractelement <16 x float> %x, i32 1
%x01 = fadd float %x1, %x0 %x01 = fadd float %x1, %x0
ret float %x01 ret float %x01
} }
define double @extract_extract01_v8f64_fadd_f64(<8 x double> %x) { define double @extract_extract01_v8f64_fadd_f64(<8 x double> %x) {
; SSE3-SLOW-LABEL: extract_extract01_v8f64_fadd_f64: ; SSE3-SLOW-LABEL: extract_extract01_v8f64_fadd_f64:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addsd %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addsd %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract01_v8f64_fadd_f64: ; SSE3-FAST-LABEL: extract_extract01_v8f64_fadd_f64:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: haddpd %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddpd %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
Show All 13 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <8 x double> %x, i32 1 %x1 = extractelement <8 x double> %x, i32 1
%x01 = fadd double %x0, %x1 %x01 = fadd double %x0, %x1
ret double %x01 ret double %x01
} }
define double @extract_extract01_v8f64_fadd_f64_commute(<8 x double> %x) { define double @extract_extract01_v8f64_fadd_f64_commute(<8 x double> %x) {
; SSE3-SLOW-LABEL: extract_extract01_v8f64_fadd_f64_commute: ; SSE3-SLOW-LABEL: extract_extract01_v8f64_fadd_f64_commute:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addsd %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addsd %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract01_v8f64_fadd_f64_commute: ; SSE3-FAST-LABEL: extract_extract01_v8f64_fadd_f64_commute:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: haddpd %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddpd %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%x1 = extractelement <16 x float> %x, i32 1 %x1 = extractelement <16 x float> %x, i32 1
%x01 = fsub float %x1, %x0 %x01 = fsub float %x1, %x0
ret float %x01 ret float %x01
} }
define double @extract_extract01_v8f64_fsub_f64(<8 x double> %x) { define double @extract_extract01_v8f64_fsub_f64(<8 x double> %x) {
; SSE3-SLOW-LABEL: extract_extract01_v8f64_fsub_f64: ; SSE3-SLOW-LABEL: extract_extract01_v8f64_fsub_f64:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movapd %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: subsd %xmm1, %xmm0 ; SSE3-SLOW-NEXT: subsd %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: extract_extract01_v8f64_fsub_f64: ; SSE3-FAST-LABEL: extract_extract01_v8f64_fsub_f64:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: hsubpd %xmm0, %xmm0 ; SSE3-FAST-NEXT: hsubpd %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
Show All 13 Lines; AVX-FAST-NEXT: retq
%x1 = extractelement <8 x double> %x, i32 1 %x1 = extractelement <8 x double> %x, i32 1
%x01 = fsub double %x0, %x1 %x01 = fsub double %x0, %x1
ret double %x01 ret double %x01
} }
define double @extract_extract01_v8f64_fsub_f64_commute(<8 x double> %x) { define double @extract_extract01_v8f64_fsub_f64_commute(<8 x double> %x) {
; SSE3-LABEL: extract_extract01_v8f64_fsub_f64_commute: ; SSE3-LABEL: extract_extract01_v8f64_fsub_f64_commute:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movapd %xmm0, %xmm1 ; SSE3-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-NEXT: subsd %xmm0, %xmm1 ; SSE3-NEXT: subsd %xmm0, %xmm1
; SSE3-NEXT: movapd %xmm1, %xmm0 ; SSE3-NEXT: movapd %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: extract_extract01_v8f64_fsub_f64_commute: ; AVX-LABEL: extract_extract01_v8f64_fsub_f64_commute:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vsubsd %xmm0, %xmm1, %xmm0 ; AVX-NEXT: vsubsd %xmm0, %xmm1, %xmm0
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines
declare float @llvm.vector.reduce.fadd.f32.v8f32(float, <8 x float>) declare float @llvm.vector.reduce.fadd.f32.v8f32(float, <8 x float>)
declare double @llvm.vector.reduce.fadd.f64.v4f64(double, <4 x double>) declare double @llvm.vector.reduce.fadd.f64.v4f64(double, <4 x double>)
define float @fadd_reduce_v8f32(float %a0, <8 x float> %a1) { define float @fadd_reduce_v8f32(float %a0, <8 x float> %a1) {
; SSE3-SLOW-LABEL: fadd_reduce_v8f32: ; SSE3-SLOW-LABEL: fadd_reduce_v8f32:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: addps %xmm2, %xmm1 ; SSE3-SLOW-NEXT: addps %xmm2, %xmm1
; SSE3-SLOW-NEXT: movaps %xmm1, %xmm2 ; SSE3-SLOW-NEXT: xorps %xmm2, %xmm2
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE3-SLOW-NEXT: addps %xmm1, %xmm2 ; SSE3-SLOW-NEXT: addps %xmm1, %xmm2
; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE3-SLOW-NEXT: addss %xmm2, %xmm1 ; SSE3-SLOW-NEXT: addss %xmm2, %xmm1
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: fadd_reduce_v8f32: ; SSE3-FAST-LABEL: fadd_reduce_v8f32:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
Show All 27 Lines; AVX-FAST-NEXT: retq
%r = call fast float @llvm.vector.reduce.fadd.f32.v8f32(float %a0, <8 x float> %a1) %r = call fast float @llvm.vector.reduce.fadd.f32.v8f32(float %a0, <8 x float> %a1)
ret float %r ret float %r
} }
define double @fadd_reduce_v4f64(double %a0, <4 x double> %a1) { define double @fadd_reduce_v4f64(double %a0, <4 x double> %a1) {
; SSE3-SLOW-LABEL: fadd_reduce_v4f64: ; SSE3-SLOW-LABEL: fadd_reduce_v4f64:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: addpd %xmm2, %xmm1 ; SSE3-SLOW-NEXT: addpd %xmm2, %xmm1
; SSE3-SLOW-NEXT: movapd %xmm1, %xmm2 ; SSE3-SLOW-NEXT: xorps %xmm2, %xmm2
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE3-SLOW-NEXT: addsd %xmm1, %xmm2 ; SSE3-SLOW-NEXT: addsd %xmm1, %xmm2
; SSE3-SLOW-NEXT: addsd %xmm2, %xmm0 ; SSE3-SLOW-NEXT: addsd %xmm2, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: fadd_reduce_v4f64: ; SSE3-FAST-LABEL: fadd_reduce_v4f64:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: haddpd %xmm1, %xmm2 ; SSE3-FAST-NEXT: haddpd %xmm1, %xmm2
; SSE3-FAST-NEXT: haddpd %xmm2, %xmm2 ; SSE3-FAST-NEXT: haddpd %xmm2, %xmm2
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines; AVX-FAST-NEXT: retq
%9 = fadd <8 x float> %7, %8 %9 = fadd <8 x float> %7, %8
%10 = extractelement <8 x float> %9, i32 0 %10 = extractelement <8 x float> %9, i32 0
ret float %10 ret float %10
} }
define float @hadd32_4(<4 x float> %x225) { define float @hadd32_4(<4 x float> %x225) {
; SSE3-SLOW-LABEL: hadd32_4: ; SSE3-SLOW-LABEL: hadd32_4:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addps %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: hadd32_4: ; SSE3-FAST-LABEL: hadd32_4:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: movaps %xmm0, %xmm1 ; SSE3-FAST-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-FAST-NEXT: addps %xmm1, %xmm0 ; SSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
; AVX-SLOW-LABEL: hadd32_4: ; AVX-SLOW-LABEL: hadd32_4:
; AVX-SLOW: # %bb.0: ; AVX-SLOW: # %bb.0:
; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
Show All 13 Lines; AVX-FAST-NEXT: retq
%x229 = fadd <4 x float> %x227, %x228 %x229 = fadd <4 x float> %x227, %x228
%x230 = extractelement <4 x float> %x229, i32 0 %x230 = extractelement <4 x float> %x229, i32 0
ret float %x230 ret float %x230
} }
define float @hadd32_8(<8 x float> %x225) { define float @hadd32_8(<8 x float> %x225) {
; SSE3-SLOW-LABEL: hadd32_8: ; SSE3-SLOW-LABEL: hadd32_8:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addps %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: hadd32_8: ; SSE3-FAST-LABEL: hadd32_8:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: movaps %xmm0, %xmm1 ; SSE3-FAST-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-FAST-NEXT: addps %xmm1, %xmm0 ; SSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
; AVX-SLOW-LABEL: hadd32_8: ; AVX-SLOW-LABEL: hadd32_8:
; AVX-SLOW: # %bb.0: ; AVX-SLOW: # %bb.0:
; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
Show All 15 Lines; AVX-FAST-NEXT: retq
%x229 = fadd <8 x float> %x227, %x228 %x229 = fadd <8 x float> %x227, %x228
%x230 = extractelement <8 x float> %x229, i32 0 %x230 = extractelement <8 x float> %x229, i32 0
ret float %x230 ret float %x230
} }
define float @hadd32_16(<16 x float> %x225) { define float @hadd32_16(<16 x float> %x225) {
; SSE3-SLOW-LABEL: hadd32_16: ; SSE3-SLOW-LABEL: hadd32_16:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addps %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: hadd32_16: ; SSE3-FAST-LABEL: hadd32_16:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: movaps %xmm0, %xmm1 ; SSE3-FAST-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-FAST-NEXT: addps %xmm1, %xmm0 ; SSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
; AVX-SLOW-LABEL: hadd32_16: ; AVX-SLOW-LABEL: hadd32_16:
; AVX-SLOW: # %bb.0: ; AVX-SLOW: # %bb.0:
; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
Show All 15 Lines; AVX-FAST-NEXT: retq
%x229 = fadd <16 x float> %x227, %x228 %x229 = fadd <16 x float> %x227, %x228
%x230 = extractelement <16 x float> %x229, i32 0 %x230 = extractelement <16 x float> %x229, i32 0
ret float %x230 ret float %x230
} }
define float @hadd32_4_optsize(<4 x float> %x225) optsize { define float @hadd32_4_optsize(<4 x float> %x225) optsize {
; SSE3-LABEL: hadd32_4_optsize: ; SSE3-LABEL: hadd32_4_optsize:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movaps %xmm0, %xmm1 ; SSE3-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-NEXT: addps %xmm1, %xmm0 ; SSE3-NEXT: addps %xmm1, %xmm0
; SSE3-NEXT: haddps %xmm0, %xmm0 ; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: hadd32_4_optsize: ; AVX-LABEL: hadd32_4_optsize:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%x226 = shufflevector <4 x float> %x225, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef> %x226 = shufflevector <4 x float> %x225, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
%x227 = fadd <4 x float> %x225, %x226 %x227 = fadd <4 x float> %x225, %x226
%x228 = shufflevector <4 x float> %x227, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %x228 = shufflevector <4 x float> %x227, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
%x229 = fadd <4 x float> %x227, %x228 %x229 = fadd <4 x float> %x227, %x228
%x230 = extractelement <4 x float> %x229, i32 0 %x230 = extractelement <4 x float> %x229, i32 0
ret float %x230 ret float %x230
} }
define float @hadd32_8_optsize(<8 x float> %x225) optsize { define float @hadd32_8_optsize(<8 x float> %x225) optsize {
; SSE3-LABEL: hadd32_8_optsize: ; SSE3-LABEL: hadd32_8_optsize:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movaps %xmm0, %xmm1 ; SSE3-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-NEXT: addps %xmm1, %xmm0 ; SSE3-NEXT: addps %xmm1, %xmm0
; SSE3-NEXT: haddps %xmm0, %xmm0 ; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: hadd32_8_optsize: ; AVX-LABEL: hadd32_8_optsize:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
%x226 = shufflevector <8 x float> %x225, <8 x float> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %x226 = shufflevector <8 x float> %x225, <8 x float> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%x227 = fadd <8 x float> %x225, %x226 %x227 = fadd <8 x float> %x225, %x226
%x228 = shufflevector <8 x float> %x227, <8 x float> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %x228 = shufflevector <8 x float> %x227, <8 x float> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%x229 = fadd <8 x float> %x227, %x228 %x229 = fadd <8 x float> %x227, %x228
%x230 = extractelement <8 x float> %x229, i32 0 %x230 = extractelement <8 x float> %x229, i32 0
ret float %x230 ret float %x230
} }
define float @hadd32_16_optsize(<16 x float> %x225) optsize { define float @hadd32_16_optsize(<16 x float> %x225) optsize {
; SSE3-LABEL: hadd32_16_optsize: ; SSE3-LABEL: hadd32_16_optsize:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movaps %xmm0, %xmm1 ; SSE3-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-NEXT: addps %xmm1, %xmm0 ; SSE3-NEXT: addps %xmm1, %xmm0
; SSE3-NEXT: haddps %xmm0, %xmm0 ; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: hadd32_16_optsize: ; AVX-LABEL: hadd32_16_optsize:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
%x226 = shufflevector <16 x float> %x225, <16 x float> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %x226 = shufflevector <16 x float> %x225, <16 x float> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%x227 = fadd <16 x float> %x225, %x226 %x227 = fadd <16 x float> %x225, %x226
%x228 = shufflevector <16 x float> %x227, <16 x float> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %x228 = shufflevector <16 x float> %x227, <16 x float> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%x229 = fadd <16 x float> %x227, %x228 %x229 = fadd <16 x float> %x227, %x228
%x230 = extractelement <16 x float> %x229, i32 0 %x230 = extractelement <16 x float> %x229, i32 0
ret float %x230 ret float %x230
} }
define float @hadd32_4_pgso(<4 x float> %x225) !prof !14 { define float @hadd32_4_pgso(<4 x float> %x225) !prof !14 {
; SSE3-LABEL: hadd32_4_pgso: ; SSE3-LABEL: hadd32_4_pgso:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movaps %xmm0, %xmm1 ; SSE3-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-NEXT: addps %xmm1, %xmm0 ; SSE3-NEXT: addps %xmm1, %xmm0
; SSE3-NEXT: haddps %xmm0, %xmm0 ; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: hadd32_4_pgso: ; AVX-LABEL: hadd32_4_pgso:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%x226 = shufflevector <4 x float> %x225, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef> %x226 = shufflevector <4 x float> %x225, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
%x227 = fadd <4 x float> %x225, %x226 %x227 = fadd <4 x float> %x225, %x226
%x228 = shufflevector <4 x float> %x227, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %x228 = shufflevector <4 x float> %x227, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
%x229 = fadd <4 x float> %x227, %x228 %x229 = fadd <4 x float> %x227, %x228
%x230 = extractelement <4 x float> %x229, i32 0 %x230 = extractelement <4 x float> %x229, i32 0
ret float %x230 ret float %x230
} }
define float @hadd32_8_pgso(<8 x float> %x225) !prof !14 { define float @hadd32_8_pgso(<8 x float> %x225) !prof !14 {
; SSE3-LABEL: hadd32_8_pgso: ; SSE3-LABEL: hadd32_8_pgso:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movaps %xmm0, %xmm1 ; SSE3-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-NEXT: addps %xmm1, %xmm0 ; SSE3-NEXT: addps %xmm1, %xmm0
; SSE3-NEXT: haddps %xmm0, %xmm0 ; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: hadd32_8_pgso: ; AVX-LABEL: hadd32_8_pgso:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
%x226 = shufflevector <8 x float> %x225, <8 x float> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %x226 = shufflevector <8 x float> %x225, <8 x float> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%x227 = fadd <8 x float> %x225, %x226 %x227 = fadd <8 x float> %x225, %x226
%x228 = shufflevector <8 x float> %x227, <8 x float> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %x228 = shufflevector <8 x float> %x227, <8 x float> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%x229 = fadd <8 x float> %x227, %x228 %x229 = fadd <8 x float> %x227, %x228
%x230 = extractelement <8 x float> %x229, i32 0 %x230 = extractelement <8 x float> %x229, i32 0
ret float %x230 ret float %x230
} }
define float @hadd32_16_pgso(<16 x float> %x225) !prof !14 { define float @hadd32_16_pgso(<16 x float> %x225) !prof !14 {
; SSE3-LABEL: hadd32_16_pgso: ; SSE3-LABEL: hadd32_16_pgso:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movaps %xmm0, %xmm1 ; SSE3-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-NEXT: addps %xmm1, %xmm0 ; SSE3-NEXT: addps %xmm1, %xmm0
; SSE3-NEXT: haddps %xmm0, %xmm0 ; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: hadd32_16_pgso: ; AVX-LABEL: hadd32_16_pgso:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
%x226 = shufflevector <16 x float> %x225, <16 x float> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %x226 = shufflevector <16 x float> %x225, <16 x float> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%x227 = fadd <16 x float> %x225, %x226 %x227 = fadd <16 x float> %x225, %x226
%x228 = shufflevector <16 x float> %x227, <16 x float> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %x228 = shufflevector <16 x float> %x227, <16 x float> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%x229 = fadd <16 x float> %x227, %x228 %x229 = fadd <16 x float> %x227, %x228
%x230 = extractelement <16 x float> %x229, i32 0 %x230 = extractelement <16 x float> %x229, i32 0
ret float %x230 ret float %x230
} }
define float @partial_reduction_fadd_v8f32(<8 x float> %x) { define float @partial_reduction_fadd_v8f32(<8 x float> %x) {
; SSE3-SLOW-LABEL: partial_reduction_fadd_v8f32: ; SSE3-SLOW-LABEL: partial_reduction_fadd_v8f32:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addps %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: partial_reduction_fadd_v8f32: ; SSE3-FAST-LABEL: partial_reduction_fadd_v8f32:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: movaps %xmm0, %xmm1 ; SSE3-FAST-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-FAST-NEXT: addps %xmm1, %xmm0 ; SSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
; AVX-SLOW-LABEL: partial_reduction_fadd_v8f32: ; AVX-SLOW-LABEL: partial_reduction_fadd_v8f32:
; AVX-SLOW: # %bb.0: ; AVX-SLOW: # %bb.0:
; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
Show All 17 Lines
} }
; Negative test - only the flags on the final math op in the ; Negative test - only the flags on the final math op in the
; sequence determine whether we can transform to horizontal ops. ; sequence determine whether we can transform to horizontal ops.
define float @partial_reduction_fadd_v8f32_wrong_flags(<8 x float> %x) { define float @partial_reduction_fadd_v8f32_wrong_flags(<8 x float> %x) {
; SSE3-SLOW-LABEL: partial_reduction_fadd_v8f32_wrong_flags: ; SSE3-SLOW-LABEL: partial_reduction_fadd_v8f32_wrong_flags:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addps %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: partial_reduction_fadd_v8f32_wrong_flags: ; SSE3-FAST-LABEL: partial_reduction_fadd_v8f32_wrong_flags:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: movaps %xmm0, %xmm1 ; SSE3-FAST-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-FAST-NEXT: addps %xmm1, %xmm0 ; SSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
; AVX-SLOW-LABEL: partial_reduction_fadd_v8f32_wrong_flags: ; AVX-SLOW-LABEL: partial_reduction_fadd_v8f32_wrong_flags:
; AVX-SLOW: # %bb.0: ; AVX-SLOW: # %bb.0:
; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
Show All 15 Lines; AVX-FAST-NEXT: retq
%x0123 = fadd ninf nnan <8 x float> %x0213, %x13 %x0123 = fadd ninf nnan <8 x float> %x0213, %x13
%r = extractelement <8 x float> %x0123, i32 0 %r = extractelement <8 x float> %x0123, i32 0
ret float %r ret float %r
} }
define float @partial_reduction_fadd_v16f32(<16 x float> %x) { define float @partial_reduction_fadd_v16f32(<16 x float> %x) {
; SSE3-SLOW-LABEL: partial_reduction_fadd_v16f32: ; SSE3-SLOW-LABEL: partial_reduction_fadd_v16f32:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addps %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: partial_reduction_fadd_v16f32: ; SSE3-FAST-LABEL: partial_reduction_fadd_v16f32:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: movaps %xmm0, %xmm1 ; SSE3-FAST-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-FAST-NEXT: addps %xmm1, %xmm0 ; SSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
; AVX-SLOW-LABEL: partial_reduction_fadd_v16f32: ; AVX-SLOW-LABEL: partial_reduction_fadd_v16f32:
; AVX-SLOW: # %bb.0: ; AVX-SLOW: # %bb.0:
; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
Show All 35 Lines

llvm/test/CodeGen/X86/half.ll

Show First 20 Lines • Show All 579 Lines • ▼ Show 20 Lines
; BWON-NOF16C: # %bb.0: ; BWON-NOF16C: # %bb.0:
; BWON-NOF16C-NEXT: pushq %rbp ; BWON-NOF16C-NEXT: pushq %rbp
; BWON-NOF16C-NEXT: pushq %r15 ; BWON-NOF16C-NEXT: pushq %r15
; BWON-NOF16C-NEXT: pushq %r14 ; BWON-NOF16C-NEXT: pushq %r14
; BWON-NOF16C-NEXT: pushq %rbx ; BWON-NOF16C-NEXT: pushq %rbx
; BWON-NOF16C-NEXT: subq $24, %rsp ; BWON-NOF16C-NEXT: subq $24, %rsp
; BWON-NOF16C-NEXT: movq %rdi, %rbx ; BWON-NOF16C-NEXT: movq %rdi, %rbx
; BWON-NOF16C-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; BWON-NOF16C-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; BWON-NOF16C-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; BWON-NOF16C-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; BWON-NOF16C-NEXT: callq __gnu_f2h_ieee@PLT ; BWON-NOF16C-NEXT: callq __gnu_f2h_ieee@PLT
; BWON-NOF16C-NEXT: movl %eax, %r14d ; BWON-NOF16C-NEXT: movl %eax, %r14d
; BWON-NOF16C-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; BWON-NOF16C-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; BWON-NOF16C-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; BWON-NOF16C-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; BWON-NOF16C-NEXT: callq __gnu_f2h_ieee@PLT ; BWON-NOF16C-NEXT: callq __gnu_f2h_ieee@PLT
; BWON-NOF16C-NEXT: movl %eax, %r15d ; BWON-NOF16C-NEXT: movl %eax, %r15d
; BWON-NOF16C-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; BWON-NOF16C-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; BWON-NOF16C-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; BWON-NOF16C-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; BWON-NOF16C-NEXT: callq __gnu_f2h_ieee@PLT ; BWON-NOF16C-NEXT: callq __gnu_f2h_ieee@PLT
; BWON-NOF16C-NEXT: movl %eax, %ebp ; BWON-NOF16C-NEXT: movl %eax, %ebp
; BWON-NOF16C-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; BWON-NOF16C-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; BWON-NOF16C-NEXT: callq __gnu_f2h_ieee@PLT ; BWON-NOF16C-NEXT: callq __gnu_f2h_ieee@PLT
; BWON-NOF16C-NEXT: movw %ax, (%rbx) ; BWON-NOF16C-NEXT: movw %ax, (%rbx)
; BWON-NOF16C-NEXT: movw %bp, 6(%rbx) ; BWON-NOF16C-NEXT: movw %bp, 6(%rbx)
; BWON-NOF16C-NEXT: movw %r15w, 4(%rbx) ; BWON-NOF16C-NEXT: movw %r14w, 4(%rbx)
; BWON-NOF16C-NEXT: movw %r14w, 2(%rbx) ; BWON-NOF16C-NEXT: movw %r15w, 2(%rbx)
; BWON-NOF16C-NEXT: addq $24, %rsp ; BWON-NOF16C-NEXT: addq $24, %rsp
; BWON-NOF16C-NEXT: popq %rbx ; BWON-NOF16C-NEXT: popq %rbx
; BWON-NOF16C-NEXT: popq %r14 ; BWON-NOF16C-NEXT: popq %r14
; BWON-NOF16C-NEXT: popq %r15 ; BWON-NOF16C-NEXT: popq %r15
; BWON-NOF16C-NEXT: popq %rbp ; BWON-NOF16C-NEXT: popq %rbp
; BWON-NOF16C-NEXT: retq ; BWON-NOF16C-NEXT: retq
; ;
; BWOFF-LABEL: test_trunc32_vec4: ; BWOFF-LABEL: test_trunc32_vec4:
; BWOFF: # %bb.0: ; BWOFF: # %bb.0:
; BWOFF-NEXT: pushq %rbp ; BWOFF-NEXT: pushq %rbp
; BWOFF-NEXT: pushq %r15 ; BWOFF-NEXT: pushq %r15
; BWOFF-NEXT: pushq %r14 ; BWOFF-NEXT: pushq %r14
; BWOFF-NEXT: pushq %rbx ; BWOFF-NEXT: pushq %rbx
; BWOFF-NEXT: subq $24, %rsp ; BWOFF-NEXT: subq $24, %rsp
; BWOFF-NEXT: movq %rdi, %rbx ; BWOFF-NEXT: movq %rdi, %rbx
; BWOFF-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; BWOFF-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; BWOFF-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; BWOFF-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; BWOFF-NEXT: callq __gnu_f2h_ieee@PLT ; BWOFF-NEXT: callq __gnu_f2h_ieee@PLT
; BWOFF-NEXT: movw %ax, %r14w ; BWOFF-NEXT: movw %ax, %r14w
; BWOFF-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; BWOFF-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; BWOFF-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; BWOFF-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; BWOFF-NEXT: callq __gnu_f2h_ieee@PLT ; BWOFF-NEXT: callq __gnu_f2h_ieee@PLT
; BWOFF-NEXT: movw %ax, %r15w ; BWOFF-NEXT: movw %ax, %r15w
; BWOFF-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; BWOFF-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; BWOFF-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; BWOFF-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; BWOFF-NEXT: callq __gnu_f2h_ieee@PLT ; BWOFF-NEXT: callq __gnu_f2h_ieee@PLT
; BWOFF-NEXT: movw %ax, %bp ; BWOFF-NEXT: movw %ax, %bp
; BWOFF-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; BWOFF-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; BWOFF-NEXT: callq __gnu_f2h_ieee@PLT ; BWOFF-NEXT: callq __gnu_f2h_ieee@PLT
; BWOFF-NEXT: movw %ax, (%rbx) ; BWOFF-NEXT: movw %ax, (%rbx)
; BWOFF-NEXT: movw %bp, 6(%rbx) ; BWOFF-NEXT: movw %bp, 6(%rbx)
; BWOFF-NEXT: movw %r15w, 4(%rbx) ; BWOFF-NEXT: movw %r14w, 4(%rbx)
; BWOFF-NEXT: movw %r14w, 2(%rbx) ; BWOFF-NEXT: movw %r15w, 2(%rbx)
; BWOFF-NEXT: addq $24, %rsp ; BWOFF-NEXT: addq $24, %rsp
; BWOFF-NEXT: popq %rbx ; BWOFF-NEXT: popq %rbx
; BWOFF-NEXT: popq %r14 ; BWOFF-NEXT: popq %r14
; BWOFF-NEXT: popq %r15 ; BWOFF-NEXT: popq %r15
; BWOFF-NEXT: popq %rbp ; BWOFF-NEXT: popq %rbp
; BWOFF-NEXT: retq ; BWOFF-NEXT: retq
; ;
; BWON-F16C-LABEL: test_trunc32_vec4: ; BWON-F16C-LABEL: test_trunc32_vec4:
; BWON-F16C: # %bb.0: ; BWON-F16C: # %bb.0:
; BWON-F16C-NEXT: vcvtps2ph $4, %xmm0, (%rdi) ; BWON-F16C-NEXT: vcvtps2ph $4, %xmm0, (%rdi)
; BWON-F16C-NEXT: retq ; BWON-F16C-NEXT: retq
; ;
; CHECK-I686-LABEL: test_trunc32_vec4: ; CHECK-I686-LABEL: test_trunc32_vec4:
; CHECK-I686: # %bb.0: ; CHECK-I686: # %bb.0:
; CHECK-I686-NEXT: pushl %ebp ; CHECK-I686-NEXT: pushl %ebp
; CHECK-I686-NEXT: pushl %ebx ; CHECK-I686-NEXT: pushl %ebx
; CHECK-I686-NEXT: pushl %edi ; CHECK-I686-NEXT: pushl %edi
; CHECK-I686-NEXT: pushl %esi ; CHECK-I686-NEXT: pushl %esi
; CHECK-I686-NEXT: subl $44, %esp ; CHECK-I686-NEXT: subl $60, %esp
; CHECK-I686-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill ; CHECK-I686-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; CHECK-I686-NEXT: movl {{[0-9]+}}(%esp), %ebp ; CHECK-I686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; CHECK-I686-NEXT: movaps %xmm0, %xmm1 ; CHECK-I686-NEXT: movaps %xmm0, %xmm1
; CHECK-I686-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; CHECK-I686-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; CHECK-I686-NEXT: movss %xmm1, (%esp) ; CHECK-I686-NEXT: movss %xmm1, (%esp)
; CHECK-I686-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-I686-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; CHECK-I686-NEXT: calll __gnu_f2h_ieee ; CHECK-I686-NEXT: calll __gnu_f2h_ieee
; CHECK-I686-NEXT: movw %ax, %si ; CHECK-I686-NEXT: movw %ax, %si
; CHECK-I686-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-I686-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-I686-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-I686-NEXT: movss %xmm0, (%esp) ; CHECK-I686-NEXT: movss %xmm0, (%esp)
; CHECK-I686-NEXT: calll __gnu_f2h_ieee ; CHECK-I686-NEXT: calll __gnu_f2h_ieee
; CHECK-I686-NEXT: movw %ax, %di ; CHECK-I686-NEXT: movw %ax, %di
; CHECK-I686-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-I686-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-I686-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; CHECK-I686-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; CHECK-I686-NEXT: movss %xmm0, (%esp) ; CHECK-I686-NEXT: movss %xmm0, (%esp)
; CHECK-I686-NEXT: calll __gnu_f2h_ieee ; CHECK-I686-NEXT: calll __gnu_f2h_ieee
; CHECK-I686-NEXT: movw %ax, %bx ; CHECK-I686-NEXT: movw %ax, %bx
; CHECK-I686-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-I686-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-I686-NEXT: movss %xmm0, (%esp) ; CHECK-I686-NEXT: movss %xmm0, (%esp)
; CHECK-I686-NEXT: calll __gnu_f2h_ieee ; CHECK-I686-NEXT: calll __gnu_f2h_ieee
; CHECK-I686-NEXT: movw %ax, (%ebp) ; CHECK-I686-NEXT: movw %ax, (%ebp)
; CHECK-I686-NEXT: movw %bx, 6(%ebp) ; CHECK-I686-NEXT: movw %bx, 6(%ebp)
; CHECK-I686-NEXT: movw %di, 4(%ebp) ; CHECK-I686-NEXT: movw %di, 4(%ebp)
; CHECK-I686-NEXT: movw %si, 2(%ebp) ; CHECK-I686-NEXT: movw %si, 2(%ebp)
; CHECK-I686-NEXT: addl $44, %esp ; CHECK-I686-NEXT: addl $60, %esp
; CHECK-I686-NEXT: popl %esi ; CHECK-I686-NEXT: popl %esi
; CHECK-I686-NEXT: popl %edi ; CHECK-I686-NEXT: popl %edi
; CHECK-I686-NEXT: popl %ebx ; CHECK-I686-NEXT: popl %ebx
; CHECK-I686-NEXT: popl %ebp ; CHECK-I686-NEXT: popl %ebp
; CHECK-I686-NEXT: retl ; CHECK-I686-NEXT: retl
%v = fptrunc <4 x float> %a to <4 x half> %v = fptrunc <4 x float> %a to <4 x half>
store <4 x half> %v, <4 x half>* %p store <4 x half> %v, <4 x half>* %p
ret void ret void
▲ Show 20 Lines • Show All 308 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/horizontal-reduce-fadd.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSSE3-SLOW ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSSE3-SLOW
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3,fast-hops | FileCheck %s --check-prefix=SSSE3-FAST ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3,fast-hops | FileCheck %s --check-prefix=SSSE3-FAST
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX1-SLOW ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX1-SLOW
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx,fast-hops | FileCheck %s --check-prefix=AVX1-FAST ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx,fast-hops | FileCheck %s --check-prefix=AVX1-FAST
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX2
; PR37890 - subvector reduction followed by shuffle reduction ; PR37890 - subvector reduction followed by shuffle reduction
define float @PR37890_v4f32(<4 x float> %a) { define float @PR37890_v4f32(<4 x float> %a) {
; SSE2-LABEL: PR37890_v4f32: ; SSE2-LABEL: PR37890_v4f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-SLOW-LABEL: PR37890_v4f32: ; SSSE3-SLOW-LABEL: PR37890_v4f32:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: PR37890_v4f32: ; SSSE3-FAST-LABEL: PR37890_v4f32:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0
Show All 29 Lines; AVX2-NEXT: retq
%e = extractelement <2 x float> %sum1, i32 0 %e = extractelement <2 x float> %sum1, i32 0
ret float %e ret float %e
} }
define double @PR37890_v4f64(<4 x double> %a) { define double @PR37890_v4f64(<4 x double> %a) {
; SSE2-LABEL: PR37890_v4f64: ; SSE2-LABEL: PR37890_v4f64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addpd %xmm1, %xmm0 ; SSE2-NEXT: addpd %xmm1, %xmm0
; SSE2-NEXT: movapd %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: addsd %xmm1, %xmm0 ; SSE2-NEXT: addsd %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-SLOW-LABEL: PR37890_v4f64: ; SSSE3-SLOW-LABEL: PR37890_v4f64:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: addpd %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addpd %xmm1, %xmm0
; SSSE3-SLOW-NEXT: movapd %xmm0, %xmm1 ; SSSE3-SLOW-NEXT: xorps %xmm1, %xmm1
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSSE3-SLOW-NEXT: addsd %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addsd %xmm1, %xmm0
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: PR37890_v4f64: ; SSSE3-FAST-LABEL: PR37890_v4f64:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: addpd %xmm1, %xmm0 ; SSSE3-FAST-NEXT: addpd %xmm1, %xmm0
; SSSE3-FAST-NEXT: haddpd %xmm0, %xmm0 ; SSSE3-FAST-NEXT: haddpd %xmm0, %xmm0
; SSSE3-FAST-NEXT: retq ; SSSE3-FAST-NEXT: retq
Show All 31 Lines; AVX2-NEXT: retq
%e = extractelement <2 x double> %sum1, i32 0 %e = extractelement <2 x double> %sum1, i32 0
ret double %e ret double %e
} }
define float @PR37890_v8f32(<8 x float> %a) { define float @PR37890_v8f32(<8 x float> %a) {
; SSE2-LABEL: PR37890_v8f32: ; SSE2-LABEL: PR37890_v8f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-SLOW-LABEL: PR37890_v8f32: ; SSSE3-SLOW-LABEL: PR37890_v8f32:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSSE3-SLOW-NEXT: xorps %xmm1, %xmm1
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: PR37890_v8f32: ; SSSE3-FAST-LABEL: PR37890_v8f32:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: addps %xmm1, %xmm0 ; SSSE3-FAST-NEXT: addps %xmm1, %xmm0
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
} }
define double @PR37890_v8f64(<8 x double> %a) { define double @PR37890_v8f64(<8 x double> %a) {
; SSE2-LABEL: PR37890_v8f64: ; SSE2-LABEL: PR37890_v8f64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addpd %xmm3, %xmm1 ; SSE2-NEXT: addpd %xmm3, %xmm1
; SSE2-NEXT: addpd %xmm2, %xmm1 ; SSE2-NEXT: addpd %xmm2, %xmm1
; SSE2-NEXT: addpd %xmm1, %xmm0 ; SSE2-NEXT: addpd %xmm1, %xmm0
; SSE2-NEXT: movapd %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: addsd %xmm1, %xmm0 ; SSE2-NEXT: addsd %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-SLOW-LABEL: PR37890_v8f64: ; SSSE3-SLOW-LABEL: PR37890_v8f64:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: addpd %xmm3, %xmm1 ; SSSE3-SLOW-NEXT: addpd %xmm3, %xmm1
; SSSE3-SLOW-NEXT: addpd %xmm2, %xmm1 ; SSSE3-SLOW-NEXT: addpd %xmm2, %xmm1
; SSSE3-SLOW-NEXT: addpd %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addpd %xmm1, %xmm0
; SSSE3-SLOW-NEXT: movapd %xmm0, %xmm1 ; SSSE3-SLOW-NEXT: xorps %xmm1, %xmm1
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSSE3-SLOW-NEXT: addsd %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addsd %xmm1, %xmm0
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: PR37890_v8f64: ; SSSE3-FAST-LABEL: PR37890_v8f64:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: addpd %xmm3, %xmm1 ; SSSE3-FAST-NEXT: addpd %xmm3, %xmm1
; SSSE3-FAST-NEXT: addpd %xmm2, %xmm1 ; SSSE3-FAST-NEXT: addpd %xmm2, %xmm1
; SSSE3-FAST-NEXT: addpd %xmm1, %xmm0 ; SSSE3-FAST-NEXT: addpd %xmm1, %xmm0
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
} }
define float @PR37890_v16f32(<16 x float> %a) { define float @PR37890_v16f32(<16 x float> %a) {
; SSE2-LABEL: PR37890_v16f32: ; SSE2-LABEL: PR37890_v16f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addps %xmm3, %xmm1 ; SSE2-NEXT: addps %xmm3, %xmm1
; SSE2-NEXT: addps %xmm2, %xmm1 ; SSE2-NEXT: addps %xmm2, %xmm1
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-SLOW-LABEL: PR37890_v16f32: ; SSSE3-SLOW-LABEL: PR37890_v16f32:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: addps %xmm3, %xmm1 ; SSSE3-SLOW-NEXT: addps %xmm3, %xmm1
; SSSE3-SLOW-NEXT: addps %xmm2, %xmm1 ; SSSE3-SLOW-NEXT: addps %xmm2, %xmm1
; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSSE3-SLOW-NEXT: xorps %xmm1, %xmm1
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: PR37890_v16f32: ; SSSE3-FAST-LABEL: PR37890_v16f32:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: addps %xmm3, %xmm1 ; SSSE3-FAST-NEXT: addps %xmm3, %xmm1
; SSSE3-FAST-NEXT: addps %xmm2, %xmm1 ; SSSE3-FAST-NEXT: addps %xmm2, %xmm1
; SSSE3-FAST-NEXT: addps %xmm1, %xmm0 ; SSSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSSE3-FAST-NEXT: movaps %xmm0, %xmm1 ; SSSE3-FAST-NEXT: xorps %xmm1, %xmm1
; SSSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSSE3-FAST-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSSE3-FAST-NEXT: addps %xmm1, %xmm0 ; SSSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSSE3-FAST-NEXT: retq ; SSSE3-FAST-NEXT: retq
; ;
; AVX1-SLOW-LABEL: PR37890_v16f32: ; AVX1-SLOW-LABEL: PR37890_v16f32:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddps %ymm1, %ymm0, %ymm0
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1
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llvm/test/CodeGen/X86/horizontal-sum.ll

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; SSSE3-SLOW-LABEL: pair_sum_v8f32_v4f32: ; SSSE3-SLOW-LABEL: pair_sum_v8f32_v4f32:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: haddps %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: haddps %xmm1, %xmm0
; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm1
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm0[1,3] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm0[1,3]
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSSE3-SLOW-NEXT: haddps %xmm3, %xmm2 ; SSSE3-SLOW-NEXT: haddps %xmm3, %xmm2
; SSSE3-SLOW-NEXT: movaps %xmm5, %xmm1 ; SSSE3-SLOW-NEXT: haddps %xmm4, %xmm5
; SSSE3-SLOW-NEXT: haddps %xmm4, %xmm1 ; SSSE3-SLOW-NEXT: haddps %xmm5, %xmm2
; SSSE3-SLOW-NEXT: haddps %xmm1, %xmm2
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1,3,2] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1,3,2]
; SSSE3-SLOW-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSSE3-SLOW-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSSE3-SLOW-NEXT: haddps %xmm7, %xmm6 ; SSSE3-SLOW-NEXT: haddps %xmm7, %xmm6
; SSSE3-SLOW-NEXT: haddps %xmm5, %xmm4 ; SSSE3-SLOW-NEXT: haddps %xmm6, %xmm6
; SSSE3-SLOW-NEXT: haddps %xmm6, %xmm4 ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,3],xmm6[0,1]
; SSSE3-SLOW-NEXT: movaps %xmm4, %xmm1 ; SSSE3-SLOW-NEXT: movaps %xmm2, %xmm1
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: pair_sum_v8f32_v4f32: ; SSSE3-FAST-LABEL: pair_sum_v8f32_v4f32:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: haddps %xmm1, %xmm0 ; SSSE3-FAST-NEXT: haddps %xmm1, %xmm0
; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSSE3-FAST-NEXT: haddps %xmm3, %xmm2 ; SSSE3-FAST-NEXT: haddps %xmm3, %xmm2
; SSSE3-FAST-NEXT: haddps %xmm5, %xmm4 ; SSSE3-FAST-NEXT: haddps %xmm5, %xmm4
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; SSSE3-SLOW-NEXT: addps %xmm2, %xmm0 ; SSSE3-SLOW-NEXT: addps %xmm2, %xmm0
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2],xmm0[0,1] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2],xmm0[0,1]
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm2[2,3] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm2[2,3]
; SSSE3-SLOW-NEXT: addps %xmm5, %xmm4 ; SSSE3-SLOW-NEXT: addps %xmm5, %xmm4
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[3,3] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[3,3]
; SSSE3-SLOW-NEXT: addps %xmm1, %xmm4 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm4
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm3[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm3[1,1,3,3]
; SSSE3-SLOW-NEXT: addps %xmm3, %xmm0 ; SSSE3-SLOW-NEXT: addps %xmm3, %xmm0
; SSSE3-SLOW-NEXT: movaps %xmm3, %xmm1 ; SSSE3-SLOW-NEXT: xorps %xmm1, %xmm1
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1] ; SSSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSSE3-SLOW-NEXT: addps %xmm0, %xmm1 ; SSSE3-SLOW-NEXT: addps %xmm0, %xmm1
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSSE3-SLOW-NEXT: addps %xmm1, %xmm3 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm3
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm4[2,3] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm4[2,3]
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm3[2,0] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm3[2,0]
; SSSE3-SLOW-NEXT: movaps %xmm4, %xmm0 ; SSSE3-SLOW-NEXT: movaps %xmm4, %xmm0
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: sequential_sum_v4f32_v4f32: ; SSSE3-FAST-LABEL: sequential_sum_v4f32_v4f32:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: movaps %xmm0, %xmm5 ; SSSE3-FAST-NEXT: movaps %xmm0, %xmm5
; SSSE3-FAST-NEXT: haddps %xmm1, %xmm5 ; SSSE3-FAST-NEXT: haddps %xmm1, %xmm5
; SSSE3-FAST-NEXT: movaps %xmm0, %xmm4 ; SSSE3-FAST-NEXT: movaps %xmm0, %xmm4
; SSSE3-FAST-NEXT: unpckhps {{.*#+}} xmm4 = xmm4[2],xmm1[2],xmm4[3],xmm1[3] ; SSSE3-FAST-NEXT: unpckhps {{.*#+}} xmm4 = xmm4[2],xmm1[2],xmm4[3],xmm1[3]
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm2[2,3] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm2[2,3]
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[3,3] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[3,3]
; SSSE3-FAST-NEXT: haddps %xmm2, %xmm2 ; SSSE3-FAST-NEXT: haddps %xmm2, %xmm2
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2],xmm2[0,1] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2],xmm2[0,1]
; SSSE3-FAST-NEXT: addps %xmm5, %xmm4 ; SSSE3-FAST-NEXT: addps %xmm5, %xmm4
; SSSE3-FAST-NEXT: addps %xmm1, %xmm4 ; SSSE3-FAST-NEXT: addps %xmm1, %xmm4
; SSSE3-FAST-NEXT: movaps %xmm3, %xmm0 ; SSSE3-FAST-NEXT: movaps %xmm3, %xmm0
; SSSE3-FAST-NEXT: haddps %xmm3, %xmm0 ; SSSE3-FAST-NEXT: haddps %xmm3, %xmm0
; SSSE3-FAST-NEXT: movaps %xmm3, %xmm1 ; SSSE3-FAST-NEXT: xorps %xmm1, %xmm1
; SSSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1] ; SSSE3-FAST-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSSE3-FAST-NEXT: addps %xmm0, %xmm1 ; SSSE3-FAST-NEXT: addps %xmm0, %xmm1
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSSE3-FAST-NEXT: addps %xmm1, %xmm3 ; SSSE3-FAST-NEXT: addps %xmm1, %xmm3
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm4[2,3] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm4[2,3]
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm3[2,0] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm3[2,0]
; SSSE3-FAST-NEXT: movaps %xmm4, %xmm0 ; SSSE3-FAST-NEXT: movaps %xmm4, %xmm0
; SSSE3-FAST-NEXT: retq ; SSSE3-FAST-NEXT: retq
; ;
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; return (VTYPE) { reduce( A0 ), reduce( A1 ), reduce( A2 ), reduce( A3 ) }; ; return (VTYPE) { reduce( A0 ), reduce( A1 ), reduce( A2 ), reduce( A3 ) };
; } ; }
define <4 x float> @reduction_sum_v4f32_v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3) { define <4 x float> @reduction_sum_v4f32_v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3) {
; SSSE3-SLOW-LABEL: reduction_sum_v4f32_v4f32: ; SSSE3-SLOW-LABEL: reduction_sum_v4f32_v4f32:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
; SSSE3-SLOW-NEXT: addss %xmm0, %xmm4 ; SSSE3-SLOW-NEXT: addss %xmm0, %xmm4
; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm5 ; SSSE3-SLOW-NEXT: movhlps {{.*#+}} xmm5 = xmm0[1],xmm5[1]
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm0[1]
; SSSE3-SLOW-NEXT: addss %xmm4, %xmm5 ; SSSE3-SLOW-NEXT: addss %xmm4, %xmm5
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSSE3-SLOW-NEXT: addss %xmm5, %xmm0 ; SSSE3-SLOW-NEXT: addss %xmm5, %xmm0
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm4 = xmm1[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm4 = xmm1[1,1,3,3]
; SSSE3-SLOW-NEXT: addss %xmm1, %xmm4 ; SSSE3-SLOW-NEXT: addss %xmm1, %xmm4
; SSSE3-SLOW-NEXT: movaps %xmm1, %xmm5 ; SSSE3-SLOW-NEXT: xorps %xmm5, %xmm5
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm1[1] ; SSSE3-SLOW-NEXT: movhlps {{.*#+}} xmm5 = xmm1[1],xmm5[1]
; SSSE3-SLOW-NEXT: addss %xmm4, %xmm5 ; SSSE3-SLOW-NEXT: addss %xmm4, %xmm5
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSSE3-SLOW-NEXT: addss %xmm5, %xmm1 ; SSSE3-SLOW-NEXT: addss %xmm5, %xmm1
; SSSE3-SLOW-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSSE3-SLOW-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSSE3-SLOW-NEXT: addss %xmm2, %xmm1 ; SSSE3-SLOW-NEXT: addss %xmm2, %xmm1
; SSSE3-SLOW-NEXT: movaps %xmm2, %xmm4 ; SSSE3-SLOW-NEXT: xorps %xmm4, %xmm4
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm2[1] ; SSSE3-SLOW-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSSE3-SLOW-NEXT: addss %xmm1, %xmm4 ; SSSE3-SLOW-NEXT: addss %xmm1, %xmm4
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSSE3-SLOW-NEXT: addss %xmm4, %xmm2 ; SSSE3-SLOW-NEXT: addss %xmm4, %xmm2
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm3[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm3[1,1,3,3]
; SSSE3-SLOW-NEXT: addss %xmm3, %xmm1 ; SSSE3-SLOW-NEXT: addss %xmm3, %xmm1
; SSSE3-SLOW-NEXT: movaps %xmm3, %xmm4 ; SSSE3-SLOW-NEXT: xorps %xmm4, %xmm4
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm3[1] ; SSSE3-SLOW-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSSE3-SLOW-NEXT: addss %xmm1, %xmm4 ; SSSE3-SLOW-NEXT: addss %xmm1, %xmm4
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSSE3-SLOW-NEXT: addss %xmm4, %xmm3 ; SSSE3-SLOW-NEXT: addss %xmm4, %xmm3
; SSSE3-SLOW-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSSE3-SLOW-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; SSSE3-SLOW-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSSE3-SLOW-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: reduction_sum_v4f32_v4f32: ; SSSE3-FAST-LABEL: reduction_sum_v4f32_v4f32:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: movaps %xmm0, %xmm4 ; SSSE3-FAST-NEXT: movaps %xmm0, %xmm4
; SSSE3-FAST-NEXT: haddps %xmm0, %xmm4 ; SSSE3-FAST-NEXT: haddps %xmm0, %xmm4
; SSSE3-FAST-NEXT: movaps %xmm0, %xmm5 ; SSSE3-FAST-NEXT: movhlps {{.*#+}} xmm5 = xmm0[1],xmm5[1]
; SSSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm0[1]
; SSSE3-FAST-NEXT: addss %xmm4, %xmm5 ; SSSE3-FAST-NEXT: addss %xmm4, %xmm5
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSSE3-FAST-NEXT: addss %xmm5, %xmm0 ; SSSE3-FAST-NEXT: addss %xmm5, %xmm0
; SSSE3-FAST-NEXT: movaps %xmm1, %xmm4 ; SSSE3-FAST-NEXT: movaps %xmm1, %xmm4
; SSSE3-FAST-NEXT: haddps %xmm1, %xmm4 ; SSSE3-FAST-NEXT: haddps %xmm1, %xmm4
; SSSE3-FAST-NEXT: movaps %xmm1, %xmm5 ; SSSE3-FAST-NEXT: xorps %xmm5, %xmm5
; SSSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm1[1] ; SSSE3-FAST-NEXT: movhlps {{.*#+}} xmm5 = xmm1[1],xmm5[1]
; SSSE3-FAST-NEXT: addss %xmm4, %xmm5 ; SSSE3-FAST-NEXT: addss %xmm4, %xmm5
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSSE3-FAST-NEXT: addss %xmm5, %xmm1 ; SSSE3-FAST-NEXT: addss %xmm5, %xmm1
; SSSE3-FAST-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSSE3-FAST-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSSE3-FAST-NEXT: movaps %xmm2, %xmm1 ; SSSE3-FAST-NEXT: movaps %xmm2, %xmm1
; SSSE3-FAST-NEXT: haddps %xmm2, %xmm1 ; SSSE3-FAST-NEXT: haddps %xmm2, %xmm1
; SSSE3-FAST-NEXT: movaps %xmm2, %xmm4 ; SSSE3-FAST-NEXT: xorps %xmm4, %xmm4
; SSSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm2[1] ; SSSE3-FAST-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSSE3-FAST-NEXT: addss %xmm1, %xmm4 ; SSSE3-FAST-NEXT: addss %xmm1, %xmm4
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSSE3-FAST-NEXT: addss %xmm4, %xmm2 ; SSSE3-FAST-NEXT: addss %xmm4, %xmm2
; SSSE3-FAST-NEXT: movaps %xmm3, %xmm1 ; SSSE3-FAST-NEXT: movaps %xmm3, %xmm1
; SSSE3-FAST-NEXT: haddps %xmm3, %xmm1 ; SSSE3-FAST-NEXT: haddps %xmm3, %xmm1
; SSSE3-FAST-NEXT: movaps %xmm3, %xmm4 ; SSSE3-FAST-NEXT: xorps %xmm4, %xmm4
; SSSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm3[1] ; SSSE3-FAST-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSSE3-FAST-NEXT: addss %xmm1, %xmm4 ; SSSE3-FAST-NEXT: addss %xmm1, %xmm4
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSSE3-FAST-NEXT: addss %xmm4, %xmm3 ; SSSE3-FAST-NEXT: addss %xmm4, %xmm3
; SSSE3-FAST-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSSE3-FAST-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; SSSE3-FAST-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSSE3-FAST-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSSE3-FAST-NEXT: retq ; SSSE3-FAST-NEXT: retq
; ;
; AVX-SLOW-LABEL: reduction_sum_v4f32_v4f32: ; AVX-SLOW-LABEL: reduction_sum_v4f32_v4f32:
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines; AVX-FAST-NEXT: retq
%12 = insertelement <4 x float> %11, float %8, i32 3 %12 = insertelement <4 x float> %11, float %8, i32 3
ret <4 x float> %12 ret <4 x float> %12
} }
declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>) declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>)
define <4 x float> @reduction_sum_v4f32_v4f32_reassoc(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3) { define <4 x float> @reduction_sum_v4f32_v4f32_reassoc(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3) {
; SSSE3-SLOW-LABEL: reduction_sum_v4f32_v4f32_reassoc: ; SSSE3-SLOW-LABEL: reduction_sum_v4f32_v4f32_reassoc:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm4 ; SSSE3-SLOW-NEXT: movhlps {{.*#+}} xmm4 = xmm0[1],xmm4[1]
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1]
; SSSE3-SLOW-NEXT: addps %xmm4, %xmm0 ; SSSE3-SLOW-NEXT: addps %xmm4, %xmm0
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
; SSSE3-SLOW-NEXT: movaps %xmm1, %xmm5 ; SSSE3-SLOW-NEXT: movhlps {{.*#+}} xmm5 = xmm1[1],xmm5[1]
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm1[1]
; SSSE3-SLOW-NEXT: addps %xmm1, %xmm5 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm5
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm5[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm5[1,1,3,3]
; SSSE3-SLOW-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] ; SSSE3-SLOW-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
; SSSE3-SLOW-NEXT: movaps %xmm2, %xmm1 ; SSSE3-SLOW-NEXT: xorps %xmm1, %xmm1
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSSE3-SLOW-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSSE3-SLOW-NEXT: addps %xmm2, %xmm1 ; SSSE3-SLOW-NEXT: addps %xmm2, %xmm1
; SSSE3-SLOW-NEXT: movaps %xmm3, %xmm2 ; SSSE3-SLOW-NEXT: xorps %xmm2, %xmm2
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm3[1] ; SSSE3-SLOW-NEXT: movhlps {{.*#+}} xmm2 = xmm3[1],xmm2[1]
; SSSE3-SLOW-NEXT: addps %xmm3, %xmm2 ; SSSE3-SLOW-NEXT: addps %xmm3, %xmm2
; SSSE3-SLOW-NEXT: movaps %xmm2, %xmm3 ; SSSE3-SLOW-NEXT: movaps %xmm2, %xmm3
; SSSE3-SLOW-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm1[0] ; SSSE3-SLOW-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm1[0]
; SSSE3-SLOW-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1] ; SSSE3-SLOW-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,0] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,0]
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1]
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm2[2,0] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm2[2,0]
; SSSE3-SLOW-NEXT: addps %xmm4, %xmm0 ; SSSE3-SLOW-NEXT: addps %xmm4, %xmm0
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: reduction_sum_v4f32_v4f32_reassoc: ; SSSE3-FAST-LABEL: reduction_sum_v4f32_v4f32_reassoc:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: movaps %xmm0, %xmm4 ; SSSE3-FAST-NEXT: movhlps {{.*#+}} xmm4 = xmm0[1],xmm4[1]
; SSSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1]
; SSSE3-FAST-NEXT: addps %xmm4, %xmm0 ; SSSE3-FAST-NEXT: addps %xmm4, %xmm0
; SSSE3-FAST-NEXT: movaps %xmm1, %xmm4 ; SSSE3-FAST-NEXT: xorps %xmm4, %xmm4
; SSSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm1[1] ; SSSE3-FAST-NEXT: movhlps {{.*#+}} xmm4 = xmm1[1],xmm4[1]
; SSSE3-FAST-NEXT: addps %xmm1, %xmm4 ; SSSE3-FAST-NEXT: addps %xmm1, %xmm4
; SSSE3-FAST-NEXT: haddps %xmm4, %xmm0 ; SSSE3-FAST-NEXT: haddps %xmm4, %xmm0
; SSSE3-FAST-NEXT: movaps %xmm2, %xmm1 ; SSSE3-FAST-NEXT: xorps %xmm1, %xmm1
; SSSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSSE3-FAST-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSSE3-FAST-NEXT: addps %xmm2, %xmm1 ; SSSE3-FAST-NEXT: addps %xmm2, %xmm1
; SSSE3-FAST-NEXT: movaps %xmm3, %xmm2 ; SSSE3-FAST-NEXT: xorps %xmm2, %xmm2
; SSSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm3[1] ; SSSE3-FAST-NEXT: movhlps {{.*#+}} xmm2 = xmm3[1],xmm2[1]
; SSSE3-FAST-NEXT: addps %xmm3, %xmm2 ; SSSE3-FAST-NEXT: addps %xmm3, %xmm2
; SSSE3-FAST-NEXT: haddps %xmm2, %xmm1 ; SSSE3-FAST-NEXT: haddps %xmm2, %xmm1
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; SSSE3-FAST-NEXT: retq ; SSSE3-FAST-NEXT: retq
; ;
; AVX-SLOW-LABEL: reduction_sum_v4f32_v4f32_reassoc: ; AVX-SLOW-LABEL: reduction_sum_v4f32_v4f32_reassoc:
; AVX-SLOW: # %bb.0: ; AVX-SLOW: # %bb.0:
; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm4 = xmm0[1,0] ; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm4 = xmm0[1,0]
▲ Show 20 Lines • Show All 150 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/inline-asm-x-i128.ll

Show All 10 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movq %rsi, %xmm0 ; CHECK-NEXT: movq %rsi, %xmm0
; CHECK-NEXT: movq %rdi, %xmm1 ; CHECK-NEXT: movq %rdi, %xmm1
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: movq %xmm0, %rax ; CHECK-NEXT: movq %xmm0, %rax
; CHECK-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movq %xmm0, %rdx ; CHECK-NEXT: movq %xmm0, %rdx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%3 = zext i64 %1 to i128 %3 = zext i64 %1 to i128
%4 = shl nuw i128 %3, 64 %4 = shl nuw i128 %3, 64
%5 = zext i64 %0 to i128 %5 = zext i64 %0 to i128
%6 = or i128 %4, %5 %6 = or i128 %4, %5
%7 = tail call i128 asm sideeffect "movdqa $1, $0", "=x,x,~{dirflag},~{fpsr},~{flags}"(i128 %6) %7 = tail call i128 asm sideeffect "movdqa $1, $0", "=x,x,~{dirflag},~{fpsr},~{flags}"(i128 %6)
%8 = trunc i128 %7 to i64 %8 = trunc i128 %7 to i64
%9 = lshr i128 %7, 64 %9 = lshr i128 %7, 64
%10 = trunc i128 %9 to i64 %10 = trunc i128 %9 to i64
%11 = insertvalue { i64, i64 } undef, i64 %8, 0 %11 = insertvalue { i64, i64 } undef, i64 %8, 0
%12 = insertvalue { i64, i64 } %11, i64 %10, 1 %12 = insertvalue { i64, i64 } %11, i64 %10, 1
ret { i64, i64 } %12 ret { i64, i64 } %12
} }

llvm/test/CodeGen/X86/load-partial-dot-product.ll

Show All 13 Lines
define float @dot3_float4(float* dereferenceable(16) %a0, float* dereferenceable(16) %a1) { define float @dot3_float4(float* dereferenceable(16) %a0, float* dereferenceable(16) %a1) {
; SSE2-LABEL: dot3_float4: ; SSE2-LABEL: dot3_float4:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movups (%rdi), %xmm0 ; SSE2-NEXT: movups (%rdi), %xmm0
; SSE2-NEXT: movups (%rsi), %xmm1 ; SSE2-NEXT: movups (%rsi), %xmm1
; SSE2-NEXT: mulps %xmm0, %xmm1 ; SSE2-NEXT: mulps %xmm0, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: dot3_float4: ; SSSE3-LABEL: dot3_float4:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movups (%rdi), %xmm0 ; SSSE3-NEXT: movups (%rdi), %xmm0
; SSSE3-NEXT: movups (%rsi), %xmm1 ; SSSE3-NEXT: movups (%rsi), %xmm1
; SSSE3-NEXT: mulps %xmm0, %xmm1 ; SSSE3-NEXT: mulps %xmm0, %xmm1
; SSSE3-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSSE3-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
; SSSE3-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSSE3-NEXT: addss %xmm1, %xmm0 ; SSSE3-NEXT: addss %xmm1, %xmm0
; SSSE3-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; SSSE3-NEXT: addss %xmm2, %xmm0
; SSSE3-NEXT: addss %xmm1, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: dot3_float4: ; SSE41-LABEL: dot3_float4:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movups (%rdi), %xmm0 ; SSE41-NEXT: movups (%rdi), %xmm0
; SSE41-NEXT: movups (%rsi), %xmm1 ; SSE41-NEXT: movups (%rsi), %xmm1
; SSE41-NEXT: mulps %xmm0, %xmm1 ; SSE41-NEXT: mulps %xmm0, %xmm1
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: dot3_float4: ; AVX-LABEL: dot3_float4:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovups (%rdi), %xmm0 ; AVX-NEXT: vmovups (%rdi), %xmm0
; AVX-NEXT: vmulps (%rsi), %xmm0, %xmm0 ; AVX-NEXT: vmulps (%rsi), %xmm0, %xmm0
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
Show All 16 Lines
define float @dot3_float4_as_float3(float* dereferenceable(16) %a0, float* dereferenceable(16) %a1) { define float @dot3_float4_as_float3(float* dereferenceable(16) %a0, float* dereferenceable(16) %a1) {
; SSE2-LABEL: dot3_float4_as_float3: ; SSE2-LABEL: dot3_float4_as_float3:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movups (%rdi), %xmm0 ; SSE2-NEXT: movups (%rdi), %xmm0
; SSE2-NEXT: movups (%rsi), %xmm1 ; SSE2-NEXT: movups (%rsi), %xmm1
; SSE2-NEXT: mulps %xmm0, %xmm1 ; SSE2-NEXT: mulps %xmm0, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: dot3_float4_as_float3: ; SSSE3-LABEL: dot3_float4_as_float3:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movups (%rdi), %xmm0 ; SSSE3-NEXT: movups (%rdi), %xmm0
; SSSE3-NEXT: movups (%rsi), %xmm1 ; SSSE3-NEXT: movups (%rsi), %xmm1
; SSSE3-NEXT: mulps %xmm0, %xmm1 ; SSSE3-NEXT: mulps %xmm0, %xmm1
; SSSE3-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSSE3-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
; SSSE3-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSSE3-NEXT: addss %xmm1, %xmm0 ; SSSE3-NEXT: addss %xmm1, %xmm0
; SSSE3-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; SSSE3-NEXT: addss %xmm2, %xmm0
; SSSE3-NEXT: addss %xmm1, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: dot3_float4_as_float3: ; SSE41-LABEL: dot3_float4_as_float3:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movups (%rdi), %xmm0 ; SSE41-NEXT: movups (%rdi), %xmm0
; SSE41-NEXT: movups (%rsi), %xmm1 ; SSE41-NEXT: movups (%rsi), %xmm1
; SSE41-NEXT: mulps %xmm0, %xmm1 ; SSE41-NEXT: mulps %xmm0, %xmm1
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: dot3_float4_as_float3: ; AVX-LABEL: dot3_float4_as_float3:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovups (%rdi), %xmm0 ; AVX-NEXT: vmovups (%rdi), %xmm0
; AVX-NEXT: vmulps (%rsi), %xmm0, %xmm0 ; AVX-NEXT: vmulps (%rsi), %xmm0, %xmm0
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
Show All 24 Lines
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
; SSE2-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; SSE2-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
; SSE2-NEXT: mulps %xmm0, %xmm1 ; SSE2-NEXT: mulps %xmm0, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: dot3_float3: ; SSSE3-LABEL: dot3_float3:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSSE3-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSSE3-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0] ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2] ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
; SSSE3-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; SSSE3-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; SSSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0] ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2] ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
; SSSE3-NEXT: mulps %xmm0, %xmm1 ; SSSE3-NEXT: mulps %xmm0, %xmm1
; SSSE3-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSSE3-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
; SSSE3-NEXT: xorps %xmm2, %xmm2
; SSSE3-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSSE3-NEXT: addss %xmm1, %xmm0 ; SSSE3-NEXT: addss %xmm1, %xmm0
; SSSE3-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; SSSE3-NEXT: addss %xmm2, %xmm0
; SSSE3-NEXT: addss %xmm1, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: dot3_float3: ; SSE41-LABEL: dot3_float3:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE41-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
; SSE41-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; SSE41-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3] ; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
; SSE41-NEXT: mulps %xmm0, %xmm1 ; SSE41-NEXT: mulps %xmm0, %xmm1
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: dot3_float3: ; AVX-LABEL: dot3_float3:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; AVX-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3] ; AVX-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
▲ Show 20 Lines • Show All 248 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/masked_compressstore.ll

Show First 20 Lines • Show All 724 Lines • ▼ Show 20 Lines
; SSE2-NEXT: LBB3_3: ## %cond.store1 ; SSE2-NEXT: LBB3_3: ## %cond.store1
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: movss %xmm1, (%rdi) ; SSE2-NEXT: movss %xmm1, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB3_6 ; SSE2-NEXT: je LBB3_6
; SSE2-NEXT: LBB3_5: ## %cond.store4 ; SSE2-NEXT: LBB3_5: ## %cond.store4
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: movss %xmm1, (%rdi) ; SSE2-NEXT: movss %xmm1, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: je LBB3_8 ; SSE2-NEXT: je LBB3_8
; SSE2-NEXT: LBB3_7: ## %cond.store7 ; SSE2-NEXT: LBB3_7: ## %cond.store7
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: retq ; SSE2-NEXT: retq
▲ Show 20 Lines • Show All 137 Lines • ▼ Show 20 Lines
; SSE2-NEXT: LBB4_3: ## %cond.store1 ; SSE2-NEXT: LBB4_3: ## %cond.store1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1]
; SSE2-NEXT: movss %xmm2, (%rdi) ; SSE2-NEXT: movss %xmm2, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB4_6 ; SSE2-NEXT: je LBB4_6
; SSE2-NEXT: LBB4_5: ## %cond.store4 ; SSE2-NEXT: LBB4_5: ## %cond.store4
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE2-NEXT: movd %xmm2, (%rdi) ; SSE2-NEXT: movss %xmm2, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: je LBB4_8 ; SSE2-NEXT: je LBB4_8
; SSE2-NEXT: LBB4_7: ## %cond.store7 ; SSE2-NEXT: LBB4_7: ## %cond.store7
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: testb $16, %al
; SSE2-NEXT: je LBB4_10 ; SSE2-NEXT: je LBB4_10
; SSE2-NEXT: LBB4_9: ## %cond.store10 ; SSE2-NEXT: LBB4_9: ## %cond.store10
; SSE2-NEXT: movss %xmm1, (%rdi) ; SSE2-NEXT: movss %xmm1, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $32, %al ; SSE2-NEXT: testb $32, %al
; SSE2-NEXT: je LBB4_12 ; SSE2-NEXT: je LBB4_12
; SSE2-NEXT: LBB4_11: ## %cond.store13 ; SSE2-NEXT: LBB4_11: ## %cond.store13
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: je LBB4_14 ; SSE2-NEXT: je LBB4_14
; SSE2-NEXT: LBB4_13: ## %cond.store16 ; SSE2-NEXT: LBB4_13: ## %cond.store16
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: testb $-128, %al
; SSE2-NEXT: je LBB4_16 ; SSE2-NEXT: je LBB4_16
; SSE2-NEXT: LBB4_15: ## %cond.store19 ; SSE2-NEXT: LBB4_15: ## %cond.store19
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: movss %xmm1, (%rdi) ; SSE2-NEXT: movss %xmm1, (%rdi)
; SSE2-NEXT: retq ; SSE2-NEXT: retq
▲ Show 20 Lines • Show All 241 Lines • ▼ Show 20 Lines
define void @compressstore_v16f32_const(float* %base, <16 x float> %V) { define void @compressstore_v16f32_const(float* %base, <16 x float> %V) {
; SSE2-LABEL: compressstore_v16f32_const: ; SSE2-LABEL: compressstore_v16f32_const:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: movaps %xmm0, %xmm4 ; SSE2-NEXT: movaps %xmm0, %xmm4
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[1,1]
; SSE2-NEXT: movss %xmm4, 4(%rdi) ; SSE2-NEXT: movss %xmm4, 4(%rdi)
; SSE2-NEXT: movaps %xmm0, %xmm4 ; SSE2-NEXT: xorps %xmm4, %xmm4
; SSE2-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm4 = xmm0[1],xmm4[1]
; SSE2-NEXT: movss %xmm4, 8(%rdi) ; SSE2-NEXT: movss %xmm4, 8(%rdi)
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: movss %xmm0, 12(%rdi) ; SSE2-NEXT: movss %xmm0, 12(%rdi)
; SSE2-NEXT: movss %xmm1, 16(%rdi) ; SSE2-NEXT: movss %xmm1, 16(%rdi)
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; SSE2-NEXT: movss %xmm0, 20(%rdi) ; SSE2-NEXT: movss %xmm0, 20(%rdi)
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSE2-NEXT: movss %xmm0, 24(%rdi) ; SSE2-NEXT: movss %xmm0, 24(%rdi)
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: movss %xmm1, 28(%rdi) ; SSE2-NEXT: movss %xmm1, 28(%rdi)
; SSE2-NEXT: movss %xmm2, 32(%rdi) ; SSE2-NEXT: movss %xmm2, 32(%rdi)
; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm2[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm2[1],xmm0[1]
; SSE2-NEXT: movss %xmm0, 36(%rdi) ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1] ; SSE2-NEXT: movss %xmm2, 36(%rdi)
; SSE2-NEXT: movss %xmm2, 40(%rdi) ; SSE2-NEXT: movss %xmm0, 40(%rdi)
; SSE2-NEXT: movss %xmm3, 44(%rdi) ; SSE2-NEXT: movss %xmm3, 44(%rdi)
; SSE2-NEXT: movaps %xmm3, %xmm0 ; SSE2-NEXT: movaps %xmm3, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm3[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm3[1,1]
; SSE2-NEXT: movss %xmm0, 48(%rdi) ; SSE2-NEXT: movss %xmm0, 48(%rdi)
; SSE2-NEXT: movaps %xmm3, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm3[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm3[1],xmm0[1]
; SSE2-NEXT: movss %xmm0, 52(%rdi) ; SSE2-NEXT: movss %xmm0, 52(%rdi)
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSE2-NEXT: movss %xmm3, 56(%rdi) ; SSE2-NEXT: movss %xmm3, 56(%rdi)
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: compressstore_v16f32_const: ; SSE42-LABEL: compressstore_v16f32_const:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: movups %xmm0, (%rdi) ; SSE42-NEXT: movups %xmm0, (%rdi)
▲ Show 20 Lines • Show All 191 Lines • ▼ Show 20 Lines
; SSE2-NEXT: LBB6_3: ## %cond.store1 ; SSE2-NEXT: LBB6_3: ## %cond.store1
; SSE2-NEXT: movaps %xmm0, %xmm8 ; SSE2-NEXT: movaps %xmm0, %xmm8
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[1,1],xmm0[1,1]
; SSE2-NEXT: movss %xmm8, (%rdi) ; SSE2-NEXT: movss %xmm8, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB6_6 ; SSE2-NEXT: je LBB6_6
; SSE2-NEXT: LBB6_5: ## %cond.store4 ; SSE2-NEXT: LBB6_5: ## %cond.store4
; SSE2-NEXT: movaps %xmm0, %xmm8 ; SSE2-NEXT: xorps %xmm8, %xmm8
; SSE2-NEXT: unpckhpd {{.*#+}} xmm8 = xmm8[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm8 = xmm0[1],xmm8[1]
; SSE2-NEXT: movss %xmm8, (%rdi) ; SSE2-NEXT: movss %xmm8, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: je LBB6_8 ; SSE2-NEXT: je LBB6_8
; SSE2-NEXT: LBB6_7: ## %cond.store7 ; SSE2-NEXT: LBB6_7: ## %cond.store7
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: testb $16, %al
; SSE2-NEXT: je LBB6_10 ; SSE2-NEXT: je LBB6_10
; SSE2-NEXT: LBB6_9: ## %cond.store10 ; SSE2-NEXT: LBB6_9: ## %cond.store10
; SSE2-NEXT: movss %xmm1, (%rdi) ; SSE2-NEXT: movss %xmm1, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $32, %al ; SSE2-NEXT: testb $32, %al
; SSE2-NEXT: je LBB6_12 ; SSE2-NEXT: je LBB6_12
; SSE2-NEXT: LBB6_11: ## %cond.store13 ; SSE2-NEXT: LBB6_11: ## %cond.store13
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: je LBB6_14 ; SSE2-NEXT: je LBB6_14
; SSE2-NEXT: LBB6_13: ## %cond.store16 ; SSE2-NEXT: LBB6_13: ## %cond.store16
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: testb $-128, %al
; SSE2-NEXT: je LBB6_16 ; SSE2-NEXT: je LBB6_16
; SSE2-NEXT: LBB6_15: ## %cond.store19 ; SSE2-NEXT: LBB6_15: ## %cond.store19
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: movss %xmm1, (%rdi) ; SSE2-NEXT: movss %xmm1, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $256, %eax ## imm = 0x100 ; SSE2-NEXT: testl $256, %eax ## imm = 0x100
; SSE2-NEXT: je LBB6_18 ; SSE2-NEXT: je LBB6_18
; SSE2-NEXT: LBB6_17: ## %cond.store22 ; SSE2-NEXT: LBB6_17: ## %cond.store22
; SSE2-NEXT: movss %xmm2, (%rdi) ; SSE2-NEXT: movss %xmm2, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $512, %eax ## imm = 0x200 ; SSE2-NEXT: testl $512, %eax ## imm = 0x200
; SSE2-NEXT: je LBB6_20 ; SSE2-NEXT: je LBB6_20
; SSE2-NEXT: LBB6_19: ## %cond.store25 ; SSE2-NEXT: LBB6_19: ## %cond.store25
; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm2[1,1]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400
; SSE2-NEXT: je LBB6_22 ; SSE2-NEXT: je LBB6_22
; SSE2-NEXT: LBB6_21: ## %cond.store28 ; SSE2-NEXT: LBB6_21: ## %cond.store28
; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm2[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm2[1],xmm0[1]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800
; SSE2-NEXT: je LBB6_24 ; SSE2-NEXT: je LBB6_24
; SSE2-NEXT: LBB6_23: ## %cond.store31 ; SSE2-NEXT: LBB6_23: ## %cond.store31
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE2-NEXT: movss %xmm2, (%rdi) ; SSE2-NEXT: movss %xmm2, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000
; SSE2-NEXT: je LBB6_26 ; SSE2-NEXT: je LBB6_26
; SSE2-NEXT: LBB6_25: ## %cond.store34 ; SSE2-NEXT: LBB6_25: ## %cond.store34
; SSE2-NEXT: movss %xmm3, (%rdi) ; SSE2-NEXT: movss %xmm3, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000
; SSE2-NEXT: je LBB6_28 ; SSE2-NEXT: je LBB6_28
; SSE2-NEXT: LBB6_27: ## %cond.store37 ; SSE2-NEXT: LBB6_27: ## %cond.store37
; SSE2-NEXT: movaps %xmm3, %xmm0 ; SSE2-NEXT: movaps %xmm3, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm3[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm3[1,1]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000
; SSE2-NEXT: je LBB6_30 ; SSE2-NEXT: je LBB6_30
; SSE2-NEXT: LBB6_29: ## %cond.store40 ; SSE2-NEXT: LBB6_29: ## %cond.store40
; SSE2-NEXT: movaps %xmm3, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm3[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm3[1],xmm0[1]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 ; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE2-NEXT: je LBB6_32 ; SSE2-NEXT: je LBB6_32
; SSE2-NEXT: LBB6_31: ## %cond.store43 ; SSE2-NEXT: LBB6_31: ## %cond.store43
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSE2-NEXT: movss %xmm3, (%rdi) ; SSE2-NEXT: movss %xmm3, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $65536, %eax ## imm = 0x10000 ; SSE2-NEXT: testl $65536, %eax ## imm = 0x10000
; SSE2-NEXT: je LBB6_34 ; SSE2-NEXT: je LBB6_34
; SSE2-NEXT: LBB6_33: ## %cond.store46 ; SSE2-NEXT: LBB6_33: ## %cond.store46
; SSE2-NEXT: movss %xmm4, (%rdi) ; SSE2-NEXT: movss %xmm4, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $131072, %eax ## imm = 0x20000 ; SSE2-NEXT: testl $131072, %eax ## imm = 0x20000
; SSE2-NEXT: je LBB6_36 ; SSE2-NEXT: je LBB6_36
; SSE2-NEXT: LBB6_35: ## %cond.store49 ; SSE2-NEXT: LBB6_35: ## %cond.store49
; SSE2-NEXT: movaps %xmm4, %xmm0 ; SSE2-NEXT: movaps %xmm4, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm4[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm4[1,1]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $262144, %eax ## imm = 0x40000 ; SSE2-NEXT: testl $262144, %eax ## imm = 0x40000
; SSE2-NEXT: je LBB6_38 ; SSE2-NEXT: je LBB6_38
; SSE2-NEXT: LBB6_37: ## %cond.store52 ; SSE2-NEXT: LBB6_37: ## %cond.store52
; SSE2-NEXT: movaps %xmm4, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm4[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm4[1],xmm0[1]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $524288, %eax ## imm = 0x80000 ; SSE2-NEXT: testl $524288, %eax ## imm = 0x80000
; SSE2-NEXT: je LBB6_40 ; SSE2-NEXT: je LBB6_40
; SSE2-NEXT: LBB6_39: ## %cond.store55 ; SSE2-NEXT: LBB6_39: ## %cond.store55
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
; SSE2-NEXT: movss %xmm4, (%rdi) ; SSE2-NEXT: movss %xmm4, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $1048576, %eax ## imm = 0x100000 ; SSE2-NEXT: testl $1048576, %eax ## imm = 0x100000
; SSE2-NEXT: je LBB6_42 ; SSE2-NEXT: je LBB6_42
; SSE2-NEXT: LBB6_41: ## %cond.store58 ; SSE2-NEXT: LBB6_41: ## %cond.store58
; SSE2-NEXT: movss %xmm5, (%rdi) ; SSE2-NEXT: movss %xmm5, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $2097152, %eax ## imm = 0x200000 ; SSE2-NEXT: testl $2097152, %eax ## imm = 0x200000
; SSE2-NEXT: je LBB6_44 ; SSE2-NEXT: je LBB6_44
; SSE2-NEXT: LBB6_43: ## %cond.store61 ; SSE2-NEXT: LBB6_43: ## %cond.store61
; SSE2-NEXT: movaps %xmm5, %xmm0 ; SSE2-NEXT: movaps %xmm5, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm5[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm5[1,1]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $4194304, %eax ## imm = 0x400000 ; SSE2-NEXT: testl $4194304, %eax ## imm = 0x400000
; SSE2-NEXT: je LBB6_46 ; SSE2-NEXT: je LBB6_46
; SSE2-NEXT: LBB6_45: ## %cond.store64 ; SSE2-NEXT: LBB6_45: ## %cond.store64
; SSE2-NEXT: movaps %xmm5, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm5[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm5[1],xmm0[1]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $8388608, %eax ## imm = 0x800000 ; SSE2-NEXT: testl $8388608, %eax ## imm = 0x800000
; SSE2-NEXT: je LBB6_48 ; SSE2-NEXT: je LBB6_48
; SSE2-NEXT: LBB6_47: ## %cond.store67 ; SSE2-NEXT: LBB6_47: ## %cond.store67
; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3,3,3]
; SSE2-NEXT: movss %xmm5, (%rdi) ; SSE2-NEXT: movss %xmm5, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $16777216, %eax ## imm = 0x1000000 ; SSE2-NEXT: testl $16777216, %eax ## imm = 0x1000000
; SSE2-NEXT: je LBB6_50 ; SSE2-NEXT: je LBB6_50
; SSE2-NEXT: LBB6_49: ## %cond.store70 ; SSE2-NEXT: LBB6_49: ## %cond.store70
; SSE2-NEXT: movss %xmm6, (%rdi) ; SSE2-NEXT: movss %xmm6, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $33554432, %eax ## imm = 0x2000000 ; SSE2-NEXT: testl $33554432, %eax ## imm = 0x2000000
; SSE2-NEXT: je LBB6_52 ; SSE2-NEXT: je LBB6_52
; SSE2-NEXT: LBB6_51: ## %cond.store73 ; SSE2-NEXT: LBB6_51: ## %cond.store73
; SSE2-NEXT: movaps %xmm6, %xmm0 ; SSE2-NEXT: movaps %xmm6, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm6[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm6[1,1]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $67108864, %eax ## imm = 0x4000000 ; SSE2-NEXT: testl $67108864, %eax ## imm = 0x4000000
; SSE2-NEXT: je LBB6_54 ; SSE2-NEXT: je LBB6_54
; SSE2-NEXT: LBB6_53: ## %cond.store76 ; SSE2-NEXT: LBB6_53: ## %cond.store76
; SSE2-NEXT: movaps %xmm6, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm6[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm6[1],xmm0[1]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $134217728, %eax ## imm = 0x8000000 ; SSE2-NEXT: testl $134217728, %eax ## imm = 0x8000000
; SSE2-NEXT: je LBB6_56 ; SSE2-NEXT: je LBB6_56
; SSE2-NEXT: LBB6_55: ## %cond.store79 ; SSE2-NEXT: LBB6_55: ## %cond.store79
; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3,3,3]
; SSE2-NEXT: movss %xmm6, (%rdi) ; SSE2-NEXT: movss %xmm6, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $268435456, %eax ## imm = 0x10000000 ; SSE2-NEXT: testl $268435456, %eax ## imm = 0x10000000
; SSE2-NEXT: je LBB6_58 ; SSE2-NEXT: je LBB6_58
; SSE2-NEXT: LBB6_57: ## %cond.store82 ; SSE2-NEXT: LBB6_57: ## %cond.store82
; SSE2-NEXT: movss %xmm7, (%rdi) ; SSE2-NEXT: movss %xmm7, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $536870912, %eax ## imm = 0x20000000 ; SSE2-NEXT: testl $536870912, %eax ## imm = 0x20000000
; SSE2-NEXT: je LBB6_60 ; SSE2-NEXT: je LBB6_60
; SSE2-NEXT: LBB6_59: ## %cond.store85 ; SSE2-NEXT: LBB6_59: ## %cond.store85
; SSE2-NEXT: movaps %xmm7, %xmm0 ; SSE2-NEXT: movaps %xmm7, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm7[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm7[1,1]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $1073741824, %eax ## imm = 0x40000000 ; SSE2-NEXT: testl $1073741824, %eax ## imm = 0x40000000
; SSE2-NEXT: je LBB6_62 ; SSE2-NEXT: je LBB6_62
; SSE2-NEXT: LBB6_61: ## %cond.store88 ; SSE2-NEXT: LBB6_61: ## %cond.store88
; SSE2-NEXT: movaps %xmm7, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm7[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm7[1],xmm0[1]
; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; SSE2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000
; SSE2-NEXT: je LBB6_64 ; SSE2-NEXT: je LBB6_64
; SSE2-NEXT: LBB6_63: ## %cond.store91 ; SSE2-NEXT: LBB6_63: ## %cond.store91
; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[3,3,3,3]
; SSE2-NEXT: movss %xmm7, (%rdi) ; SSE2-NEXT: movss %xmm7, (%rdi)
; SSE2-NEXT: retq ; SSE2-NEXT: retq
▲ Show 20 Lines • Show All 2,853 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/masked_store.ll

Show First 20 Lines • Show All 303 Lines • ▼ Show 20 Lines
; SSE2-NEXT: je LBB4_4 ; SSE2-NEXT: je LBB4_4
; SSE2-NEXT: LBB4_3: ## %cond.store1 ; SSE2-NEXT: LBB4_3: ## %cond.store1
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: movss %xmm1, 4(%rdi) ; SSE2-NEXT: movss %xmm1, 4(%rdi)
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB4_6 ; SSE2-NEXT: je LBB4_6
; SSE2-NEXT: LBB4_5: ## %cond.store3 ; SSE2-NEXT: LBB4_5: ## %cond.store3
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: movss %xmm1, 8(%rdi) ; SSE2-NEXT: movss %xmm1, 8(%rdi)
; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: je LBB4_8 ; SSE2-NEXT: je LBB4_8
; SSE2-NEXT: LBB4_7: ## %cond.store5 ; SSE2-NEXT: LBB4_7: ## %cond.store5
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: movss %xmm0, 12(%rdi) ; SSE2-NEXT: movss %xmm0, 12(%rdi)
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
; SSE2-NEXT: je LBB5_4 ; SSE2-NEXT: je LBB5_4
; SSE2-NEXT: LBB5_3: ## %cond.store1 ; SSE2-NEXT: LBB5_3: ## %cond.store1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1]
; SSE2-NEXT: movss %xmm2, 4(%rdi) ; SSE2-NEXT: movss %xmm2, 4(%rdi)
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB5_6 ; SSE2-NEXT: je LBB5_6
; SSE2-NEXT: LBB5_5: ## %cond.store3 ; SSE2-NEXT: LBB5_5: ## %cond.store3
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE2-NEXT: movss %xmm2, 8(%rdi) ; SSE2-NEXT: movss %xmm2, 8(%rdi)
; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: je LBB5_8 ; SSE2-NEXT: je LBB5_8
; SSE2-NEXT: LBB5_7: ## %cond.store5 ; SSE2-NEXT: LBB5_7: ## %cond.store5
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: movss %xmm0, 12(%rdi) ; SSE2-NEXT: movss %xmm0, 12(%rdi)
; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: testb $16, %al
; SSE2-NEXT: je LBB5_10 ; SSE2-NEXT: je LBB5_10
; SSE2-NEXT: LBB5_9: ## %cond.store7 ; SSE2-NEXT: LBB5_9: ## %cond.store7
; SSE2-NEXT: movss %xmm1, 16(%rdi) ; SSE2-NEXT: movss %xmm1, 16(%rdi)
; SSE2-NEXT: testb $32, %al ; SSE2-NEXT: testb $32, %al
; SSE2-NEXT: je LBB5_12 ; SSE2-NEXT: je LBB5_12
; SSE2-NEXT: LBB5_11: ## %cond.store9 ; SSE2-NEXT: LBB5_11: ## %cond.store9
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; SSE2-NEXT: movss %xmm0, 20(%rdi) ; SSE2-NEXT: movss %xmm0, 20(%rdi)
; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: je LBB5_14 ; SSE2-NEXT: je LBB5_14
; SSE2-NEXT: LBB5_13: ## %cond.store11 ; SSE2-NEXT: LBB5_13: ## %cond.store11
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSE2-NEXT: movss %xmm0, 24(%rdi) ; SSE2-NEXT: movss %xmm0, 24(%rdi)
; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: testb $-128, %al
; SSE2-NEXT: je LBB5_16 ; SSE2-NEXT: je LBB5_16
; SSE2-NEXT: LBB5_15: ## %cond.store13 ; SSE2-NEXT: LBB5_15: ## %cond.store13
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: movss %xmm1, 28(%rdi) ; SSE2-NEXT: movss %xmm1, 28(%rdi)
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Lines
; SSE2-NEXT: je LBB6_4 ; SSE2-NEXT: je LBB6_4
; SSE2-NEXT: LBB6_3: ## %cond.store1 ; SSE2-NEXT: LBB6_3: ## %cond.store1
; SSE2-NEXT: movaps %xmm0, %xmm4 ; SSE2-NEXT: movaps %xmm0, %xmm4
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[1,1]
; SSE2-NEXT: movss %xmm4, 4(%rdi) ; SSE2-NEXT: movss %xmm4, 4(%rdi)
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB6_6 ; SSE2-NEXT: je LBB6_6
; SSE2-NEXT: LBB6_5: ## %cond.store3 ; SSE2-NEXT: LBB6_5: ## %cond.store3
; SSE2-NEXT: movaps %xmm0, %xmm4 ; SSE2-NEXT: xorps %xmm4, %xmm4
; SSE2-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm4 = xmm0[1],xmm4[1]
; SSE2-NEXT: movss %xmm4, 8(%rdi) ; SSE2-NEXT: movss %xmm4, 8(%rdi)
; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: je LBB6_8 ; SSE2-NEXT: je LBB6_8
; SSE2-NEXT: LBB6_7: ## %cond.store5 ; SSE2-NEXT: LBB6_7: ## %cond.store5
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: movss %xmm0, 12(%rdi) ; SSE2-NEXT: movss %xmm0, 12(%rdi)
; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: testb $16, %al
; SSE2-NEXT: je LBB6_10 ; SSE2-NEXT: je LBB6_10
; SSE2-NEXT: LBB6_9: ## %cond.store7 ; SSE2-NEXT: LBB6_9: ## %cond.store7
; SSE2-NEXT: movss %xmm1, 16(%rdi) ; SSE2-NEXT: movss %xmm1, 16(%rdi)
; SSE2-NEXT: testb $32, %al ; SSE2-NEXT: testb $32, %al
; SSE2-NEXT: je LBB6_12 ; SSE2-NEXT: je LBB6_12
; SSE2-NEXT: LBB6_11: ## %cond.store9 ; SSE2-NEXT: LBB6_11: ## %cond.store9
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; SSE2-NEXT: movss %xmm0, 20(%rdi) ; SSE2-NEXT: movss %xmm0, 20(%rdi)
; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: je LBB6_14 ; SSE2-NEXT: je LBB6_14
; SSE2-NEXT: LBB6_13: ## %cond.store11 ; SSE2-NEXT: LBB6_13: ## %cond.store11
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSE2-NEXT: movss %xmm0, 24(%rdi) ; SSE2-NEXT: movss %xmm0, 24(%rdi)
; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: testb $-128, %al
; SSE2-NEXT: je LBB6_16 ; SSE2-NEXT: je LBB6_16
; SSE2-NEXT: LBB6_15: ## %cond.store13 ; SSE2-NEXT: LBB6_15: ## %cond.store13
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: movss %xmm1, 28(%rdi) ; SSE2-NEXT: movss %xmm1, 28(%rdi)
; SSE2-NEXT: testl $256, %eax ## imm = 0x100 ; SSE2-NEXT: testl $256, %eax ## imm = 0x100
; SSE2-NEXT: je LBB6_18 ; SSE2-NEXT: je LBB6_18
; SSE2-NEXT: LBB6_17: ## %cond.store15 ; SSE2-NEXT: LBB6_17: ## %cond.store15
; SSE2-NEXT: movss %xmm2, 32(%rdi) ; SSE2-NEXT: movss %xmm2, 32(%rdi)
; SSE2-NEXT: testl $512, %eax ## imm = 0x200 ; SSE2-NEXT: testl $512, %eax ## imm = 0x200
; SSE2-NEXT: je LBB6_20 ; SSE2-NEXT: je LBB6_20
; SSE2-NEXT: LBB6_19: ## %cond.store17 ; SSE2-NEXT: LBB6_19: ## %cond.store17
; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm2[1,1]
; SSE2-NEXT: movss %xmm0, 36(%rdi) ; SSE2-NEXT: movss %xmm0, 36(%rdi)
; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400
; SSE2-NEXT: je LBB6_22 ; SSE2-NEXT: je LBB6_22
; SSE2-NEXT: LBB6_21: ## %cond.store19 ; SSE2-NEXT: LBB6_21: ## %cond.store19
; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm2[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm2[1],xmm0[1]
; SSE2-NEXT: movss %xmm0, 40(%rdi) ; SSE2-NEXT: movss %xmm0, 40(%rdi)
; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800
; SSE2-NEXT: je LBB6_24 ; SSE2-NEXT: je LBB6_24
; SSE2-NEXT: LBB6_23: ## %cond.store21 ; SSE2-NEXT: LBB6_23: ## %cond.store21
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE2-NEXT: movss %xmm2, 44(%rdi) ; SSE2-NEXT: movss %xmm2, 44(%rdi)
; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000
; SSE2-NEXT: je LBB6_26 ; SSE2-NEXT: je LBB6_26
; SSE2-NEXT: LBB6_25: ## %cond.store23 ; SSE2-NEXT: LBB6_25: ## %cond.store23
; SSE2-NEXT: movss %xmm3, 48(%rdi) ; SSE2-NEXT: movss %xmm3, 48(%rdi)
; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000
; SSE2-NEXT: je LBB6_28 ; SSE2-NEXT: je LBB6_28
; SSE2-NEXT: LBB6_27: ## %cond.store25 ; SSE2-NEXT: LBB6_27: ## %cond.store25
; SSE2-NEXT: movaps %xmm3, %xmm0 ; SSE2-NEXT: movaps %xmm3, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm3[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm3[1,1]
; SSE2-NEXT: movss %xmm0, 52(%rdi) ; SSE2-NEXT: movss %xmm0, 52(%rdi)
; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000
; SSE2-NEXT: je LBB6_30 ; SSE2-NEXT: je LBB6_30
; SSE2-NEXT: LBB6_29: ## %cond.store27 ; SSE2-NEXT: LBB6_29: ## %cond.store27
; SSE2-NEXT: movaps %xmm3, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm3[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm3[1],xmm0[1]
; SSE2-NEXT: movss %xmm0, 56(%rdi) ; SSE2-NEXT: movss %xmm0, 56(%rdi)
; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 ; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE2-NEXT: je LBB6_32 ; SSE2-NEXT: je LBB6_32
; SSE2-NEXT: LBB6_31: ## %cond.store29 ; SSE2-NEXT: LBB6_31: ## %cond.store29
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSE2-NEXT: movss %xmm3, 60(%rdi) ; SSE2-NEXT: movss %xmm3, 60(%rdi)
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
▲ Show 20 Lines • Show All 4,434 Lines • ▼ Show 20 Lines
; SSE2-NEXT: je LBB27_4 ; SSE2-NEXT: je LBB27_4
; SSE2-NEXT: LBB27_3: ## %cond.store1 ; SSE2-NEXT: LBB27_3: ## %cond.store1
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: movss %xmm1, 4(%rdi) ; SSE2-NEXT: movss %xmm1, 4(%rdi)
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB27_6 ; SSE2-NEXT: je LBB27_6
; SSE2-NEXT: LBB27_5: ## %cond.store3 ; SSE2-NEXT: LBB27_5: ## %cond.store3
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: movss %xmm1, 8(%rdi) ; SSE2-NEXT: movss %xmm1, 8(%rdi)
; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: je LBB27_8 ; SSE2-NEXT: je LBB27_8
; SSE2-NEXT: LBB27_7: ## %cond.store5 ; SSE2-NEXT: LBB27_7: ## %cond.store5
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: movss %xmm0, 12(%rdi) ; SSE2-NEXT: movss %xmm0, 12(%rdi)
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
▲ Show 20 Lines • Show All 298 Lines • ▼ Show 20 Lines
; SSE2-NEXT: je LBB30_4 ; SSE2-NEXT: je LBB30_4
; SSE2-NEXT: LBB30_3: ## %cond.store1 ; SSE2-NEXT: LBB30_3: ## %cond.store1
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1]
; SSE2-NEXT: movss %xmm2, 4(%rdi) ; SSE2-NEXT: movss %xmm2, 4(%rdi)
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB30_6 ; SSE2-NEXT: je LBB30_6
; SSE2-NEXT: LBB30_5: ## %cond.store3 ; SSE2-NEXT: LBB30_5: ## %cond.store3
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE2-NEXT: movss %xmm2, 8(%rdi) ; SSE2-NEXT: movss %xmm2, 8(%rdi)
; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: je LBB30_8 ; SSE2-NEXT: je LBB30_8
; SSE2-NEXT: LBB30_7: ## %cond.store5 ; SSE2-NEXT: LBB30_7: ## %cond.store5
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: movss %xmm0, 12(%rdi) ; SSE2-NEXT: movss %xmm0, 12(%rdi)
; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: testb $1, %al
; SSE2-NEXT: je LBB30_10 ; SSE2-NEXT: je LBB30_10
; SSE2-NEXT: LBB30_9: ## %cond.store8 ; SSE2-NEXT: LBB30_9: ## %cond.store8
; SSE2-NEXT: movss %xmm1, (%rdi) ; SSE2-NEXT: movss %xmm1, (%rdi)
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: je LBB30_12 ; SSE2-NEXT: je LBB30_12
; SSE2-NEXT: LBB30_11: ## %cond.store10 ; SSE2-NEXT: LBB30_11: ## %cond.store10
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; SSE2-NEXT: movss %xmm0, 4(%rdi) ; SSE2-NEXT: movss %xmm0, 4(%rdi)
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB30_14 ; SSE2-NEXT: je LBB30_14
; SSE2-NEXT: LBB30_13: ## %cond.store12 ; SSE2-NEXT: LBB30_13: ## %cond.store12
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSE2-NEXT: movss %xmm0, 8(%rdi) ; SSE2-NEXT: movss %xmm0, 8(%rdi)
; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: je LBB30_16 ; SSE2-NEXT: je LBB30_16
; SSE2-NEXT: LBB30_15: ## %cond.store14 ; SSE2-NEXT: LBB30_15: ## %cond.store14
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: movss %xmm1, 12(%rdi) ; SSE2-NEXT: movss %xmm1, 12(%rdi)
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
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llvm/test/CodeGen/X86/pr11334.ll

Show All 14 Lines
entry: entry:
%f1 = fpext <2 x float> %v1 to <2 x double> %f1 = fpext <2 x float> %v1 to <2 x double>
ret <2 x double> %f1 ret <2 x double> %f1
} }
define <3 x double> @v3f2d_ext_vec(<3 x float> %v1) nounwind { define <3 x double> @v3f2d_ext_vec(<3 x float> %v1) nounwind {
; SSE-LABEL: v3f2d_ext_vec: ; SSE-LABEL: v3f2d_ext_vec:
; SSE: # %bb.0: # %entry ; SSE: # %bb.0: # %entry
; SSE-NEXT: cvtps2pd %xmm0, %xmm2 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE-NEXT: cvtps2pd %xmm1, %xmm1
; SSE-NEXT: cvtps2pd %xmm0, %xmm0 ; SSE-NEXT: cvtps2pd %xmm0, %xmm0
; SSE-NEXT: movlps %xmm0, -{{[0-9]+}}(%rsp) ; SSE-NEXT: movlps %xmm1, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm2, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: fldl -{{[0-9]+}}(%rsp) ; SSE-NEXT: fldl -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: v3f2d_ext_vec: ; AVX-LABEL: v3f2d_ext_vec:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vcvtps2pd %xmm0, %ymm0 ; AVX-NEXT: vcvtps2pd %xmm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%f1 = fpext <3 x float> %v1 to <3 x double> %f1 = fpext <3 x float> %v1 to <3 x double>
ret <3 x double> %f1 ret <3 x double> %f1
} }
define <4 x double> @v4f2d_ext_vec(<4 x float> %v1) nounwind { define <4 x double> @v4f2d_ext_vec(<4 x float> %v1) nounwind {
; SSE-LABEL: v4f2d_ext_vec: ; SSE-LABEL: v4f2d_ext_vec:
; SSE: # %bb.0: # %entry ; SSE: # %bb.0: # %entry
; SSE-NEXT: cvtps2pd %xmm0, %xmm2 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE-NEXT: cvtps2pd %xmm1, %xmm1
; SSE-NEXT: cvtps2pd %xmm0, %xmm1 ; SSE-NEXT: cvtps2pd %xmm0, %xmm0
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: v4f2d_ext_vec: ; AVX-LABEL: v4f2d_ext_vec:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vcvtps2pd %xmm0, %ymm0 ; AVX-NEXT: vcvtps2pd %xmm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%f1 = fpext <4 x float> %v1 to <4 x double> %f1 = fpext <4 x float> %v1 to <4 x double>
ret <4 x double> %f1 ret <4 x double> %f1
} }
define <8 x double> @v8f2d_ext_vec(<8 x float> %v1) nounwind { define <8 x double> @v8f2d_ext_vec(<8 x float> %v1) nounwind {
; SSE-LABEL: v8f2d_ext_vec: ; SSE-LABEL: v8f2d_ext_vec:
; SSE: # %bb.0: # %entry ; SSE: # %bb.0: # %entry
; SSE-NEXT: cvtps2pd %xmm0, %xmm5 ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE-NEXT: cvtps2pd %xmm2, %xmm4
; SSE-NEXT: xorps %xmm2, %xmm2
; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE-NEXT: cvtps2pd %xmm2, %xmm3
; SSE-NEXT: cvtps2pd %xmm0, %xmm0
; SSE-NEXT: cvtps2pd %xmm1, %xmm2 ; SSE-NEXT: cvtps2pd %xmm1, %xmm2
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: cvtps2pd %xmm0, %xmm4
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: cvtps2pd %xmm1, %xmm3
; SSE-NEXT: movaps %xmm5, %xmm0
; SSE-NEXT: movaps %xmm4, %xmm1 ; SSE-NEXT: movaps %xmm4, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: v8f2d_ext_vec: ; AVX-LABEL: v8f2d_ext_vec:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vcvtps2pd %xmm0, %ymm2 ; AVX-NEXT: vcvtps2pd %xmm0, %ymm2
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX-NEXT: vcvtps2pd %xmm0, %ymm1 ; AVX-NEXT: vcvtps2pd %xmm0, %ymm1
Show All 27 Lines

llvm/test/CodeGen/X86/scalar-int-to-fp.ll

Show First 20 Lines • Show All 664 Lines • ▼ Show 20 Lines
; SSE2_32: # %bb.0: ; SSE2_32: # %bb.0:
; SSE2_32-NEXT: pushl %ebp ; SSE2_32-NEXT: pushl %ebp
; SSE2_32-NEXT: movl %esp, %ebp ; SSE2_32-NEXT: movl %esp, %ebp
; SSE2_32-NEXT: andl $-8, %esp ; SSE2_32-NEXT: andl $-8, %esp
; SSE2_32-NEXT: subl $8, %esp ; SSE2_32-NEXT: subl $8, %esp
; SSE2_32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2_32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE2_32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; SSE2_32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE2_32-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ; SSE2_32-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2_32-NEXT: movapd %xmm0, %xmm1 ; SSE2_32-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2_32-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2_32-NEXT: addsd %xmm0, %xmm1 ; SSE2_32-NEXT: addsd %xmm0, %xmm1
; SSE2_32-NEXT: movsd %xmm1, (%esp) ; SSE2_32-NEXT: movsd %xmm1, (%esp)
; SSE2_32-NEXT: fldl (%esp) ; SSE2_32-NEXT: fldl (%esp)
; SSE2_32-NEXT: movl %ebp, %esp ; SSE2_32-NEXT: movl %ebp, %esp
; SSE2_32-NEXT: popl %ebp ; SSE2_32-NEXT: popl %ebp
; SSE2_32-NEXT: retl ; SSE2_32-NEXT: retl
; ;
; SSE2_64-LABEL: u64_to_d: ; SSE2_64-LABEL: u64_to_d:
; SSE2_64: # %bb.0: ; SSE2_64: # %bb.0:
; SSE2_64-NEXT: movq %rdi, %xmm1 ; SSE2_64-NEXT: movq %rdi, %xmm1
; SSE2_64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1] ; SSE2_64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
; SSE2_64-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2_64-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2_64-NEXT: movapd %xmm1, %xmm0 ; SSE2_64-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSE2_64-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE2_64-NEXT: addsd %xmm1, %xmm0 ; SSE2_64-NEXT: addsd %xmm1, %xmm0
; SSE2_64-NEXT: retq ; SSE2_64-NEXT: retq
; ;
; SSE1_32-LABEL: u64_to_d: ; SSE1_32-LABEL: u64_to_d:
; SSE1_32: # %bb.0: ; SSE1_32: # %bb.0:
; SSE1_32-NEXT: pushl %ebp ; SSE1_32-NEXT: pushl %ebp
; SSE1_32-NEXT: movl %esp, %ebp ; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp ; SSE1_32-NEXT: andl $-8, %esp
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; SSE2_32: # %bb.0: ; SSE2_32: # %bb.0:
; SSE2_32-NEXT: pushl %ebp ; SSE2_32-NEXT: pushl %ebp
; SSE2_32-NEXT: movl %esp, %ebp ; SSE2_32-NEXT: movl %esp, %ebp
; SSE2_32-NEXT: andl $-8, %esp ; SSE2_32-NEXT: andl $-8, %esp
; SSE2_32-NEXT: subl $8, %esp ; SSE2_32-NEXT: subl $8, %esp
; SSE2_32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2_32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE2_32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; SSE2_32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE2_32-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ; SSE2_32-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2_32-NEXT: movapd %xmm0, %xmm1 ; SSE2_32-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2_32-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2_32-NEXT: addsd %xmm0, %xmm1 ; SSE2_32-NEXT: addsd %xmm0, %xmm1
; SSE2_32-NEXT: movsd %xmm1, (%esp) ; SSE2_32-NEXT: movsd %xmm1, (%esp)
; SSE2_32-NEXT: fldl (%esp) ; SSE2_32-NEXT: fldl (%esp)
; SSE2_32-NEXT: movl %ebp, %esp ; SSE2_32-NEXT: movl %ebp, %esp
; SSE2_32-NEXT: popl %ebp ; SSE2_32-NEXT: popl %ebp
; SSE2_32-NEXT: retl ; SSE2_32-NEXT: retl
; ;
; SSE2_64-LABEL: u64_to_d_optsize: ; SSE2_64-LABEL: u64_to_d_optsize:
; SSE2_64: # %bb.0: ; SSE2_64: # %bb.0:
; SSE2_64-NEXT: movq %rdi, %xmm1 ; SSE2_64-NEXT: movq %rdi, %xmm1
; SSE2_64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1] ; SSE2_64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
; SSE2_64-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2_64-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2_64-NEXT: movapd %xmm1, %xmm0 ; SSE2_64-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSE2_64-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE2_64-NEXT: addsd %xmm1, %xmm0 ; SSE2_64-NEXT: addsd %xmm1, %xmm0
; SSE2_64-NEXT: retq ; SSE2_64-NEXT: retq
; ;
; SSE1_32-LABEL: u64_to_d_optsize: ; SSE1_32-LABEL: u64_to_d_optsize:
; SSE1_32: # %bb.0: ; SSE1_32: # %bb.0:
; SSE1_32-NEXT: pushl %ebp ; SSE1_32-NEXT: pushl %ebp
; SSE1_32-NEXT: movl %esp, %ebp ; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp ; SSE1_32-NEXT: andl $-8, %esp
▲ Show 20 Lines • Show All 293 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/split-vector-rem.ll

Show First 20 Lines • Show All 135 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <8 x i32> %m ret <8 x i32> %m
} }
define <8 x float> @qux(<8 x float> %t, <8 x float> %u) { define <8 x float> @qux(<8 x float> %t, <8 x float> %u) {
; CHECK-LABEL: qux: ; CHECK-LABEL: qux:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: subq $104, %rsp ; CHECK-NEXT: subq $104, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 112 ; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm2, (%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; CHECK-NEXT: movaps %xmm2, %xmm1
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm2[3,3]
; CHECK-NEXT: callq fmodf@PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; CHECK-NEXT: callq fmodf@PLT ; CHECK-NEXT: callq fmodf@PLT
; CHECK-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; CHECK-NEXT: callq fmodf@PLT
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: callq fmodf@PLT ; CHECK-NEXT: callq fmodf@PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
; CHECK-NEXT: callq fmodf@PLT ; CHECK-NEXT: callq fmodf@PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload ; CHECK-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload
; CHECK-NEXT: # xmm1 = xmm1[0],mem[0] ; CHECK-NEXT: # xmm1 = xmm1[0],mem[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq fmodf@PLT ; CHECK-NEXT: callq fmodf@PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; CHECK-NEXT: callq fmodf@PLT ; CHECK-NEXT: callq fmodf@PLT
; CHECK-NEXT: unpcklps (%rsp), %xmm0 # 16-byte Folded Reload ; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: callq fmodf@PLT ; CHECK-NEXT: callq fmodf@PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
Show All 12 Lines

llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll

Show First 20 Lines • Show All 2,785 Lines • ▼ Show 20 Lines
; X64-SSE1: # %bb.0: ; X64-SSE1: # %bb.0:
; X64-SSE1-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) # encoding: [0x0f,0x29,0x44,0x24,0xe8] ; X64-SSE1-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) # encoding: [0x0f,0x29,0x44,0x24,0xe8]
; X64-SSE1-NEXT: movq -{{[0-9]+}}(%rsp), %rax # encoding: [0x48,0x8b,0x44,0x24,0xf0] ; X64-SSE1-NEXT: movq -{{[0-9]+}}(%rsp), %rax # encoding: [0x48,0x8b,0x44,0x24,0xf0]
; X64-SSE1-NEXT: movq %rax, (%rdi) # encoding: [0x48,0x89,0x07] ; X64-SSE1-NEXT: movq %rax, (%rdi) # encoding: [0x48,0x89,0x07]
; X64-SSE1-NEXT: retq # encoding: [0xc3] ; X64-SSE1-NEXT: retq # encoding: [0xc3]
; ;
; X64-SSE2-LABEL: test_mm_storeh_pi: ; X64-SSE2-LABEL: test_mm_storeh_pi:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: punpckhqdq %xmm0, %xmm0 # encoding: [0x66,0x0f,0x6d,0xc0] ; X64-SSE2-NEXT: movhlps %xmm0, %xmm0 # encoding: [0x0f,0x12,0xc0]
; X64-SSE2-NEXT: # xmm0 = xmm0[1,1] ; X64-SSE2-NEXT: # xmm0 = xmm0[1,1]
; X64-SSE2-NEXT: movq %xmm0, %rax # encoding: [0x66,0x48,0x0f,0x7e,0xc0] ; X64-SSE2-NEXT: movq %xmm0, %rax # encoding: [0x66,0x48,0x0f,0x7e,0xc0]
; X64-SSE2-NEXT: movq %rax, (%rdi) # encoding: [0x48,0x89,0x07] ; X64-SSE2-NEXT: movq %rax, (%rdi) # encoding: [0x48,0x89,0x07]
; X64-SSE2-NEXT: retq # encoding: [0xc3] ; X64-SSE2-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX1-LABEL: test_mm_storeh_pi: ; X64-AVX1-LABEL: test_mm_storeh_pi:
; X64-AVX1: # %bb.0: ; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vpextrq $1, %xmm0, %rax # encoding: [0xc4,0xe3,0xf9,0x16,0xc0,0x01] ; X64-AVX1-NEXT: vpextrq $1, %xmm0, %rax # encoding: [0xc4,0xe3,0xf9,0x16,0xc0,0x01]
▲ Show 20 Lines • Show All 783 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll

Show First 20 Lines • Show All 1,472 Lines • ▼ Show 20 Lines; X64-AVX512-NEXT: retq
%8 = insertelement <2 x double> %a, double %7, i64 0 %8 = insertelement <2 x double> %a, double %7, i64 0
ret <2 x double> %8 ret <2 x double> %8
} }
define float @PR26515(<4 x float> %0) nounwind { define float @PR26515(<4 x float> %0) nounwind {
; X86-SSE-LABEL: PR26515: ; X86-SSE-LABEL: PR26515:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pushl %eax ; X86-SSE-NEXT: pushl %eax
; X86-SSE-NEXT: movaps %xmm0, %xmm1 ; X86-SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; X86-SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; X86-SSE-NEXT: addss %xmm0, %xmm1 ; X86-SSE-NEXT: addss %xmm0, %xmm1
; X86-SSE-NEXT: movss %xmm1, (%esp) ; X86-SSE-NEXT: movss %xmm1, (%esp)
; X86-SSE-NEXT: flds (%esp) ; X86-SSE-NEXT: flds (%esp)
; X86-SSE-NEXT: popl %eax ; X86-SSE-NEXT: popl %eax
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: PR26515: ; X86-AVX-LABEL: PR26515:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: pushl %eax ; X86-AVX-NEXT: pushl %eax
; X86-AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; X86-AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; X86-AVX-NEXT: vaddss %xmm0, %xmm1, %xmm0 ; X86-AVX-NEXT: vaddss %xmm0, %xmm1, %xmm0
; X86-AVX-NEXT: vmovss %xmm0, (%esp) ; X86-AVX-NEXT: vmovss %xmm0, (%esp)
; X86-AVX-NEXT: flds (%esp) ; X86-AVX-NEXT: flds (%esp)
; X86-AVX-NEXT: popl %eax ; X86-AVX-NEXT: popl %eax
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: PR26515: ; X64-SSE-LABEL: PR26515:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movaps %xmm0, %xmm1 ; X64-SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; X64-SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; X64-SSE-NEXT: addss %xmm1, %xmm0 ; X64-SSE-NEXT: addss %xmm1, %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: PR26515: ; X64-AVX-LABEL: PR26515:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; X64-AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; X64-AVX-NEXT: vaddss %xmm0, %xmm1, %xmm0 ; X64-AVX-NEXT: vaddss %xmm0, %xmm1, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%2 = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef> %2 = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef>
%3 = fadd <4 x float> %2, %0 %3 = fadd <4 x float> %2, %0
%4 = extractelement <4 x float> %3, i64 0 %4 = extractelement <4 x float> %3, i64 0
ret float %4 ret float %4
} }

llvm/test/CodeGen/X86/sse3-avx-addsub-2.ll

Show First 20 Lines • Show All 355 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
%add = fadd float %1, %2 %add = fadd float %1, %2
%vecinsert1 = insertelement <4 x float> undef, float %add, i32 3 %vecinsert1 = insertelement <4 x float> undef, float %add, i32 3
ret <4 x float> %vecinsert1 ret <4 x float> %vecinsert1
} }
define <4 x float> @test14(<4 x float> %A, <4 x float> %B) { define <4 x float> @test14(<4 x float> %A, <4 x float> %B) {
; SSE-LABEL: test14: ; SSE-LABEL: test14:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm0, %xmm2 ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE-NEXT: subss %xmm1, %xmm2
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: subss %xmm1, %xmm0 ; SSE-NEXT: subss %xmm1, %xmm0
; SSE-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: movaps %xmm2, %xmm0 ; SSE-NEXT: subss %xmm1, %xmm2
; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test14: ; AVX-LABEL: test14:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vsubss %xmm1, %xmm0, %xmm2 ; AVX-NEXT: vsubss %xmm1, %xmm0, %xmm2
; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm1[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm1[1,0]
; AVX-NEXT: vsubss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vsubss %xmm1, %xmm0, %xmm0
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
} }
define <4 x float> @test16(<4 x float> %A, <4 x float> %B) { define <4 x float> @test16(<4 x float> %A, <4 x float> %B) {
; SSE-LABEL: test16: ; SSE-LABEL: test16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SSE-NEXT: movaps %xmm0, %xmm2 ; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: subss %xmm3, %xmm2 ; SSE-NEXT: subss %xmm3, %xmm2
; SSE-NEXT: movaps %xmm0, %xmm4 ; SSE-NEXT: movhlps {{.*#+}} xmm4 = xmm0[1],xmm4[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm5 = xmm1[1],xmm5[1]
; SSE-NEXT: movaps %xmm1, %xmm5
; SSE-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm1[1]
; SSE-NEXT: subss %xmm5, %xmm4 ; SSE-NEXT: subss %xmm5, %xmm4
; SSE-NEXT: movshdup {{.*#+}} xmm5 = xmm0[1,1,3,3] ; SSE-NEXT: movshdup {{.*#+}} xmm5 = xmm0[1,1,3,3]
; SSE-NEXT: addss %xmm3, %xmm5 ; SSE-NEXT: addss %xmm3, %xmm5
; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1] ; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1]
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE-NEXT: addss %xmm0, %xmm1 ; SSE-NEXT: addss %xmm0, %xmm1
; SSE-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] ; SSE-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
▲ Show 20 Lines • Show All 205 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vec-strict-128.ll

Show First 20 Lines • Show All 218 Lines • ▼ Show 20 Lines %cvt = call double @llvm.experimental.constrained.fpext.f64.f32(float %ext,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
%res = insertelement <2 x double> %a0, double %cvt, i32 0 %res = insertelement <2 x double> %a0, double %cvt, i32 0
ret <2 x double> %res ret <2 x double> %res
} }
define <4 x float> @f13(<4 x float> %a, <4 x float> %b, <4 x float> %c) #0 { define <4 x float> @f13(<4 x float> %a, <4 x float> %b, <4 x float> %c) #0 {
; SSE-X86-LABEL: f13: ; SSE-X86-LABEL: f13:
; SSE-X86: # %bb.0: ; SSE-X86: # %bb.0:
; SSE-X86-NEXT: subl $100, %esp ; SSE-X86-NEXT: subl $104, %esp
; SSE-X86-NEXT: .cfi_def_cfa_offset 104 ; SSE-X86-NEXT: .cfi_def_cfa_offset 108
; SSE-X86-NEXT: movups %xmm2, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill ; SSE-X86-NEXT: movups %xmm2, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; SSE-X86-NEXT: movups %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill ; SSE-X86-NEXT: movups %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; SSE-X86-NEXT: movups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill ; SSE-X86-NEXT: movups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; SSE-X86-NEXT: movss %xmm2, {{[0-9]+}}(%esp) ; SSE-X86-NEXT: movss %xmm2, {{[0-9]+}}(%esp)
; SSE-X86-NEXT: movss %xmm1, {{[0-9]+}}(%esp) ; SSE-X86-NEXT: movss %xmm1, {{[0-9]+}}(%esp)
; SSE-X86-NEXT: movss %xmm0, (%esp) ; SSE-X86-NEXT: movss %xmm0, (%esp)
; SSE-X86-NEXT: xorps %xmm0, %xmm0
; SSE-X86-NEXT: movhlps {{.*#+}} xmm0 = xmm2[1],xmm0[1]
; SSE-X86-NEXT: movups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; SSE-X86-NEXT: calll fmaf ; SSE-X86-NEXT: calll fmaf
; SSE-X86-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill ; SSE-X86-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill
; SSE-X86-NEXT: wait ; SSE-X86-NEXT: wait
; SSE-X86-NEXT: movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload ; SSE-X86-NEXT: movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-X86-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-X86-NEXT: movss %xmm0, {{[0-9]+}}(%esp) ; SSE-X86-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; SSE-X86-NEXT: movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload ; SSE-X86-NEXT: movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-X86-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE-X86-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-X86-NEXT: movss %xmm0, {{[0-9]+}}(%esp) ; SSE-X86-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; SSE-X86-NEXT: movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload ; SSE-X86-NEXT: movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-X86-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE-X86-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-X86-NEXT: movss %xmm0, (%esp) ; SSE-X86-NEXT: movss %xmm0, (%esp)
; SSE-X86-NEXT: calll fmaf ; SSE-X86-NEXT: calll fmaf
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; SSE-X86-NEXT: wait ; SSE-X86-NEXT: wait
; SSE-X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE-X86-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE-X86-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE-X86-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE-X86-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE-X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE-X86-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE-X86-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE-X86-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; SSE-X86-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; SSE-X86-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE-X86-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-X86-NEXT: addl $100, %esp ; SSE-X86-NEXT: addl $104, %esp
; SSE-X86-NEXT: .cfi_def_cfa_offset 4 ; SSE-X86-NEXT: .cfi_def_cfa_offset 4
; SSE-X86-NEXT: retl ; SSE-X86-NEXT: retl
; ;
; SSE-X64-LABEL: f13: ; SSE-X64-LABEL: f13:
; SSE-X64: # %bb.0: ; SSE-X64: # %bb.0:
; SSE-X64-NEXT: subq $88, %rsp ; SSE-X64-NEXT: subq $88, %rsp
; SSE-X64-NEXT: .cfi_def_cfa_offset 96 ; SSE-X64-NEXT: .cfi_def_cfa_offset 96
; SSE-X64-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; SSE-X64-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-X64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; SSE-X64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-X64-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; SSE-X64-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-X64-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; SSE-X64-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; SSE-X64-NEXT: callq fmaf@PLT
; SSE-X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; SSE-X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-X64-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE-X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; SSE-X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE-X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; SSE-X64-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE-X64-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE-X64-NEXT: callq fmaf@PLT ; SSE-X64-NEXT: callq fmaf@PLT
; SSE-X64-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-X64-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; SSE-X64-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; SSE-X64-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload ; SSE-X64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-X64-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1] ; SSE-X64-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-X64-NEXT: callq fmaf@PLT
; SSE-X64-NEXT: unpcklps (%rsp), %xmm0 # 16-byte Folded Reload
; SSE-X64-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE-X64-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload ; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; SSE-X64-NEXT: callq fmaf@PLT ; SSE-X64-NEXT: callq fmaf@PLT
; SSE-X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; SSE-X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; SSE-X64-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE-X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; SSE-X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1] ; SSE-X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload ; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; SSE-X64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-X64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-X64-NEXT: callq fmaf@PLT ; SSE-X64-NEXT: callq fmaf@PLT
; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; SSE-X64-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE-X64-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE-X64-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload ; SSE-X64-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; SSE-X64-NEXT: # xmm1 = xmm1[0],mem[0] ; SSE-X64-NEXT: # xmm1 = xmm1[0],mem[0]
; SSE-X64-NEXT: movaps %xmm1, %xmm0 ; SSE-X64-NEXT: movaps %xmm1, %xmm0
; SSE-X64-NEXT: addq $88, %rsp ; SSE-X64-NEXT: addq $88, %rsp
; SSE-X64-NEXT: .cfi_def_cfa_offset 8 ; SSE-X64-NEXT: .cfi_def_cfa_offset 8
; SSE-X64-NEXT: retq ; SSE-X64-NEXT: retq
; ;
; AVX-LABEL: f13: ; AVX-LABEL: f13:
; AVX: # %bb.0: ; AVX: # %bb.0:
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; SSE-X86-NEXT: retl ; SSE-X86-NEXT: retl
; ;
; SSE-X64-LABEL: f14: ; SSE-X64-LABEL: f14:
; SSE-X64: # %bb.0: ; SSE-X64: # %bb.0:
; SSE-X64-NEXT: subq $72, %rsp ; SSE-X64-NEXT: subq $72, %rsp
; SSE-X64-NEXT: .cfi_def_cfa_offset 80 ; SSE-X64-NEXT: .cfi_def_cfa_offset 80
; SSE-X64-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; SSE-X64-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-X64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; SSE-X64-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-X64-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; SSE-X64-NEXT: callq fma@PLT
; SSE-X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; SSE-X64-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-X64-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-X64-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE-X64-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; SSE-X64-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; SSE-X64-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; SSE-X64-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1] ; SSE-X64-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; SSE-X64-NEXT: callq fma@PLT ; SSE-X64-NEXT: callq fma@PLT
; SSE-X64-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; SSE-X64-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE-X64-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; SSE-X64-NEXT: movaps %xmm1, %xmm0 ; SSE-X64-NEXT: callq fma@PLT
; SSE-X64-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; SSE-X64-NEXT: # xmm0 = xmm0[0],mem[0]
; SSE-X64-NEXT: addq $72, %rsp ; SSE-X64-NEXT: addq $72, %rsp
; SSE-X64-NEXT: .cfi_def_cfa_offset 8 ; SSE-X64-NEXT: .cfi_def_cfa_offset 8
; SSE-X64-NEXT: retq ; SSE-X64-NEXT: retq
; ;
; AVX-LABEL: f14: ; AVX-LABEL: f14:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vfmadd213pd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2 ; AVX-NEXT: vfmadd213pd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
; AVX-NEXT: ret{{[l|q]}} ; AVX-NEXT: ret{{[l|q]}}
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llvm/test/CodeGen/X86/vec-strict-cmp-128.ll

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define <4 x i32> @test_v4f32_ogt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 { define <4 x i32> @test_v4f32_ogt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
; SSE-32-LABEL: test_v4f32_ogt_q: ; SSE-32-LABEL: test_v4f32_ogt_q:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movaps 8(%ebp), %xmm3 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movaps %xmm3, %xmm4 ; SSE-32-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSE-32-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm3[3,3] ; SSE-32-NEXT: movhlps {{.*#+}} xmm5 = xmm2[1],xmm5[1]
; SSE-32-NEXT: movaps %xmm2, %xmm5
; SSE-32-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm2[3,3]
; SSE-32-NEXT: xorl %eax, %eax ; SSE-32-NEXT: xorl %eax, %eax
; SSE-32-NEXT: ucomiss %xmm4, %xmm5 ; SSE-32-NEXT: ucomiss %xmm4, %xmm5
; SSE-32-NEXT: movl $-1, %ecx ; SSE-32-NEXT: movl $-1, %ecx
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmoval %ecx, %edx ; SSE-32-NEXT: cmoval %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm5 ; SSE-32-NEXT: movd %edx, %xmm4
; SSE-32-NEXT: movaps %xmm3, %xmm4 ; SSE-32-NEXT: movaps %xmm3, %xmm5
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm3[1] ; SSE-32-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm3[3,3]
; SSE-32-NEXT: movaps %xmm2, %xmm6 ; SSE-32-NEXT: movaps %xmm2, %xmm6
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1] ; SSE-32-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm2[3,3]
; SSE-32-NEXT: ucomiss %xmm4, %xmm6 ; SSE-32-NEXT: ucomiss %xmm5, %xmm6
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmoval %ecx, %edx ; SSE-32-NEXT: cmoval %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm4 ; SSE-32-NEXT: movd %edx, %xmm5
; SSE-32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; SSE-32-NEXT: ucomiss %xmm3, %xmm2 ; SSE-32-NEXT: ucomiss %xmm3, %xmm2
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmoval %ecx, %edx ; SSE-32-NEXT: cmoval %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm5 ; SSE-32-NEXT: movd %edx, %xmm5
; SSE-32-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1] ; SSE-32-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1]
; SSE-32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-32-NEXT: ucomiss %xmm3, %xmm2 ; SSE-32-NEXT: ucomiss %xmm3, %xmm2
; SSE-32-NEXT: cmoval %ecx, %eax ; SSE-32-NEXT: cmoval %ecx, %eax
; SSE-32-NEXT: movd %eax, %xmm2 ; SSE-32-NEXT: movd %eax, %xmm2
; SSE-32-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE-32-NEXT: pand %xmm5, %xmm0 ; SSE-32-NEXT: pand %xmm5, %xmm0
; SSE-32-NEXT: pandn %xmm1, %xmm5 ; SSE-32-NEXT: pandn %xmm1, %xmm5
; SSE-32-NEXT: por %xmm5, %xmm0 ; SSE-32-NEXT: por %xmm5, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v4f32_ogt_q: ; SSE-64-LABEL: test_v4f32_ogt_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movaps %xmm3, %xmm4 ; SSE-64-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSE-64-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm3[3,3] ; SSE-64-NEXT: movhlps {{.*#+}} xmm5 = xmm2[1],xmm5[1]
; SSE-64-NEXT: movaps %xmm2, %xmm5
; SSE-64-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm2[3,3]
; SSE-64-NEXT: xorl %eax, %eax ; SSE-64-NEXT: xorl %eax, %eax
; SSE-64-NEXT: ucomiss %xmm4, %xmm5 ; SSE-64-NEXT: ucomiss %xmm4, %xmm5
; SSE-64-NEXT: movl $-1, %ecx ; SSE-64-NEXT: movl $-1, %ecx
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmoval %ecx, %edx ; SSE-64-NEXT: cmoval %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm4 ; SSE-64-NEXT: movd %edx, %xmm4
; SSE-64-NEXT: movaps %xmm3, %xmm5 ; SSE-64-NEXT: movaps %xmm3, %xmm5
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm3[1] ; SSE-64-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm3[3,3]
; SSE-64-NEXT: movaps %xmm2, %xmm6 ; SSE-64-NEXT: movaps %xmm2, %xmm6
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1] ; SSE-64-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm2[3,3]
; SSE-64-NEXT: ucomiss %xmm5, %xmm6 ; SSE-64-NEXT: ucomiss %xmm5, %xmm6
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmoval %ecx, %edx ; SSE-64-NEXT: cmoval %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm5 ; SSE-64-NEXT: movd %edx, %xmm5
; SSE-64-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; SSE-64-NEXT: ucomiss %xmm3, %xmm2 ; SSE-64-NEXT: ucomiss %xmm3, %xmm2
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmoval %ecx, %edx ; SSE-64-NEXT: cmoval %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm4 ; SSE-64-NEXT: movd %edx, %xmm5
; SSE-64-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1] ; SSE-64-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1]
; SSE-64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-64-NEXT: ucomiss %xmm3, %xmm2 ; SSE-64-NEXT: ucomiss %xmm3, %xmm2
; SSE-64-NEXT: cmoval %ecx, %eax ; SSE-64-NEXT: cmoval %ecx, %eax
; SSE-64-NEXT: movd %eax, %xmm2 ; SSE-64-NEXT: movd %eax, %xmm2
; SSE-64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE-64-NEXT: pand %xmm4, %xmm0 ; SSE-64-NEXT: pand %xmm5, %xmm0
; SSE-64-NEXT: pandn %xmm1, %xmm4 ; SSE-64-NEXT: pandn %xmm1, %xmm5
; SSE-64-NEXT: por %xmm4, %xmm0 ; SSE-64-NEXT: por %xmm5, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v4f32_ogt_q: ; AVX-32-LABEL: test_v4f32_ogt_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
define <4 x i32> @test_v4f32_oge_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 { define <4 x i32> @test_v4f32_oge_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
; SSE-32-LABEL: test_v4f32_oge_q: ; SSE-32-LABEL: test_v4f32_oge_q:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movaps 8(%ebp), %xmm3 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movaps %xmm3, %xmm4 ; SSE-32-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSE-32-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm3[3,3] ; SSE-32-NEXT: movhlps {{.*#+}} xmm5 = xmm2[1],xmm5[1]
; SSE-32-NEXT: movaps %xmm2, %xmm5
; SSE-32-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm2[3,3]
; SSE-32-NEXT: xorl %eax, %eax ; SSE-32-NEXT: xorl %eax, %eax
; SSE-32-NEXT: ucomiss %xmm4, %xmm5 ; SSE-32-NEXT: ucomiss %xmm4, %xmm5
; SSE-32-NEXT: movl $-1, %ecx ; SSE-32-NEXT: movl $-1, %ecx
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovael %ecx, %edx ; SSE-32-NEXT: cmovael %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm5 ; SSE-32-NEXT: movd %edx, %xmm4
; SSE-32-NEXT: movaps %xmm3, %xmm4 ; SSE-32-NEXT: movaps %xmm3, %xmm5
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm3[1] ; SSE-32-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm3[3,3]
; SSE-32-NEXT: movaps %xmm2, %xmm6 ; SSE-32-NEXT: movaps %xmm2, %xmm6
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1] ; SSE-32-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm2[3,3]
; SSE-32-NEXT: ucomiss %xmm4, %xmm6 ; SSE-32-NEXT: ucomiss %xmm5, %xmm6
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovael %ecx, %edx ; SSE-32-NEXT: cmovael %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm4 ; SSE-32-NEXT: movd %edx, %xmm5
; SSE-32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; SSE-32-NEXT: ucomiss %xmm3, %xmm2 ; SSE-32-NEXT: ucomiss %xmm3, %xmm2
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovael %ecx, %edx ; SSE-32-NEXT: cmovael %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm5 ; SSE-32-NEXT: movd %edx, %xmm5
; SSE-32-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1] ; SSE-32-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1]
; SSE-32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-32-NEXT: ucomiss %xmm3, %xmm2 ; SSE-32-NEXT: ucomiss %xmm3, %xmm2
; SSE-32-NEXT: cmovael %ecx, %eax ; SSE-32-NEXT: cmovael %ecx, %eax
; SSE-32-NEXT: movd %eax, %xmm2 ; SSE-32-NEXT: movd %eax, %xmm2
; SSE-32-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE-32-NEXT: pand %xmm5, %xmm0 ; SSE-32-NEXT: pand %xmm5, %xmm0
; SSE-32-NEXT: pandn %xmm1, %xmm5 ; SSE-32-NEXT: pandn %xmm1, %xmm5
; SSE-32-NEXT: por %xmm5, %xmm0 ; SSE-32-NEXT: por %xmm5, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v4f32_oge_q: ; SSE-64-LABEL: test_v4f32_oge_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movaps %xmm3, %xmm4 ; SSE-64-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSE-64-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm3[3,3] ; SSE-64-NEXT: movhlps {{.*#+}} xmm5 = xmm2[1],xmm5[1]
; SSE-64-NEXT: movaps %xmm2, %xmm5
; SSE-64-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm2[3,3]
; SSE-64-NEXT: xorl %eax, %eax ; SSE-64-NEXT: xorl %eax, %eax
; SSE-64-NEXT: ucomiss %xmm4, %xmm5 ; SSE-64-NEXT: ucomiss %xmm4, %xmm5
; SSE-64-NEXT: movl $-1, %ecx ; SSE-64-NEXT: movl $-1, %ecx
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovael %ecx, %edx ; SSE-64-NEXT: cmovael %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm4 ; SSE-64-NEXT: movd %edx, %xmm4
; SSE-64-NEXT: movaps %xmm3, %xmm5 ; SSE-64-NEXT: movaps %xmm3, %xmm5
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm3[1] ; SSE-64-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm3[3,3]
; SSE-64-NEXT: movaps %xmm2, %xmm6 ; SSE-64-NEXT: movaps %xmm2, %xmm6
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1] ; SSE-64-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm2[3,3]
; SSE-64-NEXT: ucomiss %xmm5, %xmm6 ; SSE-64-NEXT: ucomiss %xmm5, %xmm6
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovael %ecx, %edx ; SSE-64-NEXT: cmovael %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm5 ; SSE-64-NEXT: movd %edx, %xmm5
; SSE-64-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; SSE-64-NEXT: ucomiss %xmm3, %xmm2 ; SSE-64-NEXT: ucomiss %xmm3, %xmm2
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovael %ecx, %edx ; SSE-64-NEXT: cmovael %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm4 ; SSE-64-NEXT: movd %edx, %xmm5
; SSE-64-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1] ; SSE-64-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1]
; SSE-64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-64-NEXT: ucomiss %xmm3, %xmm2 ; SSE-64-NEXT: ucomiss %xmm3, %xmm2
; SSE-64-NEXT: cmovael %ecx, %eax ; SSE-64-NEXT: cmovael %ecx, %eax
; SSE-64-NEXT: movd %eax, %xmm2 ; SSE-64-NEXT: movd %eax, %xmm2
; SSE-64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE-64-NEXT: pand %xmm4, %xmm0 ; SSE-64-NEXT: pand %xmm5, %xmm0
; SSE-64-NEXT: pandn %xmm1, %xmm4 ; SSE-64-NEXT: pandn %xmm1, %xmm5
; SSE-64-NEXT: por %xmm4, %xmm0 ; SSE-64-NEXT: por %xmm5, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v4f32_oge_q: ; AVX-32-LABEL: test_v4f32_oge_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
define <4 x i32> @test_v4f32_olt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 { define <4 x i32> @test_v4f32_olt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
; SSE-32-LABEL: test_v4f32_olt_q: ; SSE-32-LABEL: test_v4f32_olt_q:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movaps 8(%ebp), %xmm3 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSE-32-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm2[3,3] ; SSE-32-NEXT: movhlps {{.*#+}} xmm5 = xmm3[1],xmm5[1]
; SSE-32-NEXT: movaps %xmm3, %xmm5
; SSE-32-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm3[3,3]
; SSE-32-NEXT: xorl %eax, %eax ; SSE-32-NEXT: xorl %eax, %eax
; SSE-32-NEXT: ucomiss %xmm4, %xmm5 ; SSE-32-NEXT: ucomiss %xmm4, %xmm5
; SSE-32-NEXT: movl $-1, %ecx ; SSE-32-NEXT: movl $-1, %ecx
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmoval %ecx, %edx ; SSE-32-NEXT: cmoval %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm5 ; SSE-32-NEXT: movd %edx, %xmm4
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movaps %xmm2, %xmm5
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm2[1] ; SSE-32-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm2[3,3]
; SSE-32-NEXT: movaps %xmm3, %xmm6 ; SSE-32-NEXT: movaps %xmm3, %xmm6
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm3[1] ; SSE-32-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm3[3,3]
; SSE-32-NEXT: ucomiss %xmm4, %xmm6 ; SSE-32-NEXT: ucomiss %xmm5, %xmm6
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmoval %ecx, %edx ; SSE-32-NEXT: cmoval %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm4 ; SSE-32-NEXT: movd %edx, %xmm5
; SSE-32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; SSE-32-NEXT: ucomiss %xmm2, %xmm3 ; SSE-32-NEXT: ucomiss %xmm2, %xmm3
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmoval %ecx, %edx ; SSE-32-NEXT: cmoval %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm5 ; SSE-32-NEXT: movd %edx, %xmm5
; SSE-32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-32-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1] ; SSE-32-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1]
; SSE-32-NEXT: ucomiss %xmm2, %xmm3 ; SSE-32-NEXT: ucomiss %xmm2, %xmm3
; SSE-32-NEXT: cmoval %ecx, %eax ; SSE-32-NEXT: cmoval %ecx, %eax
; SSE-32-NEXT: movd %eax, %xmm2 ; SSE-32-NEXT: movd %eax, %xmm2
; SSE-32-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE-32-NEXT: pand %xmm5, %xmm0 ; SSE-32-NEXT: pand %xmm5, %xmm0
; SSE-32-NEXT: pandn %xmm1, %xmm5 ; SSE-32-NEXT: pandn %xmm1, %xmm5
; SSE-32-NEXT: por %xmm5, %xmm0 ; SSE-32-NEXT: por %xmm5, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v4f32_olt_q: ; SSE-64-LABEL: test_v4f32_olt_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movaps %xmm2, %xmm4 ; SSE-64-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSE-64-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm2[3,3] ; SSE-64-NEXT: movhlps {{.*#+}} xmm5 = xmm3[1],xmm5[1]
; SSE-64-NEXT: movaps %xmm3, %xmm5
; SSE-64-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm3[3,3]
; SSE-64-NEXT: xorl %eax, %eax ; SSE-64-NEXT: xorl %eax, %eax
; SSE-64-NEXT: ucomiss %xmm4, %xmm5 ; SSE-64-NEXT: ucomiss %xmm4, %xmm5
; SSE-64-NEXT: movl $-1, %ecx ; SSE-64-NEXT: movl $-1, %ecx
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmoval %ecx, %edx ; SSE-64-NEXT: cmoval %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm4 ; SSE-64-NEXT: movd %edx, %xmm4
; SSE-64-NEXT: movaps %xmm2, %xmm5 ; SSE-64-NEXT: movaps %xmm2, %xmm5
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm2[1] ; SSE-64-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm2[3,3]
; SSE-64-NEXT: movaps %xmm3, %xmm6 ; SSE-64-NEXT: movaps %xmm3, %xmm6
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm3[1] ; SSE-64-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm3[3,3]
; SSE-64-NEXT: ucomiss %xmm5, %xmm6 ; SSE-64-NEXT: ucomiss %xmm5, %xmm6
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmoval %ecx, %edx ; SSE-64-NEXT: cmoval %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm5 ; SSE-64-NEXT: movd %edx, %xmm5
; SSE-64-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; SSE-64-NEXT: ucomiss %xmm2, %xmm3 ; SSE-64-NEXT: ucomiss %xmm2, %xmm3
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmoval %ecx, %edx ; SSE-64-NEXT: cmoval %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm4 ; SSE-64-NEXT: movd %edx, %xmm5
; SSE-64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-64-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1] ; SSE-64-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1]
; SSE-64-NEXT: ucomiss %xmm2, %xmm3 ; SSE-64-NEXT: ucomiss %xmm2, %xmm3
; SSE-64-NEXT: cmoval %ecx, %eax ; SSE-64-NEXT: cmoval %ecx, %eax
; SSE-64-NEXT: movd %eax, %xmm2 ; SSE-64-NEXT: movd %eax, %xmm2
; SSE-64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE-64-NEXT: pand %xmm4, %xmm0 ; SSE-64-NEXT: pand %xmm5, %xmm0
; SSE-64-NEXT: pandn %xmm1, %xmm4 ; SSE-64-NEXT: pandn %xmm1, %xmm5
; SSE-64-NEXT: por %xmm4, %xmm0 ; SSE-64-NEXT: por %xmm5, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v4f32_olt_q: ; AVX-32-LABEL: test_v4f32_olt_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
define <4 x i32> @test_v4f32_ole_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 { define <4 x i32> @test_v4f32_ole_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
; SSE-32-LABEL: test_v4f32_ole_q: ; SSE-32-LABEL: test_v4f32_ole_q:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movaps 8(%ebp), %xmm3 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSE-32-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm2[3,3] ; SSE-32-NEXT: movhlps {{.*#+}} xmm5 = xmm3[1],xmm5[1]
; SSE-32-NEXT: movaps %xmm3, %xmm5
; SSE-32-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm3[3,3]
; SSE-32-NEXT: xorl %eax, %eax ; SSE-32-NEXT: xorl %eax, %eax
; SSE-32-NEXT: ucomiss %xmm4, %xmm5 ; SSE-32-NEXT: ucomiss %xmm4, %xmm5
; SSE-32-NEXT: movl $-1, %ecx ; SSE-32-NEXT: movl $-1, %ecx
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovael %ecx, %edx ; SSE-32-NEXT: cmovael %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm5 ; SSE-32-NEXT: movd %edx, %xmm4
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movaps %xmm2, %xmm5
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm2[1] ; SSE-32-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm2[3,3]
; SSE-32-NEXT: movaps %xmm3, %xmm6 ; SSE-32-NEXT: movaps %xmm3, %xmm6
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm3[1] ; SSE-32-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm3[3,3]
; SSE-32-NEXT: ucomiss %xmm4, %xmm6 ; SSE-32-NEXT: ucomiss %xmm5, %xmm6
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovael %ecx, %edx ; SSE-32-NEXT: cmovael %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm4 ; SSE-32-NEXT: movd %edx, %xmm5
; SSE-32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; SSE-32-NEXT: ucomiss %xmm2, %xmm3 ; SSE-32-NEXT: ucomiss %xmm2, %xmm3
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovael %ecx, %edx ; SSE-32-NEXT: cmovael %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm5 ; SSE-32-NEXT: movd %edx, %xmm5
; SSE-32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-32-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1] ; SSE-32-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1]
; SSE-32-NEXT: ucomiss %xmm2, %xmm3 ; SSE-32-NEXT: ucomiss %xmm2, %xmm3
; SSE-32-NEXT: cmovael %ecx, %eax ; SSE-32-NEXT: cmovael %ecx, %eax
; SSE-32-NEXT: movd %eax, %xmm2 ; SSE-32-NEXT: movd %eax, %xmm2
; SSE-32-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE-32-NEXT: pand %xmm5, %xmm0 ; SSE-32-NEXT: pand %xmm5, %xmm0
; SSE-32-NEXT: pandn %xmm1, %xmm5 ; SSE-32-NEXT: pandn %xmm1, %xmm5
; SSE-32-NEXT: por %xmm5, %xmm0 ; SSE-32-NEXT: por %xmm5, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v4f32_ole_q: ; SSE-64-LABEL: test_v4f32_ole_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movaps %xmm2, %xmm4 ; SSE-64-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSE-64-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm2[3,3] ; SSE-64-NEXT: movhlps {{.*#+}} xmm5 = xmm3[1],xmm5[1]
; SSE-64-NEXT: movaps %xmm3, %xmm5
; SSE-64-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm3[3,3]
; SSE-64-NEXT: xorl %eax, %eax ; SSE-64-NEXT: xorl %eax, %eax
; SSE-64-NEXT: ucomiss %xmm4, %xmm5 ; SSE-64-NEXT: ucomiss %xmm4, %xmm5
; SSE-64-NEXT: movl $-1, %ecx ; SSE-64-NEXT: movl $-1, %ecx
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovael %ecx, %edx ; SSE-64-NEXT: cmovael %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm4 ; SSE-64-NEXT: movd %edx, %xmm4
; SSE-64-NEXT: movaps %xmm2, %xmm5 ; SSE-64-NEXT: movaps %xmm2, %xmm5
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm2[1] ; SSE-64-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm2[3,3]
; SSE-64-NEXT: movaps %xmm3, %xmm6 ; SSE-64-NEXT: movaps %xmm3, %xmm6
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm3[1] ; SSE-64-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm3[3,3]
; SSE-64-NEXT: ucomiss %xmm5, %xmm6 ; SSE-64-NEXT: ucomiss %xmm5, %xmm6
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovael %ecx, %edx ; SSE-64-NEXT: cmovael %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm5 ; SSE-64-NEXT: movd %edx, %xmm5
; SSE-64-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; SSE-64-NEXT: ucomiss %xmm2, %xmm3 ; SSE-64-NEXT: ucomiss %xmm2, %xmm3
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovael %ecx, %edx ; SSE-64-NEXT: cmovael %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm4 ; SSE-64-NEXT: movd %edx, %xmm5
; SSE-64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-64-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1] ; SSE-64-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1]
; SSE-64-NEXT: ucomiss %xmm2, %xmm3 ; SSE-64-NEXT: ucomiss %xmm2, %xmm3
; SSE-64-NEXT: cmovael %ecx, %eax ; SSE-64-NEXT: cmovael %ecx, %eax
; SSE-64-NEXT: movd %eax, %xmm2 ; SSE-64-NEXT: movd %eax, %xmm2
; SSE-64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE-64-NEXT: pand %xmm4, %xmm0 ; SSE-64-NEXT: pand %xmm5, %xmm0
; SSE-64-NEXT: pandn %xmm1, %xmm4 ; SSE-64-NEXT: pandn %xmm1, %xmm5
; SSE-64-NEXT: por %xmm4, %xmm0 ; SSE-64-NEXT: por %xmm5, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v4f32_ole_q: ; AVX-32-LABEL: test_v4f32_ole_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 357 Lines • ▼ Show 20 Lines
define <4 x i32> @test_v4f32_ugt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 { define <4 x i32> @test_v4f32_ugt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
; SSE-32-LABEL: test_v4f32_ugt_q: ; SSE-32-LABEL: test_v4f32_ugt_q:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movaps 8(%ebp), %xmm3 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSE-32-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm2[3,3] ; SSE-32-NEXT: movhlps {{.*#+}} xmm5 = xmm3[1],xmm5[1]
; SSE-32-NEXT: movaps %xmm3, %xmm5
; SSE-32-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm3[3,3]
; SSE-32-NEXT: xorl %eax, %eax ; SSE-32-NEXT: xorl %eax, %eax
; SSE-32-NEXT: ucomiss %xmm4, %xmm5 ; SSE-32-NEXT: ucomiss %xmm4, %xmm5
; SSE-32-NEXT: movl $-1, %ecx ; SSE-32-NEXT: movl $-1, %ecx
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovbl %ecx, %edx ; SSE-32-NEXT: cmovbl %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm5 ; SSE-32-NEXT: movd %edx, %xmm4
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movaps %xmm2, %xmm5
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm2[1] ; SSE-32-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm2[3,3]
; SSE-32-NEXT: movaps %xmm3, %xmm6 ; SSE-32-NEXT: movaps %xmm3, %xmm6
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm3[1] ; SSE-32-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm3[3,3]
; SSE-32-NEXT: ucomiss %xmm4, %xmm6 ; SSE-32-NEXT: ucomiss %xmm5, %xmm6
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovbl %ecx, %edx ; SSE-32-NEXT: cmovbl %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm4 ; SSE-32-NEXT: movd %edx, %xmm5
; SSE-32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; SSE-32-NEXT: ucomiss %xmm2, %xmm3 ; SSE-32-NEXT: ucomiss %xmm2, %xmm3
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovbl %ecx, %edx ; SSE-32-NEXT: cmovbl %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm5 ; SSE-32-NEXT: movd %edx, %xmm5
; SSE-32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-32-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1] ; SSE-32-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1]
; SSE-32-NEXT: ucomiss %xmm2, %xmm3 ; SSE-32-NEXT: ucomiss %xmm2, %xmm3
; SSE-32-NEXT: cmovbl %ecx, %eax ; SSE-32-NEXT: cmovbl %ecx, %eax
; SSE-32-NEXT: movd %eax, %xmm2 ; SSE-32-NEXT: movd %eax, %xmm2
; SSE-32-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE-32-NEXT: pand %xmm5, %xmm0 ; SSE-32-NEXT: pand %xmm5, %xmm0
; SSE-32-NEXT: pandn %xmm1, %xmm5 ; SSE-32-NEXT: pandn %xmm1, %xmm5
; SSE-32-NEXT: por %xmm5, %xmm0 ; SSE-32-NEXT: por %xmm5, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v4f32_ugt_q: ; SSE-64-LABEL: test_v4f32_ugt_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movaps %xmm2, %xmm4 ; SSE-64-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSE-64-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm2[3,3] ; SSE-64-NEXT: movhlps {{.*#+}} xmm5 = xmm3[1],xmm5[1]
; SSE-64-NEXT: movaps %xmm3, %xmm5
; SSE-64-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm3[3,3]
; SSE-64-NEXT: xorl %eax, %eax ; SSE-64-NEXT: xorl %eax, %eax
; SSE-64-NEXT: ucomiss %xmm4, %xmm5 ; SSE-64-NEXT: ucomiss %xmm4, %xmm5
; SSE-64-NEXT: movl $-1, %ecx ; SSE-64-NEXT: movl $-1, %ecx
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovbl %ecx, %edx ; SSE-64-NEXT: cmovbl %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm4 ; SSE-64-NEXT: movd %edx, %xmm4
; SSE-64-NEXT: movaps %xmm2, %xmm5 ; SSE-64-NEXT: movaps %xmm2, %xmm5
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm2[1] ; SSE-64-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm2[3,3]
; SSE-64-NEXT: movaps %xmm3, %xmm6 ; SSE-64-NEXT: movaps %xmm3, %xmm6
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm3[1] ; SSE-64-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm3[3,3]
; SSE-64-NEXT: ucomiss %xmm5, %xmm6 ; SSE-64-NEXT: ucomiss %xmm5, %xmm6
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovbl %ecx, %edx ; SSE-64-NEXT: cmovbl %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm5 ; SSE-64-NEXT: movd %edx, %xmm5
; SSE-64-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; SSE-64-NEXT: ucomiss %xmm2, %xmm3 ; SSE-64-NEXT: ucomiss %xmm2, %xmm3
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovbl %ecx, %edx ; SSE-64-NEXT: cmovbl %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm4 ; SSE-64-NEXT: movd %edx, %xmm5
; SSE-64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-64-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1] ; SSE-64-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1]
; SSE-64-NEXT: ucomiss %xmm2, %xmm3 ; SSE-64-NEXT: ucomiss %xmm2, %xmm3
; SSE-64-NEXT: cmovbl %ecx, %eax ; SSE-64-NEXT: cmovbl %ecx, %eax
; SSE-64-NEXT: movd %eax, %xmm2 ; SSE-64-NEXT: movd %eax, %xmm2
; SSE-64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE-64-NEXT: pand %xmm4, %xmm0 ; SSE-64-NEXT: pand %xmm5, %xmm0
; SSE-64-NEXT: pandn %xmm1, %xmm4 ; SSE-64-NEXT: pandn %xmm1, %xmm5
; SSE-64-NEXT: por %xmm4, %xmm0 ; SSE-64-NEXT: por %xmm5, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v4f32_ugt_q: ; AVX-32-LABEL: test_v4f32_ugt_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
define <4 x i32> @test_v4f32_uge_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 { define <4 x i32> @test_v4f32_uge_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
; SSE-32-LABEL: test_v4f32_uge_q: ; SSE-32-LABEL: test_v4f32_uge_q:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movaps 8(%ebp), %xmm3 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSE-32-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm2[3,3] ; SSE-32-NEXT: movhlps {{.*#+}} xmm5 = xmm3[1],xmm5[1]
; SSE-32-NEXT: movaps %xmm3, %xmm5
; SSE-32-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm3[3,3]
; SSE-32-NEXT: xorl %eax, %eax ; SSE-32-NEXT: xorl %eax, %eax
; SSE-32-NEXT: ucomiss %xmm4, %xmm5 ; SSE-32-NEXT: ucomiss %xmm4, %xmm5
; SSE-32-NEXT: movl $-1, %ecx ; SSE-32-NEXT: movl $-1, %ecx
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovbel %ecx, %edx ; SSE-32-NEXT: cmovbel %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm5 ; SSE-32-NEXT: movd %edx, %xmm4
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movaps %xmm2, %xmm5
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm2[1] ; SSE-32-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm2[3,3]
; SSE-32-NEXT: movaps %xmm3, %xmm6 ; SSE-32-NEXT: movaps %xmm3, %xmm6
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm3[1] ; SSE-32-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm3[3,3]
; SSE-32-NEXT: ucomiss %xmm4, %xmm6 ; SSE-32-NEXT: ucomiss %xmm5, %xmm6
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovbel %ecx, %edx ; SSE-32-NEXT: cmovbel %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm4 ; SSE-32-NEXT: movd %edx, %xmm5
; SSE-32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; SSE-32-NEXT: ucomiss %xmm2, %xmm3 ; SSE-32-NEXT: ucomiss %xmm2, %xmm3
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovbel %ecx, %edx ; SSE-32-NEXT: cmovbel %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm5 ; SSE-32-NEXT: movd %edx, %xmm5
; SSE-32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-32-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1] ; SSE-32-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1]
; SSE-32-NEXT: ucomiss %xmm2, %xmm3 ; SSE-32-NEXT: ucomiss %xmm2, %xmm3
; SSE-32-NEXT: cmovbel %ecx, %eax ; SSE-32-NEXT: cmovbel %ecx, %eax
; SSE-32-NEXT: movd %eax, %xmm2 ; SSE-32-NEXT: movd %eax, %xmm2
; SSE-32-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE-32-NEXT: pand %xmm5, %xmm0 ; SSE-32-NEXT: pand %xmm5, %xmm0
; SSE-32-NEXT: pandn %xmm1, %xmm5 ; SSE-32-NEXT: pandn %xmm1, %xmm5
; SSE-32-NEXT: por %xmm5, %xmm0 ; SSE-32-NEXT: por %xmm5, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v4f32_uge_q: ; SSE-64-LABEL: test_v4f32_uge_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movaps %xmm2, %xmm4 ; SSE-64-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSE-64-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm2[3,3] ; SSE-64-NEXT: movhlps {{.*#+}} xmm5 = xmm3[1],xmm5[1]
; SSE-64-NEXT: movaps %xmm3, %xmm5
; SSE-64-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm3[3,3]
; SSE-64-NEXT: xorl %eax, %eax ; SSE-64-NEXT: xorl %eax, %eax
; SSE-64-NEXT: ucomiss %xmm4, %xmm5 ; SSE-64-NEXT: ucomiss %xmm4, %xmm5
; SSE-64-NEXT: movl $-1, %ecx ; SSE-64-NEXT: movl $-1, %ecx
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovbel %ecx, %edx ; SSE-64-NEXT: cmovbel %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm4 ; SSE-64-NEXT: movd %edx, %xmm4
; SSE-64-NEXT: movaps %xmm2, %xmm5 ; SSE-64-NEXT: movaps %xmm2, %xmm5
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm2[1] ; SSE-64-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm2[3,3]
; SSE-64-NEXT: movaps %xmm3, %xmm6 ; SSE-64-NEXT: movaps %xmm3, %xmm6
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm3[1] ; SSE-64-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm3[3,3]
; SSE-64-NEXT: ucomiss %xmm5, %xmm6 ; SSE-64-NEXT: ucomiss %xmm5, %xmm6
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovbel %ecx, %edx ; SSE-64-NEXT: cmovbel %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm5 ; SSE-64-NEXT: movd %edx, %xmm5
; SSE-64-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; SSE-64-NEXT: ucomiss %xmm2, %xmm3 ; SSE-64-NEXT: ucomiss %xmm2, %xmm3
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovbel %ecx, %edx ; SSE-64-NEXT: cmovbel %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm4 ; SSE-64-NEXT: movd %edx, %xmm5
; SSE-64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-64-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1] ; SSE-64-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1]
; SSE-64-NEXT: ucomiss %xmm2, %xmm3 ; SSE-64-NEXT: ucomiss %xmm2, %xmm3
; SSE-64-NEXT: cmovbel %ecx, %eax ; SSE-64-NEXT: cmovbel %ecx, %eax
; SSE-64-NEXT: movd %eax, %xmm2 ; SSE-64-NEXT: movd %eax, %xmm2
; SSE-64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE-64-NEXT: pand %xmm4, %xmm0 ; SSE-64-NEXT: pand %xmm5, %xmm0
; SSE-64-NEXT: pandn %xmm1, %xmm4 ; SSE-64-NEXT: pandn %xmm1, %xmm5
; SSE-64-NEXT: por %xmm4, %xmm0 ; SSE-64-NEXT: por %xmm5, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v4f32_uge_q: ; AVX-32-LABEL: test_v4f32_uge_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
define <4 x i32> @test_v4f32_ult_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 { define <4 x i32> @test_v4f32_ult_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
; SSE-32-LABEL: test_v4f32_ult_q: ; SSE-32-LABEL: test_v4f32_ult_q:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movaps 8(%ebp), %xmm3 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movaps %xmm3, %xmm4 ; SSE-32-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSE-32-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm3[3,3] ; SSE-32-NEXT: movhlps {{.*#+}} xmm5 = xmm2[1],xmm5[1]
; SSE-32-NEXT: movaps %xmm2, %xmm5
; SSE-32-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm2[3,3]
; SSE-32-NEXT: xorl %eax, %eax ; SSE-32-NEXT: xorl %eax, %eax
; SSE-32-NEXT: ucomiss %xmm4, %xmm5 ; SSE-32-NEXT: ucomiss %xmm4, %xmm5
; SSE-32-NEXT: movl $-1, %ecx ; SSE-32-NEXT: movl $-1, %ecx
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovbl %ecx, %edx ; SSE-32-NEXT: cmovbl %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm5 ; SSE-32-NEXT: movd %edx, %xmm4
; SSE-32-NEXT: movaps %xmm3, %xmm4 ; SSE-32-NEXT: movaps %xmm3, %xmm5
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm3[1] ; SSE-32-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm3[3,3]
; SSE-32-NEXT: movaps %xmm2, %xmm6 ; SSE-32-NEXT: movaps %xmm2, %xmm6
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1] ; SSE-32-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm2[3,3]
; SSE-32-NEXT: ucomiss %xmm4, %xmm6 ; SSE-32-NEXT: ucomiss %xmm5, %xmm6
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovbl %ecx, %edx ; SSE-32-NEXT: cmovbl %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm4 ; SSE-32-NEXT: movd %edx, %xmm5
; SSE-32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; SSE-32-NEXT: ucomiss %xmm3, %xmm2 ; SSE-32-NEXT: ucomiss %xmm3, %xmm2
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovbl %ecx, %edx ; SSE-32-NEXT: cmovbl %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm5 ; SSE-32-NEXT: movd %edx, %xmm5
; SSE-32-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1] ; SSE-32-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1]
; SSE-32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-32-NEXT: ucomiss %xmm3, %xmm2 ; SSE-32-NEXT: ucomiss %xmm3, %xmm2
; SSE-32-NEXT: cmovbl %ecx, %eax ; SSE-32-NEXT: cmovbl %ecx, %eax
; SSE-32-NEXT: movd %eax, %xmm2 ; SSE-32-NEXT: movd %eax, %xmm2
; SSE-32-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE-32-NEXT: pand %xmm5, %xmm0 ; SSE-32-NEXT: pand %xmm5, %xmm0
; SSE-32-NEXT: pandn %xmm1, %xmm5 ; SSE-32-NEXT: pandn %xmm1, %xmm5
; SSE-32-NEXT: por %xmm5, %xmm0 ; SSE-32-NEXT: por %xmm5, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v4f32_ult_q: ; SSE-64-LABEL: test_v4f32_ult_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movaps %xmm3, %xmm4 ; SSE-64-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSE-64-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm3[3,3] ; SSE-64-NEXT: movhlps {{.*#+}} xmm5 = xmm2[1],xmm5[1]
; SSE-64-NEXT: movaps %xmm2, %xmm5
; SSE-64-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm2[3,3]
; SSE-64-NEXT: xorl %eax, %eax ; SSE-64-NEXT: xorl %eax, %eax
; SSE-64-NEXT: ucomiss %xmm4, %xmm5 ; SSE-64-NEXT: ucomiss %xmm4, %xmm5
; SSE-64-NEXT: movl $-1, %ecx ; SSE-64-NEXT: movl $-1, %ecx
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovbl %ecx, %edx ; SSE-64-NEXT: cmovbl %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm4 ; SSE-64-NEXT: movd %edx, %xmm4
; SSE-64-NEXT: movaps %xmm3, %xmm5 ; SSE-64-NEXT: movaps %xmm3, %xmm5
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm3[1] ; SSE-64-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm3[3,3]
; SSE-64-NEXT: movaps %xmm2, %xmm6 ; SSE-64-NEXT: movaps %xmm2, %xmm6
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1] ; SSE-64-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm2[3,3]
; SSE-64-NEXT: ucomiss %xmm5, %xmm6 ; SSE-64-NEXT: ucomiss %xmm5, %xmm6
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovbl %ecx, %edx ; SSE-64-NEXT: cmovbl %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm5 ; SSE-64-NEXT: movd %edx, %xmm5
; SSE-64-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; SSE-64-NEXT: ucomiss %xmm3, %xmm2 ; SSE-64-NEXT: ucomiss %xmm3, %xmm2
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovbl %ecx, %edx ; SSE-64-NEXT: cmovbl %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm4 ; SSE-64-NEXT: movd %edx, %xmm5
; SSE-64-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1] ; SSE-64-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1]
; SSE-64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-64-NEXT: ucomiss %xmm3, %xmm2 ; SSE-64-NEXT: ucomiss %xmm3, %xmm2
; SSE-64-NEXT: cmovbl %ecx, %eax ; SSE-64-NEXT: cmovbl %ecx, %eax
; SSE-64-NEXT: movd %eax, %xmm2 ; SSE-64-NEXT: movd %eax, %xmm2
; SSE-64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE-64-NEXT: pand %xmm4, %xmm0 ; SSE-64-NEXT: pand %xmm5, %xmm0
; SSE-64-NEXT: pandn %xmm1, %xmm4 ; SSE-64-NEXT: pandn %xmm1, %xmm5
; SSE-64-NEXT: por %xmm4, %xmm0 ; SSE-64-NEXT: por %xmm5, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v4f32_ult_q: ; AVX-32-LABEL: test_v4f32_ult_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
define <4 x i32> @test_v4f32_ule_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 { define <4 x i32> @test_v4f32_ule_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
; SSE-32-LABEL: test_v4f32_ule_q: ; SSE-32-LABEL: test_v4f32_ule_q:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movaps 8(%ebp), %xmm3 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movaps %xmm3, %xmm4 ; SSE-32-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSE-32-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm3[3,3] ; SSE-32-NEXT: movhlps {{.*#+}} xmm5 = xmm2[1],xmm5[1]
; SSE-32-NEXT: movaps %xmm2, %xmm5
; SSE-32-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm2[3,3]
; SSE-32-NEXT: xorl %eax, %eax ; SSE-32-NEXT: xorl %eax, %eax
; SSE-32-NEXT: ucomiss %xmm4, %xmm5 ; SSE-32-NEXT: ucomiss %xmm4, %xmm5
; SSE-32-NEXT: movl $-1, %ecx ; SSE-32-NEXT: movl $-1, %ecx
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovbel %ecx, %edx ; SSE-32-NEXT: cmovbel %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm5 ; SSE-32-NEXT: movd %edx, %xmm4
; SSE-32-NEXT: movaps %xmm3, %xmm4 ; SSE-32-NEXT: movaps %xmm3, %xmm5
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm3[1] ; SSE-32-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm3[3,3]
; SSE-32-NEXT: movaps %xmm2, %xmm6 ; SSE-32-NEXT: movaps %xmm2, %xmm6
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1] ; SSE-32-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm2[3,3]
; SSE-32-NEXT: ucomiss %xmm4, %xmm6 ; SSE-32-NEXT: ucomiss %xmm5, %xmm6
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovbel %ecx, %edx ; SSE-32-NEXT: cmovbel %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm4 ; SSE-32-NEXT: movd %edx, %xmm5
; SSE-32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; SSE-32-NEXT: ucomiss %xmm3, %xmm2 ; SSE-32-NEXT: ucomiss %xmm3, %xmm2
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovbel %ecx, %edx ; SSE-32-NEXT: cmovbel %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm5 ; SSE-32-NEXT: movd %edx, %xmm5
; SSE-32-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1] ; SSE-32-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1]
; SSE-32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-32-NEXT: ucomiss %xmm3, %xmm2 ; SSE-32-NEXT: ucomiss %xmm3, %xmm2
; SSE-32-NEXT: cmovbel %ecx, %eax ; SSE-32-NEXT: cmovbel %ecx, %eax
; SSE-32-NEXT: movd %eax, %xmm2 ; SSE-32-NEXT: movd %eax, %xmm2
; SSE-32-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE-32-NEXT: pand %xmm5, %xmm0 ; SSE-32-NEXT: pand %xmm5, %xmm0
; SSE-32-NEXT: pandn %xmm1, %xmm5 ; SSE-32-NEXT: pandn %xmm1, %xmm5
; SSE-32-NEXT: por %xmm5, %xmm0 ; SSE-32-NEXT: por %xmm5, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v4f32_ule_q: ; SSE-64-LABEL: test_v4f32_ule_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movaps %xmm3, %xmm4 ; SSE-64-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSE-64-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm3[3,3] ; SSE-64-NEXT: movhlps {{.*#+}} xmm5 = xmm2[1],xmm5[1]
; SSE-64-NEXT: movaps %xmm2, %xmm5
; SSE-64-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm2[3,3]
; SSE-64-NEXT: xorl %eax, %eax ; SSE-64-NEXT: xorl %eax, %eax
; SSE-64-NEXT: ucomiss %xmm4, %xmm5 ; SSE-64-NEXT: ucomiss %xmm4, %xmm5
; SSE-64-NEXT: movl $-1, %ecx ; SSE-64-NEXT: movl $-1, %ecx
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovbel %ecx, %edx ; SSE-64-NEXT: cmovbel %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm4 ; SSE-64-NEXT: movd %edx, %xmm4
; SSE-64-NEXT: movaps %xmm3, %xmm5 ; SSE-64-NEXT: movaps %xmm3, %xmm5
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm3[1] ; SSE-64-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm3[3,3]
; SSE-64-NEXT: movaps %xmm2, %xmm6 ; SSE-64-NEXT: movaps %xmm2, %xmm6
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1] ; SSE-64-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm2[3,3]
; SSE-64-NEXT: ucomiss %xmm5, %xmm6 ; SSE-64-NEXT: ucomiss %xmm5, %xmm6
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovbel %ecx, %edx ; SSE-64-NEXT: cmovbel %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm5 ; SSE-64-NEXT: movd %edx, %xmm5
; SSE-64-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; SSE-64-NEXT: ucomiss %xmm3, %xmm2 ; SSE-64-NEXT: ucomiss %xmm3, %xmm2
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovbel %ecx, %edx ; SSE-64-NEXT: cmovbel %ecx, %edx
; SSE-64-NEXT: movd %edx, %xmm4 ; SSE-64-NEXT: movd %edx, %xmm5
; SSE-64-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1] ; SSE-64-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1,1,1]
; SSE-64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; SSE-64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; SSE-64-NEXT: ucomiss %xmm3, %xmm2 ; SSE-64-NEXT: ucomiss %xmm3, %xmm2
; SSE-64-NEXT: cmovbel %ecx, %eax ; SSE-64-NEXT: cmovbel %ecx, %eax
; SSE-64-NEXT: movd %eax, %xmm2 ; SSE-64-NEXT: movd %eax, %xmm2
; SSE-64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE-64-NEXT: pand %xmm4, %xmm0 ; SSE-64-NEXT: pand %xmm5, %xmm0
; SSE-64-NEXT: pandn %xmm1, %xmm4 ; SSE-64-NEXT: pandn %xmm1, %xmm5
; SSE-64-NEXT: por %xmm4, %xmm0 ; SSE-64-NEXT: por %xmm5, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v4f32_ule_q: ; AVX-32-LABEL: test_v4f32_ule_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 344 Lines • ▼ Show 20 Lines
define <2 x i64> @test_v2f64_ogt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 { define <2 x i64> @test_v2f64_ogt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
; SSE-32-LABEL: test_v2f64_ogt_q: ; SSE-32-LABEL: test_v2f64_ogt_q:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movapd 8(%ebp), %xmm4 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSE-32-NEXT: movhlps {{.*#+}} xmm5 = xmm2[1],xmm5[1]
; SSE-32-NEXT: xorl %eax, %eax ; SSE-32-NEXT: xorl %eax, %eax
; SSE-32-NEXT: ucomisd %xmm4, %xmm2 ; SSE-32-NEXT: ucomisd %xmm4, %xmm5
; SSE-32-NEXT: movl $-1, %ecx ; SSE-32-NEXT: movl $-1, %ecx
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmoval %ecx, %edx ; SSE-32-NEXT: cmoval %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm3 ; SSE-32-NEXT: movd %edx, %xmm4
; SSE-32-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,0,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,1,1]
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1] ; SSE-32-NEXT: ucomisd %xmm3, %xmm2
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; SSE-32-NEXT: ucomisd %xmm4, %xmm2
; SSE-32-NEXT: cmoval %ecx, %eax ; SSE-32-NEXT: cmoval %ecx, %eax
; SSE-32-NEXT: movd %eax, %xmm2 ; SSE-32-NEXT: movd %eax, %xmm2
; SSE-32-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1]
; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-32-NEXT: pand %xmm3, %xmm0 ; SSE-32-NEXT: pand %xmm2, %xmm0
; SSE-32-NEXT: pandn %xmm1, %xmm3 ; SSE-32-NEXT: pandn %xmm1, %xmm2
; SSE-32-NEXT: por %xmm3, %xmm0 ; SSE-32-NEXT: por %xmm2, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v2f64_ogt_q: ; SSE-64-LABEL: test_v2f64_ogt_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSE-64-NEXT: movhlps {{.*#+}} xmm5 = xmm2[1],xmm5[1]
; SSE-64-NEXT: xorl %eax, %eax ; SSE-64-NEXT: xorl %eax, %eax
; SSE-64-NEXT: ucomisd %xmm3, %xmm2 ; SSE-64-NEXT: ucomisd %xmm4, %xmm5
; SSE-64-NEXT: movq $-1, %rcx ; SSE-64-NEXT: movq $-1, %rcx
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovaq %rcx, %rdx ; SSE-64-NEXT: cmovaq %rcx, %rdx
; SSE-64-NEXT: movq %rdx, %xmm4 ; SSE-64-NEXT: movq %rdx, %xmm4
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; SSE-64-NEXT: ucomisd %xmm3, %xmm2 ; SSE-64-NEXT: ucomisd %xmm3, %xmm2
; SSE-64-NEXT: cmovaq %rcx, %rax ; SSE-64-NEXT: cmovaq %rcx, %rax
; SSE-64-NEXT: movq %rax, %xmm2 ; SSE-64-NEXT: movq %rax, %xmm2
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm2[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-64-NEXT: pand %xmm4, %xmm0 ; SSE-64-NEXT: pand %xmm2, %xmm0
; SSE-64-NEXT: pandn %xmm1, %xmm4 ; SSE-64-NEXT: pandn %xmm1, %xmm2
; SSE-64-NEXT: por %xmm4, %xmm0 ; SSE-64-NEXT: por %xmm2, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v2f64_ogt_q: ; AVX-32-LABEL: test_v2f64_ogt_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
define <2 x i64> @test_v2f64_oge_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 { define <2 x i64> @test_v2f64_oge_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
; SSE-32-LABEL: test_v2f64_oge_q: ; SSE-32-LABEL: test_v2f64_oge_q:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movapd 8(%ebp), %xmm4 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSE-32-NEXT: movhlps {{.*#+}} xmm5 = xmm2[1],xmm5[1]
; SSE-32-NEXT: xorl %eax, %eax ; SSE-32-NEXT: xorl %eax, %eax
; SSE-32-NEXT: ucomisd %xmm4, %xmm2 ; SSE-32-NEXT: ucomisd %xmm4, %xmm5
; SSE-32-NEXT: movl $-1, %ecx ; SSE-32-NEXT: movl $-1, %ecx
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovael %ecx, %edx ; SSE-32-NEXT: cmovael %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm3 ; SSE-32-NEXT: movd %edx, %xmm4
; SSE-32-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,0,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,1,1]
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1] ; SSE-32-NEXT: ucomisd %xmm3, %xmm2
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; SSE-32-NEXT: ucomisd %xmm4, %xmm2
; SSE-32-NEXT: cmovael %ecx, %eax ; SSE-32-NEXT: cmovael %ecx, %eax
; SSE-32-NEXT: movd %eax, %xmm2 ; SSE-32-NEXT: movd %eax, %xmm2
; SSE-32-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1]
; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-32-NEXT: pand %xmm3, %xmm0 ; SSE-32-NEXT: pand %xmm2, %xmm0
; SSE-32-NEXT: pandn %xmm1, %xmm3 ; SSE-32-NEXT: pandn %xmm1, %xmm2
; SSE-32-NEXT: por %xmm3, %xmm0 ; SSE-32-NEXT: por %xmm2, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v2f64_oge_q: ; SSE-64-LABEL: test_v2f64_oge_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSE-64-NEXT: movhlps {{.*#+}} xmm5 = xmm2[1],xmm5[1]
; SSE-64-NEXT: xorl %eax, %eax ; SSE-64-NEXT: xorl %eax, %eax
; SSE-64-NEXT: ucomisd %xmm3, %xmm2 ; SSE-64-NEXT: ucomisd %xmm4, %xmm5
; SSE-64-NEXT: movq $-1, %rcx ; SSE-64-NEXT: movq $-1, %rcx
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovaeq %rcx, %rdx ; SSE-64-NEXT: cmovaeq %rcx, %rdx
; SSE-64-NEXT: movq %rdx, %xmm4 ; SSE-64-NEXT: movq %rdx, %xmm4
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; SSE-64-NEXT: ucomisd %xmm3, %xmm2 ; SSE-64-NEXT: ucomisd %xmm3, %xmm2
; SSE-64-NEXT: cmovaeq %rcx, %rax ; SSE-64-NEXT: cmovaeq %rcx, %rax
; SSE-64-NEXT: movq %rax, %xmm2 ; SSE-64-NEXT: movq %rax, %xmm2
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm2[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-64-NEXT: pand %xmm4, %xmm0 ; SSE-64-NEXT: pand %xmm2, %xmm0
; SSE-64-NEXT: pandn %xmm1, %xmm4 ; SSE-64-NEXT: pandn %xmm1, %xmm2
; SSE-64-NEXT: por %xmm4, %xmm0 ; SSE-64-NEXT: por %xmm2, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v2f64_oge_q: ; AVX-32-LABEL: test_v2f64_oge_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
define <2 x i64> @test_v2f64_olt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 { define <2 x i64> @test_v2f64_olt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
; SSE-32-LABEL: test_v2f64_olt_q: ; SSE-32-LABEL: test_v2f64_olt_q:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movapd 8(%ebp), %xmm4 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSE-32-NEXT: movhlps {{.*#+}} xmm5 = xmm3[1],xmm5[1]
; SSE-32-NEXT: xorl %eax, %eax ; SSE-32-NEXT: xorl %eax, %eax
; SSE-32-NEXT: ucomisd %xmm2, %xmm4 ; SSE-32-NEXT: ucomisd %xmm4, %xmm5
; SSE-32-NEXT: movl $-1, %ecx ; SSE-32-NEXT: movl $-1, %ecx
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmoval %ecx, %edx ; SSE-32-NEXT: cmoval %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm3 ; SSE-32-NEXT: movd %edx, %xmm4
; SSE-32-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,0,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,1,1]
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-32-NEXT: ucomisd %xmm2, %xmm3
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1]
; SSE-32-NEXT: ucomisd %xmm2, %xmm4
; SSE-32-NEXT: cmoval %ecx, %eax ; SSE-32-NEXT: cmoval %ecx, %eax
; SSE-32-NEXT: movd %eax, %xmm2 ; SSE-32-NEXT: movd %eax, %xmm2
; SSE-32-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1]
; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-32-NEXT: pand %xmm3, %xmm0 ; SSE-32-NEXT: pand %xmm2, %xmm0
; SSE-32-NEXT: pandn %xmm1, %xmm3 ; SSE-32-NEXT: pandn %xmm1, %xmm2
; SSE-32-NEXT: por %xmm3, %xmm0 ; SSE-32-NEXT: por %xmm2, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v2f64_olt_q: ; SSE-64-LABEL: test_v2f64_olt_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSE-64-NEXT: movhlps {{.*#+}} xmm5 = xmm3[1],xmm5[1]
; SSE-64-NEXT: xorl %eax, %eax ; SSE-64-NEXT: xorl %eax, %eax
; SSE-64-NEXT: ucomisd %xmm2, %xmm3 ; SSE-64-NEXT: ucomisd %xmm4, %xmm5
; SSE-64-NEXT: movq $-1, %rcx ; SSE-64-NEXT: movq $-1, %rcx
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovaq %rcx, %rdx ; SSE-64-NEXT: cmovaq %rcx, %rdx
; SSE-64-NEXT: movq %rdx, %xmm4 ; SSE-64-NEXT: movq %rdx, %xmm4
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-64-NEXT: ucomisd %xmm2, %xmm3 ; SSE-64-NEXT: ucomisd %xmm2, %xmm3
; SSE-64-NEXT: cmovaq %rcx, %rax ; SSE-64-NEXT: cmovaq %rcx, %rax
; SSE-64-NEXT: movq %rax, %xmm2 ; SSE-64-NEXT: movq %rax, %xmm2
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm2[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-64-NEXT: pand %xmm4, %xmm0 ; SSE-64-NEXT: pand %xmm2, %xmm0
; SSE-64-NEXT: pandn %xmm1, %xmm4 ; SSE-64-NEXT: pandn %xmm1, %xmm2
; SSE-64-NEXT: por %xmm4, %xmm0 ; SSE-64-NEXT: por %xmm2, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v2f64_olt_q: ; AVX-32-LABEL: test_v2f64_olt_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
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define <2 x i64> @test_v2f64_ole_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 { define <2 x i64> @test_v2f64_ole_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
; SSE-32-LABEL: test_v2f64_ole_q: ; SSE-32-LABEL: test_v2f64_ole_q:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movapd 8(%ebp), %xmm4 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSE-32-NEXT: movhlps {{.*#+}} xmm5 = xmm3[1],xmm5[1]
; SSE-32-NEXT: xorl %eax, %eax ; SSE-32-NEXT: xorl %eax, %eax
; SSE-32-NEXT: ucomisd %xmm2, %xmm4 ; SSE-32-NEXT: ucomisd %xmm4, %xmm5
; SSE-32-NEXT: movl $-1, %ecx ; SSE-32-NEXT: movl $-1, %ecx
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovael %ecx, %edx ; SSE-32-NEXT: cmovael %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm3 ; SSE-32-NEXT: movd %edx, %xmm4
; SSE-32-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,0,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,1,1]
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-32-NEXT: ucomisd %xmm2, %xmm3
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1]
; SSE-32-NEXT: ucomisd %xmm2, %xmm4
; SSE-32-NEXT: cmovael %ecx, %eax ; SSE-32-NEXT: cmovael %ecx, %eax
; SSE-32-NEXT: movd %eax, %xmm2 ; SSE-32-NEXT: movd %eax, %xmm2
; SSE-32-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1]
; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-32-NEXT: pand %xmm3, %xmm0 ; SSE-32-NEXT: pand %xmm2, %xmm0
; SSE-32-NEXT: pandn %xmm1, %xmm3 ; SSE-32-NEXT: pandn %xmm1, %xmm2
; SSE-32-NEXT: por %xmm3, %xmm0 ; SSE-32-NEXT: por %xmm2, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v2f64_ole_q: ; SSE-64-LABEL: test_v2f64_ole_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSE-64-NEXT: movhlps {{.*#+}} xmm5 = xmm3[1],xmm5[1]
; SSE-64-NEXT: xorl %eax, %eax ; SSE-64-NEXT: xorl %eax, %eax
; SSE-64-NEXT: ucomisd %xmm2, %xmm3 ; SSE-64-NEXT: ucomisd %xmm4, %xmm5
; SSE-64-NEXT: movq $-1, %rcx ; SSE-64-NEXT: movq $-1, %rcx
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovaeq %rcx, %rdx ; SSE-64-NEXT: cmovaeq %rcx, %rdx
; SSE-64-NEXT: movq %rdx, %xmm4 ; SSE-64-NEXT: movq %rdx, %xmm4
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-64-NEXT: ucomisd %xmm2, %xmm3 ; SSE-64-NEXT: ucomisd %xmm2, %xmm3
; SSE-64-NEXT: cmovaeq %rcx, %rax ; SSE-64-NEXT: cmovaeq %rcx, %rax
; SSE-64-NEXT: movq %rax, %xmm2 ; SSE-64-NEXT: movq %rax, %xmm2
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm2[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-64-NEXT: pand %xmm4, %xmm0 ; SSE-64-NEXT: pand %xmm2, %xmm0
; SSE-64-NEXT: pandn %xmm1, %xmm4 ; SSE-64-NEXT: pandn %xmm1, %xmm2
; SSE-64-NEXT: por %xmm4, %xmm0 ; SSE-64-NEXT: por %xmm2, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v2f64_ole_q: ; AVX-32-LABEL: test_v2f64_ole_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 356 Lines • ▼ Show 20 Lines
define <2 x i64> @test_v2f64_ugt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 { define <2 x i64> @test_v2f64_ugt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
; SSE-32-LABEL: test_v2f64_ugt_q: ; SSE-32-LABEL: test_v2f64_ugt_q:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movapd 8(%ebp), %xmm4 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSE-32-NEXT: movhlps {{.*#+}} xmm5 = xmm3[1],xmm5[1]
; SSE-32-NEXT: xorl %eax, %eax ; SSE-32-NEXT: xorl %eax, %eax
; SSE-32-NEXT: ucomisd %xmm2, %xmm4 ; SSE-32-NEXT: ucomisd %xmm4, %xmm5
; SSE-32-NEXT: movl $-1, %ecx ; SSE-32-NEXT: movl $-1, %ecx
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovbl %ecx, %edx ; SSE-32-NEXT: cmovbl %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm3 ; SSE-32-NEXT: movd %edx, %xmm4
; SSE-32-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,0,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,1,1]
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-32-NEXT: ucomisd %xmm2, %xmm3
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1]
; SSE-32-NEXT: ucomisd %xmm2, %xmm4
; SSE-32-NEXT: cmovbl %ecx, %eax ; SSE-32-NEXT: cmovbl %ecx, %eax
; SSE-32-NEXT: movd %eax, %xmm2 ; SSE-32-NEXT: movd %eax, %xmm2
; SSE-32-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1]
; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-32-NEXT: pand %xmm3, %xmm0 ; SSE-32-NEXT: pand %xmm2, %xmm0
; SSE-32-NEXT: pandn %xmm1, %xmm3 ; SSE-32-NEXT: pandn %xmm1, %xmm2
; SSE-32-NEXT: por %xmm3, %xmm0 ; SSE-32-NEXT: por %xmm2, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v2f64_ugt_q: ; SSE-64-LABEL: test_v2f64_ugt_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSE-64-NEXT: movhlps {{.*#+}} xmm5 = xmm3[1],xmm5[1]
; SSE-64-NEXT: xorl %eax, %eax ; SSE-64-NEXT: xorl %eax, %eax
; SSE-64-NEXT: ucomisd %xmm2, %xmm3 ; SSE-64-NEXT: ucomisd %xmm4, %xmm5
; SSE-64-NEXT: movq $-1, %rcx ; SSE-64-NEXT: movq $-1, %rcx
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovbq %rcx, %rdx ; SSE-64-NEXT: cmovbq %rcx, %rdx
; SSE-64-NEXT: movq %rdx, %xmm4 ; SSE-64-NEXT: movq %rdx, %xmm4
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-64-NEXT: ucomisd %xmm2, %xmm3 ; SSE-64-NEXT: ucomisd %xmm2, %xmm3
; SSE-64-NEXT: cmovbq %rcx, %rax ; SSE-64-NEXT: cmovbq %rcx, %rax
; SSE-64-NEXT: movq %rax, %xmm2 ; SSE-64-NEXT: movq %rax, %xmm2
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm2[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-64-NEXT: pand %xmm4, %xmm0 ; SSE-64-NEXT: pand %xmm2, %xmm0
; SSE-64-NEXT: pandn %xmm1, %xmm4 ; SSE-64-NEXT: pandn %xmm1, %xmm2
; SSE-64-NEXT: por %xmm4, %xmm0 ; SSE-64-NEXT: por %xmm2, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v2f64_ugt_q: ; AVX-32-LABEL: test_v2f64_ugt_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
define <2 x i64> @test_v2f64_uge_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 { define <2 x i64> @test_v2f64_uge_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
; SSE-32-LABEL: test_v2f64_uge_q: ; SSE-32-LABEL: test_v2f64_uge_q:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movapd 8(%ebp), %xmm4 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSE-32-NEXT: movhlps {{.*#+}} xmm5 = xmm3[1],xmm5[1]
; SSE-32-NEXT: xorl %eax, %eax ; SSE-32-NEXT: xorl %eax, %eax
; SSE-32-NEXT: ucomisd %xmm2, %xmm4 ; SSE-32-NEXT: ucomisd %xmm4, %xmm5
; SSE-32-NEXT: movl $-1, %ecx ; SSE-32-NEXT: movl $-1, %ecx
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovbel %ecx, %edx ; SSE-32-NEXT: cmovbel %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm3 ; SSE-32-NEXT: movd %edx, %xmm4
; SSE-32-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,0,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,1,1]
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-32-NEXT: ucomisd %xmm2, %xmm3
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1]
; SSE-32-NEXT: ucomisd %xmm2, %xmm4
; SSE-32-NEXT: cmovbel %ecx, %eax ; SSE-32-NEXT: cmovbel %ecx, %eax
; SSE-32-NEXT: movd %eax, %xmm2 ; SSE-32-NEXT: movd %eax, %xmm2
; SSE-32-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1]
; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-32-NEXT: pand %xmm3, %xmm0 ; SSE-32-NEXT: pand %xmm2, %xmm0
; SSE-32-NEXT: pandn %xmm1, %xmm3 ; SSE-32-NEXT: pandn %xmm1, %xmm2
; SSE-32-NEXT: por %xmm3, %xmm0 ; SSE-32-NEXT: por %xmm2, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v2f64_uge_q: ; SSE-64-LABEL: test_v2f64_uge_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movhlps {{.*#+}} xmm4 = xmm2[1],xmm4[1]
; SSE-64-NEXT: movhlps {{.*#+}} xmm5 = xmm3[1],xmm5[1]
; SSE-64-NEXT: xorl %eax, %eax ; SSE-64-NEXT: xorl %eax, %eax
; SSE-64-NEXT: ucomisd %xmm2, %xmm3 ; SSE-64-NEXT: ucomisd %xmm4, %xmm5
; SSE-64-NEXT: movq $-1, %rcx ; SSE-64-NEXT: movq $-1, %rcx
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovbeq %rcx, %rdx ; SSE-64-NEXT: cmovbeq %rcx, %rdx
; SSE-64-NEXT: movq %rdx, %xmm4 ; SSE-64-NEXT: movq %rdx, %xmm4
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-64-NEXT: ucomisd %xmm2, %xmm3 ; SSE-64-NEXT: ucomisd %xmm2, %xmm3
; SSE-64-NEXT: cmovbeq %rcx, %rax ; SSE-64-NEXT: cmovbeq %rcx, %rax
; SSE-64-NEXT: movq %rax, %xmm2 ; SSE-64-NEXT: movq %rax, %xmm2
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm2[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-64-NEXT: pand %xmm4, %xmm0 ; SSE-64-NEXT: pand %xmm2, %xmm0
; SSE-64-NEXT: pandn %xmm1, %xmm4 ; SSE-64-NEXT: pandn %xmm1, %xmm2
; SSE-64-NEXT: por %xmm4, %xmm0 ; SSE-64-NEXT: por %xmm2, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v2f64_uge_q: ; AVX-32-LABEL: test_v2f64_uge_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
define <2 x i64> @test_v2f64_ult_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 { define <2 x i64> @test_v2f64_ult_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
; SSE-32-LABEL: test_v2f64_ult_q: ; SSE-32-LABEL: test_v2f64_ult_q:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movapd 8(%ebp), %xmm4 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSE-32-NEXT: movhlps {{.*#+}} xmm5 = xmm2[1],xmm5[1]
; SSE-32-NEXT: xorl %eax, %eax ; SSE-32-NEXT: xorl %eax, %eax
; SSE-32-NEXT: ucomisd %xmm4, %xmm2 ; SSE-32-NEXT: ucomisd %xmm4, %xmm5
; SSE-32-NEXT: movl $-1, %ecx ; SSE-32-NEXT: movl $-1, %ecx
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovbl %ecx, %edx ; SSE-32-NEXT: cmovbl %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm3 ; SSE-32-NEXT: movd %edx, %xmm4
; SSE-32-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,0,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,1,1]
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1] ; SSE-32-NEXT: ucomisd %xmm3, %xmm2
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; SSE-32-NEXT: ucomisd %xmm4, %xmm2
; SSE-32-NEXT: cmovbl %ecx, %eax ; SSE-32-NEXT: cmovbl %ecx, %eax
; SSE-32-NEXT: movd %eax, %xmm2 ; SSE-32-NEXT: movd %eax, %xmm2
; SSE-32-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1]
; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-32-NEXT: pand %xmm3, %xmm0 ; SSE-32-NEXT: pand %xmm2, %xmm0
; SSE-32-NEXT: pandn %xmm1, %xmm3 ; SSE-32-NEXT: pandn %xmm1, %xmm2
; SSE-32-NEXT: por %xmm3, %xmm0 ; SSE-32-NEXT: por %xmm2, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v2f64_ult_q: ; SSE-64-LABEL: test_v2f64_ult_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSE-64-NEXT: movhlps {{.*#+}} xmm5 = xmm2[1],xmm5[1]
; SSE-64-NEXT: xorl %eax, %eax ; SSE-64-NEXT: xorl %eax, %eax
; SSE-64-NEXT: ucomisd %xmm3, %xmm2 ; SSE-64-NEXT: ucomisd %xmm4, %xmm5
; SSE-64-NEXT: movq $-1, %rcx ; SSE-64-NEXT: movq $-1, %rcx
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovbq %rcx, %rdx ; SSE-64-NEXT: cmovbq %rcx, %rdx
; SSE-64-NEXT: movq %rdx, %xmm4 ; SSE-64-NEXT: movq %rdx, %xmm4
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; SSE-64-NEXT: ucomisd %xmm3, %xmm2 ; SSE-64-NEXT: ucomisd %xmm3, %xmm2
; SSE-64-NEXT: cmovbq %rcx, %rax ; SSE-64-NEXT: cmovbq %rcx, %rax
; SSE-64-NEXT: movq %rax, %xmm2 ; SSE-64-NEXT: movq %rax, %xmm2
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm2[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-64-NEXT: pand %xmm4, %xmm0 ; SSE-64-NEXT: pand %xmm2, %xmm0
; SSE-64-NEXT: pandn %xmm1, %xmm4 ; SSE-64-NEXT: pandn %xmm1, %xmm2
; SSE-64-NEXT: por %xmm4, %xmm0 ; SSE-64-NEXT: por %xmm2, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v2f64_ult_q: ; AVX-32-LABEL: test_v2f64_ult_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
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define <2 x i64> @test_v2f64_ule_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 { define <2 x i64> @test_v2f64_ule_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
; SSE-32-LABEL: test_v2f64_ule_q: ; SSE-32-LABEL: test_v2f64_ule_q:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movapd 8(%ebp), %xmm4 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSE-32-NEXT: movhlps {{.*#+}} xmm5 = xmm2[1],xmm5[1]
; SSE-32-NEXT: xorl %eax, %eax ; SSE-32-NEXT: xorl %eax, %eax
; SSE-32-NEXT: ucomisd %xmm4, %xmm2 ; SSE-32-NEXT: ucomisd %xmm4, %xmm5
; SSE-32-NEXT: movl $-1, %ecx ; SSE-32-NEXT: movl $-1, %ecx
; SSE-32-NEXT: movl $0, %edx ; SSE-32-NEXT: movl $0, %edx
; SSE-32-NEXT: cmovbel %ecx, %edx ; SSE-32-NEXT: cmovbel %ecx, %edx
; SSE-32-NEXT: movd %edx, %xmm3 ; SSE-32-NEXT: movd %edx, %xmm4
; SSE-32-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,0,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,1,1]
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1] ; SSE-32-NEXT: ucomisd %xmm3, %xmm2
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; SSE-32-NEXT: ucomisd %xmm4, %xmm2
; SSE-32-NEXT: cmovbel %ecx, %eax ; SSE-32-NEXT: cmovbel %ecx, %eax
; SSE-32-NEXT: movd %eax, %xmm2 ; SSE-32-NEXT: movd %eax, %xmm2
; SSE-32-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1]
; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-32-NEXT: pand %xmm3, %xmm0 ; SSE-32-NEXT: pand %xmm2, %xmm0
; SSE-32-NEXT: pandn %xmm1, %xmm3 ; SSE-32-NEXT: pandn %xmm1, %xmm2
; SSE-32-NEXT: por %xmm3, %xmm0 ; SSE-32-NEXT: por %xmm2, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v2f64_ule_q: ; SSE-64-LABEL: test_v2f64_ule_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movhlps {{.*#+}} xmm4 = xmm3[1],xmm4[1]
; SSE-64-NEXT: movhlps {{.*#+}} xmm5 = xmm2[1],xmm5[1]
; SSE-64-NEXT: xorl %eax, %eax ; SSE-64-NEXT: xorl %eax, %eax
; SSE-64-NEXT: ucomisd %xmm3, %xmm2 ; SSE-64-NEXT: ucomisd %xmm4, %xmm5
; SSE-64-NEXT: movq $-1, %rcx ; SSE-64-NEXT: movq $-1, %rcx
; SSE-64-NEXT: movl $0, %edx ; SSE-64-NEXT: movl $0, %edx
; SSE-64-NEXT: cmovbeq %rcx, %rdx ; SSE-64-NEXT: cmovbeq %rcx, %rdx
; SSE-64-NEXT: movq %rdx, %xmm4 ; SSE-64-NEXT: movq %rdx, %xmm4
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; SSE-64-NEXT: ucomisd %xmm3, %xmm2 ; SSE-64-NEXT: ucomisd %xmm3, %xmm2
; SSE-64-NEXT: cmovbeq %rcx, %rax ; SSE-64-NEXT: cmovbeq %rcx, %rax
; SSE-64-NEXT: movq %rax, %xmm2 ; SSE-64-NEXT: movq %rax, %xmm2
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm2[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-64-NEXT: pand %xmm4, %xmm0 ; SSE-64-NEXT: pand %xmm2, %xmm0
; SSE-64-NEXT: pandn %xmm1, %xmm4 ; SSE-64-NEXT: pandn %xmm1, %xmm2
; SSE-64-NEXT: por %xmm4, %xmm0 ; SSE-64-NEXT: por %xmm2, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v2f64_ule_q: ; AVX-32-LABEL: test_v2f64_ule_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
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llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll

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; SSE-32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE-32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: .cfi_def_cfa %esp, 4 ; SSE-32-NEXT: .cfi_def_cfa %esp, 4
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: strict_vector_fptosi_v2f64_to_v2i64: ; SSE-64-LABEL: strict_vector_fptosi_v2f64_to_v2i64:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: cvttsd2si %xmm0, %rax ; SSE-64-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-64-NEXT: cvttsd2si %xmm1, %rax
; SSE-64-NEXT: movq %rax, %xmm1 ; SSE-64-NEXT: movq %rax, %xmm1
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; SSE-64-NEXT: cvttsd2si %xmm0, %rax ; SSE-64-NEXT: cvttsd2si %xmm0, %rax
; SSE-64-NEXT: movq %rax, %xmm0 ; SSE-64-NEXT: movq %rax, %xmm0
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-64-NEXT: movdqa %xmm1, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: strict_vector_fptosi_v2f64_to_v2i64: ; AVX-32-LABEL: strict_vector_fptosi_v2f64_to_v2i64:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: .cfi_def_cfa_offset 8 ; AVX-32-NEXT: .cfi_def_cfa_offset 8
; AVX-32-NEXT: .cfi_offset %ebp, -8 ; AVX-32-NEXT: .cfi_offset %ebp, -8
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
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; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: .cfi_def_cfa %esp, 4 ; SSE-32-NEXT: .cfi_def_cfa %esp, 4
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: strict_vector_fptoui_v2f64_to_v2i64: ; SSE-64-LABEL: strict_vector_fptoui_v2f64_to_v2i64:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movapd %xmm0, %xmm1
; SSE-64-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero ; SSE-64-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
; SSE-64-NEXT: comisd %xmm3, %xmm0 ; SSE-64-NEXT: comisd %xmm3, %xmm0
; SSE-64-NEXT: xorpd %xmm2, %xmm2 ; SSE-64-NEXT: xorpd %xmm2, %xmm2
; SSE-64-NEXT: xorpd %xmm1, %xmm1 ; SSE-64-NEXT: xorpd %xmm0, %xmm0
; SSE-64-NEXT: jb .LBB1_2 ; SSE-64-NEXT: jb .LBB1_2
; SSE-64-NEXT: # %bb.1: ; SSE-64-NEXT: # %bb.1:
; SSE-64-NEXT: movapd %xmm3, %xmm1 ; SSE-64-NEXT: movapd %xmm3, %xmm0
; SSE-64-NEXT: .LBB1_2: ; SSE-64-NEXT: .LBB1_2:
; SSE-64-NEXT: movapd %xmm0, %xmm4 ; SSE-64-NEXT: movapd %xmm1, %xmm4
; SSE-64-NEXT: subsd %xmm1, %xmm4 ; SSE-64-NEXT: subsd %xmm0, %xmm4
; SSE-64-NEXT: cvttsd2si %xmm4, %rax ; SSE-64-NEXT: cvttsd2si %xmm4, %rax
; SSE-64-NEXT: setae %cl ; SSE-64-NEXT: setae %cl
; SSE-64-NEXT: movzbl %cl, %ecx ; SSE-64-NEXT: movzbl %cl, %ecx
; SSE-64-NEXT: shlq $63, %rcx ; SSE-64-NEXT: shlq $63, %rcx
; SSE-64-NEXT: xorq %rax, %rcx ; SSE-64-NEXT: xorq %rax, %rcx
; SSE-64-NEXT: movq %rcx, %xmm1 ; SSE-64-NEXT: movq %rcx, %xmm0
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1] ; SSE-64-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-64-NEXT: comisd %xmm3, %xmm0 ; SSE-64-NEXT: comisd %xmm3, %xmm1
; SSE-64-NEXT: jb .LBB1_4 ; SSE-64-NEXT: jb .LBB1_4
; SSE-64-NEXT: # %bb.3: ; SSE-64-NEXT: # %bb.3:
; SSE-64-NEXT: movapd %xmm3, %xmm2 ; SSE-64-NEXT: movapd %xmm3, %xmm2
; SSE-64-NEXT: .LBB1_4: ; SSE-64-NEXT: .LBB1_4:
; SSE-64-NEXT: subsd %xmm2, %xmm0 ; SSE-64-NEXT: subsd %xmm2, %xmm1
; SSE-64-NEXT: cvttsd2si %xmm0, %rax ; SSE-64-NEXT: cvttsd2si %xmm1, %rax
; SSE-64-NEXT: setae %cl ; SSE-64-NEXT: setae %cl
; SSE-64-NEXT: movzbl %cl, %ecx ; SSE-64-NEXT: movzbl %cl, %ecx
; SSE-64-NEXT: shlq $63, %rcx ; SSE-64-NEXT: shlq $63, %rcx
; SSE-64-NEXT: xorq %rax, %rcx ; SSE-64-NEXT: xorq %rax, %rcx
; SSE-64-NEXT: movq %rcx, %xmm0 ; SSE-64-NEXT: movq %rcx, %xmm1
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-64-NEXT: movdqa %xmm1, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: strict_vector_fptoui_v2f64_to_v2i64: ; AVX-32-LABEL: strict_vector_fptoui_v2f64_to_v2i64:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: .cfi_def_cfa_offset 8 ; AVX-32-NEXT: .cfi_def_cfa_offset 8
; AVX-32-NEXT: .cfi_offset %ebp, -8 ; AVX-32-NEXT: .cfi_offset %ebp, -8
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
▲ Show 20 Lines • Show All 1,234 Lines • ▼ Show 20 Lines; AVX512VLDQ-NEXT: ret{{[l|q]}}
%ret = call <2 x i32> @llvm.experimental.constrained.fptosi.v2i32.v2f64(<2 x double> %a, %ret = call <2 x i32> @llvm.experimental.constrained.fptosi.v2i32.v2f64(<2 x double> %a,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <2 x i32> %ret ret <2 x i32> %ret
} }
define <2 x i32> @strict_vector_fptoui_v2f64_to_v2i32(<2 x double> %a) #0 { define <2 x i32> @strict_vector_fptoui_v2f64_to_v2i32(<2 x double> %a) #0 {
; SSE-32-LABEL: strict_vector_fptoui_v2f64_to_v2i32: ; SSE-32-LABEL: strict_vector_fptoui_v2f64_to_v2i32:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: movapd %xmm0, %xmm1
; SSE-32-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero ; SSE-32-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
; SSE-32-NEXT: comisd %xmm3, %xmm0 ; SSE-32-NEXT: comisd %xmm3, %xmm0
; SSE-32-NEXT: xorpd %xmm2, %xmm2 ; SSE-32-NEXT: xorpd %xmm2, %xmm2
; SSE-32-NEXT: xorpd %xmm1, %xmm1 ; SSE-32-NEXT: xorpd %xmm0, %xmm0
; SSE-32-NEXT: jb .LBB7_2 ; SSE-32-NEXT: jb .LBB7_2
; SSE-32-NEXT: # %bb.1: ; SSE-32-NEXT: # %bb.1:
; SSE-32-NEXT: movapd %xmm3, %xmm1 ; SSE-32-NEXT: movapd %xmm3, %xmm0
; SSE-32-NEXT: .LBB7_2: ; SSE-32-NEXT: .LBB7_2:
; SSE-32-NEXT: setae %al ; SSE-32-NEXT: setae %al
; SSE-32-NEXT: movzbl %al, %eax ; SSE-32-NEXT: movzbl %al, %eax
; SSE-32-NEXT: shll $31, %eax ; SSE-32-NEXT: shll $31, %eax
; SSE-32-NEXT: movapd %xmm0, %xmm4 ; SSE-32-NEXT: movapd %xmm1, %xmm4
; SSE-32-NEXT: subsd %xmm1, %xmm4 ; SSE-32-NEXT: subsd %xmm0, %xmm4
; SSE-32-NEXT: cvttsd2si %xmm4, %ecx ; SSE-32-NEXT: cvttsd2si %xmm4, %ecx
; SSE-32-NEXT: xorl %eax, %ecx ; SSE-32-NEXT: xorl %eax, %ecx
; SSE-32-NEXT: movd %ecx, %xmm1 ; SSE-32-NEXT: movd %ecx, %xmm0
; SSE-32-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1] ; SSE-32-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-32-NEXT: comisd %xmm3, %xmm0 ; SSE-32-NEXT: comisd %xmm3, %xmm1
; SSE-32-NEXT: jb .LBB7_4 ; SSE-32-NEXT: jb .LBB7_4
; SSE-32-NEXT: # %bb.3: ; SSE-32-NEXT: # %bb.3:
; SSE-32-NEXT: movapd %xmm3, %xmm2 ; SSE-32-NEXT: movapd %xmm3, %xmm2
; SSE-32-NEXT: .LBB7_4: ; SSE-32-NEXT: .LBB7_4:
; SSE-32-NEXT: setae %al ; SSE-32-NEXT: subsd %xmm2, %xmm1
; SSE-32-NEXT: movzbl %al, %eax ; SSE-32-NEXT: cvttsd2si %xmm1, %eax
; SSE-32-NEXT: shll $31, %eax ; SSE-32-NEXT: setae %cl
; SSE-32-NEXT: subsd %xmm2, %xmm0 ; SSE-32-NEXT: movzbl %cl, %ecx
; SSE-32-NEXT: cvttsd2si %xmm0, %ecx ; SSE-32-NEXT: shll $31, %ecx
; SSE-32-NEXT: xorl %eax, %ecx ; SSE-32-NEXT: xorl %eax, %ecx
; SSE-32-NEXT: movd %ecx, %xmm0 ; SSE-32-NEXT: movd %ecx, %xmm1
; SSE-32-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-32-NEXT: movdqa %xmm1, %xmm0
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: strict_vector_fptoui_v2f64_to_v2i32: ; SSE-64-LABEL: strict_vector_fptoui_v2f64_to_v2i32:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: cvttsd2si %xmm0, %rax ; SSE-64-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-64-NEXT: cvttsd2si %xmm1, %rax
; SSE-64-NEXT: movd %eax, %xmm1 ; SSE-64-NEXT: movd %eax, %xmm1
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; SSE-64-NEXT: cvttsd2si %xmm0, %rax ; SSE-64-NEXT: cvttsd2si %xmm0, %rax
; SSE-64-NEXT: movd %eax, %xmm0 ; SSE-64-NEXT: movd %eax, %xmm0
; SSE-64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE-64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-64-NEXT: movdqa %xmm1, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: strict_vector_fptoui_v2f64_to_v2i32: ; AVX-32-LABEL: strict_vector_fptoui_v2f64_to_v2i32:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: .cfi_def_cfa_offset 8 ; AVX-32-NEXT: .cfi_def_cfa_offset 8
; AVX-32-NEXT: .cfi_offset %ebp, -8 ; AVX-32-NEXT: .cfi_offset %ebp, -8
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
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; SSE-32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE-32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: .cfi_def_cfa %esp, 4 ; SSE-32-NEXT: .cfi_def_cfa %esp, 4
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: strict_vector_fptosi_v2f64_to_v2i1: ; SSE-64-LABEL: strict_vector_fptosi_v2f64_to_v2i1:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: cvttsd2si %xmm0, %rax ; SSE-64-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-64-NEXT: cvttsd2si %xmm1, %rax
; SSE-64-NEXT: movq %rax, %xmm1 ; SSE-64-NEXT: movq %rax, %xmm1
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; SSE-64-NEXT: cvttsd2si %xmm0, %rax ; SSE-64-NEXT: cvttsd2si %xmm0, %rax
; SSE-64-NEXT: movq %rax, %xmm0 ; SSE-64-NEXT: movq %rax, %xmm0
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-64-NEXT: movdqa %xmm1, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: strict_vector_fptosi_v2f64_to_v2i1: ; AVX-32-LABEL: strict_vector_fptosi_v2f64_to_v2i1:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: .cfi_def_cfa_offset 8 ; AVX-32-NEXT: .cfi_def_cfa_offset 8
; AVX-32-NEXT: .cfi_offset %ebp, -8 ; AVX-32-NEXT: .cfi_offset %ebp, -8
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
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; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: .cfi_def_cfa %esp, 4 ; SSE-32-NEXT: .cfi_def_cfa %esp, 4
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: strict_vector_fptoui_v2f64_to_v2i1: ; SSE-64-LABEL: strict_vector_fptoui_v2f64_to_v2i1:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movapd %xmm0, %xmm1
; SSE-64-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero ; SSE-64-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
; SSE-64-NEXT: comisd %xmm3, %xmm0 ; SSE-64-NEXT: comisd %xmm3, %xmm0
; SSE-64-NEXT: xorpd %xmm2, %xmm2 ; SSE-64-NEXT: xorpd %xmm2, %xmm2
; SSE-64-NEXT: xorpd %xmm1, %xmm1 ; SSE-64-NEXT: xorpd %xmm0, %xmm0
; SSE-64-NEXT: jb .LBB19_2 ; SSE-64-NEXT: jb .LBB19_2
; SSE-64-NEXT: # %bb.1: ; SSE-64-NEXT: # %bb.1:
; SSE-64-NEXT: movapd %xmm3, %xmm1 ; SSE-64-NEXT: movapd %xmm3, %xmm0
; SSE-64-NEXT: .LBB19_2: ; SSE-64-NEXT: .LBB19_2:
; SSE-64-NEXT: movapd %xmm0, %xmm4 ; SSE-64-NEXT: movapd %xmm1, %xmm4
; SSE-64-NEXT: subsd %xmm1, %xmm4 ; SSE-64-NEXT: subsd %xmm0, %xmm4
; SSE-64-NEXT: cvttsd2si %xmm4, %rax ; SSE-64-NEXT: cvttsd2si %xmm4, %rax
; SSE-64-NEXT: setae %cl ; SSE-64-NEXT: setae %cl
; SSE-64-NEXT: movzbl %cl, %ecx ; SSE-64-NEXT: movzbl %cl, %ecx
; SSE-64-NEXT: shlq $63, %rcx ; SSE-64-NEXT: shlq $63, %rcx
; SSE-64-NEXT: xorq %rax, %rcx ; SSE-64-NEXT: xorq %rax, %rcx
; SSE-64-NEXT: movq %rcx, %xmm1 ; SSE-64-NEXT: movq %rcx, %xmm0
; SSE-64-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1] ; SSE-64-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-64-NEXT: comisd %xmm3, %xmm0 ; SSE-64-NEXT: comisd %xmm3, %xmm1
; SSE-64-NEXT: jb .LBB19_4 ; SSE-64-NEXT: jb .LBB19_4
; SSE-64-NEXT: # %bb.3: ; SSE-64-NEXT: # %bb.3:
; SSE-64-NEXT: movapd %xmm3, %xmm2 ; SSE-64-NEXT: movapd %xmm3, %xmm2
; SSE-64-NEXT: .LBB19_4: ; SSE-64-NEXT: .LBB19_4:
; SSE-64-NEXT: subsd %xmm2, %xmm0 ; SSE-64-NEXT: subsd %xmm2, %xmm1
; SSE-64-NEXT: cvttsd2si %xmm0, %rax ; SSE-64-NEXT: cvttsd2si %xmm1, %rax
; SSE-64-NEXT: setae %cl ; SSE-64-NEXT: setae %cl
; SSE-64-NEXT: movzbl %cl, %ecx ; SSE-64-NEXT: movzbl %cl, %ecx
; SSE-64-NEXT: shlq $63, %rcx ; SSE-64-NEXT: shlq $63, %rcx
; SSE-64-NEXT: xorq %rax, %rcx ; SSE-64-NEXT: xorq %rax, %rcx
; SSE-64-NEXT: movq %rcx, %xmm0 ; SSE-64-NEXT: movq %rcx, %xmm1
; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-64-NEXT: movdqa %xmm1, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: strict_vector_fptoui_v2f64_to_v2i1: ; AVX-32-LABEL: strict_vector_fptoui_v2f64_to_v2i1:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: .cfi_def_cfa_offset 8 ; AVX-32-NEXT: .cfi_def_cfa_offset 8
; AVX-32-NEXT: .cfi_offset %ebp, -8 ; AVX-32-NEXT: .cfi_offset %ebp, -8
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
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llvm/test/CodeGen/X86/vec_fp_to_int.ll

Show All 13 Lines
; ;
; Double to Signed Integer ; Double to Signed Integer
; ;
define <2 x i64> @fptosi_2f64_to_2i64(<2 x double> %a) { define <2 x i64> @fptosi_2f64_to_2i64(<2 x double> %a) {
; SSE-LABEL: fptosi_2f64_to_2i64: ; SSE-LABEL: fptosi_2f64_to_2i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: cvttsd2si %xmm0, %rax ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: cvttsd2si %xmm1, %rax
; SSE-NEXT: movq %rax, %xmm1 ; SSE-NEXT: movq %rax, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: cvttsd2si %xmm0, %rax ; SSE-NEXT: cvttsd2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm0 ; SSE-NEXT: movq %rax, %xmm0
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: movdqa %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; VEX-LABEL: fptosi_2f64_to_2i64: ; VEX-LABEL: fptosi_2f64_to_2i64:
; VEX: # %bb.0: ; VEX: # %bb.0:
; VEX-NEXT: vcvttsd2si %xmm0, %rax ; VEX-NEXT: vcvttsd2si %xmm0, %rax
; VEX-NEXT: vmovq %rax, %xmm1 ; VEX-NEXT: vmovq %rax, %xmm1
; VEX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; VEX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; VEX-NEXT: vcvttsd2si %xmm0, %rax ; VEX-NEXT: vcvttsd2si %xmm0, %rax
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%ext = shufflevector <2 x double> %a, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %ext = shufflevector <2 x double> %a, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%cvt = fptosi <4 x double> %ext to <4 x i32> %cvt = fptosi <4 x double> %ext to <4 x i32>
ret <4 x i32> %cvt ret <4 x i32> %cvt
} }
define <4 x i64> @fptosi_4f64_to_4i64(<4 x double> %a) { define <4 x i64> @fptosi_4f64_to_4i64(<4 x double> %a) {
; SSE-LABEL: fptosi_4f64_to_4i64: ; SSE-LABEL: fptosi_4f64_to_4i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: cvttsd2si %xmm0, %rax ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE-NEXT: cvttsd2si %xmm2, %rax
; SSE-NEXT: movq %rax, %xmm2 ; SSE-NEXT: movq %rax, %xmm2
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: cvttsd2si %xmm0, %rax ; SSE-NEXT: cvttsd2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm0 ; SSE-NEXT: movq %rax, %xmm0
; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0] ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE-NEXT: cvttsd2si %xmm1, %rax ; SSE-NEXT: xorps %xmm2, %xmm2
; SSE-NEXT: movq %rax, %xmm3 ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: cvttsd2si %xmm2, %rax
; SSE-NEXT: movq %rax, %xmm2
; SSE-NEXT: cvttsd2si %xmm1, %rax ; SSE-NEXT: cvttsd2si %xmm1, %rax
; SSE-NEXT: movq %rax, %xmm0 ; SSE-NEXT: movq %rax, %xmm1
; SSE-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0] ; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: movdqa %xmm3, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: fptosi_4f64_to_4i64: ; AVX1-LABEL: fptosi_4f64_to_4i64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vcvttsd2si %xmm1, %rax ; AVX1-NEXT: vcvttsd2si %xmm1, %rax
; AVX1-NEXT: vmovq %rax, %xmm2 ; AVX1-NEXT: vmovq %rax, %xmm2
; AVX1-NEXT: vpermilpd {{.*#+}} xmm1 = xmm1[1,0] ; AVX1-NEXT: vpermilpd {{.*#+}} xmm1 = xmm1[1,0]
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; ;
; Double to Unsigned Integer ; Double to Unsigned Integer
; ;
define <2 x i64> @fptoui_2f64_to_2i64(<2 x double> %a) { define <2 x i64> @fptoui_2f64_to_2i64(<2 x double> %a) {
; SSE-LABEL: fptoui_2f64_to_2i64: ; SSE-LABEL: fptoui_2f64_to_2i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: cvttsd2si %xmm1, %rax
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: sarq $63, %rcx
; SSE-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero ; SSE-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; SSE-NEXT: movapd %xmm0, %xmm1
; SSE-NEXT: subsd %xmm2, %xmm1 ; SSE-NEXT: subsd %xmm2, %xmm1
; SSE-NEXT: cvttsd2si %xmm1, %rax ; SSE-NEXT: cvttsd2si %xmm1, %rdx
; SSE-NEXT: cvttsd2si %xmm0, %rcx ; SSE-NEXT: andq %rcx, %rdx
; SSE-NEXT: movq %rcx, %rdx ; SSE-NEXT: orq %rax, %rdx
; SSE-NEXT: sarq $63, %rdx
; SSE-NEXT: andq %rax, %rdx
; SSE-NEXT: orq %rcx, %rdx
; SSE-NEXT: movq %rdx, %xmm1 ; SSE-NEXT: movq %rdx, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: cvttsd2si %xmm0, %rax ; SSE-NEXT: cvttsd2si %xmm0, %rax
; SSE-NEXT: subsd %xmm2, %xmm0 ; SSE-NEXT: subsd %xmm2, %xmm0
; SSE-NEXT: cvttsd2si %xmm0, %rcx ; SSE-NEXT: cvttsd2si %xmm0, %rcx
; SSE-NEXT: movq %rax, %rdx ; SSE-NEXT: movq %rax, %rdx
; SSE-NEXT: sarq $63, %rdx ; SSE-NEXT: sarq $63, %rdx
; SSE-NEXT: andq %rcx, %rdx ; SSE-NEXT: andq %rcx, %rdx
; SSE-NEXT: orq %rax, %rdx ; SSE-NEXT: orq %rax, %rdx
; SSE-NEXT: movq %rdx, %xmm0 ; SSE-NEXT: movq %rdx, %xmm0
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: movdqa %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; VEX-LABEL: fptoui_2f64_to_2i64: ; VEX-LABEL: fptoui_2f64_to_2i64:
; VEX: # %bb.0: ; VEX: # %bb.0:
; VEX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero ; VEX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; VEX-NEXT: vsubsd %xmm1, %xmm0, %xmm2 ; VEX-NEXT: vsubsd %xmm1, %xmm0, %xmm2
; VEX-NEXT: vcvttsd2si %xmm2, %rax ; VEX-NEXT: vcvttsd2si %xmm2, %rax
; VEX-NEXT: vcvttsd2si %xmm0, %rcx ; VEX-NEXT: vcvttsd2si %xmm0, %rcx
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%ext = shufflevector <2 x double> %a, <2 x double> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %ext = shufflevector <2 x double> %a, <2 x double> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = fptoui <4 x double> %ext to <4 x i32> %cvt = fptoui <4 x double> %ext to <4 x i32>
ret <4 x i32> %cvt ret <4 x i32> %cvt
} }
define <4 x i64> @fptoui_4f64_to_4i64(<4 x double> %a) { define <4 x i64> @fptoui_4f64_to_4i64(<4 x double> %a) {
; SSE-LABEL: fptoui_4f64_to_4i64: ; SSE-LABEL: fptoui_4f64_to_4i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm2 ; SSE-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; SSE-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero ; SSE-NEXT: cvttsd2si %xmm3, %rax
; SSE-NEXT: subsd %xmm3, %xmm0 ; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: sarq $63, %rcx
; SSE-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; SSE-NEXT: subsd %xmm2, %xmm3
; SSE-NEXT: cvttsd2si %xmm3, %rdx
; SSE-NEXT: andq %rcx, %rdx
; SSE-NEXT: orq %rax, %rdx
; SSE-NEXT: movq %rdx, %xmm3
; SSE-NEXT: cvttsd2si %xmm0, %rax ; SSE-NEXT: cvttsd2si %xmm0, %rax
; SSE-NEXT: cvttsd2si %xmm2, %rcx ; SSE-NEXT: subsd %xmm2, %xmm0
; SSE-NEXT: movq %rcx, %rdx ; SSE-NEXT: cvttsd2si %xmm0, %rcx
; SSE-NEXT: sarq $63, %rdx
; SSE-NEXT: andq %rax, %rdx
; SSE-NEXT: orq %rcx, %rdx
; SSE-NEXT: movq %rdx, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; SSE-NEXT: cvttsd2si %xmm2, %rax
; SSE-NEXT: subsd %xmm3, %xmm2
; SSE-NEXT: cvttsd2si %xmm2, %rcx
; SSE-NEXT: movq %rax, %rdx ; SSE-NEXT: movq %rax, %rdx
; SSE-NEXT: sarq $63, %rdx ; SSE-NEXT: sarq $63, %rdx
; SSE-NEXT: andq %rcx, %rdx ; SSE-NEXT: andq %rcx, %rdx
; SSE-NEXT: orq %rax, %rdx ; SSE-NEXT: orq %rax, %rdx
; SSE-NEXT: movq %rdx, %xmm2 ; SSE-NEXT: movq %rdx, %xmm0
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; SSE-NEXT: movapd %xmm1, %xmm2 ; SSE-NEXT: xorps %xmm3, %xmm3
; SSE-NEXT: subsd %xmm3, %xmm2 ; SSE-NEXT: movhlps {{.*#+}} xmm3 = xmm1[1],xmm3[1]
; SSE-NEXT: cvttsd2si %xmm2, %rax ; SSE-NEXT: cvttsd2si %xmm3, %rax
; SSE-NEXT: cvttsd2si %xmm1, %rcx ; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: movq %rcx, %rdx ; SSE-NEXT: sarq $63, %rcx
; SSE-NEXT: sarq $63, %rdx ; SSE-NEXT: subsd %xmm2, %xmm3
; SSE-NEXT: andq %rax, %rdx ; SSE-NEXT: cvttsd2si %xmm3, %rdx
; SSE-NEXT: orq %rcx, %rdx ; SSE-NEXT: andq %rcx, %rdx
; SSE-NEXT: movq %rdx, %xmm2 ; SSE-NEXT: orq %rax, %rdx
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: movq %rdx, %xmm3
; SSE-NEXT: cvttsd2si %xmm1, %rax ; SSE-NEXT: cvttsd2si %xmm1, %rax
; SSE-NEXT: subsd %xmm3, %xmm1 ; SSE-NEXT: subsd %xmm2, %xmm1
; SSE-NEXT: cvttsd2si %xmm1, %rcx ; SSE-NEXT: cvttsd2si %xmm1, %rcx
; SSE-NEXT: movq %rax, %rdx ; SSE-NEXT: movq %rax, %rdx
; SSE-NEXT: sarq $63, %rdx ; SSE-NEXT: sarq $63, %rdx
; SSE-NEXT: andq %rcx, %rdx ; SSE-NEXT: andq %rcx, %rdx
; SSE-NEXT: orq %rax, %rdx ; SSE-NEXT: orq %rax, %rdx
; SSE-NEXT: movq %rdx, %xmm1 ; SSE-NEXT: movq %rdx, %xmm1
; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0] ; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
; SSE-NEXT: movdqa %xmm2, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: fptoui_4f64_to_4i64: ; AVX1-LABEL: fptoui_4f64_to_4i64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero ; AVX1-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; AVX1-NEXT: vsubsd %xmm1, %xmm2, %xmm3 ; AVX1-NEXT: vsubsd %xmm1, %xmm2, %xmm3
; AVX1-NEXT: vcvttsd2si %xmm3, %rax ; AVX1-NEXT: vcvttsd2si %xmm3, %rax
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; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: cvttss2si %xmm0, %rax ; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm2 ; SSE-NEXT: movq %rax, %xmm2
; SSE-NEXT: movaps %xmm0, %xmm1 ; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE-NEXT: cvttss2si %xmm1, %rax ; SSE-NEXT: cvttss2si %xmm1, %rax
; SSE-NEXT: movq %rax, %xmm1 ; SSE-NEXT: movq %rax, %xmm1
; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0] ; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; SSE-NEXT: movaps %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: cvttss2si %xmm1, %rax ; SSE-NEXT: cvttss2si %xmm1, %rax
; SSE-NEXT: movq %rax, %xmm3
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm1 ; SSE-NEXT: movq %rax, %xmm1
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm0
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE-NEXT: movdqa %xmm2, %xmm0 ; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: fptosi_4f32_to_4i64: ; AVX1-LABEL: fptosi_4f32_to_4i64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,3,3,3] ; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,3,3,3]
; AVX1-NEXT: vcvttss2si %xmm1, %rax ; AVX1-NEXT: vcvttss2si %xmm1, %rax
; AVX1-NEXT: vmovq %rax, %xmm1 ; AVX1-NEXT: vmovq %rax, %xmm1
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; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: cvttss2si %xmm0, %rax ; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm2 ; SSE-NEXT: movq %rax, %xmm2
; SSE-NEXT: movaps %xmm0, %xmm1 ; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE-NEXT: cvttss2si %xmm1, %rax ; SSE-NEXT: cvttss2si %xmm1, %rax
; SSE-NEXT: movq %rax, %xmm1 ; SSE-NEXT: movq %rax, %xmm1
; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0] ; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; SSE-NEXT: movaps %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: cvttss2si %xmm1, %rax ; SSE-NEXT: cvttss2si %xmm1, %rax
; SSE-NEXT: movq %rax, %xmm3
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm1 ; SSE-NEXT: movq %rax, %xmm1
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm0
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE-NEXT: movdqa %xmm2, %xmm0 ; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: fptosi_8f32_to_4i64: ; AVX1-LABEL: fptosi_8f32_to_4i64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,3,3,3] ; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,3,3,3]
; AVX1-NEXT: vcvttss2si %xmm1, %rax ; AVX1-NEXT: vcvttss2si %xmm1, %rax
; AVX1-NEXT: vmovq %rax, %xmm1 ; AVX1-NEXT: vmovq %rax, %xmm1
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; AVX512VLDQ-NEXT: retq ; AVX512VLDQ-NEXT: retq
%cvt = fptoui <8 x float> %a to <8 x i32> %cvt = fptoui <8 x float> %a to <8 x i32>
ret <8 x i32> %cvt ret <8 x i32> %cvt
} }
define <4 x i64> @fptoui_4f32_to_4i64(<8 x float> %a) { define <4 x i64> @fptoui_4f32_to_4i64(<8 x float> %a) {
; SSE-LABEL: fptoui_4f32_to_4i64: ; SSE-LABEL: fptoui_4f32_to_4i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SSE-NEXT: movaps %xmm0, %xmm2 ; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: subss %xmm1, %xmm2 ; SSE-NEXT: subss %xmm3, %xmm1
; SSE-NEXT: cvttss2si %xmm2, %rax ; SSE-NEXT: cvttss2si %xmm1, %rax
; SSE-NEXT: cvttss2si %xmm0, %rcx ; SSE-NEXT: cvttss2si %xmm0, %rcx
; SSE-NEXT: movq %rcx, %rdx ; SSE-NEXT: movq %rcx, %rdx
; SSE-NEXT: sarq $63, %rdx ; SSE-NEXT: sarq $63, %rdx
; SSE-NEXT: andq %rax, %rdx ; SSE-NEXT: andq %rax, %rdx
; SSE-NEXT: orq %rcx, %rdx ; SSE-NEXT: orq %rcx, %rdx
; SSE-NEXT: movq %rdx, %xmm2 ; SSE-NEXT: movq %rdx, %xmm2
; SSE-NEXT: movaps %xmm0, %xmm3 ; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm0[1,1] ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE-NEXT: cvttss2si %xmm3, %rax ; SSE-NEXT: cvttss2si %xmm1, %rax
; SSE-NEXT: subss %xmm1, %xmm3 ; SSE-NEXT: subss %xmm3, %xmm1
; SSE-NEXT: cvttss2si %xmm3, %rcx ; SSE-NEXT: cvttss2si %xmm1, %rcx
; SSE-NEXT: movq %rax, %rdx ; SSE-NEXT: movq %rax, %rdx
; SSE-NEXT: sarq $63, %rdx ; SSE-NEXT: sarq $63, %rdx
; SSE-NEXT: andq %rcx, %rdx ; SSE-NEXT: andq %rcx, %rdx
; SSE-NEXT: orq %rax, %rdx ; SSE-NEXT: orq %rax, %rdx
; SSE-NEXT: movq %rdx, %xmm3 ; SSE-NEXT: movq %rdx, %xmm1
; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] ; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; SSE-NEXT: movaps %xmm0, %xmm3 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3],xmm0[3,3] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: cvttss2si %xmm3, %rax ; SSE-NEXT: cvttss2si %xmm1, %rax
; SSE-NEXT: subss %xmm1, %xmm3 ; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: cvttss2si %xmm3, %rcx ; SSE-NEXT: sarq $63, %rcx
; SSE-NEXT: movq %rax, %rdx ; SSE-NEXT: subss %xmm3, %xmm1
; SSE-NEXT: sarq $63, %rdx ; SSE-NEXT: cvttss2si %xmm1, %rdx
; SSE-NEXT: andq %rcx, %rdx ; SSE-NEXT: andq %rcx, %rdx
; SSE-NEXT: orq %rax, %rdx ; SSE-NEXT: orq %rax, %rdx
; SSE-NEXT: movq %rdx, %xmm3 ; SSE-NEXT: movq %rdx, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE-NEXT: cvttss2si %xmm0, %rax ; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: subss %xmm1, %xmm0 ; SSE-NEXT: subss %xmm3, %xmm0
; SSE-NEXT: cvttss2si %xmm0, %rcx ; SSE-NEXT: cvttss2si %xmm0, %rcx
; SSE-NEXT: movq %rax, %rdx ; SSE-NEXT: movq %rax, %rdx
; SSE-NEXT: sarq $63, %rdx ; SSE-NEXT: sarq $63, %rdx
; SSE-NEXT: andq %rcx, %rdx ; SSE-NEXT: andq %rcx, %rdx
; SSE-NEXT: orq %rax, %rdx ; SSE-NEXT: orq %rax, %rdx
; SSE-NEXT: movq %rdx, %xmm1 ; SSE-NEXT: movq %rdx, %xmm0
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] ; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE-NEXT: movdqa %xmm2, %xmm0 ; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: fptoui_4f32_to_4i64: ; AVX1-LABEL: fptoui_4f32_to_4i64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[3,3,3,3] ; AVX1-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[3,3,3,3]
; AVX1-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; AVX1-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX1-NEXT: vsubss %xmm1, %xmm2, %xmm3 ; AVX1-NEXT: vsubss %xmm1, %xmm2, %xmm3
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%shuf = shufflevector <8 x float> %a, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %shuf = shufflevector <8 x float> %a, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = fptoui <4 x float> %shuf to <4 x i64> %cvt = fptoui <4 x float> %shuf to <4 x i64>
ret <4 x i64> %cvt ret <4 x i64> %cvt
} }
define <4 x i64> @fptoui_8f32_to_4i64(<8 x float> %a) { define <4 x i64> @fptoui_8f32_to_4i64(<8 x float> %a) {
; SSE-LABEL: fptoui_8f32_to_4i64: ; SSE-LABEL: fptoui_8f32_to_4i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SSE-NEXT: movaps %xmm0, %xmm2 ; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: subss %xmm1, %xmm2 ; SSE-NEXT: subss %xmm3, %xmm1
; SSE-NEXT: cvttss2si %xmm2, %rax ; SSE-NEXT: cvttss2si %xmm1, %rax
; SSE-NEXT: cvttss2si %xmm0, %rcx ; SSE-NEXT: cvttss2si %xmm0, %rcx
; SSE-NEXT: movq %rcx, %rdx ; SSE-NEXT: movq %rcx, %rdx
; SSE-NEXT: sarq $63, %rdx ; SSE-NEXT: sarq $63, %rdx
; SSE-NEXT: andq %rax, %rdx ; SSE-NEXT: andq %rax, %rdx
; SSE-NEXT: orq %rcx, %rdx ; SSE-NEXT: orq %rcx, %rdx
; SSE-NEXT: movq %rdx, %xmm2 ; SSE-NEXT: movq %rdx, %xmm2
; SSE-NEXT: movaps %xmm0, %xmm3 ; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm0[1,1] ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE-NEXT: cvttss2si %xmm3, %rax ; SSE-NEXT: cvttss2si %xmm1, %rax
; SSE-NEXT: subss %xmm1, %xmm3 ; SSE-NEXT: subss %xmm3, %xmm1
; SSE-NEXT: cvttss2si %xmm3, %rcx ; SSE-NEXT: cvttss2si %xmm1, %rcx
; SSE-NEXT: movq %rax, %rdx ; SSE-NEXT: movq %rax, %rdx
; SSE-NEXT: sarq $63, %rdx ; SSE-NEXT: sarq $63, %rdx
; SSE-NEXT: andq %rcx, %rdx ; SSE-NEXT: andq %rcx, %rdx
; SSE-NEXT: orq %rax, %rdx ; SSE-NEXT: orq %rax, %rdx
; SSE-NEXT: movq %rdx, %xmm3 ; SSE-NEXT: movq %rdx, %xmm1
; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] ; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; SSE-NEXT: movaps %xmm0, %xmm3 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3],xmm0[3,3] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: cvttss2si %xmm3, %rax ; SSE-NEXT: cvttss2si %xmm1, %rax
; SSE-NEXT: subss %xmm1, %xmm3 ; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: cvttss2si %xmm3, %rcx ; SSE-NEXT: sarq $63, %rcx
; SSE-NEXT: movq %rax, %rdx ; SSE-NEXT: subss %xmm3, %xmm1
; SSE-NEXT: sarq $63, %rdx ; SSE-NEXT: cvttss2si %xmm1, %rdx
; SSE-NEXT: andq %rcx, %rdx ; SSE-NEXT: andq %rcx, %rdx
; SSE-NEXT: orq %rax, %rdx ; SSE-NEXT: orq %rax, %rdx
; SSE-NEXT: movq %rdx, %xmm3 ; SSE-NEXT: movq %rdx, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE-NEXT: cvttss2si %xmm0, %rax ; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: subss %xmm1, %xmm0 ; SSE-NEXT: subss %xmm3, %xmm0
; SSE-NEXT: cvttss2si %xmm0, %rcx ; SSE-NEXT: cvttss2si %xmm0, %rcx
; SSE-NEXT: movq %rax, %rdx ; SSE-NEXT: movq %rax, %rdx
; SSE-NEXT: sarq $63, %rdx ; SSE-NEXT: sarq $63, %rdx
; SSE-NEXT: andq %rcx, %rdx ; SSE-NEXT: andq %rcx, %rdx
; SSE-NEXT: orq %rax, %rdx ; SSE-NEXT: orq %rax, %rdx
; SSE-NEXT: movq %rdx, %xmm1 ; SSE-NEXT: movq %rdx, %xmm0
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] ; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE-NEXT: movdqa %xmm2, %xmm0 ; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: fptoui_8f32_to_4i64: ; AVX1-LABEL: fptoui_8f32_to_4i64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[3,3,3,3] ; AVX1-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[3,3,3,3]
; AVX1-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; AVX1-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX1-NEXT: vsubss %xmm1, %xmm2, %xmm3 ; AVX1-NEXT: vsubss %xmm1, %xmm2, %xmm3
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llvm/test/CodeGen/X86/vec_fpext.ll

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%cvt = fpext <8 x float> %a to <8 x double> %cvt = fpext <8 x float> %a to <8 x double>
%shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <2 x i32> <i32 0, i32 1> %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf ret <2 x double> %shuf
} }
define <4 x double> @fpext_8f32_to_4f64(<8 x float> %a) { define <4 x double> @fpext_8f32_to_4f64(<8 x float> %a) {
; SSE-LABEL: fpext_8f32_to_4f64: ; SSE-LABEL: fpext_8f32_to_4f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: cvtps2pd %xmm0, %xmm2 # encoding: [0x0f,0x5a,0xd0] ; SSE-NEXT: movhlps %xmm0, %xmm1 # encoding: [0x0f,0x12,0xc8]
; SSE-NEXT: movhlps %xmm0, %xmm0 # encoding: [0x0f,0x12,0xc0] ; SSE-NEXT: # xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: # xmm0 = xmm0[1,1] ; SSE-NEXT: cvtps2pd %xmm1, %xmm1 # encoding: [0x0f,0x5a,0xc9]
; SSE-NEXT: cvtps2pd %xmm0, %xmm1 # encoding: [0x0f,0x5a,0xc8] ; SSE-NEXT: cvtps2pd %xmm0, %xmm0 # encoding: [0x0f,0x5a,0xc0]
; SSE-NEXT: movaps %xmm2, %xmm0 # encoding: [0x0f,0x28,0xc2]
; SSE-NEXT: ret{{[l|q]}} # encoding: [0xc3] ; SSE-NEXT: ret{{[l|q]}} # encoding: [0xc3]
; ;
; AVX-LABEL: fpext_8f32_to_4f64: ; AVX-LABEL: fpext_8f32_to_4f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vcvtps2pd %xmm0, %ymm0 # encoding: [0xc5,0xfc,0x5a,0xc0] ; AVX-NEXT: vcvtps2pd %xmm0, %ymm0 # encoding: [0xc5,0xfc,0x5a,0xc0]
; AVX-NEXT: ret{{[l|q]}} # encoding: [0xc3] ; AVX-NEXT: ret{{[l|q]}} # encoding: [0xc3]
; ;
; AVX512VL-LABEL: fpext_8f32_to_4f64: ; AVX512VL-LABEL: fpext_8f32_to_4f64:
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llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
define <3 x double> @constrained_vector_fdiv_v3f64() #0 { define <3 x double> @constrained_vector_fdiv_v3f64() #0 {
; CHECK-LABEL: constrained_vector_fdiv_v3f64: ; CHECK-LABEL: constrained_vector_fdiv_v3f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movapd {{.*#+}} xmm0 = [1.0E+0,2.0E+0] ; CHECK-NEXT: movapd {{.*#+}} xmm0 = [1.0E+0,2.0E+0]
; CHECK-NEXT: divpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-NEXT: divpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: divsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-NEXT: divsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movapd %xmm0, %xmm1 ; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: fldl -{{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl -{{[0-9]+}}(%rsp)
; CHECK-NEXT: wait ; CHECK-NEXT: wait
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_fdiv_v3f64: ; AVX-LABEL: constrained_vector_fdiv_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: vdivsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vdivsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 376 Lines • ▼ Show 20 Lines
define <3 x double> @constrained_vector_fmul_v3f64() #0 { define <3 x double> @constrained_vector_fmul_v3f64() #0 {
; CHECK-LABEL: constrained_vector_fmul_v3f64: ; CHECK-LABEL: constrained_vector_fmul_v3f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movapd {{.*#+}} xmm0 = [1.7976931348623157E+308,1.7976931348623157E+308] ; CHECK-NEXT: movapd {{.*#+}} xmm0 = [1.7976931348623157E+308,1.7976931348623157E+308]
; CHECK-NEXT: mulpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-NEXT: mulpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movapd %xmm0, %xmm1 ; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: fldl -{{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl -{{[0-9]+}}(%rsp)
; CHECK-NEXT: wait ; CHECK-NEXT: wait
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_fmul_v3f64: ; AVX-LABEL: constrained_vector_fmul_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines
define <3 x double> @constrained_vector_fadd_v3f64() #0 { define <3 x double> @constrained_vector_fadd_v3f64() #0 {
; CHECK-LABEL: constrained_vector_fadd_v3f64: ; CHECK-LABEL: constrained_vector_fadd_v3f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movapd {{.*#+}} xmm0 = [1.7976931348623157E+308,1.7976931348623157E+308] ; CHECK-NEXT: movapd {{.*#+}} xmm0 = [1.7976931348623157E+308,1.7976931348623157E+308]
; CHECK-NEXT: addpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-NEXT: addpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: xorpd %xmm1, %xmm1 ; CHECK-NEXT: xorpd %xmm1, %xmm1
; CHECK-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movapd %xmm0, %xmm1 ; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: fldl -{{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl -{{[0-9]+}}(%rsp)
; CHECK-NEXT: wait ; CHECK-NEXT: wait
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_fadd_v3f64: ; AVX-LABEL: constrained_vector_fadd_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vxorpd %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vxorpd %xmm0, %xmm0, %xmm0
; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; CHECK-LABEL: constrained_vector_fsub_v3f64: ; CHECK-LABEL: constrained_vector_fsub_v3f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorpd %xmm0, %xmm0 ; CHECK-NEXT: xorpd %xmm0, %xmm0
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: subsd %xmm0, %xmm1 ; CHECK-NEXT: subsd %xmm0, %xmm1
; CHECK-NEXT: movapd {{.*#+}} xmm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308] ; CHECK-NEXT: movapd {{.*#+}} xmm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308]
; CHECK-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movapd %xmm0, %xmm1 ; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: fldl -{{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl -{{[0-9]+}}(%rsp)
; CHECK-NEXT: wait ; CHECK-NEXT: wait
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_fsub_v3f64: ; AVX-LABEL: constrained_vector_fsub_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vxorpd %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vxorpd %xmm0, %xmm0, %xmm0
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
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define <3 x double> @constrained_vector_sqrt_v3f64() #0 { define <3 x double> @constrained_vector_sqrt_v3f64() #0 {
; CHECK-LABEL: constrained_vector_sqrt_v3f64: ; CHECK-LABEL: constrained_vector_sqrt_v3f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: sqrtsd %xmm0, %xmm1 ; CHECK-NEXT: sqrtsd %xmm0, %xmm1
; CHECK-NEXT: sqrtpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-NEXT: sqrtpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movapd %xmm0, %xmm1 ; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; CHECK-NEXT: fldl -{{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl -{{[0-9]+}}(%rsp)
; CHECK-NEXT: wait ; CHECK-NEXT: wait
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_sqrt_v3f64: ; AVX-LABEL: constrained_vector_sqrt_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
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llvm/test/CodeGen/X86/vector-intrinsics.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
declare <4 x double> @llvm.sin.v4f64(<4 x double> %p) declare <4 x double> @llvm.sin.v4f64(<4 x double> %p)
declare <4 x double> @llvm.cos.v4f64(<4 x double> %p) declare <4 x double> @llvm.cos.v4f64(<4 x double> %p)
declare <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q) declare <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q)
declare <4 x double> @llvm.powi.v4f64.i32(<4 x double> %p, i32) declare <4 x double> @llvm.powi.v4f64.i32(<4 x double> %p, i32)
define <4 x double> @foo(<4 x double> %p) define <4 x double> @foo(<4 x double> %p)
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: subq $56, %rsp ; CHECK-NEXT: subq $56, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: callq sin@PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq sin@PLT ; CHECK-NEXT: callq sin@PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: callq sin@PLT ; CHECK-NEXT: callq sin@PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq sin@PLT ; CHECK-NEXT: callq sin@PLT
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: callq sin@PLT
; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload
; CHECK-NEXT: # xmm1 = xmm1[0],mem[0]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: addq $56, %rsp ; CHECK-NEXT: addq $56, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
{ {
%t = call <4 x double> @llvm.sin.v4f64(<4 x double> %p) %t = call <4 x double> @llvm.sin.v4f64(<4 x double> %p)
ret <4 x double> %t ret <4 x double> %t
} }
define <4 x double> @goo(<4 x double> %p) define <4 x double> @goo(<4 x double> %p)
; CHECK-LABEL: goo: ; CHECK-LABEL: goo:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: subq $56, %rsp ; CHECK-NEXT: subq $56, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: callq cos@PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq cos@PLT ; CHECK-NEXT: callq cos@PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: callq cos@PLT ; CHECK-NEXT: callq cos@PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq cos@PLT ; CHECK-NEXT: callq cos@PLT
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: callq cos@PLT
; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload
; CHECK-NEXT: # xmm1 = xmm1[0],mem[0]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: addq $56, %rsp ; CHECK-NEXT: addq $56, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
{ {
%t = call <4 x double> @llvm.cos.v4f64(<4 x double> %p) %t = call <4 x double> @llvm.cos.v4f64(<4 x double> %p)
ret <4 x double> %t ret <4 x double> %t
} }
define <4 x double> @moo(<4 x double> %p, <4 x double> %q) define <4 x double> @moo(<4 x double> %p, <4 x double> %q)
; CHECK-LABEL: moo: ; CHECK-LABEL: moo:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: subq $88, %rsp ; CHECK-NEXT: subq $88, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 96 ; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm2, (%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm2, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm2, %xmm1 ; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; CHECK-NEXT: callq pow@PLT ; CHECK-NEXT: callq pow@PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq pow@PLT ; CHECK-NEXT: callq pow@PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq pow@PLT ; CHECK-NEXT: callq pow@PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq pow@PLT ; CHECK-NEXT: callq pow@PLT
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload
; CHECK-NEXT: # xmm1 = xmm1[0],mem[0]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: addq $88, %rsp ; CHECK-NEXT: addq $88, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
{ {
%t = call <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q) %t = call <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q)
ret <4 x double> %t ret <4 x double> %t
} }
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: subq $96, %rsp ; CHECK-NEXT: subq $96, %rsp
; CHECK-NEXT: movq %rdi, %rbx ; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rdi), %xmm0 ; CHECK-NEXT: movaps (%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 16(%rdi), %xmm0 ; CHECK-NEXT: movaps 16(%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 32(%rdi), %xmm0 ; CHECK-NEXT: movaps 32(%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 48(%rdi), %xmm0 ; CHECK-NEXT: movaps 48(%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq exp@PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: callq exp@PLT ; CHECK-NEXT: callq exp@PLT
; CHECK-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq exp@PLT ; CHECK-NEXT: callq exp@PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: callq exp@PLT ; CHECK-NEXT: callq exp@PLT
; CHECK-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq exp@PLT ; CHECK-NEXT: callq exp@PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: callq exp@PLT ; CHECK-NEXT: callq exp@PLT
; CHECK-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq exp@PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq exp@PLT ; CHECK-NEXT: callq exp@PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq exp@PLT ; CHECK-NEXT: callq exp@PLT
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
; CHECK-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: callq exp@PLT ; CHECK-NEXT: callq exp@PLT
; CHECK-NEXT: movsd %xmm0, 64(%rbx) ; CHECK-NEXT: movsd %xmm0, 64(%rbx)
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, (%rbx) ; CHECK-NEXT: movaps %xmm0, (%rbx)
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, 16(%rbx) ; CHECK-NEXT: movaps %xmm0, 16(%rbx)
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, 32(%rbx) ; CHECK-NEXT: movaps %xmm0, 32(%rbx)
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, 48(%rbx) ; CHECK-NEXT: movaps %xmm0, 48(%rbx)
; CHECK-NEXT: addq $96, %rsp ; CHECK-NEXT: addq $96, %rsp
Show All 10 Lines
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: subq $160, %rsp ; CHECK-NEXT: subq $160, %rsp
; CHECK-NEXT: movq %rdi, %rbx ; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rdi), %xmm0 ; CHECK-NEXT: movaps (%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 16(%rdi), %xmm0 ; CHECK-NEXT: movaps 16(%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 32(%rdi), %xmm0 ; CHECK-NEXT: movaps 32(%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 48(%rdi), %xmm2 ; CHECK-NEXT: movaps 48(%rdi), %xmm1
; CHECK-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rsi), %xmm0 ; CHECK-NEXT: movaps (%rsi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 16(%rsi), %xmm0 ; CHECK-NEXT: movaps 16(%rsi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 32(%rsi), %xmm0 ; CHECK-NEXT: movaps 32(%rsi), %xmm0
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps 48(%rsi), %xmm2
; CHECK-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; CHECK-NEXT: callq pow@PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 48(%rsi), %xmm1 ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movaps %xmm2, %xmm0
; CHECK-NEXT: callq pow@PLT ; CHECK-NEXT: callq pow@PLT
; CHECK-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq pow@PLT ; CHECK-NEXT: callq pow@PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: callq pow@PLT ; CHECK-NEXT: callq pow@PLT
; CHECK-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq pow@PLT ; CHECK-NEXT: callq pow@PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: callq pow@PLT ; CHECK-NEXT: callq pow@PLT
; CHECK-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq pow@PLT ; CHECK-NEXT: callq pow@PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: callq pow@PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq pow@PLT ; CHECK-NEXT: callq pow@PLT
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: # xmm0 = xmm0[0],mem[0]
; CHECK-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: callq pow@PLT ; CHECK-NEXT: callq pow@PLT
; CHECK-NEXT: movsd %xmm0, 64(%rbx) ; CHECK-NEXT: movsd %xmm0, 64(%rbx)
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, (%rbx) ; CHECK-NEXT: movaps %xmm0, (%rbx)
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, 16(%rbx) ; CHECK-NEXT: movaps %xmm0, 16(%rbx)
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, 32(%rbx) ; CHECK-NEXT: movaps %xmm0, 32(%rbx)
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, 48(%rbx) ; CHECK-NEXT: movaps %xmm0, 48(%rbx)
; CHECK-NEXT: addq $160, %rsp ; CHECK-NEXT: addq $160, %rsp
▲ Show 20 Lines • Show All 91 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-narrow-binop.ll

Show First 20 Lines • Show All 148 Lines • ▼ Show 20 Lines
define <4 x double> @fmul_v2f64(<2 x double> %x, <2 x double> %y) { define <4 x double> @fmul_v2f64(<2 x double> %x, <2 x double> %y) {
; SSE-LABEL: fmul_v2f64: ; SSE-LABEL: fmul_v2f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm1, %xmm2 ; SSE-NEXT: movapd %xmm1, %xmm2
; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm0[0] ; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; SSE-NEXT: mulpd %xmm2, %xmm2 ; SSE-NEXT: mulpd %xmm2, %xmm2
; SSE-NEXT: mulpd %xmm1, %xmm1 ; SSE-NEXT: mulpd %xmm1, %xmm1
; SSE-NEXT: addpd %xmm1, %xmm2 ; SSE-NEXT: addpd %xmm1, %xmm2
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movapd %xmm2, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm2[1],xmm0[1]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: fmul_v2f64: ; AVX1-LABEL: fmul_v2f64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm1[0],xmm0[0] ; AVX1-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm1[0],xmm0[0]
; AVX1-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; AVX1-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; AVX1-NEXT: vmulpd %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vmulpd %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vmulpd %xmm2, %xmm2, %xmm1 ; AVX1-NEXT: vmulpd %xmm2, %xmm2, %xmm1
Show All 29 Lines

llvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call fast float @llvm.vector.reduce.fadd.f32.v2f32(float %a0, <2 x float> %a1) %1 = call fast float @llvm.vector.reduce.fadd.f32.v2f32(float %a0, <2 x float> %a1)
ret float %1 ret float %1
} }
define float @test_v4f32(float %a0, <4 x float> %a1) { define float @test_v4f32(float %a0, <4 x float> %a1) {
; SSE2-LABEL: test_v4f32: ; SSE2-LABEL: test_v4f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1]
; SSE2-NEXT: addps %xmm1, %xmm2 ; SSE2-NEXT: addps %xmm1, %xmm2
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1]
; SSE2-NEXT: addss %xmm2, %xmm1 ; SSE2-NEXT: addss %xmm2, %xmm1
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32: ; SSE41-LABEL: test_v4f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm1, %xmm2 ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1]
; SSE41-NEXT: addps %xmm1, %xmm2 ; SSE41-NEXT: addps %xmm1, %xmm2
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE41-NEXT: addss %xmm2, %xmm1 ; SSE41-NEXT: addss %xmm2, %xmm1
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v4f32: ; AVX1-SLOW-LABEL: test_v4f32:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
Show All 31 Lines; AVX512-NEXT: retq
%1 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float %a0, <4 x float> %a1) %1 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float %a0, <4 x float> %a1)
ret float %1 ret float %1
} }
define float @test_v8f32(float %a0, <8 x float> %a1) { define float @test_v8f32(float %a0, <8 x float> %a1) {
; SSE2-LABEL: test_v8f32: ; SSE2-LABEL: test_v8f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addps %xmm2, %xmm1 ; SSE2-NEXT: addps %xmm2, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE2-NEXT: addps %xmm1, %xmm2 ; SSE2-NEXT: addps %xmm1, %xmm2
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1]
; SSE2-NEXT: addss %xmm2, %xmm1 ; SSE2-NEXT: addss %xmm2, %xmm1
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32: ; SSE41-LABEL: test_v8f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: addps %xmm2, %xmm1 ; SSE41-NEXT: addps %xmm2, %xmm1
; SSE41-NEXT: movaps %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: addps %xmm1, %xmm2 ; SSE41-NEXT: addps %xmm1, %xmm2
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE41-NEXT: addss %xmm2, %xmm1 ; SSE41-NEXT: addss %xmm2, %xmm1
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v8f32: ; AVX1-SLOW-LABEL: test_v8f32:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
} }
define float @test_v16f32(float %a0, <16 x float> %a1) { define float @test_v16f32(float %a0, <16 x float> %a1) {
; SSE2-LABEL: test_v16f32: ; SSE2-LABEL: test_v16f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addps %xmm4, %xmm2 ; SSE2-NEXT: addps %xmm4, %xmm2
; SSE2-NEXT: addps %xmm3, %xmm1 ; SSE2-NEXT: addps %xmm3, %xmm1
; SSE2-NEXT: addps %xmm2, %xmm1 ; SSE2-NEXT: addps %xmm2, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE2-NEXT: addps %xmm1, %xmm2 ; SSE2-NEXT: addps %xmm1, %xmm2
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1]
; SSE2-NEXT: addss %xmm2, %xmm1 ; SSE2-NEXT: addss %xmm2, %xmm1
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32: ; SSE41-LABEL: test_v16f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: addps %xmm4, %xmm2 ; SSE41-NEXT: addps %xmm4, %xmm2
; SSE41-NEXT: addps %xmm3, %xmm1 ; SSE41-NEXT: addps %xmm3, %xmm1
; SSE41-NEXT: addps %xmm2, %xmm1 ; SSE41-NEXT: addps %xmm2, %xmm1
; SSE41-NEXT: movaps %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: addps %xmm1, %xmm2 ; SSE41-NEXT: addps %xmm1, %xmm2
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE41-NEXT: addss %xmm2, %xmm1 ; SSE41-NEXT: addss %xmm2, %xmm1
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v16f32: ; AVX1-SLOW-LABEL: test_v16f32:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call fast float @llvm.vector.reduce.fadd.f32.v2f32(float 0.0, <2 x float> %a0) %1 = call fast float @llvm.vector.reduce.fadd.f32.v2f32(float 0.0, <2 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v4f32_zero(<4 x float> %a0) { define float @test_v4f32_zero(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32_zero: ; SSE2-LABEL: test_v4f32_zero:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32_zero: ; SSE41-LABEL: test_v4f32_zero:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: addps %xmm1, %xmm0 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v4f32_zero: ; AVX1-SLOW-LABEL: test_v4f32_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
Show All 26 Lines; AVX512-NEXT: retq
%1 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 0.0, <4 x float> %a0) %1 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 0.0, <4 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v8f32_zero(<8 x float> %a0) { define float @test_v8f32_zero(<8 x float> %a0) {
; SSE2-LABEL: test_v8f32_zero: ; SSE2-LABEL: test_v8f32_zero:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32_zero: ; SSE41-LABEL: test_v8f32_zero:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: addps %xmm1, %xmm0 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: addps %xmm1, %xmm0 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v8f32_zero: ; AVX1-SLOW-LABEL: test_v8f32_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1
Show All 40 Lines
} }
define float @test_v16f32_zero(<16 x float> %a0) { define float @test_v16f32_zero(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32_zero: ; SSE2-LABEL: test_v16f32_zero:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addps %xmm3, %xmm1 ; SSE2-NEXT: addps %xmm3, %xmm1
; SSE2-NEXT: addps %xmm2, %xmm0 ; SSE2-NEXT: addps %xmm2, %xmm0
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32_zero: ; SSE41-LABEL: test_v16f32_zero:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: addps %xmm3, %xmm1 ; SSE41-NEXT: addps %xmm3, %xmm1
; SSE41-NEXT: addps %xmm2, %xmm0 ; SSE41-NEXT: addps %xmm2, %xmm0
; SSE41-NEXT: addps %xmm1, %xmm0 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: addps %xmm1, %xmm0 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v16f32_zero: ; AVX1-SLOW-LABEL: test_v16f32_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddps %ymm1, %ymm0, %ymm0
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call fast float @llvm.vector.reduce.fadd.f32.v2f32(float 0.0, <2 x float> %a0) %1 = call fast float @llvm.vector.reduce.fadd.f32.v2f32(float 0.0, <2 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v4f32_undef(<4 x float> %a0) { define float @test_v4f32_undef(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32_undef: ; SSE2-LABEL: test_v4f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32_undef: ; SSE41-LABEL: test_v4f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: addps %xmm1, %xmm0 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v4f32_undef: ; AVX1-SLOW-LABEL: test_v4f32_undef:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
Show All 26 Lines; AVX512-NEXT: retq
%1 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 0.0, <4 x float> %a0) %1 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 0.0, <4 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v8f32_undef(<8 x float> %a0) { define float @test_v8f32_undef(<8 x float> %a0) {
; SSE2-LABEL: test_v8f32_undef: ; SSE2-LABEL: test_v8f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32_undef: ; SSE41-LABEL: test_v8f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: addps %xmm1, %xmm0 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: addps %xmm1, %xmm0 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v8f32_undef: ; AVX1-SLOW-LABEL: test_v8f32_undef:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1
Show All 40 Lines
} }
define float @test_v16f32_undef(<16 x float> %a0) { define float @test_v16f32_undef(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32_undef: ; SSE2-LABEL: test_v16f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addps %xmm3, %xmm1 ; SSE2-NEXT: addps %xmm3, %xmm1
; SSE2-NEXT: addps %xmm2, %xmm0 ; SSE2-NEXT: addps %xmm2, %xmm0
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32_undef: ; SSE41-LABEL: test_v16f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: addps %xmm3, %xmm1 ; SSE41-NEXT: addps %xmm3, %xmm1
; SSE41-NEXT: addps %xmm2, %xmm0 ; SSE41-NEXT: addps %xmm2, %xmm0
; SSE41-NEXT: addps %xmm1, %xmm0 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: addps %xmm1, %xmm0 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v16f32_undef: ; AVX1-SLOW-LABEL: test_v16f32_undef:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddps %ymm1, %ymm0, %ymm0
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; ;
; vXf64 (accum) ; vXf64 (accum)
; ;
define double @test_v2f64(double %a0, <2 x double> %a1) { define double @test_v2f64(double %a0, <2 x double> %a1) {
; SSE-LABEL: test_v2f64: ; SSE-LABEL: test_v2f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm1, %xmm2 ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm2 ; SSE-NEXT: addsd %xmm1, %xmm2
; SSE-NEXT: addsd %xmm2, %xmm0 ; SSE-NEXT: addsd %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v2f64: ; AVX1-SLOW-LABEL: test_v2f64:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm2 = xmm1[1,0] ; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm2 = xmm1[1,0]
; AVX1-SLOW-NEXT: vaddsd %xmm2, %xmm1, %xmm1 ; AVX1-SLOW-NEXT: vaddsd %xmm2, %xmm1, %xmm1
Show All 22 Lines; AVX512-NEXT: retq
%1 = call fast double @llvm.vector.reduce.fadd.f64.v2f64(double %a0, <2 x double> %a1) %1 = call fast double @llvm.vector.reduce.fadd.f64.v2f64(double %a0, <2 x double> %a1)
ret double %1 ret double %1
} }
define double @test_v4f64(double %a0, <4 x double> %a1) { define double @test_v4f64(double %a0, <4 x double> %a1) {
; SSE-LABEL: test_v4f64: ; SSE-LABEL: test_v4f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm2, %xmm1 ; SSE-NEXT: addpd %xmm2, %xmm1
; SSE-NEXT: movapd %xmm1, %xmm2 ; SSE-NEXT: xorps %xmm2, %xmm2
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE-NEXT: addsd %xmm1, %xmm2 ; SSE-NEXT: addsd %xmm1, %xmm2
; SSE-NEXT: addsd %xmm2, %xmm0 ; SSE-NEXT: addsd %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v4f64: ; AVX1-SLOW-LABEL: test_v4f64:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-SLOW-NEXT: vaddpd %xmm2, %xmm1, %xmm1 ; AVX1-SLOW-NEXT: vaddpd %xmm2, %xmm1, %xmm1
Show All 36 Lines
} }
define double @test_v8f64(double %a0, <8 x double> %a1) { define double @test_v8f64(double %a0, <8 x double> %a1) {
; SSE-LABEL: test_v8f64: ; SSE-LABEL: test_v8f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm4, %xmm2 ; SSE-NEXT: addpd %xmm4, %xmm2
; SSE-NEXT: addpd %xmm3, %xmm1 ; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: addpd %xmm2, %xmm1 ; SSE-NEXT: addpd %xmm2, %xmm1
; SSE-NEXT: movapd %xmm1, %xmm2 ; SSE-NEXT: xorps %xmm2, %xmm2
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE-NEXT: addsd %xmm1, %xmm2 ; SSE-NEXT: addsd %xmm1, %xmm2
; SSE-NEXT: addsd %xmm2, %xmm0 ; SSE-NEXT: addsd %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v8f64: ; AVX1-SLOW-LABEL: test_v8f64:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vaddpd %ymm2, %ymm1, %ymm1 ; AVX1-SLOW-NEXT: vaddpd %ymm2, %ymm1, %ymm1
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm1, %xmm2
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} }
define double @test_v16f64(double %a0, <16 x double> %a1) { define double @test_v16f64(double %a0, <16 x double> %a1) {
; SSE-LABEL: test_v16f64: ; SSE-LABEL: test_v16f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm6, %xmm2 ; SSE-NEXT: addpd %xmm6, %xmm2
; SSE-NEXT: addpd %xmm7, %xmm3 ; SSE-NEXT: addpd %xmm7, %xmm3
; SSE-NEXT: addpd %xmm5, %xmm1 ; SSE-NEXT: addpd %xmm5, %xmm1
; SSE-NEXT: addpd {{[0-9]+}}(%rsp), %xmm4
; SSE-NEXT: addpd %xmm3, %xmm1 ; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: addpd {{[0-9]+}}(%rsp), %xmm4
; SSE-NEXT: addpd %xmm2, %xmm4 ; SSE-NEXT: addpd %xmm2, %xmm4
; SSE-NEXT: addpd %xmm1, %xmm4 ; SSE-NEXT: addpd %xmm1, %xmm4
; SSE-NEXT: movapd %xmm4, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm4[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm4[1],xmm1[1]
; SSE-NEXT: addsd %xmm4, %xmm1 ; SSE-NEXT: addsd %xmm4, %xmm1
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v16f64: ; AVX1-SLOW-LABEL: test_v16f64:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vaddpd %ymm4, %ymm2, %ymm2 ; AVX1-SLOW-NEXT: vaddpd %ymm4, %ymm2, %ymm2
; AVX1-SLOW-NEXT: vaddpd %ymm3, %ymm1, %ymm1 ; AVX1-SLOW-NEXT: vaddpd %ymm3, %ymm1, %ymm1
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; ;
; vXf64 (zero) ; vXf64 (zero)
; ;
define double @test_v2f64_zero(<2 x double> %a0) { define double @test_v2f64_zero(<2 x double> %a0) {
; SSE-LABEL: test_v2f64_zero: ; SSE-LABEL: test_v2f64_zero:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v2f64_zero: ; AVX1-SLOW-LABEL: test_v2f64_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX1-SLOW-NEXT: vaddsd %xmm1, %xmm0, %xmm0 ; AVX1-SLOW-NEXT: vaddsd %xmm1, %xmm0, %xmm0
; AVX1-SLOW-NEXT: retq ; AVX1-SLOW-NEXT: retq
Show All 17 Lines; AVX512-NEXT: retq
%1 = call fast double @llvm.vector.reduce.fadd.f64.v2f64(double 0.0, <2 x double> %a0) %1 = call fast double @llvm.vector.reduce.fadd.f64.v2f64(double 0.0, <2 x double> %a0)
ret double %1 ret double %1
} }
define double @test_v4f64_zero(<4 x double> %a0) { define double @test_v4f64_zero(<4 x double> %a0) {
; SSE-LABEL: test_v4f64_zero: ; SSE-LABEL: test_v4f64_zero:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm1, %xmm0 ; SSE-NEXT: addpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v4f64_zero: ; AVX1-SLOW-LABEL: test_v4f64_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-SLOW-NEXT: vaddpd %xmm1, %xmm0, %xmm0 ; AVX1-SLOW-NEXT: vaddpd %xmm1, %xmm0, %xmm0
; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
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} }
define double @test_v8f64_zero(<8 x double> %a0) { define double @test_v8f64_zero(<8 x double> %a0) {
; SSE-LABEL: test_v8f64_zero: ; SSE-LABEL: test_v8f64_zero:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm3, %xmm1 ; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: addpd %xmm2, %xmm0 ; SSE-NEXT: addpd %xmm2, %xmm0
; SSE-NEXT: addpd %xmm1, %xmm0 ; SSE-NEXT: addpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v8f64_zero: ; AVX1-SLOW-LABEL: test_v8f64_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-SLOW-NEXT: vaddpd %xmm1, %xmm0, %xmm0 ; AVX1-SLOW-NEXT: vaddpd %xmm1, %xmm0, %xmm0
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; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm6, %xmm2 ; SSE-NEXT: addpd %xmm6, %xmm2
; SSE-NEXT: addpd %xmm4, %xmm0 ; SSE-NEXT: addpd %xmm4, %xmm0
; SSE-NEXT: addpd %xmm2, %xmm0 ; SSE-NEXT: addpd %xmm2, %xmm0
; SSE-NEXT: addpd %xmm7, %xmm3 ; SSE-NEXT: addpd %xmm7, %xmm3
; SSE-NEXT: addpd %xmm5, %xmm1 ; SSE-NEXT: addpd %xmm5, %xmm1
; SSE-NEXT: addpd %xmm3, %xmm1 ; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: addpd %xmm1, %xmm0 ; SSE-NEXT: addpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v16f64_zero: ; AVX1-SLOW-LABEL: test_v16f64_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vaddpd %ymm3, %ymm1, %ymm1 ; AVX1-SLOW-NEXT: vaddpd %ymm3, %ymm1, %ymm1
; AVX1-SLOW-NEXT: vaddpd %ymm2, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVX1-SLOW-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddpd %ymm1, %ymm0, %ymm0
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; ;
; vXf64 (undef) ; vXf64 (undef)
; ;
define double @test_v2f64_undef(<2 x double> %a0) { define double @test_v2f64_undef(<2 x double> %a0) {
; SSE-LABEL: test_v2f64_undef: ; SSE-LABEL: test_v2f64_undef:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v2f64_undef: ; AVX1-SLOW-LABEL: test_v2f64_undef:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX1-SLOW-NEXT: vaddsd %xmm1, %xmm0, %xmm0 ; AVX1-SLOW-NEXT: vaddsd %xmm1, %xmm0, %xmm0
; AVX1-SLOW-NEXT: retq ; AVX1-SLOW-NEXT: retq
Show All 17 Lines; AVX512-NEXT: retq
%1 = call fast double @llvm.vector.reduce.fadd.f64.v2f64(double 0.0, <2 x double> %a0) %1 = call fast double @llvm.vector.reduce.fadd.f64.v2f64(double 0.0, <2 x double> %a0)
ret double %1 ret double %1
} }
define double @test_v4f64_undef(<4 x double> %a0) { define double @test_v4f64_undef(<4 x double> %a0) {
; SSE-LABEL: test_v4f64_undef: ; SSE-LABEL: test_v4f64_undef:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm1, %xmm0 ; SSE-NEXT: addpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v4f64_undef: ; AVX1-SLOW-LABEL: test_v4f64_undef:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-SLOW-NEXT: vaddpd %xmm1, %xmm0, %xmm0 ; AVX1-SLOW-NEXT: vaddpd %xmm1, %xmm0, %xmm0
; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
Show All 31 Lines
} }
define double @test_v8f64_undef(<8 x double> %a0) { define double @test_v8f64_undef(<8 x double> %a0) {
; SSE-LABEL: test_v8f64_undef: ; SSE-LABEL: test_v8f64_undef:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm3, %xmm1 ; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: addpd %xmm2, %xmm0 ; SSE-NEXT: addpd %xmm2, %xmm0
; SSE-NEXT: addpd %xmm1, %xmm0 ; SSE-NEXT: addpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v8f64_undef: ; AVX1-SLOW-LABEL: test_v8f64_undef:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-SLOW-NEXT: vaddpd %xmm1, %xmm0, %xmm0 ; AVX1-SLOW-NEXT: vaddpd %xmm1, %xmm0, %xmm0
Show All 40 Lines
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm6, %xmm2 ; SSE-NEXT: addpd %xmm6, %xmm2
; SSE-NEXT: addpd %xmm4, %xmm0 ; SSE-NEXT: addpd %xmm4, %xmm0
; SSE-NEXT: addpd %xmm2, %xmm0 ; SSE-NEXT: addpd %xmm2, %xmm0
; SSE-NEXT: addpd %xmm7, %xmm3 ; SSE-NEXT: addpd %xmm7, %xmm3
; SSE-NEXT: addpd %xmm5, %xmm1 ; SSE-NEXT: addpd %xmm5, %xmm1
; SSE-NEXT: addpd %xmm3, %xmm1 ; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: addpd %xmm1, %xmm0 ; SSE-NEXT: addpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v16f64_undef: ; AVX1-SLOW-LABEL: test_v16f64_undef:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vaddpd %ymm3, %ymm1, %ymm1 ; AVX1-SLOW-NEXT: vaddpd %ymm3, %ymm1, %ymm1
; AVX1-SLOW-NEXT: vaddpd %ymm2, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVX1-SLOW-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddpd %ymm1, %ymm0, %ymm0
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llvm/test/CodeGen/X86/vector-reduce-fadd.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
define float @test_v4f32(float %a0, <4 x float> %a1) { define float @test_v4f32(float %a0, <4 x float> %a1) {
; SSE2-LABEL: test_v4f32: ; SSE2-LABEL: test_v4f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: movaps %xmm1, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1]
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
RKSimonAuthorUnsubmitted
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TBH I'm not convinced any of these need dependency breaks.

RKSimon: TBH I'm not convinced any of these need dependency breaks.
craig.topperUnsubmitted
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Will it always insert a dependency break because it can't rewrite the tied dest?

craig.topper: Will it always insert a dependency break because it can't rewrite the tied dest?
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32: ; SSE41-LABEL: test_v4f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3]
; SSE41-NEXT: addss %xmm2, %xmm0 ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: movaps %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: addss %xmm2, %xmm0 ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v4f32: ; AVX-LABEL: test_v4f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
Show All 21 Lines
define float @test_v8f32(float %a0, <8 x float> %a1) { define float @test_v8f32(float %a0, <8 x float> %a1) {
; SSE2-LABEL: test_v8f32: ; SSE2-LABEL: test_v8f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm3 ; SSE2-NEXT: movaps %xmm1, %xmm3
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm1[1,1]
; SSE2-NEXT: addss %xmm3, %xmm0 ; SSE2-NEXT: addss %xmm3, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm3 ; SSE2-NEXT: xorps %xmm3, %xmm3
; SSE2-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm3 = xmm1[1],xmm3[1]
; SSE2-NEXT: addss %xmm3, %xmm0 ; SSE2-NEXT: addss %xmm3, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32: ; SSE41-LABEL: test_v8f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm3 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm3 = xmm1[1,1,3,3]
; SSE41-NEXT: addss %xmm3, %xmm0 ; SSE41-NEXT: addss %xmm3, %xmm0
; SSE41-NEXT: movaps %xmm1, %xmm3 ; SSE41-NEXT: xorps %xmm3, %xmm3
; SSE41-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm3 = xmm1[1],xmm3[1]
; SSE41-NEXT: addss %xmm3, %xmm0 ; SSE41-NEXT: addss %xmm3, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: addss %xmm2, %xmm0 ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm2, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE41-NEXT: addss %xmm2, %xmm0 ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v8f32: ; AVX-LABEL: test_v8f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
Show All 39 Lines
define float @test_v16f32(float %a0, <16 x float> %a1) { define float @test_v16f32(float %a0, <16 x float> %a1) {
; SSE2-LABEL: test_v16f32: ; SSE2-LABEL: test_v16f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm5 ; SSE2-NEXT: movaps %xmm1, %xmm5
; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,1],xmm1[1,1]
; SSE2-NEXT: addss %xmm5, %xmm0 ; SSE2-NEXT: addss %xmm5, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm5 ; SSE2-NEXT: xorps %xmm5, %xmm5
; SSE2-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm5 = xmm1[1],xmm5[1]
; SSE2-NEXT: addss %xmm5, %xmm0 ; SSE2-NEXT: addss %xmm5, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: addss %xmm3, %xmm0 ; SSE2-NEXT: addss %xmm3, %xmm0
; SSE2-NEXT: movaps %xmm3, %xmm1 ; SSE2-NEXT: movaps %xmm3, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm3[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm3[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm3, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSE2-NEXT: addss %xmm3, %xmm0 ; SSE2-NEXT: addss %xmm3, %xmm0
; SSE2-NEXT: addss %xmm4, %xmm0 ; SSE2-NEXT: addss %xmm4, %xmm0
; SSE2-NEXT: movaps %xmm4, %xmm1 ; SSE2-NEXT: movaps %xmm4, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm4[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm4[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm4, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm4[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm4[1],xmm1[1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
; SSE2-NEXT: addss %xmm4, %xmm0 ; SSE2-NEXT: addss %xmm4, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32: ; SSE41-LABEL: test_v16f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm5 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm5 = xmm1[1,1,3,3]
; SSE41-NEXT: addss %xmm5, %xmm0 ; SSE41-NEXT: addss %xmm5, %xmm0
; SSE41-NEXT: movaps %xmm1, %xmm5 ; SSE41-NEXT: xorps %xmm5, %xmm5
; SSE41-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm5 = xmm1[1],xmm5[1]
; SSE41-NEXT: addss %xmm5, %xmm0 ; SSE41-NEXT: addss %xmm5, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: addss %xmm2, %xmm0 ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm2, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE41-NEXT: addss %xmm2, %xmm0 ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: addss %xmm3, %xmm0 ; SSE41-NEXT: addss %xmm3, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm3[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm3[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm3, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSE41-NEXT: addss %xmm3, %xmm0 ; SSE41-NEXT: addss %xmm3, %xmm0
; SSE41-NEXT: addss %xmm4, %xmm0 ; SSE41-NEXT: addss %xmm4, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm4[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm4[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm4, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm4[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm4[1],xmm1[1]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
; SSE41-NEXT: addss %xmm4, %xmm0 ; SSE41-NEXT: addss %xmm4, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v16f32: ; AVX-LABEL: test_v16f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
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} }
define float @test_v4f32_zero(<4 x float> %a0) { define float @test_v4f32_zero(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32_zero: ; SSE2-LABEL: test_v4f32_zero:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm0, %xmm1 ; SSE2-NEXT: addss %xmm0, %xmm1
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE2-NEXT: addss %xmm1, %xmm2 ; SSE2-NEXT: addss %xmm1, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32_zero: ; SSE41-LABEL: test_v4f32_zero:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: addss %xmm0, %xmm1 ; SSE41-NEXT: addss %xmm0, %xmm1
; SSE41-NEXT: movaps %xmm0, %xmm2 ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE41-NEXT: addss %xmm1, %xmm2 ; SSE41-NEXT: addss %xmm1, %xmm2
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE41-NEXT: addss %xmm2, %xmm0 ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v4f32_zero: ; AVX1-SLOW-LABEL: test_v4f32_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX1-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
Show All 37 Lines
} }
define float @test_v8f32_zero(<8 x float> %a0) { define float @test_v8f32_zero(<8 x float> %a0) {
; SSE2-LABEL: test_v8f32_zero: ; SSE2-LABEL: test_v8f32_zero:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm0, %xmm2 ; SSE2-NEXT: addss %xmm0, %xmm2
; SSE2-NEXT: movaps %xmm0, %xmm3 ; SSE2-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; SSE2-NEXT: addss %xmm2, %xmm3 ; SSE2-NEXT: addss %xmm2, %xmm3
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: addss %xmm3, %xmm0 ; SSE2-NEXT: addss %xmm3, %xmm0
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: movaps %xmm1, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1]
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32_zero: ; SSE41-LABEL: test_v8f32_zero:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
; SSE41-NEXT: addss %xmm0, %xmm2 ; SSE41-NEXT: addss %xmm0, %xmm2
; SSE41-NEXT: movaps %xmm0, %xmm3 ; SSE41-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; SSE41-NEXT: addss %xmm2, %xmm3 ; SSE41-NEXT: addss %xmm2, %xmm3
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE41-NEXT: addss %xmm3, %xmm0 ; SSE41-NEXT: addss %xmm3, %xmm0
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3]
; SSE41-NEXT: addss %xmm2, %xmm0 ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: movaps %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: addss %xmm2, %xmm0 ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v8f32_zero: ; AVX1-SLOW-LABEL: test_v8f32_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX1-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
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} }
define float @test_v16f32_zero(<16 x float> %a0) { define float @test_v16f32_zero(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32_zero: ; SSE2-LABEL: test_v16f32_zero:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm4 ; SSE2-NEXT: movaps %xmm0, %xmm4
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm0, %xmm4 ; SSE2-NEXT: addss %xmm0, %xmm4
; SSE2-NEXT: movaps %xmm0, %xmm5 ; SSE2-NEXT: movhlps {{.*#+}} xmm5 = xmm0[1],xmm5[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm0[1]
; SSE2-NEXT: addss %xmm4, %xmm5 ; SSE2-NEXT: addss %xmm4, %xmm5
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: addss %xmm5, %xmm0 ; SSE2-NEXT: addss %xmm5, %xmm0
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm4 ; SSE2-NEXT: movaps %xmm1, %xmm4
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm1[1,1]
; SSE2-NEXT: addss %xmm4, %xmm0 ; SSE2-NEXT: addss %xmm4, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm4 ; SSE2-NEXT: xorps %xmm4, %xmm4
; SSE2-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm4 = xmm1[1],xmm4[1]
; SSE2-NEXT: addss %xmm4, %xmm0 ; SSE2-NEXT: addss %xmm4, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: addss %xmm3, %xmm0 ; SSE2-NEXT: addss %xmm3, %xmm0
; SSE2-NEXT: movaps %xmm3, %xmm1 ; SSE2-NEXT: movaps %xmm3, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm3[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm3[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm3, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSE2-NEXT: addss %xmm3, %xmm0 ; SSE2-NEXT: addss %xmm3, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32_zero: ; SSE41-LABEL: test_v16f32_zero:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
; SSE41-NEXT: addss %xmm0, %xmm4 ; SSE41-NEXT: addss %xmm0, %xmm4
; SSE41-NEXT: movaps %xmm0, %xmm5 ; SSE41-NEXT: movhlps {{.*#+}} xmm5 = xmm0[1],xmm5[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm0[1]
; SSE41-NEXT: addss %xmm4, %xmm5 ; SSE41-NEXT: addss %xmm4, %xmm5
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE41-NEXT: addss %xmm5, %xmm0 ; SSE41-NEXT: addss %xmm5, %xmm0
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm1[1,1,3,3]
; SSE41-NEXT: addss %xmm4, %xmm0 ; SSE41-NEXT: addss %xmm4, %xmm0
; SSE41-NEXT: movaps %xmm1, %xmm4 ; SSE41-NEXT: xorps %xmm4, %xmm4
; SSE41-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm4 = xmm1[1],xmm4[1]
; SSE41-NEXT: addss %xmm4, %xmm0 ; SSE41-NEXT: addss %xmm4, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: addss %xmm2, %xmm0 ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm2, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE41-NEXT: addss %xmm2, %xmm0 ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: addss %xmm3, %xmm0 ; SSE41-NEXT: addss %xmm3, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm3[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm3[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm3, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSE41-NEXT: addss %xmm3, %xmm0 ; SSE41-NEXT: addss %xmm3, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v16f32_zero: ; AVX1-SLOW-LABEL: test_v16f32_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3] ; AVX1-SLOW-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 166 Lines • ▼ Show 20 Lines
} }
define float @test_v4f32_undef(<4 x float> %a0) { define float @test_v4f32_undef(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32_undef: ; SSE2-LABEL: test_v4f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE2-NEXT: addss %xmm1, %xmm2 ; SSE2-NEXT: addss %xmm1, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32_undef: ; SSE41-LABEL: test_v4f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE41-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: movaps %xmm0, %xmm2 ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE41-NEXT: addss %xmm1, %xmm2 ; SSE41-NEXT: addss %xmm1, %xmm2
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE41-NEXT: addss %xmm2, %xmm0 ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v4f32_undef: ; AVX-LABEL: test_v4f32_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
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} }
define float @test_v8f32_undef(<8 x float> %a0) { define float @test_v8f32_undef(<8 x float> %a0) {
; SSE2-LABEL: test_v8f32_undef: ; SSE2-LABEL: test_v8f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1]
; SSE2-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 ; SSE2-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: movaps %xmm0, %xmm3 ; SSE2-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; SSE2-NEXT: addss %xmm2, %xmm3 ; SSE2-NEXT: addss %xmm2, %xmm3
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: addss %xmm3, %xmm0 ; SSE2-NEXT: addss %xmm3, %xmm0
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: movaps %xmm1, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1]
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32_undef: ; SSE41-LABEL: test_v8f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
; SSE41-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 ; SSE41-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: movaps %xmm0, %xmm3 ; SSE41-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; SSE41-NEXT: addss %xmm2, %xmm3 ; SSE41-NEXT: addss %xmm2, %xmm3
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE41-NEXT: addss %xmm3, %xmm0 ; SSE41-NEXT: addss %xmm3, %xmm0
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3]
; SSE41-NEXT: addss %xmm2, %xmm0 ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: movaps %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: addss %xmm2, %xmm0 ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v8f32_undef: ; AVX-LABEL: test_v8f32_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
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} }
define float @test_v16f32_undef(<16 x float> %a0) { define float @test_v16f32_undef(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32_undef: ; SSE2-LABEL: test_v16f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm4 ; SSE2-NEXT: movaps %xmm0, %xmm4
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[1,1]
; SSE2-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4 ; SSE2-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NEXT: movaps %xmm0, %xmm5 ; SSE2-NEXT: movhlps {{.*#+}} xmm5 = xmm0[1],xmm5[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm0[1]
; SSE2-NEXT: addss %xmm4, %xmm5 ; SSE2-NEXT: addss %xmm4, %xmm5
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: addss %xmm5, %xmm0 ; SSE2-NEXT: addss %xmm5, %xmm0
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm4 ; SSE2-NEXT: movaps %xmm1, %xmm4
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm1[1,1]
; SSE2-NEXT: addss %xmm4, %xmm0 ; SSE2-NEXT: addss %xmm4, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm4 ; SSE2-NEXT: xorps %xmm4, %xmm4
; SSE2-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm4 = xmm1[1],xmm4[1]
; SSE2-NEXT: addss %xmm4, %xmm0 ; SSE2-NEXT: addss %xmm4, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: addss %xmm3, %xmm0 ; SSE2-NEXT: addss %xmm3, %xmm0
; SSE2-NEXT: movaps %xmm3, %xmm1 ; SSE2-NEXT: movaps %xmm3, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm3[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm3[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm3, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSE2-NEXT: addss %xmm3, %xmm0 ; SSE2-NEXT: addss %xmm3, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32_undef: ; SSE41-LABEL: test_v16f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
; SSE41-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4 ; SSE41-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE41-NEXT: movaps %xmm0, %xmm5 ; SSE41-NEXT: movhlps {{.*#+}} xmm5 = xmm0[1],xmm5[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm0[1]
; SSE41-NEXT: addss %xmm4, %xmm5 ; SSE41-NEXT: addss %xmm4, %xmm5
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE41-NEXT: addss %xmm5, %xmm0 ; SSE41-NEXT: addss %xmm5, %xmm0
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm1[1,1,3,3]
; SSE41-NEXT: addss %xmm4, %xmm0 ; SSE41-NEXT: addss %xmm4, %xmm0
; SSE41-NEXT: movaps %xmm1, %xmm4 ; SSE41-NEXT: xorps %xmm4, %xmm4
; SSE41-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm4 = xmm1[1],xmm4[1]
; SSE41-NEXT: addss %xmm4, %xmm0 ; SSE41-NEXT: addss %xmm4, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: addss %xmm2, %xmm0 ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm2, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE41-NEXT: addss %xmm2, %xmm0 ; SSE41-NEXT: addss %xmm2, %xmm0
; SSE41-NEXT: addss %xmm3, %xmm0 ; SSE41-NEXT: addss %xmm3, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm3[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm3[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm3, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSE41-NEXT: addss %xmm3, %xmm0 ; SSE41-NEXT: addss %xmm3, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v16f32_undef: ; AVX-LABEL: test_v16f32_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
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define double @test_v4f64(double %a0, <4 x double> %a1) { define double @test_v4f64(double %a0, <4 x double> %a1) {
; SSE-LABEL: test_v4f64: ; SSE-LABEL: test_v4f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: addsd %xmm2, %xmm0 ; SSE-NEXT: addsd %xmm2, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: addsd %xmm2, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v4f64: ; AVX-LABEL: test_v4f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm1[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm1[1,0]
; AVX-NEXT: vaddsd %xmm2, %xmm0, %xmm0 ; AVX-NEXT: vaddsd %xmm2, %xmm0, %xmm0
; AVX-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm1, %xmm1
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define double @test_v8f64(double %a0, <8 x double> %a1) { define double @test_v8f64(double %a0, <8 x double> %a1) {
; SSE-LABEL: test_v8f64: ; SSE-LABEL: test_v8f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: addsd %xmm2, %xmm0 ; SSE-NEXT: addsd %xmm2, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: addsd %xmm2, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE-NEXT: addsd %xmm3, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-NEXT: addsd %xmm3, %xmm0 ; SSE-NEXT: addsd %xmm3, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: addsd %xmm4, %xmm0 ; SSE-NEXT: addsd %xmm4, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: addsd %xmm4, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm4[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v8f64: ; AVX-LABEL: test_v8f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpermilpd {{.*#+}} xmm3 = xmm1[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm3 = xmm1[1,0]
; AVX-NEXT: vaddsd %xmm3, %xmm0, %xmm0 ; AVX-NEXT: vaddsd %xmm3, %xmm0, %xmm0
; AVX-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm1, %xmm1
Show All 36 Lines
define double @test_v16f64(double %a0, <16 x double> %a1) { define double @test_v16f64(double %a0, <16 x double> %a1) {
; SSE2-LABEL: test_v16f64: ; SSE2-LABEL: test_v16f64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm8 ; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm8
; SSE2-NEXT: addsd %xmm1, %xmm0 ; SSE2-NEXT: addsd %xmm1, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE2-NEXT: addsd %xmm1, %xmm0 ; SSE2-NEXT: addsd %xmm1, %xmm0
; SSE2-NEXT: addsd %xmm2, %xmm0 ; SSE2-NEXT: addsd %xmm2, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: addsd %xmm2, %xmm0 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE2-NEXT: addsd %xmm3, %xmm0 ; SSE2-NEXT: addsd %xmm1, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE2-NEXT: addsd %xmm3, %xmm0 ; SSE2-NEXT: addsd %xmm3, %xmm0
; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE2-NEXT: addsd %xmm1, %xmm0
; SSE2-NEXT: addsd %xmm4, %xmm0 ; SSE2-NEXT: addsd %xmm4, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1] ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: addsd %xmm4, %xmm0 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm4[1],xmm1[1]
; SSE2-NEXT: addsd %xmm5, %xmm0 ; SSE2-NEXT: addsd %xmm1, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1,1]
; SSE2-NEXT: addsd %xmm5, %xmm0 ; SSE2-NEXT: addsd %xmm5, %xmm0
; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm5[1],xmm1[1]
; SSE2-NEXT: addsd %xmm1, %xmm0
; SSE2-NEXT: addsd %xmm6, %xmm0 ; SSE2-NEXT: addsd %xmm6, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1,1] ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: addsd %xmm6, %xmm0 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm6[1],xmm1[1]
; SSE2-NEXT: addsd %xmm7, %xmm0 ; SSE2-NEXT: addsd %xmm1, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm7 = xmm7[1,1]
; SSE2-NEXT: addsd %xmm7, %xmm0 ; SSE2-NEXT: addsd %xmm7, %xmm0
; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm7[1],xmm1[1]
; SSE2-NEXT: addsd %xmm1, %xmm0
; SSE2-NEXT: addsd %xmm8, %xmm0 ; SSE2-NEXT: addsd %xmm8, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm8 = xmm8[1,1] ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: addsd %xmm8, %xmm0 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm8[1],xmm1[1]
; SSE2-NEXT: addsd %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f64: ; SSE41-LABEL: test_v16f64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: addsd %xmm1, %xmm0 ; SSE41-NEXT: addsd %xmm1, %xmm0
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE41-NEXT: addsd %xmm1, %xmm0 ; SSE41-NEXT: addsd %xmm1, %xmm0
; SSE41-NEXT: addsd %xmm2, %xmm0 ; SSE41-NEXT: addsd %xmm2, %xmm0
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: addsd %xmm2, %xmm0 ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE41-NEXT: addsd %xmm3, %xmm0 ; SSE41-NEXT: addsd %xmm1, %xmm0
; SSE41-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE41-NEXT: addsd %xmm3, %xmm0 ; SSE41-NEXT: addsd %xmm3, %xmm0
; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE41-NEXT: addsd %xmm1, %xmm0
; SSE41-NEXT: addsd %xmm4, %xmm0 ; SSE41-NEXT: addsd %xmm4, %xmm0
; SSE41-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1] ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: addsd %xmm4, %xmm0 ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm4[1],xmm1[1]
; SSE41-NEXT: addsd %xmm5, %xmm0 ; SSE41-NEXT: addsd %xmm1, %xmm0
; SSE41-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1,1]
; SSE41-NEXT: addsd %xmm5, %xmm0 ; SSE41-NEXT: addsd %xmm5, %xmm0
; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm5[1],xmm1[1]
; SSE41-NEXT: addsd %xmm1, %xmm0
; SSE41-NEXT: addsd %xmm6, %xmm0 ; SSE41-NEXT: addsd %xmm6, %xmm0
; SSE41-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1,1] ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: addsd %xmm6, %xmm0 ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm6[1],xmm1[1]
; SSE41-NEXT: addsd %xmm7, %xmm0 ; SSE41-NEXT: addsd %xmm1, %xmm0
; SSE41-NEXT: unpckhpd {{.*#+}} xmm7 = xmm7[1,1]
; SSE41-NEXT: addsd %xmm7, %xmm0 ; SSE41-NEXT: addsd %xmm7, %xmm0
; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm7[1],xmm1[1]
; SSE41-NEXT: addsd %xmm1, %xmm0
; SSE41-NEXT: addsd {{[0-9]+}}(%rsp), %xmm0 ; SSE41-NEXT: addsd {{[0-9]+}}(%rsp), %xmm0
; SSE41-NEXT: addsd {{[0-9]+}}(%rsp), %xmm0 ; SSE41-NEXT: addsd {{[0-9]+}}(%rsp), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v16f64: ; AVX-LABEL: test_v16f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpermilpd {{.*#+}} xmm5 = xmm1[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm5 = xmm1[1,0]
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; ;
; vXf64 (zero) ; vXf64 (zero)
; ;
define double @test_v2f64_zero(<2 x double> %a0) { define double @test_v2f64_zero(<2 x double> %a0) {
; SSE-LABEL: test_v2f64_zero: ; SSE-LABEL: test_v2f64_zero:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v2f64_zero: ; AVX1-SLOW-LABEL: test_v2f64_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX1-SLOW-NEXT: vaddsd %xmm1, %xmm0, %xmm0 ; AVX1-SLOW-NEXT: vaddsd %xmm1, %xmm0, %xmm0
; AVX1-SLOW-NEXT: retq ; AVX1-SLOW-NEXT: retq
Show All 16 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call double @llvm.vector.reduce.fadd.f64.v2f64(double -0.0, <2 x double> %a0) %1 = call double @llvm.vector.reduce.fadd.f64.v2f64(double -0.0, <2 x double> %a0)
ret double %1 ret double %1
} }
define double @test_v4f64_zero(<4 x double> %a0) { define double @test_v4f64_zero(<4 x double> %a0) {
; SSE-LABEL: test_v4f64_zero: ; SSE-LABEL: test_v4f64_zero:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm2 ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE-NEXT: addsd %xmm2, %xmm0 ; SSE-NEXT: addsd %xmm2, %xmm0
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v4f64_zero: ; AVX1-SLOW-LABEL: test_v4f64_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
Show All 39 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call double @llvm.vector.reduce.fadd.f64.v4f64(double -0.0, <4 x double> %a0) %1 = call double @llvm.vector.reduce.fadd.f64.v4f64(double -0.0, <4 x double> %a0)
ret double %1 ret double %1
} }
define double @test_v8f64_zero(<8 x double> %a0) { define double @test_v8f64_zero(<8 x double> %a0) {
; SSE-LABEL: test_v8f64_zero: ; SSE-LABEL: test_v8f64_zero:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm4 ; SSE-NEXT: movhlps {{.*#+}} xmm4 = xmm0[1],xmm4[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1]
; SSE-NEXT: addsd %xmm4, %xmm0 ; SSE-NEXT: addsd %xmm4, %xmm0
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: addsd %xmm2, %xmm0 ; SSE-NEXT: addsd %xmm2, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: addsd %xmm2, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE-NEXT: addsd %xmm3, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-NEXT: addsd %xmm3, %xmm0 ; SSE-NEXT: addsd %xmm3, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v8f64_zero: ; AVX1-SLOW-LABEL: test_v8f64_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0] ; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX1-SLOW-NEXT: vaddsd %xmm2, %xmm0, %xmm2 ; AVX1-SLOW-NEXT: vaddsd %xmm2, %xmm0, %xmm2
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-SLOW-NEXT: vaddsd %xmm0, %xmm2, %xmm2 ; AVX1-SLOW-NEXT: vaddsd %xmm0, %xmm2, %xmm2
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call double @llvm.vector.reduce.fadd.f64.v8f64(double -0.0, <8 x double> %a0) %1 = call double @llvm.vector.reduce.fadd.f64.v8f64(double -0.0, <8 x double> %a0)
ret double %1 ret double %1
} }
define double @test_v16f64_zero(<16 x double> %a0) { define double @test_v16f64_zero(<16 x double> %a0) {
; SSE-LABEL: test_v16f64_zero: ; SSE-LABEL: test_v16f64_zero:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm8 ; SSE-NEXT: movhlps {{.*#+}} xmm8 = xmm0[1],xmm8[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm8 = xmm8[1],xmm0[1]
; SSE-NEXT: addsd %xmm8, %xmm0 ; SSE-NEXT: addsd %xmm8, %xmm0
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: addsd %xmm2, %xmm0 ; SSE-NEXT: addsd %xmm2, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: addsd %xmm2, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE-NEXT: addsd %xmm3, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-NEXT: addsd %xmm3, %xmm0 ; SSE-NEXT: addsd %xmm3, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: addsd %xmm4, %xmm0 ; SSE-NEXT: addsd %xmm4, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: addsd %xmm4, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm4[1],xmm1[1]
; SSE-NEXT: addsd %xmm5, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1,1]
; SSE-NEXT: addsd %xmm5, %xmm0 ; SSE-NEXT: addsd %xmm5, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm5[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: addsd %xmm6, %xmm0 ; SSE-NEXT: addsd %xmm6, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: addsd %xmm6, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm6[1],xmm1[1]
; SSE-NEXT: addsd %xmm7, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm7 = xmm7[1,1]
; SSE-NEXT: addsd %xmm7, %xmm0 ; SSE-NEXT: addsd %xmm7, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm7[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v16f64_zero: ; AVX1-SLOW-LABEL: test_v16f64_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm4 = xmm0[1,0] ; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm4 = xmm0[1,0]
; AVX1-SLOW-NEXT: vaddsd %xmm4, %xmm0, %xmm4 ; AVX1-SLOW-NEXT: vaddsd %xmm4, %xmm0, %xmm4
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-SLOW-NEXT: vaddsd %xmm0, %xmm4, %xmm4 ; AVX1-SLOW-NEXT: vaddsd %xmm0, %xmm4, %xmm4
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; SSE-LABEL: test_v8f64_undef: ; SSE-LABEL: test_v8f64_undef:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: addsd %xmm2, %xmm0 ; SSE-NEXT: addsd %xmm2, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: addsd %xmm2, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE-NEXT: addsd %xmm3, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-NEXT: addsd %xmm3, %xmm0 ; SSE-NEXT: addsd %xmm3, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v8f64_undef: ; AVX-LABEL: test_v8f64_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 ; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX-NEXT: vaddsd %xmm0, %xmm2, %xmm2 ; AVX-NEXT: vaddsd %xmm0, %xmm2, %xmm2
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; SSE-LABEL: test_v16f64_undef: ; SSE-LABEL: test_v16f64_undef:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: addsd %xmm2, %xmm0 ; SSE-NEXT: addsd %xmm2, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: addsd %xmm2, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE-NEXT: addsd %xmm3, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-NEXT: addsd %xmm3, %xmm0 ; SSE-NEXT: addsd %xmm3, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: addsd %xmm4, %xmm0 ; SSE-NEXT: addsd %xmm4, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: addsd %xmm4, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm4[1],xmm1[1]
; SSE-NEXT: addsd %xmm5, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1,1]
; SSE-NEXT: addsd %xmm5, %xmm0 ; SSE-NEXT: addsd %xmm5, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm5[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: addsd %xmm6, %xmm0 ; SSE-NEXT: addsd %xmm6, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: addsd %xmm6, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm6[1],xmm1[1]
; SSE-NEXT: addsd %xmm7, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm7 = xmm7[1,1]
; SSE-NEXT: addsd %xmm7, %xmm0 ; SSE-NEXT: addsd %xmm7, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm7[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v16f64_undef: ; AVX-LABEL: test_v16f64_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm4 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm4 = xmm0[1,0]
; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4 ; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX-NEXT: vaddsd %xmm0, %xmm4, %xmm4 ; AVX-NEXT: vaddsd %xmm0, %xmm4, %xmm4
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llvm/test/CodeGen/X86/vector-reduce-fmax-fmin-fast.ll

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; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call fast float @llvm.vector.reduce.fmin.v2f32(<2 x float> %a0) %1 = call fast float @llvm.vector.reduce.fmin.v2f32(<2 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v4f32(<4 x float> %a0) { define float @test_v4f32(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32: ; SSE2-LABEL: test_v4f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: maxps %xmm1, %xmm0 ; SSE2-NEXT: maxps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: maxss %xmm1, %xmm0 ; SSE2-NEXT: maxss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32: ; SSE41-LABEL: test_v4f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: maxps %xmm1, %xmm0 ; SSE41-NEXT: maxps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: maxss %xmm1, %xmm0 ; SSE41-NEXT: maxss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v4f32: ; AVX-LABEL: test_v4f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
Show All 12 Lines; AVX512-NEXT: retq
%1 = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a0) %1 = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v8f32(<8 x float> %a0) { define float @test_v8f32(<8 x float> %a0) {
; SSE2-LABEL: test_v8f32: ; SSE2-LABEL: test_v8f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: minps %xmm1, %xmm0 ; SSE2-NEXT: minps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: minps %xmm1, %xmm0 ; SSE2-NEXT: minps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: minss %xmm1, %xmm0 ; SSE2-NEXT: minss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32: ; SSE41-LABEL: test_v8f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: minps %xmm1, %xmm0 ; SSE41-NEXT: minps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: minps %xmm1, %xmm0 ; SSE41-NEXT: minps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: minss %xmm1, %xmm0 ; SSE41-NEXT: minss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v8f32: ; AVX-LABEL: test_v8f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
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} }
define float @test_v16f32(<16 x float> %a0) { define float @test_v16f32(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32: ; SSE2-LABEL: test_v16f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: maxps %xmm3, %xmm1 ; SSE2-NEXT: maxps %xmm3, %xmm1
; SSE2-NEXT: maxps %xmm2, %xmm0 ; SSE2-NEXT: maxps %xmm2, %xmm0
; SSE2-NEXT: maxps %xmm1, %xmm0 ; SSE2-NEXT: maxps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: maxps %xmm1, %xmm0 ; SSE2-NEXT: maxps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: maxss %xmm1, %xmm0 ; SSE2-NEXT: maxss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32: ; SSE41-LABEL: test_v16f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: maxps %xmm3, %xmm1 ; SSE41-NEXT: maxps %xmm3, %xmm1
; SSE41-NEXT: maxps %xmm2, %xmm0 ; SSE41-NEXT: maxps %xmm2, %xmm0
; SSE41-NEXT: maxps %xmm1, %xmm0 ; SSE41-NEXT: maxps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: maxps %xmm1, %xmm0 ; SSE41-NEXT: maxps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: maxss %xmm1, %xmm0 ; SSE41-NEXT: maxss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v16f32: ; AVX-LABEL: test_v16f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmaxps %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmaxps %ymm1, %ymm0, %ymm0
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; ;
; vXf64 ; vXf64
; ;
define double @test_v2f64(<2 x double> %a0) { define double @test_v2f64(<2 x double> %a0) {
; SSE-LABEL: test_v2f64: ; SSE-LABEL: test_v2f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE-NEXT: minsd %xmm1, %xmm0 ; SSE-NEXT: minsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v2f64: ; AVX-LABEL: test_v2f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vminsd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vminsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; AVX512-LABEL: test_v2f64: ; AVX512-LABEL: test_v2f64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX512-NEXT: vminsd %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vminsd %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call fast double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a0) %1 = call fast double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a0)
ret double %1 ret double %1
} }
define double @test_v4f64(<4 x double> %a0) { define double @test_v4f64(<4 x double> %a0) {
; SSE-LABEL: test_v4f64: ; SSE-LABEL: test_v4f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: maxpd %xmm1, %xmm0 ; SSE-NEXT: maxpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: maxsd %xmm1, %xmm0 ; SSE-NEXT: maxsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v4f64: ; AVX-LABEL: test_v4f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
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} }
define double @test_v8f64(<8 x double> %a0) { define double @test_v8f64(<8 x double> %a0) {
; SSE-LABEL: test_v8f64: ; SSE-LABEL: test_v8f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: minpd %xmm3, %xmm1 ; SSE-NEXT: minpd %xmm3, %xmm1
; SSE-NEXT: minpd %xmm2, %xmm0 ; SSE-NEXT: minpd %xmm2, %xmm0
; SSE-NEXT: minpd %xmm1, %xmm0 ; SSE-NEXT: minpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: minsd %xmm1, %xmm0 ; SSE-NEXT: minsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v8f64: ; AVX-LABEL: test_v8f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vminpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vminpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vminpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vminpd %xmm1, %xmm0, %xmm0
Show All 21 Lines
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: maxpd %xmm6, %xmm2 ; SSE-NEXT: maxpd %xmm6, %xmm2
; SSE-NEXT: maxpd %xmm4, %xmm0 ; SSE-NEXT: maxpd %xmm4, %xmm0
; SSE-NEXT: maxpd %xmm2, %xmm0 ; SSE-NEXT: maxpd %xmm2, %xmm0
; SSE-NEXT: maxpd %xmm7, %xmm3 ; SSE-NEXT: maxpd %xmm7, %xmm3
; SSE-NEXT: maxpd %xmm5, %xmm1 ; SSE-NEXT: maxpd %xmm5, %xmm1
; SSE-NEXT: maxpd %xmm3, %xmm1 ; SSE-NEXT: maxpd %xmm3, %xmm1
; SSE-NEXT: maxpd %xmm1, %xmm0 ; SSE-NEXT: maxpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: maxsd %xmm1, %xmm0 ; SSE-NEXT: maxsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v16f64: ; AVX-LABEL: test_v16f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmaxpd %ymm3, %ymm1, %ymm1 ; AVX-NEXT: vmaxpd %ymm3, %ymm1, %ymm1
; AVX-NEXT: vmaxpd %ymm2, %ymm0, %ymm0 ; AVX-NEXT: vmaxpd %ymm2, %ymm0, %ymm0
; AVX-NEXT: vmaxpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmaxpd %ymm1, %ymm0, %ymm0
Show All 31 Lines

llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call nnan float @llvm.vector.reduce.fmax.v2f32(<2 x float> %a0) %1 = call nnan float @llvm.vector.reduce.fmax.v2f32(<2 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v4f32(<4 x float> %a0) { define float @test_v4f32(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32: ; SSE2-LABEL: test_v4f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: maxps %xmm1, %xmm0 ; SSE2-NEXT: maxps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: maxss %xmm1, %xmm0 ; SSE2-NEXT: maxss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32: ; SSE41-LABEL: test_v4f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: maxps %xmm1, %xmm0 ; SSE41-NEXT: maxps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: maxss %xmm1, %xmm0 ; SSE41-NEXT: maxss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v4f32: ; AVX-LABEL: test_v4f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
Show All 12 Lines; AVX512-NEXT: retq
%1 = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a0) %1 = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v8f32(<8 x float> %a0) { define float @test_v8f32(<8 x float> %a0) {
; SSE2-LABEL: test_v8f32: ; SSE2-LABEL: test_v8f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: maxps %xmm1, %xmm0 ; SSE2-NEXT: maxps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: maxps %xmm1, %xmm0 ; SSE2-NEXT: maxps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: maxss %xmm1, %xmm0 ; SSE2-NEXT: maxss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32: ; SSE41-LABEL: test_v8f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: maxps %xmm1, %xmm0 ; SSE41-NEXT: maxps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: maxps %xmm1, %xmm0 ; SSE41-NEXT: maxps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: maxss %xmm1, %xmm0 ; SSE41-NEXT: maxss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v8f32: ; AVX-LABEL: test_v8f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
Show All 20 Lines
} }
define float @test_v16f32(<16 x float> %a0) { define float @test_v16f32(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32: ; SSE2-LABEL: test_v16f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: maxps %xmm3, %xmm1 ; SSE2-NEXT: maxps %xmm3, %xmm1
; SSE2-NEXT: maxps %xmm2, %xmm0 ; SSE2-NEXT: maxps %xmm2, %xmm0
; SSE2-NEXT: maxps %xmm1, %xmm0 ; SSE2-NEXT: maxps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: maxps %xmm1, %xmm0 ; SSE2-NEXT: maxps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: maxss %xmm1, %xmm0 ; SSE2-NEXT: maxss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32: ; SSE41-LABEL: test_v16f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: maxps %xmm3, %xmm1 ; SSE41-NEXT: maxps %xmm3, %xmm1
; SSE41-NEXT: maxps %xmm2, %xmm0 ; SSE41-NEXT: maxps %xmm2, %xmm0
; SSE41-NEXT: maxps %xmm1, %xmm0 ; SSE41-NEXT: maxps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: maxps %xmm1, %xmm0 ; SSE41-NEXT: maxps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: maxss %xmm1, %xmm0 ; SSE41-NEXT: maxss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v16f32: ; AVX-LABEL: test_v16f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmaxps %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmaxps %ymm1, %ymm0, %ymm0
Show All 24 Lines
; ;
; vXf64 ; vXf64
; ;
define double @test_v2f64(<2 x double> %a0) { define double @test_v2f64(<2 x double> %a0) {
; SSE-LABEL: test_v2f64: ; SSE-LABEL: test_v2f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE-NEXT: maxsd %xmm1, %xmm0 ; SSE-NEXT: maxsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v2f64: ; AVX-LABEL: test_v2f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; AVX512-LABEL: test_v2f64: ; AVX512-LABEL: test_v2f64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call nnan double @llvm.vector.reduce.fmax.v2f64(<2 x double> %a0) %1 = call nnan double @llvm.vector.reduce.fmax.v2f64(<2 x double> %a0)
ret double %1 ret double %1
} }
define double @test_v3f64(<3 x double> %a0) { define double @test_v3f64(<3 x double> %a0) {
; SSE2-LABEL: test_v3f64: ; SSE2-LABEL: test_v3f64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: shufpd {{.*#+}} xmm2 = xmm2[0],mem[1] ; SSE2-NEXT: shufpd {{.*#+}} xmm2 = xmm2[0],mem[1]
; SSE2-NEXT: maxpd %xmm2, %xmm0 ; SSE2-NEXT: maxpd %xmm2, %xmm0
; SSE2-NEXT: movapd %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: maxsd %xmm1, %xmm0 ; SSE2-NEXT: maxsd %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v3f64: ; SSE41-LABEL: test_v3f64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE41-NEXT: blendpd {{.*#+}} xmm2 = xmm2[0],mem[1] ; SSE41-NEXT: blendpd {{.*#+}} xmm2 = xmm2[0],mem[1]
; SSE41-NEXT: maxpd %xmm2, %xmm0 ; SSE41-NEXT: maxpd %xmm2, %xmm0
; SSE41-NEXT: movapd %xmm0, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: maxsd %xmm1, %xmm0 ; SSE41-NEXT: maxsd %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v3f64: ; AVX-LABEL: test_v3f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm1 ; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
Show All 12 Lines; AVX512-NEXT: retq
%1 = call nnan double @llvm.vector.reduce.fmax.v3f64(<3 x double> %a0) %1 = call nnan double @llvm.vector.reduce.fmax.v3f64(<3 x double> %a0)
ret double %1 ret double %1
} }
define double @test_v4f64(<4 x double> %a0) { define double @test_v4f64(<4 x double> %a0) {
; SSE-LABEL: test_v4f64: ; SSE-LABEL: test_v4f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: maxpd %xmm1, %xmm0 ; SSE-NEXT: maxpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: maxsd %xmm1, %xmm0 ; SSE-NEXT: maxsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v4f64: ; AVX-LABEL: test_v4f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
Show All 14 Lines
} }
define double @test_v8f64(<8 x double> %a0) { define double @test_v8f64(<8 x double> %a0) {
; SSE-LABEL: test_v8f64: ; SSE-LABEL: test_v8f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: maxpd %xmm3, %xmm1 ; SSE-NEXT: maxpd %xmm3, %xmm1
; SSE-NEXT: maxpd %xmm2, %xmm0 ; SSE-NEXT: maxpd %xmm2, %xmm0
; SSE-NEXT: maxpd %xmm1, %xmm0 ; SSE-NEXT: maxpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: maxsd %xmm1, %xmm0 ; SSE-NEXT: maxsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v8f64: ; AVX-LABEL: test_v8f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmaxpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmaxpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm0
Show All 21 Lines
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: maxpd %xmm6, %xmm2 ; SSE-NEXT: maxpd %xmm6, %xmm2
; SSE-NEXT: maxpd %xmm4, %xmm0 ; SSE-NEXT: maxpd %xmm4, %xmm0
; SSE-NEXT: maxpd %xmm2, %xmm0 ; SSE-NEXT: maxpd %xmm2, %xmm0
; SSE-NEXT: maxpd %xmm7, %xmm3 ; SSE-NEXT: maxpd %xmm7, %xmm3
; SSE-NEXT: maxpd %xmm5, %xmm1 ; SSE-NEXT: maxpd %xmm5, %xmm1
; SSE-NEXT: maxpd %xmm3, %xmm1 ; SSE-NEXT: maxpd %xmm3, %xmm1
; SSE-NEXT: maxpd %xmm1, %xmm0 ; SSE-NEXT: maxpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: maxsd %xmm1, %xmm0 ; SSE-NEXT: maxsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v16f64: ; AVX-LABEL: test_v16f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmaxpd %ymm3, %ymm1, %ymm1 ; AVX-NEXT: vmaxpd %ymm3, %ymm1, %ymm1
; AVX-NEXT: vmaxpd %ymm2, %ymm0, %ymm0 ; AVX-NEXT: vmaxpd %ymm2, %ymm0, %ymm0
; AVX-NEXT: vmaxpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmaxpd %ymm1, %ymm0, %ymm0
▲ Show 20 Lines • Show All 114 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-reduce-fmax.ll

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a0) %1 = call float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v4f32(<4 x float> %a0) { define float @test_v4f32(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32: ; SSE2-LABEL: test_v4f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE2-NEXT: movaps %xmm0, %xmm3 ; SSE2-NEXT: movaps %xmm0, %xmm3
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm0[1,1]
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: cmpunordss %xmm0, %xmm1 ; SSE2-NEXT: cmpunordss %xmm0, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm4 ; SSE2-NEXT: movaps %xmm1, %xmm4
; SSE2-NEXT: andps %xmm3, %xmm4 ; SSE2-NEXT: andps %xmm3, %xmm4
; SSE2-NEXT: maxss %xmm0, %xmm3 ; SSE2-NEXT: maxss %xmm0, %xmm3
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; SSE2-NEXT: andnps %xmm3, %xmm1 ; SSE2-NEXT: andnps %xmm3, %xmm1
; SSE2-NEXT: orps %xmm4, %xmm1 ; SSE2-NEXT: orps %xmm4, %xmm1
; SSE2-NEXT: movaps %xmm2, %xmm3 ; SSE2-NEXT: movaps %xmm2, %xmm3
; SSE2-NEXT: maxss %xmm1, %xmm3 ; SSE2-NEXT: maxss %xmm1, %xmm3
; SSE2-NEXT: cmpunordss %xmm1, %xmm1 ; SSE2-NEXT: cmpunordss %xmm1, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm4 ; SSE2-NEXT: movaps %xmm1, %xmm4
; SSE2-NEXT: andnps %xmm3, %xmm4 ; SSE2-NEXT: andnps %xmm3, %xmm4
; SSE2-NEXT: andps %xmm2, %xmm1 ; SSE2-NEXT: andps %xmm2, %xmm1
; SSE2-NEXT: orps %xmm4, %xmm1 ; SSE2-NEXT: orps %xmm4, %xmm1
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: maxss %xmm1, %xmm2 ; SSE2-NEXT: maxss %xmm1, %xmm2
; SSE2-NEXT: cmpunordss %xmm1, %xmm1 ; SSE2-NEXT: cmpunordss %xmm1, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm3 ; SSE2-NEXT: movaps %xmm1, %xmm3
; SSE2-NEXT: andnps %xmm2, %xmm3 ; SSE2-NEXT: andnps %xmm2, %xmm3
; SSE2-NEXT: andps %xmm0, %xmm1 ; SSE2-NEXT: andps %xmm0, %xmm1
; SSE2-NEXT: orps %xmm3, %xmm1 ; SSE2-NEXT: orps %xmm3, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32: ; SSE41-LABEL: test_v4f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm0, %xmm2 ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE41-NEXT: movshdup {{.*#+}} xmm3 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movaps %xmm0, %xmm1
; SSE41-NEXT: cmpunordss %xmm0, %xmm1 ; SSE41-NEXT: cmpunordss %xmm0, %xmm1
; SSE41-NEXT: movaps %xmm1, %xmm4 ; SSE41-NEXT: movaps %xmm1, %xmm4
; SSE41-NEXT: andps %xmm3, %xmm4 ; SSE41-NEXT: andps %xmm3, %xmm4
; SSE41-NEXT: maxss %xmm0, %xmm3 ; SSE41-NEXT: maxss %xmm0, %xmm3
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; SSE41-NEXT: andnps %xmm3, %xmm1 ; SSE41-NEXT: andnps %xmm3, %xmm1
; SSE41-NEXT: orps %xmm4, %xmm1 ; SSE41-NEXT: orps %xmm4, %xmm1
; SSE41-NEXT: movaps %xmm2, %xmm3 ; SSE41-NEXT: movaps %xmm2, %xmm3
; SSE41-NEXT: maxss %xmm1, %xmm3 ; SSE41-NEXT: maxss %xmm1, %xmm3
; SSE41-NEXT: cmpunordss %xmm1, %xmm1 ; SSE41-NEXT: cmpunordss %xmm1, %xmm1
; SSE41-NEXT: movaps %xmm1, %xmm4 ; SSE41-NEXT: movaps %xmm1, %xmm4
; SSE41-NEXT: andnps %xmm3, %xmm4 ; SSE41-NEXT: andnps %xmm3, %xmm4
; SSE41-NEXT: andps %xmm2, %xmm1 ; SSE41-NEXT: andps %xmm2, %xmm1
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; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE41-NEXT: movaps %xmm2, %xmm0 ; SSE41-NEXT: movaps %xmm2, %xmm0
; SSE41-NEXT: cmpunordss %xmm2, %xmm0 ; SSE41-NEXT: cmpunordss %xmm2, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm3 ; SSE41-NEXT: movaps %xmm0, %xmm3
; SSE41-NEXT: andps %xmm1, %xmm3 ; SSE41-NEXT: andps %xmm1, %xmm3
; SSE41-NEXT: maxss %xmm2, %xmm1 ; SSE41-NEXT: maxss %xmm2, %xmm1
; SSE41-NEXT: andnps %xmm1, %xmm0 ; SSE41-NEXT: andnps %xmm1, %xmm0
; SSE41-NEXT: orps %xmm3, %xmm0 ; SSE41-NEXT: orps %xmm3, %xmm0
; SSE41-NEXT: movaps %xmm2, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE41-NEXT: movaps %xmm1, %xmm3 ; SSE41-NEXT: movaps %xmm1, %xmm3
; SSE41-NEXT: maxss %xmm0, %xmm3 ; SSE41-NEXT: maxss %xmm0, %xmm3
; SSE41-NEXT: cmpunordss %xmm0, %xmm0 ; SSE41-NEXT: cmpunordss %xmm0, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm4 ; SSE41-NEXT: movaps %xmm0, %xmm4
; SSE41-NEXT: andnps %xmm3, %xmm4 ; SSE41-NEXT: andnps %xmm3, %xmm4
; SSE41-NEXT: andps %xmm1, %xmm0 ; SSE41-NEXT: andps %xmm1, %xmm0
; SSE41-NEXT: orps %xmm4, %xmm0 ; SSE41-NEXT: orps %xmm4, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
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; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3]
; SSE41-NEXT: movaps %xmm1, %xmm0 ; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: cmpunordss %xmm1, %xmm0 ; SSE41-NEXT: cmpunordss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm3 ; SSE41-NEXT: movaps %xmm0, %xmm3
; SSE41-NEXT: andps %xmm2, %xmm3 ; SSE41-NEXT: andps %xmm2, %xmm3
; SSE41-NEXT: maxss %xmm1, %xmm2 ; SSE41-NEXT: maxss %xmm1, %xmm2
; SSE41-NEXT: andnps %xmm2, %xmm0 ; SSE41-NEXT: andnps %xmm2, %xmm0
; SSE41-NEXT: orps %xmm3, %xmm0 ; SSE41-NEXT: orps %xmm3, %xmm0
; SSE41-NEXT: movaps %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: movaps %xmm2, %xmm3 ; SSE41-NEXT: movaps %xmm2, %xmm3
; SSE41-NEXT: maxss %xmm0, %xmm3 ; SSE41-NEXT: maxss %xmm0, %xmm3
; SSE41-NEXT: cmpunordss %xmm0, %xmm0 ; SSE41-NEXT: cmpunordss %xmm0, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm4 ; SSE41-NEXT: movaps %xmm0, %xmm4
; SSE41-NEXT: andnps %xmm3, %xmm4 ; SSE41-NEXT: andnps %xmm3, %xmm4
; SSE41-NEXT: andps %xmm2, %xmm0 ; SSE41-NEXT: andps %xmm2, %xmm0
; SSE41-NEXT: orps %xmm4, %xmm0 ; SSE41-NEXT: orps %xmm4, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
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; ;
; vXf64 ; vXf64
; ;
define double @test_v2f64(<2 x double> %a0) { define double @test_v2f64(<2 x double> %a0) {
; SSE-LABEL: test_v2f64: ; SSE-LABEL: test_v2f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm2 ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1] ; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: movapd %xmm0, %xmm1
; SSE-NEXT: cmpunordsd %xmm0, %xmm1 ; SSE-NEXT: cmpunordsd %xmm0, %xmm1
; SSE-NEXT: movapd %xmm1, %xmm3 ; SSE-NEXT: movapd %xmm1, %xmm3
; SSE-NEXT: andpd %xmm2, %xmm3 ; SSE-NEXT: andpd %xmm2, %xmm3
; SSE-NEXT: maxsd %xmm0, %xmm2 ; SSE-NEXT: maxsd %xmm0, %xmm2
; SSE-NEXT: andnpd %xmm2, %xmm1 ; SSE-NEXT: andnpd %xmm2, %xmm1
; SSE-NEXT: orpd %xmm3, %xmm1 ; SSE-NEXT: orpd %xmm3, %xmm1
; SSE-NEXT: movapd %xmm1, %xmm0 ; SSE-NEXT: movapd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
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; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f64: ; SSE41-LABEL: test_v4f64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movapd %xmm1, %xmm2 ; SSE41-NEXT: movapd %xmm1, %xmm2
; SSE41-NEXT: maxpd %xmm0, %xmm2 ; SSE41-NEXT: maxpd %xmm0, %xmm2
; SSE41-NEXT: cmpunordpd %xmm0, %xmm0 ; SSE41-NEXT: cmpunordpd %xmm0, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2 ; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; SSE41-NEXT: movapd %xmm2, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE41-NEXT: movapd %xmm2, %xmm0 ; SSE41-NEXT: movapd %xmm2, %xmm0
; SSE41-NEXT: cmpunordsd %xmm2, %xmm0 ; SSE41-NEXT: cmpunordsd %xmm2, %xmm0
; SSE41-NEXT: movapd %xmm0, %xmm3 ; SSE41-NEXT: movapd %xmm0, %xmm3
; SSE41-NEXT: andpd %xmm1, %xmm3 ; SSE41-NEXT: andpd %xmm1, %xmm3
; SSE41-NEXT: maxsd %xmm2, %xmm1 ; SSE41-NEXT: maxsd %xmm2, %xmm1
; SSE41-NEXT: andnpd %xmm1, %xmm0 ; SSE41-NEXT: andnpd %xmm1, %xmm0
; SSE41-NEXT: orpd %xmm3, %xmm0 ; SSE41-NEXT: orpd %xmm3, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
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; SSE41-NEXT: cmpunordpd %xmm1, %xmm1 ; SSE41-NEXT: cmpunordpd %xmm1, %xmm1
; SSE41-NEXT: movapd %xmm1, %xmm0 ; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm2 ; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movapd %xmm2, %xmm1 ; SSE41-NEXT: movapd %xmm2, %xmm1
; SSE41-NEXT: maxpd %xmm4, %xmm1 ; SSE41-NEXT: maxpd %xmm4, %xmm1
; SSE41-NEXT: cmpunordpd %xmm4, %xmm4 ; SSE41-NEXT: cmpunordpd %xmm4, %xmm4
; SSE41-NEXT: movapd %xmm4, %xmm0 ; SSE41-NEXT: movapd %xmm4, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1 ; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movapd %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: movapd %xmm1, %xmm0 ; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: cmpunordsd %xmm1, %xmm0 ; SSE41-NEXT: cmpunordsd %xmm1, %xmm0
; SSE41-NEXT: movapd %xmm0, %xmm3 ; SSE41-NEXT: movapd %xmm0, %xmm3
; SSE41-NEXT: andpd %xmm2, %xmm3 ; SSE41-NEXT: andpd %xmm2, %xmm3
; SSE41-NEXT: maxsd %xmm1, %xmm2 ; SSE41-NEXT: maxsd %xmm1, %xmm2
; SSE41-NEXT: andnpd %xmm2, %xmm0 ; SSE41-NEXT: andnpd %xmm2, %xmm0
; SSE41-NEXT: orpd %xmm3, %xmm0 ; SSE41-NEXT: orpd %xmm3, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
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; SSE41-NEXT: cmpunordpd %xmm3, %xmm3 ; SSE41-NEXT: cmpunordpd %xmm3, %xmm3
; SSE41-NEXT: movapd %xmm3, %xmm0 ; SSE41-NEXT: movapd %xmm3, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm4 ; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm4
; SSE41-NEXT: movapd %xmm4, %xmm1 ; SSE41-NEXT: movapd %xmm4, %xmm1
; SSE41-NEXT: maxpd %xmm2, %xmm1 ; SSE41-NEXT: maxpd %xmm2, %xmm1
; SSE41-NEXT: cmpunordpd %xmm2, %xmm2 ; SSE41-NEXT: cmpunordpd %xmm2, %xmm2
; SSE41-NEXT: movapd %xmm2, %xmm0 ; SSE41-NEXT: movapd %xmm2, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm1 ; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm1
; SSE41-NEXT: movapd %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: movapd %xmm1, %xmm0 ; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: cmpunordsd %xmm1, %xmm0 ; SSE41-NEXT: cmpunordsd %xmm1, %xmm0
; SSE41-NEXT: movapd %xmm0, %xmm3 ; SSE41-NEXT: movapd %xmm0, %xmm3
; SSE41-NEXT: andpd %xmm2, %xmm3 ; SSE41-NEXT: andpd %xmm2, %xmm3
; SSE41-NEXT: maxsd %xmm1, %xmm2 ; SSE41-NEXT: maxsd %xmm1, %xmm2
; SSE41-NEXT: andnpd %xmm2, %xmm0 ; SSE41-NEXT: andnpd %xmm2, %xmm0
; SSE41-NEXT: orpd %xmm3, %xmm0 ; SSE41-NEXT: orpd %xmm3, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
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llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call nnan float @llvm.vector.reduce.fmin.v2f32(<2 x float> %a0) %1 = call nnan float @llvm.vector.reduce.fmin.v2f32(<2 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v3f32(<3 x float> %a0) { define float @test_v3f32(<3 x float> %a0) {
; SSE2-LABEL: test_v3f32: ; SSE2-LABEL: test_v3f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1]
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: minss %xmm2, %xmm1 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE2-NEXT: minss %xmm0, %xmm1 ; SSE2-NEXT: minss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: minss %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v3f32: ; SSE41-LABEL: test_v3f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE41-NEXT: minss %xmm2, %xmm1 ; SSE41-NEXT: minss %xmm1, %xmm0
; SSE41-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE41-NEXT: minss %xmm2, %xmm0
; SSE41-NEXT: minss %xmm0, %xmm1
; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v3f32: ; AVX-LABEL: test_v3f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX-NEXT: vminss %xmm1, %xmm0, %xmm1 ; AVX-NEXT: vminss %xmm1, %xmm0, %xmm1
; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX-NEXT: vminss %xmm0, %xmm1, %xmm0 ; AVX-NEXT: vminss %xmm0, %xmm1, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; AVX512-LABEL: test_v3f32: ; AVX512-LABEL: test_v3f32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX512-NEXT: vminss %xmm1, %xmm0, %xmm1 ; AVX512-NEXT: vminss %xmm1, %xmm0, %xmm1
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512-NEXT: vminss %xmm0, %xmm1, %xmm0 ; AVX512-NEXT: vminss %xmm0, %xmm1, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call nnan float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a0) %1 = call nnan float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v4f32(<4 x float> %a0) { define float @test_v4f32(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32: ; SSE2-LABEL: test_v4f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: minps %xmm1, %xmm0 ; SSE2-NEXT: minps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: minss %xmm1, %xmm0 ; SSE2-NEXT: minss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32: ; SSE41-LABEL: test_v4f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: minps %xmm1, %xmm0 ; SSE41-NEXT: minps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: minss %xmm1, %xmm0 ; SSE41-NEXT: minss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v4f32: ; AVX-LABEL: test_v4f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
Show All 12 Lines; AVX512-NEXT: retq
%1 = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a0) %1 = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v8f32(<8 x float> %a0) { define float @test_v8f32(<8 x float> %a0) {
; SSE2-LABEL: test_v8f32: ; SSE2-LABEL: test_v8f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: minps %xmm1, %xmm0 ; SSE2-NEXT: minps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: minps %xmm1, %xmm0 ; SSE2-NEXT: minps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: minss %xmm1, %xmm0 ; SSE2-NEXT: minss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32: ; SSE41-LABEL: test_v8f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: minps %xmm1, %xmm0 ; SSE41-NEXT: minps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: minps %xmm1, %xmm0 ; SSE41-NEXT: minps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: minss %xmm1, %xmm0 ; SSE41-NEXT: minss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v8f32: ; AVX-LABEL: test_v8f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
Show All 20 Lines
} }
define float @test_v16f32(<16 x float> %a0) { define float @test_v16f32(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32: ; SSE2-LABEL: test_v16f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: minps %xmm3, %xmm1 ; SSE2-NEXT: minps %xmm3, %xmm1
; SSE2-NEXT: minps %xmm2, %xmm0 ; SSE2-NEXT: minps %xmm2, %xmm0
; SSE2-NEXT: minps %xmm1, %xmm0 ; SSE2-NEXT: minps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: minps %xmm1, %xmm0 ; SSE2-NEXT: minps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: minss %xmm1, %xmm0 ; SSE2-NEXT: minss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32: ; SSE41-LABEL: test_v16f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: minps %xmm3, %xmm1 ; SSE41-NEXT: minps %xmm3, %xmm1
; SSE41-NEXT: minps %xmm2, %xmm0 ; SSE41-NEXT: minps %xmm2, %xmm0
; SSE41-NEXT: minps %xmm1, %xmm0 ; SSE41-NEXT: minps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: minps %xmm1, %xmm0 ; SSE41-NEXT: minps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: minss %xmm1, %xmm0 ; SSE41-NEXT: minss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v16f32: ; AVX-LABEL: test_v16f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vminps %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vminps %ymm1, %ymm0, %ymm0
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; ;
; vXf64 ; vXf64
; ;
define double @test_v2f64(<2 x double> %a0) { define double @test_v2f64(<2 x double> %a0) {
; SSE-LABEL: test_v2f64: ; SSE-LABEL: test_v2f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE-NEXT: minsd %xmm1, %xmm0 ; SSE-NEXT: minsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v2f64: ; AVX-LABEL: test_v2f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vminsd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vminsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; AVX512-LABEL: test_v2f64: ; AVX512-LABEL: test_v2f64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX512-NEXT: vminsd %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vminsd %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call nnan double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a0) %1 = call nnan double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a0)
ret double %1 ret double %1
} }
define double @test_v4f64(<4 x double> %a0) { define double @test_v4f64(<4 x double> %a0) {
; SSE-LABEL: test_v4f64: ; SSE-LABEL: test_v4f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: minpd %xmm1, %xmm0 ; SSE-NEXT: minpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: minsd %xmm1, %xmm0 ; SSE-NEXT: minsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v4f64: ; AVX-LABEL: test_v4f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vminpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vminpd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
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} }
define double @test_v8f64(<8 x double> %a0) { define double @test_v8f64(<8 x double> %a0) {
; SSE-LABEL: test_v8f64: ; SSE-LABEL: test_v8f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: minpd %xmm3, %xmm1 ; SSE-NEXT: minpd %xmm3, %xmm1
; SSE-NEXT: minpd %xmm2, %xmm0 ; SSE-NEXT: minpd %xmm2, %xmm0
; SSE-NEXT: minpd %xmm1, %xmm0 ; SSE-NEXT: minpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: minsd %xmm1, %xmm0 ; SSE-NEXT: minsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v8f64: ; AVX-LABEL: test_v8f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vminpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vminpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vminpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vminpd %xmm1, %xmm0, %xmm0
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; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: minpd %xmm6, %xmm2 ; SSE-NEXT: minpd %xmm6, %xmm2
; SSE-NEXT: minpd %xmm4, %xmm0 ; SSE-NEXT: minpd %xmm4, %xmm0
; SSE-NEXT: minpd %xmm2, %xmm0 ; SSE-NEXT: minpd %xmm2, %xmm0
; SSE-NEXT: minpd %xmm7, %xmm3 ; SSE-NEXT: minpd %xmm7, %xmm3
; SSE-NEXT: minpd %xmm5, %xmm1 ; SSE-NEXT: minpd %xmm5, %xmm1
; SSE-NEXT: minpd %xmm3, %xmm1 ; SSE-NEXT: minpd %xmm3, %xmm1
; SSE-NEXT: minpd %xmm1, %xmm0 ; SSE-NEXT: minpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: minsd %xmm1, %xmm0 ; SSE-NEXT: minsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v16f64: ; AVX-LABEL: test_v16f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vminpd %ymm3, %ymm1, %ymm1 ; AVX-NEXT: vminpd %ymm3, %ymm1, %ymm1
; AVX-NEXT: vminpd %ymm2, %ymm0, %ymm0 ; AVX-NEXT: vminpd %ymm2, %ymm0, %ymm0
; AVX-NEXT: vminpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vminpd %ymm1, %ymm0, %ymm0
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llvm/test/CodeGen/X86/vector-reduce-fmin.ll

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; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %a0) %1 = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v4f32(<4 x float> %a0) { define float @test_v4f32(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32: ; SSE2-LABEL: test_v4f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE2-NEXT: movaps %xmm0, %xmm3 ; SSE2-NEXT: movaps %xmm0, %xmm3
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm0[1,1]
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: cmpunordss %xmm0, %xmm1 ; SSE2-NEXT: cmpunordss %xmm0, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm4 ; SSE2-NEXT: movaps %xmm1, %xmm4
; SSE2-NEXT: andps %xmm3, %xmm4 ; SSE2-NEXT: andps %xmm3, %xmm4
; SSE2-NEXT: minss %xmm0, %xmm3 ; SSE2-NEXT: minss %xmm0, %xmm3
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; SSE2-NEXT: andnps %xmm3, %xmm1 ; SSE2-NEXT: andnps %xmm3, %xmm1
; SSE2-NEXT: orps %xmm4, %xmm1 ; SSE2-NEXT: orps %xmm4, %xmm1
; SSE2-NEXT: movaps %xmm2, %xmm3 ; SSE2-NEXT: movaps %xmm2, %xmm3
; SSE2-NEXT: minss %xmm1, %xmm3 ; SSE2-NEXT: minss %xmm1, %xmm3
; SSE2-NEXT: cmpunordss %xmm1, %xmm1 ; SSE2-NEXT: cmpunordss %xmm1, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm4 ; SSE2-NEXT: movaps %xmm1, %xmm4
; SSE2-NEXT: andnps %xmm3, %xmm4 ; SSE2-NEXT: andnps %xmm3, %xmm4
; SSE2-NEXT: andps %xmm2, %xmm1 ; SSE2-NEXT: andps %xmm2, %xmm1
; SSE2-NEXT: orps %xmm4, %xmm1 ; SSE2-NEXT: orps %xmm4, %xmm1
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: minss %xmm1, %xmm2 ; SSE2-NEXT: minss %xmm1, %xmm2
; SSE2-NEXT: cmpunordss %xmm1, %xmm1 ; SSE2-NEXT: cmpunordss %xmm1, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm3 ; SSE2-NEXT: movaps %xmm1, %xmm3
; SSE2-NEXT: andnps %xmm2, %xmm3 ; SSE2-NEXT: andnps %xmm2, %xmm3
; SSE2-NEXT: andps %xmm0, %xmm1 ; SSE2-NEXT: andps %xmm0, %xmm1
; SSE2-NEXT: orps %xmm3, %xmm1 ; SSE2-NEXT: orps %xmm3, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32: ; SSE41-LABEL: test_v4f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm0, %xmm2 ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE41-NEXT: movshdup {{.*#+}} xmm3 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movaps %xmm0, %xmm1
; SSE41-NEXT: cmpunordss %xmm0, %xmm1 ; SSE41-NEXT: cmpunordss %xmm0, %xmm1
; SSE41-NEXT: movaps %xmm1, %xmm4 ; SSE41-NEXT: movaps %xmm1, %xmm4
; SSE41-NEXT: andps %xmm3, %xmm4 ; SSE41-NEXT: andps %xmm3, %xmm4
; SSE41-NEXT: minss %xmm0, %xmm3 ; SSE41-NEXT: minss %xmm0, %xmm3
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; SSE41-NEXT: andnps %xmm3, %xmm1 ; SSE41-NEXT: andnps %xmm3, %xmm1
; SSE41-NEXT: orps %xmm4, %xmm1 ; SSE41-NEXT: orps %xmm4, %xmm1
; SSE41-NEXT: movaps %xmm2, %xmm3 ; SSE41-NEXT: movaps %xmm2, %xmm3
; SSE41-NEXT: minss %xmm1, %xmm3 ; SSE41-NEXT: minss %xmm1, %xmm3
; SSE41-NEXT: cmpunordss %xmm1, %xmm1 ; SSE41-NEXT: cmpunordss %xmm1, %xmm1
; SSE41-NEXT: movaps %xmm1, %xmm4 ; SSE41-NEXT: movaps %xmm1, %xmm4
; SSE41-NEXT: andnps %xmm3, %xmm4 ; SSE41-NEXT: andnps %xmm3, %xmm4
; SSE41-NEXT: andps %xmm2, %xmm1 ; SSE41-NEXT: andps %xmm2, %xmm1
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; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE41-NEXT: movaps %xmm2, %xmm0 ; SSE41-NEXT: movaps %xmm2, %xmm0
; SSE41-NEXT: cmpunordss %xmm2, %xmm0 ; SSE41-NEXT: cmpunordss %xmm2, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm3 ; SSE41-NEXT: movaps %xmm0, %xmm3
; SSE41-NEXT: andps %xmm1, %xmm3 ; SSE41-NEXT: andps %xmm1, %xmm3
; SSE41-NEXT: minss %xmm2, %xmm1 ; SSE41-NEXT: minss %xmm2, %xmm1
; SSE41-NEXT: andnps %xmm1, %xmm0 ; SSE41-NEXT: andnps %xmm1, %xmm0
; SSE41-NEXT: orps %xmm3, %xmm0 ; SSE41-NEXT: orps %xmm3, %xmm0
; SSE41-NEXT: movaps %xmm2, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE41-NEXT: movaps %xmm1, %xmm3 ; SSE41-NEXT: movaps %xmm1, %xmm3
; SSE41-NEXT: minss %xmm0, %xmm3 ; SSE41-NEXT: minss %xmm0, %xmm3
; SSE41-NEXT: cmpunordss %xmm0, %xmm0 ; SSE41-NEXT: cmpunordss %xmm0, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm4 ; SSE41-NEXT: movaps %xmm0, %xmm4
; SSE41-NEXT: andnps %xmm3, %xmm4 ; SSE41-NEXT: andnps %xmm3, %xmm4
; SSE41-NEXT: andps %xmm1, %xmm0 ; SSE41-NEXT: andps %xmm1, %xmm0
; SSE41-NEXT: orps %xmm4, %xmm0 ; SSE41-NEXT: orps %xmm4, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
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; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3]
; SSE41-NEXT: movaps %xmm1, %xmm0 ; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: cmpunordss %xmm1, %xmm0 ; SSE41-NEXT: cmpunordss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm3 ; SSE41-NEXT: movaps %xmm0, %xmm3
; SSE41-NEXT: andps %xmm2, %xmm3 ; SSE41-NEXT: andps %xmm2, %xmm3
; SSE41-NEXT: minss %xmm1, %xmm2 ; SSE41-NEXT: minss %xmm1, %xmm2
; SSE41-NEXT: andnps %xmm2, %xmm0 ; SSE41-NEXT: andnps %xmm2, %xmm0
; SSE41-NEXT: orps %xmm3, %xmm0 ; SSE41-NEXT: orps %xmm3, %xmm0
; SSE41-NEXT: movaps %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: movaps %xmm2, %xmm3 ; SSE41-NEXT: movaps %xmm2, %xmm3
; SSE41-NEXT: minss %xmm0, %xmm3 ; SSE41-NEXT: minss %xmm0, %xmm3
; SSE41-NEXT: cmpunordss %xmm0, %xmm0 ; SSE41-NEXT: cmpunordss %xmm0, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm4 ; SSE41-NEXT: movaps %xmm0, %xmm4
; SSE41-NEXT: andnps %xmm3, %xmm4 ; SSE41-NEXT: andnps %xmm3, %xmm4
; SSE41-NEXT: andps %xmm2, %xmm0 ; SSE41-NEXT: andps %xmm2, %xmm0
; SSE41-NEXT: orps %xmm4, %xmm0 ; SSE41-NEXT: orps %xmm4, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
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; ;
; vXf64 ; vXf64
; ;
define double @test_v2f64(<2 x double> %a0) { define double @test_v2f64(<2 x double> %a0) {
; SSE-LABEL: test_v2f64: ; SSE-LABEL: test_v2f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm2 ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1] ; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: movapd %xmm0, %xmm1
; SSE-NEXT: cmpunordsd %xmm0, %xmm1 ; SSE-NEXT: cmpunordsd %xmm0, %xmm1
; SSE-NEXT: movapd %xmm1, %xmm3 ; SSE-NEXT: movapd %xmm1, %xmm3
; SSE-NEXT: andpd %xmm2, %xmm3 ; SSE-NEXT: andpd %xmm2, %xmm3
; SSE-NEXT: minsd %xmm0, %xmm2 ; SSE-NEXT: minsd %xmm0, %xmm2
; SSE-NEXT: andnpd %xmm2, %xmm1 ; SSE-NEXT: andnpd %xmm2, %xmm1
; SSE-NEXT: orpd %xmm3, %xmm1 ; SSE-NEXT: orpd %xmm3, %xmm1
; SSE-NEXT: movapd %xmm1, %xmm0 ; SSE-NEXT: movapd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
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; SSE41-LABEL: test_v3f64: ; SSE41-LABEL: test_v3f64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE41-NEXT: blendpd {{.*#+}} xmm2 = xmm2[0],mem[1] ; SSE41-NEXT: blendpd {{.*#+}} xmm2 = xmm2[0],mem[1]
; SSE41-NEXT: movapd %xmm2, %xmm1 ; SSE41-NEXT: movapd %xmm2, %xmm1
; SSE41-NEXT: minpd %xmm0, %xmm1 ; SSE41-NEXT: minpd %xmm0, %xmm1
; SSE41-NEXT: cmpunordpd %xmm0, %xmm0 ; SSE41-NEXT: cmpunordpd %xmm0, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1 ; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movapd %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: movapd %xmm1, %xmm0 ; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: cmpunordsd %xmm1, %xmm0 ; SSE41-NEXT: cmpunordsd %xmm1, %xmm0
; SSE41-NEXT: movapd %xmm0, %xmm3 ; SSE41-NEXT: movapd %xmm0, %xmm3
; SSE41-NEXT: andpd %xmm2, %xmm3 ; SSE41-NEXT: andpd %xmm2, %xmm3
; SSE41-NEXT: minsd %xmm1, %xmm2 ; SSE41-NEXT: minsd %xmm1, %xmm2
; SSE41-NEXT: andnpd %xmm2, %xmm0 ; SSE41-NEXT: andnpd %xmm2, %xmm0
; SSE41-NEXT: orpd %xmm3, %xmm0 ; SSE41-NEXT: orpd %xmm3, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
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; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f64: ; SSE41-LABEL: test_v4f64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movapd %xmm1, %xmm2 ; SSE41-NEXT: movapd %xmm1, %xmm2
; SSE41-NEXT: minpd %xmm0, %xmm2 ; SSE41-NEXT: minpd %xmm0, %xmm2
; SSE41-NEXT: cmpunordpd %xmm0, %xmm0 ; SSE41-NEXT: cmpunordpd %xmm0, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2 ; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; SSE41-NEXT: movapd %xmm2, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE41-NEXT: movapd %xmm2, %xmm0 ; SSE41-NEXT: movapd %xmm2, %xmm0
; SSE41-NEXT: cmpunordsd %xmm2, %xmm0 ; SSE41-NEXT: cmpunordsd %xmm2, %xmm0
; SSE41-NEXT: movapd %xmm0, %xmm3 ; SSE41-NEXT: movapd %xmm0, %xmm3
; SSE41-NEXT: andpd %xmm1, %xmm3 ; SSE41-NEXT: andpd %xmm1, %xmm3
; SSE41-NEXT: minsd %xmm2, %xmm1 ; SSE41-NEXT: minsd %xmm2, %xmm1
; SSE41-NEXT: andnpd %xmm1, %xmm0 ; SSE41-NEXT: andnpd %xmm1, %xmm0
; SSE41-NEXT: orpd %xmm3, %xmm0 ; SSE41-NEXT: orpd %xmm3, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
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; SSE41-NEXT: cmpunordpd %xmm1, %xmm1 ; SSE41-NEXT: cmpunordpd %xmm1, %xmm1
; SSE41-NEXT: movapd %xmm1, %xmm0 ; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm2 ; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movapd %xmm2, %xmm1 ; SSE41-NEXT: movapd %xmm2, %xmm1
; SSE41-NEXT: minpd %xmm4, %xmm1 ; SSE41-NEXT: minpd %xmm4, %xmm1
; SSE41-NEXT: cmpunordpd %xmm4, %xmm4 ; SSE41-NEXT: cmpunordpd %xmm4, %xmm4
; SSE41-NEXT: movapd %xmm4, %xmm0 ; SSE41-NEXT: movapd %xmm4, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1 ; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movapd %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: movapd %xmm1, %xmm0 ; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: cmpunordsd %xmm1, %xmm0 ; SSE41-NEXT: cmpunordsd %xmm1, %xmm0
; SSE41-NEXT: movapd %xmm0, %xmm3 ; SSE41-NEXT: movapd %xmm0, %xmm3
; SSE41-NEXT: andpd %xmm2, %xmm3 ; SSE41-NEXT: andpd %xmm2, %xmm3
; SSE41-NEXT: minsd %xmm1, %xmm2 ; SSE41-NEXT: minsd %xmm1, %xmm2
; SSE41-NEXT: andnpd %xmm2, %xmm0 ; SSE41-NEXT: andnpd %xmm2, %xmm0
; SSE41-NEXT: orpd %xmm3, %xmm0 ; SSE41-NEXT: orpd %xmm3, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
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; SSE41-NEXT: cmpunordpd %xmm3, %xmm3 ; SSE41-NEXT: cmpunordpd %xmm3, %xmm3
; SSE41-NEXT: movapd %xmm3, %xmm0 ; SSE41-NEXT: movapd %xmm3, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm4 ; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm4
; SSE41-NEXT: movapd %xmm4, %xmm1 ; SSE41-NEXT: movapd %xmm4, %xmm1
; SSE41-NEXT: minpd %xmm2, %xmm1 ; SSE41-NEXT: minpd %xmm2, %xmm1
; SSE41-NEXT: cmpunordpd %xmm2, %xmm2 ; SSE41-NEXT: cmpunordpd %xmm2, %xmm2
; SSE41-NEXT: movapd %xmm2, %xmm0 ; SSE41-NEXT: movapd %xmm2, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm1 ; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm1
; SSE41-NEXT: movapd %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: movapd %xmm1, %xmm0 ; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: cmpunordsd %xmm1, %xmm0 ; SSE41-NEXT: cmpunordsd %xmm1, %xmm0
; SSE41-NEXT: movapd %xmm0, %xmm3 ; SSE41-NEXT: movapd %xmm0, %xmm3
; SSE41-NEXT: andpd %xmm2, %xmm3 ; SSE41-NEXT: andpd %xmm2, %xmm3
; SSE41-NEXT: minsd %xmm1, %xmm2 ; SSE41-NEXT: minsd %xmm1, %xmm2
; SSE41-NEXT: andnpd %xmm2, %xmm0 ; SSE41-NEXT: andnpd %xmm2, %xmm0
; SSE41-NEXT: orpd %xmm3, %xmm0 ; SSE41-NEXT: orpd %xmm3, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
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llvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll

Show All 40 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call fast float @llvm.vector.reduce.fmul.f32.v2f32(float %a0, <2 x float> %a1) %1 = call fast float @llvm.vector.reduce.fmul.f32.v2f32(float %a0, <2 x float> %a1)
ret float %1 ret float %1
} }
define float @test_v4f32(float %a0, <4 x float> %a1) { define float @test_v4f32(float %a0, <4 x float> %a1) {
; SSE2-LABEL: test_v4f32: ; SSE2-LABEL: test_v4f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1]
; SSE2-NEXT: mulps %xmm1, %xmm2 ; SSE2-NEXT: mulps %xmm1, %xmm2
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1]
; SSE2-NEXT: mulss %xmm2, %xmm1 ; SSE2-NEXT: mulss %xmm2, %xmm1
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32: ; SSE41-LABEL: test_v4f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm1, %xmm2 ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1]
; SSE41-NEXT: mulps %xmm1, %xmm2 ; SSE41-NEXT: mulps %xmm1, %xmm2
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE41-NEXT: mulss %xmm2, %xmm1 ; SSE41-NEXT: mulss %xmm2, %xmm1
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v4f32: ; AVX-LABEL: test_v4f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
Show All 15 Lines; AVX512-NEXT: retq
%1 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float %a0, <4 x float> %a1) %1 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float %a0, <4 x float> %a1)
ret float %1 ret float %1
} }
define float @test_v8f32(float %a0, <8 x float> %a1) { define float @test_v8f32(float %a0, <8 x float> %a1) {
; SSE2-LABEL: test_v8f32: ; SSE2-LABEL: test_v8f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: mulps %xmm2, %xmm1 ; SSE2-NEXT: mulps %xmm2, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE2-NEXT: mulps %xmm1, %xmm2 ; SSE2-NEXT: mulps %xmm1, %xmm2
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1]
; SSE2-NEXT: mulss %xmm2, %xmm1 ; SSE2-NEXT: mulss %xmm2, %xmm1
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32: ; SSE41-LABEL: test_v8f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: mulps %xmm2, %xmm1 ; SSE41-NEXT: mulps %xmm2, %xmm1
; SSE41-NEXT: movaps %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: mulps %xmm1, %xmm2 ; SSE41-NEXT: mulps %xmm1, %xmm2
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE41-NEXT: mulss %xmm2, %xmm1 ; SSE41-NEXT: mulss %xmm2, %xmm1
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v8f32: ; AVX-LABEL: test_v8f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
Show All 23 Lines
} }
define float @test_v16f32(float %a0, <16 x float> %a1) { define float @test_v16f32(float %a0, <16 x float> %a1) {
; SSE2-LABEL: test_v16f32: ; SSE2-LABEL: test_v16f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: mulps %xmm4, %xmm2 ; SSE2-NEXT: mulps %xmm4, %xmm2
; SSE2-NEXT: mulps %xmm3, %xmm1 ; SSE2-NEXT: mulps %xmm3, %xmm1
; SSE2-NEXT: mulps %xmm2, %xmm1 ; SSE2-NEXT: mulps %xmm2, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE2-NEXT: mulps %xmm1, %xmm2 ; SSE2-NEXT: mulps %xmm1, %xmm2
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1]
; SSE2-NEXT: mulss %xmm2, %xmm1 ; SSE2-NEXT: mulss %xmm2, %xmm1
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32: ; SSE41-LABEL: test_v16f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: mulps %xmm4, %xmm2 ; SSE41-NEXT: mulps %xmm4, %xmm2
; SSE41-NEXT: mulps %xmm3, %xmm1 ; SSE41-NEXT: mulps %xmm3, %xmm1
; SSE41-NEXT: mulps %xmm2, %xmm1 ; SSE41-NEXT: mulps %xmm2, %xmm1
; SSE41-NEXT: movaps %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: mulps %xmm1, %xmm2 ; SSE41-NEXT: mulps %xmm1, %xmm2
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE41-NEXT: mulss %xmm2, %xmm1 ; SSE41-NEXT: mulss %xmm2, %xmm1
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v16f32: ; AVX-LABEL: test_v16f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call fast float @llvm.vector.reduce.fmul.f32.v2f32(float 1.0, <2 x float> %a0) %1 = call fast float @llvm.vector.reduce.fmul.f32.v2f32(float 1.0, <2 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v4f32_zero(<4 x float> %a0) { define float @test_v4f32_zero(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32_zero: ; SSE2-LABEL: test_v4f32_zero:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: mulps %xmm1, %xmm0 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32_zero: ; SSE41-LABEL: test_v4f32_zero:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: mulps %xmm1, %xmm0 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v4f32_zero: ; AVX-LABEL: test_v4f32_zero:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
Show All 12 Lines; AVX512-NEXT: retq
%1 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %a0) %1 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v8f32_zero(<8 x float> %a0) { define float @test_v8f32_zero(<8 x float> %a0) {
; SSE2-LABEL: test_v8f32_zero: ; SSE2-LABEL: test_v8f32_zero:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: mulps %xmm1, %xmm0 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: mulps %xmm1, %xmm0 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32_zero: ; SSE41-LABEL: test_v8f32_zero:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: mulps %xmm1, %xmm0 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: mulps %xmm1, %xmm0 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v8f32_zero: ; AVX-LABEL: test_v8f32_zero:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
Show All 20 Lines
} }
define float @test_v16f32_zero(<16 x float> %a0) { define float @test_v16f32_zero(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32_zero: ; SSE2-LABEL: test_v16f32_zero:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: mulps %xmm3, %xmm1 ; SSE2-NEXT: mulps %xmm3, %xmm1
; SSE2-NEXT: mulps %xmm2, %xmm0 ; SSE2-NEXT: mulps %xmm2, %xmm0
; SSE2-NEXT: mulps %xmm1, %xmm0 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: mulps %xmm1, %xmm0 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32_zero: ; SSE41-LABEL: test_v16f32_zero:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: mulps %xmm3, %xmm1 ; SSE41-NEXT: mulps %xmm3, %xmm1
; SSE41-NEXT: mulps %xmm2, %xmm0 ; SSE41-NEXT: mulps %xmm2, %xmm0
; SSE41-NEXT: mulps %xmm1, %xmm0 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: mulps %xmm1, %xmm0 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v16f32_zero: ; AVX-LABEL: test_v16f32_zero:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm0
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call fast float @llvm.vector.reduce.fmul.f32.v2f32(float 1.0, <2 x float> %a0) %1 = call fast float @llvm.vector.reduce.fmul.f32.v2f32(float 1.0, <2 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v4f32_undef(<4 x float> %a0) { define float @test_v4f32_undef(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32_undef: ; SSE2-LABEL: test_v4f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: mulps %xmm1, %xmm0 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32_undef: ; SSE41-LABEL: test_v4f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: mulps %xmm1, %xmm0 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v4f32_undef: ; AVX-LABEL: test_v4f32_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
Show All 12 Lines; AVX512-NEXT: retq
%1 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %a0) %1 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %a0)
ret float %1 ret float %1
} }
define float @test_v8f32_undef(<8 x float> %a0) { define float @test_v8f32_undef(<8 x float> %a0) {
; SSE2-LABEL: test_v8f32_undef: ; SSE2-LABEL: test_v8f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: mulps %xmm1, %xmm0 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: mulps %xmm1, %xmm0 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32_undef: ; SSE41-LABEL: test_v8f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: mulps %xmm1, %xmm0 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: mulps %xmm1, %xmm0 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v8f32_undef: ; AVX-LABEL: test_v8f32_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
Show All 20 Lines
} }
define float @test_v16f32_undef(<16 x float> %a0) { define float @test_v16f32_undef(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32_undef: ; SSE2-LABEL: test_v16f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: mulps %xmm3, %xmm1 ; SSE2-NEXT: mulps %xmm3, %xmm1
; SSE2-NEXT: mulps %xmm2, %xmm0 ; SSE2-NEXT: mulps %xmm2, %xmm0
; SSE2-NEXT: mulps %xmm1, %xmm0 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: mulps %xmm1, %xmm0 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32_undef: ; SSE41-LABEL: test_v16f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: mulps %xmm3, %xmm1 ; SSE41-NEXT: mulps %xmm3, %xmm1
; SSE41-NEXT: mulps %xmm2, %xmm0 ; SSE41-NEXT: mulps %xmm2, %xmm0
; SSE41-NEXT: mulps %xmm1, %xmm0 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE41-NEXT: mulps %xmm1, %xmm0 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v16f32_undef: ; AVX-LABEL: test_v16f32_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm0
Show All 24 Lines
; ;
; vXf64 (accum) ; vXf64 (accum)
; ;
define double @test_v2f64(double %a0, <2 x double> %a1) { define double @test_v2f64(double %a0, <2 x double> %a1) {
; SSE-LABEL: test_v2f64: ; SSE-LABEL: test_v2f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm1, %xmm2 ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm2 ; SSE-NEXT: mulsd %xmm1, %xmm2
; SSE-NEXT: mulsd %xmm2, %xmm0 ; SSE-NEXT: mulsd %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v2f64: ; AVX-LABEL: test_v2f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm1[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm1[1,0]
; AVX-NEXT: vmulsd %xmm2, %xmm1, %xmm1 ; AVX-NEXT: vmulsd %xmm2, %xmm1, %xmm1
Show All 9 Lines; AVX512-NEXT: retq
%1 = call fast double @llvm.vector.reduce.fmul.f64.v2f64(double %a0, <2 x double> %a1) %1 = call fast double @llvm.vector.reduce.fmul.f64.v2f64(double %a0, <2 x double> %a1)
ret double %1 ret double %1
} }
define double @test_v4f64(double %a0, <4 x double> %a1) { define double @test_v4f64(double %a0, <4 x double> %a1) {
; SSE-LABEL: test_v4f64: ; SSE-LABEL: test_v4f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulpd %xmm2, %xmm1 ; SSE-NEXT: mulpd %xmm2, %xmm1
; SSE-NEXT: movapd %xmm1, %xmm2 ; SSE-NEXT: xorps %xmm2, %xmm2
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE-NEXT: mulsd %xmm1, %xmm2 ; SSE-NEXT: mulsd %xmm1, %xmm2
; SSE-NEXT: mulsd %xmm2, %xmm0 ; SSE-NEXT: mulsd %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v4f64: ; AVX-LABEL: test_v4f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX-NEXT: vmulpd %xmm2, %xmm1, %xmm1 ; AVX-NEXT: vmulpd %xmm2, %xmm1, %xmm1
Show All 17 Lines
} }
define double @test_v8f64(double %a0, <8 x double> %a1) { define double @test_v8f64(double %a0, <8 x double> %a1) {
; SSE-LABEL: test_v8f64: ; SSE-LABEL: test_v8f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulpd %xmm4, %xmm2 ; SSE-NEXT: mulpd %xmm4, %xmm2
; SSE-NEXT: mulpd %xmm3, %xmm1 ; SSE-NEXT: mulpd %xmm3, %xmm1
; SSE-NEXT: mulpd %xmm2, %xmm1 ; SSE-NEXT: mulpd %xmm2, %xmm1
; SSE-NEXT: movapd %xmm1, %xmm2 ; SSE-NEXT: xorps %xmm2, %xmm2
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE-NEXT: mulsd %xmm1, %xmm2 ; SSE-NEXT: mulsd %xmm1, %xmm2
; SSE-NEXT: mulsd %xmm2, %xmm0 ; SSE-NEXT: mulsd %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v8f64: ; AVX-LABEL: test_v8f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulpd %ymm2, %ymm1, %ymm1 ; AVX-NEXT: vmulpd %ymm2, %ymm1, %ymm1
; AVX-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX-NEXT: vextractf128 $1, %ymm1, %xmm2
Show All 20 Lines
} }
define double @test_v16f64(double %a0, <16 x double> %a1) { define double @test_v16f64(double %a0, <16 x double> %a1) {
; SSE-LABEL: test_v16f64: ; SSE-LABEL: test_v16f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulpd %xmm6, %xmm2 ; SSE-NEXT: mulpd %xmm6, %xmm2
; SSE-NEXT: mulpd %xmm7, %xmm3 ; SSE-NEXT: mulpd %xmm7, %xmm3
; SSE-NEXT: mulpd %xmm5, %xmm1 ; SSE-NEXT: mulpd %xmm5, %xmm1
; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm4
; SSE-NEXT: mulpd %xmm3, %xmm1 ; SSE-NEXT: mulpd %xmm3, %xmm1
; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm4
; SSE-NEXT: mulpd %xmm2, %xmm4 ; SSE-NEXT: mulpd %xmm2, %xmm4
; SSE-NEXT: mulpd %xmm1, %xmm4 ; SSE-NEXT: mulpd %xmm1, %xmm4
; SSE-NEXT: movapd %xmm4, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm4[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm4[1],xmm1[1]
; SSE-NEXT: mulsd %xmm4, %xmm1 ; SSE-NEXT: mulsd %xmm4, %xmm1
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v16f64: ; AVX-LABEL: test_v16f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulpd %ymm4, %ymm2, %ymm2 ; AVX-NEXT: vmulpd %ymm4, %ymm2, %ymm2
; AVX-NEXT: vmulpd %ymm3, %ymm1, %ymm1 ; AVX-NEXT: vmulpd %ymm3, %ymm1, %ymm1
Show All 24 Lines
; ;
; vXf64 (one) ; vXf64 (one)
; ;
define double @test_v2f64_zero(<2 x double> %a0) { define double @test_v2f64_zero(<2 x double> %a0) {
; SSE-LABEL: test_v2f64_zero: ; SSE-LABEL: test_v2f64_zero:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v2f64_zero: ; AVX-LABEL: test_v2f64_zero:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; AVX512-LABEL: test_v2f64_zero: ; AVX512-LABEL: test_v2f64_zero:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX512-NEXT: vmulsd %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vmulsd %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call fast double @llvm.vector.reduce.fmul.f64.v2f64(double 1.0, <2 x double> %a0) %1 = call fast double @llvm.vector.reduce.fmul.f64.v2f64(double 1.0, <2 x double> %a0)
ret double %1 ret double %1
} }
define double @test_v4f64_zero(<4 x double> %a0) { define double @test_v4f64_zero(<4 x double> %a0) {
; SSE-LABEL: test_v4f64_zero: ; SSE-LABEL: test_v4f64_zero:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulpd %xmm1, %xmm0 ; SSE-NEXT: mulpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v4f64_zero: ; AVX-LABEL: test_v4f64_zero:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmulpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulpd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
Show All 14 Lines
} }
define double @test_v8f64_zero(<8 x double> %a0) { define double @test_v8f64_zero(<8 x double> %a0) {
; SSE-LABEL: test_v8f64_zero: ; SSE-LABEL: test_v8f64_zero:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulpd %xmm3, %xmm1 ; SSE-NEXT: mulpd %xmm3, %xmm1
; SSE-NEXT: mulpd %xmm2, %xmm0 ; SSE-NEXT: mulpd %xmm2, %xmm0
; SSE-NEXT: mulpd %xmm1, %xmm0 ; SSE-NEXT: mulpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v8f64_zero: ; AVX-LABEL: test_v8f64_zero:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmulpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmulpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulpd %xmm1, %xmm0, %xmm0
Show All 21 Lines
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulpd %xmm6, %xmm2 ; SSE-NEXT: mulpd %xmm6, %xmm2
; SSE-NEXT: mulpd %xmm4, %xmm0 ; SSE-NEXT: mulpd %xmm4, %xmm0
; SSE-NEXT: mulpd %xmm2, %xmm0 ; SSE-NEXT: mulpd %xmm2, %xmm0
; SSE-NEXT: mulpd %xmm7, %xmm3 ; SSE-NEXT: mulpd %xmm7, %xmm3
; SSE-NEXT: mulpd %xmm5, %xmm1 ; SSE-NEXT: mulpd %xmm5, %xmm1
; SSE-NEXT: mulpd %xmm3, %xmm1 ; SSE-NEXT: mulpd %xmm3, %xmm1
; SSE-NEXT: mulpd %xmm1, %xmm0 ; SSE-NEXT: mulpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v16f64_zero: ; AVX-LABEL: test_v16f64_zero:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulpd %ymm3, %ymm1, %ymm1 ; AVX-NEXT: vmulpd %ymm3, %ymm1, %ymm1
; AVX-NEXT: vmulpd %ymm2, %ymm0, %ymm0 ; AVX-NEXT: vmulpd %ymm2, %ymm0, %ymm0
; AVX-NEXT: vmulpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmulpd %ymm1, %ymm0, %ymm0
Show All 21 Lines
; ;
; vXf64 (undef) ; vXf64 (undef)
; ;
define double @test_v2f64_undef(<2 x double> %a0) { define double @test_v2f64_undef(<2 x double> %a0) {
; SSE-LABEL: test_v2f64_undef: ; SSE-LABEL: test_v2f64_undef:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v2f64_undef: ; AVX-LABEL: test_v2f64_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; AVX512-LABEL: test_v2f64_undef: ; AVX512-LABEL: test_v2f64_undef:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX512-NEXT: vmulsd %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vmulsd %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call fast double @llvm.vector.reduce.fmul.f64.v2f64(double 1.0, <2 x double> %a0) %1 = call fast double @llvm.vector.reduce.fmul.f64.v2f64(double 1.0, <2 x double> %a0)
ret double %1 ret double %1
} }
define double @test_v4f64_undef(<4 x double> %a0) { define double @test_v4f64_undef(<4 x double> %a0) {
; SSE-LABEL: test_v4f64_undef: ; SSE-LABEL: test_v4f64_undef:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulpd %xmm1, %xmm0 ; SSE-NEXT: mulpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v4f64_undef: ; AVX-LABEL: test_v4f64_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmulpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulpd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
Show All 14 Lines
} }
define double @test_v8f64_undef(<8 x double> %a0) { define double @test_v8f64_undef(<8 x double> %a0) {
; SSE-LABEL: test_v8f64_undef: ; SSE-LABEL: test_v8f64_undef:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulpd %xmm3, %xmm1 ; SSE-NEXT: mulpd %xmm3, %xmm1
; SSE-NEXT: mulpd %xmm2, %xmm0 ; SSE-NEXT: mulpd %xmm2, %xmm0
; SSE-NEXT: mulpd %xmm1, %xmm0 ; SSE-NEXT: mulpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v8f64_undef: ; AVX-LABEL: test_v8f64_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmulpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmulpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulpd %xmm1, %xmm0, %xmm0
Show All 21 Lines
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulpd %xmm6, %xmm2 ; SSE-NEXT: mulpd %xmm6, %xmm2
; SSE-NEXT: mulpd %xmm4, %xmm0 ; SSE-NEXT: mulpd %xmm4, %xmm0
; SSE-NEXT: mulpd %xmm2, %xmm0 ; SSE-NEXT: mulpd %xmm2, %xmm0
; SSE-NEXT: mulpd %xmm7, %xmm3 ; SSE-NEXT: mulpd %xmm7, %xmm3
; SSE-NEXT: mulpd %xmm5, %xmm1 ; SSE-NEXT: mulpd %xmm5, %xmm1
; SSE-NEXT: mulpd %xmm3, %xmm1 ; SSE-NEXT: mulpd %xmm3, %xmm1
; SSE-NEXT: mulpd %xmm1, %xmm0 ; SSE-NEXT: mulpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v16f64_undef: ; AVX-LABEL: test_v16f64_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulpd %ymm3, %ymm1, %ymm1 ; AVX-NEXT: vmulpd %ymm3, %ymm1, %ymm1
; AVX-NEXT: vmulpd %ymm2, %ymm0, %ymm0 ; AVX-NEXT: vmulpd %ymm2, %ymm0, %ymm0
; AVX-NEXT: vmulpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmulpd %ymm1, %ymm0, %ymm0
Show All 31 Lines

llvm/test/CodeGen/X86/vector-reduce-fmul.ll

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
define float @test_v4f32(float %a0, <4 x float> %a1) { define float @test_v4f32(float %a0, <4 x float> %a1) {
; SSE2-LABEL: test_v4f32: ; SSE2-LABEL: test_v4f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: movaps %xmm1, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1]
; SSE2-NEXT: mulss %xmm2, %xmm0 ; SSE2-NEXT: mulss %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE2-NEXT: mulss %xmm2, %xmm0 ; SSE2-NEXT: mulss %xmm2, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32: ; SSE41-LABEL: test_v4f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3]
; SSE41-NEXT: mulss %xmm2, %xmm0 ; SSE41-NEXT: mulss %xmm2, %xmm0
; SSE41-NEXT: movaps %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: mulss %xmm2, %xmm0 ; SSE41-NEXT: mulss %xmm2, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v4f32: ; AVX-LABEL: test_v4f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0
Show All 21 Lines
define float @test_v8f32(float %a0, <8 x float> %a1) { define float @test_v8f32(float %a0, <8 x float> %a1) {
; SSE2-LABEL: test_v8f32: ; SSE2-LABEL: test_v8f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm3 ; SSE2-NEXT: movaps %xmm1, %xmm3
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm1[1,1]
; SSE2-NEXT: mulss %xmm3, %xmm0 ; SSE2-NEXT: mulss %xmm3, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm3 ; SSE2-NEXT: xorps %xmm3, %xmm3
; SSE2-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm3 = xmm1[1],xmm3[1]
; SSE2-NEXT: mulss %xmm3, %xmm0 ; SSE2-NEXT: mulss %xmm3, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: mulss %xmm2, %xmm0 ; SSE2-NEXT: mulss %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE2-NEXT: mulss %xmm2, %xmm0 ; SSE2-NEXT: mulss %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32: ; SSE41-LABEL: test_v8f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm3 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm3 = xmm1[1,1,3,3]
; SSE41-NEXT: mulss %xmm3, %xmm0 ; SSE41-NEXT: mulss %xmm3, %xmm0
; SSE41-NEXT: movaps %xmm1, %xmm3 ; SSE41-NEXT: xorps %xmm3, %xmm3
; SSE41-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm3 = xmm1[1],xmm3[1]
; SSE41-NEXT: mulss %xmm3, %xmm0 ; SSE41-NEXT: mulss %xmm3, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: mulss %xmm2, %xmm0 ; SSE41-NEXT: mulss %xmm2, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm2, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE41-NEXT: mulss %xmm2, %xmm0 ; SSE41-NEXT: mulss %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v8f32: ; AVX-LABEL: test_v8f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0
Show All 39 Lines
define float @test_v16f32(float %a0, <16 x float> %a1) { define float @test_v16f32(float %a0, <16 x float> %a1) {
; SSE2-LABEL: test_v16f32: ; SSE2-LABEL: test_v16f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm5 ; SSE2-NEXT: movaps %xmm1, %xmm5
; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,1],xmm1[1,1]
; SSE2-NEXT: mulss %xmm5, %xmm0 ; SSE2-NEXT: mulss %xmm5, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm5 ; SSE2-NEXT: xorps %xmm5, %xmm5
; SSE2-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm5 = xmm1[1],xmm5[1]
; SSE2-NEXT: mulss %xmm5, %xmm0 ; SSE2-NEXT: mulss %xmm5, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: mulss %xmm2, %xmm0 ; SSE2-NEXT: mulss %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE2-NEXT: mulss %xmm2, %xmm0 ; SSE2-NEXT: mulss %xmm2, %xmm0
; SSE2-NEXT: mulss %xmm3, %xmm0 ; SSE2-NEXT: mulss %xmm3, %xmm0
; SSE2-NEXT: movaps %xmm3, %xmm1 ; SSE2-NEXT: movaps %xmm3, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm3[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm3[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm3, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSE2-NEXT: mulss %xmm3, %xmm0 ; SSE2-NEXT: mulss %xmm3, %xmm0
; SSE2-NEXT: mulss %xmm4, %xmm0 ; SSE2-NEXT: mulss %xmm4, %xmm0
; SSE2-NEXT: movaps %xmm4, %xmm1 ; SSE2-NEXT: movaps %xmm4, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm4[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm4[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm4, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm4[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm4[1],xmm1[1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
; SSE2-NEXT: mulss %xmm4, %xmm0 ; SSE2-NEXT: mulss %xmm4, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32: ; SSE41-LABEL: test_v16f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm5 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm5 = xmm1[1,1,3,3]
; SSE41-NEXT: mulss %xmm5, %xmm0 ; SSE41-NEXT: mulss %xmm5, %xmm0
; SSE41-NEXT: movaps %xmm1, %xmm5 ; SSE41-NEXT: xorps %xmm5, %xmm5
; SSE41-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm5 = xmm1[1],xmm5[1]
; SSE41-NEXT: mulss %xmm5, %xmm0 ; SSE41-NEXT: mulss %xmm5, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: mulss %xmm2, %xmm0 ; SSE41-NEXT: mulss %xmm2, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm2, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE41-NEXT: mulss %xmm2, %xmm0 ; SSE41-NEXT: mulss %xmm2, %xmm0
; SSE41-NEXT: mulss %xmm3, %xmm0 ; SSE41-NEXT: mulss %xmm3, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm3[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm3[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm3, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSE41-NEXT: mulss %xmm3, %xmm0 ; SSE41-NEXT: mulss %xmm3, %xmm0
; SSE41-NEXT: mulss %xmm4, %xmm0 ; SSE41-NEXT: mulss %xmm4, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm4[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm4[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm4, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm4[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm4[1],xmm1[1]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
; SSE41-NEXT: mulss %xmm4, %xmm0 ; SSE41-NEXT: mulss %xmm4, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v16f32: ; AVX-LABEL: test_v16f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0
▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
} }
define float @test_v4f32_one(<4 x float> %a0) { define float @test_v4f32_one(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32_one: ; SSE2-LABEL: test_v4f32_one:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: mulss %xmm0, %xmm1 ; SSE2-NEXT: mulss %xmm0, %xmm1
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE2-NEXT: mulss %xmm1, %xmm2 ; SSE2-NEXT: mulss %xmm1, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: mulss %xmm2, %xmm0 ; SSE2-NEXT: mulss %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32_one: ; SSE41-LABEL: test_v4f32_one:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss %xmm0, %xmm1 ; SSE41-NEXT: mulss %xmm0, %xmm1
; SSE41-NEXT: movaps %xmm0, %xmm2 ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE41-NEXT: mulss %xmm1, %xmm2 ; SSE41-NEXT: mulss %xmm1, %xmm2
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE41-NEXT: mulss %xmm2, %xmm0 ; SSE41-NEXT: mulss %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v4f32_one: ; AVX-LABEL: test_v4f32_one:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
Show All 18 Lines
} }
define float @test_v8f32_one(<8 x float> %a0) { define float @test_v8f32_one(<8 x float> %a0) {
; SSE2-LABEL: test_v8f32_one: ; SSE2-LABEL: test_v8f32_one:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1]
; SSE2-NEXT: mulss %xmm0, %xmm2 ; SSE2-NEXT: mulss %xmm0, %xmm2
; SSE2-NEXT: movaps %xmm0, %xmm3 ; SSE2-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; SSE2-NEXT: mulss %xmm2, %xmm3 ; SSE2-NEXT: mulss %xmm2, %xmm3
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: mulss %xmm3, %xmm0 ; SSE2-NEXT: mulss %xmm3, %xmm0
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: movaps %xmm1, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1]
; SSE2-NEXT: mulss %xmm2, %xmm0 ; SSE2-NEXT: mulss %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE2-NEXT: mulss %xmm2, %xmm0 ; SSE2-NEXT: mulss %xmm2, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32_one: ; SSE41-LABEL: test_v8f32_one:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss %xmm0, %xmm2 ; SSE41-NEXT: mulss %xmm0, %xmm2
; SSE41-NEXT: movaps %xmm0, %xmm3 ; SSE41-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; SSE41-NEXT: mulss %xmm2, %xmm3 ; SSE41-NEXT: mulss %xmm2, %xmm3
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE41-NEXT: mulss %xmm3, %xmm0 ; SSE41-NEXT: mulss %xmm3, %xmm0
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3]
; SSE41-NEXT: mulss %xmm2, %xmm0 ; SSE41-NEXT: mulss %xmm2, %xmm0
; SSE41-NEXT: movaps %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: mulss %xmm2, %xmm0 ; SSE41-NEXT: mulss %xmm2, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v8f32_one: ; AVX-LABEL: test_v8f32_one:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
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} }
define float @test_v16f32_one(<16 x float> %a0) { define float @test_v16f32_one(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32_one: ; SSE2-LABEL: test_v16f32_one:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm4 ; SSE2-NEXT: movaps %xmm0, %xmm4
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[1,1]
; SSE2-NEXT: mulss %xmm0, %xmm4 ; SSE2-NEXT: mulss %xmm0, %xmm4
; SSE2-NEXT: movaps %xmm0, %xmm5 ; SSE2-NEXT: movhlps {{.*#+}} xmm5 = xmm0[1],xmm5[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm0[1]
; SSE2-NEXT: mulss %xmm4, %xmm5 ; SSE2-NEXT: mulss %xmm4, %xmm5
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: mulss %xmm5, %xmm0 ; SSE2-NEXT: mulss %xmm5, %xmm0
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm4 ; SSE2-NEXT: movaps %xmm1, %xmm4
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm1[1,1]
; SSE2-NEXT: mulss %xmm4, %xmm0 ; SSE2-NEXT: mulss %xmm4, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm4 ; SSE2-NEXT: xorps %xmm4, %xmm4
; SSE2-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm4 = xmm1[1],xmm4[1]
; SSE2-NEXT: mulss %xmm4, %xmm0 ; SSE2-NEXT: mulss %xmm4, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: mulss %xmm2, %xmm0 ; SSE2-NEXT: mulss %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE2-NEXT: mulss %xmm2, %xmm0 ; SSE2-NEXT: mulss %xmm2, %xmm0
; SSE2-NEXT: mulss %xmm3, %xmm0 ; SSE2-NEXT: mulss %xmm3, %xmm0
; SSE2-NEXT: movaps %xmm3, %xmm1 ; SSE2-NEXT: movaps %xmm3, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm3[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm3[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm3, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSE2-NEXT: mulss %xmm3, %xmm0 ; SSE2-NEXT: mulss %xmm3, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32_one: ; SSE41-LABEL: test_v16f32_one:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss %xmm0, %xmm4 ; SSE41-NEXT: mulss %xmm0, %xmm4
; SSE41-NEXT: movaps %xmm0, %xmm5 ; SSE41-NEXT: movhlps {{.*#+}} xmm5 = xmm0[1],xmm5[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm0[1]
; SSE41-NEXT: mulss %xmm4, %xmm5 ; SSE41-NEXT: mulss %xmm4, %xmm5
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE41-NEXT: mulss %xmm5, %xmm0 ; SSE41-NEXT: mulss %xmm5, %xmm0
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm1[1,1,3,3]
; SSE41-NEXT: mulss %xmm4, %xmm0 ; SSE41-NEXT: mulss %xmm4, %xmm0
; SSE41-NEXT: movaps %xmm1, %xmm4 ; SSE41-NEXT: xorps %xmm4, %xmm4
; SSE41-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm4 = xmm1[1],xmm4[1]
; SSE41-NEXT: mulss %xmm4, %xmm0 ; SSE41-NEXT: mulss %xmm4, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: mulss %xmm2, %xmm0 ; SSE41-NEXT: mulss %xmm2, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm2, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE41-NEXT: mulss %xmm2, %xmm0 ; SSE41-NEXT: mulss %xmm2, %xmm0
; SSE41-NEXT: mulss %xmm3, %xmm0 ; SSE41-NEXT: mulss %xmm3, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm3[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm3[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm3, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSE41-NEXT: mulss %xmm3, %xmm0 ; SSE41-NEXT: mulss %xmm3, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v16f32_one: ; AVX-LABEL: test_v16f32_one:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 99 Lines • ▼ Show 20 Lines
} }
define float @test_v4f32_undef(<4 x float> %a0) { define float @test_v4f32_undef(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32_undef: ; SSE2-LABEL: test_v4f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE2-NEXT: mulss %xmm1, %xmm2 ; SSE2-NEXT: mulss %xmm1, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: mulss %xmm2, %xmm0 ; SSE2-NEXT: mulss %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32_undef: ; SSE41-LABEL: test_v4f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE41-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: movaps %xmm0, %xmm2 ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE41-NEXT: mulss %xmm1, %xmm2 ; SSE41-NEXT: mulss %xmm1, %xmm2
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE41-NEXT: mulss %xmm2, %xmm0 ; SSE41-NEXT: mulss %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v4f32_undef: ; AVX-LABEL: test_v4f32_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
Show All 18 Lines
} }
define float @test_v8f32_undef(<8 x float> %a0) { define float @test_v8f32_undef(<8 x float> %a0) {
; SSE2-LABEL: test_v8f32_undef: ; SSE2-LABEL: test_v8f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1]
; SSE2-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 ; SSE2-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: movaps %xmm0, %xmm3 ; SSE2-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; SSE2-NEXT: mulss %xmm2, %xmm3 ; SSE2-NEXT: mulss %xmm2, %xmm3
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: mulss %xmm3, %xmm0 ; SSE2-NEXT: mulss %xmm3, %xmm0
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: movaps %xmm1, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1]
; SSE2-NEXT: mulss %xmm2, %xmm0 ; SSE2-NEXT: mulss %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE2-NEXT: mulss %xmm2, %xmm0 ; SSE2-NEXT: mulss %xmm2, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32_undef: ; SSE41-LABEL: test_v8f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 ; SSE41-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: movaps %xmm0, %xmm3 ; SSE41-NEXT: movhlps {{.*#+}} xmm3 = xmm0[1],xmm3[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; SSE41-NEXT: mulss %xmm2, %xmm3 ; SSE41-NEXT: mulss %xmm2, %xmm3
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE41-NEXT: mulss %xmm3, %xmm0 ; SSE41-NEXT: mulss %xmm3, %xmm0
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3]
; SSE41-NEXT: mulss %xmm2, %xmm0 ; SSE41-NEXT: mulss %xmm2, %xmm0
; SSE41-NEXT: movaps %xmm1, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE41-NEXT: mulss %xmm2, %xmm0 ; SSE41-NEXT: mulss %xmm2, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v8f32_undef: ; AVX-LABEL: test_v8f32_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
Show All 36 Lines
} }
define float @test_v16f32_undef(<16 x float> %a0) { define float @test_v16f32_undef(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32_undef: ; SSE2-LABEL: test_v16f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm4 ; SSE2-NEXT: movaps %xmm0, %xmm4
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[1,1]
; SSE2-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4 ; SSE2-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NEXT: movaps %xmm0, %xmm5 ; SSE2-NEXT: movhlps {{.*#+}} xmm5 = xmm0[1],xmm5[1]
; SSE2-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm0[1]
; SSE2-NEXT: mulss %xmm4, %xmm5 ; SSE2-NEXT: mulss %xmm4, %xmm5
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE2-NEXT: mulss %xmm5, %xmm0 ; SSE2-NEXT: mulss %xmm5, %xmm0
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm4 ; SSE2-NEXT: movaps %xmm1, %xmm4
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm1[1,1]
; SSE2-NEXT: mulss %xmm4, %xmm0 ; SSE2-NEXT: mulss %xmm4, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm4 ; SSE2-NEXT: xorps %xmm4, %xmm4
; SSE2-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm1[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm4 = xmm1[1],xmm4[1]
; SSE2-NEXT: mulss %xmm4, %xmm0 ; SSE2-NEXT: mulss %xmm4, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: mulss %xmm2, %xmm0 ; SSE2-NEXT: mulss %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE2-NEXT: mulss %xmm2, %xmm0 ; SSE2-NEXT: mulss %xmm2, %xmm0
; SSE2-NEXT: mulss %xmm3, %xmm0 ; SSE2-NEXT: mulss %xmm3, %xmm0
; SSE2-NEXT: movaps %xmm3, %xmm1 ; SSE2-NEXT: movaps %xmm3, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm3[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm3[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm3, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1] ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSE2-NEXT: mulss %xmm3, %xmm0 ; SSE2-NEXT: mulss %xmm3, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32_undef: ; SSE41-LABEL: test_v16f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4 ; SSE41-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE41-NEXT: movaps %xmm0, %xmm5 ; SSE41-NEXT: movhlps {{.*#+}} xmm5 = xmm0[1],xmm5[1]
; SSE41-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm0[1]
; SSE41-NEXT: mulss %xmm4, %xmm5 ; SSE41-NEXT: mulss %xmm4, %xmm5
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE41-NEXT: mulss %xmm5, %xmm0 ; SSE41-NEXT: mulss %xmm5, %xmm0
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm4 = xmm1[1,1,3,3]
; SSE41-NEXT: mulss %xmm4, %xmm0 ; SSE41-NEXT: mulss %xmm4, %xmm0
; SSE41-NEXT: movaps %xmm1, %xmm4 ; SSE41-NEXT: xorps %xmm4, %xmm4
; SSE41-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm1[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm4 = xmm1[1],xmm4[1]
; SSE41-NEXT: mulss %xmm4, %xmm0 ; SSE41-NEXT: mulss %xmm4, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: mulss %xmm2, %xmm0 ; SSE41-NEXT: mulss %xmm2, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm2, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
; SSE41-NEXT: mulss %xmm2, %xmm0 ; SSE41-NEXT: mulss %xmm2, %xmm0
; SSE41-NEXT: mulss %xmm3, %xmm0 ; SSE41-NEXT: mulss %xmm3, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm3[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm3[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm3, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1] ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE41-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSE41-NEXT: mulss %xmm3, %xmm0 ; SSE41-NEXT: mulss %xmm3, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v16f32_undef: ; AVX-LABEL: test_v16f32_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
define double @test_v4f64(double %a0, <4 x double> %a1) { define double @test_v4f64(double %a0, <4 x double> %a1) {
; SSE-LABEL: test_v4f64: ; SSE-LABEL: test_v4f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: mulsd %xmm2, %xmm0 ; SSE-NEXT: mulsd %xmm2, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: mulsd %xmm2, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v4f64: ; AVX-LABEL: test_v4f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm1[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm1[1,0]
; AVX-NEXT: vmulsd %xmm2, %xmm0, %xmm0 ; AVX-NEXT: vmulsd %xmm2, %xmm0, %xmm0
; AVX-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm1, %xmm1
Show All 20 Lines
define double @test_v8f64(double %a0, <8 x double> %a1) { define double @test_v8f64(double %a0, <8 x double> %a1) {
; SSE-LABEL: test_v8f64: ; SSE-LABEL: test_v8f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: mulsd %xmm2, %xmm0 ; SSE-NEXT: mulsd %xmm2, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: mulsd %xmm2, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE-NEXT: mulsd %xmm3, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-NEXT: mulsd %xmm3, %xmm0 ; SSE-NEXT: mulsd %xmm3, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: mulsd %xmm4, %xmm0 ; SSE-NEXT: mulsd %xmm4, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: mulsd %xmm4, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm4[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v8f64: ; AVX-LABEL: test_v8f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpermilpd {{.*#+}} xmm3 = xmm1[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm3 = xmm1[1,0]
; AVX-NEXT: vmulsd %xmm3, %xmm0, %xmm0 ; AVX-NEXT: vmulsd %xmm3, %xmm0, %xmm0
; AVX-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm1, %xmm1
Show All 36 Lines
define double @test_v16f64(double %a0, <16 x double> %a1) { define double @test_v16f64(double %a0, <16 x double> %a1) {
; SSE2-LABEL: test_v16f64: ; SSE2-LABEL: test_v16f64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm8 ; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm8
; SSE2-NEXT: mulsd %xmm1, %xmm0 ; SSE2-NEXT: mulsd %xmm1, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE2-NEXT: mulsd %xmm1, %xmm0 ; SSE2-NEXT: mulsd %xmm1, %xmm0
; SSE2-NEXT: mulsd %xmm2, %xmm0 ; SSE2-NEXT: mulsd %xmm2, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: mulsd %xmm2, %xmm0 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE2-NEXT: mulsd %xmm3, %xmm0 ; SSE2-NEXT: mulsd %xmm1, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE2-NEXT: mulsd %xmm3, %xmm0 ; SSE2-NEXT: mulsd %xmm3, %xmm0
; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE2-NEXT: mulsd %xmm1, %xmm0
; SSE2-NEXT: mulsd %xmm4, %xmm0 ; SSE2-NEXT: mulsd %xmm4, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1] ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: mulsd %xmm4, %xmm0 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm4[1],xmm1[1]
; SSE2-NEXT: mulsd %xmm5, %xmm0 ; SSE2-NEXT: mulsd %xmm1, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1,1]
; SSE2-NEXT: mulsd %xmm5, %xmm0 ; SSE2-NEXT: mulsd %xmm5, %xmm0
; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm5[1],xmm1[1]
; SSE2-NEXT: mulsd %xmm1, %xmm0
; SSE2-NEXT: mulsd %xmm6, %xmm0 ; SSE2-NEXT: mulsd %xmm6, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1,1] ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: mulsd %xmm6, %xmm0 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm6[1],xmm1[1]
; SSE2-NEXT: mulsd %xmm7, %xmm0 ; SSE2-NEXT: mulsd %xmm1, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm7 = xmm7[1,1]
; SSE2-NEXT: mulsd %xmm7, %xmm0 ; SSE2-NEXT: mulsd %xmm7, %xmm0
; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm7[1],xmm1[1]
; SSE2-NEXT: mulsd %xmm1, %xmm0
; SSE2-NEXT: mulsd %xmm8, %xmm0 ; SSE2-NEXT: mulsd %xmm8, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm8 = xmm8[1,1] ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: mulsd %xmm8, %xmm0 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm8[1],xmm1[1]
; SSE2-NEXT: mulsd %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f64: ; SSE41-LABEL: test_v16f64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: mulsd %xmm1, %xmm0 ; SSE41-NEXT: mulsd %xmm1, %xmm0
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE41-NEXT: mulsd %xmm1, %xmm0 ; SSE41-NEXT: mulsd %xmm1, %xmm0
; SSE41-NEXT: mulsd %xmm2, %xmm0 ; SSE41-NEXT: mulsd %xmm2, %xmm0
; SSE41-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: mulsd %xmm2, %xmm0 ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE41-NEXT: mulsd %xmm3, %xmm0 ; SSE41-NEXT: mulsd %xmm1, %xmm0
; SSE41-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE41-NEXT: mulsd %xmm3, %xmm0 ; SSE41-NEXT: mulsd %xmm3, %xmm0
; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE41-NEXT: mulsd %xmm1, %xmm0
; SSE41-NEXT: mulsd %xmm4, %xmm0 ; SSE41-NEXT: mulsd %xmm4, %xmm0
; SSE41-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1] ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: mulsd %xmm4, %xmm0 ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm4[1],xmm1[1]
; SSE41-NEXT: mulsd %xmm5, %xmm0 ; SSE41-NEXT: mulsd %xmm1, %xmm0
; SSE41-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1,1]
; SSE41-NEXT: mulsd %xmm5, %xmm0 ; SSE41-NEXT: mulsd %xmm5, %xmm0
; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm5[1],xmm1[1]
; SSE41-NEXT: mulsd %xmm1, %xmm0
; SSE41-NEXT: mulsd %xmm6, %xmm0 ; SSE41-NEXT: mulsd %xmm6, %xmm0
; SSE41-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1,1] ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: mulsd %xmm6, %xmm0 ; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm6[1],xmm1[1]
; SSE41-NEXT: mulsd %xmm7, %xmm0 ; SSE41-NEXT: mulsd %xmm1, %xmm0
; SSE41-NEXT: unpckhpd {{.*#+}} xmm7 = xmm7[1,1]
; SSE41-NEXT: mulsd %xmm7, %xmm0 ; SSE41-NEXT: mulsd %xmm7, %xmm0
; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm7[1],xmm1[1]
; SSE41-NEXT: mulsd %xmm1, %xmm0
; SSE41-NEXT: mulsd {{[0-9]+}}(%rsp), %xmm0 ; SSE41-NEXT: mulsd {{[0-9]+}}(%rsp), %xmm0
; SSE41-NEXT: mulsd {{[0-9]+}}(%rsp), %xmm0 ; SSE41-NEXT: mulsd {{[0-9]+}}(%rsp), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v16f64: ; AVX-LABEL: test_v16f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpermilpd {{.*#+}} xmm5 = xmm1[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm5 = xmm1[1,0]
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; ;
; vXf64 (one) ; vXf64 (one)
; ;
define double @test_v2f64_one(<2 x double> %a0) { define double @test_v2f64_one(<2 x double> %a0) {
; SSE-LABEL: test_v2f64_one: ; SSE-LABEL: test_v2f64_one:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm1 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v2f64_one: ; AVX-LABEL: test_v2f64_one:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; AVX512-LABEL: test_v2f64_one: ; AVX512-LABEL: test_v2f64_one:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX512-NEXT: vmulsd %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vmulsd %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call double @llvm.vector.reduce.fmul.f64.v2f64(double 1.0, <2 x double> %a0) %1 = call double @llvm.vector.reduce.fmul.f64.v2f64(double 1.0, <2 x double> %a0)
ret double %1 ret double %1
} }
define double @test_v4f64_one(<4 x double> %a0) { define double @test_v4f64_one(<4 x double> %a0) {
; SSE-LABEL: test_v4f64_one: ; SSE-LABEL: test_v4f64_one:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm2 ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE-NEXT: mulsd %xmm2, %xmm0 ; SSE-NEXT: mulsd %xmm2, %xmm0
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v4f64_one: ; AVX-LABEL: test_v4f64_one:
; AVX: # %bb.0: ; AVX: # %bb.0:
Show All 18 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call double @llvm.vector.reduce.fmul.f64.v4f64(double 1.0, <4 x double> %a0) %1 = call double @llvm.vector.reduce.fmul.f64.v4f64(double 1.0, <4 x double> %a0)
ret double %1 ret double %1
} }
define double @test_v8f64_one(<8 x double> %a0) { define double @test_v8f64_one(<8 x double> %a0) {
; SSE-LABEL: test_v8f64_one: ; SSE-LABEL: test_v8f64_one:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm4 ; SSE-NEXT: movhlps {{.*#+}} xmm4 = xmm0[1],xmm4[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1]
; SSE-NEXT: mulsd %xmm4, %xmm0 ; SSE-NEXT: mulsd %xmm4, %xmm0
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: mulsd %xmm2, %xmm0 ; SSE-NEXT: mulsd %xmm2, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: mulsd %xmm2, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE-NEXT: mulsd %xmm3, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-NEXT: mulsd %xmm3, %xmm0 ; SSE-NEXT: mulsd %xmm3, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v8f64_one: ; AVX-LABEL: test_v8f64_one:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX-NEXT: vmulsd %xmm2, %xmm0, %xmm2 ; AVX-NEXT: vmulsd %xmm2, %xmm0, %xmm2
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX-NEXT: vmulsd %xmm0, %xmm2, %xmm2 ; AVX-NEXT: vmulsd %xmm0, %xmm2, %xmm2
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; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call double @llvm.vector.reduce.fmul.f64.v8f64(double 1.0, <8 x double> %a0) %1 = call double @llvm.vector.reduce.fmul.f64.v8f64(double 1.0, <8 x double> %a0)
ret double %1 ret double %1
} }
define double @test_v16f64_one(<16 x double> %a0) { define double @test_v16f64_one(<16 x double> %a0) {
; SSE-LABEL: test_v16f64_one: ; SSE-LABEL: test_v16f64_one:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm8 ; SSE-NEXT: movhlps {{.*#+}} xmm8 = xmm0[1],xmm8[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm8 = xmm8[1],xmm0[1]
; SSE-NEXT: mulsd %xmm8, %xmm0 ; SSE-NEXT: mulsd %xmm8, %xmm0
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: mulsd %xmm2, %xmm0 ; SSE-NEXT: mulsd %xmm2, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: mulsd %xmm2, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE-NEXT: mulsd %xmm3, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-NEXT: mulsd %xmm3, %xmm0 ; SSE-NEXT: mulsd %xmm3, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: mulsd %xmm4, %xmm0 ; SSE-NEXT: mulsd %xmm4, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: mulsd %xmm4, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm4[1],xmm1[1]
; SSE-NEXT: mulsd %xmm5, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1,1]
; SSE-NEXT: mulsd %xmm5, %xmm0 ; SSE-NEXT: mulsd %xmm5, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm5[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: mulsd %xmm6, %xmm0 ; SSE-NEXT: mulsd %xmm6, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: mulsd %xmm6, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm6[1],xmm1[1]
; SSE-NEXT: mulsd %xmm7, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm7 = xmm7[1,1]
; SSE-NEXT: mulsd %xmm7, %xmm0 ; SSE-NEXT: mulsd %xmm7, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm7[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v16f64_one: ; AVX-LABEL: test_v16f64_one:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm4 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm4 = xmm0[1,0]
; AVX-NEXT: vmulsd %xmm4, %xmm0, %xmm4 ; AVX-NEXT: vmulsd %xmm4, %xmm0, %xmm4
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX-NEXT: vmulsd %xmm0, %xmm4, %xmm4 ; AVX-NEXT: vmulsd %xmm0, %xmm4, %xmm4
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; SSE-LABEL: test_v8f64_undef: ; SSE-LABEL: test_v8f64_undef:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: mulsd %xmm2, %xmm0 ; SSE-NEXT: mulsd %xmm2, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: mulsd %xmm2, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE-NEXT: mulsd %xmm3, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-NEXT: mulsd %xmm3, %xmm0 ; SSE-NEXT: mulsd %xmm3, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v8f64_undef: ; AVX-LABEL: test_v8f64_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 ; AVX-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX-NEXT: vmulsd %xmm0, %xmm2, %xmm2 ; AVX-NEXT: vmulsd %xmm0, %xmm2, %xmm2
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; SSE-LABEL: test_v16f64_undef: ; SSE-LABEL: test_v16f64_undef:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE-NEXT: mulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: mulsd %xmm2, %xmm0 ; SSE-NEXT: mulsd %xmm2, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: mulsd %xmm2, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE-NEXT: mulsd %xmm3, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-NEXT: mulsd %xmm3, %xmm0 ; SSE-NEXT: mulsd %xmm3, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: mulsd %xmm4, %xmm0 ; SSE-NEXT: mulsd %xmm4, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: mulsd %xmm4, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm4[1],xmm1[1]
; SSE-NEXT: mulsd %xmm5, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1,1]
; SSE-NEXT: mulsd %xmm5, %xmm0 ; SSE-NEXT: mulsd %xmm5, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm5[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: mulsd %xmm6, %xmm0 ; SSE-NEXT: mulsd %xmm6, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1,1] ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: mulsd %xmm6, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm6[1],xmm1[1]
; SSE-NEXT: mulsd %xmm7, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm7 = xmm7[1,1]
; SSE-NEXT: mulsd %xmm7, %xmm0 ; SSE-NEXT: mulsd %xmm7, %xmm0
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm7[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v16f64_undef: ; AVX-LABEL: test_v16f64_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm4 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm4 = xmm0[1,0]
; AVX-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4 ; AVX-NEXT: vmulsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX-NEXT: vmulsd %xmm0, %xmm4, %xmm4 ; AVX-NEXT: vmulsd %xmm0, %xmm4, %xmm4
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llvm/test/CodeGen/X86/vector-rem.ll

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <4 x i32> %m ret <4 x i32> %m
} }
define <4 x float> @qux(<4 x float> %t, <4 x float> %u) nounwind { define <4 x float> @qux(<4 x float> %t, <4 x float> %u) nounwind {
; CHECK-LABEL: qux: ; CHECK-LABEL: qux:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: subq $72, %rsp ; CHECK-NEXT: subq $72, %rsp
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq fmodf@PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; CHECK-NEXT: callq fmodf@PLT ; CHECK-NEXT: callq fmodf@PLT
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: callq fmodf@PLT ; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: unpcklps (%rsp), %xmm0 # 16-byte Folded Reload ; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: callq fmodf@PLT ; CHECK-NEXT: callq fmodf@PLT
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1] ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
; CHECK-NEXT: callq fmodf@PLT ; CHECK-NEXT: callq fmodf@PLT
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload ; CHECK-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; CHECK-NEXT: # xmm1 = xmm1[0],mem[0] ; CHECK-NEXT: # xmm1 = xmm1[0],mem[0]
; CHECK-NEXT: movaps %xmm1, %xmm0 ; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: addq $72, %rsp ; CHECK-NEXT: addq $72, %rsp
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%m = frem <4 x float> %t, %u %m = frem <4 x float> %t, %u
ret <4 x float> %m ret <4 x float> %m
} }

llvm/test/CodeGen/X86/vector-shuffle-128-v2.ll

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; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm1[0,0] ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm1[0,0]
; AVX-NEXT: retq ; AVX-NEXT: retq
%shuffle = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 undef, i32 2> %shuffle = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 undef, i32 2>
ret <2 x double> %shuffle ret <2 x double> %shuffle
} }
define <2 x double> @shuffle_v2f64_3u(<2 x double> %a, <2 x double> %b) { define <2 x double> @shuffle_v2f64_3u(<2 x double> %a, <2 x double> %b) {
; SSE-LABEL: shuffle_v2f64_3u: ; SSE-LABEL: shuffle_v2f64_3u:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm1, %xmm0 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: shuffle_v2f64_3u: ; AVX-LABEL: shuffle_v2f64_3u:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm1[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm1[1,0]
; AVX-NEXT: retq ; AVX-NEXT: retq
%shuffle = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 3, i32 undef> %shuffle = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 3, i32 undef>
ret <2 x double> %shuffle ret <2 x double> %shuffle
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llvm/test/CodeGen/X86/widen_conv-3.ll

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; X86-SSE2-NEXT: pslld $16, %xmm2 ; X86-SSE2-NEXT: pslld $16, %xmm2
; X86-SSE2-NEXT: pandn %xmm2, %xmm1 ; X86-SSE2-NEXT: pandn %xmm2, %xmm1
; X86-SSE2-NEXT: por %xmm0, %xmm1 ; X86-SSE2-NEXT: por %xmm0, %xmm1
; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X86-SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] ; X86-SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; X86-SSE2-NEXT: psrad $24, %xmm0 ; X86-SSE2-NEXT: psrad $24, %xmm0
; X86-SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 ; X86-SSE2-NEXT: cvtdq2ps %xmm0, %xmm0
; X86-SSE2-NEXT: movss %xmm0, (%eax) ; X86-SSE2-NEXT: movss %xmm0, (%eax)
; X86-SSE2-NEXT: movaps %xmm0, %xmm1 ; X86-SSE2-NEXT: xorps %xmm1, %xmm1
; X86-SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; X86-SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; X86-SSE2-NEXT: movss %xmm1, 8(%eax) ; X86-SSE2-NEXT: movss %xmm1, 8(%eax)
; X86-SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; X86-SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; X86-SSE2-NEXT: movss %xmm0, 4(%eax) ; X86-SSE2-NEXT: movss %xmm0, 4(%eax)
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSE42-LABEL: convert_v3i8_to_v3f32: ; X86-SSE42-LABEL: convert_v3i8_to_v3f32:
; X86-SSE42: # %bb.0: # %entry ; X86-SSE42: # %bb.0: # %entry
; X86-SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax
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llvm/test/CodeGen/X86/widen_conv-4.ll

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; X86-SSE2-NEXT: pxor %xmm1, %xmm1 ; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
; X86-SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] ; X86-SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
; X86-SSE2-NEXT: cvtdq2ps %xmm2, %xmm2 ; X86-SSE2-NEXT: cvtdq2ps %xmm2, %xmm2
; X86-SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; X86-SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; X86-SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 ; X86-SSE2-NEXT: cvtdq2ps %xmm0, %xmm0
; X86-SSE2-NEXT: movups %xmm0, (%eax) ; X86-SSE2-NEXT: movups %xmm0, (%eax)
; X86-SSE2-NEXT: movss %xmm2, 16(%eax) ; X86-SSE2-NEXT: movss %xmm2, 16(%eax)
; X86-SSE2-NEXT: movaps %xmm2, %xmm0 ; X86-SSE2-NEXT: xorps %xmm0, %xmm0
; X86-SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm2[1] ; X86-SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm2[1],xmm0[1]
; X86-SSE2-NEXT: movss %xmm0, 24(%eax) ; X86-SSE2-NEXT: movss %xmm0, 24(%eax)
; X86-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1] ; X86-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,1,1]
; X86-SSE2-NEXT: movss %xmm2, 20(%eax) ; X86-SSE2-NEXT: movss %xmm2, 20(%eax)
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSE42-LABEL: convert_v7i16_v7f32: ; X86-SSE42-LABEL: convert_v7i16_v7f32:
; X86-SSE42: # %bb.0: # %entry ; X86-SSE42: # %bb.0: # %entry
; X86-SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-SSE2-NEXT: pslld $16, %xmm2 ; X86-SSE2-NEXT: pslld $16, %xmm2
; X86-SSE2-NEXT: pandn %xmm2, %xmm1 ; X86-SSE2-NEXT: pandn %xmm2, %xmm1
; X86-SSE2-NEXT: por %xmm0, %xmm1 ; X86-SSE2-NEXT: por %xmm0, %xmm1
; X86-SSE2-NEXT: pxor %xmm0, %xmm0 ; X86-SSE2-NEXT: pxor %xmm0, %xmm0
; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] ; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; X86-SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] ; X86-SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; X86-SSE2-NEXT: cvtdq2ps %xmm1, %xmm0 ; X86-SSE2-NEXT: cvtdq2ps %xmm1, %xmm0
; X86-SSE2-NEXT: movss %xmm0, (%eax) ; X86-SSE2-NEXT: movss %xmm0, (%eax)
; X86-SSE2-NEXT: movaps %xmm0, %xmm1 ; X86-SSE2-NEXT: xorps %xmm1, %xmm1
; X86-SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; X86-SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; X86-SSE2-NEXT: movss %xmm1, 8(%eax) ; X86-SSE2-NEXT: movss %xmm1, 8(%eax)
; X86-SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; X86-SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; X86-SSE2-NEXT: movss %xmm0, 4(%eax) ; X86-SSE2-NEXT: movss %xmm0, 4(%eax)
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSE42-LABEL: convert_v3i8_to_v3f32: ; X86-SSE42-LABEL: convert_v3i8_to_v3f32:
; X86-SSE42: # %bb.0: # %entry ; X86-SSE42: # %bb.0: # %entry
; X86-SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax
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