[DAGCombiner] Fold (sext/zext undef) -> 0 and aext(undef) -> undef.

[RKSimon]

LGTM

[jrtc27]

What's the justification for 0 rather than undef? That the high bits need to be guaranteed equal even for undef input?

[craig.topper]

In D124988#3494483, @jrtc27 wrote:

What's the justification for 0 rather than undef? That the high bits need to be guaranteed equal even for undef input?

For zext the high bits need to be 0 and for sext the high bits need to match. The result of the fold needs to produce a value that is possible given the undefined input we received. If we folded to undef that would be a larger set of values than were possible. We're allowed to assume a specific value for the input. So here we've assume the input is 0.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::foldSextSetcc(SDNode *N) {
   return SDValue();
 }
 
 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   EVT VT = N->getValueType(0);
   SDLoc DL(N);
 
+  // sext(undef) = 0 because the top bit will all be the same.
+  if (N0.isUndef())
+    return DAG.getConstant(0, DL, VT);
+
   if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes))
     return Res;
 
   // fold (sext (sext x)) -> (sext x)
   // fold (sext (aext x)) -> (sext x)
   if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
     return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N0.getOperand(0));
 
static SDValue widenCtPop(SDNode *Extend, SelectionDAG &DAG) {
   SDValue NewZext = DAG.getZExtOrTrunc(CtPop.getOperand(0), DL, VT);
   return DAG.getNode(ISD::CTPOP, DL, VT, NewZext);
 }
 
 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   EVT VT = N->getValueType(0);
 
+  // zext(undef) = 0
+  if (N0.isUndef())
+    return DAG.getConstant(0, SDLoc(N), VT);
+
   if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes))
     return Res;
 
   // fold (zext (zext x)) -> (zext x)
   // fold (zext (aext x)) -> (zext x)
   if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
     return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT,
                        N0.getOperand(0));
SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
 
   return SDValue();
 }
 
 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   EVT VT = N->getValueType(0);
 
+  // aext(undef) = undef
+  if (N0.isUndef())
+    return DAG.getUNDEF(VT);
+
   if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes))
     return Res;
 
   // fold (aext (aext x)) -> (aext x)
   // fold (aext (zext x)) -> (zext x)
   // fold (aext (sext x)) -> (sext x)
   if (N0.getOpcode() == ISD::ANY_EXTEND  ||
       N0.getOpcode() == ISD::ZERO_EXTEND ||

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll

 ; SI: s_endpgm
 define amdgpu_kernel void @test_class_0_f64(i32 addrspace(1)* %out, double %a) #0 {
   %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 0) #1
   %sext = sext i1 %result to i32
   store i32 %sext, i32 addrspace(1)* %out, align 4
   ret void
 }
 
-; FIXME: Why is the extension still here?
 ; SI-LABEL: {{^}}test_class_undef_f32:
 ; SI-NOT: v_cmp_class
-; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, -1,
-; SI: buffer_store_dword
+; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0
+; SI: buffer_store_dword [[RESULT]]
+; SI: s_endpgm
 define amdgpu_kernel void @test_class_undef_f32(i32 addrspace(1)* %out, float %a, i32 %b) #0 {
   %result = call i1 @llvm.amdgcn.class.f32(float undef, i32 %b) #1
   %sext = sext i1 %result to i32
   store i32 %sext, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; SI-LABEL: {{^}}test_fold_and_ord:

llvm/test/CodeGen/RISCV/min-max.ll

 ; ZBB-LABEL: umax_same_op_i32:
 ; ZBB:       # %bb.0:
 ; ZBB-NEXT:    ret
   %c = call i32 @llvm.umax.i32(i32 %a, i32 %a)
   ret i32 %c
 }
 
 ; Tests with undef operands. These should fold to undef for RV32 or 0 for RV64.
-; FIXME: The RV64 cases are hitting pr55178.
 
 define signext i32 @smin_undef_i32() {
-; NOZBB-LABEL: smin_undef_i32:
-; NOZBB:       # %bb.0:
-; NOZBB-NEXT:    ret
+; RV32I-LABEL: smin_undef_i32:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    ret
 ;
-; ZBB-LABEL: smin_undef_i32:
-; ZBB:       # %bb.0:
-; ZBB-NEXT:    ret
+; RV64I-LABEL: smin_undef_i32:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a0, 0
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: smin_undef_i32:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: smin_undef_i32:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    li a0, 0
+; RV64ZBB-NEXT:    ret
   %c = call i32 @llvm.smin.i32(i32 undef, i32 undef)
   ret i32 %c
 }
 
 define signext i32 @smax_undef_i32() {
-; NOZBB-LABEL: smax_undef_i32:
-; NOZBB:       # %bb.0:
-; NOZBB-NEXT:    ret
+; RV32I-LABEL: smax_undef_i32:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    ret
 ;
-; ZBB-LABEL: smax_undef_i32:
-; ZBB:       # %bb.0:
-; ZBB-NEXT:    ret
+; RV64I-LABEL: smax_undef_i32:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a0, 0
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: smax_undef_i32:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: smax_undef_i32:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    li a0, 0
+; RV64ZBB-NEXT:    ret
   %c = call i32 @llvm.smax.i32(i32 undef, i32 undef)
   ret i32 %c
 }
 
 define signext i32 @umin_undef_i32() {
-; NOZBB-LABEL: umin_undef_i32:
-; NOZBB:       # %bb.0:
-; NOZBB-NEXT:    ret
+; RV32I-LABEL: umin_undef_i32:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    ret
 ;
-; ZBB-LABEL: umin_undef_i32:
-; ZBB:       # %bb.0:
-; ZBB-NEXT:    ret
+; RV64I-LABEL: umin_undef_i32:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a0, 0
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: umin_undef_i32:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: umin_undef_i32:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    li a0, 0
+; RV64ZBB-NEXT:    ret
   %c = call i32 @llvm.umin.i32(i32 undef, i32 undef)
   ret i32 %c
 }
 
 define signext i32 @umax_undef_i32() {
-; NOZBB-LABEL: umax_undef_i32:
-; NOZBB:       # %bb.0:
-; NOZBB-NEXT:    ret
+; RV32I-LABEL: umax_undef_i32:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    ret
 ;
-; ZBB-LABEL: umax_undef_i32:
-; ZBB:       # %bb.0:
-; ZBB-NEXT:    ret
+; RV64I-LABEL: umax_undef_i32:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a0, 0
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: umax_undef_i32:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: umax_undef_i32:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    li a0, 0
+; RV64ZBB-NEXT:    ret
   %c = call i32 @llvm.umax.i32(i32 undef, i32 undef)
   ret i32 %c
 }