Avoid 8 and 16bit switch conditions on x86

[MatzeB]

Summary

This adds a TargetLoweringBase::getSwitchConditionType callback to give targets a chance to control the type used in CodeGenPrepare::optimizeSwitchInst.

Implement callback for X86 to avoid i8 and i16 types where possible as they often incur extra zero-extensions.

This is NFC for non-X86 targets.

[MatzeB]

Add a comment.

[craig.topper]

llvm/lib/CodeGen/TargetLoweringBase.cpp

1614

If we just gave targets control over RegType here would that be enough?

[MatzeB]

llvm/lib/CodeGen/TargetLoweringBase.cpp

1614

The callback is used by CodeGenPrepare though which deals with llvm IR and rather has Type*s than MVTs...

[craig.topper]

llvm/lib/CodeGen/TargetLoweringBase.cpp

1614

Ok could we return ExtType from the target and use ExtType to calculate RegWidth for if on 1617?

Realy, I'm wondering why we had to move all of the code into TargetLowering and duplicate Argument attributes checking in X86. Or is there some subtle difference that prevents us from sharing the Argument attribute handling.

[MatzeB]

llvm/lib/CodeGen/TargetLoweringBase.cpp

1614

If you prefer we can share the logic starting at line 1632 (deciding between ZExt/SExt and the argument handling) simplifying the X86 callback with the drawback that targets can no longer opt-out of that logic (admittedly I don't know why they would want to opt-out, so I don't care too deeply).

[MatzeB]

llvm/lib/CodeGen/TargetLoweringBase.cpp

1614

Hmm we need an MVT if we want to have the isSExtCheaperThanZExt in the shared code as there's no equivalent callback for Type*...

[craig.topper]

llvm/lib/CodeGen/TargetLoweringBase.cpp

1607

I think we would typically pass ExtOp by reference so you can't pass null.

1614

I guess it might be better to give targets the control. There was a patch proposing to ignore the attributes on X86. D122963.

[MatzeB]

Address review comments: Keep more code shared.

[MatzeB]

llvm/lib/CodeGen/TargetLoweringBase.cpp

1607

I think we would typically pass ExtOp by reference so you can't pass null.

No longer relevant as the parameter is gone now, but FWIW:

I prefer pointers for "out parameters" because that makes it clearer when readining the calling code that there is an "out parameter".

i.e. foobar(&baz) has a clear signal that baz is probably an "out parameter", for foobar(baz) it's easy to miss this when baz happens to be a writable reference.

I find that more valuable than having an assurance that nobody passes nullptr...

[MatzeB]

llvm/lib/CodeGen/TargetLoweringBase.cpp

1614

Oh, I just switched it to a more minimal version of this patch. Should I go back to the old version?

[MatzeB]

llvm/lib/CodeGen/TargetLoweringBase.cpp

1614

There was a patch proposing to ignore the attributes on X86

FWIW: While working on this I did originally not replicate the logic in the X86 callback and the result was worse at least for the llvm unit-tests.

I think ultimately we had a global instruction selection and wouldn't need to rely on IR->IR transformations upfront... (because I think for optimal results you want to control the overflow-check independently of the value used for the jump-table address calculations; it also depends about what sorts of extensions and truncations the target gets for free; etc.).

But yeah I think for the LLVM of today this patch here at least improves some cases.

[craig.topper]

LGTM with what I think is a typo in the X86 override fixed.

llvm/lib/CodeGen/TargetLoweringBase.cpp

1607

Yeah that is an unfortunate annoyance of the syntax. I was basing on what I usually see done in code. Our coding standards probably say nothing about this.

1614

We can keep the minimal patch. If the x86 patch were to go through and ignore the attribute, it would only be for i8/i16 types. Extending those to i32 isn't free or more costly no matter which we choose.

llvm/lib/Target/X86/X86ISelLowering.cpp

33724

the -> they?

[spatel]

llvm/include/llvm/CodeGen/TargetLowering.h

1226

I'd put the "preferred" in the name itself to make the logic clear:

getPreferredSwitchCondType(...)

llvm/lib/Target/X86/X86ISelLowering.cpp

33726

Nit: can remove braces for one-line 'if'

[MatzeB]

address review feedback

llvm/include/llvm/CodeGen/TargetLowering.h

#include "llvm/IR/ConstrainedOps.def"
   }
 
   /// Return true if lowering to a jump table is suitable for a set of case
   /// clusters which may contain \p NumCases cases, \p Range range of values.
   virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
                                       uint64_t Range, ProfileSummaryInfo *PSI,
                                       BlockFrequencyInfo *BFI) const;
 
+  /// Returns preferred type for switch condition.
+  virtual MVT getPreferredSwitchConditionType(LLVMContext &Context,
+                                              EVT ConditionVT) const;
+
   /// Return true if lowering to a bit test is suitable for a set of case
   /// clusters which contains \p NumDests unique destinations, \p Low and
   /// \p High as its lowest and highest case values, and expects \p NumCmps
   /// case value comparisons. Check if the number of destinations, comparison
   /// metric, and range are all suitable.
   bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
                              const APInt &Low, const APInt &High,
                              const DataLayout &DL) const {

llvm/lib/CodeGen/CodeGenPrepare.cpp

bool CodeGenPrepare::tryToSinkFreeOperands(Instruction *I) {
   return Changed;
 }
 
 bool CodeGenPrepare::optimizeSwitchInst(SwitchInst *SI) {
   Value *Cond = SI->getCondition();
   Type *OldType = Cond->getType();
   LLVMContext &Context = Cond->getContext();
   EVT OldVT = TLI->getValueType(*DL, OldType);
-  MVT RegType = TLI->getRegisterType(Context, OldVT);
+  MVT RegType = TLI->getPreferredSwitchConditionType(Context, OldVT);
   unsigned RegWidth = RegType.getSizeInBits();
 
   if (RegWidth <= cast<IntegerType>(OldType)->getBitWidth())
     return false;
 
   // If the register width is greater than the type width, expand the condition
   // of the switch instruction and each case constant to the width of the
   // register. By widening the type of the switch condition, subsequent

llvm/lib/CodeGen/TargetLoweringBase.cpp

bool TargetLoweringBase::isSuitableForJumpTable(const SwitchInst *SI,
   const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
 
   // Check whether the number of cases is small enough and
   // the range is dense enough for a jump table.
   return (OptForSize || Range <= MaxJumpTableSize) &&
          (NumCases * 100 >= Range * MinDensity);
 }
 
+MVT TargetLoweringBase::getPreferredSwitchConditionType(LLVMContext &Context,
+                                                        EVT ConditionVT) const {
+  return getRegisterType(Context, ConditionVT);
+}
+
 /// Get the EVTs and ArgFlags collections that represent the legalized return
 /// type of the given function.  This does not require a DAG or a return value,
 /// and is suitable for use before any DAGs for the function are constructed.
 /// TODO: Move this out of TargetLowering.cpp.
 void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType,
                          AttributeList attr,
                          SmallVectorImpl<ISD::OutputArg> &Outs,
                          const TargetLowering &TLI, const DataLayout &DL) {
   SmallVector<EVT, 4> ValueVTs;
   ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
   unsigned NumValues = ValueVTs.size();
   if (NumValues == 0) return;
 

llvm/lib/Target/X86/X86ISelLowering.h

public:
     /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
     /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
     /// constant pool entry.
     bool isVectorClearMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
 
     /// Returns true if lowering to a jump table is allowed.
     bool areJTsAllowed(const Function *Fn) const override;
 
+    MVT getPreferredSwitchConditionType(LLVMContext &Context,
+                                        EVT ConditionVT) const override;
+
     /// If true, then instruction selection should
     /// seek to shrink the FP constant of the specified type to a smaller type
     /// in order to save space and / or reduce runtime.
     bool ShouldShrinkFPConstant(EVT VT) const override;
 
     /// Return true if we believe it is correct and profitable to reduce the
     /// load node to a smaller type.
     bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,

llvm/lib/Target/X86/X86ISelLowering.cpp

bool X86TargetLowering::areJTsAllowed(const Function *Fn) const {
   // If the subtarget is using thunks, we need to not generate jump tables.
   if (Subtarget.useIndirectThunkBranches())
     return false;
 
   // Otherwise, fallback on the generic logic.
   return TargetLowering::areJTsAllowed(Fn);
 }
 
+MVT X86TargetLowering::getPreferredSwitchConditionType(LLVMContext &Context,
+                                                       EVT ConditionVT) const {
+  // Avoid 8 and 16 bit types because they increase the chance for unnecessary
+  // zero-extensions.
+  if (ConditionVT.getSizeInBits() < 32)
+    return MVT::i32;
+  return TargetLoweringBase::getPreferredSwitchConditionType(Context,
+                                                             ConditionVT);
+}
+
 //===----------------------------------------------------------------------===//
 //                           X86 Scheduler Hooks
 //===----------------------------------------------------------------------===//
 
 // Returns true if EFLAG is consumed after this iterator in the rest of the
 // basic block or any successors of the basic block.
 static bool isEFLAGSLiveAfter(MachineBasicBlock::iterator Itr,
                               MachineBasicBlock *BB) {

llvm/test/CodeGen/X86/2008-12-01-loop-iv-used-outside-loop.ll

 ; CHECK-NEXT:    jmp LBB0_2
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_1: ## %bb
 ; CHECK-NEXT:    ## in Loop: Header=BB0_2 Depth=1
 ; CHECK-NEXT:    incl %eax
 ; CHECK-NEXT:  LBB0_2: ## %bb1
 ; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    movzbl (%eax), %ecx
-; CHECK-NEXT:    cmpb $12, %cl
+; CHECK-NEXT:    cmpl $12, %ecx
 ; CHECK-NEXT:    je LBB0_1
 ; CHECK-NEXT:  ## %bb.3: ## %bb1
 ; CHECK-NEXT:    ## in Loop: Header=BB0_2 Depth=1
-; CHECK-NEXT:    cmpb $42, %cl
+; CHECK-NEXT:    cmpl $42, %ecx
 ; CHECK-NEXT:    je LBB0_1
 ; CHECK-NEXT:  ## %bb.4: ## %bb3
 ; CHECK-NEXT:    movb $4, 2(%eax)
 ; CHECK-NEXT:    retl
 entry:
   br label %bb1
 
 bb:   ; preds = %bb1, %bb1

llvm/test/CodeGen/X86/SwitchLowering.ll

 ; CHECK-NEXT:    .cfi_offset %edi, -8
 ; CHECK-NEXT:    xorl %edi, %edi
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB0_1: # %bb
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    movzbl (%esi,%edi), %eax
 ; CHECK-NEXT:    incl %edi
-; CHECK-NEXT:    cmpb $120, %al
+; CHECK-NEXT:    cmpl $120, %eax
 ; CHECK-NEXT:    je .LBB0_3
 ; CHECK-NEXT:  # %bb.2: # %bb
 ; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
-; CHECK-NEXT:    testb %al, %al
+; CHECK-NEXT:    testl %eax, %eax
 ; CHECK-NEXT:    jne .LBB0_1
 ; CHECK-NEXT:  .LBB0_3: # %bb7
 ; CHECK-NEXT:    movzbl %al, %eax
 ; CHECK-NEXT:    pushl %eax
 ; CHECK-NEXT:    .cfi_adjust_cfa_offset 4
 ; CHECK-NEXT:    calll foo@PLT
 ; CHECK-NEXT:    addl $4, %esp
 ; CHECK-NEXT:    .cfi_adjust_cfa_offset -4

llvm/test/CodeGen/X86/conditional-tailcall.ll

 ; CHECK32-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK32-NEXT:    .cfi_offset %esi, -20
 ; CHECK32-NEXT:    .cfi_offset %edi, -16
 ; CHECK32-NEXT:    .cfi_offset %ebx, -12
 ; CHECK32-NEXT:    .cfi_offset %ebp, -8
 ; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x20]
 ; CHECK32-NEXT:    movl (%eax), %eax # encoding: [0x8b,0x00]
 ; CHECK32-NEXT:    movl -24(%eax), %edx # encoding: [0x8b,0x50,0xe8]
-; CHECK32-NEXT:    leal (%eax,%edx), %ebp # encoding: [0x8d,0x2c,0x10]
+; CHECK32-NEXT:    leal (%eax,%edx), %ecx # encoding: [0x8d,0x0c,0x10]
 ; CHECK32-NEXT:    xorl %ebx, %ebx # encoding: [0x31,0xdb]
 ; CHECK32-NEXT:    pushl $2 # encoding: [0x6a,0x02]
 ; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
 ; CHECK32-NEXT:    popl %esi # encoding: [0x5e]
 ; CHECK32-NEXT:    .cfi_adjust_cfa_offset -4
 ; CHECK32-NEXT:    xorl %edi, %edi # encoding: [0x31,0xff]
 ; CHECK32-NEXT:    incl %edi # encoding: [0x47]
 ; CHECK32-NEXT:  .LBB3_1: # %for.cond
 ; CHECK32-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK32-NEXT:    testl %edx, %edx # encoding: [0x85,0xd2]
-; CHECK32-NEXT:    je .LBB3_13 # encoding: [0x74,A]
-; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_13-1, kind: FK_PCRel_1
+; CHECK32-NEXT:    je .LBB3_14 # encoding: [0x74,A]
+; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_14-1, kind: FK_PCRel_1
 ; CHECK32-NEXT:  # %bb.2: # %for.body
 ; CHECK32-NEXT:    # in Loop: Header=BB3_1 Depth=1
 ; CHECK32-NEXT:    cmpl $2, %ebx # encoding: [0x83,0xfb,0x02]
-; CHECK32-NEXT:    je .LBB3_11 # encoding: [0x74,A]
-; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_11-1, kind: FK_PCRel_1
+; CHECK32-NEXT:    je .LBB3_12 # encoding: [0x74,A]
+; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_12-1, kind: FK_PCRel_1
 ; CHECK32-NEXT:  # %bb.3: # %for.body
 ; CHECK32-NEXT:    # in Loop: Header=BB3_1 Depth=1
 ; CHECK32-NEXT:    cmpl $1, %ebx # encoding: [0x83,0xfb,0x01]
-; CHECK32-NEXT:    je .LBB3_9 # encoding: [0x74,A]
-; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_9-1, kind: FK_PCRel_1
+; CHECK32-NEXT:    je .LBB3_10 # encoding: [0x74,A]
+; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1
 ; CHECK32-NEXT:  # %bb.4: # %for.body
 ; CHECK32-NEXT:    # in Loop: Header=BB3_1 Depth=1
 ; CHECK32-NEXT:    testl %ebx, %ebx # encoding: [0x85,0xdb]
-; CHECK32-NEXT:    jne .LBB3_10 # encoding: [0x75,A]
-; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1
+; CHECK32-NEXT:    jne .LBB3_11 # encoding: [0x75,A]
+; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_11-1, kind: FK_PCRel_1
 ; CHECK32-NEXT:  # %bb.5: # %sw.bb
 ; CHECK32-NEXT:    # in Loop: Header=BB3_1 Depth=1
-; CHECK32-NEXT:    movzbl (%eax), %ecx # encoding: [0x0f,0xb6,0x08]
-; CHECK32-NEXT:    cmpl $43, %ecx # encoding: [0x83,0xf9,0x2b]
+; CHECK32-NEXT:    movzbl (%eax), %ebp # encoding: [0x0f,0xb6,0x28]
+; CHECK32-NEXT:    cmpl $43, %ebp # encoding: [0x83,0xfd,0x2b]
 ; CHECK32-NEXT:    movl %edi, %ebx # encoding: [0x89,0xfb]
-; CHECK32-NEXT:    je .LBB3_10 # encoding: [0x74,A]
-; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1
+; CHECK32-NEXT:    je .LBB3_11 # encoding: [0x74,A]
+; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_11-1, kind: FK_PCRel_1
 ; CHECK32-NEXT:  # %bb.6: # %sw.bb
 ; CHECK32-NEXT:    # in Loop: Header=BB3_1 Depth=1
-; CHECK32-NEXT:    cmpb $45, %cl # encoding: [0x80,0xf9,0x2d]
+; CHECK32-NEXT:    cmpl $45, %ebp # encoding: [0x83,0xfd,0x2d]
 ; CHECK32-NEXT:    movl %edi, %ebx # encoding: [0x89,0xfb]
-; CHECK32-NEXT:    je .LBB3_10 # encoding: [0x74,A]
-; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1
-; CHECK32-NEXT:    jmp .LBB3_7 # encoding: [0xeb,A]
-; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_7-1, kind: FK_PCRel_1
-; CHECK32-NEXT:  .LBB3_11: # %sw.bb22
+; CHECK32-NEXT:    je .LBB3_11 # encoding: [0x74,A]
+; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_11-1, kind: FK_PCRel_1
+; CHECK32-NEXT:  # %bb.7: # %if.else
+; CHECK32-NEXT:    # in Loop: Header=BB3_1 Depth=1
+; CHECK32-NEXT:    addl $-48, %ebp # encoding: [0x83,0xc5,0xd0]
+; CHECK32-NEXT:    cmpl $10, %ebp # encoding: [0x83,0xfd,0x0a]
+; CHECK32-NEXT:    jmp .LBB3_8 # encoding: [0xeb,A]
+; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_8-1, kind: FK_PCRel_1
+; CHECK32-NEXT:  .LBB3_12: # %sw.bb22
 ; CHECK32-NEXT:    # in Loop: Header=BB3_1 Depth=1
-; CHECK32-NEXT:    movzbl (%eax), %ecx # encoding: [0x0f,0xb6,0x08]
-; CHECK32-NEXT:    addl $-48, %ecx # encoding: [0x83,0xc1,0xd0]
-; CHECK32-NEXT:    cmpl $10, %ecx # encoding: [0x83,0xf9,0x0a]
+; CHECK32-NEXT:    movzbl (%eax), %ebx # encoding: [0x0f,0xb6,0x18]
+; CHECK32-NEXT:    addl $-48, %ebx # encoding: [0x83,0xc3,0xd0]
+; CHECK32-NEXT:    cmpl $10, %ebx # encoding: [0x83,0xfb,0x0a]
 ; CHECK32-NEXT:    movl %esi, %ebx # encoding: [0x89,0xf3]
-; CHECK32-NEXT:    jb .LBB3_10 # encoding: [0x72,A]
-; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1
-; CHECK32-NEXT:    jmp .LBB3_12 # encoding: [0xeb,A]
-; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_12-1, kind: FK_PCRel_1
-; CHECK32-NEXT:  .LBB3_9: # %sw.bb14
+; CHECK32-NEXT:    jb .LBB3_11 # encoding: [0x72,A]
+; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_11-1, kind: FK_PCRel_1
+; CHECK32-NEXT:    jmp .LBB3_13 # encoding: [0xeb,A]
+; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_13-1, kind: FK_PCRel_1
+; CHECK32-NEXT:  .LBB3_10: # %sw.bb14
 ; CHECK32-NEXT:    # in Loop: Header=BB3_1 Depth=1
-; CHECK32-NEXT:    movzbl (%eax), %ecx # encoding: [0x0f,0xb6,0x08]
-; CHECK32-NEXT:  .LBB3_7: # %if.else
+; CHECK32-NEXT:    movzbl (%eax), %ebx # encoding: [0x0f,0xb6,0x18]
+; CHECK32-NEXT:    addl $-48, %ebx # encoding: [0x83,0xc3,0xd0]
+; CHECK32-NEXT:    cmpl $10, %ebx # encoding: [0x83,0xfb,0x0a]
+; CHECK32-NEXT:  .LBB3_8: # %if.else
 ; CHECK32-NEXT:    # in Loop: Header=BB3_1 Depth=1
-; CHECK32-NEXT:    addl $-48, %ecx # encoding: [0x83,0xc1,0xd0]
-; CHECK32-NEXT:    cmpl $10, %ecx # encoding: [0x83,0xf9,0x0a]
 ; CHECK32-NEXT:    movl %esi, %ebx # encoding: [0x89,0xf3]
-; CHECK32-NEXT:    jae .LBB3_8 # encoding: [0x73,A]
-; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_8-1, kind: FK_PCRel_1
-; CHECK32-NEXT:  .LBB3_10: # %for.inc
+; CHECK32-NEXT:    jae .LBB3_9 # encoding: [0x73,A]
+; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_9-1, kind: FK_PCRel_1
+; CHECK32-NEXT:  .LBB3_11: # %for.inc
 ; CHECK32-NEXT:    # in Loop: Header=BB3_1 Depth=1
 ; CHECK32-NEXT:    incl %eax # encoding: [0x40]
 ; CHECK32-NEXT:    decl %edx # encoding: [0x4a]
 ; CHECK32-NEXT:    jmp .LBB3_1 # encoding: [0xeb,A]
 ; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_1-1, kind: FK_PCRel_1
-; CHECK32-NEXT:  .LBB3_13:
+; CHECK32-NEXT:  .LBB3_14:
 ; CHECK32-NEXT:    cmpl $2, %ebx # encoding: [0x83,0xfb,0x02]
 ; CHECK32-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
-; CHECK32-NEXT:    jmp .LBB3_14 # encoding: [0xeb,A]
-; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_14-1, kind: FK_PCRel_1
-; CHECK32-NEXT:  .LBB3_8:
+; CHECK32-NEXT:    jmp .LBB3_15 # encoding: [0xeb,A]
+; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_15-1, kind: FK_PCRel_1
+; CHECK32-NEXT:  .LBB3_9:
 ; CHECK32-NEXT:    xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK32-NEXT:  .LBB3_14: # %cleanup.thread
+; CHECK32-NEXT:  .LBB3_15: # %cleanup.thread
 ; CHECK32-NEXT:    # kill: def $al killed $al killed $eax
 ; CHECK32-NEXT:    addl $12, %esp # encoding: [0x83,0xc4,0x0c]
 ; CHECK32-NEXT:    .cfi_def_cfa_offset 20
-; CHECK32-NEXT:  .LBB3_15: # %cleanup.thread
+; CHECK32-NEXT:  .LBB3_16: # %cleanup.thread
 ; CHECK32-NEXT:    popl %esi # encoding: [0x5e]
 ; CHECK32-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK32-NEXT:    popl %edi # encoding: [0x5f]
 ; CHECK32-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK32-NEXT:    popl %ebx # encoding: [0x5b]
 ; CHECK32-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK32-NEXT:    popl %ebp # encoding: [0x5d]
 ; CHECK32-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK32-NEXT:    retl # encoding: [0xc3]
-; CHECK32-NEXT:  .LBB3_12: # %if.else28
+; CHECK32-NEXT:  .LBB3_13: # %if.else28
 ; CHECK32-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK32-NEXT:    subl $8, %esp # encoding: [0x83,0xec,0x08]
 ; CHECK32-NEXT:    .cfi_adjust_cfa_offset 8
-; CHECK32-NEXT:    pushl %ebp # encoding: [0x55]
+; CHECK32-NEXT:    pushl %ecx # encoding: [0x51]
 ; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
 ; CHECK32-NEXT:    pushl %eax # encoding: [0x50]
 ; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
 ; CHECK32-NEXT:    calll _Z20isValidIntegerSuffixN9__gnu_cxx17__normal_iteratorIPKcSsEES3_ # encoding: [0xe8,A,A,A,A]
 ; CHECK32-NEXT:    # fixup A - offset: 1, value: _Z20isValidIntegerSuffixN9__gnu_cxx17__normal_iteratorIPKcSsEES3_-4, kind: FK_PCRel_4
 ; CHECK32-NEXT:    addl $28, %esp # encoding: [0x83,0xc4,0x1c]
 ; CHECK32-NEXT:    .cfi_adjust_cfa_offset -28
-; CHECK32-NEXT:    jmp .LBB3_15 # encoding: [0xeb,A]
-; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_15-1, kind: FK_PCRel_1
+; CHECK32-NEXT:    jmp .LBB3_16 # encoding: [0xeb,A]
+; CHECK32-NEXT:    # fixup A - offset: 1, value: .LBB3_16-1, kind: FK_PCRel_1
 ;
 ; CHECK64-LABEL: pr31257:
 ; CHECK64:       # %bb.0: # %entry
 ; CHECK64-NEXT:    movq (%rdi), %rdi # encoding: [0x48,0x8b,0x3f]
 ; CHECK64-NEXT:    movq -24(%rdi), %rax # encoding: [0x48,0x8b,0x47,0xe8]
 ; CHECK64-NEXT:    leaq (%rdi,%rax), %rsi # encoding: [0x48,0x8d,0x34,0x07]
 ; CHECK64-NEXT:    xorl %ecx, %ecx # encoding: [0x31,0xc9]
 ; CHECK64-NEXT:    pushq $2 # encoding: [0x6a,0x02]

 ; CHECK64-NEXT:    # in Loop: Header=BB3_1 Depth=1
 ; CHECK64-NEXT:    movzbl (%rdi), %edx # encoding: [0x0f,0xb6,0x17]
 ; CHECK64-NEXT:    cmpl $43, %edx # encoding: [0x83,0xfa,0x2b]
 ; CHECK64-NEXT:    movl %r8d, %ecx # encoding: [0x44,0x89,0xc1]
 ; CHECK64-NEXT:    je .LBB3_11 # encoding: [0x74,A]
 ; CHECK64-NEXT:    # fixup A - offset: 1, value: .LBB3_11-1, kind: FK_PCRel_1
 ; CHECK64-NEXT:  # %bb.6: # %sw.bb
 ; CHECK64-NEXT:    # in Loop: Header=BB3_1 Depth=1
-; CHECK64-NEXT:    cmpb $45, %dl # encoding: [0x80,0xfa,0x2d]
+; CHECK64-NEXT:    cmpl $45, %edx # encoding: [0x83,0xfa,0x2d]
 ; CHECK64-NEXT:    movl %r8d, %ecx # encoding: [0x44,0x89,0xc1]
 ; CHECK64-NEXT:    je .LBB3_11 # encoding: [0x74,A]
 ; CHECK64-NEXT:    # fixup A - offset: 1, value: .LBB3_11-1, kind: FK_PCRel_1
 ; CHECK64-NEXT:  # %bb.7: # %if.else
 ; CHECK64-NEXT:    # in Loop: Header=BB3_1 Depth=1
 ; CHECK64-NEXT:    addl $-48, %edx # encoding: [0x83,0xc2,0xd0]
 ; CHECK64-NEXT:    cmpl $10, %edx # encoding: [0x83,0xfa,0x0a]
 ; CHECK64-NEXT:    jmp .LBB3_9 # encoding: [0xeb,A]

 ; WIN64-NEXT:    # in Loop: Header=BB3_1 Depth=1
 ; WIN64-NEXT:    movzbl (%rcx), %r9d # encoding: [0x44,0x0f,0xb6,0x09]
 ; WIN64-NEXT:    cmpl $43, %r9d # encoding: [0x41,0x83,0xf9,0x2b]
 ; WIN64-NEXT:    movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
 ; WIN64-NEXT:    je .LBB3_10 # encoding: [0x74,A]
 ; WIN64-NEXT:    # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1
 ; WIN64-NEXT:  # %bb.6: # %sw.bb
 ; WIN64-NEXT:    # in Loop: Header=BB3_1 Depth=1
-; WIN64-NEXT:    cmpb $45, %r9b # encoding: [0x41,0x80,0xf9,0x2d]
+; WIN64-NEXT:    cmpl $45, %r9d # encoding: [0x41,0x83,0xf9,0x2d]
 ; WIN64-NEXT:    je .LBB3_10 # encoding: [0x74,A]
 ; WIN64-NEXT:    # fixup A - offset: 1, value: .LBB3_10-1, kind: FK_PCRel_1
 ; WIN64-NEXT:    jmp .LBB3_8 # encoding: [0xeb,A]
 ; WIN64-NEXT:    # fixup A - offset: 1, value: .LBB3_8-1, kind: FK_PCRel_1
 ; WIN64-NEXT:  .LBB3_7: # %sw.bb14
 ; WIN64-NEXT:    # in Loop: Header=BB3_1 Depth=1
 ; WIN64-NEXT:    movzbl (%rcx), %r9d # encoding: [0x44,0x0f,0xb6,0x09]
 ; WIN64-NEXT:  .LBB3_8: # %if.else

llvm/test/CodeGen/X86/switch-phi-const.ll

 }
 
 @g64 = global i64 0
 @effect64 = global i64 0
 
 define void @switch_trunc_phi_const(i32 %x) {
 ; CHECK-LABEL: switch_trunc_phi_const:
 ; CHECK:       # %bb.0: # %bb0
-; CHECK-NEXT:    movl $3895, %r8d # imm = 0xF37
+; CHECK-NEXT:    movzbl %dil, %r8d
+; CHECK-NEXT:    movl $3895, %ecx # imm = 0xF37
 ; CHECK-NEXT:    movl $42, %esi
 ; CHECK-NEXT:    movl $13, %edx
-; CHECK-NEXT:    movl $5, %eax
-; CHECK-NEXT:    movl $1, %ecx
-; CHECK-NEXT:    decb %dil
-; CHECK-NEXT:    movzbl %dil, %edi
-; CHECK-NEXT:    cmpb $54, %dil
+; CHECK-NEXT:    movl $5, %edi
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    decl %r8d
+; CHECK-NEXT:    cmpl $54, %r8d
 ; CHECK-NEXT:    ja .LBB1_8
 ; CHECK-NEXT:  # %bb.1: # %bb0
-; CHECK-NEXT:    jmpq *.LJTI1_0(,%rdi,8)
+; CHECK-NEXT:    jmpq *.LJTI1_0(,%r8,8)
 ; CHECK-NEXT:  .LBB1_8: # %default
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB1_2: # %case_1_loop
-; CHECK-NEXT:    movq effect64@GOTPCREL(%rip), %rax
-; CHECK-NEXT:    movq $1, (%rax)
-; CHECK-NEXT:    movq %rcx, %rax
-; CHECK-NEXT:  .LBB1_3: # %case_5
 ; CHECK-NEXT:    movq effect64@GOTPCREL(%rip), %rcx
-; CHECK-NEXT:    movq $5, (%rcx)
-; CHECK-NEXT:    movq %rax, %rdx
+; CHECK-NEXT:    movq $1, (%rcx)
+; CHECK-NEXT:    movq %rax, %rdi
+; CHECK-NEXT:  .LBB1_3: # %case_5
+; CHECK-NEXT:    movq effect64@GOTPCREL(%rip), %rax
+; CHECK-NEXT:    movq $5, (%rax)
+; CHECK-NEXT:    movq %rdi, %rdx
 ; CHECK-NEXT:  .LBB1_4: # %case_13
 ; CHECK-NEXT:    movq effect64@GOTPCREL(%rip), %rax
 ; CHECK-NEXT:    movq $13, (%rax)
 ; CHECK-NEXT:    movq %rdx, %rsi
 ; CHECK-NEXT:  .LBB1_5: # %case_42
 ; CHECK-NEXT:    movq effect64@GOTPCREL(%rip), %rax
 ; CHECK-NEXT:    movq %rsi, (%rax)
-; CHECK-NEXT:    movl $55, %r8d
+; CHECK-NEXT:    movl $55, %ecx
 ; CHECK-NEXT:  .LBB1_6: # %case_55
 ; CHECK-NEXT:    movq effect64@GOTPCREL(%rip), %rax
-; CHECK-NEXT:    movq %r8, (%rax)
+; CHECK-NEXT:    movq %rcx, (%rax)
 ; CHECK-NEXT:  .LBB1_7: # %case_7
 ; CHECK-NEXT:    movq g64@GOTPCREL(%rip), %rax
-; CHECK-NEXT:    movq (%rax), %rcx
-; CHECK-NEXT:    movq effect64@GOTPCREL(%rip), %rax
-; CHECK-NEXT:    movq $7, (%rax)
+; CHECK-NEXT:    movq (%rax), %rax
+; CHECK-NEXT:    movq effect64@GOTPCREL(%rip), %rcx
+; CHECK-NEXT:    movq $7, (%rcx)
 ; CHECK-NEXT:    jmp .LBB1_2
 bb0:
   %x_trunc = trunc i32 %x to i8
   switch i8 %x_trunc, label %default [
   i8 1, label %case_1_loop
   i8 5, label %case_5
   i8 7, label %case_7
   i8 13, label %case_13

llvm/test/CodeGen/X86/switch.ll

 }
 
 
 ; Don't infloop on jump tables where the upper bound is the max value of the
 ; input type (in this case 127).
 define void @int_max_table_cluster(i8 %x) {
 ; CHECK-LABEL: int_max_table_cluster:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addb $64, %dil
-; CHECK-NEXT:    cmpb $-65, %dil
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    cmpb $-9, %dil
 ; CHECK-NEXT:    ja .LBB15_4
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    movzbl %dil, %eax
 ; CHECK-NEXT:    jmpq *.LJTI15_0(,%rax,8)
 ; CHECK-NEXT:  .LBB15_2: # %bb0
 ; CHECK-NEXT:    xorl %edi, %edi
 ; CHECK-NEXT:    jmp g@PLT # TAILCALL
 ; CHECK-NEXT:  .LBB15_3: # %bb3

 }
 
 
 ; Don't assert due to truncating the bitwidth (64) to i4 when checking
 ; that the bit-test range fits in a word.
 define void @pr23738(i4 %x) {
 ; CHECK-LABEL: pr23738:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
 ; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    andb $15, %al
 ; CHECK-NEXT:    cmpb $11, %al
 ; CHECK-NEXT:    ja .LBB23_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    andl $15, %edi
 ; CHECK-NEXT:    movl $2051, %eax # imm = 0x803
-; CHECK-NEXT:    btq %rdi, %rax
+; CHECK-NEXT:    btl %edi, %eax
 ; CHECK-NEXT:    jae .LBB23_2
 ; CHECK-NEXT:  # %bb.3: # %bb1
 ; CHECK-NEXT:    movl $1, %edi
 ; CHECK-NEXT:    jmp g@PLT # TAILCALL
 ; CHECK-NEXT:  .LBB23_2: # %bb0
 ; CHECK-NEXT:    xorl %edi, %edi
 ; CHECK-NEXT:    jmp g@PLT # TAILCALL
 ;

 
 
 ; A switch over a small type (i8) should be extended to avoid truncation
 ; instructions.
 define void @switch_i8(i32 %a) {
 ; CHECK-LABEL: switch_i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
-; CHECK-NEXT:    andb $127, %dil
+; CHECK-NEXT:    andl $127, %edi
 ; CHECK-NEXT:    leal -1(%rdi), %eax
-; CHECK-NEXT:    cmpb $8, %al
+; CHECK-NEXT:    cmpl $8, %eax
 ; CHECK-NEXT:    ja .LBB26_1
 ; CHECK-NEXT:  # %bb.10:
-; CHECK-NEXT:    movzbl %al, %eax
 ; CHECK-NEXT:    jmpq *.LJTI26_0(,%rax,8)
 ; CHECK-NEXT:  .LBB26_4: # %bb0
 ; CHECK-NEXT:    xorl %edi, %edi
 ; CHECK-NEXT:    jmp g@PLT # TAILCALL
 ; CHECK-NEXT:  .LBB26_1:
-; CHECK-NEXT:    cmpb $13, %dil
+; CHECK-NEXT:    cmpl $13, %edi
 ; CHECK-NEXT:    je .LBB26_8
 ; CHECK-NEXT:  # %bb.2:
-; CHECK-NEXT:    cmpb $42, %dil
+; CHECK-NEXT:    cmpl $42, %edi
 ; CHECK-NEXT:    jne .LBB26_9
 ; CHECK-NEXT:  # %bb.3: # %bb5
 ; CHECK-NEXT:    movl $5, %edi
 ; CHECK-NEXT:    jmp g@PLT # TAILCALL
 ; CHECK-NEXT:  .LBB26_9: # %return
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB26_5: # %bb1
 ; CHECK-NEXT:    movl $1, %edi

llvm/test/CodeGen/X86/tail-dup-multiple-latch-loop.ll

 ; CHECK-NEXT:    movl %esi, %eax
 ; CHECK-NEXT:    jmp .LBB1_1
 ; CHECK-NEXT:  .LBB1_7: # in Loop: Header=BB1_1 Depth=1
 ; CHECK-NEXT:    addl $7, %eax
 ; CHECK-NEXT:    incq %rdi
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB1_1: # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    movzbl (%rdi), %ecx
-; CHECK-NEXT:    decb %cl
-; CHECK-NEXT:    cmpb $5, %cl
+; CHECK-NEXT:    decl %ecx
+; CHECK-NEXT:    cmpl $5, %ecx
 ; CHECK-NEXT:    ja .LBB1_9
 ; CHECK-NEXT:  # %bb.2: # in Loop: Header=BB1_1 Depth=1
-; CHECK-NEXT:    movzbl %cl, %ecx
 ; CHECK-NEXT:    jmpq *.LJTI1_0(,%rcx,8)
 ; CHECK-NEXT:  .LBB1_3: # in Loop: Header=BB1_1 Depth=1
 ; CHECK-NEXT:    incl %eax
 ; CHECK-NEXT:    incq %rdi
 ; CHECK-NEXT:    jmp .LBB1_1
 ; CHECK-NEXT:  .LBB1_4: # in Loop: Header=BB1_1 Depth=1
 ; CHECK-NEXT:    decl %eax
 ; CHECK-NEXT:    incq %rdi

llvm/test/CodeGen/X86/tail-opts.ll

 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:  .LBB3_16: # %lvalue_p.exit4
 ; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:    jne .LBB3_9
 ; CHECK-NEXT:  # %bb.17: # %lvalue_p.exit4
 ; CHECK-NEXT:    testb %bl, %bl
 ; CHECK-NEXT:  .LBB3_10: # %bb2.i3
 ; CHECK-NEXT:    movq 8(%rax), %rax
-; CHECK-NEXT:    movb 16(%rax), %cl
+; CHECK-NEXT:    movzbl 16(%rax), %ecx
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpb $23, %cl
+; CHECK-NEXT:    cmpl $23, %ecx
 ; CHECK-NEXT:    je .LBB3_16
 ; CHECK-NEXT:  # %bb.11: # %bb2.i3
-; CHECK-NEXT:    cmpb $16, %cl
+; CHECK-NEXT:    cmpl $16, %ecx
 ; CHECK-NEXT:    je .LBB3_16
 ; CHECK-NEXT:    jmp .LBB3_9
 ; CHECK-NEXT:  .LBB3_13: # %bb2.i.i2
 ; CHECK-NEXT:    movq 8(%rax), %rax
-; CHECK-NEXT:    movb 16(%rax), %cl
+; CHECK-NEXT:    movzbl 16(%rax), %ecx
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpb $16, %cl
+; CHECK-NEXT:    cmpl $16, %ecx
 ; CHECK-NEXT:    je .LBB3_16
 ; CHECK-NEXT:  # %bb.14: # %bb2.i.i2
-; CHECK-NEXT:    cmpb $23, %cl
+; CHECK-NEXT:    cmpl $23, %ecx
 ; CHECK-NEXT:    je .LBB3_16
 ; CHECK-NEXT:    jmp .LBB3_9
 entry:
   %tmp4 = load i8, i8* null, align 8                  ; <i8> [#uses=3]
   switch i8 %tmp4, label %bb3 [
     i8 18, label %bb
   ]
 

llvm/test/Transforms/CodeGenPrepare/X86/widen_switch.ll

 ;; x86 is chosen to show the transform when 8-bit and 16-bit registers are available.
 
 ; RUN: opt < %s -codegenprepare -S -mtriple=x86_64-unknown-unknown    | FileCheck %s --check-prefix=X86
 ; RUN: opt < %s -debugify -codegenprepare -S -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=DEBUG
 
-; No change for x86 because 16-bit registers are part of the architecture.
+; X86 prefers i32 over i16 for address calculation.
 
 define i32 @widen_switch_i16(i32 %a)  {
 entry:
   %trunc = trunc i32 %a to i16
   switch i16 %trunc, label %sw.default [
     i16 1, label %sw.bb0
     i16 -1, label %sw.bb1
   ]
 
 sw.bb0:
   br label %return
 
 sw.bb1:
   br label %return
 
 sw.default:
   br label %return
 
 return:
   %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
   ret i32 %retval
 
 ; X86-LABEL: @widen_switch_i16(
 ; X86:       %trunc = trunc i32 %a to i16
-; X86-NEXT:  switch i16 %trunc, label %sw.default [
-; X86-NEXT:    i16 1, label %sw.bb0
-; X86-NEXT:    i16 -1, label %sw.bb1
+; X86-NEXT:  %0 = zext i16 %trunc to i32
+; X86-NEXT:  switch i32 %0, label %sw.default [
+; X86-NEXT:    i32 1, label %sw.bb0
+; X86-NEXT:    i32 65535, label %sw.bb1
 }
 
 ; Widen to 32-bit from a smaller, non-native type.
 
 define i32 @widen_switch_i17(i32 %a)  {
 entry:
   %trunc = trunc i32 %a to i17
   switch i17 %trunc, label %sw.default [

 sw.default:
   br label %return
 
 return:
   %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
   ret i32 %retval
 
 ; X86-LABEL: @widen_switch_i16_sext(
-; X86:       %0 = sext i2 %a to i8
-; X86-NEXT:  switch i8 %0, label %sw.default [
-; X86-NEXT:    i8 1, label %sw.bb0
-; X86-NEXT:    i8 -1, label %sw.bb1
+; X86:       %0 = sext i2 %a to i32
+; X86-NEXT:  switch i32 %0, label %sw.default [
+; X86-NEXT:    i32 1, label %sw.bb0
+; X86-NEXT:    i32 -1, label %sw.bb1
 }