[RISCV] Fix incorrect codegen for masked vmsge{u}.vx with mask agnostic.

[khchen]

Summary

The result was totally wrong.
We could use mask undisturbed result to emulate the mask agnostic result.

[craig.topper]

LGTM

llvm/test/CodeGen/RISCV/rvv/masked-tama.ll

1435

Will we eventually be able to use 'ma' here?

[kito-cheng]

llvm/test/CodeGen/RISCV/rvv/masked-tama.ll

1435

Sounds like that what we can optimized in vsetvli insertion?

[khchen]

llvm/test/CodeGen/RISCV/rvv/masked-tama.ll

1435

Yes, I think I could try to add ForceMaskAgnostic or optimize InsertVSETVLI in follow-up patch.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

#undef CASE_VMXOR_VMANDN_VMOR_OPCODES
 
       // Mask needs to be copied to V0.
       SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL,
                                            RISCV::V0, Mask, SDValue());
       SDValue Glue = Chain.getValue(1);
       SDValue V0 = CurDAG->getRegister(RISCV::V0, VT);
 
       // Otherwise use
-      // vmslt{u}.vx vd, va, x, v0.t; if mask policy is agnostic.
+      // vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
+      // The result is mask undisturbed.
+      // We use the same instructions to emulate mask agnostic behavior, because
+      // the agnostic result can be either undisturbed or all 1.
       SDValue Cmp = SDValue(
           CurDAG->getMachineNode(VMSLTMaskOpcode, DL, VT,
                                  {MaskedOff, Src1, Src2, V0, VL, SEW, Glue}),
           0);
-      if (MaskedOff.isUndef()) {
-        ReplaceNode(Node, Cmp.getNode());
-        return;
-      }
-      // Need vmxor.mm vd, vd, v0 to assign inactive value.
+      // vmxor.mm vd, vd, v0 is used to update active value.
       ReplaceNode(Node, CurDAG->getMachineNode(VMXOROpcode, DL, VT,
                                                {Cmp, Mask, VL, MaskSEW}));
       return;
     }
     case Intrinsic::riscv_vsetvli_opt:
     case Intrinsic::riscv_vsetvlimax_opt:
       return selectVSETVLI(Node);
     }

llvm/test/CodeGen/RISCV/rvv/masked-tama.ll

 ; RV32-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
 ; RV32-NEXT:    vmsle.vv v0, v9, v8, v0.t
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; RV64-NEXT:    vmslt.vx v0, v8, a0, v0.t
+; RV64-NEXT:    vmslt.vx v8, v8, a0, v0.t
+; RV64-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
+; RV64-NEXT:    vmxor.mm v0, v8, v0
 ; RV64-NEXT:    ret
 entry:
   %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
     <vscale x 1 x i1> undef,
     <vscale x 1 x i64> %0,
     i64 %1,
     <vscale x 1 x i1> %2,
     iXLen %3)