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Differential D124424

[RISCV] Fix alias printing for vmnot.m
ClosedPublic

Authored by craig.topper on Apr 25 2022, 4:53 PM.

Details

Reviewers
khchen
kito-cheng
frasercrmck
rogfer01
arcbbb
Commits
rG8631a5e712a4: [RISCV] Fix alias printing for vmnot.m
Summary

By clearing the HasDummyMask flag from mask register binary operations
and mask load/store.

HasDummyMask was causing an extra operand to get appended when
converting from MachineInstr to MCInst. This extra operand doesn't
appear in the assembly string so was mostly ignored, but it prevented
the alias instruction printing from working correctly.

Diff Detail

Event Timeline

craig.topper created this revision.Apr 25 2022, 4:53 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 25 2022, 4:53 PM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 27 others. · View Herald Transcript
craig.topper requested review of this revision.Apr 25 2022, 4:53 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 25 2022, 4:53 PM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
craig.topper updated this revision to Diff 425063.Apr 25 2022, 5:09 PM

Fix extra operand for VLM and VSM too.

craig.topper edited the summary of this revision. (Show Details)Apr 25 2022, 5:10 PM
Harbormaster completed remote builds in B161279: Diff 425063.Apr 25 2022, 6:24 PM
craig.topper added a reviewer: arcbbb.Apr 27 2022, 9:18 PM
craig.topper retitled this revision from [RISCV] Fix alias print for vmnot.m to [RISCV] Fix alias printing for vmnot.m.
arcbbb accepted this revision.Apr 27 2022, 10:32 PM

LGTM. Thanks for the fix!

This revision is now accepted and ready to land.Apr 27 2022, 10:32 PM
khchen added a comment.Apr 28 2022, 2:37 AM

LGTM too.

This revision was landed with ongoing or failed builds.Apr 28 2022, 8:36 AM
Closed by commit rG8631a5e712a4: [RISCV] Fix alias printing for vmnot.m (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG8631a5e712a4: [RISCV] Fix alias printing for vmnot.m.

Revision Contents

Diff 425061

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 1,028 Lines • ▼ Show 20 Linesclass VPseudoUnaryAnyMask<VReg RetClass,
let HasSEWOp = 1; let HasSEWOp = 1;
let HasMergeOp = 1; let HasMergeOp = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
} }
class VPseudoBinaryNoMask<VReg RetClass, class VPseudoBinaryNoMask<VReg RetClass,
VReg Op1Class, VReg Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
string Constraint> : string Constraint,
int DummyMask = 1> :
Pseudo<(outs RetClass:$rd), Pseudo<(outs RetClass:$rd),
(ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>, (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo { RISCVVPseudo {
let mayLoad = 0; let mayLoad = 0;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
let Constraints = Constraint; let Constraints = Constraint;
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
let HasDummyMask = 1; let HasDummyMask = DummyMask;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
} }
class VPseudoBinaryNoMaskTU<VReg RetClass, class VPseudoBinaryNoMaskTU<VReg RetClass,
VReg Op1Class, VReg Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
string Constraint> : string Constraint> :
Pseudo<(outs RetClass:$rd), Pseudo<(outs RetClass:$rd),
▲ Show 20 Lines • Show All 804 Lines • ▼ Show 20 Lines
multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, string Constraint = ""> { multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, string Constraint = ""> {
foreach m = MxList in foreach m = MxList in
defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>; defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
} }
multiclass VPseudoVALU_MM { multiclass VPseudoVALU_MM {
foreach m = MxList in foreach m = MxList in
let VLMul = m.value in { let VLMul = m.value in {
def "_MM_" # m.MX : VPseudoBinaryNoMask<VR, VR, VR, "">, def "_MM_" # m.MX : VPseudoBinaryNoMask<VR, VR, VR, "", /*DummyMask*/0>,
Sched<[WriteVMALUV, ReadVMALUV, ReadVMALUV]>; Sched<[WriteVMALUV, ReadVMALUV, ReadVMALUV]>;
} }
} }
// We use earlyclobber here due to // We use earlyclobber here due to
// * The destination EEW is smaller than the source EEW and the overlap is // * The destination EEW is smaller than the source EEW and the overlap is
// in the lowest-numbered part of the source register group is legal. // in the lowest-numbered part of the source register group is legal.
// Otherwise, it is illegal. // Otherwise, it is illegal.
▲ Show 20 Lines • Show All 3,639 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll

Show First 20 Lines • Show All 250 Lines • ▼ Show 20 Lines
define void @fcmp_ule_vv_v32f16(<32 x half>* %x, <32 x half>* %y, <32 x i1>* %z) { define void @fcmp_ule_vv_v32f16(<32 x half>* %x, <32 x half>* %y, <32 x i1>* %z) {
; CHECK-LABEL: fcmp_ule_vv_v32f16: ; CHECK-LABEL: fcmp_ule_vv_v32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32 ; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vle16.v v12, (a1) ; CHECK-NEXT: vle16.v v12, (a1)
; CHECK-NEXT: vmflt.vv v16, v12, v8 ; CHECK-NEXT: vmflt.vv v16, v12, v8
; CHECK-NEXT: vmnand.mm v8, v16, v16 ; CHECK-NEXT: vmnot.m v8, v16
; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <32 x half>, <32 x half>* %x %a = load <32 x half>, <32 x half>* %x
%b = load <32 x half>, <32 x half>* %y %b = load <32 x half>, <32 x half>* %y
%c = fcmp ule <32 x half> %a, %b %c = fcmp ule <32 x half> %a, %b
store <32 x i1> %c, <32 x i1>* %z store <32 x i1> %c, <32 x i1>* %z
ret void ret void
} }
Show All 17 Lines
define void @fcmp_uge_vv_v16f32(<16 x float>* %x, <16 x float>* %y, <16 x i1>* %z) { define void @fcmp_uge_vv_v16f32(<16 x float>* %x, <16 x float>* %y, <16 x i1>* %z) {
; CHECK-LABEL: fcmp_uge_vv_v16f32: ; CHECK-LABEL: fcmp_uge_vv_v16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vle32.v v12, (a1) ; CHECK-NEXT: vle32.v v12, (a1)
; CHECK-NEXT: vmflt.vv v16, v8, v12 ; CHECK-NEXT: vmflt.vv v16, v8, v12
; CHECK-NEXT: vmnand.mm v8, v16, v16 ; CHECK-NEXT: vmnot.m v8, v16
; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x %a = load <16 x float>, <16 x float>* %x
%b = load <16 x float>, <16 x float>* %y %b = load <16 x float>, <16 x float>* %y
%c = fcmp uge <16 x float> %a, %b %c = fcmp uge <16 x float> %a, %b
store <16 x i1> %c, <16 x i1>* %z store <16 x i1> %c, <16 x i1>* %z
ret void ret void
} }
Show All 16 Lines
define void @fcmp_ult_vv_v8f64(<8 x double>* %x, <8 x double>* %y, <8 x i1>* %z) { define void @fcmp_ult_vv_v8f64(<8 x double>* %x, <8 x double>* %y, <8 x i1>* %z) {
; CHECK-LABEL: fcmp_ult_vv_v8f64: ; CHECK-LABEL: fcmp_ult_vv_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v12, (a1) ; CHECK-NEXT: vle64.v v12, (a1)
; CHECK-NEXT: vmfle.vv v16, v12, v8 ; CHECK-NEXT: vmfle.vv v16, v12, v8
; CHECK-NEXT: vmnand.mm v8, v16, v16 ; CHECK-NEXT: vmnot.m v8, v16
; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x %a = load <8 x double>, <8 x double>* %x
%b = load <8 x double>, <8 x double>* %y %b = load <8 x double>, <8 x double>* %y
%c = fcmp ult <8 x double> %a, %b %c = fcmp ult <8 x double> %a, %b
store <8 x i1> %c, <8 x i1>* %z store <8 x i1> %c, <8 x i1>* %z
ret void ret void
} }
Show All 17 Lines
define void @fcmp_ugt_vv_v64f16(<64 x half>* %x, <64 x half>* %y, <64 x i1>* %z) { define void @fcmp_ugt_vv_v64f16(<64 x half>* %x, <64 x half>* %y, <64 x i1>* %z) {
; CHECK-LABEL: fcmp_ugt_vv_v64f16: ; CHECK-LABEL: fcmp_ugt_vv_v64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 64 ; CHECK-NEXT: li a3, 64
; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vle16.v v16, (a1) ; CHECK-NEXT: vle16.v v16, (a1)
; CHECK-NEXT: vmfle.vv v24, v8, v16 ; CHECK-NEXT: vmfle.vv v24, v8, v16
; CHECK-NEXT: vmnand.mm v8, v24, v24 ; CHECK-NEXT: vmnot.m v8, v24
; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <64 x half>, <64 x half>* %x %a = load <64 x half>, <64 x half>* %x
%b = load <64 x half>, <64 x half>* %y %b = load <64 x half>, <64 x half>* %y
%c = fcmp ugt <64 x half> %a, %b %c = fcmp ugt <64 x half> %a, %b
store <64 x i1> %c, <64 x i1>* %z store <64 x i1> %c, <64 x i1>* %z
ret void ret void
} }
▲ Show 20 Lines • Show All 387 Lines • ▼ Show 20 Lines
define void @fcmp_ule_vf_v32f16(<32 x half>* %x, half %y, <32 x i1>* %z) { define void @fcmp_ule_vf_v32f16(<32 x half>* %x, half %y, <32 x i1>* %z) {
; CHECK-LABEL: fcmp_ule_vf_v32f16: ; CHECK-LABEL: fcmp_ule_vf_v32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 32 ; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmfgt.vf v12, v8, fa0 ; CHECK-NEXT: vmfgt.vf v12, v8, fa0
; CHECK-NEXT: vmnand.mm v8, v12, v12 ; CHECK-NEXT: vmnot.m v8, v12
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <32 x half>, <32 x half>* %x %a = load <32 x half>, <32 x half>* %x
%b = insertelement <32 x half> poison, half %y, i32 0 %b = insertelement <32 x half> poison, half %y, i32 0
%c = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> zeroinitializer %c = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> zeroinitializer
%d = fcmp ule <32 x half> %a, %c %d = fcmp ule <32 x half> %a, %c
store <32 x i1> %d, <32 x i1>* %z store <32 x i1> %d, <32 x i1>* %z
ret void ret void
Show All 17 Lines
} }
define void @fcmp_uge_vf_v16f32(<16 x float>* %x, float %y, <16 x i1>* %z) { define void @fcmp_uge_vf_v16f32(<16 x float>* %x, float %y, <16 x i1>* %z) {
; CHECK-LABEL: fcmp_uge_vf_v16f32: ; CHECK-LABEL: fcmp_uge_vf_v16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmflt.vf v12, v8, fa0 ; CHECK-NEXT: vmflt.vf v12, v8, fa0
; CHECK-NEXT: vmnand.mm v8, v12, v12 ; CHECK-NEXT: vmnot.m v8, v12
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x %a = load <16 x float>, <16 x float>* %x
%b = insertelement <16 x float> poison, float %y, i32 0 %b = insertelement <16 x float> poison, float %y, i32 0
%c = shufflevector <16 x float> %b, <16 x float> poison, <16 x i32> zeroinitializer %c = shufflevector <16 x float> %b, <16 x float> poison, <16 x i32> zeroinitializer
%d = fcmp uge <16 x float> %a, %c %d = fcmp uge <16 x float> %a, %c
store <16 x i1> %d, <16 x i1>* %z store <16 x i1> %d, <16 x i1>* %z
ret void ret void
Show All 16 Lines
} }
define void @fcmp_ult_vf_v8f64(<8 x double>* %x, double %y, <8 x i1>* %z) { define void @fcmp_ult_vf_v8f64(<8 x double>* %x, double %y, <8 x i1>* %z) {
; CHECK-LABEL: fcmp_ult_vf_v8f64: ; CHECK-LABEL: fcmp_ult_vf_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfge.vf v12, v8, fa0 ; CHECK-NEXT: vmfge.vf v12, v8, fa0
; CHECK-NEXT: vmnand.mm v8, v12, v12 ; CHECK-NEXT: vmnot.m v8, v12
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x %a = load <8 x double>, <8 x double>* %x
%b = insertelement <8 x double> poison, double %y, i32 0 %b = insertelement <8 x double> poison, double %y, i32 0
%c = shufflevector <8 x double> %b, <8 x double> poison, <8 x i32> zeroinitializer %c = shufflevector <8 x double> %b, <8 x double> poison, <8 x i32> zeroinitializer
%d = fcmp ult <8 x double> %a, %c %d = fcmp ult <8 x double> %a, %c
store <8 x i1> %d, <8 x i1>* %z store <8 x i1> %d, <8 x i1>* %z
ret void ret void
Show All 17 Lines
define void @fcmp_ugt_vf_v64f16(<64 x half>* %x, half %y, <64 x i1>* %z) { define void @fcmp_ugt_vf_v64f16(<64 x half>* %x, half %y, <64 x i1>* %z) {
; CHECK-LABEL: fcmp_ugt_vf_v64f16: ; CHECK-LABEL: fcmp_ugt_vf_v64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 64 ; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmfle.vf v16, v8, fa0 ; CHECK-NEXT: vmfle.vf v16, v8, fa0
; CHECK-NEXT: vmnand.mm v8, v16, v16 ; CHECK-NEXT: vmnot.m v8, v16
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <64 x half>, <64 x half>* %x %a = load <64 x half>, <64 x half>* %x
%b = insertelement <64 x half> poison, half %y, i32 0 %b = insertelement <64 x half> poison, half %y, i32 0
%c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer %c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
%d = fcmp ugt <64 x half> %a, %c %d = fcmp ugt <64 x half> %a, %c
store <64 x i1> %d, <64 x i1>* %z store <64 x i1> %d, <64 x i1>* %z
ret void ret void
▲ Show 20 Lines • Show All 390 Lines • ▼ Show 20 Lines
define void @fcmp_ule_fv_v32f16(<32 x half>* %x, half %y, <32 x i1>* %z) { define void @fcmp_ule_fv_v32f16(<32 x half>* %x, half %y, <32 x i1>* %z) {
; CHECK-LABEL: fcmp_ule_fv_v32f16: ; CHECK-LABEL: fcmp_ule_fv_v32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 32 ; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmflt.vf v12, v8, fa0 ; CHECK-NEXT: vmflt.vf v12, v8, fa0
; CHECK-NEXT: vmnand.mm v8, v12, v12 ; CHECK-NEXT: vmnot.m v8, v12
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <32 x half>, <32 x half>* %x %a = load <32 x half>, <32 x half>* %x
%b = insertelement <32 x half> poison, half %y, i32 0 %b = insertelement <32 x half> poison, half %y, i32 0
%c = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> zeroinitializer %c = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> zeroinitializer
%d = fcmp ule <32 x half> %c, %a %d = fcmp ule <32 x half> %c, %a
store <32 x i1> %d, <32 x i1>* %z store <32 x i1> %d, <32 x i1>* %z
ret void ret void
Show All 17 Lines
} }
define void @fcmp_uge_fv_v16f32(<16 x float>* %x, float %y, <16 x i1>* %z) { define void @fcmp_uge_fv_v16f32(<16 x float>* %x, float %y, <16 x i1>* %z) {
; CHECK-LABEL: fcmp_uge_fv_v16f32: ; CHECK-LABEL: fcmp_uge_fv_v16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfgt.vf v12, v8, fa0 ; CHECK-NEXT: vmfgt.vf v12, v8, fa0
; CHECK-NEXT: vmnand.mm v8, v12, v12 ; CHECK-NEXT: vmnot.m v8, v12
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x %a = load <16 x float>, <16 x float>* %x
%b = insertelement <16 x float> poison, float %y, i32 0 %b = insertelement <16 x float> poison, float %y, i32 0
%c = shufflevector <16 x float> %b, <16 x float> poison, <16 x i32> zeroinitializer %c = shufflevector <16 x float> %b, <16 x float> poison, <16 x i32> zeroinitializer
%d = fcmp uge <16 x float> %c, %a %d = fcmp uge <16 x float> %c, %a
store <16 x i1> %d, <16 x i1>* %z store <16 x i1> %d, <16 x i1>* %z
ret void ret void
Show All 16 Lines
} }
define void @fcmp_ult_fv_v8f64(<8 x double>* %x, double %y, <8 x i1>* %z) { define void @fcmp_ult_fv_v8f64(<8 x double>* %x, double %y, <8 x i1>* %z) {
; CHECK-LABEL: fcmp_ult_fv_v8f64: ; CHECK-LABEL: fcmp_ult_fv_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfle.vf v12, v8, fa0 ; CHECK-NEXT: vmfle.vf v12, v8, fa0
; CHECK-NEXT: vmnand.mm v8, v12, v12 ; CHECK-NEXT: vmnot.m v8, v12
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x %a = load <8 x double>, <8 x double>* %x
%b = insertelement <8 x double> poison, double %y, i32 0 %b = insertelement <8 x double> poison, double %y, i32 0
%c = shufflevector <8 x double> %b, <8 x double> poison, <8 x i32> zeroinitializer %c = shufflevector <8 x double> %b, <8 x double> poison, <8 x i32> zeroinitializer
%d = fcmp ult <8 x double> %c, %a %d = fcmp ult <8 x double> %c, %a
store <8 x i1> %d, <8 x i1>* %z store <8 x i1> %d, <8 x i1>* %z
ret void ret void
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define void @fcmp_ugt_fv_v64f16(<64 x half>* %x, half %y, <64 x i1>* %z) { define void @fcmp_ugt_fv_v64f16(<64 x half>* %x, half %y, <64 x i1>* %z) {
; CHECK-LABEL: fcmp_ugt_fv_v64f16: ; CHECK-LABEL: fcmp_ugt_fv_v64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 64 ; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmfge.vf v16, v8, fa0 ; CHECK-NEXT: vmfge.vf v16, v8, fa0
; CHECK-NEXT: vmnand.mm v8, v16, v16 ; CHECK-NEXT: vmnot.m v8, v16
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <64 x half>, <64 x half>* %x %a = load <64 x half>, <64 x half>* %x
%b = insertelement <64 x half> poison, half %y, i32 0 %b = insertelement <64 x half> poison, half %y, i32 0
%c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer %c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
%d = fcmp ugt <64 x half> %c, %a %d = fcmp ugt <64 x half> %c, %a
store <64 x i1> %d, <64 x i1>* %z store <64 x i1> %d, <64 x i1>* %z
ret void ret void
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
} }
define void @not_v64i1(<64 x i1>* %x, <64 x i1>* %y) { define void @not_v64i1(<64 x i1>* %x, <64 x i1>* %y) {
; CHECK-LABEL: not_v64i1: ; CHECK-LABEL: not_v64i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vlm.v v8, (a0) ; CHECK-NEXT: vlm.v v8, (a0)
; CHECK-NEXT: vmnand.mm v8, v8, v8 ; CHECK-NEXT: vmnot.m v8, v8
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x %a = load <64 x i1>, <64 x i1>* %x
%b = load <64 x i1>, <64 x i1>* %y %b = load <64 x i1>, <64 x i1>* %y
%c = xor <64 x i1> %a, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1> %c = xor <64 x i1> %a, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
store <64 x i1> %c, <64 x i1>* %x store <64 x i1> %c, <64 x i1>* %x
ret void ret void
} }
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
declare i1 @llvm.vp.reduce.and.v1i1(i1, <1 x i1>, <1 x i1>, i32) declare i1 @llvm.vp.reduce.and.v1i1(i1, <1 x i1>, <1 x i1>, i32)
define signext i1 @vpreduce_and_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) { define signext i1 @vpreduce_and_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_v1i1: ; CHECK-LABEL: vpreduce_and_v1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmnot.m v9, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a1, v9, v0.t ; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl) %r = call i1 @llvm.vp.reduce.and.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl)
ret i1 %r ret i1 %r
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} }
declare i1 @llvm.vp.reduce.and.v2i1(i1, <2 x i1>, <2 x i1>, i32) declare i1 @llvm.vp.reduce.and.v2i1(i1, <2 x i1>, <2 x i1>, i32)
define signext i1 @vpreduce_and_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) { define signext i1 @vpreduce_and_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_v2i1: ; CHECK-LABEL: vpreduce_and_v2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmnot.m v9, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a1, v9, v0.t ; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl) %r = call i1 @llvm.vp.reduce.and.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl)
ret i1 %r ret i1 %r
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} }
declare i1 @llvm.vp.reduce.and.v4i1(i1, <4 x i1>, <4 x i1>, i32) declare i1 @llvm.vp.reduce.and.v4i1(i1, <4 x i1>, <4 x i1>, i32)
define signext i1 @vpreduce_and_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) { define signext i1 @vpreduce_and_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_v4i1: ; CHECK-LABEL: vpreduce_and_v4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmnot.m v9, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a1, v9, v0.t ; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl) %r = call i1 @llvm.vp.reduce.and.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl)
ret i1 %r ret i1 %r
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} }
declare i1 @llvm.vp.reduce.and.v8i1(i1, <8 x i1>, <8 x i1>, i32) declare i1 @llvm.vp.reduce.and.v8i1(i1, <8 x i1>, <8 x i1>, i32)
define signext i1 @vpreduce_and_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) { define signext i1 @vpreduce_and_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_v8i1: ; CHECK-LABEL: vpreduce_and_v8i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmnot.m v9, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a1, v9, v0.t ; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl) %r = call i1 @llvm.vp.reduce.and.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl)
ret i1 %r ret i1 %r
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} }
declare i1 @llvm.vp.reduce.and.v10i1(i1, <10 x i1>, <10 x i1>, i32) declare i1 @llvm.vp.reduce.and.v10i1(i1, <10 x i1>, <10 x i1>, i32)
define signext i1 @vpreduce_and_v10i1(i1 signext %s, <10 x i1> %v, <10 x i1> %m, i32 zeroext %evl) { define signext i1 @vpreduce_and_v10i1(i1 signext %s, <10 x i1> %v, <10 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_v10i1: ; CHECK-LABEL: vpreduce_and_v10i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmnot.m v9, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a1, v9, v0.t ; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.v10i1(i1 %s, <10 x i1> %v, <10 x i1> %m, i32 %evl) %r = call i1 @llvm.vp.reduce.and.v10i1(i1 %s, <10 x i1> %v, <10 x i1> %m, i32 %evl)
ret i1 %r ret i1 %r
} }
declare i1 @llvm.vp.reduce.and.v16i1(i1, <16 x i1>, <16 x i1>, i32) declare i1 @llvm.vp.reduce.and.v16i1(i1, <16 x i1>, <16 x i1>, i32)
define signext i1 @vpreduce_and_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) { define signext i1 @vpreduce_and_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_v16i1: ; CHECK-LABEL: vpreduce_and_v16i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmnot.m v9, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a1, v9, v0.t ; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl) %r = call i1 @llvm.vp.reduce.and.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl)
ret i1 %r ret i1 %r
} }
declare i1 @llvm.vp.reduce.and.v256i1(i1, <256 x i1>, <256 x i1>, i32) declare i1 @llvm.vp.reduce.and.v256i1(i1, <256 x i1>, <256 x i1>, i32)
define signext i1 @vpreduce_and_v256i1(i1 signext %s, <256 x i1> %v, <256 x i1> %m, i32 zeroext %evl) { define signext i1 @vpreduce_and_v256i1(i1 signext %s, <256 x i1> %v, <256 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_v256i1: ; CHECK-LABEL: vpreduce_and_v256i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, a1, -128 ; CHECK-NEXT: addi a2, a1, -128
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: li a3, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: bltu a1, a2, .LBB14_2 ; CHECK-NEXT: bltu a1, a2, .LBB14_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a3, a2 ; CHECK-NEXT: mv a3, a2
; CHECK-NEXT: .LBB14_2: ; CHECK-NEXT: .LBB14_2:
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu
; CHECK-NEXT: vmnand.mm v8, v8, v8 ; CHECK-NEXT: vmnot.m v8, v8
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vcpop.m a2, v8, v0.t ; CHECK-NEXT: vcpop.m a2, v8, v0.t
; CHECK-NEXT: li a3, 128 ; CHECK-NEXT: li a3, 128
; CHECK-NEXT: seqz a2, a2 ; CHECK-NEXT: seqz a2, a2
; CHECK-NEXT: bltu a1, a3, .LBB14_4 ; CHECK-NEXT: bltu a1, a3, .LBB14_4
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: li a1, 128 ; CHECK-NEXT: li a1, 128
; CHECK-NEXT: .LBB14_4: ; CHECK-NEXT: .LBB14_4:
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vmnand.mm v8, v11, v11 ; CHECK-NEXT: vmnot.m v8, v11
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vcpop.m a1, v8, v0.t ; CHECK-NEXT: vcpop.m a1, v8, v0.t
; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: and a0, a2, a0 ; CHECK-NEXT: and a0, a2, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.v256i1(i1 %s, <256 x i1> %v, <256 x i1> %m, i32 %evl) %r = call i1 @llvm.vp.reduce.and.v256i1(i1 %s, <256 x i1> %v, <256 x i1> %m, i32 %evl)
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll

Show First 20 Lines • Show All 309 Lines • ▼ Show 20 Lines
} }
define <8 x i1> @fcmp_ugt_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ugt_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vv_v8f16: ; CHECK-LABEL: fcmp_ugt_vv_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmfle.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmfle.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ugt", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ugt", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ugt_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ugt_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vf_v8f16: ; CHECK-LABEL: fcmp_ugt_vf_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmfle.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0 %elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ugt", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ugt", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ugt_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ugt_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vf_swap_v8f16: ; CHECK-LABEL: fcmp_ugt_vf_swap_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmfge.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0 %elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ugt", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ugt", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_uge_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_uge_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vv_v8f16: ; CHECK-LABEL: fcmp_uge_vv_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmflt.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmflt.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"uge", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"uge", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_uge_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_uge_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vf_v8f16: ; CHECK-LABEL: fcmp_uge_vf_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0 %elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"uge", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"uge", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_uge_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_uge_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vf_swap_v8f16: ; CHECK-LABEL: fcmp_uge_vf_swap_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0 %elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"uge", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"uge", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ult_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ult_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vv_v8f16: ; CHECK-LABEL: fcmp_ult_vv_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmfle.vv v8, v9, v8, v0.t ; CHECK-NEXT: vmfle.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ult", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ult", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ult_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ult_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vf_v8f16: ; CHECK-LABEL: fcmp_ult_vf_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmfge.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0 %elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ult", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ult", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ult_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ult_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vf_swap_v8f16: ; CHECK-LABEL: fcmp_ult_vf_swap_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmfle.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0 %elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ult", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ult", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ule_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ule_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vv_v8f16: ; CHECK-LABEL: fcmp_ule_vv_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmflt.vv v8, v9, v8, v0.t ; CHECK-NEXT: vmflt.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ule", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ule", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ule_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ule_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vf_v8f16: ; CHECK-LABEL: fcmp_ule_vf_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0 %elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ule", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ule", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ule_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ule_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vf_swap_v8f16: ; CHECK-LABEL: fcmp_ule_vf_swap_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0 %elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ule", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ule", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_une_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_une_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
▲ Show 20 Lines • Show All 398 Lines • ▼ Show 20 Lines
} }
define <8 x i1> @fcmp_ugt_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ugt_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vv_v8f64: ; CHECK-LABEL: fcmp_ugt_vv_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmfle.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmfle.vv v16, v8, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"ugt", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"ugt", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ugt_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ugt_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vf_v8f64: ; CHECK-LABEL: fcmp_ugt_vf_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmfle.vf v12, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> poison, double %b, i32 0 %elt.head = insertelement <8 x double> poison, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"ugt", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"ugt", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ugt_vf_swap_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ugt_vf_swap_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vf_swap_v8f64: ; CHECK-LABEL: fcmp_ugt_vf_swap_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmfge.vf v12, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> poison, double %b, i32 0 %elt.head = insertelement <8 x double> poison, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %vb, <8 x double> %va, metadata !"ugt", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %vb, <8 x double> %va, metadata !"ugt", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_uge_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_uge_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vv_v8f64: ; CHECK-LABEL: fcmp_uge_vv_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmflt.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmflt.vv v16, v8, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"uge", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"uge", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_uge_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_uge_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vf_v8f64: ; CHECK-LABEL: fcmp_uge_vf_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmflt.vf v12, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> poison, double %b, i32 0 %elt.head = insertelement <8 x double> poison, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"uge", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"uge", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_uge_vf_swap_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_uge_vf_swap_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vf_swap_v8f64: ; CHECK-LABEL: fcmp_uge_vf_swap_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmfgt.vf v12, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> poison, double %b, i32 0 %elt.head = insertelement <8 x double> poison, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %vb, <8 x double> %va, metadata !"uge", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %vb, <8 x double> %va, metadata !"uge", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ult_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ult_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vv_v8f64: ; CHECK-LABEL: fcmp_ult_vv_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmfle.vv v16, v12, v8, v0.t ; CHECK-NEXT: vmfle.vv v16, v12, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"ult", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"ult", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ult_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ult_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vf_v8f64: ; CHECK-LABEL: fcmp_ult_vf_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmfge.vf v12, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> poison, double %b, i32 0 %elt.head = insertelement <8 x double> poison, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"ult", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"ult", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ult_vf_swap_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ult_vf_swap_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vf_swap_v8f64: ; CHECK-LABEL: fcmp_ult_vf_swap_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmfle.vf v12, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> poison, double %b, i32 0 %elt.head = insertelement <8 x double> poison, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %vb, <8 x double> %va, metadata !"ult", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %vb, <8 x double> %va, metadata !"ult", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ule_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ule_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vv_v8f64: ; CHECK-LABEL: fcmp_ule_vv_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmflt.vv v16, v12, v8, v0.t ; CHECK-NEXT: vmflt.vv v16, v12, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"ule", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"ule", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ule_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ule_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vf_v8f64: ; CHECK-LABEL: fcmp_ule_vf_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmfgt.vf v12, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> poison, double %b, i32 0 %elt.head = insertelement <8 x double> poison, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"ule", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"ule", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ule_vf_swap_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ule_vf_swap_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vf_swap_v8f64: ; CHECK-LABEL: fcmp_ule_vf_swap_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmflt.vf v12, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> poison, double %b, i32 0 %elt.head = insertelement <8 x double> poison, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %vb, <8 x double> %va, metadata !"ule", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %vb, <8 x double> %va, metadata !"ule", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_une_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_une_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) {
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll

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} }
declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>) declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)
define signext i1 @vreduce_and_v2i1(<2 x i1> %v) { define signext i1 @vreduce_and_v2i1(<2 x i1> %v) {
; CHECK-LABEL: vreduce_and_v2i1: ; CHECK-LABEL: vreduce_and_v2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v8, v0, v0 ; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: vcpop.m a0, v8
; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %v) %red = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %v)
ret i1 %red ret i1 %red
} }
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} }
declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1>) declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1>)
define signext i1 @vreduce_and_v4i1(<4 x i1> %v) { define signext i1 @vreduce_and_v4i1(<4 x i1> %v) {
; CHECK-LABEL: vreduce_and_v4i1: ; CHECK-LABEL: vreduce_and_v4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vmnand.mm v8, v0, v0 ; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: vcpop.m a0, v8
; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %v) %red = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %v)
ret i1 %red ret i1 %red
} }
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} }
declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1>) declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1>)
define signext i1 @vreduce_and_v8i1(<8 x i1> %v) { define signext i1 @vreduce_and_v8i1(<8 x i1> %v) {
; CHECK-LABEL: vreduce_and_v8i1: ; CHECK-LABEL: vreduce_and_v8i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v8, v0, v0 ; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: vcpop.m a0, v8
; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %v) %red = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %v)
ret i1 %red ret i1 %red
} }
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} }
declare i1 @llvm.vector.reduce.and.v16i1(<16 x i1>) declare i1 @llvm.vector.reduce.and.v16i1(<16 x i1>)
define signext i1 @vreduce_and_v16i1(<16 x i1> %v) { define signext i1 @vreduce_and_v16i1(<16 x i1> %v) {
; CHECK-LABEL: vreduce_and_v16i1: ; CHECK-LABEL: vreduce_and_v16i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v8, v0, v0 ; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: vcpop.m a0, v8
; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %v) %red = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %v)
ret i1 %red ret i1 %red
} }
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; LMULMAX1-NEXT: seqz a0, a0 ; LMULMAX1-NEXT: seqz a0, a0
; LMULMAX1-NEXT: neg a0, a0 ; LMULMAX1-NEXT: neg a0, a0
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX8-LABEL: vreduce_and_v32i1: ; LMULMAX8-LABEL: vreduce_and_v32i1:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: li a0, 32 ; LMULMAX8-NEXT: li a0, 32
; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; LMULMAX8-NEXT: vmnand.mm v8, v0, v0 ; LMULMAX8-NEXT: vmnot.m v8, v0
; LMULMAX8-NEXT: vcpop.m a0, v8 ; LMULMAX8-NEXT: vcpop.m a0, v8
; LMULMAX8-NEXT: seqz a0, a0 ; LMULMAX8-NEXT: seqz a0, a0
; LMULMAX8-NEXT: neg a0, a0 ; LMULMAX8-NEXT: neg a0, a0
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %v) %red = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %v)
ret i1 %red ret i1 %red
} }
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; LMULMAX1-NEXT: seqz a0, a0 ; LMULMAX1-NEXT: seqz a0, a0
; LMULMAX1-NEXT: neg a0, a0 ; LMULMAX1-NEXT: neg a0, a0
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX8-LABEL: vreduce_and_v64i1: ; LMULMAX8-LABEL: vreduce_and_v64i1:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: li a0, 64 ; LMULMAX8-NEXT: li a0, 64
; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; LMULMAX8-NEXT: vmnand.mm v8, v0, v0 ; LMULMAX8-NEXT: vmnot.m v8, v0
; LMULMAX8-NEXT: vcpop.m a0, v8 ; LMULMAX8-NEXT: vcpop.m a0, v8
; LMULMAX8-NEXT: seqz a0, a0 ; LMULMAX8-NEXT: seqz a0, a0
; LMULMAX8-NEXT: neg a0, a0 ; LMULMAX8-NEXT: neg a0, a0
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> %v) %red = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> %v)
ret i1 %red ret i1 %red
} }

llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll

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} }
define <vscale x 1 x i1> @fcmp_ugt_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ugt_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vv_nxv1f16: ; CHECK-LABEL: fcmp_ugt_vv_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmfle.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmfle.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ugt_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ugt_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vf_nxv1f16: ; CHECK-LABEL: fcmp_ugt_vf_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmfle.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ugt_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ugt_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vf_swap_nxv1f16: ; CHECK-LABEL: fcmp_ugt_vf_swap_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmfge.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_uge_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_uge_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vv_nxv1f16: ; CHECK-LABEL: fcmp_uge_vv_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmflt.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmflt.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_uge_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_uge_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vf_nxv1f16: ; CHECK-LABEL: fcmp_uge_vf_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_uge_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_uge_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vf_swap_nxv1f16: ; CHECK-LABEL: fcmp_uge_vf_swap_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ult_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ult_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vv_nxv1f16: ; CHECK-LABEL: fcmp_ult_vv_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmfle.vv v8, v9, v8, v0.t ; CHECK-NEXT: vmfle.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ult_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ult_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vf_nxv1f16: ; CHECK-LABEL: fcmp_ult_vf_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmfge.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ult_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ult_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vf_swap_nxv1f16: ; CHECK-LABEL: fcmp_ult_vf_swap_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmfle.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ule_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ule_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vv_nxv1f16: ; CHECK-LABEL: fcmp_ule_vv_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmflt.vv v8, v9, v8, v0.t ; CHECK-NEXT: vmflt.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ule", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ule", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ule_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ule_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vf_nxv1f16: ; CHECK-LABEL: fcmp_ule_vf_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ule", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ule", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ule_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ule_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vf_swap_nxv1f16: ; CHECK-LABEL: fcmp_ule_vf_swap_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ule", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ule", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_une_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_une_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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} }
define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vv_nxv8f16: ; CHECK-LABEL: fcmp_ugt_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmfle.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmfle.vv v12, v8, v10, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ugt", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ugt", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vf_nxv8f16: ; CHECK-LABEL: fcmp_ugt_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ugt", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ugt", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ugt_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ugt_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vf_swap_nxv8f16: ; CHECK-LABEL: fcmp_ugt_vf_swap_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ugt", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ugt", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vv_nxv8f16: ; CHECK-LABEL: fcmp_uge_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmflt.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmflt.vv v12, v8, v10, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vf_nxv8f16: ; CHECK-LABEL: fcmp_uge_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_uge_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_uge_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vf_swap_nxv8f16: ; CHECK-LABEL: fcmp_uge_vf_swap_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vv_nxv8f16: ; CHECK-LABEL: fcmp_ult_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmfle.vv v12, v10, v8, v0.t ; CHECK-NEXT: vmfle.vv v12, v10, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ult", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ult", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vf_nxv8f16: ; CHECK-LABEL: fcmp_ult_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ult", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ult", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ult_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ult_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vf_swap_nxv8f16: ; CHECK-LABEL: fcmp_ult_vf_swap_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ult", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ult", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vv_nxv8f16: ; CHECK-LABEL: fcmp_ule_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmflt.vv v12, v10, v8, v0.t ; CHECK-NEXT: vmflt.vv v12, v10, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ule", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ule", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vf_nxv8f16: ; CHECK-LABEL: fcmp_ule_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ule", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ule", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ule_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ule_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vf_swap_nxv8f16: ; CHECK-LABEL: fcmp_ule_vf_swap_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ule", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ule", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
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} }
define <vscale x 1 x i1> @fcmp_ugt_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ugt_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vv_nxv1f64: ; CHECK-LABEL: fcmp_ugt_vv_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmfle.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmfle.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ugt_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ugt_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vf_nxv1f64: ; CHECK-LABEL: fcmp_ugt_vf_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmfle.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ugt_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ugt_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vf_swap_nxv1f64: ; CHECK-LABEL: fcmp_ugt_vf_swap_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmfge.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_uge_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_uge_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vv_nxv1f64: ; CHECK-LABEL: fcmp_uge_vv_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmflt.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmflt.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_uge_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_uge_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vf_nxv1f64: ; CHECK-LABEL: fcmp_uge_vf_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_uge_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_uge_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vf_swap_nxv1f64: ; CHECK-LABEL: fcmp_uge_vf_swap_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ult_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ult_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vv_nxv1f64: ; CHECK-LABEL: fcmp_ult_vv_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmfle.vv v8, v9, v8, v0.t ; CHECK-NEXT: vmfle.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ult_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ult_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vf_nxv1f64: ; CHECK-LABEL: fcmp_ult_vf_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmfge.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ult_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ult_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vf_swap_nxv1f64: ; CHECK-LABEL: fcmp_ult_vf_swap_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmfle.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ule_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ule_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vv_nxv1f64: ; CHECK-LABEL: fcmp_ule_vv_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmflt.vv v8, v9, v8, v0.t ; CHECK-NEXT: vmflt.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ule", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ule", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ule_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ule_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vf_nxv1f64: ; CHECK-LABEL: fcmp_ule_vf_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ule", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ule", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ule_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ule_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vf_swap_nxv1f64: ; CHECK-LABEL: fcmp_ule_vf_swap_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"ule", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"ule", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_une_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_une_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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} }
define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vv_nxv8f64: ; CHECK-LABEL: fcmp_ugt_vv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfle.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmfle.vv v24, v8, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v24, v24 ; CHECK-NEXT: vmnot.m v0, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ugt", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ugt", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vf_nxv8f64: ; CHECK-LABEL: fcmp_ugt_vf_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfle.vf v16, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ugt", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ugt", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ugt_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ugt_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ugt_vf_swap_nxv8f64: ; CHECK-LABEL: fcmp_ugt_vf_swap_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfge.vf v16, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"ugt", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"ugt", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vv_nxv8f64: ; CHECK-LABEL: fcmp_uge_vv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmflt.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmflt.vv v24, v8, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v24, v24 ; CHECK-NEXT: vmnot.m v0, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vf_nxv8f64: ; CHECK-LABEL: fcmp_uge_vf_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmflt.vf v16, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_uge_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_uge_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uge_vf_swap_nxv8f64: ; CHECK-LABEL: fcmp_uge_vf_swap_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfgt.vf v16, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vv_nxv8f64: ; CHECK-LABEL: fcmp_ult_vv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfle.vv v24, v16, v8, v0.t ; CHECK-NEXT: vmfle.vv v24, v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v24, v24 ; CHECK-NEXT: vmnot.m v0, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ult", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ult", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vf_nxv8f64: ; CHECK-LABEL: fcmp_ult_vf_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfge.vf v16, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ult", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ult", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ult_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ult_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ult_vf_swap_nxv8f64: ; CHECK-LABEL: fcmp_ult_vf_swap_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfle.vf v16, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"ult", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"ult", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vv_nxv8f64: ; CHECK-LABEL: fcmp_ule_vv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmflt.vv v24, v16, v8, v0.t ; CHECK-NEXT: vmflt.vv v24, v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v24, v24 ; CHECK-NEXT: vmnot.m v0, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ule", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ule", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vf_nxv8f64: ; CHECK-LABEL: fcmp_ule_vf_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfgt.vf v16, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ule", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ule", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ule_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ule_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ule_vf_swap_nxv8f64: ; CHECK-LABEL: fcmp_ule_vf_swap_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmflt.vf v16, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"ule", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"ule", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_une_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_une_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
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llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll

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ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_ugt_vv_nxv8f16: ; CHECK-LABEL: fcmp_ugt_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vmfle.vv v12, v8, v10 ; CHECK-NEXT: vmfle.vv v12, v8, v10
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ugt <vscale x 8 x half> %va, %vb %vc = fcmp ugt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ugt_vf_nxv8f16: ; CHECK-LABEL: fcmp_ugt_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vmfle.vf v10, v8, fa0 ; CHECK-NEXT: vmfle.vf v10, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ugt <vscale x 8 x half> %va, %splat %vc = fcmp ugt <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ugt_fv_nxv8f16: ; CHECK-LABEL: fcmp_ugt_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vmfge.vf v10, v8, fa0 ; CHECK-NEXT: vmfge.vf v10, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ugt <vscale x 8 x half> %splat, %va %vc = fcmp ugt <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
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ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_uge_vv_nxv8f16: ; CHECK-LABEL: fcmp_uge_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vmflt.vv v12, v8, v10 ; CHECK-NEXT: vmflt.vv v12, v8, v10
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp uge <vscale x 8 x half> %va, %vb %vc = fcmp uge <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_uge_vf_nxv8f16: ; CHECK-LABEL: fcmp_uge_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v8, fa0 ; CHECK-NEXT: vmflt.vf v10, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uge <vscale x 8 x half> %va, %splat %vc = fcmp uge <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_uge_fv_nxv8f16: ; CHECK-LABEL: fcmp_uge_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vmfgt.vf v10, v8, fa0 ; CHECK-NEXT: vmfgt.vf v10, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uge <vscale x 8 x half> %splat, %va %vc = fcmp uge <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
Show All 18 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_ult_vv_nxv8f16: ; CHECK-LABEL: fcmp_ult_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vmfle.vv v12, v10, v8 ; CHECK-NEXT: vmfle.vv v12, v10, v8
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ult <vscale x 8 x half> %va, %vb %vc = fcmp ult <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ult_vf_nxv8f16: ; CHECK-LABEL: fcmp_ult_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vmfge.vf v10, v8, fa0 ; CHECK-NEXT: vmfge.vf v10, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ult <vscale x 8 x half> %va, %splat %vc = fcmp ult <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ult_fv_nxv8f16: ; CHECK-LABEL: fcmp_ult_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vmfle.vf v10, v8, fa0 ; CHECK-NEXT: vmfle.vf v10, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ult <vscale x 8 x half> %splat, %va %vc = fcmp ult <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
Show All 18 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_ule_vv_nxv8f16: ; CHECK-LABEL: fcmp_ule_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vmflt.vv v12, v10, v8 ; CHECK-NEXT: vmflt.vv v12, v10, v8
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ule <vscale x 8 x half> %va, %vb %vc = fcmp ule <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ule_vf_nxv8f16: ; CHECK-LABEL: fcmp_ule_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vmfgt.vf v10, v8, fa0 ; CHECK-NEXT: vmfgt.vf v10, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ule <vscale x 8 x half> %va, %splat %vc = fcmp ule <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ule_fv_nxv8f16: ; CHECK-LABEL: fcmp_ule_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vmflt.vf v10, v8, fa0 ; CHECK-NEXT: vmflt.vf v10, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ule <vscale x 8 x half> %splat, %va %vc = fcmp ule <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
▲ Show 20 Lines • Show All 616 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) { define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: fcmp_ugt_vv_nxv8f32: ; CHECK-LABEL: fcmp_ugt_vv_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmfle.vv v16, v8, v12 ; CHECK-NEXT: vmfle.vv v16, v8, v12
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ugt <vscale x 8 x float> %va, %vb %vc = fcmp ugt <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f32(<vscale x 8 x float> %va, float %b) { define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: fcmp_ugt_vf_nxv8f32: ; CHECK-LABEL: fcmp_ugt_vf_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmfle.vf v12, v8, fa0 ; CHECK-NEXT: vmfle.vf v12, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float %b, i32 0 %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ugt <vscale x 8 x float> %va, %splat %vc = fcmp ugt <vscale x 8 x float> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f32(<vscale x 8 x float> %va, float %b) { define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: fcmp_ugt_fv_nxv8f32: ; CHECK-LABEL: fcmp_ugt_fv_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmfge.vf v12, v8, fa0 ; CHECK-NEXT: vmfge.vf v12, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float %b, i32 0 %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ugt <vscale x 8 x float> %splat, %va %vc = fcmp ugt <vscale x 8 x float> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 { define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
Show All 18 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) { define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: fcmp_uge_vv_nxv8f32: ; CHECK-LABEL: fcmp_uge_vv_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmflt.vv v16, v8, v12 ; CHECK-NEXT: vmflt.vv v16, v8, v12
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp uge <vscale x 8 x float> %va, %vb %vc = fcmp uge <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f32(<vscale x 8 x float> %va, float %b) { define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: fcmp_uge_vf_nxv8f32: ; CHECK-LABEL: fcmp_uge_vf_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v8, fa0 ; CHECK-NEXT: vmflt.vf v12, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float %b, i32 0 %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uge <vscale x 8 x float> %va, %splat %vc = fcmp uge <vscale x 8 x float> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f32(<vscale x 8 x float> %va, float %b) { define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: fcmp_uge_fv_nxv8f32: ; CHECK-LABEL: fcmp_uge_fv_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmfgt.vf v12, v8, fa0 ; CHECK-NEXT: vmfgt.vf v12, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float %b, i32 0 %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uge <vscale x 8 x float> %splat, %va %vc = fcmp uge <vscale x 8 x float> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 { define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
Show All 18 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) { define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: fcmp_ult_vv_nxv8f32: ; CHECK-LABEL: fcmp_ult_vv_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmfle.vv v16, v12, v8 ; CHECK-NEXT: vmfle.vv v16, v12, v8
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ult <vscale x 8 x float> %va, %vb %vc = fcmp ult <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f32(<vscale x 8 x float> %va, float %b) { define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: fcmp_ult_vf_nxv8f32: ; CHECK-LABEL: fcmp_ult_vf_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmfge.vf v12, v8, fa0 ; CHECK-NEXT: vmfge.vf v12, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float %b, i32 0 %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ult <vscale x 8 x float> %va, %splat %vc = fcmp ult <vscale x 8 x float> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f32(<vscale x 8 x float> %va, float %b) { define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: fcmp_ult_fv_nxv8f32: ; CHECK-LABEL: fcmp_ult_fv_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmfle.vf v12, v8, fa0 ; CHECK-NEXT: vmfle.vf v12, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float %b, i32 0 %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ult <vscale x 8 x float> %splat, %va %vc = fcmp ult <vscale x 8 x float> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 { define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
Show All 18 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) { define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: fcmp_ule_vv_nxv8f32: ; CHECK-LABEL: fcmp_ule_vv_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmflt.vv v16, v12, v8 ; CHECK-NEXT: vmflt.vv v16, v12, v8
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ule <vscale x 8 x float> %va, %vb %vc = fcmp ule <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f32(<vscale x 8 x float> %va, float %b) { define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: fcmp_ule_vf_nxv8f32: ; CHECK-LABEL: fcmp_ule_vf_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmfgt.vf v12, v8, fa0 ; CHECK-NEXT: vmfgt.vf v12, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float %b, i32 0 %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ule <vscale x 8 x float> %va, %splat %vc = fcmp ule <vscale x 8 x float> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f32(<vscale x 8 x float> %va, float %b) { define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: fcmp_ule_fv_nxv8f32: ; CHECK-LABEL: fcmp_ule_fv_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmflt.vf v12, v8, fa0 ; CHECK-NEXT: vmflt.vf v12, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float %b, i32 0 %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ule <vscale x 8 x float> %splat, %va %vc = fcmp ule <vscale x 8 x float> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 { define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
▲ Show 20 Lines • Show All 616 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) { define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
; CHECK-LABEL: fcmp_ugt_vv_nxv8f64: ; CHECK-LABEL: fcmp_ugt_vv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmfle.vv v24, v8, v16 ; CHECK-NEXT: vmfle.vv v24, v8, v16
; CHECK-NEXT: vmnand.mm v0, v24, v24 ; CHECK-NEXT: vmnot.m v0, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ugt <vscale x 8 x double> %va, %vb %vc = fcmp ugt <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f64(<vscale x 8 x double> %va, double %b) { define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: fcmp_ugt_vf_nxv8f64: ; CHECK-LABEL: fcmp_ugt_vf_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmfle.vf v16, v8, fa0 ; CHECK-NEXT: vmfle.vf v16, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ugt <vscale x 8 x double> %va, %splat %vc = fcmp ugt <vscale x 8 x double> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f64(<vscale x 8 x double> %va, double %b) { define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: fcmp_ugt_fv_nxv8f64: ; CHECK-LABEL: fcmp_ugt_fv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmfge.vf v16, v8, fa0 ; CHECK-NEXT: vmfge.vf v16, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ugt <vscale x 8 x double> %splat, %va %vc = fcmp ugt <vscale x 8 x double> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 { define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
Show All 18 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) { define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
; CHECK-LABEL: fcmp_uge_vv_nxv8f64: ; CHECK-LABEL: fcmp_uge_vv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vv v24, v8, v16 ; CHECK-NEXT: vmflt.vv v24, v8, v16
; CHECK-NEXT: vmnand.mm v0, v24, v24 ; CHECK-NEXT: vmnot.m v0, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp uge <vscale x 8 x double> %va, %vb %vc = fcmp uge <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f64(<vscale x 8 x double> %va, double %b) { define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: fcmp_uge_vf_nxv8f64: ; CHECK-LABEL: fcmp_uge_vf_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v8, fa0 ; CHECK-NEXT: vmflt.vf v16, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uge <vscale x 8 x double> %va, %splat %vc = fcmp uge <vscale x 8 x double> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f64(<vscale x 8 x double> %va, double %b) { define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: fcmp_uge_fv_nxv8f64: ; CHECK-LABEL: fcmp_uge_fv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmfgt.vf v16, v8, fa0 ; CHECK-NEXT: vmfgt.vf v16, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uge <vscale x 8 x double> %splat, %va %vc = fcmp uge <vscale x 8 x double> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 { define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
Show All 18 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) { define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
; CHECK-LABEL: fcmp_ult_vv_nxv8f64: ; CHECK-LABEL: fcmp_ult_vv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmfle.vv v24, v16, v8 ; CHECK-NEXT: vmfle.vv v24, v16, v8
; CHECK-NEXT: vmnand.mm v0, v24, v24 ; CHECK-NEXT: vmnot.m v0, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ult <vscale x 8 x double> %va, %vb %vc = fcmp ult <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f64(<vscale x 8 x double> %va, double %b) { define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: fcmp_ult_vf_nxv8f64: ; CHECK-LABEL: fcmp_ult_vf_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmfge.vf v16, v8, fa0 ; CHECK-NEXT: vmfge.vf v16, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ult <vscale x 8 x double> %va, %splat %vc = fcmp ult <vscale x 8 x double> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f64(<vscale x 8 x double> %va, double %b) { define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: fcmp_ult_fv_nxv8f64: ; CHECK-LABEL: fcmp_ult_fv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmfle.vf v16, v8, fa0 ; CHECK-NEXT: vmfle.vf v16, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ult <vscale x 8 x double> %splat, %va %vc = fcmp ult <vscale x 8 x double> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 { define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
Show All 18 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) { define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
; CHECK-LABEL: fcmp_ule_vv_nxv8f64: ; CHECK-LABEL: fcmp_ule_vv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vv v24, v16, v8 ; CHECK-NEXT: vmflt.vv v24, v16, v8
; CHECK-NEXT: vmnand.mm v0, v24, v24 ; CHECK-NEXT: vmnot.m v0, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ule <vscale x 8 x double> %va, %vb %vc = fcmp ule <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f64(<vscale x 8 x double> %va, double %b) { define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: fcmp_ule_vf_nxv8f64: ; CHECK-LABEL: fcmp_ule_vf_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmfgt.vf v16, v8, fa0 ; CHECK-NEXT: vmfgt.vf v16, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ule <vscale x 8 x double> %va, %splat %vc = fcmp ule <vscale x 8 x double> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f64(<vscale x 8 x double> %va, double %b) { define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: fcmp_ule_fv_nxv8f64: ; CHECK-LABEL: fcmp_ule_fv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v16, v8, fa0 ; CHECK-NEXT: vmflt.vf v16, v8, fa0
; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: vmnot.m v0, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ule <vscale x 8 x double> %splat, %va %vc = fcmp ule <vscale x 8 x double> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 { define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
▲ Show 20 Lines • Show All 179 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll

Show First 20 Lines • Show All 941 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8(
i8, i8,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
Show All 31 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8(
i8, i8,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
Show All 31 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8(
i8, i8,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
Show All 31 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8(
i8, i8,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
Show All 31 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8(
i8, i8,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsge_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmslt.vx v10, v8, a0 ; CHECK-NEXT: vmslt.vx v10, v8, a0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
Show All 31 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.i8(
i8, i8,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsge_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 32 x i1> @intrinsic_vmsge_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmslt.vx v12, v8, a0 ; CHECK-NEXT: vmslt.vx v12, v8, a0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16.i16(
i16, i16,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16.i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
Show All 31 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16.i16(
i16, i16,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16.i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
Show All 31 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16.i16(
i16, i16,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16.i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
Show All 31 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16.i16(
i16, i16,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmslt.vx v10, v8, a0 ; CHECK-NEXT: vmslt.vx v10, v8, a0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16.i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
Show All 31 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16.i16(
i16, i16,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsge_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmslt.vx v12, v8, a0 ; CHECK-NEXT: vmslt.vx v12, v8, a0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16.i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32.i32(
i32, i32,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32.i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
Show All 31 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32.i32(
i32, i32,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32.i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
Show All 31 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32.i32(
i32, i32,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmslt.vx v10, v8, a0 ; CHECK-NEXT: vmslt.vx v10, v8, a0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32.i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
Show All 31 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32.i32(
i32, i32,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmslt.vx v12, v8, a0 ; CHECK-NEXT: vmslt.vx v12, v8, a0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32.i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
▲ Show 20 Lines • Show All 1,179 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll

Show First 20 Lines • Show All 941 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8(
i8, i8,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
Show All 31 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8(
i8, i8,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
Show All 31 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8(
i8, i8,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
Show All 31 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8(
i8, i8,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
Show All 31 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8(
i8, i8,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsge_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmslt.vx v10, v8, a0 ; CHECK-NEXT: vmslt.vx v10, v8, a0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
Show All 31 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.i8(
i8, i8,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsge_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 32 x i1> @intrinsic_vmsge_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmslt.vx v12, v8, a0 ; CHECK-NEXT: vmslt.vx v12, v8, a0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16.i16(
i16, i16,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16.i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
Show All 31 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16.i16(
i16, i16,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16.i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
Show All 31 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16.i16(
i16, i16,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16.i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
Show All 31 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16.i16(
i16, i16,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmslt.vx v10, v8, a0 ; CHECK-NEXT: vmslt.vx v10, v8, a0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16.i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
Show All 31 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16.i16(
i16, i16,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsge_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmslt.vx v12, v8, a0 ; CHECK-NEXT: vmslt.vx v12, v8, a0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16.i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32.i32(
i32, i32,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32.i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
Show All 31 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32.i32(
i32, i32,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32.i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
Show All 31 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32.i32(
i32, i32,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmslt.vx v10, v8, a0 ; CHECK-NEXT: vmslt.vx v10, v8, a0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32.i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
Show All 31 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32.i32(
i32, i32,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmslt.vx v12, v8, a0 ; CHECK-NEXT: vmslt.vx v12, v8, a0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32.i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64.i64(
i64, i64,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
Show All 31 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64.i64(
i64, i64,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmslt.vx v10, v8, a0 ; CHECK-NEXT: vmslt.vx v10, v8, a0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
Show All 31 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64.i64(
i64, i64,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmslt.vx v12, v8, a0 ; CHECK-NEXT: vmslt.vx v12, v8, a0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
▲ Show 20 Lines • Show All 983 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll

Show First 20 Lines • Show All 941 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8(
i8, i8,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
Show All 31 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8(
i8, i8,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
Show All 31 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8(
i8, i8,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
Show All 31 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8(
i8, i8,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
Show All 31 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8(
i8, i8,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsgeu_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmsltu.vx v10, v8, a0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
Show All 31 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.i8(
i8, i8,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsgeu_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgeu_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmsltu.vx v12, v8, a0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16.i16(
i16, i16,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16.i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
Show All 31 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16(
i16, i16,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
Show All 31 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16(
i16, i16,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
Show All 31 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16.i16(
i16, i16,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmsltu.vx v10, v8, a0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16.i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
Show All 31 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16.i16(
i16, i16,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsgeu_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmsltu.vx v12, v8, a0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16.i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32.i32(
i32, i32,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32.i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
Show All 31 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32.i32(
i32, i32,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32.i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
Show All 31 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32.i32(
i32, i32,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmsltu.vx v10, v8, a0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32.i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
Show All 31 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32.i32(
i32, i32,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmsltu.vx v12, v8, a0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32.i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
▲ Show 20 Lines • Show All 1,191 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll

Show First 20 Lines • Show All 941 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8(
i8, i8,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
Show All 31 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8(
i8, i8,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
Show All 31 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8(
i8, i8,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
Show All 31 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8(
i8, i8,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
Show All 31 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8(
i8, i8,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsgeu_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmsltu.vx v10, v8, a0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
Show All 31 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.i8(
i8, i8,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsgeu_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgeu_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmsltu.vx v12, v8, a0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16.i16(
i16, i16,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16.i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
Show All 31 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16(
i16, i16,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
Show All 31 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16(
i16, i16,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
Show All 31 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16.i16(
i16, i16,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmsltu.vx v10, v8, a0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16.i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
Show All 31 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16.i16(
i16, i16,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsgeu_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmsltu.vx v12, v8, a0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16.i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32.i32(
i32, i32,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32.i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
Show All 31 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32.i32(
i32, i32,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32.i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
Show All 31 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32.i32(
i32, i32,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmsltu.vx v10, v8, a0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32.i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
Show All 31 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32.i32(
i32, i32,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmsltu.vx v12, v8, a0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32.i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64.i64(
i64, i64,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vmnot.m v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
Show All 31 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64.i64(
i64, i64,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmsltu.vx v10, v8, a0
; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: vmnot.m v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
Show All 31 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64.i64(
i64, i64,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmsltu.vx v12, v8, a0
; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: vmnot.m v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
▲ Show 20 Lines • Show All 995 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
declare i1 @llvm.vp.reduce.and.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32) declare i1 @llvm.vp.reduce.and.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
define signext i1 @vpreduce_and_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) { define signext i1 @vpreduce_and_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_nxv1i1: ; CHECK-LABEL: vpreduce_and_nxv1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmnot.m v9, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a1, v9, v0.t ; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl) %r = call i1 @llvm.vp.reduce.and.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i1 %r ret i1 %r
Show All 35 Lines
} }
declare i1 @llvm.vp.reduce.and.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32) declare i1 @llvm.vp.reduce.and.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
define signext i1 @vpreduce_and_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) { define signext i1 @vpreduce_and_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_nxv2i1: ; CHECK-LABEL: vpreduce_and_nxv2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmnot.m v9, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a1, v9, v0.t ; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl) %r = call i1 @llvm.vp.reduce.and.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i1 %r ret i1 %r
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} }
declare i1 @llvm.vp.reduce.and.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32) declare i1 @llvm.vp.reduce.and.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
define signext i1 @vpreduce_and_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) { define signext i1 @vpreduce_and_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_nxv4i1: ; CHECK-LABEL: vpreduce_and_nxv4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmnot.m v9, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a1, v9, v0.t ; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl) %r = call i1 @llvm.vp.reduce.and.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i1 %r ret i1 %r
Show All 35 Lines
} }
declare i1 @llvm.vp.reduce.and.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32) declare i1 @llvm.vp.reduce.and.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
define signext i1 @vpreduce_and_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) { define signext i1 @vpreduce_and_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_nxv8i1: ; CHECK-LABEL: vpreduce_and_nxv8i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmnot.m v9, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a1, v9, v0.t ; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl) %r = call i1 @llvm.vp.reduce.and.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)
ret i1 %r ret i1 %r
Show All 35 Lines
} }
declare i1 @llvm.vp.reduce.and.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32) declare i1 @llvm.vp.reduce.and.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
define signext i1 @vpreduce_and_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) { define signext i1 @vpreduce_and_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_nxv16i1: ; CHECK-LABEL: vpreduce_and_nxv16i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmnot.m v9, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a1, v9, v0.t ; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl) %r = call i1 @llvm.vp.reduce.and.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)
ret i1 %r ret i1 %r
Show All 35 Lines
} }
declare i1 @llvm.vp.reduce.and.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32) declare i1 @llvm.vp.reduce.and.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
define signext i1 @vpreduce_and_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) { define signext i1 @vpreduce_and_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_nxv32i1: ; CHECK-LABEL: vpreduce_and_nxv32i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmnot.m v9, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a1, v9, v0.t ; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl) %r = call i1 @llvm.vp.reduce.and.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)
ret i1 %r ret i1 %r
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
} }
declare i1 @llvm.vp.reduce.and.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32) declare i1 @llvm.vp.reduce.and.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
define signext i1 @vpreduce_and_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) { define signext i1 @vpreduce_and_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_nxv64i1: ; CHECK-LABEL: vpreduce_and_nxv64i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmnot.m v9, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a1, v9, v0.t ; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl) %r = call i1 @llvm.vp.reduce.and.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
ret i1 %r ret i1 %r
▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll

Show All 30 Lines
} }
declare i1 @llvm.vector.reduce.and.nxv1i1(<vscale x 1 x i1>) declare i1 @llvm.vector.reduce.and.nxv1i1(<vscale x 1 x i1>)
define signext i1 @vreduce_and_nxv1i1(<vscale x 1 x i1> %v) { define signext i1 @vreduce_and_nxv1i1(<vscale x 1 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv1i1: ; CHECK-LABEL: vreduce_and_nxv1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v8, v0, v0 ; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: vcpop.m a0, v8
; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.nxv1i1(<vscale x 1 x i1> %v) %red = call i1 @llvm.vector.reduce.and.nxv1i1(<vscale x 1 x i1> %v)
ret i1 %red ret i1 %red
} }
Show All 26 Lines
} }
declare i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1>) declare i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1>)
define signext i1 @vreduce_and_nxv2i1(<vscale x 2 x i1> %v) { define signext i1 @vreduce_and_nxv2i1(<vscale x 2 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv2i1: ; CHECK-LABEL: vreduce_and_nxv2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmnand.mm v8, v0, v0 ; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: vcpop.m a0, v8
; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1> %v) %red = call i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1> %v)
ret i1 %red ret i1 %red
} }
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} }
declare i1 @llvm.vector.reduce.and.nxv4i1(<vscale x 4 x i1>) declare i1 @llvm.vector.reduce.and.nxv4i1(<vscale x 4 x i1>)
define signext i1 @vreduce_and_nxv4i1(<vscale x 4 x i1> %v) { define signext i1 @vreduce_and_nxv4i1(<vscale x 4 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv4i1: ; CHECK-LABEL: vreduce_and_nxv4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v8, v0, v0 ; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: vcpop.m a0, v8
; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.nxv4i1(<vscale x 4 x i1> %v) %red = call i1 @llvm.vector.reduce.and.nxv4i1(<vscale x 4 x i1> %v)
ret i1 %red ret i1 %red
} }
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} }
declare i1 @llvm.vector.reduce.and.nxv8i1(<vscale x 8 x i1>) declare i1 @llvm.vector.reduce.and.nxv8i1(<vscale x 8 x i1>)
define signext i1 @vreduce_and_nxv8i1(<vscale x 8 x i1> %v) { define signext i1 @vreduce_and_nxv8i1(<vscale x 8 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv8i1: ; CHECK-LABEL: vreduce_and_nxv8i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v8, v0, v0 ; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: vcpop.m a0, v8
; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.nxv8i1(<vscale x 8 x i1> %v) %red = call i1 @llvm.vector.reduce.and.nxv8i1(<vscale x 8 x i1> %v)
ret i1 %red ret i1 %red
} }
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} }
declare i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1>) declare i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1>)
define signext i1 @vreduce_and_nxv16i1(<vscale x 16 x i1> %v) { define signext i1 @vreduce_and_nxv16i1(<vscale x 16 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv16i1: ; CHECK-LABEL: vreduce_and_nxv16i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; CHECK-NEXT: vmnand.mm v8, v0, v0 ; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: vcpop.m a0, v8
; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %v) %red = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %v)
ret i1 %red ret i1 %red
} }
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} }
declare i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1>) declare i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1>)
define signext i1 @vreduce_and_nxv32i1(<vscale x 32 x i1> %v) { define signext i1 @vreduce_and_nxv32i1(<vscale x 32 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv32i1: ; CHECK-LABEL: vreduce_and_nxv32i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; CHECK-NEXT: vmnand.mm v8, v0, v0 ; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: vcpop.m a0, v8
; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1> %v) %red = call i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1> %v)
ret i1 %red ret i1 %red
} }
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} }
declare i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1>) declare i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1>)
define signext i1 @vreduce_and_nxv64i1(<vscale x 64 x i1> %v) { define signext i1 @vreduce_and_nxv64i1(<vscale x 64 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv64i1: ; CHECK-LABEL: vreduce_and_nxv64i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; CHECK-NEXT: vmnand.mm v8, v0, v0 ; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: vcpop.m a0, v8
; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1> %v) %red = call i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1> %v)
ret i1 %red ret i1 %red
} }