[SelectionDAG][RISCV] Make RegsForValue::getCopyToRegs explicitly zero_extend constants.

[craig.topper]

Summary

ComputePHILiveOutRegInfo assumes that constant incoming values to
Phis will be zero extended if they aren't a legal type. To guarantee
that we should zero_extend rather than any_extend constants.

This fixes a bug for RISCV where any_extend of constants can be
treated as a sign_extend.

[RKSimon]

LGTM

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 //===- SelectionDAGBuilder.cpp - Selection-DAG building -------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
   for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
     unsigned NumParts = RegCount[Value];
 
     MVT RegisterVT = isABIMangled() ? TLI.getRegisterTypeForCallingConv(
                                           *DAG.getContext(),
                                           CallConv.getValue(), RegVTs[Value])
                                     : RegVTs[Value];
 
-    if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
+    // We need to zero extend constants that are liveout to match assumptions
+    // in FunctionLoweringInfo::ComputePHILiveOutRegInfo.
+    if (ExtendKind == ISD::ANY_EXTEND &&
+        (TLI.isZExtFree(Val, RegisterVT) || isa<ConstantSDNode>(Val)))
       ExtendKind = ISD::ZERO_EXTEND;
 
     getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part],
                    NumParts, RegisterVT, V, CallConv, ExtendKind);
     Part += NumParts;
   }
 
   // Copy the parts into the registers.

llvm/test/CodeGen/RISCV/aext-to-sext.ll

 bar:
   ret i32 %b
 }
 
 ; The code that inserts AssertZExt based on predecessor information assumes
 ; constants are zero extended for phi incoming values so an AssertZExt is
 ; created in 'merge' allowing the zext to be removed.
 ; SelectionDAG::getNode treats any_extend of i32 constants as sext for RISCV.
-; The code that creates phi incoming values in the predecessors creates an
-; any_extend for the constants which then gets treated as a sext by getNode.
-; This means the zext was not safe to remove.
+; This code used to miscompile because the code that creates phi incoming values
+; in the predecessors created any_extend for the constants which then gets
+; treated as a sext by getNode. This made the removal of the zext incorrect.
+; SelectionDAGBuilder now creates a zero_extend instead of an any_extend to
+; match the assumption.
+; FIXME: RISCV would prefer constant inputs to phis to be sign extended.
 define i64 @miscompile(i32 %c) {
 ; RV64I-LABEL: miscompile:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    beqz a0, .LBB2_2
+; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    beqz a1, .LBB2_2
-; RV64I-NEXT:  # %bb.1: # %merge
+; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB2_2: # %iffalse
-; RV64I-NEXT:    li a0, -2
+; RV64I-NEXT:    li a0, 1
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    addi a0, a0, -2
 ; RV64I-NEXT:    ret
   %a = icmp ne i32 %c, 0
   br i1 %a, label %iftrue, label %iffalse
 
 iftrue:
   br label %merge
 
 iffalse:
   br label %merge
 
 merge:
   %b = phi i32 [-1, %iftrue], [-2, %iffalse]
   %d = zext i32 %b to i64
   ret i64 %d
 }