[RISCV] The immediate version of sgt/ugt lowering to slti/sltiu + xori

[Miss_Grape]

Summary

[jrtc27]

There's a whole set of these you could do; why this one in particular? And what about it makes it RV32-specific?

[craig.topper]

In D122051#3393725, @jrtc27 wrote:

There's a whole set of these you could do; why this one in particular? And what about it makes it RV32-specific?

Agreed, I'd at least expect the same for setugt.

llvm/lib/Target/RISCV/RISCVInstrInfo.td

354

Can we use [-2049, 2046] to describe the range like the comments on AddiPair? That's a more common way to represent a range. The ~ character in there is weird. Please update the comment on simm12_plus1 as well.

[craig.topper]

In D122051#3393730, @craig.topper wrote:

In D122051#3393725, @jrtc27 wrote:

There's a whole set of these you could do; why this one in particular? And what about it makes it RV32-specific?

Agreed, I'd at least expect the same for setugt.

Though I guess that requires a special case for the discontinuity around 0.

[craig.topper]

llvm/test/CodeGen/RISCV/arith-with-overflow.ll

32

This looks like a regression

[Miss_Grape]

In D122051#3393725, @jrtc27 wrote:

There's a whole set of these you could do; why this one in particular? And what about it makes it RV32-specific?

I have add sgt/ugt ,and there are support RV32/RV64

[Miss_Grape]

In D122051#3393730, @craig.topper wrote:

In D122051#3393725, @jrtc27 wrote:

There's a whole set of these you could do; why this one in particular? And what about it makes it RV32-specific?

Agreed, I'd at least expect the same for setugt.

done

[benshi001]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

355

The zero value should be excluded, which is not needed to do li, and case just
be used with the register X0.

[Miss_Grape]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

354

done

llvm/test/CodeGen/RISCV/arith-with-overflow.ll

32

sgtz a3 a1 ------> slt a3, X0, a1
slt a3, X0, a1---->slti a1, a1, 1 + xori a1, a1, 1
I think the result of the above assembly conversion is correct， which can reduce the registers use.

[benshi001]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

355

I think

1. The form (-2049 <= Imm && Imm < 0) || (0 < Imm && Imm <= 2046) is more clear.

2. Do a further check that the imm node has only one use.

[Miss_Grape]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

355

I don't think we need to specifically consider the case of Imm == 0， riscv-gcc did not exclude it alone

[craig.topper]

llvm/test/CodeGen/RISCV/arith-with-overflow.ll

32

If a1 was free to use as a destination register then it could have been sgtz a1, a1. This patch just moved the slti+xor below the the sub. We could do the same thing with the sgtz but it wouldn't change the number of registers needed.

[khchen]

llvm/test/CodeGen/RISCV/float-fcmp-strict.ll

72

It seems no any benefits in this case, is it expected?

[Miss_Grape]

llvm/test/CodeGen/RISCV/float-fcmp-strict.ll

72

sgtz ---->slt rd, X0, rs2
slt rd, 0 rs2 ---> slti + xori
which can reduce the usage of one register

[Miss_Grape]

llvm/test/CodeGen/RISCV/arith-with-overflow.ll

32

Do you want me to exclude scenarios where Imm == 0 ？

[Miss_Grape]

immediate version of sgt/ugt lowering to slti/sltiu + xori， and exclude imm == 0

[Miss_Grape]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

355

done

llvm/test/CodeGen/RISCV/float-fcmp-strict.ll

72

If this is the case（sgtz x1，x1）, there is really no benefit，so I have excluded the case where the immediate value is 0

[Miss_Grape]

Add test for sgt/ugt， which Imm == 0

[benshi001]

llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll

1484

This case becames poor, due to a0 (containing -1) has mutlple uses. So I think your need an extra check, that the immediate (simm12_sub1_exc0) has only one use.

[Miss_Grape]

Increase the limit that immediate can only be used once

[benshi001]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1217

For this setugt, it would be better to make a comment, the coresspondant positve value range of [-2049, -1], which is different on rv32 and rv64.

llvm/test/CodeGen/RISCV/i32-icmp.ll

218

Though the code is correct, it would be better to use positive number, which is more clear.

[benshi001]

llvm/test/CodeGen/RISCV/i32-icmp.ll

179

We need a more test case of -2050, which is the lower bound of simm12_sub1_exc0

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

360

There's an extra space before the third use of Imm

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

355

Use simm12_sub1_nonzero that's consistent with simm5_plus1_nonzero from RISCVInstrInfoV.td

llvm/test/CodeGen/RISCV/i32-icmp.ll

1

Is there a similar test file for rv64?

[Miss_Grape]

Correction review comments

[Miss_Grape]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

355

done

360

done

llvm/test/CodeGen/RISCV/i32-icmp.ll

1

I have add i64-icmp.ll test， and just test sgt/ugt. I will resubmit a new patch for anthor icmp tests

179

done

[craig.topper]

llvm/test/CodeGen/RISCV/i64-icmp.ll

5 ↗

(On Diff #418433)

Shouldn't this use i64 instead of i32 to match the file name?

[Miss_Grape]

Updata test

[Miss_Grape]

llvm/test/CodeGen/RISCV/i64-icmp.ll

5 ↗

(On Diff #418433)

done

[craig.topper]

LGTM with that change.

llvm/lib/Target/RISCV/RISCVInstrInfo.td

355

Use minus1 instead of sub1 to match better with the plus1 PatFrag abobe.

[benshi001]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

355

sorry, I did not notice your comments when commiting, and I will change that to minus1 in my next commit.

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 def ixlenimm : Operand<XLenVT>;
 
 def ixlenimm_li : Operand<XLenVT> {
   let ParserMatchClass = ImmXLenAsmOperand<"", "LI">;
 }
 
 // Standalone (codegen-only) immleaf patterns.
 
-// A 12-bit signed immediate plus one where the imm range will be -2047~2048.
+// A 12-bit signed immediate plus one where the imm range will be [-2047, 2048].
 def simm12_plus1 : ImmLeaf<XLenVT,
   [{return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
 
+// A 12-bit signed immediate sub one where the imm range will be [-2049, 2046].
+def simm12_sub1 : ImmLeaf<XLenVT,
+  [{return (isInt<12>(Imm) && Imm != 2047) || Imm == -2049;}]>;
+
 // A 6-bit constant greater than 32.
 def uimm6gt32 : ImmLeaf<XLenVT, [{
   return isUInt<6>(Imm) && Imm > 32;
 }]>;
 
 // Addressing modes.
 // Necessary because a frameindex can't be matched directly in a pattern.
 def AddrFI : ComplexPattern<iPTR, 1, "SelectAddrFI", [frameindex], []>;
 def BaseAddr : ComplexPattern<iPTR, 1, "SelectBaseAddr">;
 
 // Return the negation of an immediate value.
 def NegImm : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(-N->getSExtValue(), SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
 // Return an immediate value minus 32.
 def ImmSub32 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(N->getSExtValue() - 32, SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
-// Return an immediate value plus 32.
-def ImmPlus32 : SDNodeXForm<imm, [{
-  return CurDAG->getTargetConstant(N->getSExtValue() + 32, SDLoc(N),
+// Return an immediate value plus 1.
+def ImmPlus1 : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(N->getSExtValue() + 1, SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
 // Return an immediate subtracted from XLen.
 def ImmSubFromXLen : SDNodeXForm<imm, [{
   uint64_t XLen = Subtarget->getXLen();
   return CurDAG->getTargetConstant(XLen - N->getZExtValue(), SDLoc(N),
                                    N->getValueType(0));

 def : Pat<(setne GPR:$rs1, simm12_plus1:$imm12),
           (SLTU X0, (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)))>;
 def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>;
 def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>;
 def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>;
 def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>;
 def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
 def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
+def : Pat<(setgt GPR:$rs1, simm12_sub1:$imm),
+          (XORI (SLTI GPR:$rs1, (ImmPlus1 simm12_sub1:$imm)), 1)>;
+def : Pat<(setugt GPR:$rs1, simm12_sub1:$imm),
+          (XORI (SLTIU GPR:$rs1, (ImmPlus1 simm12_sub1:$imm)), 1)>;
 
 def IntCCtoRISCVCC : SDNodeXForm<riscv_selectcc, [{
   ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
   RISCVCC::CondCode BrCC = getRISCVCCForIntCC(CC);
   return CurDAG->getTargetConstant(BrCC, SDLoc(N), Subtarget->getXLenVT());
 }]>;
 
 def riscv_selectcc_frag : PatFrag<(ops node:$lhs, node:$rhs, node:$cc,

llvm/test/CodeGen/RISCV/arith-with-overflow.ll

entry:
   %ovf = extractvalue {i32, i1} %x, 1
   store i32 %calc, i32* %c
   ret i1 %ovf
 }
 
 define i1 @ssub(i32 %a, i32 %b, i32* %c) nounwind {
 ; RV32I-LABEL: ssub:
 ; RV32I:       # %bb.0: # %entry
-; RV32I-NEXT:    sgtz a3, a1
-; RV32I-NEXT:    sub a1, a0, a1
-; RV32I-NEXT:    slt a0, a1, a0
-; RV32I-NEXT:    xor a0, a3, a0
-; RV32I-NEXT:    sw a1, 0(a2)
+; RV32I-NEXT:    sub a3, a0, a1
+; RV32I-NEXT:    slt a0, a3, a0
+; RV32I-NEXT:    slti a1, a1, 1
+; RV32I-NEXT:    xori a1, a1, 1
+; RV32I-NEXT:    xor a0, a1, a0
+; RV32I-NEXT:    sw a3, 0(a2)
 ; RV32I-NEXT:    ret
 entry:
   %x = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
   %calc = extractvalue {i32, i1} %x, 0
   %ovf = extractvalue {i32, i1} %x, 1
   store i32 %calc, i32* %c
   ret i1 %ovf
 }

llvm/test/CodeGen/RISCV/double-fcmp-strict.ll

 ; RV64IFD-NEXT:    feq.d zero, fa1, fa0
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtdf2@plt
-; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    slti a0, a0, 1
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ogt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __gtdf2@plt
-; RV64I-NEXT:    sgtz a0, a0
+; RV64I-NEXT:    slti a0, a0, 1
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; RV64IFD-NEXT:    feq.d zero, fa1, fa0
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_oge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __gedf2@plt
-; RV64I-NEXT:    li a1, -1
-; RV64I-NEXT:    slt a0, a1, a0
+; RV64I-NEXT:    slti a0, a0, 0
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; RV64IFD-NEXT:    feq.d zero, fa0, fa1
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ledf2@plt
-; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    slti a0, a0, 1
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ugt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __ledf2@plt
-; RV64I-NEXT:    sgtz a0, a0
+; RV64I-NEXT:    slti a0, a0, 1
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; RV64IFD-NEXT:    feq.d zero, fa0, fa1
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltdf2@plt
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_uge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __ltdf2@plt
-; RV64I-NEXT:    li a1, -1
-; RV64I-NEXT:    slt a0, a1, a0
+; RV64I-NEXT:    slti a0, a0, 0
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; RV64IFD-NEXT:    flt.d a0, fa1, fa0
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtdf2@plt
-; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    slti a0, a0, 1
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmps_ogt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __gtdf2@plt
-; RV64I-NEXT:    sgtz a0, a0
+; RV64I-NEXT:    slti a0, a0, 1
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_oge(double %a, double %b) nounwind strictfp {
 ; RV32IFD-LABEL: fcmps_oge:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    fle.d a0, fa1, fa0
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcmps_oge:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fle.d a0, fa1, fa0
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmps_oge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __gedf2@plt
-; RV64I-NEXT:    li a1, -1
-; RV64I-NEXT:    slt a0, a1, a0
+; RV64I-NEXT:    slti a0, a0, 0
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; RV64IFD-NEXT:    xori a0, a0, 1
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ledf2@plt
-; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    slti a0, a0, 1
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmps_ugt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __ledf2@plt
-; RV64I-NEXT:    sgtz a0, a0
+; RV64I-NEXT:    slti a0, a0, 1
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; RV64IFD-NEXT:    xori a0, a0, 1
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltdf2@plt
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmps_uge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __ltdf2@plt
-; RV64I-NEXT:    li a1, -1
-; RV64I-NEXT:    slt a0, a1, a0
+; RV64I-NEXT:    slti a0, a0, 0
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

llvm/test/CodeGen/RISCV/double-fcmp.ll

 ; RV64IFD-NEXT:    flt.d a0, fa1, fa0
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtdf2@plt
-; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    slti a0, a0, 1
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ogt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __gtdf2@plt
-; RV64I-NEXT:    sgtz a0, a0
+; RV64I-NEXT:    slti a0, a0, 1
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ogt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oge(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: fcmp_oge:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    fle.d a0, fa1, fa0
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcmp_oge:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fle.d a0, fa1, fa0
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_oge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __gedf2@plt
-; RV64I-NEXT:    li a1, -1
-; RV64I-NEXT:    slt a0, a1, a0
+; RV64I-NEXT:    slti a0, a0, 0
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp oge double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; RV64IFD-NEXT:    xori a0, a0, 1
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ledf2@plt
-; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    slti a0, a0, 1
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ugt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __ledf2@plt
-; RV64I-NEXT:    sgtz a0, a0
+; RV64I-NEXT:    slti a0, a0, 1
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ugt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; RV64IFD-NEXT:    xori a0, a0, 1
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltdf2@plt
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_uge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __ltdf2@plt
-; RV64I-NEXT:    li a1, -1
-; RV64I-NEXT:    slt a0, a1, a0
+; RV64I-NEXT:    slti a0, a0, 0
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp uge double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

llvm/test/CodeGen/RISCV/float-fcmp-strict.ll

 ; RV64IF-NEXT:    feq.s zero, fa1, fa0
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    slti a0, a0, 1
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ogt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __gtsf2@plt
-; RV64I-NEXT:    sgtz a0, a0
+; RV64I-NEXT:    slti a0, a0, 1
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; RV64IF-NEXT:    feq.s zero, fa1, fa0
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_oge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __gesf2@plt
-; RV64I-NEXT:    li a1, -1
-; RV64I-NEXT:    slt a0, a1, a0
+; RV64I-NEXT:    slti a0, a0, 0
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; RV64IF-NEXT:    feq.s zero, fa0, fa1
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
-; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    slti a0, a0, 1
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ugt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __lesf2@plt
-; RV64I-NEXT:    sgtz a0, a0
+; RV64I-NEXT:    slti a0, a0, 1
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; RV64IF-NEXT:    feq.s zero, fa0, fa1
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_uge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __ltsf2@plt
-; RV64I-NEXT:    li a1, -1
-; RV64I-NEXT:    slt a0, a1, a0
+; RV64I-NEXT:    slti a0, a0, 0
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; RV64IF-NEXT:    flt.s a0, fa1, fa0
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    slti a0, a0, 1
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmps_ogt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __gtsf2@plt
-; RV64I-NEXT:    sgtz a0, a0
+; RV64I-NEXT:    slti a0, a0, 1
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_oge(float %a, float %b) nounwind strictfp {
 ; RV32IF-LABEL: fcmps_oge:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fle.s a0, fa1, fa0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcmps_oge:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fle.s a0, fa1, fa0
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmps_oge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __gesf2@plt
-; RV64I-NEXT:    li a1, -1
-; RV64I-NEXT:    slt a0, a1, a0
+; RV64I-NEXT:    slti a0, a0, 0
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; RV64IF-NEXT:    xori a0, a0, 1
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
-; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    slti a0, a0, 1
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmps_ugt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __lesf2@plt
-; RV64I-NEXT:    sgtz a0, a0
+; RV64I-NEXT:    slti a0, a0, 1
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; RV64IF-NEXT:    xori a0, a0, 1
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmps_uge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __ltsf2@plt
-; RV64I-NEXT:    li a1, -1
-; RV64I-NEXT:    slt a0, a1, a0
+; RV64I-NEXT:    slti a0, a0, 0
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

llvm/test/CodeGen/RISCV/float-fcmp.ll

 ; RV64IF-NEXT:    flt.s a0, fa1, fa0
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    slti a0, a0, 1
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ogt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __gtsf2@plt
-; RV64I-NEXT:    sgtz a0, a0
+; RV64I-NEXT:    slti a0, a0, 1
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ogt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oge(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fcmp_oge:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fle.s a0, fa1, fa0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcmp_oge:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fle.s a0, fa1, fa0
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_oge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __gesf2@plt
-; RV64I-NEXT:    li a1, -1
-; RV64I-NEXT:    slt a0, a1, a0
+; RV64I-NEXT:    slti a0, a0, 0
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp oge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; RV64IF-NEXT:    xori a0, a0, 1
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
-; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    slti a0, a0, 1
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ugt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __lesf2@plt
-; RV64I-NEXT:    sgtz a0, a0
+; RV64I-NEXT:    slti a0, a0, 1
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ugt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

 ; RV64IF-NEXT:    xori a0, a0, 1
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_uge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __ltsf2@plt
-; RV64I-NEXT:    li a1, -1
-; RV64I-NEXT:    slt a0, a1, a0
+; RV64I-NEXT:    slti a0, a0, 0
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp uge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 

llvm/test/CodeGen/RISCV/fpclamptosat.ll

 ; RV32IF-NEXT:    bnez a4, .LBB0_4
 ; RV32IF-NEXT:  .LBB0_3: # %entry
 ; RV32IF-NEXT:    li a1, 0
 ; RV32IF-NEXT:    mv a0, a3
 ; RV32IF-NEXT:  .LBB0_4: # %entry
 ; RV32IF-NEXT:    li a3, -1
 ; RV32IF-NEXT:    beq a1, a3, .LBB0_6
 ; RV32IF-NEXT:  # %bb.5: # %entry
-; RV32IF-NEXT:    slt a1, a3, a1
+; RV32IF-NEXT:    slti a1, a1, 0
+; RV32IF-NEXT:    xori a1, a1, 1
 ; RV32IF-NEXT:    beqz a1, .LBB0_7
 ; RV32IF-NEXT:    j .LBB0_8
 ; RV32IF-NEXT:  .LBB0_6:
 ; RV32IF-NEXT:    sltu a1, a2, a0
 ; RV32IF-NEXT:    bnez a1, .LBB0_8
 ; RV32IF-NEXT:  .LBB0_7: # %entry
 ; RV32IF-NEXT:    lui a0, 524288
 ; RV32IF-NEXT:  .LBB0_8: # %entry

 ; RV32IF-NEXT:    snez a2, a2
 ; RV32IF-NEXT:    bnez a2, .LBB2_4
 ; RV32IF-NEXT:  .LBB2_3: # %entry
 ; RV32IF-NEXT:    li a1, 0
 ; RV32IF-NEXT:    li a0, -1
 ; RV32IF-NEXT:  .LBB2_4: # %entry
 ; RV32IF-NEXT:    beqz a1, .LBB2_6
 ; RV32IF-NEXT:  # %bb.5: # %entry
-; RV32IF-NEXT:    sgtz a1, a1
+; RV32IF-NEXT:    slti a1, a1, 1
+; RV32IF-NEXT:    xori a1, a1, 1
 ; RV32IF-NEXT:    beqz a1, .LBB2_7
 ; RV32IF-NEXT:    j .LBB2_8
 ; RV32IF-NEXT:  .LBB2_6:
 ; RV32IF-NEXT:    snez a1, a0
 ; RV32IF-NEXT:    bnez a1, .LBB2_8
 ; RV32IF-NEXT:  .LBB2_7: # %entry
 ; RV32IF-NEXT:    li a0, 0
 ; RV32IF-NEXT:  .LBB2_8: # %entry

 ; RV32-NEXT:    bnez a4, .LBB6_4
 ; RV32-NEXT:  .LBB6_3: # %entry
 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    mv a0, a3
 ; RV32-NEXT:  .LBB6_4: # %entry
 ; RV32-NEXT:    li a3, -1
 ; RV32-NEXT:    beq a1, a3, .LBB6_6
 ; RV32-NEXT:  # %bb.5: # %entry
-; RV32-NEXT:    slt a1, a3, a1
+; RV32-NEXT:    slti a1, a1, 0
+; RV32-NEXT:    xori a1, a1, 1
 ; RV32-NEXT:    beqz a1, .LBB6_7
 ; RV32-NEXT:    j .LBB6_8
 ; RV32-NEXT:  .LBB6_6:
 ; RV32-NEXT:    sltu a1, a2, a0
 ; RV32-NEXT:    bnez a1, .LBB6_8
 ; RV32-NEXT:  .LBB6_7: # %entry
 ; RV32-NEXT:    lui a0, 524288
 ; RV32-NEXT:  .LBB6_8: # %entry

 ; RV32-NEXT:    snez a2, a2
 ; RV32-NEXT:    bnez a2, .LBB8_4
 ; RV32-NEXT:  .LBB8_3: # %entry
 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    li a0, -1
 ; RV32-NEXT:  .LBB8_4: # %entry
 ; RV32-NEXT:    beqz a1, .LBB8_6
 ; RV32-NEXT:  # %bb.5: # %entry
-; RV32-NEXT:    sgtz a1, a1
+; RV32-NEXT:    slti a1, a1, 1
+; RV32-NEXT:    xori a1, a1, 1
 ; RV32-NEXT:    beqz a1, .LBB8_7
 ; RV32-NEXT:    j .LBB8_8
 ; RV32-NEXT:  .LBB8_6:
 ; RV32-NEXT:    snez a1, a0
 ; RV32-NEXT:    bnez a1, .LBB8_8
 ; RV32-NEXT:  .LBB8_7: # %entry
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:  .LBB8_8: # %entry

 ; RV32IF-NEXT:    li a0, -1
 ; RV32IF-NEXT:    mv a1, a5
 ; RV32IF-NEXT:    bne a1, a4, .LBB18_6
 ; RV32IF-NEXT:  .LBB18_8:
 ; RV32IF-NEXT:    snez a4, a0
 ; RV32IF-NEXT:    and a3, a3, a2
 ; RV32IF-NEXT:    beq a3, a6, .LBB18_10
 ; RV32IF-NEXT:  .LBB18_9: # %entry
-; RV32IF-NEXT:    slt a4, a6, a2
+; RV32IF-NEXT:    slti a2, a2, 0
+; RV32IF-NEXT:    xori a4, a2, 1
 ; RV32IF-NEXT:  .LBB18_10: # %entry
 ; RV32IF-NEXT:    bnez a4, .LBB18_12
 ; RV32IF-NEXT:  # %bb.11: # %entry
 ; RV32IF-NEXT:    li a0, 0
 ; RV32IF-NEXT:    lui a1, 524288
 ; RV32IF-NEXT:  .LBB18_12: # %entry
 ; RV32IF-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 32

 ; RV64IF-NEXT:    bnez a4, .LBB18_4
 ; RV64IF-NEXT:  .LBB18_3: # %entry
 ; RV64IF-NEXT:    li a1, 0
 ; RV64IF-NEXT:    mv a0, a3
 ; RV64IF-NEXT:  .LBB18_4: # %entry
 ; RV64IF-NEXT:    slli a3, a2, 63
 ; RV64IF-NEXT:    beq a1, a2, .LBB18_6
 ; RV64IF-NEXT:  # %bb.5: # %entry
-; RV64IF-NEXT:    slt a1, a2, a1
+; RV64IF-NEXT:    slti a1, a1, 0
+; RV64IF-NEXT:    xori a1, a1, 1
 ; RV64IF-NEXT:    beqz a1, .LBB18_7
 ; RV64IF-NEXT:    j .LBB18_8
 ; RV64IF-NEXT:  .LBB18_6:
 ; RV64IF-NEXT:    sltu a1, a3, a0
 ; RV64IF-NEXT:    bnez a1, .LBB18_8
 ; RV64IF-NEXT:  .LBB18_7: # %entry
 ; RV64IF-NEXT:    mv a0, a3
 ; RV64IF-NEXT:  .LBB18_8: # %entry

 ; RV32IFD-NEXT:    li a0, -1
 ; RV32IFD-NEXT:    mv a1, a5
 ; RV32IFD-NEXT:    bne a1, a4, .LBB18_6
 ; RV32IFD-NEXT:  .LBB18_8:
 ; RV32IFD-NEXT:    snez a4, a0
 ; RV32IFD-NEXT:    and a3, a3, a2
 ; RV32IFD-NEXT:    beq a3, a6, .LBB18_10
 ; RV32IFD-NEXT:  .LBB18_9: # %entry
-; RV32IFD-NEXT:    slt a4, a6, a2
+; RV32IFD-NEXT:    slti a2, a2, 0
+; RV32IFD-NEXT:    xori a4, a2, 1
 ; RV32IFD-NEXT:  .LBB18_10: # %entry
 ; RV32IFD-NEXT:    bnez a4, .LBB18_12
 ; RV32IFD-NEXT:  # %bb.11: # %entry
 ; RV32IFD-NEXT:    li a0, 0
 ; RV32IFD-NEXT:    lui a1, 524288
 ; RV32IFD-NEXT:  .LBB18_12: # %entry
 ; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 32

 ; RV32IF-NEXT:    or a4, a1, a2
 ; RV32IF-NEXT:    li a1, 0
 ; RV32IF-NEXT:    beqz a4, .LBB20_5
 ; RV32IF-NEXT:  # %bb.4: # %entry
 ; RV32IF-NEXT:    mv a1, a0
 ; RV32IF-NEXT:  .LBB20_5: # %entry
 ; RV32IF-NEXT:    bnez a1, .LBB20_9
 ; RV32IF-NEXT:  # %bb.6: # %entry
-; RV32IF-NEXT:    li a0, 0
 ; RV32IF-NEXT:    li a2, 0
+; RV32IF-NEXT:    li a0, 0
 ; RV32IF-NEXT:    li a3, 1
-; RV32IF-NEXT:    bnez a2, .LBB20_10
+; RV32IF-NEXT:    bnez a1, .LBB20_10
 ; RV32IF-NEXT:  .LBB20_7:
-; RV32IF-NEXT:    snez a4, a3
-; RV32IF-NEXT:    bnez a1, .LBB20_11
+; RV32IF-NEXT:    snez a4, a0
+; RV32IF-NEXT:    bnez a2, .LBB20_11
 ; RV32IF-NEXT:  .LBB20_8:
-; RV32IF-NEXT:    snez a5, a0
+; RV32IF-NEXT:    snez a5, a3
 ; RV32IF-NEXT:    or a2, a3, a2
 ; RV32IF-NEXT:    bnez a2, .LBB20_12
 ; RV32IF-NEXT:    j .LBB20_13
 ; RV32IF-NEXT:  .LBB20_9:
 ; RV32IF-NEXT:    lw a1, 12(sp)
 ; RV32IF-NEXT:    lw a0, 8(sp)
-; RV32IF-NEXT:    beqz a2, .LBB20_7
+; RV32IF-NEXT:    beqz a1, .LBB20_7
 ; RV32IF-NEXT:  .LBB20_10: # %entry
-; RV32IF-NEXT:    sgtz a4, a2
-; RV32IF-NEXT:    beqz a1, .LBB20_8
+; RV32IF-NEXT:    snez a4, a1
+; RV32IF-NEXT:    beqz a2, .LBB20_8
 ; RV32IF-NEXT:  .LBB20_11: # %entry
-; RV32IF-NEXT:    snez a5, a1
+; RV32IF-NEXT:    slti a5, a2, 1
+; RV32IF-NEXT:    xori a5, a5, 1
 ; RV32IF-NEXT:    or a2, a3, a2
 ; RV32IF-NEXT:    beqz a2, .LBB20_13
 ; RV32IF-NEXT:  .LBB20_12: # %entry
-; RV32IF-NEXT:    mv a5, a4
+; RV32IF-NEXT:    mv a4, a5
 ; RV32IF-NEXT:  .LBB20_13: # %entry
-; RV32IF-NEXT:    bnez a5, .LBB20_15
+; RV32IF-NEXT:    bnez a4, .LBB20_15
 ; RV32IF-NEXT:  # %bb.14: # %entry
 ; RV32IF-NEXT:    li a0, 0
 ; RV32IF-NEXT:    li a1, 0
 ; RV32IF-NEXT:  .LBB20_15: # %entry
 ; RV32IF-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 32
 ; RV32IF-NEXT:    ret
 ;
 ; RV64-LABEL: ustest_f64i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    call __fixdfti@plt
 ; RV64-NEXT:    blez a1, .LBB20_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    li a1, 1
 ; RV64-NEXT:  .LBB20_2: # %entry
 ; RV64-NEXT:    beqz a1, .LBB20_4
 ; RV64-NEXT:  # %bb.3: # %entry
-; RV64-NEXT:    sgtz a1, a1
+; RV64-NEXT:    slti a1, a1, 1
+; RV64-NEXT:    xori a1, a1, 1
 ; RV64-NEXT:    beqz a1, .LBB20_5
 ; RV64-NEXT:    j .LBB20_6
 ; RV64-NEXT:  .LBB20_4:
 ; RV64-NEXT:    snez a1, a0
 ; RV64-NEXT:    bnez a1, .LBB20_6
 ; RV64-NEXT:  .LBB20_5: # %entry
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:  .LBB20_6: # %entry

 ; RV32IFD-NEXT:    or a4, a1, a2
 ; RV32IFD-NEXT:    li a1, 0
 ; RV32IFD-NEXT:    beqz a4, .LBB20_5
 ; RV32IFD-NEXT:  # %bb.4: # %entry
 ; RV32IFD-NEXT:    mv a1, a0
 ; RV32IFD-NEXT:  .LBB20_5: # %entry
 ; RV32IFD-NEXT:    bnez a1, .LBB20_9
 ; RV32IFD-NEXT:  # %bb.6: # %entry
-; RV32IFD-NEXT:    li a0, 0
 ; RV32IFD-NEXT:    li a2, 0
+; RV32IFD-NEXT:    li a0, 0
 ; RV32IFD-NEXT:    li a3, 1
-; RV32IFD-NEXT:    bnez a2, .LBB20_10
+; RV32IFD-NEXT:    bnez a1, .LBB20_10
 ; RV32IFD-NEXT:  .LBB20_7:
-; RV32IFD-NEXT:    snez a4, a3
-; RV32IFD-NEXT:    bnez a1, .LBB20_11
+; RV32IFD-NEXT:    snez a4, a0
+; RV32IFD-NEXT:    bnez a2, .LBB20_11
 ; RV32IFD-NEXT:  .LBB20_8:
-; RV32IFD-NEXT:    snez a5, a0
+; RV32IFD-NEXT:    snez a5, a3
 ; RV32IFD-NEXT:    or a2, a3, a2
 ; RV32IFD-NEXT:    bnez a2, .LBB20_12
 ; RV32IFD-NEXT:    j .LBB20_13
 ; RV32IFD-NEXT:  .LBB20_9:
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
-; RV32IFD-NEXT:    beqz a2, .LBB20_7
+; RV32IFD-NEXT:    beqz a1, .LBB20_7
 ; RV32IFD-NEXT:  .LBB20_10: # %entry
-; RV32IFD-NEXT:    sgtz a4, a2
-; RV32IFD-NEXT:    beqz a1, .LBB20_8
+; RV32IFD-NEXT:    snez a4, a1
+; RV32IFD-NEXT:    beqz a2, .LBB20_8
 ; RV32IFD-NEXT:  .LBB20_11: # %entry
-; RV32IFD-NEXT:    snez a5, a1
+; RV32IFD-NEXT:    slti a5, a2, 1
+; RV32IFD-NEXT:    xori a5, a5, 1
 ; RV32IFD-NEXT:    or a2, a3, a2
 ; RV32IFD-NEXT:    beqz a2, .LBB20_13
 ; RV32IFD-NEXT:  .LBB20_12: # %entry
-; RV32IFD-NEXT:    mv a5, a4
+; RV32IFD-NEXT:    mv a4, a5
 ; RV32IFD-NEXT:  .LBB20_13: # %entry
-; RV32IFD-NEXT:    bnez a5, .LBB20_15
+; RV32IFD-NEXT:    bnez a4, .LBB20_15
 ; RV32IFD-NEXT:  # %bb.14: # %entry
 ; RV32IFD-NEXT:    li a0, 0
 ; RV32IFD-NEXT:    li a1, 0
 ; RV32IFD-NEXT:  .LBB20_15: # %entry
 ; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
 entry:

 ; RV32-NEXT:    li a0, -1
 ; RV32-NEXT:    mv a1, a5
 ; RV32-NEXT:    bne a1, a4, .LBB21_6
 ; RV32-NEXT:  .LBB21_8:
 ; RV32-NEXT:    snez a4, a0
 ; RV32-NEXT:    and a3, a3, a2
 ; RV32-NEXT:    beq a3, a6, .LBB21_10
 ; RV32-NEXT:  .LBB21_9: # %entry
-; RV32-NEXT:    slt a4, a6, a2
+; RV32-NEXT:    slti a2, a2, 0
+; RV32-NEXT:    xori a4, a2, 1
 ; RV32-NEXT:  .LBB21_10: # %entry
 ; RV32-NEXT:    bnez a4, .LBB21_12
 ; RV32-NEXT:  # %bb.11: # %entry
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    lui a1, 524288
 ; RV32-NEXT:  .LBB21_12: # %entry
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32

 ; RV32-NEXT:    or a4, a1, a2
 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    beqz a4, .LBB23_5
 ; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    mv a1, a0
 ; RV32-NEXT:  .LBB23_5: # %entry
 ; RV32-NEXT:    bnez a1, .LBB23_9
 ; RV32-NEXT:  # %bb.6: # %entry
-; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    li a2, 0
+; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    li a3, 1
-; RV32-NEXT:    bnez a2, .LBB23_10
+; RV32-NEXT:    bnez a1, .LBB23_10
 ; RV32-NEXT:  .LBB23_7:
-; RV32-NEXT:    snez a4, a3
-; RV32-NEXT:    bnez a1, .LBB23_11
+; RV32-NEXT:    snez a4, a0
+; RV32-NEXT:    bnez a2, .LBB23_11
 ; RV32-NEXT:  .LBB23_8:
-; RV32-NEXT:    snez a5, a0
+; RV32-NEXT:    snez a5, a3
 ; RV32-NEXT:    or a2, a3, a2
 ; RV32-NEXT:    bnez a2, .LBB23_12
 ; RV32-NEXT:    j .LBB23_13
 ; RV32-NEXT:  .LBB23_9:
 ; RV32-NEXT:    lw a1, 12(sp)
 ; RV32-NEXT:    lw a0, 8(sp)
-; RV32-NEXT:    beqz a2, .LBB23_7
+; RV32-NEXT:    beqz a1, .LBB23_7
 ; RV32-NEXT:  .LBB23_10: # %entry
-; RV32-NEXT:    sgtz a4, a2
-; RV32-NEXT:    beqz a1, .LBB23_8
+; RV32-NEXT:    snez a4, a1
+; RV32-NEXT:    beqz a2, .LBB23_8
 ; RV32-NEXT:  .LBB23_11: # %entry
-; RV32-NEXT:    snez a5, a1
+; RV32-NEXT:    slti a5, a2, 1
+; RV32-NEXT:    xori a5, a5, 1
 ; RV32-NEXT:    or a2, a3, a2
 ; RV32-NEXT:    beqz a2, .LBB23_13
 ; RV32-NEXT:  .LBB23_12: # %entry
-; RV32-NEXT:    mv a5, a4
+; RV32-NEXT:    mv a4, a5
 ; RV32-NEXT:  .LBB23_13: # %entry
-; RV32-NEXT:    bnez a5, .LBB23_15
+; RV32-NEXT:    bnez a4, .LBB23_15
 ; RV32-NEXT:  # %bb.14: # %entry
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:  .LBB23_15: # %entry
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ustest_f32i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    call __fixsfti@plt
 ; RV64-NEXT:    blez a1, .LBB23_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    li a1, 1
 ; RV64-NEXT:  .LBB23_2: # %entry
 ; RV64-NEXT:    beqz a1, .LBB23_4
 ; RV64-NEXT:  # %bb.3: # %entry
-; RV64-NEXT:    sgtz a1, a1
+; RV64-NEXT:    slti a1, a1, 1
+; RV64-NEXT:    xori a1, a1, 1
 ; RV64-NEXT:    beqz a1, .LBB23_5
 ; RV64-NEXT:    j .LBB23_6
 ; RV64-NEXT:  .LBB23_4:
 ; RV64-NEXT:    snez a1, a0
 ; RV64-NEXT:    bnez a1, .LBB23_6
 ; RV64-NEXT:  .LBB23_5: # %entry
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:  .LBB23_6: # %entry

 ; RV32-NEXT:    li a0, -1
 ; RV32-NEXT:    mv a1, a5
 ; RV32-NEXT:    bne a1, a4, .LBB24_6
 ; RV32-NEXT:  .LBB24_8:
 ; RV32-NEXT:    snez a4, a0
 ; RV32-NEXT:    and a3, a3, a2
 ; RV32-NEXT:    beq a3, a6, .LBB24_10
 ; RV32-NEXT:  .LBB24_9: # %entry
-; RV32-NEXT:    slt a4, a6, a2
+; RV32-NEXT:    slti a2, a2, 0
+; RV32-NEXT:    xori a4, a2, 1
 ; RV32-NEXT:  .LBB24_10: # %entry
 ; RV32-NEXT:    bnez a4, .LBB24_12
 ; RV32-NEXT:  # %bb.11: # %entry
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    lui a1, 524288
 ; RV32-NEXT:  .LBB24_12: # %entry
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32

 ; RV64-NEXT:    bnez a4, .LBB24_4
 ; RV64-NEXT:  .LBB24_3: # %entry
 ; RV64-NEXT:    li a1, 0
 ; RV64-NEXT:    mv a0, a3
 ; RV64-NEXT:  .LBB24_4: # %entry
 ; RV64-NEXT:    slli a3, a2, 63
 ; RV64-NEXT:    beq a1, a2, .LBB24_6
 ; RV64-NEXT:  # %bb.5: # %entry
-; RV64-NEXT:    slt a1, a2, a1
+; RV64-NEXT:    slti a1, a1, 0
+; RV64-NEXT:    xori a1, a1, 1
 ; RV64-NEXT:    beqz a1, .LBB24_7
 ; RV64-NEXT:    j .LBB24_8
 ; RV64-NEXT:  .LBB24_6:
 ; RV64-NEXT:    sltu a1, a3, a0
 ; RV64-NEXT:    bnez a1, .LBB24_8
 ; RV64-NEXT:  .LBB24_7: # %entry
 ; RV64-NEXT:    mv a0, a3
 ; RV64-NEXT:  .LBB24_8: # %entry

 ; RV32-NEXT:    or a4, a1, a2
 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    beqz a4, .LBB26_5
 ; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    mv a1, a0
 ; RV32-NEXT:  .LBB26_5: # %entry
 ; RV32-NEXT:    bnez a1, .LBB26_9
 ; RV32-NEXT:  # %bb.6: # %entry
-; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    li a2, 0
+; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    li a3, 1
-; RV32-NEXT:    bnez a2, .LBB26_10
+; RV32-NEXT:    bnez a1, .LBB26_10
 ; RV32-NEXT:  .LBB26_7:
-; RV32-NEXT:    snez a4, a3
-; RV32-NEXT:    bnez a1, .LBB26_11
+; RV32-NEXT:    snez a4, a0
+; RV32-NEXT:    bnez a2, .LBB26_11
 ; RV32-NEXT:  .LBB26_8:
-; RV32-NEXT:    snez a5, a0
+; RV32-NEXT:    snez a5, a3
 ; RV32-NEXT:    or a2, a3, a2
 ; RV32-NEXT:    bnez a2, .LBB26_12
 ; RV32-NEXT:    j .LBB26_13
 ; RV32-NEXT:  .LBB26_9:
 ; RV32-NEXT:    lw a1, 12(sp)
 ; RV32-NEXT:    lw a0, 8(sp)
-; RV32-NEXT:    beqz a2, .LBB26_7
+; RV32-NEXT:    beqz a1, .LBB26_7
 ; RV32-NEXT:  .LBB26_10: # %entry
-; RV32-NEXT:    sgtz a4, a2
-; RV32-NEXT:    beqz a1, .LBB26_8
+; RV32-NEXT:    snez a4, a1
+; RV32-NEXT:    beqz a2, .LBB26_8
 ; RV32-NEXT:  .LBB26_11: # %entry
-; RV32-NEXT:    snez a5, a1
+; RV32-NEXT:    slti a5, a2, 1
+; RV32-NEXT:    xori a5, a5, 1
 ; RV32-NEXT:    or a2, a3, a2
 ; RV32-NEXT:    beqz a2, .LBB26_13
 ; RV32-NEXT:  .LBB26_12: # %entry
-; RV32-NEXT:    mv a5, a4
+; RV32-NEXT:    mv a4, a5
 ; RV32-NEXT:  .LBB26_13: # %entry
-; RV32-NEXT:    bnez a5, .LBB26_15
+; RV32-NEXT:    bnez a4, .LBB26_15
 ; RV32-NEXT:  # %bb.14: # %entry
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:  .LBB26_15: # %entry
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ustest_f16i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    fmv.x.w a0, fa0
 ; RV64-NEXT:    call __extendhfsf2@plt
 ; RV64-NEXT:    call __fixsfti@plt
 ; RV64-NEXT:    blez a1, .LBB26_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    li a1, 1
 ; RV64-NEXT:  .LBB26_2: # %entry
 ; RV64-NEXT:    beqz a1, .LBB26_4
 ; RV64-NEXT:  # %bb.3: # %entry
-; RV64-NEXT:    sgtz a1, a1
+; RV64-NEXT:    slti a1, a1, 1
+; RV64-NEXT:    xori a1, a1, 1
 ; RV64-NEXT:    beqz a1, .LBB26_5
 ; RV64-NEXT:    j .LBB26_6
 ; RV64-NEXT:  .LBB26_4:
 ; RV64-NEXT:    snez a1, a0
 ; RV64-NEXT:    bnez a1, .LBB26_6
 ; RV64-NEXT:  .LBB26_5: # %entry
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:  .LBB26_6: # %entry

 ; RV32IF-NEXT:    mv a5, a4
 ; RV32IF-NEXT:    beqz a1, .LBB47_21
 ; RV32IF-NEXT:  .LBB47_17: # %entry
 ; RV32IF-NEXT:    mv a0, a4
 ; RV32IF-NEXT:    bnez a1, .LBB47_22
 ; RV32IF-NEXT:  .LBB47_18: # %entry
 ; RV32IF-NEXT:    beqz a2, .LBB47_23
 ; RV32IF-NEXT:  .LBB47_19: # %entry
-; RV32IF-NEXT:    sgtz a5, a2
+; RV32IF-NEXT:    slti a5, a2, 1
+; RV32IF-NEXT:    xori a5, a5, 1
 ; RV32IF-NEXT:    beqz a5, .LBB47_24
 ; RV32IF-NEXT:    j .LBB47_25
 ; RV32IF-NEXT:  .LBB47_20: # %entry
 ; RV32IF-NEXT:    li a2, 0
 ; RV32IF-NEXT:    mv a5, a4
 ; RV32IF-NEXT:    bnez a1, .LBB47_17
 ; RV32IF-NEXT:  .LBB47_21: # %entry
 ; RV32IF-NEXT:    li a5, 0

 ; RV32IFD-NEXT:    mv a5, a4
 ; RV32IFD-NEXT:    beqz a1, .LBB47_21
 ; RV32IFD-NEXT:  .LBB47_17: # %entry
 ; RV32IFD-NEXT:    mv a0, a4
 ; RV32IFD-NEXT:    bnez a1, .LBB47_22
 ; RV32IFD-NEXT:  .LBB47_18: # %entry
 ; RV32IFD-NEXT:    beqz a2, .LBB47_23
 ; RV32IFD-NEXT:  .LBB47_19: # %entry
-; RV32IFD-NEXT:    sgtz a5, a2
+; RV32IFD-NEXT:    slti a5, a2, 1
+; RV32IFD-NEXT:    xori a5, a5, 1
 ; RV32IFD-NEXT:    beqz a5, .LBB47_24
 ; RV32IFD-NEXT:    j .LBB47_25
 ; RV32IFD-NEXT:  .LBB47_20: # %entry
 ; RV32IFD-NEXT:    li a2, 0
 ; RV32IFD-NEXT:    mv a5, a4
 ; RV32IFD-NEXT:    bnez a1, .LBB47_17
 ; RV32IFD-NEXT:  .LBB47_21: # %entry
 ; RV32IFD-NEXT:    li a5, 0

 ; RV32-NEXT:    mv a5, a4
 ; RV32-NEXT:    beqz a1, .LBB50_21
 ; RV32-NEXT:  .LBB50_17: # %entry
 ; RV32-NEXT:    mv a0, a4
 ; RV32-NEXT:    bnez a1, .LBB50_22
 ; RV32-NEXT:  .LBB50_18: # %entry
 ; RV32-NEXT:    beqz a2, .LBB50_23
 ; RV32-NEXT:  .LBB50_19: # %entry
-; RV32-NEXT:    sgtz a5, a2
+; RV32-NEXT:    slti a5, a2, 1
+; RV32-NEXT:    xori a5, a5, 1
 ; RV32-NEXT:    beqz a5, .LBB50_24
 ; RV32-NEXT:    j .LBB50_25
 ; RV32-NEXT:  .LBB50_20: # %entry
 ; RV32-NEXT:    li a2, 0
 ; RV32-NEXT:    mv a5, a4
 ; RV32-NEXT:    bnez a1, .LBB50_17
 ; RV32-NEXT:  .LBB50_21: # %entry
 ; RV32-NEXT:    li a5, 0

 ; RV32-NEXT:    mv a5, a4
 ; RV32-NEXT:    beqz a1, .LBB53_21
 ; RV32-NEXT:  .LBB53_17: # %entry
 ; RV32-NEXT:    mv a0, a4
 ; RV32-NEXT:    bnez a1, .LBB53_22
 ; RV32-NEXT:  .LBB53_18: # %entry
 ; RV32-NEXT:    beqz a2, .LBB53_23
 ; RV32-NEXT:  .LBB53_19: # %entry
-; RV32-NEXT:    sgtz a5, a2
+; RV32-NEXT:    slti a5, a2, 1
+; RV32-NEXT:    xori a5, a5, 1
 ; RV32-NEXT:    beqz a5, .LBB53_24
 ; RV32-NEXT:    j .LBB53_25
 ; RV32-NEXT:  .LBB53_20: # %entry
 ; RV32-NEXT:    li a2, 0
 ; RV32-NEXT:    mv a5, a4
 ; RV32-NEXT:    bnez a1, .LBB53_17
 ; RV32-NEXT:  .LBB53_21: # %entry
 ; RV32-NEXT:    li a5, 0

llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll

 ; CHECK-NEXT:    li s1, 0
 ; CHECK-NEXT:    mv s0, a3
 ; CHECK-NEXT:  .LBB18_6: # %entry
 ; CHECK-NEXT:    beqz a4, .LBB18_10
 ; CHECK-NEXT:  # %bb.7: # %entry
 ; CHECK-NEXT:    slli a3, a0, 63
 ; CHECK-NEXT:    beq a1, a0, .LBB18_11
 ; CHECK-NEXT:  .LBB18_8: # %entry
-; CHECK-NEXT:    slt a1, a0, a1
+; CHECK-NEXT:    slti a1, a1, 0
+; CHECK-NEXT:    xori a1, a1, 1
 ; CHECK-NEXT:    bne s1, a0, .LBB18_12
 ; CHECK-NEXT:  .LBB18_9:
 ; CHECK-NEXT:    sltu a0, a3, s0
 ; CHECK-NEXT:    beqz a0, .LBB18_13
 ; CHECK-NEXT:    j .LBB18_14
 ; CHECK-NEXT:  .LBB18_10: # %entry
 ; CHECK-NEXT:    li a1, 0
 ; CHECK-NEXT:    mv a2, a3
 ; CHECK-NEXT:    slli a3, a0, 63
 ; CHECK-NEXT:    bne a1, a0, .LBB18_8
 ; CHECK-NEXT:  .LBB18_11:
 ; CHECK-NEXT:    sltu a1, a3, a2
 ; CHECK-NEXT:    beq s1, a0, .LBB18_9
 ; CHECK-NEXT:  .LBB18_12: # %entry
-; CHECK-NEXT:    slt a0, a0, s1
+; CHECK-NEXT:    slti a0, s1, 0
+; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    bnez a0, .LBB18_14
 ; CHECK-NEXT:  .LBB18_13: # %entry
 ; CHECK-NEXT:    mv s0, a3
 ; CHECK-NEXT:  .LBB18_14: # %entry
 ; CHECK-NEXT:    bnez a1, .LBB18_16
 ; CHECK-NEXT:  # %bb.15: # %entry
 ; CHECK-NEXT:    mv a2, a3
 ; CHECK-NEXT:  .LBB18_16: # %entry

 ; CHECK-NEXT:    bgtz s1, .LBB20_8
 ; CHECK-NEXT:  .LBB20_2: # %entry
 ; CHECK-NEXT:    bgtz a1, .LBB20_9
 ; CHECK-NEXT:  .LBB20_3: # %entry
 ; CHECK-NEXT:    bgtz s1, .LBB20_10
 ; CHECK-NEXT:  .LBB20_4: # %entry
 ; CHECK-NEXT:    beqz a3, .LBB20_11
 ; CHECK-NEXT:  .LBB20_5: # %entry
-; CHECK-NEXT:    sgtz a1, a3
+; CHECK-NEXT:    slti a1, a3, 1
+; CHECK-NEXT:    xori a1, a1, 1
 ; CHECK-NEXT:    bnez a2, .LBB20_12
 ; CHECK-NEXT:  .LBB20_6:
 ; CHECK-NEXT:    snez a2, a0
 ; CHECK-NEXT:    beqz a2, .LBB20_13
 ; CHECK-NEXT:    j .LBB20_14
 ; CHECK-NEXT:  .LBB20_7: # %entry
 ; CHECK-NEXT:    li a2, 1
 ; CHECK-NEXT:    mv a3, s1
 ; CHECK-NEXT:    blez s1, .LBB20_2
 ; CHECK-NEXT:  .LBB20_8: # %entry
 ; CHECK-NEXT:    li a3, 1
 ; CHECK-NEXT:    blez a1, .LBB20_3
 ; CHECK-NEXT:  .LBB20_9: # %entry
 ; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:    blez s1, .LBB20_4
 ; CHECK-NEXT:  .LBB20_10: # %entry
 ; CHECK-NEXT:    li s0, 0
 ; CHECK-NEXT:    bnez a3, .LBB20_5
 ; CHECK-NEXT:  .LBB20_11:
 ; CHECK-NEXT:    snez a1, s0
 ; CHECK-NEXT:    beqz a2, .LBB20_6
 ; CHECK-NEXT:  .LBB20_12: # %entry
-; CHECK-NEXT:    sgtz a2, a2
+; CHECK-NEXT:    slti a2, a2, 1
+; CHECK-NEXT:    xori a2, a2, 1
 ; CHECK-NEXT:    bnez a2, .LBB20_14
 ; CHECK-NEXT:  .LBB20_13: # %entry
 ; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:  .LBB20_14: # %entry
 ; CHECK-NEXT:    bnez a1, .LBB20_16
 ; CHECK-NEXT:  # %bb.15: # %entry
 ; CHECK-NEXT:    li s0, 0
 ; CHECK-NEXT:  .LBB20_16: # %entry

 ; CHECK-NEXT:    li s1, 0
 ; CHECK-NEXT:    mv s0, a3
 ; CHECK-NEXT:  .LBB21_6: # %entry
 ; CHECK-NEXT:    beqz a4, .LBB21_10
 ; CHECK-NEXT:  # %bb.7: # %entry
 ; CHECK-NEXT:    slli a3, a0, 63
 ; CHECK-NEXT:    beq a1, a0, .LBB21_11
 ; CHECK-NEXT:  .LBB21_8: # %entry
-; CHECK-NEXT:    slt a1, a0, a1
+; CHECK-NEXT:    slti a1, a1, 0
+; CHECK-NEXT:    xori a1, a1, 1
 ; CHECK-NEXT:    bne s1, a0, .LBB21_12
 ; CHECK-NEXT:  .LBB21_9:
 ; CHECK-NEXT:    sltu a0, a3, s0
 ; CHECK-NEXT:    beqz a0, .LBB21_13
 ; CHECK-NEXT:    j .LBB21_14
 ; CHECK-NEXT:  .LBB21_10: # %entry
 ; CHECK-NEXT:    li a1, 0
 ; CHECK-NEXT:    mv a2, a3
 ; CHECK-NEXT:    slli a3, a0, 63
 ; CHECK-NEXT:    bne a1, a0, .LBB21_8
 ; CHECK-NEXT:  .LBB21_11:
 ; CHECK-NEXT:    sltu a1, a3, a2
 ; CHECK-NEXT:    beq s1, a0, .LBB21_9
 ; CHECK-NEXT:  .LBB21_12: # %entry
-; CHECK-NEXT:    slt a0, a0, s1
+; CHECK-NEXT:    slti a0, s1, 0
+; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    bnez a0, .LBB21_14
 ; CHECK-NEXT:  .LBB21_13: # %entry
 ; CHECK-NEXT:    mv s0, a3
 ; CHECK-NEXT:  .LBB21_14: # %entry
 ; CHECK-NEXT:    bnez a1, .LBB21_16
 ; CHECK-NEXT:  # %bb.15: # %entry
 ; CHECK-NEXT:    mv a2, a3
 ; CHECK-NEXT:  .LBB21_16: # %entry

 ; CHECK-NEXT:    bgtz s1, .LBB23_8
 ; CHECK-NEXT:  .LBB23_2: # %entry
 ; CHECK-NEXT:    bgtz a1, .LBB23_9
 ; CHECK-NEXT:  .LBB23_3: # %entry
 ; CHECK-NEXT:    bgtz s1, .LBB23_10
 ; CHECK-NEXT:  .LBB23_4: # %entry
 ; CHECK-NEXT:    beqz a3, .LBB23_11
 ; CHECK-NEXT:  .LBB23_5: # %entry
-; CHECK-NEXT:    sgtz a1, a3
+; CHECK-NEXT:    slti a1, a3, 1
+; CHECK-NEXT:    xori a1, a1, 1
 ; CHECK-NEXT:    bnez a2, .LBB23_12
 ; CHECK-NEXT:  .LBB23_6:
 ; CHECK-NEXT:    snez a2, a0
 ; CHECK-NEXT:    beqz a2, .LBB23_13
 ; CHECK-NEXT:    j .LBB23_14
 ; CHECK-NEXT:  .LBB23_7: # %entry
 ; CHECK-NEXT:    li a2, 1
 ; CHECK-NEXT:    mv a3, s1
 ; CHECK-NEXT:    blez s1, .LBB23_2
 ; CHECK-NEXT:  .LBB23_8: # %entry
 ; CHECK-NEXT:    li a3, 1
 ; CHECK-NEXT:    blez a1, .LBB23_3
 ; CHECK-NEXT:  .LBB23_9: # %entry
 ; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:    blez s1, .LBB23_4
 ; CHECK-NEXT:  .LBB23_10: # %entry
 ; CHECK-NEXT:    li s0, 0
 ; CHECK-NEXT:    bnez a3, .LBB23_5
 ; CHECK-NEXT:  .LBB23_11:
 ; CHECK-NEXT:    snez a1, s0
 ; CHECK-NEXT:    beqz a2, .LBB23_6
 ; CHECK-NEXT:  .LBB23_12: # %entry
-; CHECK-NEXT:    sgtz a2, a2
+; CHECK-NEXT:    slti a2, a2, 1
+; CHECK-NEXT:    xori a2, a2, 1
 ; CHECK-NEXT:    bnez a2, .LBB23_14
 ; CHECK-NEXT:  .LBB23_13: # %entry
 ; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:  .LBB23_14: # %entry
 ; CHECK-NEXT:    bnez a1, .LBB23_16
 ; CHECK-NEXT:  # %bb.15: # %entry
 ; CHECK-NEXT:    li s0, 0
 ; CHECK-NEXT:  .LBB23_16: # %entry

 ; CHECK-NEXT:    li s1, 0
 ; CHECK-NEXT:    mv s0, a3
 ; CHECK-NEXT:  .LBB24_6: # %entry
 ; CHECK-NEXT:    beqz a4, .LBB24_10
 ; CHECK-NEXT:  # %bb.7: # %entry
 ; CHECK-NEXT:    slli a3, a0, 63
 ; CHECK-NEXT:    beq a1, a0, .LBB24_11
 ; CHECK-NEXT:  .LBB24_8: # %entry
-; CHECK-NEXT:    slt a1, a0, a1
+; CHECK-NEXT:    slti a1, a1, 0
+; CHECK-NEXT:    xori a1, a1, 1
 ; CHECK-NEXT:    bne s1, a0, .LBB24_12
 ; CHECK-NEXT:  .LBB24_9:
 ; CHECK-NEXT:    sltu a0, a3, s0
 ; CHECK-NEXT:    beqz a0, .LBB24_13
 ; CHECK-NEXT:    j .LBB24_14
 ; CHECK-NEXT:  .LBB24_10: # %entry
 ; CHECK-NEXT:    li a1, 0
 ; CHECK-NEXT:    mv a2, a3
 ; CHECK-NEXT:    slli a3, a0, 63
 ; CHECK-NEXT:    bne a1, a0, .LBB24_8
 ; CHECK-NEXT:  .LBB24_11:
 ; CHECK-NEXT:    sltu a1, a3, a2
 ; CHECK-NEXT:    beq s1, a0, .LBB24_9
 ; CHECK-NEXT:  .LBB24_12: # %entry
-; CHECK-NEXT:    slt a0, a0, s1
+; CHECK-NEXT:    slti a0, s1, 0
+; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    bnez a0, .LBB24_14
 ; CHECK-NEXT:  .LBB24_13: # %entry
 ; CHECK-NEXT:    mv s0, a3
 ; CHECK-NEXT:  .LBB24_14: # %entry
 ; CHECK-NEXT:    bnez a1, .LBB24_16
 ; CHECK-NEXT:  # %bb.15: # %entry
 ; CHECK-NEXT:    mv a2, a3
 ; CHECK-NEXT:  .LBB24_16: # %entry

 ; CHECK-NEXT:    bgtz s1, .LBB26_8
 ; CHECK-NEXT:  .LBB26_2: # %entry
 ; CHECK-NEXT:    bgtz a1, .LBB26_9
 ; CHECK-NEXT:  .LBB26_3: # %entry
 ; CHECK-NEXT:    bgtz s1, .LBB26_10
 ; CHECK-NEXT:  .LBB26_4: # %entry
 ; CHECK-NEXT:    beqz a3, .LBB26_11
 ; CHECK-NEXT:  .LBB26_5: # %entry
-; CHECK-NEXT:    sgtz a1, a3
+; CHECK-NEXT:    slti a1, a3, 1
+; CHECK-NEXT:    xori a1, a1, 1
 ; CHECK-NEXT:    bnez a2, .LBB26_12
 ; CHECK-NEXT:  .LBB26_6:
 ; CHECK-NEXT:    snez a2, a0
 ; CHECK-NEXT:    beqz a2, .LBB26_13
 ; CHECK-NEXT:    j .LBB26_14
 ; CHECK-NEXT:  .LBB26_7: # %entry
 ; CHECK-NEXT:    li a2, 1
 ; CHECK-NEXT:    mv a3, s1
 ; CHECK-NEXT:    blez s1, .LBB26_2
 ; CHECK-NEXT:  .LBB26_8: # %entry
 ; CHECK-NEXT:    li a3, 1
 ; CHECK-NEXT:    blez a1, .LBB26_3
 ; CHECK-NEXT:  .LBB26_9: # %entry
 ; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:    blez s1, .LBB26_4
 ; CHECK-NEXT:  .LBB26_10: # %entry
 ; CHECK-NEXT:    li s0, 0
 ; CHECK-NEXT:    bnez a3, .LBB26_5
 ; CHECK-NEXT:  .LBB26_11:
 ; CHECK-NEXT:    snez a1, s0
 ; CHECK-NEXT:    beqz a2, .LBB26_6
 ; CHECK-NEXT:  .LBB26_12: # %entry
-; CHECK-NEXT:    sgtz a2, a2
+; CHECK-NEXT:    slti a2, a2, 1
+; CHECK-NEXT:    xori a2, a2, 1
 ; CHECK-NEXT:    bnez a2, .LBB26_14
 ; CHECK-NEXT:  .LBB26_13: # %entry
 ; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:  .LBB26_14: # %entry
 ; CHECK-NEXT:    bnez a1, .LBB26_16
 ; CHECK-NEXT:  # %bb.15: # %entry
 ; CHECK-NEXT:    li s0, 0
 ; CHECK-NEXT:  .LBB26_16: # %entry

llvm/test/CodeGen/RISCV/i32-icmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 
 ; TODO: check the generated instructions for the equivalent of seqz, snez,
 ; sltz, sgtz map to something simple
 
 define i32 @icmp_eq(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: icmp_eq:

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a1, a0
 ; RV32I-NEXT:    ret
   %1 = icmp ugt i32 %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
+define i32 @icmp_ugt_constant_2047(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ugt_constant_2047:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    li a1, 2047
+; RV32I-NEXT:    sltu a0, a1, a0
+; RV32I-NEXT:    ret
+  %1 = icmp ugt i32 %a, 2047
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @icmp_ugt_constant_2046(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ugt_constant_2046:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    sltiu a0, a0, 2047
+; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    ret
+  %1 = icmp ugt i32 %a, 2046
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @icmp_ugt_constant_neg_2049(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ugt_constant_neg_2049:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    sltiu a0, a0, -2048
+; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    ret
+  %1 = icmp ugt i32 %a, -2049
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
 define i32 @icmp_uge(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: icmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a0, a1
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
   %1 = icmp uge i32 %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @icmp_ult(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: icmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a0, a1
 ; RV32I-NEXT:    ret
   %1 = icmp ult i32 %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
+define i32 @icmp_ult_constant_2047(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ult_constant_2047:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    sltiu a0, a0, 2047
+; RV32I-NEXT:    ret
+  %1 = icmp ult i32 %a, 2047
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+define i32 @icmp_ult_constant_2048(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ult_constant_2048:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srli a0, a0, 11
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    ret
+  %1 = icmp ult i32 %a, 2048
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @icmp_ult_constant_neg_2048(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ult_constant_neg_2048:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    sltiu a0, a0, -2048
+; RV32I-NEXT:    ret
+  %1 = icmp ult i32 %a, -2048
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
 define i32 @icmp_ule(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: icmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a1, a0
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
   %1 = icmp ule i32 %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @icmp_sgt(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: icmp_sgt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slt a0, a1, a0
 ; RV32I-NEXT:    ret
   %1 = icmp sgt i32 %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
+define i32 @icmp_sgt_constant(i32 %a) nounwind {
+; RV32I-LABEL: icmp_sgt_constant:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slti a0, a0, 6
+; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    ret
+  %1 = icmp sgt i32 %a, 5
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @icmp_sgt_constant_2046(i32 %a) nounwind {
+; RV32I-LABEL: icmp_sgt_constant_2046:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slti a0, a0, 2047
+; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    ret
+  %1 = icmp sgt i32 %a, 2046
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @icmp_sgt_constant_2047(i32 %a) nounwind {
+; RV32I-LABEL: icmp_sgt_constant_2047:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    li a1, 2047
+; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    ret
+  %1 = icmp sgt i32 %a, 2047
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @icmp_sgt_constant_neg_2049(i32 %a) nounwind {
+; RV32I-LABEL: icmp_sgt_constant_neg_2049:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slti a0, a0, -2048
+; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    ret
+  %1 = icmp sgt i32 %a, -2049
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @icmp_sgt_constant_neg_2050(i32 %a) nounwind {
+; RV32I-LABEL: icmp_sgt_constant_neg_2050:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 1048575
+; RV32I-NEXT:    addi a1, a1, 2046
+; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    ret
+  %1 = icmp sgt i32 %a, -2050
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
 define i32 @icmp_sge(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: icmp_sge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slt a0, a0, a1
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
   %1 = icmp sge i32 %a, %b
   %2 = zext i1 %1 to i32

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slt a0, a1, a0
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
   %1 = icmp sle i32 %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
-
-; TODO: check variants with an immediate?

llvm/test/CodeGen/RISCV/select-constant-xor.ll

; RV64-NEXT:    ret
   %c = icmp sgt i64 %a, -1
   %s = select i1 %c, i64 2147483647, i64 -2147483648
   ret i64 %s
 }
 
 define i32 @selecti64i32(i64 %a) {
 ; RV32-LABEL: selecti64i32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    li a0, -1
-; RV32-NEXT:    slt a0, a0, a1
+; RV32-NEXT:    slti a0, a1, 0
+; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    lui a1, 524288
 ; RV32-NEXT:    sub a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: selecti64i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    srai a0, a0, 63
 ; RV64-NEXT:    lui a1, 524288

llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll

 ; RV32:       # %bb.0:
 ; RV32-NEXT:    not a0, a0
 ; RV32-NEXT:    srli a0, a0, 22
 ; RV32-NEXT:    andi a0, a0, 512
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: pos_sel_special_constant:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    li a1, -1
-; RV64-NEXT:    slt a0, a1, a0
+; RV64-NEXT:    slti a0, a0, 0
+; RV64-NEXT:    xori a0, a0, 1
 ; RV64-NEXT:    slli a0, a0, 9
 ; RV64-NEXT:    ret
   %tmp.1 = icmp sgt i32 %a, -1
   %retval = select i1 %tmp.1, i32 512, i32 0
   ret i32 %retval
 }
 
 ; Compare if positive and select variable or zero.

llvm/test/CodeGen/RISCV/ssub_sat.ll

 declare i16 @llvm.ssub.sat.i16(i16, i16)
 declare i32 @llvm.ssub.sat.i32(i32, i32)
 declare i64 @llvm.ssub.sat.i64(i64, i64)
 
 define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
 ; RV32I-LABEL: func:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a2, a0
-; RV32I-NEXT:    sgtz a3, a1
 ; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    slt a1, a0, a2
-; RV32I-NEXT:    beq a3, a1, .LBB0_2
+; RV32I-NEXT:    slt a2, a0, a2
+; RV32I-NEXT:    slti a1, a1, 1
+; RV32I-NEXT:    xori a1, a1, 1
+; RV32I-NEXT:    beq a1, a2, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srai a0, a0, 31
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:  .LBB0_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func:

 ; RV64I-NEXT:    blt a1, a0, .LBB0_2
 ; RV64I-NEXT:  .LBB0_4:
 ; RV64I-NEXT:    lui a0, 524288
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbbNOZbt-LABEL: func:
 ; RV32IZbbNOZbt:       # %bb.0:
 ; RV32IZbbNOZbt-NEXT:    mv a2, a0
-; RV32IZbbNOZbt-NEXT:    sgtz a3, a1
 ; RV32IZbbNOZbt-NEXT:    sub a0, a0, a1
-; RV32IZbbNOZbt-NEXT:    slt a1, a0, a2
-; RV32IZbbNOZbt-NEXT:    beq a3, a1, .LBB0_2
+; RV32IZbbNOZbt-NEXT:    slt a2, a0, a2
+; RV32IZbbNOZbt-NEXT:    slti a1, a1, 1
+; RV32IZbbNOZbt-NEXT:    xori a1, a1, 1
+; RV32IZbbNOZbt-NEXT:    beq a1, a2, .LBB0_2
 ; RV32IZbbNOZbt-NEXT:  # %bb.1:
 ; RV32IZbbNOZbt-NEXT:    srai a0, a0, 31
 ; RV32IZbbNOZbt-NEXT:    lui a1, 524288
 ; RV32IZbbNOZbt-NEXT:    xor a0, a0, a1
 ; RV32IZbbNOZbt-NEXT:  .LBB0_2:
 ; RV32IZbbNOZbt-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func:
 ; RV64IZbb:       # %bb.0:
 ; RV64IZbb-NEXT:    sub a0, a0, a1
 ; RV64IZbb-NEXT:    lui a1, 524288
 ; RV64IZbb-NEXT:    addiw a2, a1, -1
 ; RV64IZbb-NEXT:    min a0, a0, a2
 ; RV64IZbb-NEXT:    max a0, a0, a1
 ; RV64IZbb-NEXT:    ret
 ;
 ; RV32IZbbZbt-LABEL: func:
 ; RV32IZbbZbt:       # %bb.0:
-; RV32IZbbZbt-NEXT:    sgtz a2, a1
-; RV32IZbbZbt-NEXT:    sub a1, a0, a1
-; RV32IZbbZbt-NEXT:    slt a0, a1, a0
-; RV32IZbbZbt-NEXT:    xor a0, a2, a0
-; RV32IZbbZbt-NEXT:    srai a2, a1, 31
+; RV32IZbbZbt-NEXT:    sub a2, a0, a1
+; RV32IZbbZbt-NEXT:    slt a0, a2, a0
+; RV32IZbbZbt-NEXT:    slti a1, a1, 1
+; RV32IZbbZbt-NEXT:    xori a1, a1, 1
+; RV32IZbbZbt-NEXT:    xor a0, a1, a0
+; RV32IZbbZbt-NEXT:    srai a1, a2, 31
 ; RV32IZbbZbt-NEXT:    lui a3, 524288
-; RV32IZbbZbt-NEXT:    xor a2, a2, a3
-; RV32IZbbZbt-NEXT:    cmov a0, a0, a2, a1
+; RV32IZbbZbt-NEXT:    xor a1, a1, a3
+; RV32IZbbZbt-NEXT:    cmov a0, a0, a1, a2
 ; RV32IZbbZbt-NEXT:    ret
   %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y);
   ret i32 %tmp;
 }
 
 define i64 @func2(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: func2:
 ; RV32I:       # %bb.0:

 ; RV32I-NEXT:    srai a0, a1, 31
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    xor a1, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a2, a0
-; RV64I-NEXT:    sgtz a3, a1
 ; RV64I-NEXT:    sub a0, a0, a1
-; RV64I-NEXT:    slt a1, a0, a2
-; RV64I-NEXT:    beq a3, a1, .LBB1_2
+; RV64I-NEXT:    slt a2, a0, a2
+; RV64I-NEXT:    slti a1, a1, 1
+; RV64I-NEXT:    xori a1, a1, 1
+; RV64I-NEXT:    beq a1, a2, .LBB1_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    srai a0, a0, 63
 ; RV64I-NEXT:    li a1, -1
 ; RV64I-NEXT:    slli a1, a1, 63
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:  .LBB1_2:
 ; RV64I-NEXT:    ret
 ;

 ; RV32IZbbNOZbt-NEXT:    srai a0, a1, 31
 ; RV32IZbbNOZbt-NEXT:    lui a1, 524288
 ; RV32IZbbNOZbt-NEXT:    xor a1, a0, a1
 ; RV32IZbbNOZbt-NEXT:    ret
 ;
 ; RV64IZbbNOZbt-LABEL: func2:
 ; RV64IZbbNOZbt:       # %bb.0:
 ; RV64IZbbNOZbt-NEXT:    mv a2, a0
-; RV64IZbbNOZbt-NEXT:    sgtz a3, a1
 ; RV64IZbbNOZbt-NEXT:    sub a0, a0, a1
-; RV64IZbbNOZbt-NEXT:    slt a1, a0, a2
-; RV64IZbbNOZbt-NEXT:    beq a3, a1, .LBB1_2
+; RV64IZbbNOZbt-NEXT:    slt a2, a0, a2
+; RV64IZbbNOZbt-NEXT:    slti a1, a1, 1
+; RV64IZbbNOZbt-NEXT:    xori a1, a1, 1
+; RV64IZbbNOZbt-NEXT:    beq a1, a2, .LBB1_2
 ; RV64IZbbNOZbt-NEXT:  # %bb.1:
 ; RV64IZbbNOZbt-NEXT:    srai a0, a0, 63
 ; RV64IZbbNOZbt-NEXT:    li a1, -1
 ; RV64IZbbNOZbt-NEXT:    slli a1, a1, 63
 ; RV64IZbbNOZbt-NEXT:    xor a0, a0, a1
 ; RV64IZbbNOZbt-NEXT:  .LBB1_2:
 ; RV64IZbbNOZbt-NEXT:    ret
 ;

 ; RV32IZbbZbt-NEXT:    slti a3, a1, 0
 ; RV32IZbbZbt-NEXT:    cmov a1, a3, a6, a4
 ; RV32IZbbZbt-NEXT:    sub a0, a0, a2
 ; RV32IZbbZbt-NEXT:    cmov a0, a3, a5, a0
 ; RV32IZbbZbt-NEXT:    ret
 ;
 ; RV64IZbbZbt-LABEL: func2:
 ; RV64IZbbZbt:       # %bb.0:
-; RV64IZbbZbt-NEXT:    sgtz a2, a1
-; RV64IZbbZbt-NEXT:    sub a1, a0, a1
-; RV64IZbbZbt-NEXT:    slt a0, a1, a0
-; RV64IZbbZbt-NEXT:    xor a0, a2, a0
-; RV64IZbbZbt-NEXT:    srai a2, a1, 63
+; RV64IZbbZbt-NEXT:    sub a2, a0, a1
+; RV64IZbbZbt-NEXT:    slt a0, a2, a0
+; RV64IZbbZbt-NEXT:    slti a1, a1, 1
+; RV64IZbbZbt-NEXT:    xori a1, a1, 1
+; RV64IZbbZbt-NEXT:    xor a0, a1, a0
+; RV64IZbbZbt-NEXT:    srai a1, a2, 63
 ; RV64IZbbZbt-NEXT:    li a3, -1
 ; RV64IZbbZbt-NEXT:    slli a3, a3, 63
-; RV64IZbbZbt-NEXT:    xor a2, a2, a3
-; RV64IZbbZbt-NEXT:    cmov a0, a0, a2, a1
+; RV64IZbbZbt-NEXT:    xor a1, a1, a3
+; RV64IZbbZbt-NEXT:    cmov a0, a0, a1, a2
 ; RV64IZbbZbt-NEXT:    ret
   %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y);
   ret i64 %tmp;
 }
 
 define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
 ; RV32I-LABEL: func16:
 ; RV32I:       # %bb.0:

llvm/test/CodeGen/RISCV/ssub_sat_plus.ll

 declare i16 @llvm.ssub.sat.i16(i16, i16)
 declare i32 @llvm.ssub.sat.i32(i32, i32)
 declare i64 @llvm.ssub.sat.i64(i64, i64)
 
 define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
 ; RV32I-LABEL: func32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a3, a0
-; RV32I-NEXT:    mul a0, a1, a2
-; RV32I-NEXT:    sgtz a1, a0
-; RV32I-NEXT:    sub a0, a3, a0
+; RV32I-NEXT:    mul a1, a1, a2
+; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    slt a2, a0, a3
+; RV32I-NEXT:    slti a1, a1, 1
+; RV32I-NEXT:    xori a1, a1, 1
 ; RV32I-NEXT:    beq a1, a2, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srai a0, a0, 31
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:  .LBB0_2:
 ; RV32I-NEXT:    ret
 ;

 ; RV64I-NEXT:    blt a1, a0, .LBB0_2
 ; RV64I-NEXT:  .LBB0_4:
 ; RV64I-NEXT:    lui a0, 524288
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbbNOZbt-LABEL: func32:
 ; RV32IZbbNOZbt:       # %bb.0:
 ; RV32IZbbNOZbt-NEXT:    mv a3, a0
-; RV32IZbbNOZbt-NEXT:    mul a0, a1, a2
-; RV32IZbbNOZbt-NEXT:    sgtz a1, a0
-; RV32IZbbNOZbt-NEXT:    sub a0, a3, a0
+; RV32IZbbNOZbt-NEXT:    mul a1, a1, a2
+; RV32IZbbNOZbt-NEXT:    sub a0, a0, a1
 ; RV32IZbbNOZbt-NEXT:    slt a2, a0, a3
+; RV32IZbbNOZbt-NEXT:    slti a1, a1, 1
+; RV32IZbbNOZbt-NEXT:    xori a1, a1, 1
 ; RV32IZbbNOZbt-NEXT:    beq a1, a2, .LBB0_2
 ; RV32IZbbNOZbt-NEXT:  # %bb.1:
 ; RV32IZbbNOZbt-NEXT:    srai a0, a0, 31
 ; RV32IZbbNOZbt-NEXT:    lui a1, 524288
 ; RV32IZbbNOZbt-NEXT:    xor a0, a0, a1
 ; RV32IZbbNOZbt-NEXT:  .LBB0_2:
 ; RV32IZbbNOZbt-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func32:
 ; RV64IZbb:       # %bb.0:
 ; RV64IZbb-NEXT:    sext.w a0, a0
 ; RV64IZbb-NEXT:    mulw a1, a1, a2
 ; RV64IZbb-NEXT:    sub a0, a0, a1
 ; RV64IZbb-NEXT:    lui a1, 524288
 ; RV64IZbb-NEXT:    addiw a2, a1, -1
 ; RV64IZbb-NEXT:    min a0, a0, a2
 ; RV64IZbb-NEXT:    max a0, a0, a1
 ; RV64IZbb-NEXT:    ret
 ;
 ; RV32IZbbZbt-LABEL: func32:
 ; RV32IZbbZbt:       # %bb.0:
 ; RV32IZbbZbt-NEXT:    mul a1, a1, a2
-; RV32IZbbZbt-NEXT:    sgtz a2, a1
-; RV32IZbbZbt-NEXT:    sub a1, a0, a1
-; RV32IZbbZbt-NEXT:    slt a0, a1, a0
-; RV32IZbbZbt-NEXT:    xor a0, a2, a0
-; RV32IZbbZbt-NEXT:    srai a2, a1, 31
+; RV32IZbbZbt-NEXT:    sub a2, a0, a1
+; RV32IZbbZbt-NEXT:    slt a0, a2, a0
+; RV32IZbbZbt-NEXT:    slti a1, a1, 1
+; RV32IZbbZbt-NEXT:    xori a1, a1, 1
+; RV32IZbbZbt-NEXT:    xor a0, a1, a0
+; RV32IZbbZbt-NEXT:    srai a1, a2, 31
 ; RV32IZbbZbt-NEXT:    lui a3, 524288
-; RV32IZbbZbt-NEXT:    xor a2, a2, a3
-; RV32IZbbZbt-NEXT:    cmov a0, a0, a2, a1
+; RV32IZbbZbt-NEXT:    xor a1, a1, a3
+; RV32IZbbZbt-NEXT:    cmov a0, a0, a1, a2
 ; RV32IZbbZbt-NEXT:    ret
   %a = mul i32 %y, %z
   %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a)
   ret i32 %tmp
 }
 
 define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
 ; RV32I-LABEL: func64:

 ; RV32I-NEXT:    srai a0, a1, 31
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    xor a1, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    sgtz a3, a2
 ; RV64I-NEXT:    sub a0, a0, a2
 ; RV64I-NEXT:    slt a1, a0, a1
-; RV64I-NEXT:    beq a3, a1, .LBB1_2
+; RV64I-NEXT:    slti a2, a2, 1
+; RV64I-NEXT:    xori a2, a2, 1
+; RV64I-NEXT:    beq a2, a1, .LBB1_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    srai a0, a0, 63
 ; RV64I-NEXT:    li a1, -1
 ; RV64I-NEXT:    slli a1, a1, 63
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:  .LBB1_2:
 ; RV64I-NEXT:    ret
 ;

 ; RV32IZbbNOZbt-NEXT:    srai a0, a1, 31
 ; RV32IZbbNOZbt-NEXT:    lui a1, 524288
 ; RV32IZbbNOZbt-NEXT:    xor a1, a0, a1
 ; RV32IZbbNOZbt-NEXT:    ret
 ;
 ; RV64IZbbNOZbt-LABEL: func64:
 ; RV64IZbbNOZbt:       # %bb.0:
 ; RV64IZbbNOZbt-NEXT:    mv a1, a0
-; RV64IZbbNOZbt-NEXT:    sgtz a3, a2
 ; RV64IZbbNOZbt-NEXT:    sub a0, a0, a2
 ; RV64IZbbNOZbt-NEXT:    slt a1, a0, a1
-; RV64IZbbNOZbt-NEXT:    beq a3, a1, .LBB1_2
+; RV64IZbbNOZbt-NEXT:    slti a2, a2, 1
+; RV64IZbbNOZbt-NEXT:    xori a2, a2, 1
+; RV64IZbbNOZbt-NEXT:    beq a2, a1, .LBB1_2
 ; RV64IZbbNOZbt-NEXT:  # %bb.1:
 ; RV64IZbbNOZbt-NEXT:    srai a0, a0, 63
 ; RV64IZbbNOZbt-NEXT:    li a1, -1
 ; RV64IZbbNOZbt-NEXT:    slli a1, a1, 63
 ; RV64IZbbNOZbt-NEXT:    xor a0, a0, a1
 ; RV64IZbbNOZbt-NEXT:  .LBB1_2:
 ; RV64IZbbNOZbt-NEXT:    ret
 ;

 ; RV32IZbbZbt-NEXT:    slti a5, a1, 0
 ; RV32IZbbZbt-NEXT:    cmov a1, a5, a6, a2
 ; RV32IZbbZbt-NEXT:    sub a0, a0, a4
 ; RV32IZbbZbt-NEXT:    cmov a0, a5, a3, a0
 ; RV32IZbbZbt-NEXT:    ret
 ;
 ; RV64IZbbZbt-LABEL: func64:
 ; RV64IZbbZbt:       # %bb.0:
-; RV64IZbbZbt-NEXT:    sgtz a1, a2
-; RV64IZbbZbt-NEXT:    sub a2, a0, a2
-; RV64IZbbZbt-NEXT:    slt a0, a2, a0
-; RV64IZbbZbt-NEXT:    xor a0, a1, a0
-; RV64IZbbZbt-NEXT:    srai a1, a2, 63
+; RV64IZbbZbt-NEXT:    sub a1, a0, a2
+; RV64IZbbZbt-NEXT:    slt a0, a1, a0
+; RV64IZbbZbt-NEXT:    slti a2, a2, 1
+; RV64IZbbZbt-NEXT:    xori a2, a2, 1
+; RV64IZbbZbt-NEXT:    xor a0, a2, a0
+; RV64IZbbZbt-NEXT:    srai a2, a1, 63
 ; RV64IZbbZbt-NEXT:    li a3, -1
 ; RV64IZbbZbt-NEXT:    slli a3, a3, 63
-; RV64IZbbZbt-NEXT:    xor a1, a1, a3
-; RV64IZbbZbt-NEXT:    cmov a0, a0, a1, a2
+; RV64IZbbZbt-NEXT:    xor a2, a2, a3
+; RV64IZbbZbt-NEXT:    cmov a0, a0, a2, a1
 ; RV64IZbbZbt-NEXT:    ret
   %a = mul i64 %y, %z
   %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)
   ret i64 %tmp
 }
 
 define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
 ; RV32I-LABEL: func16:

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

 
 define i1 @test_urem_odd_setne(i4 %X) nounwind {
 ; RV32-LABEL: test_urem_odd_setne:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    slli a1, a0, 1
 ; RV32-NEXT:    add a0, a1, a0
 ; RV32-NEXT:    neg a0, a0
 ; RV32-NEXT:    andi a0, a0, 15
-; RV32-NEXT:    li a1, 3
-; RV32-NEXT:    sltu a0, a1, a0
+; RV32-NEXT:    sltiu a0, a0, 4
+; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_urem_odd_setne:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    slliw a1, a0, 1
 ; RV64-NEXT:    addw a0, a1, a0
 ; RV64-NEXT:    negw a0, a0
 ; RV64-NEXT:    andi a0, a0, 15
-; RV64-NEXT:    li a1, 3
-; RV64-NEXT:    sltu a0, a1, a0
+; RV64-NEXT:    sltiu a0, a0, 4
+; RV64-NEXT:    xori a0, a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32M-LABEL: test_urem_odd_setne:
 ; RV32M:       # %bb.0:
 ; RV32M-NEXT:    slli a1, a0, 1
 ; RV32M-NEXT:    add a0, a1, a0
 ; RV32M-NEXT:    neg a0, a0
 ; RV32M-NEXT:    andi a0, a0, 15
-; RV32M-NEXT:    li a1, 3
-; RV32M-NEXT:    sltu a0, a1, a0
+; RV32M-NEXT:    sltiu a0, a0, 4
+; RV32M-NEXT:    xori a0, a0, 1
 ; RV32M-NEXT:    ret
 ;
 ; RV64M-LABEL: test_urem_odd_setne:
 ; RV64M:       # %bb.0:
 ; RV64M-NEXT:    slliw a1, a0, 1
 ; RV64M-NEXT:    addw a0, a1, a0
 ; RV64M-NEXT:    negw a0, a0
 ; RV64M-NEXT:    andi a0, a0, 15
-; RV64M-NEXT:    li a1, 3
-; RV64M-NEXT:    sltu a0, a1, a0
+; RV64M-NEXT:    sltiu a0, a0, 4
+; RV64M-NEXT:    xori a0, a0, 1
 ; RV64M-NEXT:    ret
 ;
 ; RV32MV-LABEL: test_urem_odd_setne:
 ; RV32MV:       # %bb.0:
 ; RV32MV-NEXT:    slli a1, a0, 1
 ; RV32MV-NEXT:    add a0, a1, a0
 ; RV32MV-NEXT:    neg a0, a0
 ; RV32MV-NEXT:    andi a0, a0, 15
-; RV32MV-NEXT:    li a1, 3
-; RV32MV-NEXT:    sltu a0, a1, a0
+; RV32MV-NEXT:    sltiu a0, a0, 4
+; RV32MV-NEXT:    xori a0, a0, 1
 ; RV32MV-NEXT:    ret
 ;
 ; RV64MV-LABEL: test_urem_odd_setne:
 ; RV64MV:       # %bb.0:
 ; RV64MV-NEXT:    slliw a1, a0, 1
 ; RV64MV-NEXT:    addw a0, a1, a0
 ; RV64MV-NEXT:    negw a0, a0
 ; RV64MV-NEXT:    andi a0, a0, 15
-; RV64MV-NEXT:    li a1, 3
-; RV64MV-NEXT:    sltu a0, a1, a0
+; RV64MV-NEXT:    sltiu a0, a0, 4
+; RV64MV-NEXT:    xori a0, a0, 1
 ; RV64MV-NEXT:    ret
   %urem = urem i4 %X, 5
   %cmp = icmp ne i4 %urem, 0
   ret i1 %cmp
 }
 
 define i1 @test_urem_negative_odd(i9 %X) nounwind {
 ; RV32-LABEL: test_urem_negative_odd:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    li a1, 307
 ; RV32-NEXT:    call __mulsi3@plt
 ; RV32-NEXT:    andi a0, a0, 511
-; RV32-NEXT:    li a1, 1
-; RV32-NEXT:    sltu a0, a1, a0
+; RV32-NEXT:    sltiu a0, a0, 2
+; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_urem_negative_odd:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    li a1, 307
 ; RV64-NEXT:    call __muldi3@plt
 ; RV64-NEXT:    andi a0, a0, 511
-; RV64-NEXT:    li a1, 1
-; RV64-NEXT:    sltu a0, a1, a0
+; RV64-NEXT:    sltiu a0, a0, 2
+; RV64-NEXT:    xori a0, a0, 1
 ; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
 ;
 ; RV32M-LABEL: test_urem_negative_odd:
 ; RV32M:       # %bb.0:
 ; RV32M-NEXT:    li a1, 307
 ; RV32M-NEXT:    mul a0, a0, a1
 ; RV32M-NEXT:    andi a0, a0, 511
-; RV32M-NEXT:    li a1, 1
-; RV32M-NEXT:    sltu a0, a1, a0
+; RV32M-NEXT:    sltiu a0, a0, 2
+; RV32M-NEXT:    xori a0, a0, 1
 ; RV32M-NEXT:    ret
 ;
 ; RV64M-LABEL: test_urem_negative_odd:
 ; RV64M:       # %bb.0:
 ; RV64M-NEXT:    li a1, 307
 ; RV64M-NEXT:    mulw a0, a0, a1
 ; RV64M-NEXT:    andi a0, a0, 511
-; RV64M-NEXT:    li a1, 1
-; RV64M-NEXT:    sltu a0, a1, a0
+; RV64M-NEXT:    sltiu a0, a0, 2
+; RV64M-NEXT:    xori a0, a0, 1
 ; RV64M-NEXT:    ret
 ;
 ; RV32MV-LABEL: test_urem_negative_odd:
 ; RV32MV:       # %bb.0:
 ; RV32MV-NEXT:    li a1, 307
 ; RV32MV-NEXT:    mul a0, a0, a1
 ; RV32MV-NEXT:    andi a0, a0, 511
-; RV32MV-NEXT:    li a1, 1
-; RV32MV-NEXT:    sltu a0, a1, a0
+; RV32MV-NEXT:    sltiu a0, a0, 2
+; RV32MV-NEXT:    xori a0, a0, 1
 ; RV32MV-NEXT:    ret
 ;
 ; RV64MV-LABEL: test_urem_negative_odd:
 ; RV64MV:       # %bb.0:
 ; RV64MV-NEXT:    li a1, 307
 ; RV64MV-NEXT:    mulw a0, a0, a1
 ; RV64MV-NEXT:    andi a0, a0, 511
-; RV64MV-NEXT:    li a1, 1
-; RV64MV-NEXT:    sltu a0, a1, a0
+; RV64MV-NEXT:    sltiu a0, a0, 2
+; RV64MV-NEXT:    xori a0, a0, 1
 ; RV64MV-NEXT:    ret
   %urem = urem i9 %X, -5
   %cmp = icmp ne i9 %urem, 0
   ret i1 %cmp
 }
 
 define void @test_urem_vec(<3 x i11>* %X) nounwind {
 ; RV32-LABEL: test_urem_vec:

 ; RV32-NEXT:    andi a0, a1, 2047
 ; RV32-NEXT:    li a1, 683
 ; RV32-NEXT:    call __mulsi3@plt
 ; RV32-NEXT:    slli a1, a0, 10
 ; RV32-NEXT:    slli a0, a0, 21
 ; RV32-NEXT:    srli a0, a0, 22
 ; RV32-NEXT:    or a0, a0, a1
 ; RV32-NEXT:    andi a0, a0, 2047
-; RV32-NEXT:    li a1, 341
-; RV32-NEXT:    sltu s3, a1, a0
+; RV32-NEXT:    sltiu a0, a0, 342
+; RV32-NEXT:    xori s3, a0, 1
 ; RV32-NEXT:    li a1, 819
 ; RV32-NEXT:    mv a0, s1
 ; RV32-NEXT:    call __mulsi3@plt
 ; RV32-NEXT:    addi a0, a0, -1638
 ; RV32-NEXT:    andi a0, a0, 2047
-; RV32-NEXT:    li a1, 1
-; RV32-NEXT:    sltu s1, a1, a0
+; RV32-NEXT:    sltiu a0, a0, 2
+; RV32-NEXT:    xori s1, a0, 1
 ; RV32-NEXT:    li a1, 1463
 ; RV32-NEXT:    mv a0, s2
 ; RV32-NEXT:    call __mulsi3@plt
 ; RV32-NEXT:    addi a0, a0, -1463
 ; RV32-NEXT:    andi a0, a0, 2047
-; RV32-NEXT:    li a1, 292
-; RV32-NEXT:    sltu a0, a1, a0
+; RV32-NEXT:    sltiu a0, a0, 293
+; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    neg a1, s3
 ; RV32-NEXT:    neg a0, a0
 ; RV32-NEXT:    neg a2, s1
 ; RV32-NEXT:    srli a2, a2, 10
 ; RV32-NEXT:    andi a2, a2, 1
 ; RV32-NEXT:    sb a2, 4(s0)
 ; RV32-NEXT:    andi a1, a1, 2047
 ; RV32-NEXT:    andi a0, a0, 2047

 ; RV64-NEXT:    andi a0, a0, 2047
 ; RV64-NEXT:    li a1, 683
 ; RV64-NEXT:    call __muldi3@plt
 ; RV64-NEXT:    slli a1, a0, 10
 ; RV64-NEXT:    slli a0, a0, 53
 ; RV64-NEXT:    srli a0, a0, 54
 ; RV64-NEXT:    or a0, a0, a1
 ; RV64-NEXT:    andi a0, a0, 2047
-; RV64-NEXT:    li a1, 341
-; RV64-NEXT:    sltu s3, a1, a0
+; RV64-NEXT:    sltiu a0, a0, 342
+; RV64-NEXT:    xori s3, a0, 1
 ; RV64-NEXT:    li a1, 819
 ; RV64-NEXT:    mv a0, s2
 ; RV64-NEXT:    call __muldi3@plt
 ; RV64-NEXT:    addiw a0, a0, -1638
 ; RV64-NEXT:    andi a0, a0, 2047
-; RV64-NEXT:    li a1, 1
-; RV64-NEXT:    sltu s2, a1, a0
+; RV64-NEXT:    sltiu a0, a0, 2
+; RV64-NEXT:    xori s2, a0, 1
 ; RV64-NEXT:    li a1, 1463
 ; RV64-NEXT:    mv a0, s1
 ; RV64-NEXT:    call __muldi3@plt
 ; RV64-NEXT:    addiw a0, a0, -1463
 ; RV64-NEXT:    andi a0, a0, 2047
-; RV64-NEXT:    li a1, 292
-; RV64-NEXT:    sltu a0, a1, a0
+; RV64-NEXT:    sltiu a0, a0, 293
+; RV64-NEXT:    xori a0, a0, 1
 ; RV64-NEXT:    negw a1, s3
 ; RV64-NEXT:    negw a0, a0
 ; RV64-NEXT:    andi a1, a1, 2047
 ; RV64-NEXT:    andi a0, a0, 2047
 ; RV64-NEXT:    slli a0, a0, 11
 ; RV64-NEXT:    or a0, a1, a0
 ; RV64-NEXT:    slli a1, s2, 22
 ; RV64-NEXT:    sub a0, a0, a1

 ; RV32M-NEXT:    andi a2, a2, 2047
 ; RV32M-NEXT:    li a4, 683
 ; RV32M-NEXT:    mul a2, a2, a4
 ; RV32M-NEXT:    slli a4, a2, 10
 ; RV32M-NEXT:    slli a2, a2, 21
 ; RV32M-NEXT:    srli a2, a2, 22
 ; RV32M-NEXT:    or a2, a2, a4
 ; RV32M-NEXT:    andi a2, a2, 2047
-; RV32M-NEXT:    li a4, 341
-; RV32M-NEXT:    sltu a2, a4, a2
+; RV32M-NEXT:    sltiu a2, a2, 342
+; RV32M-NEXT:    xori a2, a2, 1
 ; RV32M-NEXT:    li a4, 819
 ; RV32M-NEXT:    mul a1, a1, a4
 ; RV32M-NEXT:    addi a1, a1, -1638
 ; RV32M-NEXT:    andi a1, a1, 2047
-; RV32M-NEXT:    li a4, 1
-; RV32M-NEXT:    sltu a1, a4, a1
+; RV32M-NEXT:    sltiu a1, a1, 2
+; RV32M-NEXT:    xori a1, a1, 1
 ; RV32M-NEXT:    li a4, 1463
 ; RV32M-NEXT:    mul a3, a3, a4
 ; RV32M-NEXT:    addi a3, a3, -1463
 ; RV32M-NEXT:    andi a3, a3, 2047
-; RV32M-NEXT:    li a4, 292
-; RV32M-NEXT:    sltu a3, a4, a3
+; RV32M-NEXT:    sltiu a3, a3, 293
+; RV32M-NEXT:    xori a3, a3, 1
 ; RV32M-NEXT:    neg a2, a2
 ; RV32M-NEXT:    neg a3, a3
 ; RV32M-NEXT:    neg a4, a1
 ; RV32M-NEXT:    srli a4, a4, 10
 ; RV32M-NEXT:    andi a4, a4, 1
 ; RV32M-NEXT:    sb a4, 4(a0)
 ; RV32M-NEXT:    andi a2, a2, 2047
 ; RV32M-NEXT:    andi a3, a3, 2047

 ; RV64M-NEXT:    andi a1, a1, 2047
 ; RV64M-NEXT:    li a4, 683
 ; RV64M-NEXT:    mul a1, a1, a4
 ; RV64M-NEXT:    slli a4, a1, 10
 ; RV64M-NEXT:    slli a1, a1, 53
 ; RV64M-NEXT:    srli a1, a1, 54
 ; RV64M-NEXT:    or a1, a1, a4
 ; RV64M-NEXT:    andi a1, a1, 2047
-; RV64M-NEXT:    li a4, 341
-; RV64M-NEXT:    sltu a1, a4, a1
+; RV64M-NEXT:    sltiu a1, a1, 342
+; RV64M-NEXT:    xori a1, a1, 1
 ; RV64M-NEXT:    li a4, 819
 ; RV64M-NEXT:    mulw a3, a3, a4
 ; RV64M-NEXT:    addiw a3, a3, -1638
 ; RV64M-NEXT:    andi a3, a3, 2047
-; RV64M-NEXT:    li a4, 1
-; RV64M-NEXT:    sltu a3, a4, a3
+; RV64M-NEXT:    sltiu a3, a3, 2
+; RV64M-NEXT:    xori a3, a3, 1
 ; RV64M-NEXT:    li a4, 1463
 ; RV64M-NEXT:    mulw a2, a2, a4
 ; RV64M-NEXT:    addiw a2, a2, -1463
 ; RV64M-NEXT:    andi a2, a2, 2047
-; RV64M-NEXT:    li a4, 292
-; RV64M-NEXT:    sltu a2, a4, a2
+; RV64M-NEXT:    sltiu a2, a2, 293
+; RV64M-NEXT:    xori a2, a2, 1
 ; RV64M-NEXT:    negw a1, a1
 ; RV64M-NEXT:    negw a2, a2
 ; RV64M-NEXT:    andi a1, a1, 2047
 ; RV64M-NEXT:    andi a2, a2, 2047
 ; RV64M-NEXT:    slli a2, a2, 11
 ; RV64M-NEXT:    or a1, a1, a2
 ; RV64M-NEXT:    slli a2, a3, 22
 ; RV64M-NEXT:    sub a1, a1, a2

llvm/test/CodeGen/RISCV/xaluo.ll

entry:
   %obit = extractvalue {i64, i1} %t, 1
   store i64 %val, i64* %res
   ret i1 %obit
 }
 
 define zeroext i1 @ssubo1.i32(i32 %v1, i32 %v2, i32* %res) {
 ; RV32-LABEL: ssubo1.i32:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    sgtz a3, a1
-; RV32-NEXT:    sub a1, a0, a1
-; RV32-NEXT:    slt a0, a1, a0
-; RV32-NEXT:    xor a0, a3, a0
-; RV32-NEXT:    sw a1, 0(a2)
+; RV32-NEXT:    sub a3, a0, a1
+; RV32-NEXT:    slt a0, a3, a0
+; RV32-NEXT:    slti a1, a1, 1
+; RV32-NEXT:    xori a1, a1, 1
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    sw a3, 0(a2)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo1.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a1, a1
 ; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    sub a3, a0, a1
 ; RV64-NEXT:    subw a0, a0, a1
 ; RV64-NEXT:    xor a0, a0, a3
 ; RV64-NEXT:    snez a0, a0
 ; RV64-NEXT:    sw a3, 0(a2)
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo1.i32:
 ; RV32ZBA:       # %bb.0: # %entry
-; RV32ZBA-NEXT:    sgtz a3, a1
-; RV32ZBA-NEXT:    sub a1, a0, a1
-; RV32ZBA-NEXT:    slt a0, a1, a0
-; RV32ZBA-NEXT:    xor a0, a3, a0
-; RV32ZBA-NEXT:    sw a1, 0(a2)
+; RV32ZBA-NEXT:    sub a3, a0, a1
+; RV32ZBA-NEXT:    slt a0, a3, a0
+; RV32ZBA-NEXT:    slti a1, a1, 1
+; RV32ZBA-NEXT:    xori a1, a1, 1
+; RV32ZBA-NEXT:    xor a0, a1, a0
+; RV32ZBA-NEXT:    sw a3, 0(a2)
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssubo1.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sext.w a1, a1
 ; RV64ZBA-NEXT:    sext.w a0, a0
 ; RV64ZBA-NEXT:    sub a3, a0, a1
 ; RV64ZBA-NEXT:    subw a0, a0, a1

 ; RV32-NEXT:    sub a0, a0, a2
 ; RV32-NEXT:    sw a0, 0(a4)
 ; RV32-NEXT:    sw a5, 4(a4)
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.i64:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    sgtz a3, a1
-; RV64-NEXT:    sub a1, a0, a1
-; RV64-NEXT:    slt a0, a1, a0
-; RV64-NEXT:    xor a0, a3, a0
-; RV64-NEXT:    sd a1, 0(a2)
+; RV64-NEXT:    sub a3, a0, a1
+; RV64-NEXT:    slt a0, a3, a0
+; RV64-NEXT:    slti a1, a1, 1
+; RV64-NEXT:    xori a1, a1, 1
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    sd a3, 0(a2)
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a5, a0, a2
 ; RV32ZBA-NEXT:    sub a6, a1, a3
 ; RV32ZBA-NEXT:    sub a5, a6, a5
 ; RV32ZBA-NEXT:    xor a6, a1, a5
 ; RV32ZBA-NEXT:    xor a1, a1, a3
 ; RV32ZBA-NEXT:    and a1, a1, a6
 ; RV32ZBA-NEXT:    slti a1, a1, 0
 ; RV32ZBA-NEXT:    sub a0, a0, a2
 ; RV32ZBA-NEXT:    sw a0, 0(a4)
 ; RV32ZBA-NEXT:    sw a5, 4(a4)
 ; RV32ZBA-NEXT:    mv a0, a1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssubo.i64:
 ; RV64ZBA:       # %bb.0: # %entry
-; RV64ZBA-NEXT:    sgtz a3, a1
-; RV64ZBA-NEXT:    sub a1, a0, a1
-; RV64ZBA-NEXT:    slt a0, a1, a0
-; RV64ZBA-NEXT:    xor a0, a3, a0
-; RV64ZBA-NEXT:    sd a1, 0(a2)
+; RV64ZBA-NEXT:    sub a3, a0, a1
+; RV64ZBA-NEXT:    slt a0, a3, a0
+; RV64ZBA-NEXT:    slti a1, a1, 1
+; RV64ZBA-NEXT:    xori a1, a1, 1
+; RV64ZBA-NEXT:    xor a0, a1, a0
+; RV64ZBA-NEXT:    sd a3, 0(a2)
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   store i64 %val, i64* %res
   ret i1 %obit
 }

 ; RV32-NEXT:    add a4, a1, a3
 ; RV32-NEXT:    add a2, a0, a2
 ; RV32-NEXT:    sltu a0, a2, a0
 ; RV32-NEXT:    add a0, a4, a0
 ; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    not a1, a1
 ; RV32-NEXT:    and a0, a1, a0
-; RV32-NEXT:    li a1, -1
-; RV32-NEXT:    slt a0, a1, a0
+; RV32-NEXT:    slti a0, a0, 0
+; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: saddo.not.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a2, a0, a1
 ; RV64-NEXT:    slt a0, a2, a0
 ; RV64-NEXT:    slti a1, a1, 0
 ; RV64-NEXT:    xor a0, a1, a0
 ; RV64-NEXT:    xori a0, a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: saddo.not.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    add a4, a1, a3
 ; RV32ZBA-NEXT:    add a2, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
 ; RV32ZBA-NEXT:    add a0, a4, a0
 ; RV32ZBA-NEXT:    xor a0, a1, a0
 ; RV32ZBA-NEXT:    xor a1, a1, a3
 ; RV32ZBA-NEXT:    not a1, a1
 ; RV32ZBA-NEXT:    and a0, a1, a0
-; RV32ZBA-NEXT:    li a1, -1
-; RV32ZBA-NEXT:    slt a0, a1, a0
+; RV32ZBA-NEXT:    slti a0, a0, 0
+; RV32ZBA-NEXT:    xori a0, a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: saddo.not.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    add a2, a0, a1
 ; RV64ZBA-NEXT:    slt a0, a2, a0
 ; RV64ZBA-NEXT:    slti a1, a1, 0
 ; RV64ZBA-NEXT:    xor a0, a1, a0
entry:
   %obit = extractvalue {i64, i1} %t, 1
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 
 define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: ssubo.select.i32:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    sgtz a2, a1
-; RV32-NEXT:    sub a3, a0, a1
-; RV32-NEXT:    slt a3, a3, a0
-; RV32-NEXT:    bne a2, a3, .LBB34_2
+; RV32-NEXT:    sub a2, a0, a1
+; RV32-NEXT:    slt a2, a2, a0
+; RV32-NEXT:    slti a3, a1, 1
+; RV32-NEXT:    xori a3, a3, 1
+; RV32-NEXT:    bne a3, a2, .LBB34_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:  .LBB34_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.select.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a2, a1
 ; RV64-NEXT:    sext.w a3, a0
 ; RV64-NEXT:    sub a4, a3, a2
 ; RV64-NEXT:    subw a2, a3, a2
 ; RV64-NEXT:    bne a2, a4, .LBB34_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
 ; RV64-NEXT:  .LBB34_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo.select.i32:
 ; RV32ZBA:       # %bb.0: # %entry
-; RV32ZBA-NEXT:    sgtz a2, a1
-; RV32ZBA-NEXT:    sub a3, a0, a1
-; RV32ZBA-NEXT:    slt a3, a3, a0
-; RV32ZBA-NEXT:    bne a2, a3, .LBB34_2
+; RV32ZBA-NEXT:    sub a2, a0, a1
+; RV32ZBA-NEXT:    slt a2, a2, a0
+; RV32ZBA-NEXT:    slti a3, a1, 1
+; RV32ZBA-NEXT:    xori a3, a3, 1
+; RV32ZBA-NEXT:    bne a3, a2, .LBB34_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a1
 ; RV32ZBA-NEXT:  .LBB34_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssubo.select.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sext.w a2, a1
entry:
   %obit = extractvalue {i32, i1} %t, 1
   %ret = select i1 %obit, i32 %v1, i32 %v2
   ret i32 %ret
 }
 
 define i1 @ssubo.not.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: ssubo.not.i32:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    sgtz a2, a1
-; RV32-NEXT:    sub a1, a0, a1
-; RV32-NEXT:    slt a0, a1, a0
-; RV32-NEXT:    xor a0, a2, a0
+; RV32-NEXT:    sub a2, a0, a1
+; RV32-NEXT:    slt a0, a2, a0
+; RV32-NEXT:    slti a1, a1, 1
+; RV32-NEXT:    xori a1, a1, 1
+; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.not.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a1, a1
 ; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    sub a2, a0, a1
 ; RV64-NEXT:    subw a0, a0, a1
 ; RV64-NEXT:    xor a0, a0, a2
 ; RV64-NEXT:    seqz a0, a0
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo.not.i32:
 ; RV32ZBA:       # %bb.0: # %entry
-; RV32ZBA-NEXT:    sgtz a2, a1
-; RV32ZBA-NEXT:    sub a1, a0, a1
-; RV32ZBA-NEXT:    slt a0, a1, a0
-; RV32ZBA-NEXT:    xor a0, a2, a0
+; RV32ZBA-NEXT:    sub a2, a0, a1
+; RV32ZBA-NEXT:    slt a0, a2, a0
+; RV32ZBA-NEXT:    slti a1, a1, 1
+; RV32ZBA-NEXT:    xori a1, a1, 1
+; RV32ZBA-NEXT:    xor a0, a1, a0
 ; RV32ZBA-NEXT:    xori a0, a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssubo.not.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sext.w a1, a1
 ; RV64ZBA-NEXT:    sext.w a0, a0
 ; RV64ZBA-NEXT:    sub a2, a0, a1

 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
 ; RV32-NEXT:  .LBB36_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.select.i64:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    sgtz a2, a1
-; RV64-NEXT:    sub a3, a0, a1
-; RV64-NEXT:    slt a3, a3, a0
-; RV64-NEXT:    bne a2, a3, .LBB36_2
+; RV64-NEXT:    sub a2, a0, a1
+; RV64-NEXT:    slt a2, a2, a0
+; RV64-NEXT:    slti a3, a1, 1
+; RV64-NEXT:    xori a3, a3, 1
+; RV64-NEXT:    bne a3, a2, .LBB36_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
 ; RV64-NEXT:  .LBB36_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo.select.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a4, a0, a2
 ; RV32ZBA-NEXT:    sub a5, a1, a3
 ; RV32ZBA-NEXT:    sub a4, a5, a4
 ; RV32ZBA-NEXT:    xor a4, a1, a4
 ; RV32ZBA-NEXT:    xor a5, a1, a3
 ; RV32ZBA-NEXT:    and a4, a5, a4
 ; RV32ZBA-NEXT:    bltz a4, .LBB36_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a2
 ; RV32ZBA-NEXT:    mv a1, a3
 ; RV32ZBA-NEXT:  .LBB36_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssubo.select.i64:
 ; RV64ZBA:       # %bb.0: # %entry
-; RV64ZBA-NEXT:    sgtz a2, a1
-; RV64ZBA-NEXT:    sub a3, a0, a1
-; RV64ZBA-NEXT:    slt a3, a3, a0
-; RV64ZBA-NEXT:    bne a2, a3, .LBB36_2
+; RV64ZBA-NEXT:    sub a2, a0, a1
+; RV64ZBA-NEXT:    slt a2, a2, a0
+; RV64ZBA-NEXT:    slti a3, a1, 1
+; RV64ZBA-NEXT:    xori a3, a3, 1
+; RV64ZBA-NEXT:    bne a3, a2, .LBB36_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
 ; RV64ZBA-NEXT:  .LBB36_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
   ret i64 %ret
 }
 
 define i1 @ssub.not.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: ssub.not.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a0, a0, a2
 ; RV32-NEXT:    sub a2, a1, a3
 ; RV32-NEXT:    sub a0, a2, a0
 ; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    and a0, a1, a0
-; RV32-NEXT:    li a1, -1
-; RV32-NEXT:    slt a0, a1, a0
+; RV32-NEXT:    slti a0, a0, 0
+; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssub.not.i64:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    sgtz a2, a1
-; RV64-NEXT:    sub a1, a0, a1
-; RV64-NEXT:    slt a0, a1, a0
-; RV64-NEXT:    xor a0, a2, a0
+; RV64-NEXT:    sub a2, a0, a1
+; RV64-NEXT:    slt a0, a2, a0
+; RV64-NEXT:    slti a1, a1, 1
+; RV64-NEXT:    xori a1, a1, 1
+; RV64-NEXT:    xor a0, a1, a0
 ; RV64-NEXT:    xori a0, a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssub.not.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a0, a2
 ; RV32ZBA-NEXT:    sub a2, a1, a3
 ; RV32ZBA-NEXT:    sub a0, a2, a0
 ; RV32ZBA-NEXT:    xor a0, a1, a0
 ; RV32ZBA-NEXT:    xor a1, a1, a3
 ; RV32ZBA-NEXT:    and a0, a1, a0
-; RV32ZBA-NEXT:    li a1, -1
-; RV32ZBA-NEXT:    slt a0, a1, a0
+; RV32ZBA-NEXT:    slti a0, a0, 0
+; RV32ZBA-NEXT:    xori a0, a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssub.not.i64:
 ; RV64ZBA:       # %bb.0: # %entry
-; RV64ZBA-NEXT:    sgtz a2, a1
-; RV64ZBA-NEXT:    sub a1, a0, a1
-; RV64ZBA-NEXT:    slt a0, a1, a0
-; RV64ZBA-NEXT:    xor a0, a2, a0
+; RV64ZBA-NEXT:    sub a2, a0, a1
+; RV64ZBA-NEXT:    slt a0, a2, a0
+; RV64ZBA-NEXT:    slti a1, a1, 1
+; RV64ZBA-NEXT:    xori a1, a1, 1
+; RV64ZBA-NEXT:    xor a0, a1, a0
 ; RV64ZBA-NEXT:    xori a0, a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = xor i1 %obit, true
   ret i1 %ret
 }

 
 continue:
   ret i1 true
 }
 
 define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: ssubo.br.i32:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    sgtz a2, a1
-; RV32-NEXT:    sub a1, a0, a1
-; RV32-NEXT:    slt a0, a1, a0
-; RV32-NEXT:    beq a2, a0, .LBB54_2
+; RV32-NEXT:    sub a2, a0, a1
+; RV32-NEXT:    slt a0, a2, a0
+; RV32-NEXT:    slti a1, a1, 1
+; RV32-NEXT:    xori a1, a1, 1
+; RV32-NEXT:    beq a1, a0, .LBB54_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB54_2: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.br.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a1, a1
 ; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    sub a2, a0, a1
 ; RV64-NEXT:    subw a0, a0, a1
 ; RV64-NEXT:    beq a0, a2, .LBB54_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
 ; RV64-NEXT:  .LBB54_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo.br.i32:
 ; RV32ZBA:       # %bb.0: # %entry
-; RV32ZBA-NEXT:    sgtz a2, a1
-; RV32ZBA-NEXT:    sub a1, a0, a1
-; RV32ZBA-NEXT:    slt a0, a1, a0
-; RV32ZBA-NEXT:    beq a2, a0, .LBB54_2
+; RV32ZBA-NEXT:    sub a2, a0, a1
+; RV32ZBA-NEXT:    slt a0, a2, a0
+; RV32ZBA-NEXT:    slti a1, a1, 1
+; RV32ZBA-NEXT:    xori a1, a1, 1
+; RV32ZBA-NEXT:    beq a1, a0, .LBB54_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
 ; RV32ZBA-NEXT:  .LBB54_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssubo.br.i32:

 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB55_2: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.br.i64:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    sgtz a2, a1
-; RV64-NEXT:    sub a1, a0, a1
-; RV64-NEXT:    slt a0, a1, a0
-; RV64-NEXT:    beq a2, a0, .LBB55_2
+; RV64-NEXT:    sub a2, a0, a1
+; RV64-NEXT:    slt a0, a2, a0
+; RV64-NEXT:    slti a1, a1, 1
+; RV64-NEXT:    xori a1, a1, 1
+; RV64-NEXT:    beq a1, a0, .LBB55_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
 ; RV64-NEXT:  .LBB55_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo.br.i64:

 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
 ; RV32ZBA-NEXT:  .LBB55_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssubo.br.i64:
 ; RV64ZBA:       # %bb.0: # %entry
-; RV64ZBA-NEXT:    sgtz a2, a1
-; RV64ZBA-NEXT:    sub a1, a0, a1
-; RV64ZBA-NEXT:    slt a0, a1, a0
-; RV64ZBA-NEXT:    beq a2, a0, .LBB55_2
+; RV64ZBA-NEXT:    sub a2, a0, a1
+; RV64ZBA-NEXT:    slt a0, a2, a0
+; RV64ZBA-NEXT:    slti a1, a1, 1
+; RV64ZBA-NEXT:    xori a1, a1, 1
+; RV64ZBA-NEXT:    beq a1, a0, .LBB55_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    li a0, 0
 ; RV64ZBA-NEXT:    ret
 ; RV64ZBA-NEXT:  .LBB55_2: # %continue
 ; RV64ZBA-NEXT:    li a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)