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[RISCV] Select SRLI+SLLI for AND with leading ones mask
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Authored by Luhaocong on Mar 14 2022, 5:55 AM.

Details

Summary

Select SRLI+SLLI for and i64 %x, imm if the imm is a leading ones mask.
It's useful in RV64 when the mask exceeds simm32 (cannot be generated by LUI).

Diff Detail

Event Timeline

Luhaocong created this revision.Mar 14 2022, 5:55 AM
Luhaocong requested review of this revision.Mar 14 2022, 5:55 AM
Luhaocong updated this revision to Diff 415075.Mar 14 2022, 6:02 AM
craig.topper added inline comments.Mar 14 2022, 10:10 AM
llvm/test/CodeGen/RISCV/and.ll
103

Should we use srliw and slliw here?

llvm/test/CodeGen/RISCV/copysign-casts.ll
33

Is this worse if the AND is in a loop? The LUI could be hoisted out of the out loop, but the shifts can't.

craig.topper added inline comments.Mar 14 2022, 7:36 PM
llvm/test/CodeGen/RISCV/and.ll
121

I just submitted D121650 to fix this case so it will sign extend -1536 to i64 instead of zero extending.

Luhaocong edited the summary of this revision. (Show Details)
  1. Only do this selection for and i64 %x, imm when the imm exceeds simm32 (cannot be generated by LUI)
  2. Add some test cases
Luhaocong marked an inline comment as done.Mar 15 2022, 1:22 AM
Luhaocong added inline comments.
llvm/test/CodeGen/RISCV/copysign-casts.ll
33

if a leading ones mask can be generated by LUI, it's really unnecessary to do this. I have excluded this case.

This revision is now accepted and ready to land.Mar 15 2022, 8:37 AM
Luhaocong updated this revision to Diff 415660.Mar 15 2022, 6:46 PM
Luhaocong marked an inline comment as done.

rebase

This revision was landed with ongoing or failed builds.Mar 15 2022, 7:11 PM
This revision was automatically updated to reflect the committed changes.