[RISCV] Select SRLI+SLLI for AND with leading ones mask

[Luhaocong]

Summary

Select SRLI+SLLI for and i64 %x, imm if the imm is a leading ones mask.
It's useful in RV64 when the mask exceeds simm32 (cannot be generated by LUI).

[craig.topper]

llvm/test/CodeGen/RISCV/and.ll

103

Should we use srliw and slliw here?

llvm/test/CodeGen/RISCV/copysign-casts.ll

32

Is this worse if the AND is in a loop? The LUI could be hoisted out of the out loop, but the shifts can't.

[craig.topper]

llvm/test/CodeGen/RISCV/and.ll

121

I just submitted D121650 to fix this case so it will sign extend -1536 to i64 instead of zero extending.

[Luhaocong]

1. Only do this selection for and i64 %x, imm when the imm exceeds simm32 (cannot be generated by LUI)
2. Add some test cases

[Luhaocong]

llvm/test/CodeGen/RISCV/copysign-casts.ll

32

if a leading ones mask can be generated by LUI, it's really unnecessary to do this. I have excluded this case.

[craig.topper]

LGTM

[Luhaocong]

rebase

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 
 // Return imm - imm/2.
 def AddiPairImmB : SDNodeXForm<imm, [{
   int64_t Imm = N->getSExtValue();
   return CurDAG->getTargetConstant(Imm - Imm / 2, SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
+def TrailingZeros : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingZeros(),
+                                   SDLoc(N), N->getValueType(0));
+}]>;
+
 def XLenSubTrailingOnes : SDNodeXForm<imm, [{
   uint64_t XLen = Subtarget->getXLen();
   uint64_t TrailingOnes = N->getAPIntValue().countTrailingOnes();
   return CurDAG->getTargetConstant(XLen - TrailingOnes, SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
 // Checks if this mask is a non-empty sequence of ones starting at the
-// least significant bit with the remainder zero and exceeds simm12.
+// most/least significant bit with the remainder zero and exceeds simm12.
+def LeadingOnesMask : PatLeaf<(imm), [{
+  if (!N->hasOneUse())
+    return false;
+  return !isInt<12>(N->getSExtValue()) && isMask_64(~N->getSExtValue());
+}], TrailingZeros>;
+
 def TrailingOnesMask : PatLeaf<(imm), [{
   if (!N->hasOneUse())
     return false;
   return !isInt<12>(N->getSExtValue()) && isMask_64(N->getZExtValue());
 }], XLenSubTrailingOnes>;
 
 //===----------------------------------------------------------------------===//
 // Instruction Formats

 def : PatGprGpr<and, AND>;
 def : PatGprSimm12<and, ANDI>;
 def : PatGprGpr<xor, XOR>;
 def : PatGprSimm12<xor, XORI>;
 def : PatGprUimmLog2XLen<shl, SLLI>;
 def : PatGprUimmLog2XLen<srl, SRLI>;
 def : PatGprUimmLog2XLen<sra, SRAI>;
 
-// AND with trailing ones mask exceeding simm12.
+// AND with leading/trailing ones mask exceeding simm12.
+def : Pat<(XLenVT (and GPR:$rs, LeadingOnesMask:$mask)),
+          (SLLI (SRLI $rs, LeadingOnesMask:$mask), LeadingOnesMask:$mask)>;
+
 def : Pat<(XLenVT (and GPR:$rs, TrailingOnesMask:$mask)),
           (SRLI (SLLI $rs, TrailingOnesMask:$mask), TrailingOnesMask:$mask)>;
 
 // Match both a plain shift and one where the shift amount is masked (this is
 // typically introduced when the legalizer promotes the shift amount and
 // zero-extends it). For RISC-V, the mask is unnecessary as shifts in the base
 // ISA only read the least significant 5 bits (RV32I) or 6 bits (RV64I).
 def shiftMaskXLen : ComplexPattern<XLenVT, 1, "selectShiftMaskXLen", [], [], 0>;

llvm/test/CodeGen/RISCV/and.ll

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 52
 ; RV64I-NEXT:    srli a0, a0, 52
 ; RV64I-NEXT:    ret
   %a = and i64 %x, 4095
   ret i64 %a
 }
 
+; Test for handling of AND with constant. If this constant exceeds simm12 and
+; also is a non-empty sequence of ones starting at the most significant bit
+; with the remainder zero, we can replace it with SRLI + SLLI
+
+define i32 @and32_0x7ffff000(i32 %x) {
+; RV32I-LABEL: and32_0x7ffff000:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 524287
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: and32_0x7ffff000:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 524287
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+  %a = and i32 %x, 2147479552
+  ret i32 %a
+}
+
+define i32 @and32_0xfffff000(i32 %x) {
+; RV32I-LABEL: and32_0xfffff000:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srli a0, a0, 12
+; RV32I-NEXT:    slli a0, a0, 12
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: and32_0xfffff000:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 256
+; RV64I-NEXT:    addiw a1, a1, -1
+; RV64I-NEXT:    slli a1, a1, 12
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+  %a = and i32 %x, -4096
+  ret i32 %a
+}
+
+define i32 @and32_0xfffffa00(i32 %x) {
+; RV32I-LABEL: and32_0xfffffa00:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a0, a0, -1536
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: and32_0xfffffa00:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a1, 1
+; RV64I-NEXT:    slli a1, a1, 32
+; RV64I-NEXT:    addi a1, a1, -1536
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+  %a = and i32 %x, -1536
+  ret i32 %a
+}
+
+define i64 @and64_0x7ffffffffffff000(i64 %x) {
+; RV32I-LABEL: and64_0x7ffffffffffff000:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srli a0, a0, 12
+; RV32I-NEXT:    slli a0, a0, 12
+; RV32I-NEXT:    slli a1, a1, 1
+; RV32I-NEXT:    srli a1, a1, 1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: and64_0x7ffffffffffff000:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1048574
+; RV64I-NEXT:    srli a1, a1, 1
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+  %a = and i64 %x, 9223372036854771712
+  ret i64 %a
+}
+
+define i64 @and64_0xfffffffffffff000(i64 %x) {
+; RV32I-LABEL: and64_0xfffffffffffff000:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srli a0, a0, 12
+; RV32I-NEXT:    slli a0, a0, 12
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: and64_0xfffffffffffff000:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srli a0, a0, 12
+; RV64I-NEXT:    slli a0, a0, 12
+; RV64I-NEXT:    ret
+  %a = and i64 %x, -4096
+  ret i64 %a
+}
+
+define i64 @and64_0xfffffffffffffa00(i64 %x) {
+; RV32I-LABEL: and64_0xfffffffffffffa00:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a0, a0, -1536
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: and64_0xfffffffffffffa00:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a0, a0, -1536
+; RV64I-NEXT:    ret
+  %a = and i64 %x, -1536
+  ret i64 %a
+}
+

llvm/test/CodeGen/RISCV/copysign-casts.ll

 
 declare double @llvm.copysign.f64(double, double)
 declare float @llvm.copysign.f32(float, float)
 declare half @llvm.copysign.f16(half, half)
 
 define double @fold_promote_d_s(double %a, float %b) nounwind {
 ; RV32I-LABEL: fold_promote_d_s:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a3, 524288
-; RV32I-NEXT:    and a2, a2, a3
+; RV32I-NEXT:    srli a2, a2, 31
+; RV32I-NEXT:    slli a2, a2, 31
 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    srli a1, a1, 1
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_promote_d_s:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a2, 524288
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    slli a1, a1, 32
 ; RV64I-NEXT:    slli a0, a0, 1
 ; RV64I-NEXT:    srli a0, a0, 1
+; RV64I-NEXT:    srli a1, a1, 31
+; RV64I-NEXT:    slli a1, a1, 31
+; RV64I-NEXT:    slli a1, a1, 32
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IF-LABEL: fold_promote_d_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.x.w a2, fa0
-; RV32IF-NEXT:    lui a3, 524288
-; RV32IF-NEXT:    and a2, a2, a3
 ; RV32IF-NEXT:    slli a1, a1, 1
 ; RV32IF-NEXT:    srli a1, a1, 1
+; RV32IF-NEXT:    srli a2, a2, 31
+; RV32IF-NEXT:    slli a2, a2, 31
 ; RV32IF-NEXT:    or a1, a1, a2
 ; RV32IF-NEXT:    ret
 ;
 ; RV32IFD-LABEL: fold_promote_d_s:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    fcvt.d.s ft0, fa1
 ; RV32IFD-NEXT:    fsgnj.d fa0, fa0, ft0
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fold_promote_d_s:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fcvt.d.s ft0, fa1
 ; RV64IFD-NEXT:    fsgnj.d fa0, fa0, ft0
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32IFZFH-LABEL: fold_promote_d_s:
 ; RV32IFZFH:       # %bb.0:
 ; RV32IFZFH-NEXT:    fmv.x.w a2, fa0
-; RV32IFZFH-NEXT:    lui a3, 524288
-; RV32IFZFH-NEXT:    and a2, a2, a3
 ; RV32IFZFH-NEXT:    slli a1, a1, 1
 ; RV32IFZFH-NEXT:    srli a1, a1, 1
+; RV32IFZFH-NEXT:    srli a2, a2, 31
+; RV32IFZFH-NEXT:    slli a2, a2, 31
 ; RV32IFZFH-NEXT:    or a1, a1, a2
 ; RV32IFZFH-NEXT:    ret
 ;
 ; RV32IFDZFH-LABEL: fold_promote_d_s:
 ; RV32IFDZFH:       # %bb.0:
 ; RV32IFDZFH-NEXT:    fcvt.d.s ft0, fa1
 ; RV32IFDZFH-NEXT:    fsgnj.d fa0, fa0, ft0
 ; RV32IFDZFH-NEXT:    ret
; RV64IFDZFH-NEXT:    ret
   %c = fpext half %b to float
   %t = call float @llvm.copysign.f32(float %a, float %c)
   ret float %t
 }
 
 define float @fold_demote_s_d(float %a, double %b) nounwind {
 ; RV32I-LABEL: fold_demote_s_d:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a1, 524288
-; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    srli a1, a2, 31
+; RV32I-NEXT:    slli a1, a1, 31
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_demote_s_d:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a2, -1
-; RV64I-NEXT:    slli a2, a2, 63
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    slli a0, a0, 33
 ; RV64I-NEXT:    srli a0, a0, 33
+; RV64I-NEXT:    srli a1, a1, 63
+; RV64I-NEXT:    slli a1, a1, 63
+; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IF-LABEL: fold_demote_s_d:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fsgnj.s fa0, fa0, ft0
 ; RV32IF-NEXT:    ret
; RV64IFDZFH-NEXT:    ret
   %c = fptrunc double %b to float
   %t = call float @llvm.copysign.f32(float %a, float %c)
   ret float %t
 }
 
 define half @fold_demote_h_s(half %a, float %b) nounwind {
 ; RV32I-LABEL: fold_demote_h_s:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a2, 524288
-; RV32I-NEXT:    and a1, a1, a2
-; RV32I-NEXT:    srli a1, a1, 16
 ; RV32I-NEXT:    slli a0, a0, 17
 ; RV32I-NEXT:    srli a0, a0, 17
+; RV32I-NEXT:    srli a1, a1, 31
+; RV32I-NEXT:    slli a1, a1, 31
+; RV32I-NEXT:    srli a1, a1, 16
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_demote_h_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    slli a2, a2, 31
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a1, a1, 16
 ; RV64I-NEXT:    slli a0, a0, 49
 ; RV64I-NEXT:    srli a0, a0, 49
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IF-LABEL: fold_demote_h_s:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.x.w a0, fa0
-; RV32IF-NEXT:    fmv.x.w a1, fa1
-; RV32IF-NEXT:    lui a2, 524288
-; RV32IF-NEXT:    and a1, a1, a2
-; RV32IF-NEXT:    srli a1, a1, 16
-; RV32IF-NEXT:    slli a0, a0, 17
-; RV32IF-NEXT:    srli a0, a0, 17
-; RV32IF-NEXT:    or a0, a0, a1
+; RV32IF-NEXT:    fmv.x.w a0, fa1
+; RV32IF-NEXT:    fmv.x.w a1, fa0
+; RV32IF-NEXT:    slli a1, a1, 17
+; RV32IF-NEXT:    srli a1, a1, 17
+; RV32IF-NEXT:    srli a0, a0, 31
+; RV32IF-NEXT:    slli a0, a0, 31
+; RV32IF-NEXT:    srli a0, a0, 16
+; RV32IF-NEXT:    or a0, a1, a0
 ; RV32IF-NEXT:    lui a1, 1048560
 ; RV32IF-NEXT:    or a0, a0, a1
 ; RV32IF-NEXT:    fmv.w.x fa0, a0
 ; RV32IF-NEXT:    ret
 ;
 ; RV32IFD-LABEL: fold_demote_h_s:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fmv.x.w a0, fa0
-; RV32IFD-NEXT:    fmv.x.w a1, fa1
-; RV32IFD-NEXT:    lui a2, 524288
-; RV32IFD-NEXT:    and a1, a1, a2
-; RV32IFD-NEXT:    srli a1, a1, 16
-; RV32IFD-NEXT:    slli a0, a0, 17
-; RV32IFD-NEXT:    srli a0, a0, 17
-; RV32IFD-NEXT:    or a0, a0, a1
+; RV32IFD-NEXT:    fmv.x.w a0, fa1
+; RV32IFD-NEXT:    fmv.x.w a1, fa0
+; RV32IFD-NEXT:    slli a1, a1, 17
+; RV32IFD-NEXT:    srli a1, a1, 17
+; RV32IFD-NEXT:    srli a0, a0, 31
+; RV32IFD-NEXT:    slli a0, a0, 31
+; RV32IFD-NEXT:    srli a0, a0, 16
+; RV32IFD-NEXT:    or a0, a1, a0
 ; RV32IFD-NEXT:    lui a1, 1048560
 ; RV32IFD-NEXT:    or a0, a0, a1
 ; RV32IFD-NEXT:    fmv.w.x fa0, a0
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fold_demote_h_s:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fmv.x.w a0, fa0
-; RV64IFD-NEXT:    fmv.x.w a1, fa1
-; RV64IFD-NEXT:    lui a2, 524288
-; RV64IFD-NEXT:    and a1, a1, a2
-; RV64IFD-NEXT:    srli a1, a1, 16
-; RV64IFD-NEXT:    slli a0, a0, 49
-; RV64IFD-NEXT:    srli a0, a0, 49
-; RV64IFD-NEXT:    or a0, a0, a1
+; RV64IFD-NEXT:    fmv.x.w a0, fa1
+; RV64IFD-NEXT:    fmv.x.w a1, fa0
+; RV64IFD-NEXT:    slli a1, a1, 49
+; RV64IFD-NEXT:    srli a1, a1, 49
+; RV64IFD-NEXT:    srli a0, a0, 31
+; RV64IFD-NEXT:    slli a0, a0, 31
+; RV64IFD-NEXT:    srli a0, a0, 16
+; RV64IFD-NEXT:    or a0, a1, a0
 ; RV64IFD-NEXT:    lui a1, 1048560
 ; RV64IFD-NEXT:    or a0, a0, a1
 ; RV64IFD-NEXT:    fmv.w.x fa0, a0
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32IFZFH-LABEL: fold_demote_h_s:
 ; RV32IFZFH:       # %bb.0:
 ; RV32IFZFH-NEXT:    fcvt.h.s ft0, fa1
; RV64IFDZFH-NEXT:    ret
   %c = fptrunc float %b to half
   %t = call half @llvm.copysign.f16(half %a, half %c)
   ret half %t
 }
 
 define half @fold_demote_h_d(half %a, double %b) nounwind {
 ; RV32I-LABEL: fold_demote_h_d:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a1, 524288
-; RV32I-NEXT:    and a1, a2, a1
-; RV32I-NEXT:    srli a1, a1, 16
 ; RV32I-NEXT:    slli a0, a0, 17
 ; RV32I-NEXT:    srli a0, a0, 17
+; RV32I-NEXT:    srli a1, a2, 31
+; RV32I-NEXT:    slli a1, a1, 31
+; RV32I-NEXT:    srli a1, a1, 16
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_demote_h_d:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a2, -1
-; RV64I-NEXT:    slli a2, a2, 63
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    srli a1, a1, 48
 ; RV64I-NEXT:    slli a0, a0, 49
 ; RV64I-NEXT:    srli a0, a0, 49
+; RV64I-NEXT:    srli a1, a1, 63
+; RV64I-NEXT:    slli a1, a1, 63
+; RV64I-NEXT:    srli a1, a1, 48
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IF-LABEL: fold_demote_h_d:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.x.w a0, fa0
-; RV32IF-NEXT:    lui a2, 524288
-; RV32IF-NEXT:    and a1, a1, a2
+; RV32IF-NEXT:    srli a1, a1, 31
+; RV32IF-NEXT:    slli a1, a1, 31
 ; RV32IF-NEXT:    srli a1, a1, 16
 ; RV32IF-NEXT:    slli a0, a0, 17
 ; RV32IF-NEXT:    srli a0, a0, 17
 ; RV32IF-NEXT:    or a0, a0, a1
 ; RV32IF-NEXT:    lui a1, 1048560
 ; RV32IF-NEXT:    or a0, a0, a1
 ; RV32IF-NEXT:    fmv.w.x fa0, a0
 ; RV32IF-NEXT:    ret
 ;
 ; RV32IFD-LABEL: fold_demote_h_d:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    fsd fa1, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 12(sp)
 ; RV32IFD-NEXT:    fmv.x.w a1, fa0
-; RV32IFD-NEXT:    lui a2, 524288
-; RV32IFD-NEXT:    and a0, a0, a2
-; RV32IFD-NEXT:    srli a0, a0, 16
 ; RV32IFD-NEXT:    slli a1, a1, 17
 ; RV32IFD-NEXT:    srli a1, a1, 17
+; RV32IFD-NEXT:    srli a0, a0, 31
+; RV32IFD-NEXT:    slli a0, a0, 31
+; RV32IFD-NEXT:    srli a0, a0, 16
 ; RV32IFD-NEXT:    or a0, a1, a0
 ; RV32IFD-NEXT:    lui a1, 1048560
 ; RV32IFD-NEXT:    or a0, a0, a1
 ; RV32IFD-NEXT:    fmv.w.x fa0, a0
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fold_demote_h_d:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fmv.x.w a0, fa0
-; RV64IFD-NEXT:    fmv.x.d a1, fa1
-; RV64IFD-NEXT:    li a2, -1
-; RV64IFD-NEXT:    slli a2, a2, 63
-; RV64IFD-NEXT:    and a1, a1, a2
-; RV64IFD-NEXT:    srli a1, a1, 48
-; RV64IFD-NEXT:    slli a0, a0, 49
-; RV64IFD-NEXT:    srli a0, a0, 49
-; RV64IFD-NEXT:    or a0, a0, a1
+; RV64IFD-NEXT:    fmv.x.d a0, fa1
+; RV64IFD-NEXT:    fmv.x.w a1, fa0
+; RV64IFD-NEXT:    slli a1, a1, 49
+; RV64IFD-NEXT:    srli a1, a1, 49
+; RV64IFD-NEXT:    srli a0, a0, 63
+; RV64IFD-NEXT:    slli a0, a0, 63
+; RV64IFD-NEXT:    srli a0, a0, 48
+; RV64IFD-NEXT:    or a0, a1, a0
 ; RV64IFD-NEXT:    lui a1, 1048560
 ; RV64IFD-NEXT:    or a0, a0, a1
 ; RV64IFD-NEXT:    fmv.w.x fa0, a0
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32IFZFH-LABEL: fold_demote_h_d:
 ; RV32IFZFH:       # %bb.0:
 ; RV32IFZFH-NEXT:    srli a0, a1, 16

llvm/test/CodeGen/RISCV/double-arith.ll

 ;
 ; RV64IFD-LABEL: fsgnj_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fsgnj.d fa0, fa0, fa1
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fsgnj_d:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a2, 524288
-; RV32I-NEXT:    and a2, a3, a2
+; RV32I-NEXT:    srli a2, a3, 31
+; RV32I-NEXT:    slli a2, a2, 31
 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    srli a1, a1, 1
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fsgnj_d:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a2, -1
-; RV64I-NEXT:    slli a2, a2, 63
-; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    srli a1, a1, 63
+; RV64I-NEXT:    slli a1, a1, 63
 ; RV64I-NEXT:    slli a0, a0, 1
 ; RV64I-NEXT:    srli a0, a0, 1
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = call double @llvm.copysign.f64(double %a, double %b)
   ret double %1
 }
 

 ; RV64IFD-LABEL: fsgnjn_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fsgnjn.d fa0, fa0, fa1
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fsgnjn_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    not a2, a3
-; RV32I-NEXT:    lui a3, 524288
-; RV32I-NEXT:    and a2, a2, a3
 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    srli a1, a1, 1
+; RV32I-NEXT:    srli a2, a2, 31
+; RV32I-NEXT:    slli a2, a2, 31
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fsgnjn_d:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    not a1, a1
-; RV64I-NEXT:    li a2, -1
-; RV64I-NEXT:    slli a2, a2, 63
-; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    slli a0, a0, 1
 ; RV64I-NEXT:    srli a0, a0, 1
+; RV64I-NEXT:    srli a1, a1, 63
+; RV64I-NEXT:    slli a1, a1, 63
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = fsub double -0.0, %b
   %2 = call double @llvm.copysign.f64(double %a, double %1)
   ret double %2
 }
 
 declare double @llvm.fabs.f64(double)

llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll

 ; DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN will convert to bitwise
 ; operations if floating point isn't supported. A combine could be written to
 ; do the same even when f64 is legal.
 
 define double @fcopysign_fneg(double %a, double %b) nounwind {
 ; RV32I-LABEL: fcopysign_fneg:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    not a2, a3
-; RV32I-NEXT:    lui a3, 524288
-; RV32I-NEXT:    and a2, a2, a3
 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    srli a1, a1, 1
+; RV32I-NEXT:    srli a2, a2, 31
+; RV32I-NEXT:    slli a2, a2, 31
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IFD-LABEL: fcopysign_fneg:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a2, 8(sp)
 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
 ; RV32IFD-NEXT:    fsgnjn.d ft0, ft1, ft0
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64I-LABEL: fcopysign_fneg:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    not a1, a1
-; RV64I-NEXT:    li a2, -1
-; RV64I-NEXT:    slli a2, a2, 63
-; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    slli a0, a0, 1
 ; RV64I-NEXT:    srli a0, a0, 1
+; RV64I-NEXT:    srli a1, a1, 63
+; RV64I-NEXT:    slli a1, a1, 63
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcopysign_fneg:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    li a2, -1
 ; RV64IFD-NEXT:    slli a2, a2, 63
 ; RV64IFD-NEXT:    xor a1, a1, a2

llvm/test/CodeGen/RISCV/double-intrinsics.ll

 ;
 ; RV64IFD-LABEL: copysign_f64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fsgnj.d fa0, fa0, fa1
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: copysign_f64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a2, 524288
-; RV32I-NEXT:    and a2, a3, a2
+; RV32I-NEXT:    srli a2, a3, 31
+; RV32I-NEXT:    slli a2, a2, 31
 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    srli a1, a1, 1
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: copysign_f64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a2, -1
-; RV64I-NEXT:    slli a2, a2, 63
-; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    srli a1, a1, 63
+; RV64I-NEXT:    slli a1, a1, 63
 ; RV64I-NEXT:    slli a0, a0, 1
 ; RV64I-NEXT:    srli a0, a0, 1
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = call double @llvm.copysign.f64(double %a, double %b)
   ret double %1
 }
 

llvm/test/CodeGen/RISCV/float-arith.ll

 ;
 ; RV64IF-LABEL: fsgnj_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fsgnj.s fa0, fa0, fa1
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fsgnj_s:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a2, 524288
-; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    srli a1, a1, 31
+; RV32I-NEXT:    slli a1, a1, 31
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fsgnj_s:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a2, 524288
-; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    srli a1, a1, 31
+; RV64I-NEXT:    slli a1, a1, 31
 ; RV64I-NEXT:    slli a0, a0, 33
 ; RV64I-NEXT:    srli a0, a0, 33
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.copysign.f32(float %a, float %b)
   ret float %1
 }
 

 ; RV32I-LABEL: fsgnjn_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    not a0, a0
-; RV32I-NEXT:    lui a1, 524288
-; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    srli a0, a0, 31
+; RV32I-NEXT:    slli a0, a0, 31
 ; RV32I-NEXT:    slli a1, s0, 1
 ; RV32I-NEXT:    srli a1, a1, 1
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fsgnjn_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    call __addsf3@plt
 ; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    lui a1, 524288
-; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    srli a0, a0, 31
+; RV64I-NEXT:    slli a0, a0, 31
 ; RV64I-NEXT:    slli a1, s0, 33
 ; RV64I-NEXT:    srli a1, a1, 33
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fadd float %a, %b

llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll

 ; DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN will convert to bitwise
 ; operations if floating point isn't supported. A combine could be written to
 ; do the same even when f32 is legal.
 
 define float @fcopysign_fneg(float %a, float %b) nounwind {
 ; RV32I-LABEL: fcopysign_fneg:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    not a1, a1
-; RV32I-NEXT:    lui a2, 524288
-; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    srli a0, a0, 1
+; RV32I-NEXT:    srli a1, a1, 31
+; RV32I-NEXT:    slli a1, a1, 31
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IF-LABEL: fcopysign_fneg:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    lui a2, 524288
 ; RV32IF-NEXT:    xor a1, a1, a2
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fsgnj.s ft0, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64I-LABEL: fcopysign_fneg:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    not a1, a1
-; RV64I-NEXT:    lui a2, 524288
-; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    slli a0, a0, 33
 ; RV64I-NEXT:    srli a0, a0, 33
+; RV64I-NEXT:    srli a1, a1, 31
+; RV64I-NEXT:    slli a1, a1, 31
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcopysign_fneg:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fsgnjn.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = fneg float %b
   %2 = call float @llvm.copysign.f32(float %a, float %1)
   ret float %2
 }

llvm/test/CodeGen/RISCV/float-intrinsics.ll

 ;
 ; RV64IF-LABEL: copysign_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fsgnj.s fa0, fa0, fa1
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: copysign_f32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a2, 524288
-; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    srli a1, a1, 31
+; RV32I-NEXT:    slli a1, a1, 31
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: copysign_f32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a2, 524288
-; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    srli a1, a1, 31
+; RV64I-NEXT:    slli a1, a1, 31
 ; RV64I-NEXT:    slli a0, a0, 33
 ; RV64I-NEXT:    srli a0, a0, 33
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.copysign.f32(float %a, float %b)
   ret float %1
 }
 

llvm/test/CodeGen/RISCV/half-arith.ll

 ;
 ; RV64IZFH-LABEL: fsgnj_s:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fsgnj.h fa0, fa0, fa1
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fsgnj_s:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a2, 1048568
-; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    srli a1, a1, 15
+; RV32I-NEXT:    slli a1, a1, 15
 ; RV32I-NEXT:    slli a0, a0, 17
 ; RV32I-NEXT:    srli a0, a0, 17
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fsgnj_s:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a2, 1048568
-; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    srli a1, a1, 15
+; RV64I-NEXT:    slli a1, a1, 15
 ; RV64I-NEXT:    slli a0, a0, 49
 ; RV64I-NEXT:    srli a0, a0, 49
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = call half @llvm.copysign.f16(half %a, half %b)
   ret half %1
 }
 

 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    call __truncsfhf2@plt
 ; RV32I-NEXT:    and a0, a0, s3
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    call __truncsfhf2@plt
-; RV32I-NEXT:    lui a1, 1048568
-; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    srli a0, a0, 15
+; RV32I-NEXT:    slli a0, a0, 15
 ; RV32I-NEXT:    slli a1, s1, 17
 ; RV32I-NEXT:    srli a1, a1, 17
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __addsf3@plt
 ; RV64I-NEXT:    call __truncsfhf2@plt
 ; RV64I-NEXT:    and a0, a0, s3
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    lui a1, 524288
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    call __truncsfhf2@plt
-; RV64I-NEXT:    lui a1, 1048568
-; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    srli a0, a0, 15
+; RV64I-NEXT:    slli a0, a0, 15
 ; RV64I-NEXT:    slli a1, s1, 49
 ; RV64I-NEXT:    srli a1, a1, 49
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload

llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll

 ; DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN will convert to bitwise
 ; operations if half precision floating point isn't supported. A combine could
 ; be written to do the same even when f16 is legal.
 
 define half @fcopysign_fneg(half %a, half %b) nounwind {
 ; RV32I-LABEL: fcopysign_fneg:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    not a1, a1
-; RV32I-NEXT:    lui a2, 1048568
-; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    slli a0, a0, 17
 ; RV32I-NEXT:    srli a0, a0, 17
+; RV32I-NEXT:    srli a1, a1, 15
+; RV32I-NEXT:    slli a1, a1, 15
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IZFH-LABEL: fcopysign_fneg:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, a1
 ; RV32IZFH-NEXT:    fmv.h.x ft1, a0
 ; RV32IZFH-NEXT:    fsgnjn.h ft0, ft1, ft0
 ; RV32IZFH-NEXT:    fmv.x.h a0, ft0
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64I-LABEL: fcopysign_fneg:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    not a1, a1
-; RV64I-NEXT:    lui a2, 1048568
-; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    slli a0, a0, 49
 ; RV64I-NEXT:    srli a0, a0, 49
+; RV64I-NEXT:    srli a1, a1, 15
+; RV64I-NEXT:    slli a1, a1, 15
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcopysign_fneg:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, a1
 ; RV64IZFH-NEXT:    fmv.h.x ft1, a0
 ; RV64IZFH-NEXT:    fsgnjn.h ft0, ft1, ft0
 ; RV64IZFH-NEXT:    fmv.x.h a0, ft0
 ; RV64IZFH-NEXT:    ret
   %1 = fneg half %b
   %2 = call half @llvm.copysign.f16(half %a, half %1)
   ret half %2
 }

llvm/test/CodeGen/RISCV/half-intrinsics.ll

 ;
 ; RV64IDZFH-LABEL: copysign_f16:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fsgnj.h fa0, fa0, fa1
 ; RV64IDZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: copysign_f16:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a2, 1048568
-; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    srli a1, a1, 15
+; RV32I-NEXT:    slli a1, a1, 15
 ; RV32I-NEXT:    slli a0, a0, 17
 ; RV32I-NEXT:    srli a0, a0, 17
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: copysign_f16:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a2, 1048568
-; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    srli a1, a1, 15
+; RV64I-NEXT:    slli a1, a1, 15
 ; RV64I-NEXT:    slli a0, a0, 49
 ; RV64I-NEXT:    srli a0, a0, 49
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = call half @llvm.copysign.f16(half %a, half %b)
   ret half %1
 }
 

llvm/test/CodeGen/RISCV/rem.ll

 }
 
 define i32 @srem_pow2_2(i32 %a) nounwind {
 ; RV32I-LABEL: srem_pow2_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srai a1, a0, 31
 ; RV32I-NEXT:    srli a1, a1, 16
 ; RV32I-NEXT:    add a1, a0, a1
-; RV32I-NEXT:    lui a2, 1048560
-; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    srli a1, a1, 16
+; RV32I-NEXT:    slli a1, a1, 16
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: srem_pow2_2:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    srai a1, a0, 31
 ; RV32IM-NEXT:    srli a1, a1, 16
 ; RV32IM-NEXT:    add a1, a0, a1
-; RV32IM-NEXT:    lui a2, 1048560
-; RV32IM-NEXT:    and a1, a1, a2
+; RV32IM-NEXT:    srli a1, a1, 16
+; RV32IM-NEXT:    slli a1, a1, 16
 ; RV32IM-NEXT:    sub a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: srem_pow2_2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sraiw a1, a0, 31
 ; RV64I-NEXT:    srliw a1, a1, 16
 ; RV64I-NEXT:    add a1, a0, a1
-; RV64I-NEXT:    lui a2, 1048560
-; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    srli a1, a1, 16
+; RV64I-NEXT:    slli a1, a1, 16
 ; RV64I-NEXT:    subw a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: srem_pow2_2:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    sraiw a1, a0, 31
 ; RV64IM-NEXT:    srliw a1, a1, 16
 ; RV64IM-NEXT:    add a1, a0, a1
-; RV64IM-NEXT:    lui a2, 1048560
-; RV64IM-NEXT:    and a1, a1, a2
+; RV64IM-NEXT:    srli a1, a1, 16
+; RV64IM-NEXT:    slli a1, a1, 16
 ; RV64IM-NEXT:    subw a0, a0, a1
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %a, 65536
   ret i32 %1
 }
 
 define i32 @srem_constant_lhs(i32 %a) nounwind {
 ; RV32I-LABEL: srem_constant_lhs:

llvm/test/CodeGen/RISCV/rv32zbp.ll

; RV32ZBP-NEXT:    ret
   %or3 = or i64 %and1, %or
   ret i64 %or3
 }
 
 define i32 @packu_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: packu_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a0, a0, 16
-; RV32I-NEXT:    lui a2, 1048560
-; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    srli a1, a1, 16
+; RV32I-NEXT:    slli a1, a1, 16
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: packu_i32:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    packu a0, a0, a1
 ; RV32ZBP-NEXT:    ret
   %shr = lshr i32 %a, 16

llvm/test/CodeGen/RISCV/rv64zbp.ll

; RV64ZBP-NEXT:    ret
   %or3 = or i64 %or, %and2
   ret i64 %or3
 }
 
 define signext i32 @packu_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: packu_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srliw a0, a0, 16
-; RV64I-NEXT:    lui a2, 1048560
-; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    srli a1, a1, 16
+; RV64I-NEXT:    slli a1, a1, 16
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: packu_i32:
 ; RV64ZBP:       # %bb.0:
 ; RV64ZBP-NEXT:    packuw a0, a0, a1
 ; RV64ZBP-NEXT:    ret
   %shr = lshr i32 %a, 16
   %shr1 = and i32 %b, -65536
   %or = or i32 %shr1, %shr
   ret i32 %or
 }
 
 define i64 @packu_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: packu_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    li a2, -1
-; RV64I-NEXT:    slli a2, a2, 32
-; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    srli a1, a1, 32
+; RV64I-NEXT:    slli a1, a1, 32
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: packu_i64:
 ; RV64ZBP:       # %bb.0:
 ; RV64ZBP-NEXT:    packu a0, a0, a1
 ; RV64ZBP-NEXT:    ret
   %shr = lshr i64 %a, 32

llvm/test/CodeGen/RISCV/shift-and.ll

 
 define i64 @test4(i64 %x) {
 ; RV32I-LABEL: test4:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a2, a1, 26
 ; RV32I-NEXT:    srli a0, a0, 6
 ; RV32I-NEXT:    or a0, a0, a2
 ; RV32I-NEXT:    srli a1, a1, 6
-; RV32I-NEXT:    lui a2, 1048572
-; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    srli a0, a0, 14
+; RV32I-NEXT:    slli a0, a0, 14
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test4:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srli a0, a0, 20
 ; RV64I-NEXT:    slli a0, a0, 14
 ; RV64I-NEXT:    ret
   %a = lshr i64 %x, 6
   %b = and i64 %a, 288230376151695360
   ret i64 %b
 }
 
 define i32 @test5(i32 %x) {
 ; RV32I-LABEL: test5:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a0, a0, 10
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test5:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slliw a0, a0, 6
-; RV64I-NEXT:    lui a1, 1048560
-; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    srli a0, a0, 16
+; RV64I-NEXT:    slli a0, a0, 16
 ; RV64I-NEXT:    ret
   %a = shl i32 %x, 6
   %b = and i32 %a, -65536
   ret i32 %b
 }
 
 define i64 @test6(i64 %x) {
 ; RV32I-LABEL: test6:

llvm/test/CodeGen/RISCV/srem-lkk.ll

 
 ; Don't fold if the divisor is 2^31.
 define i32 @dont_fold_srem_i32_smax(i32 %x) nounwind {
 ; RV32I-LABEL: dont_fold_srem_i32_smax:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srai a1, a0, 31
 ; RV32I-NEXT:    srli a1, a1, 1
 ; RV32I-NEXT:    add a1, a0, a1
-; RV32I-NEXT:    lui a2, 524288
-; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    srli a1, a1, 31
+; RV32I-NEXT:    slli a1, a1, 31
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_srem_i32_smax:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    srai a1, a0, 31
 ; RV32IM-NEXT:    srli a1, a1, 1
 ; RV32IM-NEXT:    add a1, a0, a1
-; RV32IM-NEXT:    lui a2, 524288
-; RV32IM-NEXT:    and a1, a1, a2
+; RV32IM-NEXT:    srli a1, a1, 31
+; RV32IM-NEXT:    slli a1, a1, 31
 ; RV32IM-NEXT:    add a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_srem_i32_smax:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sraiw a1, a0, 31
 ; RV64I-NEXT:    srliw a1, a1, 1
 ; RV64I-NEXT:    add a1, a0, a1
-; RV64I-NEXT:    lui a2, 524288
-; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    srli a1, a1, 31
+; RV64I-NEXT:    slli a1, a1, 31
 ; RV64I-NEXT:    addw a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_srem_i32_smax:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    sraiw a1, a0, 31
 ; RV64IM-NEXT:    srliw a1, a1, 1
 ; RV64IM-NEXT:    add a1, a0, a1
-; RV64IM-NEXT:    lui a2, 524288
-; RV64IM-NEXT:    and a1, a1, a2
+; RV64IM-NEXT:    srli a1, a1, 31
+; RV64IM-NEXT:    slli a1, a1, 31
 ; RV64IM-NEXT:    addw a0, a0, a1
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %x, 2147483648
   ret i32 %1
 }
 
 ; Don't fold i64 srem
 define i64 @dont_fold_srem_i64(i64 %x) nounwind {