[Mips] support "sp" named register

[nickdesaulniers]

Summary

After Linux kernel commit
commit 200ed341b864 ("mips: Implement "current_stack_pointer"")
We observe the following build error when compiling the Linux kernel
targeting Mips:
fatal error: error in backend: Invalid register name global variable

Fixes: https://github.com/llvm/llvm-project/issues/54174
Link: https://github.com/ClangBuiltLinux/linux/issues/1608

[nathanchance]

I can build malta_defconfig on next-20220303 with this patch. I enabled CONFIG_DEBUG_STACKOVERFLOW and CONFIG_HARDENED_USERCOPY, which both use current_stack_pointer, and did not see any warnings/errors.

llvm/test/CodeGen/Mips/named-register-n64.ll

26

Should this be !llvm.named.register.$sp = !{!1}?

[atanasyan]

Do you have commit access?

[nickdesaulniers]

• fix named register metadata in n64 test, as per @nathanchance

[nickdesaulniers]

In D120926#3358183, @atanasyan wrote:

Do you have commit access?

Yep.

In D120926#3358178, @nathanchance wrote:

I can build malta_defconfig on next-20220303 with this patch. I enabled CONFIG_DEBUG_STACKOVERFLOW and CONFIG_HARDENED_USERCOPY, which both use current_stack_pointer, and did not see any warnings/errors.

I appreciate it!

llvm/test/CodeGen/Mips/named-register-n64.ll

26

Yes; good catch.

llvm/lib/Target/Mips/MipsISelLowering.cpp

MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
   return BB;
 }
 
 // FIXME? Maybe this could be a TableGen attribute on some registers and
 // this table could be generated automatically from RegInfo.
 Register
 MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT,
                                       const MachineFunction &MF) const {
-  // Named registers is expected to be fairly rare. For now, just support $28
-  // since the linux kernel uses it.
+  // The Linux kernel uses $28 and sp.
   if (Subtarget.isGP64bit()) {
     Register Reg = StringSwitch<Register>(RegName)
-                         .Case("$28", Mips::GP_64)
-                         .Default(Register());
+                       .Case("sp", Mips::SP_64)
     if (Reg)
       return Reg;
   } else {
     Register Reg = StringSwitch<Register>(RegName)
-                         .Case("$28", Mips::GP)
-                         .Default(Register());
+                       .Case("sp", Mips::SP)
     if (Reg)
       return Reg;
   }
   report_fatal_error("Invalid register name global variable");
 }
 
 MachineBasicBlock *MipsTargetLowering::emitLDR_W(MachineInstr &MI,
                                                  MachineBasicBlock *BB) const {

llvm/test/CodeGen/Mips/named-register-n32.ll

-; RUN: llc -mtriple=mips64 -relocation-model=static -mattr=+noabicalls -target-abi n32 < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips64 -relocation-model=static -mattr=+noabicalls \
+; RUN:   -target-abi n32 < %s | FileCheck %s
 
-define i32* @get_gp() {
-entry:
-  %0 = call i64 @llvm.read_register.i64(metadata !0)
-  %1 = trunc i64 %0 to i32
-  %2 = inttoptr i32 %1 to i32*
-  ret i32* %2
-}
+declare i64 @llvm.read_register.i64(metadata)
 
+define i64 @get_gp() {
 ; CHECK-LABEL: get_gp:
-; CHECK:           sll $2, $gp, 0
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    move $2, $gp
+  %1 = call i64 @llvm.read_register.i64(metadata !0)
+  ret i64 %1
+}
 
-declare i64 @llvm.read_register.i64(metadata)
+define i64 @get_sp() {
+; CHECK-LABEL: get_sp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    move $2, $sp
+  %1 = call i64 @llvm.read_register.i64(metadata !1)
+  ret i64 %1
+}
 
 !llvm.named.register.$28 = !{!0}
+!llvm.named.register.sp = !{!1}
 
 !0 = !{!"$28"}
+!1 = !{!"sp"}

llvm/test/CodeGen/Mips/named-register-n64.ll

-; RUN: llc -mtriple=mips64 -relocation-model=static -mattr=+noabicalls < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips64 -relocation-model=static -mattr=+noabicalls \
+; RUN:   < %s | FileCheck %s
 
-define i32* @get_gp() {
-entry:
-  %0 = call i64 @llvm.read_register.i64(metadata !0)
-  %1 = inttoptr i64 %0 to i32*
-  ret i32* %1
-}
+declare i64 @llvm.read_register.i64(metadata)
 
+define i64 @get_gp() {
 ; CHECK-LABEL: get_gp:
-; CHECK:           move $2, $gp
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    move $2, $gp
+  %1 = call i64 @llvm.read_register.i64(metadata !0)
+  ret i64 %1
+}
 
-declare i64 @llvm.read_register.i64(metadata)
+define i64 @get_sp() {
+; CHECK-LABEL: get_sp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    move $2, $sp
+  %1 = call i64 @llvm.read_register.i64(metadata !1)
+  ret i64 %1
+}
 
 !llvm.named.register.$28 = !{!0}
+!llvm.named.register.sp = !{!1}
 
 !0 = !{!"$28"}
+!1 = !{!"sp"}

llvm/test/CodeGen/Mips/named-register-o32.ll

-; RUN: llc -mtriple=mips -relocation-model=static -mattr=+noabicalls < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips -relocation-model=static -mattr=+noabicalls \
+; RUN:   < %s | FileCheck %s
 
-define i32* @get_gp() {
-entry:
-  %0 = call i32 @llvm.read_register.i32(metadata !0)
-  %1 = inttoptr i32 %0 to i32*
-  ret i32* %1
-}
+declare i32 @llvm.read_register.i32(metadata)
 
+define i32 @get_gp() {
 ; CHECK-LABEL: get_gp:
-; CHECK:           move $2, $gp
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    move $2, $gp
+  %1 = call i32 @llvm.read_register.i32(metadata !0)
+  ret i32 %1
+}
 
-declare i32 @llvm.read_register.i32(metadata)
+define i32 @get_sp() {
+; CHECK-LABEL: get_sp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    move $2, $sp
+  %1 = call i32 @llvm.read_register.i32(metadata !1)
+  ret i32 %1
+}
 
 !llvm.named.register.$28 = !{!0}
+!llvm.named.register.sp = !{!1}
 
 !0 = !{!"$28"}
+!1 = !{!"sp"}