[AArch64] Use simd mov to materialize big fp constants

[Allen]

Summary

mov w8, #1325400064 + fmov s0, w8 ==> movi v0.2s, 0x4f, lsl 24

Fix https://github.com/llvm/llvm-project/issues/53651

[Allen]

This comment was removed by Allen.

[Allen]

fix precommit format

[dmgreen]

Using the MOVI to materialize fp constants sounds like a good idea.

But I don't think this should be starting from a CopyToReg. CopyToReg usually means we are copying the result into the return value of a function (or into a call argument). Copying into s0 for example. CopyFromReg is used to get the value from input physical registers from arguments.

An example like this, with fadd, would preferably use the movi lowering too: https://godbolt.org/z/bc99E85qz

If the FPConstant is still in the DAG at the point that we run instruction selection (I think it should be but it may be dependant on what AArch64TargetLowering::isFPImmLegal returns), then it may be best to add a tablegen pattern for cases that we can materialize with the integer movi instruction. From here: https://github.com/llvm/llvm-project/blob/ecff9b65b54c7a4bd79ca2af157c81595678f0ee/llvm/lib/Target/AArch64/AArch64InstrInfo.td#L1545, with a different fpimm to limit it to cases where the MOVi can be generated, and an EXTRACT_SUBREG to get the s reg. If that doesn't work (the custom ImmLeaf's might be a bit much) then perhaps something in AArch64ISelDAGToDAG.cpp?

[Allen]

In D120452#3343727, @dmgreen wrote:

Using the MOVI to materialize fp constants sounds like a good idea.

Thanks very much for detail, refactor with above new method.

[Allen]

update test cases

[fhahn]

llvm/test/Transforms/LoopVectorize/AArch64/remat-const-float-simd.ll

2 ↗

(On Diff #411754)

It looks like the test is completely unrelated to the loop-vectorize pass. It should probably be either moved to CodeGen/AArch64/ or added to one of the existing tests there.

[dmgreen]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

1210

This likely doesn't need to be an Operand, it can just be a FPImmLeaf

llvm/lib/Target/AArch64/AArch64InstrInfo.td

1551

This doesn't need to define a new instruction, it can use the existing MOVI (which I believe is probably called MOVIv2i32?)

llvm/test/Transforms/LoopVectorize/AArch64/remat-const-float-simd.ll

1 ↗

(On Diff #411754)

This test file should be in CodeGen/AArch64

[Allen]

a) move case remat-const-float-simd.ll to CodeGen/AArch64
b) use MOVIv2i32 , and delete unneeded instruction MOVI2s_ns
c) delete Operand<f32>, and just be a FPImmLeaf

[Allen]

In D120452#3348692, @Allen wrote:

a) move case remat-const-float-simd.ll to CodeGen/AArch64
b) use MOVIv2i32 , and delete unneeded instruction MOVI2s_ns
c) delete Operand<f32>, and just be a FPImmLeaf

Address all comment

llvm/lib/Target/AArch64/AArch64InstrFormats.td

1210

Yes, verified ok!

llvm/lib/Target/AArch64/AArch64InstrInfo.td

1551

It's strange that here error with the following info, as it is ok on my local linux ?

AArch64InstrInfo.td:1551:1: error: Type set is empty for each HW mode in 'MOVIv2s_ns' def MOVIv2s_ns : BaseSIMDModifiedImmVectorShift<1, 1, 0b10, V128, "movi", ".2s",

1551

Thanks, delete unneeded instruction MOVI2s_ns

[Allen]

ping ?

[dmgreen]

Thanks for the updates. There are other forms of MOVI that might also be useful for some fp immediates. The one we have here (shift an i8 by 24) I imagine is the most useful, but the others could be good in places too. The MOVN's too. I'm not sure what the best way to generalise this would be. As far as I can tell it needs lots of checks to the various isAdvSIMDModImmTypeXYZ methods wherever it is? This seems like a good beginning at least.

llvm/lib/Target/AArch64/AArch64InstrFormats.td

1210

It's likely worth calling this out as a "AdvSIMDModImmType4" constant somehow. Maybe call it fpimm32SIMDModImmType4? Same for the XForm.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

6146

It is quite uncommon to not have NEON, but can you add a predicate for it:

let Predicates = [HasNEON] in {

It might be worth adding a run line without neon (-mattr=-neon) for the new remat test case too, to show the difference.

llvm/test/CodeGen/AArch64/remat-const-float-simd.ll

7

0x7fffffff -> 2147483648, as the 0x7fffffff gets rounded.

[Allen]

update testcase 0x7fffffff with 2147483648 as gets rounded

[dmgreen]

Thanks. LGTM

llvm/lib/Target/AArch64/AArch64InstrFormats.td

def fpimm16XForm : SDNodeXForm<fpimm, [{
     }]>;
 
 def fpimm32XForm : SDNodeXForm<fpimm, [{
       APFloat InVal = N->getValueAPF();
       uint32_t enc = AArch64_AM::getFP32Imm(InVal);
       return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
     }]>;
 
+def fpimm32SimdXForm : SDNodeXForm<fpimm, [{
+      uint32_t enc = AArch64_AM::encodeAdvSIMDModImmType4(N->getValueAPF()
+                                                          .bitcastToAPInt()
+                                                          .getZExtValue());
+      return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
+    }]>;
+
 def fpimm64XForm : SDNodeXForm<fpimm, [{
       APFloat InVal = N->getValueAPF();
       uint32_t enc = AArch64_AM::getFP64Imm(InVal);
       return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
     }]>;
 
 def fpimm16 : Operand<f16>,
               FPImmLeaf<f16, [{
       return AArch64_AM::getFP16Imm(Imm) != -1;
     }], fpimm16XForm> {
   let ParserMatchClass = FPImmOperand;
   let PrintMethod = "printFPImmOperand";
 }
 
 def fpimm32 : Operand<f32>,
               FPImmLeaf<f32, [{
       return AArch64_AM::getFP32Imm(Imm) != -1;
     }], fpimm32XForm> {
   let ParserMatchClass = FPImmOperand;
   let PrintMethod = "printFPImmOperand";
 }
+
+def fpimm32Simd : FPImmLeaf<f32, [{
+      uint64_t Enc = Imm.bitcastToAPInt().getZExtValue();
+      return Enc != 0 && AArch64_AM::isAdvSIMDModImmType4(Enc << 32 | Enc);
+    }], fpimm32SimdXForm> {
+}
+
 def fpimm64 : Operand<f64>,
               FPImmLeaf<f64, [{
       return AArch64_AM::getFP64Imm(Imm) != -1;
     }], fpimm64XForm> {
   let ParserMatchClass = FPImmOperand;
   let PrintMethod = "printFPImmOperand";
 }
 

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 
 
 def : Pat<(f32 fpimm:$in),
   (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
 def : Pat<(f64 fpimm:$in),
   (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
 
 
 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
 // sequences.
 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
                              tglobaladdr:$g1, tglobaladdr:$g0),
           (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g0, 0),
                                   tglobaladdr:$g1, 16),
                           tglobaladdr:$g2, 32),
                   tglobaladdr:$g3, 48)>;
 

 def : Pat<(v2i32 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>;
 def : Pat<(v4i16 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>;
 def : Pat<(v8i8  immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>;
 
 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 defm MOVI      : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
 
+// Using the MOVI to materialize fp constants.
+def : Pat<(f32 fpimm32Simd:$in),
+          (EXTRACT_SUBREG (MOVIv2i32 (fpimm32SimdXForm f32:$in), (i32 24)),
+                          ssub)>;
+
 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd,  imm0_255:$imm, 0), 0>;
 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd,  imm0_255:$imm, 0), 0>;
 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
 
 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd,  imm0_255:$imm, 0), 0>;
 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd,  imm0_255:$imm, 0), 0>;

llvm/test/CodeGen/AArch64/fabs.ll

; CHECK-NEXT:    ret
   ret double %cond
 }
 
 ; Try again with different type, predicate, and compare constant.
 
 define float @still_not_fabs(float %x) #0 {
 ; CHECK-LABEL: still_not_fabs:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-2147483648
+; CHECK-NEXT:    movi v1.2s, #128, lsl #24
 ; CHECK-NEXT:    fneg s2, s0
-; CHECK-NEXT:    fmov s1, w8
 ; CHECK-NEXT:    fcmp s0, s1
 ; CHECK-NEXT:    fcsel s0, s0, s2, ge
 ; CHECK-NEXT:    ret
   %cmp = fcmp nnan oge float %x, -0.0
   %sub = fsub nnan float -0.0, %x
   %cond = select i1 %cmp, float %x, float %sub
   ret float %cond
 }

llvm/test/CodeGen/AArch64/fcvt-fixed.ll

; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 18446744073709551616.0
   %cvt = fptosi double %fix to i64
   ret i64 %cvt
 }
 
 define i32 @fcvtzs_f16_i32_7(half %flt) {
 ; CHECK-NO16-LABEL: fcvtzs_f16_i32_7:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    mov w8, #1124073472
+; CHECK-NO16-NEXT:    movi v1.2s, #67, lsl #24
 ; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzs w0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzs_f16_i32_7:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs w0, h0, #7
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %flt, 128.0
   %cvt = fptosi half %fix to i32
   ret i32 %cvt
 }
 
 define i32 @fcvtzs_f16_i32_15(half %flt) {
 ; CHECK-NO16-LABEL: fcvtzs_f16_i32_15:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    mov w8, #1191182336
+; CHECK-NO16-NEXT:    movi v1.2s, #71, lsl #24
 ; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzs w0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzs_f16_i32_15:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs w0, h0, #15
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %flt, 32768.0
   %cvt = fptosi half %fix to i32
   ret i32 %cvt
 }
 
 define i64 @fcvtzs_f16_i64_7(half %flt) {
 ; CHECK-NO16-LABEL: fcvtzs_f16_i64_7:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    mov w8, #1124073472
+; CHECK-NO16-NEXT:    movi v1.2s, #67, lsl #24
 ; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzs x0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzs_f16_i64_7:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs x0, h0, #7
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %flt, 128.0
   %cvt = fptosi half %fix to i64
   ret i64 %cvt
 }
 
 define i64 @fcvtzs_f16_i64_15(half %flt) {
 ; CHECK-NO16-LABEL: fcvtzs_f16_i64_15:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    mov w8, #1191182336
+; CHECK-NO16-NEXT:    movi v1.2s, #71, lsl #24
 ; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzs x0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzs_f16_i64_15:
 ; CHECK-FP16:       // %bb.0:
; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 18446744073709551616.0
   %cvt = fptoui double %fix to i64
   ret i64 %cvt
 }
 
 define i32 @fcvtzu_f16_i32_7(half %flt) {
 ; CHECK-NO16-LABEL: fcvtzu_f16_i32_7:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    mov w8, #1124073472
+; CHECK-NO16-NEXT:    movi v1.2s, #67, lsl #24
 ; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzu w0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzu_f16_i32_7:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzu w0, h0, #7
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %flt, 128.0
   %cvt = fptoui half %fix to i32
   ret i32 %cvt
 }
 
 define i32 @fcvtzu_f16_i32_15(half %flt) {
 ; CHECK-NO16-LABEL: fcvtzu_f16_i32_15:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    mov w8, #1191182336
+; CHECK-NO16-NEXT:    movi v1.2s, #71, lsl #24
 ; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzu w0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzu_f16_i32_15:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzu w0, h0, #15
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %flt, 32768.0
   %cvt = fptoui half %fix to i32
   ret i32 %cvt
 }
 
 define i64 @fcvtzu_f16_i64_7(half %flt) {
 ; CHECK-NO16-LABEL: fcvtzu_f16_i64_7:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    mov w8, #1124073472
+; CHECK-NO16-NEXT:    movi v1.2s, #67, lsl #24
 ; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzu x0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzu_f16_i64_7:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzu x0, h0, #7
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %flt, 128.0
   %cvt = fptoui half %fix to i64
   ret i64 %cvt
 }
 
 define i64 @fcvtzu_f16_i64_15(half %flt) {
 ; CHECK-NO16-LABEL: fcvtzu_f16_i64_15:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    mov w8, #1191182336
+; CHECK-NO16-NEXT:    movi v1.2s, #71, lsl #24
 ; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzu x0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzu_f16_i64_15:
 ; CHECK-FP16:       // %bb.0:
; CHECK-NEXT:    ret
   %cvt = sitofp i64 %long to double
   %fix = fdiv double %cvt, 18446744073709551616.0
   ret double %fix
 }
 
 define half @scvtf_f16_i32_7(i32 %int) {
 ; CHECK-NO16-LABEL: scvtf_f16_i32_7:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    scvtf s0, w0
-; CHECK-NO16-NEXT:    mov w8, #1124073472
-; CHECK-NO16-NEXT:    fmov s1, w8
-; CHECK-NO16-NEXT:    fcvt h0, s0
-; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fdiv s0, s0, s1
+; CHECK-NO16-NEXT:    scvtf s1, w0
+; CHECK-NO16-NEXT:    movi v0.2s, #67, lsl #24
+; CHECK-NO16-NEXT:    fcvt h1, s1
+; CHECK-NO16-NEXT:    fcvt s1, h1
+; CHECK-NO16-NEXT:    fdiv s0, s1, s0
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: scvtf_f16_i32_7:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    scvtf h0, w0, #7
 ; CHECK-FP16-NEXT:    ret
   %cvt = sitofp i32 %int to half
   %fix = fdiv half %cvt, 128.0
   ret half %fix
 }
 
 define half @scvtf_f16_i32_15(i32 %int) {
 ; CHECK-NO16-LABEL: scvtf_f16_i32_15:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    scvtf s0, w0
-; CHECK-NO16-NEXT:    mov w8, #1191182336
-; CHECK-NO16-NEXT:    fmov s1, w8
-; CHECK-NO16-NEXT:    fcvt h0, s0
-; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fdiv s0, s0, s1
+; CHECK-NO16-NEXT:    scvtf s1, w0
+; CHECK-NO16-NEXT:    movi v0.2s, #71, lsl #24
+; CHECK-NO16-NEXT:    fcvt h1, s1
+; CHECK-NO16-NEXT:    fcvt s1, h1
+; CHECK-NO16-NEXT:    fdiv s0, s1, s0
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: scvtf_f16_i32_15:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    scvtf h0, w0, #15
 ; CHECK-FP16-NEXT:    ret
   %cvt = sitofp i32 %int to half
   %fix = fdiv half %cvt, 32768.0
   ret half %fix
 }
 
 define half @scvtf_f16_i64_7(i64 %long) {
 ; CHECK-NO16-LABEL: scvtf_f16_i64_7:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    scvtf s0, x0
-; CHECK-NO16-NEXT:    mov w8, #1124073472
-; CHECK-NO16-NEXT:    fmov s1, w8
-; CHECK-NO16-NEXT:    fcvt h0, s0
-; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fdiv s0, s0, s1
+; CHECK-NO16-NEXT:    scvtf s1, x0
+; CHECK-NO16-NEXT:    movi v0.2s, #67, lsl #24
+; CHECK-NO16-NEXT:    fcvt h1, s1
+; CHECK-NO16-NEXT:    fcvt s1, h1
+; CHECK-NO16-NEXT:    fdiv s0, s1, s0
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: scvtf_f16_i64_7:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    scvtf h0, x0, #7
 ; CHECK-FP16-NEXT:    ret
   %cvt = sitofp i64 %long to half
   %fix = fdiv half %cvt, 128.0
   ret half %fix
 }
 
 define half @scvtf_f16_i64_15(i64 %long) {
 ; CHECK-NO16-LABEL: scvtf_f16_i64_15:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    scvtf s0, x0
-; CHECK-NO16-NEXT:    mov w8, #1191182336
-; CHECK-NO16-NEXT:    fmov s1, w8
-; CHECK-NO16-NEXT:    fcvt h0, s0
-; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fdiv s0, s0, s1
+; CHECK-NO16-NEXT:    scvtf s1, x0
+; CHECK-NO16-NEXT:    movi v0.2s, #71, lsl #24
+; CHECK-NO16-NEXT:    fcvt h1, s1
+; CHECK-NO16-NEXT:    fcvt s1, h1
+; CHECK-NO16-NEXT:    fdiv s0, s1, s0
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: scvtf_f16_i64_15:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    scvtf h0, x0, #15
 ; CHECK-FP16-NEXT:    ret
   %cvt = sitofp i64 %long to half
; CHECK-NEXT:    ret
   %cvt = uitofp i64 %long to double
   %fix = fdiv double %cvt, 18446744073709551616.0
   ret double %fix
 }
 
 define half @ucvtf_f16_i32_7(i32 %int) {
 ; CHECK-NO16-LABEL: ucvtf_f16_i32_7:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    ucvtf s0, w0
-; CHECK-NO16-NEXT:    mov w8, #1124073472
-; CHECK-NO16-NEXT:    fmov s1, w8
-; CHECK-NO16-NEXT:    fcvt h0, s0
-; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fdiv s0, s0, s1
+; CHECK-NO16-NEXT:    ucvtf s1, w0
+; CHECK-NO16-NEXT:    movi v0.2s, #67, lsl #24
+; CHECK-NO16-NEXT:    fcvt h1, s1
+; CHECK-NO16-NEXT:    fcvt s1, h1
+; CHECK-NO16-NEXT:    fdiv s0, s1, s0
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: ucvtf_f16_i32_7:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    ucvtf h0, w0, #7
 ; CHECK-FP16-NEXT:    ret
   %cvt = uitofp i32 %int to half
   %fix = fdiv half %cvt, 128.0
   ret half %fix
 }
 
 define half @ucvtf_f16_i32_15(i32 %int) {
 ; CHECK-NO16-LABEL: ucvtf_f16_i32_15:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    ucvtf s0, w0
-; CHECK-NO16-NEXT:    mov w8, #1191182336
-; CHECK-NO16-NEXT:    fmov s1, w8
-; CHECK-NO16-NEXT:    fcvt h0, s0
-; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fdiv s0, s0, s1
+; CHECK-NO16-NEXT:    ucvtf s1, w0
+; CHECK-NO16-NEXT:    movi v0.2s, #71, lsl #24
+; CHECK-NO16-NEXT:    fcvt h1, s1
+; CHECK-NO16-NEXT:    fcvt s1, h1
+; CHECK-NO16-NEXT:    fdiv s0, s1, s0
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: ucvtf_f16_i32_15:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    ucvtf h0, w0, #15
 ; CHECK-FP16-NEXT:    ret
   %cvt = uitofp i32 %int to half
   %fix = fdiv half %cvt, 32768.0
   ret half %fix
 }
 
 define half @ucvtf_f16_i64_7(i64 %long) {
 ; CHECK-NO16-LABEL: ucvtf_f16_i64_7:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    ucvtf s0, x0
-; CHECK-NO16-NEXT:    mov w8, #1124073472
-; CHECK-NO16-NEXT:    fmov s1, w8
-; CHECK-NO16-NEXT:    fcvt h0, s0
-; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fdiv s0, s0, s1
+; CHECK-NO16-NEXT:    ucvtf s1, x0
+; CHECK-NO16-NEXT:    movi v0.2s, #67, lsl #24
+; CHECK-NO16-NEXT:    fcvt h1, s1
+; CHECK-NO16-NEXT:    fcvt s1, h1
+; CHECK-NO16-NEXT:    fdiv s0, s1, s0
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: ucvtf_f16_i64_7:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    ucvtf h0, x0, #7
 ; CHECK-FP16-NEXT:    ret
   %cvt = uitofp i64 %long to half
   %fix = fdiv half %cvt, 128.0
   ret half %fix
 }
 
 define half @ucvtf_f16_i64_15(i64 %long) {
 ; CHECK-NO16-LABEL: ucvtf_f16_i64_15:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    ucvtf s0, x0
-; CHECK-NO16-NEXT:    mov w8, #1191182336
-; CHECK-NO16-NEXT:    fmov s1, w8
-; CHECK-NO16-NEXT:    fcvt h0, s0
-; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fdiv s0, s0, s1
+; CHECK-NO16-NEXT:    ucvtf s1, x0
+; CHECK-NO16-NEXT:    movi v0.2s, #71, lsl #24
+; CHECK-NO16-NEXT:    fcvt h1, s1
+; CHECK-NO16-NEXT:    fcvt s1, h1
+; CHECK-NO16-NEXT:    fdiv s0, s1, s0
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: ucvtf_f16_i64_15:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    ucvtf h0, x0, #15
 ; CHECK-FP16-NEXT:    ret
   %cvt = uitofp i64 %long to half
; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 18446744073709551616.0
   %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
   ret i64 %cvt
 }
 
 define i32 @fcvtzs_sat_f16_i32_7(half %dbl) {
 ; CHECK-NO16-LABEL: fcvtzs_sat_f16_i32_7:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    mov w8, #1124073472
+; CHECK-NO16-NEXT:    movi v1.2s, #67, lsl #24
 ; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzs w0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzs_sat_f16_i32_7:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs w0, h0, #7
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %dbl, 128.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix)
   ret i32 %cvt
 }
 
 define i32 @fcvtzs_sat_f16_i32_15(half %dbl) {
 ; CHECK-NO16-LABEL: fcvtzs_sat_f16_i32_15:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    mov w8, #1191182336
+; CHECK-NO16-NEXT:    movi v1.2s, #71, lsl #24
 ; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzs w0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzs_sat_f16_i32_15:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs w0, h0, #15
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %dbl, 32768.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix)
   ret i32 %cvt
 }
 
 define i64 @fcvtzs_sat_f16_i64_7(half %dbl) {
 ; CHECK-NO16-LABEL: fcvtzs_sat_f16_i64_7:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    mov w8, #1124073472
+; CHECK-NO16-NEXT:    movi v1.2s, #67, lsl #24
 ; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzs x0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzs_sat_f16_i64_7:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs x0, h0, #7
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %dbl, 128.0
   %cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix)
   ret i64 %cvt
 }
 
 define i64 @fcvtzs_sat_f16_i64_15(half %dbl) {
 ; CHECK-NO16-LABEL: fcvtzs_sat_f16_i64_15:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    mov w8, #1191182336
+; CHECK-NO16-NEXT:    movi v1.2s, #71, lsl #24
 ; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzs x0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzs_sat_f16_i64_15:
 ; CHECK-FP16:       // %bb.0:
; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 18446744073709551616.0
   %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
   ret i64 %cvt
 }
 
 define i32 @fcvtzu_sat_f16_i32_7(half %dbl) {
 ; CHECK-NO16-LABEL: fcvtzu_sat_f16_i32_7:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    mov w8, #1124073472
+; CHECK-NO16-NEXT:    movi v1.2s, #67, lsl #24
 ; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzu w0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzu_sat_f16_i32_7:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzu w0, h0, #7
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %dbl, 128.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix)
   ret i32 %cvt
 }
 
 define i32 @fcvtzu_sat_f16_i32_15(half %dbl) {
 ; CHECK-NO16-LABEL: fcvtzu_sat_f16_i32_15:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    mov w8, #1191182336
+; CHECK-NO16-NEXT:    movi v1.2s, #71, lsl #24
 ; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzu w0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzu_sat_f16_i32_15:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzu w0, h0, #15
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %dbl, 32768.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix)
   ret i32 %cvt
 }
 
 define i64 @fcvtzu_sat_f16_i64_7(half %dbl) {
 ; CHECK-NO16-LABEL: fcvtzu_sat_f16_i64_7:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    mov w8, #1124073472
+; CHECK-NO16-NEXT:    movi v1.2s, #67, lsl #24
 ; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzu x0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzu_sat_f16_i64_7:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzu x0, h0, #7
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %dbl, 128.0
   %cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix)
   ret i64 %cvt
 }
 
 define i64 @fcvtzu_sat_f16_i64_15(half %dbl) {
 ; CHECK-NO16-LABEL: fcvtzu_sat_f16_i64_15:
 ; CHECK-NO16:       // %bb.0:
-; CHECK-NO16-NEXT:    mov w8, #1191182336
+; CHECK-NO16-NEXT:    movi v1.2s, #71, lsl #24
 ; CHECK-NO16-NEXT:    fcvt s0, h0
-; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzu x0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzu_sat_f16_i64_15:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzu x0, h0, #15
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %dbl, 32768.0
   %cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix)
   ret i64 %cvt
 }

llvm/test/CodeGen/AArch64/fpimm.ll

 ; RUN: llc -mtriple=aarch64-linux-gnu                                                  -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large                             -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LARGE
+; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large                             -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LARGE
 ; RUN: llc -mtriple=aarch64-none-eabi    -code-model=tiny                              -verify-machineinstrs < %s | FileCheck %s
 
 @varf32 = global float 0.0
 @varf64 = global double 0.0
 
 define void @check_float() {
 ; CHECK-LABEL: check_float:
 
   %val = load float, float* @varf32
   %newval1 = fadd float %val, 8.5
   store volatile float %newval1, float* @varf32
 ; CHECK-DAG: fmov {{s[0-9]+}}, #8.5
 
   %newval2 = fadd float %val, 128.0
   store volatile float %newval2, float* @varf32
-; CHECK-DAG: mov [[W128:w[0-9]+]], #1124073472
-; CHECK-DAG: fmov {{s[0-9]+}}, [[W128]]
+; CHECK-DAG: movi [[REG:v[0-9s]+]].2s, #67, lsl #24
 
 ; CHECK: ret
   ret void
 }
 
 define void @check_double() {
 ; CHECK-LABEL: check_double:
 

llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll

 
 define i100 @test_signed_i100_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i100_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
 ; CHECK-NEXT:    fmov s8, s0
 ; CHECK-NEXT:    bl __fixsfti
-; CHECK-NEXT:    mov w8, #-251658240
+; CHECK-NEXT:    movi v0.2s, #241, lsl #24
+; CHECK-NEXT:    mov w8, #1895825407
 ; CHECK-NEXT:    mov x10, #34359738367
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov w8, #1895825407
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov x8, #-34359738368
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    csel x8, x8, x1, lt
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    csel x8, x10, x8, gt
 ; CHECK-NEXT:    csinv x9, x9, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    csel x0, xzr, x9, vs
 ; CHECK-NEXT:    csel x1, xzr, x8, vs
 ; CHECK-NEXT:    ldr d8, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
     %x = call i100 @llvm.fptosi.sat.i100.f32(float %f)
     ret i100 %x
 }
 
 define i128 @test_signed_i128_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i128_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
 ; CHECK-NEXT:    fmov s8, s0
 ; CHECK-NEXT:    bl __fixsfti
-; CHECK-NEXT:    mov w8, #-16777216
+; CHECK-NEXT:    movi v0.2s, #255, lsl #24
+; CHECK-NEXT:    mov w8, #2130706431
 ; CHECK-NEXT:    mov x10, #9223372036854775807
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov w8, #2130706431
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov x8, #-9223372036854775808
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    csel x8, x8, x1, lt
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    csel x8, x10, x8, gt
 ; CHECK-NEXT:    csinv x9, x9, xzr, le

 define i100 @test_signed_i100_f16(half %f) nounwind {
 ; CHECK-LABEL: test_signed_i100_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    fcvt s8, h0
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
-; CHECK-NEXT:    mov w8, #-251658240
+; CHECK-NEXT:    movi v0.2s, #241, lsl #24
+; CHECK-NEXT:    mov w8, #1895825407
 ; CHECK-NEXT:    mov x10, #34359738367
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov w8, #1895825407
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov x8, #-34359738368
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    csel x8, x8, x1, lt
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    csel x8, x10, x8, gt
 ; CHECK-NEXT:    csinv x9, x9, xzr, le

 define i128 @test_signed_i128_f16(half %f) nounwind {
 ; CHECK-LABEL: test_signed_i128_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    fcvt s8, h0
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
-; CHECK-NEXT:    mov w8, #-16777216
+; CHECK-NEXT:    movi v0.2s, #255, lsl #24
+; CHECK-NEXT:    mov w8, #2130706431
 ; CHECK-NEXT:    mov x10, #9223372036854775807
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov w8, #2130706431
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov x8, #-9223372036854775808
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    csel x8, x8, x1, lt
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    csel x8, x10, x8, gt
 ; CHECK-NEXT:    csinv x9, x9, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    csel x0, xzr, x9, vs
 ; CHECK-NEXT:    csel x1, xzr, x8, vs
 ; CHECK-NEXT:    ldr d8, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
     %x = call i128 @llvm.fptosi.sat.i128.f16(half %f)
     ret i128 %x
 }

llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

 ; CHECK-NEXT:    .cfi_offset b8, -48
 ; CHECK-NEXT:    .cfi_offset b9, -56
 ; CHECK-NEXT:    .cfi_offset b10, -64
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov s8, v0.s[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
-; CHECK-NEXT:    mov w8, #-251658240
+; CHECK-NEXT:    movi v9.2s, #241, lsl #24
+; CHECK-NEXT:    mov w8, #1895825407
 ; CHECK-NEXT:    mov x21, #-34359738368
 ; CHECK-NEXT:    mov x22, #34359738367
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-NEXT:    fmov s10, w8
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $q0
-; CHECK-NEXT:    fmov s9, w8
-; CHECK-NEXT:    mov w8, #1895825407
 ; CHECK-NEXT:    fcmp s8, s9
-; CHECK-NEXT:    fmov s10, w8
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x21, x1, lt
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    csel x9, x22, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    csel x19, xzr, x8, vs
 ; CHECK-NEXT:    csel x20, xzr, x9, vs

 ; CHECK-NEXT:    .cfi_offset b8, -48
 ; CHECK-NEXT:    .cfi_offset b9, -56
 ; CHECK-NEXT:    .cfi_offset b10, -64
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov s8, v0.s[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
-; CHECK-NEXT:    mov w8, #-16777216
+; CHECK-NEXT:    movi v9.2s, #255, lsl #24
+; CHECK-NEXT:    mov w8, #2130706431
 ; CHECK-NEXT:    mov x21, #-9223372036854775808
 ; CHECK-NEXT:    mov x22, #9223372036854775807
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-NEXT:    fmov s10, w8
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $q0
-; CHECK-NEXT:    fmov s9, w8
-; CHECK-NEXT:    mov w8, #2130706431
 ; CHECK-NEXT:    fcmp s8, s9
-; CHECK-NEXT:    fmov s10, w8
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x21, x1, lt
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    csel x9, x22, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    csel x19, xzr, x8, vs
 ; CHECK-NEXT:    csel x20, xzr, x9, vs

 ; CHECK-NEXT:    .cfi_offset w30, -72
 ; CHECK-NEXT:    .cfi_offset b8, -80
 ; CHECK-NEXT:    .cfi_offset b9, -88
 ; CHECK-NEXT:    .cfi_offset b10, -96
 ; CHECK-NEXT:    mov s8, v0.s[1]
 ; CHECK-NEXT:    str q0, [sp, #16] // 16-byte Folded Spill
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
-; CHECK-NEXT:    mov w8, #-251658240
+; CHECK-NEXT:    movi v9.2s, #241, lsl #24
+; CHECK-NEXT:    mov w8, #1895825407
 ; CHECK-NEXT:    mov x25, #-34359738368
 ; CHECK-NEXT:    ldr q0, [sp, #16] // 16-byte Folded Reload
 ; CHECK-NEXT:    mov x26, #34359738367
-; CHECK-NEXT:    fmov s9, w8
-; CHECK-NEXT:    mov w8, #1895825407
-; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    fmov s10, w8
-; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $q0
+; CHECK-NEXT:    fcmp s8, s9
+; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x25, x1, lt
 ; CHECK-NEXT:    fcmp s8, s10
+; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
+; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $q0
 ; CHECK-NEXT:    csel x9, x26, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    csel x19, xzr, x8, vs
 ; CHECK-NEXT:    csel x20, xzr, x9, vs
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    fcmp s0, s9

 ; CHECK-NEXT:    .cfi_offset w30, -72
 ; CHECK-NEXT:    .cfi_offset b8, -80
 ; CHECK-NEXT:    .cfi_offset b9, -88
 ; CHECK-NEXT:    .cfi_offset b10, -96
 ; CHECK-NEXT:    mov s8, v0.s[1]
 ; CHECK-NEXT:    str q0, [sp, #16] // 16-byte Folded Spill
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
-; CHECK-NEXT:    mov w8, #-16777216
+; CHECK-NEXT:    movi v9.2s, #255, lsl #24
+; CHECK-NEXT:    mov w8, #2130706431
 ; CHECK-NEXT:    mov x25, #-9223372036854775808
 ; CHECK-NEXT:    ldr q0, [sp, #16] // 16-byte Folded Reload
 ; CHECK-NEXT:    mov x26, #9223372036854775807
-; CHECK-NEXT:    fmov s9, w8
-; CHECK-NEXT:    mov w8, #2130706431
-; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    fmov s10, w8
-; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $q0
+; CHECK-NEXT:    fcmp s8, s9
+; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x25, x1, lt
 ; CHECK-NEXT:    fcmp s8, s10
+; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
+; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $q0
 ; CHECK-NEXT:    csel x9, x26, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    csel x19, xzr, x8, vs
 ; CHECK-NEXT:    csel x20, xzr, x9, vs
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    fcmp s0, s9

 ; CHECK-NEXT:    .cfi_offset b9, -88
 ; CHECK-NEXT:    .cfi_offset b10, -96
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov h1, v0.h[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    fcvt s8, h1
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
-; CHECK-NEXT:    mov w8, #-251658240
+; CHECK-NEXT:    movi v9.2s, #241, lsl #24
+; CHECK-NEXT:    mov w8, #1895825407
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    mov x25, #-34359738368
 ; CHECK-NEXT:    mov x26, #34359738367
-; CHECK-NEXT:    fmov s9, w8
-; CHECK-NEXT:    mov w8, #1895825407
-; CHECK-NEXT:    mov h0, v0.h[2]
-; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    fmov s10, w8
+; CHECK-NEXT:    fcmp s8, s9
+; CHECK-NEXT:    mov h0, v0.h[2]
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x25, x1, lt
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    csel x9, x26, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    fcvt s8, h0
 ; CHECK-NEXT:    csel x19, xzr, x8, vs

 ; CHECK-NEXT:    .cfi_offset b9, -88
 ; CHECK-NEXT:    .cfi_offset b10, -96
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov h1, v0.h[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    fcvt s8, h1
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
-; CHECK-NEXT:    mov w8, #-16777216
+; CHECK-NEXT:    movi v9.2s, #255, lsl #24
+; CHECK-NEXT:    mov w8, #2130706431
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    mov x25, #-9223372036854775808
 ; CHECK-NEXT:    mov x26, #9223372036854775807
-; CHECK-NEXT:    fmov s9, w8
-; CHECK-NEXT:    mov w8, #2130706431
-; CHECK-NEXT:    mov h0, v0.h[2]
-; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    fmov s10, w8
+; CHECK-NEXT:    fcmp s8, s9
+; CHECK-NEXT:    mov h0, v0.h[2]
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x25, x1, lt
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    csel x9, x26, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    fcvt s8, h0
 ; CHECK-NEXT:    csel x19, xzr, x8, vs

 ; CHECK-NEXT:    str q0, [sp, #48] // 16-byte Folded Spill
 ; CHECK-NEXT:    mov x19, x8
 ; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    str q0, [sp, #32] // 16-byte Folded Spill
 ; CHECK-NEXT:    mov h0, v0.h[1]
 ; CHECK-NEXT:    fcvt s8, h0
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
-; CHECK-NEXT:    mov w8, #-251658240
+; CHECK-NEXT:    movi v10.2s, #241, lsl #24
+; CHECK-NEXT:    mov w8, #1895825407
 ; CHECK-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    mov x25, #-34359738368
 ; CHECK-NEXT:    mov x23, #34359738367
-; CHECK-NEXT:    fmov s10, w8
-; CHECK-NEXT:    mov w8, #1895825407
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    fmov s9, w8
+; CHECK-NEXT:    fcmp s8, s10
+; CHECK-NEXT:    mov h0, v0.h[3]
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x25, x1, lt
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    csel x9, x23, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    fcvt s8, h0
 ; CHECK-NEXT:    csel x8, xzr, x8, vs

 ; CHECK-NEXT:    .cfi_offset b10, -128
 ; CHECK-NEXT:    str q0, [sp, #48] // 16-byte Folded Spill
 ; CHECK-NEXT:    mov x19, x8
 ; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    fcvt s8, h0
 ; CHECK-NEXT:    str q0, [sp, #32] // 16-byte Folded Spill
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
-; CHECK-NEXT:    mov w8, #-16777216
+; CHECK-NEXT:    movi v10.2s, #255, lsl #24
+; CHECK-NEXT:    mov w8, #2130706431
 ; CHECK-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    mov x21, #-9223372036854775808
 ; CHECK-NEXT:    mov x22, #9223372036854775807
-; CHECK-NEXT:    fmov s10, w8
-; CHECK-NEXT:    mov w8, #2130706431
-; CHECK-NEXT:    mov h0, v0.h[1]
-; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    fmov s9, w8
+; CHECK-NEXT:    fcmp s8, s10
+; CHECK-NEXT:    mov h0, v0.h[1]
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x21, x1, lt
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    csel x9, x22, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    fcvt s8, h0
 ; CHECK-NEXT:    csel x8, xzr, x8, vs

llvm/test/CodeGen/AArch64/remat-const-float-simd.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -verify-machineinstrs | FileCheck %s
+
+; Check that big fp constants can be rematerialized with movi
+target triple = "aarch64-unknown-linux-gnu"
+
+; float foo(void) { return float(0x7fffffff); }
+define float @foo() {
+; CHECK-LABEL: foo:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    movi v0.2s, #79, lsl #24
+; CHECK-NEXT:    ret
+entry:
+ ret float 0x41E0000000000000
+}
+
+; float foo2(float p) { return p + float(0x7fffffff); }
+define float @foo2(float %f) {
+; CHECK-LABEL: foo2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    movi v1.2s, #79, lsl #24
+; CHECK-NEXT:    fadd s0, s0, s1
+; CHECK-NEXT:    ret
+entry:
+  %p = fadd float %f, 0x41E0000000000000
+  ret float %p
+}

llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll

 ; CHECK-NEXT:    ret
   %b = call reassoc fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128 0xL00000000000000008000000000000000, <1 x fp128> %a)
   ret fp128 %b
 }
 
 define float @test_v3f32(<3 x float> %a) nounwind {
 ; CHECK-LABEL: test_v3f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-2147483648
-; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    movi v1.2s, #128, lsl #24
 ; CHECK-NEXT:    mov v0.s[3], v1.s[0]
 ; CHECK-NEXT:    faddp v0.4s, v0.4s, v0.4s
 ; CHECK-NEXT:    faddp s0, v0.2s
 ; CHECK-NEXT:    ret
   %b = call reassoc float @llvm.vector.reduce.fadd.f32.v3f32(float -0.0, <3 x float> %a)
   ret float %b
 }