[AArch64][SVE] Perform fixed-width predicate OR reduction on SVE predicate vectors.

[sdesmalen]

Summary

By default fixed-width i1 vectors are promoted, but when SVE is available,
some expression trees can be rewritten to use <vscale x M x i1> types,
such that all operations are performed on predicate registers, thus
avoiding unnecessary sign-extends and truncates. It does this by bubbling
up the 'sign-extend + extract' operations all the way up to nodes that
can be performed on SVE predicate registers.

The example chosen in this patch is to optimise an OR reduction
of a <N x i1> type, which can be implemented directly with a PTEST
instruction.

This patch is a rework of D117574.

[efriedma]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

14379

This feels weird; we're adding nodes to the worklist without having actually done any transforms. Maybe this should be somewhere else?

llvm/test/CodeGen/AArch64/sve-fixed-length-float-compares.ll

372

This is a nice improvement.

llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll

19

We should probably prefer to do this unpacking in predicate registers. But not necessary for this patch.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

#undef LCALLNAME5
   setTargetDAGCombine(ISD::SELECT);
   setTargetDAGCombine(ISD::VSELECT);
 
   setTargetDAGCombine(ISD::INTRINSIC_VOID);
   setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
   setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
   setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
   setTargetDAGCombine(ISD::VECREDUCE_ADD);
+  setTargetDAGCombine(ISD::VECREDUCE_OR);
   setTargetDAGCombine(ISD::STEP_VECTOR);
 
   setTargetDAGCombine(ISD::MGATHER);
   setTargetDAGCombine(ISD::MSCATTER);
 
   setTargetDAGCombine(ISD::FP_EXTEND);
 
   setTargetDAGCombine(ISD::GlobalAddress);
if (A.getOpcode() == ISD::ADD) {
     if (SDValue R = DetectAddExtract(A.getOperand(1)))
       return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
                          DAG.getNode(ISD::ADD, SDLoc(A), A.getValueType(), R,
                                      A.getOperand(0)));
   }
   return SDValue();
 }
 
+// If V is a sign-extend of a scalable predicate vector (possibly masked as
+// a fixed-width vector), return the original scalable predicate vector.
+// If no such predicate is found, returns SDValue().
+static SDValue findScalablePredicateOperand(SDValue V, SelectionDAG &DAG) {
+  const auto &Subtarget =
+      static_cast<const AArch64Subtarget &>(DAG.getSubtarget());
+  if (!V.getValueType().isVector() || !Subtarget.hasSVE())
+    return SDValue();
+
+  // Look through truncates and scalable -> fixed conversion.
+  while ((V.getOpcode() == ISD::TRUNCATE ||
+          (V.getValueType().isFixedLengthVector() &&
+           V.getOpcode() == ISD::EXTRACT_SUBVECTOR)) &&
+         V.hasOneUse())
+    V = V.getOperand(0);
+
+  if (V.getValueType().isScalableVector() &&
+      V.getOpcode() == ISD::SIGN_EXTEND &&
+      V.getOperand(0).getValueType().getVectorElementType() == MVT::i1)
+    return V.getOperand(0);
+
+  if (V.getValueType().isFixedLengthVector() &&
+      ISD::isConstantSplatVectorAllOnes(V.getNode())) {
+    EVT ScalableVT = getContainerForFixedLengthVector(DAG, V.getValueType())
+                         .changeVectorElementType(MVT::i1);
+    return DAG.getConstant(-1, SDLoc(V.getNode()), ScalableVT);
+  }
+
+  return SDValue();
+}
+
+static SDValue getPredicateForFixedLengthVector(SelectionDAG &DAG, SDLoc &DL,
+                                                EVT VT);
+static SDValue performVecreduceAndOrCombine(SDNode *N,
+                                            const AArch64TargetLowering &TLI,
+                                            SelectionDAG &DAG) {
+  EVT OpVT = N->getOperand(0).getValueType();
+  if (!OpVT.isFixedLengthVector())
+    return SDValue();
+
+  // Try to perform the operation on SVE predicate vectors, if available.
+  if (SDValue Pred = findScalablePredicateOperand(N->getOperand(0), DAG)) {
+    SDLoc DL(N);
+    EVT PromVT = getPromotedVTForPredicate(Pred.getValueType());
+    SDValue PredForVL = getPredicateForFixedLengthVector(
+        DAG, DL, OpVT.changeVectorElementType(PromVT.getVectorElementType()));
+
+    // If not all bits in the scalable vector are defined, we need to
+    // manually define these to be 0 or 1.
+    if (!TLI.isAllActivePredicate(DAG, PredForVL)) {
+      EVT PredVT = PredForVL.getValueType();
+      Pred = DAG.getNode(ISD::AND, DL, PredVT, Pred, PredForVL);
+    }
+
+    return DAG.getNode(N->getOpcode(), DL, N->getValueType(0), Pred);
+  }
+
+  return SDValue();
+}
 
 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
                                  TargetLowering::DAGCombinerInfo &DCI,
                                  const AArch64Subtarget *Subtarget) {
+  // Try to perform the operation on SVE predicate vectors, if available.
+  SDValue NewLHS, NewRHS;
+  if (N->getValueType(0).isFixedLengthVector() &&
+      (NewLHS = findScalablePredicateOperand(N->getOperand(0), DAG)) &&
+      (NewRHS = findScalablePredicateOperand(N->getOperand(1), DAG))) {
+    assert(!(isa<ConstantSDNode>(NewLHS) && isa<ConstantSDNode>(NewRHS)) &&
+           "Expected nodes to have been constant folded");
+    EVT ContainerVT = getContainerForFixedLengthVector(DAG, N->getValueType(0));
+    SDValue PredXOR =
+        DAG.getNode(ISD::XOR, SDLoc(N), NewLHS.getValueType(), NewLHS, NewRHS);
+    SDValue Ext = DAG.getSExtOrTrunc(PredXOR, SDLoc(N), ContainerVT);
+    return convertFromScalableVector(DAG, N->getValueType(0), Ext);
+  }
+
   if (DCI.isBeforeLegalizeOps())
     return SDValue();
 
   return foldVectorXorShiftIntoCmp(N, DAG, Subtarget);
 }
 
 SDValue
 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
     return SDValue();
 
   if (SDValue Res = tryCombineToEXTR(N, DCI))
     return Res;
 
   if (SDValue Res = tryCombineToBSL(N, DCI))
     return Res;
 
+  // Try to perform the operation on SVE predicate vectors, if available.
+  SDValue NewLHS, NewRHS;
+  if (VT.isFixedLengthVector() &&
+      (NewLHS = findScalablePredicateOperand(N->getOperand(0), DAG)) &&
+      (NewRHS = findScalablePredicateOperand(N->getOperand(1), DAG))) {
+    assert(!(isa<ConstantSDNode>(NewLHS) && isa<ConstantSDNode>(NewRHS)) &&
+           "Expected nodes to have been constant folded");
+    EVT ContainerVT = getContainerForFixedLengthVector(DAG, N->getValueType(0));
+    SDValue PredOR =
+        DAG.getNode(ISD::OR, SDLoc(N), NewLHS.getValueType(), NewLHS, NewRHS);
+    SDValue Ext = DAG.getSExtOrTrunc(PredOR, SDLoc(N), ContainerVT);
+    return convertFromScalableVector(DAG, N->getValueType(0), Ext);
+  }
+
   return SDValue();
 }
 
 static bool isConstantSplatVectorMaskForType(SDNode *N, EVT MemVT) {
   if (!MemVT.getVectorElementType().isSimple())
     return false;
 
   uint64_t MaskForTy = 0ull;

 // This pass can also recognize signed variants of the patterns that use sign
 // extension instead of zero extension and form a srhadd(OpA, OpB) or a
 // shadd(OpA, OpB) from them.
 static SDValue
 performVectorTruncateCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
                              SelectionDAG &DAG) {
   EVT VT = N->getValueType(0);
 
+  SDValue Pred;
+  if (N->getValueType(0).isFixedLengthVector() &&
+      (Pred = findScalablePredicateOperand(N->getOperand(0), DAG))) {
+    // This pattern can be recognised, but the users may not be automatically
+    // revisited by the DAGCombiner, so add the users to the worklist.
+    assert(!isa<ConstantSDNode>(Pred) &&
+           "Expected node to have been constant folded");
+    for (auto *Use : N->uses())
+      DCI.AddToWorklist(Use);
+  }
+
   // Since we are looking for a right shift by a constant value of 1 and we are
   // operating on types at least 16 bits in length (sign/zero extended OpA and
   // OpB, which are at least 8 bits), it follows that the truncate will always
   // discard the shifted-in bit and therefore the right shift will be logical
   // regardless of the signedness of OpA and OpB.
   SDValue Shift = N->getOperand(0);
   if (Shift.getOpcode() != AArch64ISD::VLSHR)
     return SDValue();
static SDValue performCSELCombine(SDNode *N,
                                   SelectionDAG &DAG) {
   // CSEL x, x, cc -> x
   if (N->getOperand(0) == N->getOperand(1))
     return N->getOperand(0);
 
   return performCONDCombine(N, DCI, DAG, 2, 3);
 }
 
-static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
+static SDValue performSETCCCombine(SDNode *N, bool UseSVEForFixedLengthCompares,
+                                   SelectionDAG &DAG) {
   assert(N->getOpcode() == ISD::SETCC && "Unexpected opcode!");
   SDValue LHS = N->getOperand(0);
   SDValue RHS = N->getOperand(1);
   ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
 
   // setcc (csel 0, 1, cond, X), 1, ne ==> csel 0, 1, !cond, X
   if (Cond == ISD::SETNE && isOneConstant(RHS) &&
       LHS->getOpcode() == AArch64ISD::CSEL &&
if (Cond == ISD::SETNE && isOneConstant(RHS) &&
     // csel 0, 1, !cond, X
     SDValue CSEL =
         DAG.getNode(AArch64ISD::CSEL, DL, LHS.getValueType(), LHS.getOperand(0),
                     LHS.getOperand(1), DAG.getConstant(NewCond, DL, MVT::i32),
                     LHS.getOperand(3));
     return DAG.getZExtOrTrunc(CSEL, DL, N->getValueType(0));
   }
 
+  // For fixed-length vectors, convert to a scalable SETCC operation early so
+  // that we can propagate any possible sign-extends to the uses of SETCC.
+  if (UseSVEForFixedLengthCompares && N->hasOneUse() &&
+      DAG.getTargetLoweringInfo().isTypeLegal(N->getValueType(0))) {
+    SDLoc DL(N);
+    EVT ContainerVT =
+        getContainerForFixedLengthVector(DAG, N->getOperand(0).getValueType());
+    EVT PredVT = ContainerVT.changeVectorElementType(MVT::i1);
+    auto Op1 = convertToScalableVector(DAG, ContainerVT, N->getOperand(0));
+    auto Op2 = convertToScalableVector(DAG, ContainerVT, N->getOperand(1));
+    auto Cmp = DAG.getNode(ISD::SETCC, DL, PredVT, Op1, Op2, N->getOperand(2));
+    EVT PromoteVT = ContainerVT.changeTypeToInteger();
+    auto Promote = DAG.getBoolExtOrTrunc(Cmp, DL, PromoteVT,
+                                         N->getOperand(0).getValueType());
+    return convertFromScalableVector(DAG, N->getValueType(0), Promote);
+  }
+
   return SDValue();
 }
 
 static SDValue performSetCCPunpkCombine(SDNode *N, SelectionDAG &DAG) {
   // setcc_merge_zero pred
   //   (sign_extend (extract_subvector (setcc_merge_zero ... pred ...))), 0, ne
   //   => extract_subvector (inner setcc_merge_zero)
   SDValue Pred = N->getOperand(0);
if (Pred.getOpcode() == AArch64ISD::PTRUE &&
       Pred.getConstantOperandVal(0) == InnerPred.getConstantOperandVal(0) &&
       Pred->getConstantOperandVal(0) >= AArch64SVEPredPattern::vl1 &&
       Pred->getConstantOperandVal(0) <= AArch64SVEPredPattern::vl256)
     return Extract;
 
   return SDValue();
 }
 
-static SDValue getPredicateForFixedLengthVector(SelectionDAG &DAG, SDLoc &DL,
-                                                EVT VT);
 // Pattern match utility function to return if V is a conversion of a
 // fixed-width vector -> scalable vector.
 static bool isConvertToScalableVector(SDValue V) {
   return V.getOpcode() == ISD::INSERT_SUBVECTOR && V.getOperand(0).isUndef() &&
          V.getOperand(1).getValueType().isFixedLengthVector() &&
          V.getConstantOperandVal(2) == 0;
 }
 
case ISD::CONCAT_VECTORS:
     return performConcatVectorsCombine(N, DCI, DAG);
   case ISD::INSERT_SUBVECTOR:
     return performInsertSubvectorCombine(N, DCI, DAG);
   case ISD::SELECT:
     return performSelectCombine(N, DCI);
   case ISD::VSELECT:
     return performVSelectCombine(N, DCI.DAG);
   case ISD::SETCC:
-    return performSETCCCombine(N, DAG);
+    return performSETCCCombine(
+        N, useSVEForFixedLengthVectorVT(N->getValueType(0)), DAG);
   case ISD::LOAD:
     if (performTBISimplification(N->getOperand(1), DCI, DAG))
       return SDValue(N, 0);
     break;
   case ISD::STORE:
     return performSTORECombine(N, DCI, DAG, Subtarget);
   case ISD::MGATHER:
   case ISD::MSCATTER:
SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
   case ISD::INSERT_VECTOR_ELT:
     return performInsertVectorEltCombine(N, DCI);
   case ISD::EXTRACT_VECTOR_ELT:
     return performExtractVectorEltCombine(N, DAG);
   case ISD::VECREDUCE_ADD:
     return performVecReduceAddCombine(N, DCI.DAG, Subtarget);
   case AArch64ISD::UADDV:
     return performUADDVCombine(N, DAG);
+  case ISD::VECREDUCE_OR:
+    return performVecreduceAndOrCombine(N, *this, DAG);
   case ISD::INTRINSIC_VOID:
   case ISD::INTRINSIC_W_CHAIN:
     switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
     case Intrinsic::aarch64_sve_prfb_gather_scalar_offset:
       return combineSVEPrefetchVecBaseImmOff(N, DAG, 1 /*=ScalarSizeInBytes*/);
     case Intrinsic::aarch64_sve_prfh_gather_scalar_offset:
       return combineSVEPrefetchVecBaseImmOff(N, DAG, 2 /*=ScalarSizeInBytes*/);
     case Intrinsic::aarch64_sve_prfw_gather_scalar_offset:

llvm/test/CodeGen/AArch64/sve-fixed-length-float-compares.ll

 ;
 ; FCMP UEQ
 ;
 
 define void @fcmp_ueq_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) #0 {
 ; CHECK-LABEL: fcmp_ueq_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl16
-; CHECK-NEXT:    mov w8, #65535
+; CHECK-NEXT:    ptrue p2.h
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
 ; CHECK-NEXT:    ld1h { z1.h }, p0/z, [x1]
 ; CHECK-NEXT:    fcmne p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT:    mov z1.h, w8
+; CHECK-NEXT:    not p1.b, p2/z, p1.b
 ; CHECK-NEXT:    mov z0.h, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
 ; CHECK-NEXT:    st1h { z0.h }, p0, [x2]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x half>, <16 x half>* %a
   %op2 = load <16 x half>, <16 x half>* %b
   %cmp = fcmp ueq <16 x half> %op1, %op2
   %sext = sext <16 x i1> %cmp to <16 x i16>
   store <16 x i16> %sext, <16 x i16>* %c
   ret void

 ;
 ; FCMP UNE
 ;
 
 define void @fcmp_une_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) #0 {
 ; CHECK-LABEL: fcmp_une_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl16
-; CHECK-NEXT:    mov w8, #65535
+; CHECK-NEXT:    ptrue p2.h
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
 ; CHECK-NEXT:    ld1h { z1.h }, p0/z, [x1]
 ; CHECK-NEXT:    fcmeq p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT:    mov z1.h, w8
+; CHECK-NEXT:    not p1.b, p2/z, p1.b
 ; CHECK-NEXT:    mov z0.h, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
 ; CHECK-NEXT:    st1h { z0.h }, p0, [x2]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x half>, <16 x half>* %a
   %op2 = load <16 x half>, <16 x half>* %b
   %cmp = fcmp une <16 x half> %op1, %op2
   %sext = sext <16 x i1> %cmp to <16 x i16>
   store <16 x i16> %sext, <16 x i16>* %c
   ret void

 ;
 ; FCMP UGT
 ;
 
 define void @fcmp_ugt_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) #0 {
 ; CHECK-LABEL: fcmp_ugt_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl16
-; CHECK-NEXT:    mov w8, #65535
+; CHECK-NEXT:    ptrue p2.h
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
 ; CHECK-NEXT:    ld1h { z1.h }, p0/z, [x1]
 ; CHECK-NEXT:    fcmge p1.h, p0/z, z1.h, z0.h
-; CHECK-NEXT:    mov z1.h, w8
+; CHECK-NEXT:    not p1.b, p2/z, p1.b
 ; CHECK-NEXT:    mov z0.h, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
 ; CHECK-NEXT:    st1h { z0.h }, p0, [x2]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x half>, <16 x half>* %a
   %op2 = load <16 x half>, <16 x half>* %b
   %cmp = fcmp ugt <16 x half> %op1, %op2
   %sext = sext <16 x i1> %cmp to <16 x i16>
   store <16 x i16> %sext, <16 x i16>* %c
   ret void

 ;
 ; FCMP ULT
 ;
 
 define void @fcmp_ult_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) #0 {
 ; CHECK-LABEL: fcmp_ult_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl16
-; CHECK-NEXT:    mov w8, #65535
+; CHECK-NEXT:    ptrue p2.h
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
 ; CHECK-NEXT:    ld1h { z1.h }, p0/z, [x1]
 ; CHECK-NEXT:    fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT:    mov z1.h, w8
+; CHECK-NEXT:    not p1.b, p2/z, p1.b
 ; CHECK-NEXT:    mov z0.h, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
 ; CHECK-NEXT:    st1h { z0.h }, p0, [x2]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x half>, <16 x half>* %a
   %op2 = load <16 x half>, <16 x half>* %b
   %cmp = fcmp ult <16 x half> %op1, %op2
   %sext = sext <16 x i1> %cmp to <16 x i16>
   store <16 x i16> %sext, <16 x i16>* %c
   ret void

 ;
 ; FCMP UGE
 ;
 
 define void @fcmp_uge_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) #0 {
 ; CHECK-LABEL: fcmp_uge_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl16
-; CHECK-NEXT:    mov w8, #65535
+; CHECK-NEXT:    ptrue p2.h
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
 ; CHECK-NEXT:    ld1h { z1.h }, p0/z, [x1]
 ; CHECK-NEXT:    fcmgt p1.h, p0/z, z1.h, z0.h
-; CHECK-NEXT:    mov z1.h, w8
+; CHECK-NEXT:    not p1.b, p2/z, p1.b
 ; CHECK-NEXT:    mov z0.h, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
 ; CHECK-NEXT:    st1h { z0.h }, p0, [x2]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x half>, <16 x half>* %a
   %op2 = load <16 x half>, <16 x half>* %b
   %cmp = fcmp uge <16 x half> %op1, %op2
   %sext = sext <16 x i1> %cmp to <16 x i16>
   store <16 x i16> %sext, <16 x i16>* %c
   ret void

 ;
 ; FCMP ULE
 ;
 
 define void @fcmp_ule_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) #0 {
 ; CHECK-LABEL: fcmp_ule_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl16
-; CHECK-NEXT:    mov w8, #65535
+; CHECK-NEXT:    ptrue p2.h
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
 ; CHECK-NEXT:    ld1h { z1.h }, p0/z, [x1]
 ; CHECK-NEXT:    fcmgt p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT:    mov z1.h, w8
+; CHECK-NEXT:    not p1.b, p2/z, p1.b
 ; CHECK-NEXT:    mov z0.h, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
 ; CHECK-NEXT:    st1h { z0.h }, p0, [x2]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x half>, <16 x half>* %a
   %op2 = load <16 x half>, <16 x half>* %b
   %cmp = fcmp ule <16 x half> %op1, %op2
   %sext = sext <16 x i1> %cmp to <16 x i16>
   store <16 x i16> %sext, <16 x i16>* %c
   ret void

 ;
 ; FCMP ORD
 ;
 
 define void @fcmp_ord_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x i16>* %c) #0 {
 ; CHECK-LABEL: fcmp_ord_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h, vl16
-; CHECK-NEXT:    mov w8, #65535
+; CHECK-NEXT:    ptrue p2.h
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
 ; CHECK-NEXT:    ld1h { z1.h }, p0/z, [x1]
 ; CHECK-NEXT:    fcmuo p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT:    mov z1.h, w8
+; CHECK-NEXT:    not p1.b, p2/z, p1.b
 ; CHECK-NEXT:    mov z0.h, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
 ; CHECK-NEXT:    st1h { z0.h }, p0, [x2]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x half>, <16 x half>* %a
   %op2 = load <16 x half>, <16 x half>* %b
   %cmp = fcmp ord <16 x half> %op1, %op2
   %sext = sext <16 x i1> %cmp to <16 x i16>
   store <16 x i16> %sext, <16 x i16>* %c
   ret void

llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s
 
 define i1 @ptest_v16i1_256bit_min_sve(float* %a, float * %b) vscale_range(2, 0) {
 ; CHECK-LABEL: ptest_v16i1_256bit_min_sve:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #8
 ; CHECK-NEXT:    ptrue p0.s, vl8
+; CHECK-NEXT:    ptrue p2.s
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
 ; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x0]
 ; CHECK-NEXT:    fcmeq p1.s, p0/z, z0.s, #0.0
 ; CHECK-NEXT:    fcmeq p0.s, p0/z, z1.s, #0.0
+; CHECK-NEXT:    not p1.b, p2/z, p1.b
+; CHECK-NEXT:    not p0.b, p2/z, p0.b
 ; CHECK-NEXT:    mov z0.s, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z1.s, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z2.s, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
-; CHECK-NEXT:    eor z1.d, z2.d, z1.d
+; CHECK-NEXT:    mov z1.s, p0/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
 ; CHECK-NEXT:    uzp1 z1.h, z1.h, z1.h
 ; CHECK-NEXT:    uzp1 z0.b, z0.b, z0.b
 ; CHECK-NEXT:    uzp1 z1.b, z1.b, z1.b
-; CHECK-NEXT:    ptrue p0.b, vl16
 ; CHECK-NEXT:    mov v1.d[1], v0.d[0]
+; CHECK-NEXT:    ptrue p0.b, vl16
 ; CHECK-NEXT:    orv b0, p0, z1.b
 ; CHECK-NEXT:    fmov w8, s0
 ; CHECK-NEXT:    and w0, w8, #0x1
 ; CHECK-NEXT:    ret
   %v0 = bitcast float* %a to <16 x float>*
   %v1 = load <16 x float>, <16 x float>* %v0, align 4
   %v2 = fcmp une <16 x float> %v1, zeroinitializer
   %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2)
   ret i1 %v3
 }
 
 define i1 @ptest_v16i1_512bit_min_sve(float* %a, float * %b) vscale_range(4, 0) {
 ; CHECK-LABEL: ptest_v16i1_512bit_min_sve:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.s, vl16
-; CHECK-NEXT:    mov z1.s, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0]
-; CHECK-NEXT:    fcmeq p0.s, p0/z, z0.s, #0.0
-; CHECK-NEXT:    mov z0.s, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
-; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
-; CHECK-NEXT:    uzp1 z0.b, z0.b, z0.b
-; CHECK-NEXT:    orv b0, p0, z0.b
-; CHECK-NEXT:    fmov w8, s0
-; CHECK-NEXT:    and w0, w8, #0x1
+; CHECK-NEXT:    fcmeq p1.s, p0/z, z0.s, #0.0
+; CHECK-NEXT:    bic p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT:    ptest p0, p0.b
+; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %v0 = bitcast float* %a to <16 x float>*
   %v1 = load <16 x float>, <16 x float>* %v0, align 4
   %v2 = fcmp une <16 x float> %v1, zeroinitializer
   %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2)
   ret i1 %v3
 }
 
 define i1 @ptest_v16i1_512bit_sve(float* %a, float * %b) vscale_range(4, 4) {
 ; CHECK-LABEL: ptest_v16i1_512bit_sve:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    mov z1.s, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0]
-; CHECK-NEXT:    fcmeq p0.s, p0/z, z0.s, #0.0
-; CHECK-NEXT:    mov z0.s, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
-; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
-; CHECK-NEXT:    uzp1 z0.b, z0.b, z0.b
-; CHECK-NEXT:    orv b0, p0, z0.b
-; CHECK-NEXT:    fmov w8, s0
-; CHECK-NEXT:    and w0, w8, #0x1
+; CHECK-NEXT:    fcmeq p1.s, p0/z, z0.s, #0.0
+; CHECK-NEXT:    not p0.b, p0/z, p1.b
+; CHECK-NEXT:    ptest p0, p0.b
+; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %v0 = bitcast float* %a to <16 x float>*
   %v1 = load <16 x float>, <16 x float>* %v0, align 4
   %v2 = fcmp une <16 x float> %v1, zeroinitializer
   %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2)
   ret i1 %v3
 }
 
 define i1 @ptest_or_v16i1_512bit_min_sve(float* %a, float * %b) vscale_range(4, 0) {
 ; CHECK-LABEL: ptest_or_v16i1_512bit_min_sve:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.s, vl16
+; CHECK-NEXT:    ptrue p2.s
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0]
 ; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x1]
 ; CHECK-NEXT:    fcmeq p1.s, p0/z, z0.s, #0.0
-; CHECK-NEXT:    fcmeq p0.s, p0/z, z1.s, #0.0
-; CHECK-NEXT:    mov z0.s, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z1.s, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z2.s, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
-; CHECK-NEXT:    eor z1.d, z2.d, z1.d
-; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    orr z0.d, z0.d, z1.d
-; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
-; CHECK-NEXT:    uzp1 z0.b, z0.b, z0.b
-; CHECK-NEXT:    orv b0, p0, z0.b
-; CHECK-NEXT:    fmov w8, s0
-; CHECK-NEXT:    and w0, w8, #0x1
+; CHECK-NEXT:    fcmeq p3.s, p0/z, z1.s, #0.0
+; CHECK-NEXT:    not p1.b, p2/z, p1.b
+; CHECK-NEXT:    not p2.b, p2/z, p3.b
+; CHECK-NEXT:    sel p1.b, p1, p1.b, p2.b
+; CHECK-NEXT:    and p0.b, p1/z, p1.b, p0.b
+; CHECK-NEXT:    ptest p0, p0.b
+; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %v0 = bitcast float* %a to <16 x float>*
   %v1 = load <16 x float>, <16 x float>* %v0, align 4
   %v2 = fcmp une <16 x float> %v1, zeroinitializer
   %v3 = bitcast float* %b to <16 x float>*
   %v4 = load <16 x float>, <16 x float>* %v3, align 4
   %v5 = fcmp une <16 x float> %v4, zeroinitializer
   %v6 = or <16 x i1> %v2, %v5

 
 define i1 @ptest_and_v16i1_512bit_sve(float* %a, float * %b) vscale_range(4, 4) {
 ; CHECK-LABEL: ptest_and_v16i1_512bit_sve:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0]
 ; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x1]
 ; CHECK-NEXT:    fcmeq p1.s, p0/z, z0.s, #0.0
+; CHECK-NEXT:    not p1.b, p0/z, p1.b
 ; CHECK-NEXT:    fcmeq p0.s, p0/z, z1.s, #0.0
-; CHECK-NEXT:    mov z0.s, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z1.s, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
-; CHECK-NEXT:    mov z1.s, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    bic z0.d, z0.d, z1.d
+; CHECK-NEXT:    bic p0.b, p1/z, p1.b, p0.b
+; CHECK-NEXT:    mov z0.s, p0/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    ptrue p0.b, vl16
 ; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
 ; CHECK-NEXT:    uzp1 z0.b, z0.b, z0.b
 ; CHECK-NEXT:    andv b0, p0, z0.b
 ; CHECK-NEXT:    fmov w8, s0
 ; CHECK-NEXT:    and w0, w8, #0x1
 ; CHECK-NEXT:    ret
   %v0 = bitcast float* %a to <16 x float>*
   %v1 = load <16 x float>, <16 x float>* %v0, align 4
   %v2 = fcmp une <16 x float> %v1, zeroinitializer
   %v3 = bitcast float* %b to <16 x float>*
   %v4 = load <16 x float>, <16 x float>* %v3, align 4
   %v5 = fcmp une <16 x float> %v4, zeroinitializer
   %v6 = and <16 x i1> %v2, %v5
   %v7 = call i1 @llvm.vector.reduce.and.i1.v16i1 (<16 x i1> %v6)
   ret i1 %v7
 }
 
 define i1 @ptest_and_v16i1_512bit_min_sve(float* %a, float * %b) vscale_range(4, 0) {
 ; CHECK-LABEL: ptest_and_v16i1_512bit_min_sve:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.s, vl16
+; CHECK-NEXT:    ptrue p2.s
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0]
 ; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x1]
 ; CHECK-NEXT:    fcmeq p1.s, p0/z, z0.s, #0.0
 ; CHECK-NEXT:    fcmeq p0.s, p0/z, z1.s, #0.0
-; CHECK-NEXT:    mov z0.s, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z1.s, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
-; CHECK-NEXT:    mov z1.s, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    bic z0.d, z0.d, z1.d
+; CHECK-NEXT:    not p1.b, p2/z, p1.b
+; CHECK-NEXT:    bic p0.b, p1/z, p1.b, p0.b
+; CHECK-NEXT:    mov z0.s, p0/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    ptrue p0.b, vl16
 ; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
 ; CHECK-NEXT:    uzp1 z0.b, z0.b, z0.b
 ; CHECK-NEXT:    andv b0, p0, z0.b
 ; CHECK-NEXT:    fmov w8, s0
 ; CHECK-NEXT:    and w0, w8, #0x1
 ; CHECK-NEXT:    ret
   %v0 = bitcast float* %a to <16 x float>*