[Clang][OpenMP] Add the codegen support for `atomic compare`

[tianshilei1992]

Summary

This patch adds the codegen support for atomic compare in clang.

[tianshilei1992]

rebase and finish the functionality

[tianshilei1992]

remove unrelated changes

[tianshilei1992]

rebase

[tianshilei1992]

rebase

[jdoerfert]

clang/lib/CodeGen/CGStmtOpenMP.cpp

6023

leftover

clang/test/OpenMP/atomic_ast_print.cpp

1 ↗

(On Diff #405393)

this is a parser/sema test, not codegen. Add to the other patch.

llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h

1360 ↗

(On Diff #405379)

move into the other patch

[tianshilei1992]

rebase and make preparation for codegen in clang

[tianshilei1992]

remove leftovers

[tianshilei1992]

add tests

[tianshilei1992]

clang/test/OpenMP/atomic_compare_codegen.cpp

1

The test case itself was generated from a Python script.

3

This test cannot be done because clang crashed. I filed a bug https://github.com/llvm/llvm-project/issues/53601.

6

CodeGen for -fopen-simd is wrong. It doesn't emit corresponding atomic operations. I'll fix it.

llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp

3496

This change will be separated.

Actually I got a question about whether we want support equality comparison for floating point values. In the patch, we don't support '<' or '>' for floating point values because we don't have corresponding atomic instruction for them. For '==', we cast them to integers and then compare the two integers. However, We all know it doesn't make too much sense to compare two floating point variables, such as x == d. The comparison of floating point variables should always do like x - d < epsilon. However, like we said before, that comparison cannot be done because of lack of instruction. So I'm not sure if we want to support floating point variables at all.

[tianshilei1992]

fix clang crash and rebase

[tianshilei1992]

rebase and remove all SIMD-ONLY0 check lines as they are useless

[tianshilei1992]

clang/test/OpenMP/atomic_compare_codegen.cpp

1991

I think the store here is redundant. Is it because I'm using CGF.EmitScalarExpr?

1991

Oh, shoot. load here, instead of store.

[tianshilei1992]

clang/lib/CodeGen/CGStmtOpenMP.cpp

6041

Using D->IgnoreImpCasts() can make sure to avoid the case that char is casted to int in binary operation. However, say, if user writes the following code:

int x;
#pragma omp atomic compare
  x = x > 1.01 ? 1.01 : x;

1.01 here will be casted to 1 by clang, and a warning will be emitted. Because we ignore the implicit cast, in Sema, it is taken as floating point value. However, we already told user that it is casted to 1, which is a little weird to emit an error then.

[tianshilei1992]

remove support for floating point values

[tianshilei1992]

ping

[ABataev]

clang/test/OpenMP/atomic_compare_codegen.cpp

6

The logic behind -fopenmp-simd is to emit the code only for simd specific instructions.

[tianshilei1992]

clang/test/OpenMP/atomic_compare_codegen.cpp

6

Right. // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} is used here, same as other cases.

[tianshilei1992]

rebase

[ABataev]

LG with a nit

clang/include/clang/AST/StmtOpenMP.h

2970

Fix comment

[tianshilei1992]

In D118632#3336094, @ABataev wrote:

LG with a nit

Actually I got two question in the inline comments. Can you please take a look?

[ABataev]

In D118632#3336133, @tianshilei1992 wrote:

In D118632#3336094, @ABataev wrote:

LG with a nit

Actually I got two question in the inline comments. Can you please take a look?

Could you point me?

[tianshilei1992]

In D118632#3336145, @ABataev wrote:

In D118632#3336133, @tianshilei1992 wrote:

In D118632#3336094, @ABataev wrote:

LG with a nit

Actually I got two question in the inline comments. Can you please take a look?

Could you point me?

Sure.

clang/lib/CodeGen/CGStmtOpenMP.cpp

6041

@ABataev Here.

clang/test/OpenMP/atomic_compare_codegen.cpp

1991

And here. @ABataev

[ABataev]

clang/lib/CodeGen/CGStmtOpenMP.cpp

6041

Sorry, did not understand it was a question. Could you provide a bit more background, did not quite understand problem?

clang/test/OpenMP/atomic_compare_codegen.cpp

1991

Yes, because of EmitScalarExpr

[tianshilei1992]

clang/test/OpenMP/atomic_compare_codegen.cpp

1991

Can we somehow avoid the load here?

[ABataev]

clang/test/OpenMP/atomic_compare_codegen.cpp

1991

Do you need EmitScalarExpr?

[tianshilei1992]

clang/test/OpenMP/atomic_compare_codegen.cpp

1991

So it is a rvalue scalar here. What alternative do we have then?

[tianshilei1992]

fix comments

[tianshilei1992]

clang/lib/CodeGen/CGStmtOpenMP.cpp

6041

I have a better explain in another inline comment in Sema.

clang/lib/Sema/SemaOpenMP.cpp

11180

Here we do D->IgnoreImpCasts(), as shown in the code. The reason is, if we have two chars, say char a, b, and when a > b, clang also inserts an implicit cast from char to int for a and b. We want the actual type here otherwise in the IR builder, the type of D doesn't match X's, causing issues.
However, that IgnoreImpCasts here can cause another issue. Let's say we have the following code:

int x;
#pragma omp atomic compare
  x = x > 1.01 ? 1.01 : x;

clang will also insert an implicit cast from floating point value to integer for the scalar value 1.01 (corresponding to D in the code), and also emits a warning saying the floating point value has been cast to integer or something like that. Because we have the IgnoreImpCasts now, it will fail the type check because D now is of floating point type, and we will emit an error to user.
For users, it might be confusing because on one hand we emit a warning saying the floating point value has been casted, and on the other hand in Sema we tell users it is expected an integer. Users might be thinking, you already cast it to integer, why do you tell me it's a floating point value again?

[ABataev]

clang/lib/CodeGen/CGStmtOpenMP.cpp

6041

If you don't need it, do not call it. Why do you need this rvalue?

clang/lib/Sema/SemaOpenMP.cpp

11180

Yiu have the resulting type from the whole expression. You van do explicit cast to this resulting type to avoid problems, if I got it correctly

[tianshilei1992]

clang/test/OpenMP/atomic_compare_codegen.cpp

1991

I have to get it passed to IRBuilder, which accepts a llvm::Value *.

[ABataev]

clang/test/OpenMP/atomic_compare_codegen.cpp

1991

Modify irbuilder to not require it in some cases.

[tianshilei1992]

clang/test/OpenMP/atomic_compare_codegen.cpp

1991

You got me wrong. I need to call a function to convert a rvalue Express * to llvm::Value *. CGF.EmitScalarExpr can do it. Actually now I feel the load here can not be avoided as we want a scalar value instead of a pointer.

[tianshilei1992]

final touch before landing

clang/include/clang/AST/StmtOpenMP.h

explicit OMPAtomicDirective()
       : OMPExecutableDirective(OMPAtomicDirectiveClass, llvm::omp::OMPD_atomic,
                                SourceLocation(), SourceLocation()) {}
 
   enum DataPositionTy : size_t {
     POS_X = 0,
     POS_V,
     POS_E,
     POS_UpdateExpr,
+    POS_D,
+    POS_Cond,
   };
 
   /// Set 'x' part of the associated expression/statement.
   void setX(Expr *X) { Data->getChildren()[DataPositionTy::POS_X] = X; }
   /// Set helper expression of the form
   /// 'OpaqueValueExpr(x) binop OpaqueValueExpr(expr)' or
   /// 'OpaqueValueExpr(expr) binop OpaqueValueExpr(x)'.
   void setUpdateExpr(Expr *UE) {
     Data->getChildren()[DataPositionTy::POS_UpdateExpr] = UE;
   }
   /// Set 'v' part of the associated expression/statement.
   void setV(Expr *V) { Data->getChildren()[DataPositionTy::POS_V] = V; }
   /// Set 'expr' part of the associated expression/statement.
   void setExpr(Expr *E) { Data->getChildren()[DataPositionTy::POS_E] = E; }
+  /// Set 'd' part of the associated expression/statement.
+  void setD(Expr *D) { Data->getChildren()[DataPositionTy::POS_D] = D; }
+  /// Set conditional expression in `atomic compare`.
+  void setCond(Expr *C) { Data->getChildren()[DataPositionTy::POS_Cond] = C; }
 
 public:
   /// Creates directive with a list of \a Clauses and 'x', 'v' and 'expr'
   /// parts of the atomic construct (see Section 2.12.6, atomic Construct, for
   /// detailed description of 'x', 'v' and 'expr').
   ///
   /// \param C AST context.
   /// \param StartLoc Starting location of the directive kind.
   /// \param EndLoc Ending Location of the directive.
   /// \param Clauses List of clauses.
   /// \param AssociatedStmt Statement, associated with the directive.
   /// \param X 'x' part of the associated expression/statement.
   /// \param V 'v' part of the associated expression/statement.
   /// \param E 'expr' part of the associated expression/statement.
   /// \param UE Helper expression of the form
   /// 'OpaqueValueExpr(x) binop OpaqueValueExpr(expr)' or
   /// 'OpaqueValueExpr(expr) binop OpaqueValueExpr(x)'.
+  /// \param D 'd' part of the associated expression/statement.
+  /// \param Cond Conditional expression in `atomic compare` construct.
   /// \param IsXLHSInRHSPart true if \a UE has the first form and false if the
   /// second.
   /// \param IsPostfixUpdate true if original value of 'x' must be stored in
   /// 'v', not an updated one.
   static OMPAtomicDirective *
   Create(const ASTContext &C, SourceLocation StartLoc, SourceLocation EndLoc,
          ArrayRef<OMPClause *> Clauses, Stmt *AssociatedStmt, Expr *X, Expr *V,
-         Expr *E, Expr *UE, bool IsXLHSInRHSPart, bool IsPostfixUpdate);
+         Expr *E, Expr *UE, Expr *D, Expr *Cond, bool IsXLHSInRHSPart,
+         bool IsPostfixUpdate);
 
   /// Creates an empty directive with the place for \a NumClauses
   /// clauses.
   ///
   /// \param C AST context.
   /// \param NumClauses Number of clauses.
   ///
   static OMPAtomicDirective *CreateEmpty(const ASTContext &C,
public:
   }
   /// Get 'expr' part of the associated expression/statement.
   Expr *getExpr() {
     return cast_or_null<Expr>(Data->getChildren()[DataPositionTy::POS_E]);
   }
   const Expr *getExpr() const {
     return cast_or_null<Expr>(Data->getChildren()[DataPositionTy::POS_E]);
   }
+  /// Get 'd' part of the associated expression/statement.
+  Expr *getD() {
+    return cast_or_null<Expr>(Data->getChildren()[DataPositionTy::POS_D]);
+  }
+  Expr *getD() const {
+    return cast_or_null<Expr>(Data->getChildren()[DataPositionTy::POS_D]);
+  }
+  /// Get
+  Expr *getCondExpr() {
+    return cast_or_null<Expr>(Data->getChildren()[DataPositionTy::POS_Cond]);
+  }
+  Expr *getCondExpr() const {
+    return cast_or_null<Expr>(Data->getChildren()[DataPositionTy::POS_Cond]);
+  }
 
   static bool classof(const Stmt *T) {
     return T->getStmtClass() == OMPAtomicDirectiveClass;
   }
 };
 
 /// This represents '#pragma omp target' directive.
 ///

clang/lib/AST/StmtOpenMP.cpp

 OMPOrderedDirective *OMPOrderedDirective::CreateEmpty(const ASTContext &C,
                                                       unsigned NumClauses,
                                                       bool IsStandalone,
                                                       EmptyShell) {
   return createEmptyDirective<OMPOrderedDirective>(C, NumClauses,
                                                    !IsStandalone);
 }
 
-OMPAtomicDirective *OMPAtomicDirective::Create(
-    const ASTContext &C, SourceLocation StartLoc, SourceLocation EndLoc,
-    ArrayRef<OMPClause *> Clauses, Stmt *AssociatedStmt, Expr *X, Expr *V,
-    Expr *E, Expr *UE, bool IsXLHSInRHSPart, bool IsPostfixUpdate) {
+OMPAtomicDirective *
+OMPAtomicDirective::Create(const ASTContext &C, SourceLocation StartLoc,
+                           SourceLocation EndLoc, ArrayRef<OMPClause *> Clauses,
+                           Stmt *AssociatedStmt, Expr *X, Expr *V, Expr *E,
+                           Expr *UE, Expr *D, Expr *Cond, bool IsXLHSInRHSPart,
+                           bool IsPostfixUpdate) {
   auto *Dir = createDirective<OMPAtomicDirective>(
-      C, Clauses, AssociatedStmt, /*NumChildren=*/4, StartLoc, EndLoc);
+      C, Clauses, AssociatedStmt, /*NumChildren=*/6, StartLoc, EndLoc);
   Dir->setX(X);
   Dir->setV(V);
   Dir->setExpr(E);
   Dir->setUpdateExpr(UE);
+  Dir->setD(D);
+  Dir->setCond(Cond);
   Dir->IsXLHSInRHSPart = IsXLHSInRHSPart;
   Dir->IsPostfixUpdate = IsPostfixUpdate;
   return Dir;
 }
 
 OMPAtomicDirective *OMPAtomicDirective::CreateEmpty(const ASTContext &C,
                                                     unsigned NumClauses,
                                                     EmptyShell) {

clang/lib/CodeGen/CGStmtOpenMP.cpp

case llvm::AtomicOrdering::Monotonic:
       break;
     case llvm::AtomicOrdering::NotAtomic:
     case llvm::AtomicOrdering::Unordered:
       llvm_unreachable("Unexpected ordering.");
     }
   }
 }
 
+static void emitOMPAtomicCompareExpr(CodeGenFunction &CGF,
+                                     llvm::AtomicOrdering AO, const Expr *X,
+                                     const Expr *E, const Expr *D,
+                                     const Expr *CE, bool IsXBinopExpr,
+                                     SourceLocation Loc) {
+
+  llvm::OpenMPIRBuilder &OMPBuilder =
+      CGF.CGM.getOpenMPRuntime().getOMPBuilder();
+
+  OMPAtomicCompareOp Op;
+  assert(isa<BinaryOperator>(CE) && "CE is not a BinaryOperator");
+  switch (cast<BinaryOperator>(CE)->getOpcode()) {
+  case BO_EQ:
+    Op = OMPAtomicCompareOp::EQ;
+    break;
+  case BO_LT:
+    Op = OMPAtomicCompareOp::MIN;
+    break;
+  case BO_GT:
+    Op = OMPAtomicCompareOp::MAX;
+    break;
+  default:
+    llvm_unreachable("unsupported atomic compare binary operator");
+  }
+
+  LValue XLVal = CGF.EmitLValue(X);
+  llvm::Value *XPtr = XLVal.getPointer(CGF);
+  llvm::Value *EVal = CGF.EmitScalarExpr(E->IgnoreImpCasts());
+  llvm::Value *DVal = D ? CGF.EmitScalarExpr(D->IgnoreImpCasts()) : nullptr;
+
+  llvm::OpenMPIRBuilder::AtomicOpValue XOpVal{
+      XPtr, XPtr->getType()->getPointerElementType(),
+      X->getType().isVolatileQualified(),
+      X->getType()->hasSignedIntegerRepresentation()};
+
+  CGF.Builder.restoreIP(OMPBuilder.createAtomicCompare(
+      CGF.Builder, XOpVal, EVal, DVal, AO, Op, IsXBinopExpr));
+}
+
 static void emitOMPAtomicExpr(CodeGenFunction &CGF, OpenMPClauseKind Kind,
                               llvm::AtomicOrdering AO, bool IsPostfixUpdate,
                               const Expr *X, const Expr *V, const Expr *E,
-                              const Expr *UE, bool IsXLHSInRHSPart,
-                              SourceLocation Loc) {
+                              const Expr *UE, const Expr *D, const Expr *CE,
+                              bool IsXLHSInRHSPart, SourceLocation Loc) {
   switch (Kind) {
   case OMPC_read:
     emitOMPAtomicReadExpr(CGF, AO, X, V, Loc);
     break;
   case OMPC_write:
     emitOMPAtomicWriteExpr(CGF, AO, X, E, Loc);
     break;
   case OMPC_unknown:
   case OMPC_update:
     emitOMPAtomicUpdateExpr(CGF, AO, X, E, UE, IsXLHSInRHSPart, Loc);
     break;
   case OMPC_capture:
     emitOMPAtomicCaptureExpr(CGF, AO, IsPostfixUpdate, V, X, E, UE,
                              IsXLHSInRHSPart, Loc);
     break;
-  case OMPC_compare: {
-    // Emit an error here.
-    unsigned DiagID = CGF.CGM.getDiags().getCustomDiagID(
-        DiagnosticsEngine::Error, "'atomic compare' is not supported for now");
-    CGF.CGM.getDiags().Report(DiagID);
+  case OMPC_compare:
+    emitOMPAtomicCompareExpr(CGF, AO, X, E, D, CE, IsXLHSInRHSPart, Loc);
     break;
-  }
   case OMPC_if:
   case OMPC_final:
   case OMPC_num_threads:
   case OMPC_private:
   case OMPC_firstprivate:
   case OMPC_lastprivate:
   case OMPC_reduction:
   case OMPC_task_reduction:
if (DefaultOrder == llvm::AtomicOrdering::Monotonic ||
         AO = llvm::AtomicOrdering::Acquire;
       }
     }
   }
 
   LexicalScope Scope(*this, S.getSourceRange());
   EmitStopPoint(S.getAssociatedStmt());
   emitOMPAtomicExpr(*this, Kind, AO, S.isPostfixUpdate(), S.getX(), S.getV(),
-                    S.getExpr(), S.getUpdateExpr(), S.isXLHSInRHSPart(),
-                    S.getBeginLoc());
+                    S.getExpr(), S.getUpdateExpr(), S.getD(), S.getCondExpr(),
+                    S.isXLHSInRHSPart(), S.getBeginLoc());
 }
 
 static void emitCommonOMPTargetDirective(CodeGenFunction &CGF,
                                          const OMPExecutableDirective &S,
                                          const RegionCodeGenTy &CodeGen) {
   assert(isOpenMPTargetExecutionDirective(S.getDirectiveKind()));
   CodeGenModule &CGM = CGF.CGM;
 

clang/lib/Sema/SemaOpenMP.cpp

default:
     ErrorInfo.Error = ErrorTy::InvalidBinaryOp;
     ErrorInfo.ErrorLoc = ErrorInfo.NoteLoc = Cond->getExprLoc();
     ErrorInfo.ErrorRange = ErrorInfo.NoteRange = Cond->getSourceRange();
     return false;
   }
 
   if (Cond->getOpcode() == BO_EQ) {
     C = Cond;
     D = CO->getTrueExpr();
     if (checkIfTwoExprsAreSame(ContextRef, X, Cond->getLHS())) {
       E = Cond->getRHS();
     } else if (checkIfTwoExprsAreSame(ContextRef, X, Cond->getRHS())) {
       E = Cond->getLHS();
     } else {
       ErrorInfo.Error = ErrorTy::InvalidComparison;
       ErrorInfo.ErrorLoc = ErrorInfo.NoteLoc = Cond->getExprLoc();
       ErrorInfo.ErrorRange = ErrorInfo.NoteRange = Cond->getSourceRange();
StmtResult Sema::ActOnOpenMPAtomicDirective(ArrayRef<OMPClause *> Clauses,
   Stmt *Body = AStmt;
   if (auto *EWC = dyn_cast<ExprWithCleanups>(Body))
     Body = EWC->getSubExpr();
 
   Expr *X = nullptr;
   Expr *V = nullptr;
   Expr *E = nullptr;
   Expr *UE = nullptr;
+  Expr *D = nullptr;
+  Expr *CE = nullptr;
   bool IsXLHSInRHSPart = false;
   bool IsPostfixUpdate = false;
   // OpenMP [2.12.6, atomic Construct]
   // In the next expressions:
   // * x and v (as applicable) are both l-value expressions with scalar type.
   // * During the execution of an atomic region, multiple syntactic
   // occurrences of x must designate the same storage location.
   // * Neither of v and expr (as applicable) may access the storage location
if (AtomicKind == OMPC_read) {
     OpenMPAtomicCompareChecker Checker(*this);
     if (!Checker.checkStmt(Body, ErrorInfo)) {
       Diag(ErrorInfo.ErrorLoc, diag::err_omp_atomic_compare)
           << ErrorInfo.ErrorRange;
       Diag(ErrorInfo.NoteLoc, diag::note_omp_atomic_compare)
           << ErrorInfo.Error << ErrorInfo.NoteRange;
       return StmtError();
     }
-    // TODO: We don't set X, D, E, etc. here because in code gen we will emit
-    // error directly.
+    X = Checker.getX();
+    E = Checker.getE();
+    D = Checker.getD();
+    CE = Checker.getCond();
+    // We reuse this bool variable to tell if it is in the form 'x ordop expr'.
+    IsXLHSInRHSPart = Checker.isXBinopExpr();
   }
 
   setFunctionHasBranchProtectedScope();
 
   return OMPAtomicDirective::Create(Context, StartLoc, EndLoc, Clauses, AStmt,
-                                    X, V, E, UE, IsXLHSInRHSPart,
+                                    X, V, E, UE, D, CE, IsXLHSInRHSPart,
                                     IsPostfixUpdate);
 }
 
 StmtResult Sema::ActOnOpenMPTargetDirective(ArrayRef<OMPClause *> Clauses,
                                             Stmt *AStmt,
                                             SourceLocation StartLoc,
                                             SourceLocation EndLoc) {
   if (!AStmt)

clang/test/OpenMP/atomic_compare_codegen.cpp

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
+// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp -fopenmp-version=51 -x c -emit-llvm %s -o - | FileCheck %s
+// %clang_cc1 -fopenmp -fopenmp-version=51 -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s
+// %clang_cc1 -fopenmp -fopenmp-version=51 -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s
+
+// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp-simd -fopenmp-version=51 -x c -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
+// %clang_cc1 -fopenmp-simd -fopenmp-version=51 -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s
+// %clang_cc1 -fopenmp-simd -fopenmp-version=51 -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
+// expected-no-diagnostics
+
+#ifndef HEADER
+#define HEADER
+
+void foo() {
+  char cx, ce, cd;
+  unsigned char ucx, uce, ucd;
+  short sx, se, sd;
+  unsigned short usx, use, usd;
+  int ix, ie, id;
+  unsigned int uix, uie, uid;
+  long lx, le, ld;
+  unsigned long ulx, ule, uld;
+  long long llx, lle, lld;
+  unsigned long long ullx, ulle, ulld;
+  float fx, fe, fd;
+  double dx, de, dd;
+
+#pragma omp atomic compare
+  cx = cx > ce ? ce : cx;
+#pragma omp atomic compare
+  cx = cx < ce ? ce : cx;
+#pragma omp atomic compare
+  cx = ce > cx ? ce : cx;
+#pragma omp atomic compare
+  cx = ce < cx ? ce : cx;
+#pragma omp atomic compare
+  if (cx > ce)
+    cx = ce;
+#pragma omp atomic compare
+  if (cx < ce)
+    cx = ce;
+#pragma omp atomic compare
+  if (ce > cx)
+    cx = ce;
+#pragma omp atomic compare
+  if (ce < cx)
+    cx = ce;
+
+#pragma omp atomic compare
+  cx = cx == ce ? cd : cx;
+#pragma omp atomic compare
+  cx = ce == cx ? cd : cx;
+#pragma omp atomic compare
+  if (cx == ce)
+    cx = cd;
+#pragma omp atomic compare
+  if (ce == cx)
+    cx = cd;
+
+#pragma omp atomic compare
+  ucx = ucx > uce ? uce : ucx;
+#pragma omp atomic compare
+  ucx = ucx < uce ? uce : ucx;
+#pragma omp atomic compare
+  ucx = uce > ucx ? uce : ucx;
+#pragma omp atomic compare
+  ucx = uce < ucx ? uce : ucx;
+#pragma omp atomic compare
+  if (ucx > uce)
+    ucx = uce;
+#pragma omp atomic compare
+  if (ucx < uce)
+    ucx = uce;
+#pragma omp atomic compare
+  if (uce > ucx)
+    ucx = uce;
+#pragma omp atomic compare
+  if (uce < ucx)
+    ucx = uce;
+
+#pragma omp atomic compare
+  ucx = ucx == uce ? ucd : ucx;
+#pragma omp atomic compare
+  ucx = uce == ucx ? ucd : ucx;
+#pragma omp atomic compare
+  if (ucx == uce)
+    ucx = ucd;
+#pragma omp atomic compare
+  if (uce == ucx)
+    ucx = ucd;
+
+#pragma omp atomic compare acq_rel
+  cx = cx > ce ? ce : cx;
+#pragma omp atomic compare acq_rel
+  cx = cx < ce ? ce : cx;
+#pragma omp atomic compare acq_rel
+  cx = ce > cx ? ce : cx;
+#pragma omp atomic compare acq_rel
+  cx = ce < cx ? ce : cx;
+#pragma omp atomic compare acq_rel
+  if (cx > ce)
+    cx = ce;
+#pragma omp atomic compare acq_rel
+  if (cx < ce)
+    cx = ce;
+#pragma omp atomic compare acq_rel
+  if (ce > cx)
+    cx = ce;
+#pragma omp atomic compare acq_rel
+  if (ce < cx)
+    cx = ce;
+
+#pragma omp atomic compare acq_rel
+  cx = cx == ce ? cd : cx;
+#pragma omp atomic compare acq_rel
+  cx = ce == cx ? cd : cx;
+#pragma omp atomic compare acq_rel
+  if (cx == ce)
+    cx = cd;
+#pragma omp atomic compare acq_rel
+  if (ce == cx)
+    cx = cd;
+
+#pragma omp atomic compare acq_rel
+  ucx = ucx > uce ? uce : ucx;
+#pragma omp atomic compare acq_rel
+  ucx = ucx < uce ? uce : ucx;
+#pragma omp atomic compare acq_rel
+  ucx = uce > ucx ? uce : ucx;
+#pragma omp atomic compare acq_rel
+  ucx = uce < ucx ? uce : ucx;
+#pragma omp atomic compare acq_rel
+  if (ucx > uce)
+    ucx = uce;
+#pragma omp atomic compare acq_rel
+  if (ucx < uce)
+    ucx = uce;
+#pragma omp atomic compare acq_rel
+  if (uce > ucx)
+    ucx = uce;
+#pragma omp atomic compare acq_rel
+  if (uce < ucx)
+    ucx = uce;
+
+#pragma omp atomic compare acq_rel
+  ucx = ucx == uce ? ucd : ucx;
+#pragma omp atomic compare acq_rel
+  ucx = uce == ucx ? ucd : ucx;
+#pragma omp atomic compare acq_rel
+  if (ucx == uce)
+    ucx = ucd;
+#pragma omp atomic compare acq_rel
+  if (uce == ucx)
+    ucx = ucd;
+
+#pragma omp atomic compare acquire
+  cx = cx > ce ? ce : cx;
+#pragma omp atomic compare acquire
+  cx = cx < ce ? ce : cx;
+#pragma omp atomic compare acquire
+  cx = ce > cx ? ce : cx;
+#pragma omp atomic compare acquire
+  cx = ce < cx ? ce : cx;
+#pragma omp atomic compare acquire
+  if (cx > ce)
+    cx = ce;
+#pragma omp atomic compare acquire
+  if (cx < ce)
+    cx = ce;
+#pragma omp atomic compare acquire
+  if (ce > cx)
+    cx = ce;
+#pragma omp atomic compare acquire
+  if (ce < cx)
+    cx = ce;
+
+#pragma omp atomic compare acquire
+  cx = cx == ce ? cd : cx;
+#pragma omp atomic compare acquire
+  cx = ce == cx ? cd : cx;
+#pragma omp atomic compare acquire
+  if (cx == ce)
+    cx = cd;
+#pragma omp atomic compare acquire
+  if (ce == cx)
+    cx = cd;
+
+#pragma omp atomic compare acquire
+  ucx = ucx > uce ? uce : ucx;
+#pragma omp atomic compare acquire
+  ucx = ucx < uce ? uce : ucx;
+#pragma omp atomic compare acquire
+  ucx = uce > ucx ? uce : ucx;
+#pragma omp atomic compare acquire
+  ucx = uce < ucx ? uce : ucx;
+#pragma omp atomic compare acquire
+  if (ucx > uce)
+    ucx = uce;
+#pragma omp atomic compare acquire
+  if (ucx < uce)
+    ucx = uce;
+#pragma omp atomic compare acquire
+  if (uce > ucx)
+    ucx = uce;
+#pragma omp atomic compare acquire
+  if (uce < ucx)
+    ucx = uce;
+
+#pragma omp atomic compare acquire
+  ucx = ucx == uce ? ucd : ucx;
+#pragma omp atomic compare acquire
+  ucx = uce == ucx ? ucd : ucx;
+#pragma omp atomic compare acquire
+  if (ucx == uce)
+    ucx = ucd;
+#pragma omp atomic compare acquire
+  if (uce == ucx)
+    ucx = ucd;
+
+#pragma omp atomic compare relaxed
+  cx = cx > ce ? ce : cx;
+#pragma omp atomic compare relaxed
+  cx = cx < ce ? ce : cx;
+#pragma omp atomic compare relaxed
+  cx = ce > cx ? ce : cx;
+#pragma omp atomic compare relaxed
+  cx = ce < cx ? ce : cx;
+#pragma omp atomic compare relaxed
+  if (cx > ce)
+    cx = ce;
+#pragma omp atomic compare relaxed
+  if (cx < ce)
+    cx = ce;
+#pragma omp atomic compare relaxed
+  if (ce > cx)
+    cx = ce;
+#pragma omp atomic compare relaxed
+  if (ce < cx)
+    cx = ce;
+
+#pragma omp atomic compare relaxed
+  cx = cx == ce ? cd : cx;
+#pragma omp atomic compare relaxed
+  cx = ce == cx ? cd : cx;
+#pragma omp atomic compare relaxed
+  if (cx == ce)
+    cx = cd;
+#pragma omp atomic compare relaxed
+  if (ce == cx)
+    cx = cd;
+
+#pragma omp atomic compare relaxed
+  ucx = ucx > uce ? uce : ucx;
+#pragma omp atomic compare relaxed
+  ucx = ucx < uce ? uce : ucx;
+#pragma omp atomic compare relaxed
+  ucx = uce > ucx ? uce : ucx;
+#pragma omp atomic compare relaxed
+  ucx = uce < ucx ? uce : ucx;
+#pragma omp atomic compare relaxed
+  if (ucx > uce)
+    ucx = uce;
+#pragma omp atomic compare relaxed
+  if (ucx < uce)
+    ucx = uce;
+#pragma omp atomic compare relaxed
+  if (uce > ucx)
+    ucx = uce;
+#pragma omp atomic compare relaxed
+  if (uce < ucx)
+    ucx = uce;
+
+#pragma omp atomic compare relaxed
+  ucx = ucx == uce ? ucd : ucx;
+#pragma omp atomic compare relaxed
+  ucx = uce == ucx ? ucd : ucx;
+#pragma omp atomic compare relaxed
+  if (ucx == uce)
+    ucx = ucd;
+#pragma omp atomic compare relaxed
+  if (uce == ucx)
+    ucx = ucd;
+
+#pragma omp atomic compare release
+  cx = cx > ce ? ce : cx;
+#pragma omp atomic compare release
+  cx = cx < ce ? ce : cx;
+#pragma omp atomic compare release
+  cx = ce > cx ? ce : cx;
+#pragma omp atomic compare release
+  cx = ce < cx ? ce : cx;
+#pragma omp atomic compare release
+  if (cx > ce)
+    cx = ce;
+#pragma omp atomic compare release
+  if (cx < ce)
+    cx = ce;
+#pragma omp atomic compare release
+  if (ce > cx)
+    cx = ce;
+#pragma omp atomic compare release
+  if (ce < cx)
+    cx = ce;
+
+#pragma omp atomic compare release
+  cx = cx == ce ? cd : cx;
+#pragma omp atomic compare release
+  cx = ce == cx ? cd : cx;
+#pragma omp atomic compare release
+  if (cx == ce)
+    cx = cd;
+#pragma omp atomic compare release
+  if (ce == cx)
+    cx = cd;
+
+#pragma omp atomic compare release
+  ucx = ucx > uce ? uce : ucx;
+#pragma omp atomic compare release
+  ucx = ucx < uce ? uce : ucx;
+#pragma omp atomic compare release
+  ucx = uce > ucx ? uce : ucx;
+#pragma omp atomic compare release
+  ucx = uce < ucx ? uce : ucx;
+#pragma omp atomic compare release
+  if (ucx > uce)
+    ucx = uce;
+#pragma omp atomic compare release
+  if (ucx < uce)
+    ucx = uce;
+#pragma omp atomic compare release
+  if (uce > ucx)
+    ucx = uce;
+#pragma omp atomic compare release
+  if (uce < ucx)
+    ucx = uce;
+
+#pragma omp atomic compare release
+  ucx = ucx == uce ? ucd : ucx;
+#pragma omp atomic compare release
+  ucx = uce == ucx ? ucd : ucx;
+#pragma omp atomic compare release
+  if (ucx == uce)
+    ucx = ucd;
+#pragma omp atomic compare release
+  if (uce == ucx)
+    ucx = ucd;
+
+#pragma omp atomic compare seq_cst
+  cx = cx > ce ? ce : cx;
+#pragma omp atomic compare seq_cst
+  cx = cx < ce ? ce : cx;
+#pragma omp atomic compare seq_cst
+  cx = ce > cx ? ce : cx;
+#pragma omp atomic compare seq_cst
+  cx = ce < cx ? ce : cx;
+#pragma omp atomic compare seq_cst
+  if (cx > ce)
+    cx = ce;
+#pragma omp atomic compare seq_cst
+  if (cx < ce)
+    cx = ce;
+#pragma omp atomic compare seq_cst
+  if (ce > cx)
+    cx = ce;
+#pragma omp atomic compare seq_cst
+  if (ce < cx)
+    cx = ce;
+
+#pragma omp atomic compare seq_cst
+  cx = cx == ce ? cd : cx;
+#pragma omp atomic compare seq_cst
+  cx = ce == cx ? cd : cx;
+#pragma omp atomic compare seq_cst
+  if (cx == ce)
+    cx = cd;
+#pragma omp atomic compare seq_cst
+  if (ce == cx)
+    cx = cd;
+
+#pragma omp atomic compare seq_cst
+  ucx = ucx > uce ? uce : ucx;
+#pragma omp atomic compare seq_cst
+  ucx = ucx < uce ? uce : ucx;
+#pragma omp atomic compare seq_cst
+  ucx = uce > ucx ? uce : ucx;
+#pragma omp atomic compare seq_cst
+  ucx = uce < ucx ? uce : ucx;
+#pragma omp atomic compare seq_cst
+  if (ucx > uce)
+    ucx = uce;
+#pragma omp atomic compare seq_cst
+  if (ucx < uce)
+    ucx = uce;
+#pragma omp atomic compare seq_cst
+  if (uce > ucx)
+    ucx = uce;
+#pragma omp atomic compare seq_cst
+  if (uce < ucx)
+    ucx = uce;
+
+#pragma omp atomic compare seq_cst
+  ucx = ucx == uce ? ucd : ucx;
+#pragma omp atomic compare seq_cst
+  ucx = uce == ucx ? ucd : ucx;
+#pragma omp atomic compare seq_cst
+  if (ucx == uce)
+    ucx = ucd;
+#pragma omp atomic compare seq_cst
+  if (uce == ucx)
+    ucx = ucd;
+
+#pragma omp atomic compare
+  sx = sx > se ? se : sx;
+#pragma omp atomic compare
+  sx = sx < se ? se : sx;
+#pragma omp atomic compare
+  sx = se > sx ? se : sx;
+#pragma omp atomic compare
+  sx = se < sx ? se : sx;
+#pragma omp atomic compare
+  if (sx > se)
+    sx = se;
+#pragma omp atomic compare
+  if (sx < se)
+    sx = se;
+#pragma omp atomic compare
+  if (se > sx)
+    sx = se;
+#pragma omp atomic compare
+  if (se < sx)
+    sx = se;
+
+#pragma omp atomic compare
+  sx = sx == se ? sd : sx;
+#pragma omp atomic compare
+  sx = se == sx ? sd : sx;
+#pragma omp atomic compare
+  if (sx == se)
+    sx = sd;
+#pragma omp atomic compare
+  if (se == sx)
+    sx = sd;
+
+#pragma omp atomic compare
+  usx = usx > use ? use : usx;
+#pragma omp atomic compare
+  usx = usx < use ? use : usx;
+#pragma omp atomic compare
+  usx = use > usx ? use : usx;
+#pragma omp atomic compare
+  usx = use < usx ? use : usx;
+#pragma omp atomic compare
+  if (usx > use)
+    usx = use;
+#pragma omp atomic compare
+  if (usx < use)
+    usx = use;
+#pragma omp atomic compare
+  if (use > usx)
+    usx = use;
+#pragma omp atomic compare
+  if (use < usx)
+    usx = use;
+
+#pragma omp atomic compare
+  usx = usx == use ? usd : usx;
+#pragma omp atomic compare
+  usx = use == usx ? usd : usx;
+#pragma omp atomic compare
+  if (usx == use)
+    usx = usd;
+#pragma omp atomic compare
+  if (use == usx)
+    usx = usd;
+
+#pragma omp atomic compare acq_rel
+  sx = sx > se ? se : sx;
+#pragma omp atomic compare acq_rel
+  sx = sx < se ? se : sx;
+#pragma omp atomic compare acq_rel
+  sx = se > sx ? se : sx;
+#pragma omp atomic compare acq_rel
+  sx = se < sx ? se : sx;
+#pragma omp atomic compare acq_rel
+  if (sx > se)
+    sx = se;
+#pragma omp atomic compare acq_rel
+  if (sx < se)
+    sx = se;
+#pragma omp atomic compare acq_rel
+  if (se > sx)
+    sx = se;
+#pragma omp atomic compare acq_rel
+  if (se < sx)
+    sx = se;
+
+#pragma omp atomic compare acq_rel
+  sx = sx == se ? sd : sx;
+#pragma omp atomic compare acq_rel
+  sx = se == sx ? sd : sx;
+#pragma omp atomic compare acq_rel
+  if (sx == se)
+    sx = sd;
+#pragma omp atomic compare acq_rel
+  if (se == sx)
+    sx = sd;
+
+#pragma omp atomic compare acq_rel
+  usx = usx > use ? use : usx;
+#pragma omp atomic compare acq_rel
+  usx = usx < use ? use : usx;
+#pragma omp atomic compare acq_rel
+  usx = use > usx ? use : usx;
+#pragma omp atomic compare acq_rel
+  usx = use < usx ? use : usx;
+#pragma omp atomic compare acq_rel
+  if (usx > use)
+    usx = use;
+#pragma omp atomic compare acq_rel
+  if (usx < use)
+    usx = use;
+#pragma omp atomic compare acq_rel
+  if (use > usx)
+    usx = use;
+#pragma omp atomic compare acq_rel
+  if (use < usx)
+    usx = use;
+
+#pragma omp atomic compare acq_rel
+  usx = usx == use ? usd : usx;
+#pragma omp atomic compare acq_rel
+  usx = use == usx ? usd : usx;
+#pragma omp atomic compare acq_rel
+  if (usx == use)
+    usx = usd;
+#pragma omp atomic compare acq_rel
+  if (use == usx)
+    usx = usd;
+
+#pragma omp atomic compare acquire
+  sx = sx > se ? se : sx;
+#pragma omp atomic compare acquire
+  sx = sx < se ? se : sx;
+#pragma omp atomic compare acquire
+  sx = se > sx ? se : sx;
+#pragma omp atomic compare acquire
+  sx = se < sx ? se : sx;
+#pragma omp atomic compare acquire
+  if (sx > se)
+    sx = se;
+#pragma omp atomic compare acquire
+  if (sx < se)
+    sx = se;
+#pragma omp atomic compare acquire
+  if (se > sx)
+    sx = se;
+#pragma omp atomic compare acquire
+  if (se < sx)
+    sx = se;
+
+#pragma omp atomic compare acquire
+  sx = sx == se ? sd : sx;
+#pragma omp atomic compare acquire
+  sx = se == sx ? sd : sx;
+#pragma omp atomic compare acquire
+  if (sx == se)
+    sx = sd;
+#pragma omp atomic compare acquire
+  if (se == sx)
+    sx = sd;
+
+#pragma omp atomic compare acquire
+  usx = usx > use ? use : usx;
+#pragma omp atomic compare acquire
+  usx = usx < use ? use : usx;
+#pragma omp atomic compare acquire
+  usx = use > usx ? use : usx;
+#pragma omp atomic compare acquire
+  usx = use < usx ? use : usx;
+#pragma omp atomic compare acquire
+  if (usx > use)
+    usx = use;
+#pragma omp atomic compare acquire
+  if (usx < use)
+    usx = use;
+#pragma omp atomic compare acquire
+  if (use > usx)
+    usx = use;
+#pragma omp atomic compare acquire
+  if (use < usx)
+    usx = use;
+
+#pragma omp atomic compare acquire
+  usx = usx == use ? usd : usx;
+#pragma omp atomic compare acquire
+  usx = use == usx ? usd : usx;
+#pragma omp atomic compare acquire
+  if (usx == use)
+    usx = usd;
+#pragma omp atomic compare acquire
+  if (use == usx)
+    usx = usd;
+
+#pragma omp atomic compare relaxed
+  sx = sx > se ? se : sx;
+#pragma omp atomic compare relaxed
+  sx = sx < se ? se : sx;
+#pragma omp atomic compare relaxed
+  sx = se > sx ? se : sx;
+#pragma omp atomic compare relaxed
+  sx = se < sx ? se : sx;
+#pragma omp atomic compare relaxed
+  if (sx > se)
+    sx = se;
+#pragma omp atomic compare relaxed
+  if (sx < se)
+    sx = se;
+#pragma omp atomic compare relaxed
+  if (se > sx)
+    sx = se;
+#pragma omp atomic compare relaxed
+  if (se < sx)
+    sx = se;
+
+#pragma omp atomic compare relaxed
+  sx = sx == se ? sd : sx;
+#pragma omp atomic compare relaxed
+  sx = se == sx ? sd : sx;
+#pragma omp atomic compare relaxed
+  if (sx == se)
+    sx = sd;
+#pragma omp atomic compare relaxed
+  if (se == sx)
+    sx = sd;
+
+#pragma omp atomic compare relaxed
+  usx = usx > use ? use : usx;
+#pragma omp atomic compare relaxed
+  usx = usx < use ? use : usx;
+#pragma omp atomic compare relaxed
+  usx = use > usx ? use : usx;
+#pragma omp atomic compare relaxed
+  usx = use < usx ? use : usx;
+#pragma omp atomic compare relaxed
+  if (usx > use)
+    usx = use;
+#pragma omp atomic compare relaxed
+  if (usx < use)
+    usx = use;
+#pragma omp atomic compare relaxed
+  if (use > usx)
+    usx = use;
+#pragma omp atomic compare relaxed
+  if (use < usx)
+    usx = use;
+
+#pragma omp atomic compare relaxed
+  usx = usx == use ? usd : usx;
+#pragma omp atomic compare relaxed
+  usx = use == usx ? usd : usx;
+#pragma omp atomic compare relaxed
+  if (usx == use)
+    usx = usd;
+#pragma omp atomic compare relaxed
+  if (use == usx)
+    usx = usd;
+
+#pragma omp atomic compare release
+  sx = sx > se ? se : sx;
+#pragma omp atomic compare release
+  sx = sx < se ? se : sx;
+#pragma omp atomic compare release
+  sx = se > sx ? se : sx;
+#pragma omp atomic compare release
+  sx = se < sx ? se : sx;
+#pragma omp atomic compare release
+  if (sx > se)
+    sx = se;
+#pragma omp atomic compare release
+  if (sx < se)
+    sx = se;
+#pragma omp atomic compare release
+  if (se > sx)
+    sx = se;
+#pragma omp atomic compare release
+  if (se < sx)
+    sx = se;
+
+#pragma omp atomic compare release
+  sx = sx == se ? sd : sx;
+#pragma omp atomic compare release
+  sx = se == sx ? sd : sx;
+#pragma omp atomic compare release
+  if (sx == se)
+    sx = sd;
+#pragma omp atomic compare release
+  if (se == sx)
+    sx = sd;
+
+#pragma omp atomic compare release
+  usx = usx > use ? use : usx;
+#pragma omp atomic compare release
+  usx = usx < use ? use : usx;
+#pragma omp atomic compare release
+  usx = use > usx ? use : usx;
+#pragma omp atomic compare release
+  usx = use < usx ? use : usx;
+#pragma omp atomic compare release
+  if (usx > use)
+    usx = use;
+#pragma omp atomic compare release
+  if (usx < use)
+    usx = use;
+#pragma omp atomic compare release
+  if (use > usx)
+    usx = use;
+#pragma omp atomic compare release
+  if (use < usx)
+    usx = use;
+
+#pragma omp atomic compare release
+  usx = usx == use ? usd : usx;
+#pragma omp atomic compare release
+  usx = use == usx ? usd : usx;
+#pragma omp atomic compare release
+  if (usx == use)
+    usx = usd;
+#pragma omp atomic compare release
+  if (use == usx)
+    usx = usd;
+
+#pragma omp atomic compare seq_cst
+  sx = sx > se ? se : sx;
+#pragma omp atomic compare seq_cst
+  sx = sx < se ? se : sx;
+#pragma omp atomic compare seq_cst
+  sx = se > sx ? se : sx;
+#pragma omp atomic compare seq_cst
+  sx = se < sx ? se : sx;
+#pragma omp atomic compare seq_cst
+  if (sx > se)
+    sx = se;
+#pragma omp atomic compare seq_cst
+  if (sx < se)
+    sx = se;
+#pragma omp atomic compare seq_cst
+  if (se > sx)
+    sx = se;
+#pragma omp atomic compare seq_cst
+  if (se < sx)
+    sx = se;
+
+#pragma omp atomic compare seq_cst
+  sx = sx == se ? sd : sx;
+#pragma omp atomic compare seq_cst
+  sx = se == sx ? sd : sx;
+#pragma omp atomic compare seq_cst
+  if (sx == se)
+    sx = sd;
+#pragma omp atomic compare seq_cst
+  if (se == sx)
+    sx = sd;
+
+#pragma omp atomic compare seq_cst
+  usx = usx > use ? use : usx;
+#pragma omp atomic compare seq_cst
+  usx = usx < use ? use : usx;
+#pragma omp atomic compare seq_cst
+  usx = use > usx ? use : usx;
+#pragma omp atomic compare seq_cst
+  usx = use < usx ? use : usx;
+#pragma omp atomic compare seq_cst
+  if (usx > use)
+    usx = use;
+#pragma omp atomic compare seq_cst
+  if (usx < use)
+    usx = use;
+#pragma omp atomic compare seq_cst
+  if (use > usx)
+    usx = use;
+#pragma omp atomic compare seq_cst
+  if (use < usx)
+    usx = use;
+
+#pragma omp atomic compare seq_cst
+  usx = usx == use ? usd : usx;
+#pragma omp atomic compare seq_cst
+  usx = use == usx ? usd : usx;
+#pragma omp atomic compare seq_cst
+  if (usx == use)
+    usx = usd;
+#pragma omp atomic compare seq_cst
+  if (use == usx)
+    usx = usd;
+
+#pragma omp atomic compare
+  ix = ix > ie ? ie : ix;
+#pragma omp atomic compare
+  ix = ix < ie ? ie : ix;
+#pragma omp atomic compare
+  ix = ie > ix ? ie : ix;
+#pragma omp atomic compare
+  ix = ie < ix ? ie : ix;
+#pragma omp atomic compare
+  if (ix > ie)
+    ix = ie;
+#pragma omp atomic compare
+  if (ix < ie)
+    ix = ie;
+#pragma omp atomic compare
+  if (ie > ix)
+    ix = ie;
+#pragma omp atomic compare
+  if (ie < ix)
+    ix = ie;
+
+#pragma omp atomic compare
+  ix = ix == ie ? id : ix;
+#pragma omp atomic compare
+  ix = ie == ix ? id : ix;
+#pragma omp atomic compare
+  if (ix == ie)
+    ix = id;
+#pragma omp atomic compare
+  if (ie == ix)
+    ix = id;
+
+#pragma omp atomic compare
+  uix = uix > uie ? uie : uix;
+#pragma omp atomic compare
+  uix = uix < uie ? uie : uix;
+#pragma omp atomic compare
+  uix = uie > uix ? uie : uix;
+#pragma omp atomic compare
+  uix = uie < uix ? uie : uix;
+#pragma omp atomic compare
+  if (uix > uie)
+    uix = uie;
+#pragma omp atomic compare
+  if (uix < uie)
+    uix = uie;
+#pragma omp atomic compare
+  if (uie > uix)
+    uix = uie;
+#pragma omp atomic compare
+  if (uie < uix)
+    uix = uie;
+
+#pragma omp atomic compare
+  uix = uix == uie ? uid : uix;
+#pragma omp atomic compare
+  uix = uie == uix ? uid : uix;
+#pragma omp atomic compare
+  if (uix == uie)
+    uix = uid;
+#pragma omp atomic compare
+  if (uie == uix)
+    uix = uid;
+
+#pragma omp atomic compare acq_rel
+  ix = ix > ie ? ie : ix;
+#pragma omp atomic compare acq_rel
+  ix = ix < ie ? ie : ix;
+#pragma omp atomic compare acq_rel
+  ix = ie > ix ? ie : ix;
+#pragma omp atomic compare acq_rel
+  ix = ie < ix ? ie : ix;
+#pragma omp atomic compare acq_rel
+  if (ix > ie)
+    ix = ie;
+#pragma omp atomic compare acq_rel
+  if (ix < ie)
+    ix = ie;
+#pragma omp atomic compare acq_rel
+  if (ie > ix)
+    ix = ie;
+#pragma omp atomic compare acq_rel
+  if (ie < ix)
+    ix = ie;
+
+#pragma omp atomic compare acq_rel
+  ix = ix == ie ? id : ix;
+#pragma omp atomic compare acq_rel
+  ix = ie == ix ? id : ix;
+#pragma omp atomic compare acq_rel
+  if (ix == ie)
+    ix = id;
+#pragma omp atomic compare acq_rel
+  if (ie == ix)
+    ix = id;
+
+#pragma omp atomic compare acq_rel
+  uix = uix > uie ? uie : uix;
+#pragma omp atomic compare acq_rel
+  uix = uix < uie ? uie : uix;
+#pragma omp atomic compare acq_rel
+  uix = uie > uix ? uie : uix;
+#pragma omp atomic compare acq_rel
+  uix = uie < uix ? uie : uix;
+#pragma omp atomic compare acq_rel
+  if (uix > uie)
+    uix = uie;
+#pragma omp atomic compare acq_rel
+  if (uix < uie)
+    uix = uie;
+#pragma omp atomic compare acq_rel
+  if (uie > uix)
+    uix = uie;
+#pragma omp atomic compare acq_rel
+  if (uie < uix)
+    uix = uie;
+
+#pragma omp atomic compare acq_rel
+  uix = uix == uie ? uid : uix;
+#pragma omp atomic compare acq_rel
+  uix = uie == uix ? uid : uix;
+#pragma omp atomic compare acq_rel
+  if (uix == uie)
+    uix = uid;
+#pragma omp atomic compare acq_rel
+  if (uie == uix)
+    uix = uid;
+
+#pragma omp atomic compare acquire
+  ix = ix > ie ? ie : ix;
+#pragma omp atomic compare acquire
+  ix = ix < ie ? ie : ix;
+#pragma omp atomic compare acquire
+  ix = ie > ix ? ie : ix;
+#pragma omp atomic compare acquire
+  ix = ie < ix ? ie : ix;
+#pragma omp atomic compare acquire
+  if (ix > ie)
+    ix = ie;
+#pragma omp atomic compare acquire
+  if (ix < ie)
+    ix = ie;
+#pragma omp atomic compare acquire
+  if (ie > ix)
+    ix = ie;
+#pragma omp atomic compare acquire
+  if (ie < ix)
+    ix = ie;
+
+#pragma omp atomic compare acquire
+  ix = ix == ie ? id : ix;
+#pragma omp atomic compare acquire
+  ix = ie == ix ? id : ix;
+#pragma omp atomic compare acquire
+  if (ix == ie)
+    ix = id;
+#pragma omp atomic compare acquire
+  if (ie == ix)
+    ix = id;
+
+#pragma omp atomic compare acquire
+  uix = uix > uie ? uie : uix;
+#pragma omp atomic compare acquire
+  uix = uix < uie ? uie : uix;
+#pragma omp atomic compare acquire
+  uix = uie > uix ? uie : uix;
+#pragma omp atomic compare acquire
+  uix = uie < uix ? uie : uix;
+#pragma omp atomic compare acquire
+  if (uix > uie)
+    uix = uie;
+#pragma omp atomic compare acquire
+  if (uix < uie)
+    uix = uie;
+#pragma omp atomic compare acquire
+  if (uie > uix)
+    uix = uie;
+#pragma omp atomic compare acquire
+  if (uie < uix)
+    uix = uie;
+
+#pragma omp atomic compare acquire
+  uix = uix == uie ? uid : uix;
+#pragma omp atomic compare acquire
+  uix = uie == uix ? uid : uix;
+#pragma omp atomic compare acquire
+  if (uix == uie)
+    uix = uid;
+#pragma omp atomic compare acquire
+  if (uie == uix)
+    uix = uid;
+
+#pragma omp atomic compare relaxed
+  ix = ix > ie ? ie : ix;
+#pragma omp atomic compare relaxed
+  ix = ix < ie ? ie : ix;
+#pragma omp atomic compare relaxed
+  ix = ie > ix ? ie : ix;
+#pragma omp atomic compare relaxed
+  ix = ie < ix ? ie : ix;
+#pragma omp atomic compare relaxed
+  if (ix > ie)
+    ix = ie;
+#pragma omp atomic compare relaxed
+  if (ix < ie)
+    ix = ie;
+#pragma omp atomic compare relaxed
+  if (ie > ix)
+    ix = ie;
+#pragma omp atomic compare relaxed
+  if (ie < ix)
+    ix = ie;
+
+#pragma omp atomic compare relaxed
+  ix = ix == ie ? id : ix;
+#pragma omp atomic compare relaxed
+  ix = ie == ix ? id : ix;
+#pragma omp atomic compare relaxed
+  if (ix == ie)
+    ix = id;
+#pragma omp atomic compare relaxed
+  if (ie == ix)
+    ix = id;
+
+#pragma omp atomic compare relaxed
+  uix = uix > uie ? uie : uix;
+#pragma omp atomic compare relaxed
+  uix = uix < uie ? uie : uix;
+#pragma omp atomic compare relaxed
+  uix = uie > uix ? uie : uix;
+#pragma omp atomic compare relaxed
+  uix = uie < uix ? uie : uix;
+#pragma omp atomic compare relaxed
+  if (uix > uie)
+    uix = uie;
+#pragma omp atomic compare relaxed
+  if (uix < uie)
+    uix = uie;
+#pragma omp atomic compare relaxed
+  if (uie > uix)
+    uix = uie;
+#pragma omp atomic compare relaxed
+  if (uie < uix)
+    uix = uie;
+
+#pragma omp atomic compare relaxed
+  uix = uix == uie ? uid : uix;
+#pragma omp atomic compare relaxed
+  uix = uie == uix ? uid : uix;
+#pragma omp atomic compare relaxed
+  if (uix == uie)
+    uix = uid;
+#pragma omp atomic compare relaxed
+  if (uie == uix)
+    uix = uid;
+
+#pragma omp atomic compare release
+  ix = ix > ie ? ie : ix;
+#pragma omp atomic compare release
+  ix = ix < ie ? ie : ix;
+#pragma omp atomic compare release
+  ix = ie > ix ? ie : ix;
+#pragma omp atomic compare release
+  ix = ie < ix ? ie : ix;
+#pragma omp atomic compare release
+  if (ix > ie)
+    ix = ie;
+#pragma omp atomic compare release
+  if (ix < ie)
+    ix = ie;
+#pragma omp atomic compare release
+  if (ie > ix)
+    ix = ie;
+#pragma omp atomic compare release
+  if (ie < ix)
+    ix = ie;
+
+#pragma omp atomic compare release
+  ix = ix == ie ? id : ix;
+#pragma omp atomic compare release
+  ix = ie == ix ? id : ix;
+#pragma omp atomic compare release
+  if (ix == ie)
+    ix = id;
+#pragma omp atomic compare release
+  if (ie == ix)
+    ix = id;
+
+#pragma omp atomic compare release
+  uix = uix > uie ? uie : uix;
+#pragma omp atomic compare release
+  uix = uix < uie ? uie : uix;
+#pragma omp atomic compare release
+  uix = uie > uix ? uie : uix;
+#pragma omp atomic compare release
+  uix = uie < uix ? uie : uix;
+#pragma omp atomic compare release
+  if (uix > uie)
+    uix = uie;
+#pragma omp atomic compare release
+  if (uix < uie)
+    uix = uie;
+#pragma omp atomic compare release
+  if (uie > uix)
+    uix = uie;
+#pragma omp atomic compare release
+  if (uie < uix)
+    uix = uie;
+
+#pragma omp atomic compare release
+  uix = uix == uie ? uid : uix;
+#pragma omp atomic compare release
+  uix = uie == uix ? uid : uix;
+#pragma omp atomic compare release
+  if (uix == uie)
+    uix = uid;
+#pragma omp atomic compare release
+  if (uie == uix)
+    uix = uid;
+
+#pragma omp atomic compare seq_cst
+  ix = ix > ie ? ie : ix;
+#pragma omp atomic compare seq_cst
+  ix = ix < ie ? ie : ix;
+#pragma omp atomic compare seq_cst
+  ix = ie > ix ? ie : ix;
+#pragma omp atomic compare seq_cst
+  ix = ie < ix ? ie : ix;
+#pragma omp atomic compare seq_cst
+  if (ix > ie)
+    ix = ie;
+#pragma omp atomic compare seq_cst
+  if (ix < ie)
+    ix = ie;
+#pragma omp atomic compare seq_cst
+  if (ie > ix)
+    ix = ie;
+#pragma omp atomic compare seq_cst
+  if (ie < ix)
+    ix = ie;
+
+#pragma omp atomic compare seq_cst
+  ix = ix == ie ? id : ix;
+#pragma omp atomic compare seq_cst
+  ix = ie == ix ? id : ix;
+#pragma omp atomic compare seq_cst
+  if (ix == ie)
+    ix = id;
+#pragma omp atomic compare seq_cst
+  if (ie == ix)
+    ix = id;
+
+#pragma omp atomic compare seq_cst
+  uix = uix > uie ? uie : uix;
+#pragma omp atomic compare seq_cst
+  uix = uix < uie ? uie : uix;
+#pragma omp atomic compare seq_cst
+  uix = uie > uix ? uie : uix;
+#pragma omp atomic compare seq_cst
+  uix = uie < uix ? uie : uix;
+#pragma omp atomic compare seq_cst
+  if (uix > uie)
+    uix = uie;
+#pragma omp atomic compare seq_cst
+  if (uix < uie)
+    uix = uie;
+#pragma omp atomic compare seq_cst
+  if (uie > uix)
+    uix = uie;
+#pragma omp atomic compare seq_cst
+  if (uie < uix)
+    uix = uie;
+
+#pragma omp atomic compare seq_cst
+  uix = uix == uie ? uid : uix;
+#pragma omp atomic compare seq_cst
+  uix = uie == uix ? uid : uix;
+#pragma omp atomic compare seq_cst
+  if (uix == uie)
+    uix = uid;
+#pragma omp atomic compare seq_cst
+  if (uie == uix)
+    uix = uid;
+
+#pragma omp atomic compare
+  lx = lx > le ? le : lx;
+#pragma omp atomic compare
+  lx = lx < le ? le : lx;
+#pragma omp atomic compare
+  lx = le > lx ? le : lx;
+#pragma omp atomic compare
+  lx = le < lx ? le : lx;
+#pragma omp atomic compare
+  if (lx > le)
+    lx = le;
+#pragma omp atomic compare
+  if (lx < le)
+    lx = le;
+#pragma omp atomic compare
+  if (le > lx)
+    lx = le;
+#pragma omp atomic compare
+  if (le < lx)
+    lx = le;
+
+#pragma omp atomic compare
+  lx = lx == le ? ld : lx;
+#pragma omp atomic compare
+  lx = le == lx ? ld : lx;
+#pragma omp atomic compare
+  if (lx == le)
+    lx = ld;
+#pragma omp atomic compare
+  if (le == lx)
+    lx = ld;
+
+#pragma omp atomic compare
+  ulx = ulx > ule ? ule : ulx;
+#pragma omp atomic compare
+  ulx = ulx < ule ? ule : ulx;
+#pragma omp atomic compare
+  ulx = ule > ulx ? ule : ulx;
+#pragma omp atomic compare
+  ulx = ule < ulx ? ule : ulx;
+#pragma omp atomic compare
+  if (ulx > ule)
+    ulx = ule;
+#pragma omp atomic compare
+  if (ulx < ule)
+    ulx = ule;
+#pragma omp atomic compare
+  if (ule > ulx)
+    ulx = ule;
+#pragma omp atomic compare
+  if (ule < ulx)
+    ulx = ule;
+
+#pragma omp atomic compare
+  ulx = ulx == ule ? uld : ulx;
+#pragma omp atomic compare
+  ulx = ule == ulx ? uld : ulx;
+#pragma omp atomic compare
+  if (ulx == ule)
+    ulx = uld;
+#pragma omp atomic compare
+  if (ule == ulx)
+    ulx = uld;
+
+#pragma omp atomic compare acq_rel
+  lx = lx > le ? le : lx;
+#pragma omp atomic compare acq_rel
+  lx = lx < le ? le : lx;
+#pragma omp atomic compare acq_rel
+  lx = le > lx ? le : lx;
+#pragma omp atomic compare acq_rel
+  lx = le < lx ? le : lx;
+#pragma omp atomic compare acq_rel
+  if (lx > le)
+    lx = le;
+#pragma omp atomic compare acq_rel
+  if (lx < le)
+    lx = le;
+#pragma omp atomic compare acq_rel
+  if (le > lx)
+    lx = le;
+#pragma omp atomic compare acq_rel
+  if (le < lx)
+    lx = le;
+
+#pragma omp atomic compare acq_rel
+  lx = lx == le ? ld : lx;
+#pragma omp atomic compare acq_rel
+  lx = le == lx ? ld : lx;
+#pragma omp atomic compare acq_rel
+  if (lx == le)
+    lx = ld;
+#pragma omp atomic compare acq_rel
+  if (le == lx)
+    lx = ld;
+
+#pragma omp atomic compare acq_rel
+  ulx = ulx > ule ? ule : ulx;
+#pragma omp atomic compare acq_rel
+  ulx = ulx < ule ? ule : ulx;
+#pragma omp atomic compare acq_rel
+  ulx = ule > ulx ? ule : ulx;
+#pragma omp atomic compare acq_rel
+  ulx = ule < ulx ? ule : ulx;
+#pragma omp atomic compare acq_rel
+  if (ulx > ule)
+    ulx = ule;
+#pragma omp atomic compare acq_rel
+  if (ulx < ule)
+    ulx = ule;
+#pragma omp atomic compare acq_rel
+  if (ule > ulx)
+    ulx = ule;
+#pragma omp atomic compare acq_rel
+  if (ule < ulx)
+    ulx = ule;
+
+#pragma omp atomic compare acq_rel
+  ulx = ulx == ule ? uld : ulx;
+#pragma omp atomic compare acq_rel
+  ulx = ule == ulx ? uld : ulx;
+#pragma omp atomic compare acq_rel
+  if (ulx == ule)
+    ulx = uld;
+#pragma omp atomic compare acq_rel
+  if (ule == ulx)
+    ulx = uld;
+
+#pragma omp atomic compare acquire
+  lx = lx > le ? le : lx;
+#pragma omp atomic compare acquire
+  lx = lx < le ? le : lx;
+#pragma omp atomic compare acquire
+  lx = le > lx ? le : lx;
+#pragma omp atomic compare acquire
+  lx = le < lx ? le : lx;
+#pragma omp atomic compare acquire
+  if (lx > le)
+    lx = le;
+#pragma omp atomic compare acquire
+  if (lx < le)
+    lx = le;
+#pragma omp atomic compare acquire
+  if (le > lx)
+    lx = le;
+#pragma omp atomic compare acquire
+  if (le < lx)
+    lx = le;
+
+#pragma omp atomic compare acquire
+  lx = lx == le ? ld : lx;
+#pragma omp atomic compare acquire
+  lx = le == lx ? ld : lx;
+#pragma omp atomic compare acquire
+  if (lx == le)
+    lx = ld;
+#pragma omp atomic compare acquire
+  if (le == lx)
+    lx = ld;
+
+#pragma omp atomic compare acquire
+  ulx = ulx > ule ? ule : ulx;
+#pragma omp atomic compare acquire
+  ulx = ulx < ule ? ule : ulx;
+#pragma omp atomic compare acquire
+  ulx = ule > ulx ? ule : ulx;
+#pragma omp atomic compare acquire
+  ulx = ule < ulx ? ule : ulx;
+#pragma omp atomic compare acquire
+  if (ulx > ule)
+    ulx = ule;
+#pragma omp atomic compare acquire
+  if (ulx < ule)
+    ulx = ule;
+#pragma omp atomic compare acquire
+  if (ule > ulx)
+    ulx = ule;
+#pragma omp atomic compare acquire
+  if (ule < ulx)
+    ulx = ule;
+
+#pragma omp atomic compare acquire
+  ulx = ulx == ule ? uld : ulx;
+#pragma omp atomic compare acquire
+  ulx = ule == ulx ? uld : ulx;
+#pragma omp atomic compare acquire
+  if (ulx == ule)
+    ulx = uld;
+#pragma omp atomic compare acquire
+  if (ule == ulx)
+    ulx = uld;
+
+#pragma omp atomic compare relaxed
+  lx = lx > le ? le : lx;
+#pragma omp atomic compare relaxed
+  lx = lx < le ? le : lx;
+#pragma omp atomic compare relaxed
+  lx = le > lx ? le : lx;
+#pragma omp atomic compare relaxed
+  lx = le < lx ? le : lx;
+#pragma omp atomic compare relaxed
+  if (lx > le)
+    lx = le;
+#pragma omp atomic compare relaxed
+  if (lx < le)
+    lx = le;
+#pragma omp atomic compare relaxed
+  if (le > lx)
+    lx = le;
+#pragma omp atomic compare relaxed
+  if (le < lx)
+    lx = le;
+
+#pragma omp atomic compare relaxed
+  lx = lx == le ? ld : lx;
+#pragma omp atomic compare relaxed
+  lx = le == lx ? ld : lx;
+#pragma omp atomic compare relaxed
+  if (lx == le)
+    lx = ld;
+#pragma omp atomic compare relaxed
+  if (le == lx)
+    lx = ld;
+
+#pragma omp atomic compare relaxed
+  ulx = ulx > ule ? ule : ulx;
+#pragma omp atomic compare relaxed
+  ulx = ulx < ule ? ule : ulx;
+#pragma omp atomic compare relaxed
+  ulx = ule > ulx ? ule : ulx;
+#pragma omp atomic compare relaxed
+  ulx = ule < ulx ? ule : ulx;
+#pragma omp atomic compare relaxed
+  if (ulx > ule)
+    ulx = ule;
+#pragma omp atomic compare relaxed
+  if (ulx < ule)
+    ulx = ule;
+#pragma omp atomic compare relaxed
+  if (ule > ulx)
+    ulx = ule;
+#pragma omp atomic compare relaxed
+  if (ule < ulx)
+    ulx = ule;
+
+#pragma omp atomic compare relaxed
+  ulx = ulx == ule ? uld : ulx;
+#pragma omp atomic compare relaxed
+  ulx = ule == ulx ? uld : ulx;
+#pragma omp atomic compare relaxed
+  if (ulx == ule)
+    ulx = uld;
+#pragma omp atomic compare relaxed
+  if (ule == ulx)
+    ulx = uld;
+
+#pragma omp atomic compare release
+  lx = lx > le ? le : lx;
+#pragma omp atomic compare release
+  lx = lx < le ? le : lx;
+#pragma omp atomic compare release
+  lx = le > lx ? le : lx;
+#pragma omp atomic compare release
+  lx = le < lx ? le : lx;
+#pragma omp atomic compare release
+  if (lx > le)
+    lx = le;
+#pragma omp atomic compare release
+  if (lx < le)
+    lx = le;
+#pragma omp atomic compare release
+  if (le > lx)
+    lx = le;
+#pragma omp atomic compare release
+  if (le < lx)
+    lx = le;
+
+#pragma omp atomic compare release
+  lx = lx == le ? ld : lx;
+#pragma omp atomic compare release
+  lx = le == lx ? ld : lx;
+#pragma omp atomic compare release
+  if (lx == le)
+    lx = ld;
+#pragma omp atomic compare release
+  if (le == lx)
+    lx = ld;
+
+#pragma omp atomic compare release
+  ulx = ulx > ule ? ule : ulx;
+#pragma omp atomic compare release
+  ulx = ulx < ule ? ule : ulx;
+#pragma omp atomic compare release
+  ulx = ule > ulx ? ule : ulx;
+#pragma omp atomic compare release
+  ulx = ule < ulx ? ule : ulx;
+#pragma omp atomic compare release
+  if (ulx > ule)
+    ulx = ule;
+#pragma omp atomic compare release
+  if (ulx < ule)
+    ulx = ule;
+#pragma omp atomic compare release
+  if (ule > ulx)
+    ulx = ule;
+#pragma omp atomic compare release
+  if (ule < ulx)
+    ulx = ule;
+
+#pragma omp atomic compare release
+  ulx = ulx == ule ? uld : ulx;
+#pragma omp atomic compare release
+  ulx = ule == ulx ? uld : ulx;
+#pragma omp atomic compare release
+  if (ulx == ule)
+    ulx = uld;
+#pragma omp atomic compare release
+  if (ule == ulx)
+    ulx = uld;
+
+#pragma omp atomic compare seq_cst
+  lx = lx > le ? le : lx;
+#pragma omp atomic compare seq_cst
+  lx = lx < le ? le : lx;
+#pragma omp atomic compare seq_cst
+  lx = le > lx ? le : lx;
+#pragma omp atomic compare seq_cst
+  lx = le < lx ? le : lx;
+#pragma omp atomic compare seq_cst
+  if (lx > le)
+    lx = le;
+#pragma omp atomic compare seq_cst
+  if (lx < le)
+    lx = le;
+#pragma omp atomic compare seq_cst
+  if (le > lx)
+    lx = le;
+#pragma omp atomic compare seq_cst
+  if (le < lx)
+    lx = le;
+
+#pragma omp atomic compare seq_cst
+  lx = lx == le ? ld : lx;
+#pragma omp atomic compare seq_cst
+  lx = le == lx ? ld : lx;
+#pragma omp atomic compare seq_cst
+  if (lx == le)
+    lx = ld;
+#pragma omp atomic compare seq_cst
+  if (le == lx)
+    lx = ld;
+
+#pragma omp atomic compare seq_cst
+  ulx = ulx > ule ? ule : ulx;
+#pragma omp atomic compare seq_cst
+  ulx = ulx < ule ? ule : ulx;
+#pragma omp atomic compare seq_cst
+  ulx = ule > ulx ? ule : ulx;
+#pragma omp atomic compare seq_cst
+  ulx = ule < ulx ? ule : ulx;
+#pragma omp atomic compare seq_cst
+  if (ulx > ule)
+    ulx = ule;
+#pragma omp atomic compare seq_cst
+  if (ulx < ule)
+    ulx = ule;
+#pragma omp atomic compare seq_cst
+  if (ule > ulx)
+    ulx = ule;
+#pragma omp atomic compare seq_cst
+  if (ule < ulx)
+    ulx = ule;
+
+#pragma omp atomic compare seq_cst
+  ulx = ulx == ule ? uld : ulx;
+#pragma omp atomic compare seq_cst
+  ulx = ule == ulx ? uld : ulx;
+#pragma omp atomic compare seq_cst
+  if (ulx == ule)
+    ulx = uld;
+#pragma omp atomic compare seq_cst
+  if (ule == ulx)
+    ulx = uld;
+
+#pragma omp atomic compare
+  llx = llx > lle ? lle : llx;
+#pragma omp atomic compare
+  llx = llx < lle ? lle : llx;
+#pragma omp atomic compare
+  llx = lle > llx ? lle : llx;
+#pragma omp atomic compare
+  llx = lle < llx ? lle : llx;
+#pragma omp atomic compare
+  if (llx > lle)
+    llx = lle;
+#pragma omp atomic compare
+  if (llx < lle)
+    llx = lle;
+#pragma omp atomic compare
+  if (lle > llx)
+    llx = lle;
+#pragma omp atomic compare
+  if (lle < llx)
+    llx = lle;
+
+#pragma omp atomic compare
+  llx = llx == lle ? lld : llx;
+#pragma omp atomic compare
+  llx = lle == llx ? lld : llx;
+#pragma omp atomic compare
+  if (llx == lle)
+    llx = lld;
+#pragma omp atomic compare
+  if (lle == llx)
+    llx = lld;
+
+#pragma omp atomic compare
+  ullx = ullx > ulle ? ulle : ullx;
+#pragma omp atomic compare
+  ullx = ullx < ulle ? ulle : ullx;
+#pragma omp atomic compare
+  ullx = ulle > ullx ? ulle : ullx;
+#pragma omp atomic compare
+  ullx = ulle < ullx ? ulle : ullx;
+#pragma omp atomic compare
+  if (ullx > ulle)
+    ullx = ulle;
+#pragma omp atomic compare
+  if (ullx < ulle)
+    ullx = ulle;
+#pragma omp atomic compare
+  if (ulle > ullx)
+    ullx = ulle;
+#pragma omp atomic compare
+  if (ulle < ullx)
+    ullx = ulle;
+
+#pragma omp atomic compare
+  ullx = ullx == ulle ? ulld : ullx;
+#pragma omp atomic compare
+  ullx = ulle == ullx ? ulld : ullx;
+#pragma omp atomic compare
+  if (ullx == ulle)
+    ullx = ulld;
+#pragma omp atomic compare
+  if (ulle == ullx)
+    ullx = ulld;
+
+#pragma omp atomic compare acq_rel
+  llx = llx > lle ? lle : llx;
+#pragma omp atomic compare acq_rel
+  llx = llx < lle ? lle : llx;
+#pragma omp atomic compare acq_rel
+  llx = lle > llx ? lle : llx;
+#pragma omp atomic compare acq_rel
+  llx = lle < llx ? lle : llx;
+#pragma omp atomic compare acq_rel
+  if (llx > lle)
+    llx = lle;
+#pragma omp atomic compare acq_rel
+  if (llx < lle)
+    llx = lle;
+#pragma omp atomic compare acq_rel
+  if (lle > llx)
+    llx = lle;
+#pragma omp atomic compare acq_rel
+  if (lle < llx)
+    llx = lle;
+
+#pragma omp atomic compare acq_rel
+  llx = llx == lle ? lld : llx;
+#pragma omp atomic compare acq_rel
+  llx = lle == llx ? lld : llx;
+#pragma omp atomic compare acq_rel
+  if (llx == lle)
+    llx = lld;
+#pragma omp atomic compare acq_rel
+  if (lle == llx)
+    llx = lld;
+
+#pragma omp atomic compare acq_rel
+  ullx = ullx > ulle ? ulle : ullx;
+#pragma omp atomic compare acq_rel
+  ullx = ullx < ulle ? ulle : ullx;
+#pragma omp atomic compare acq_rel
+  ullx = ulle > ullx ? ulle : ullx;
+#pragma omp atomic compare acq_rel
+  ullx = ulle < ullx ? ulle : ullx;
+#pragma omp atomic compare acq_rel
+  if (ullx > ulle)
+    ullx = ulle;
+#pragma omp atomic compare acq_rel
+  if (ullx < ulle)
+    ullx = ulle;
+#pragma omp atomic compare acq_rel
+  if (ulle > ullx)
+    ullx = ulle;
+#pragma omp atomic compare acq_rel
+  if (ulle < ullx)
+    ullx = ulle;
+
+#pragma omp atomic compare acq_rel
+  ullx = ullx == ulle ? ulld : ullx;
+#pragma omp atomic compare acq_rel
+  ullx = ulle == ullx ? ulld : ullx;
+#pragma omp atomic compare acq_rel
+  if (ullx == ulle)
+    ullx = ulld;
+#pragma omp atomic compare acq_rel
+  if (ulle == ullx)
+    ullx = ulld;
+
+#pragma omp atomic compare acquire
+  llx = llx > lle ? lle : llx;
+#pragma omp atomic compare acquire
+  llx = llx < lle ? lle : llx;
+#pragma omp atomic compare acquire
+  llx = lle > llx ? lle : llx;
+#pragma omp atomic compare acquire
+  llx = lle < llx ? lle : llx;
+#pragma omp atomic compare acquire
+  if (llx > lle)
+    llx = lle;
+#pragma omp atomic compare acquire
+  if (llx < lle)
+    llx = lle;
+#pragma omp atomic compare acquire
+  if (lle > llx)
+    llx = lle;
+#pragma omp atomic compare acquire
+  if (lle < llx)
+    llx = lle;
+
+#pragma omp atomic compare acquire
+  llx = llx == lle ? lld : llx;
+#pragma omp atomic compare acquire
+  llx = lle == llx ? lld : llx;
+#pragma omp atomic compare acquire
+  if (llx == lle)
+    llx = lld;
+#pragma omp atomic compare acquire
+  if (lle == llx)
+    llx = lld;
+
+#pragma omp atomic compare acquire
+  ullx = ullx > ulle ? ulle : ullx;
+#pragma omp atomic compare acquire
+  ullx = ullx < ulle ? ulle : ullx;
+#pragma omp atomic compare acquire
+  ullx = ulle > ullx ? ulle : ullx;
+#pragma omp atomic compare acquire
+  ullx = ulle < ullx ? ulle : ullx;
+#pragma omp atomic compare acquire
+  if (ullx > ulle)
+    ullx = ulle;
+#pragma omp atomic compare acquire
+  if (ullx < ulle)
+    ullx = ulle;
+#pragma omp atomic compare acquire
+  if (ulle > ullx)
+    ullx = ulle;
+#pragma omp atomic compare acquire
+  if (ulle < ullx)
+    ullx = ulle;
+
+#pragma omp atomic compare acquire
+  ullx = ullx == ulle ? ulld : ullx;
+#pragma omp atomic compare acquire
+  ullx = ulle == ullx ? ulld : ullx;
+#pragma omp atomic compare acquire
+  if (ullx == ulle)
+    ullx = ulld;
+#pragma omp atomic compare acquire
+  if (ulle == ullx)
+    ullx = ulld;
+
+#pragma omp atomic compare relaxed
+  llx = llx > lle ? lle : llx;
+#pragma omp atomic compare relaxed
+  llx = llx < lle ? lle : llx;
+#pragma omp atomic compare relaxed
+  llx = lle > llx ? lle : llx;
+#pragma omp atomic compare relaxed
+  llx = lle < llx ? lle : llx;
+#pragma omp atomic compare relaxed
+  if (llx > lle)
+    llx = lle;
+#pragma omp atomic compare relaxed
+  if (llx < lle)
+    llx = lle;
+#pragma omp atomic compare relaxed
+  if (lle > llx)
+    llx = lle;
+#pragma omp atomic compare relaxed
+  if (lle < llx)
+    llx = lle;
+
+#pragma omp atomic compare relaxed
+  llx = llx == lle ? lld : llx;
+#pragma omp atomic compare relaxed
+  llx = lle == llx ? lld : llx;
+#pragma omp atomic compare relaxed
+  if (llx == lle)
+    llx = lld;
+#pragma omp atomic compare relaxed
+  if (lle == llx)
+    llx = lld;
+
+#pragma omp atomic compare relaxed
+  ullx = ullx > ulle ? ulle : ullx;
+#pragma omp atomic compare relaxed
+  ullx = ullx < ulle ? ulle : ullx;
+#pragma omp atomic compare relaxed
+  ullx = ulle > ullx ? ulle : ullx;
+#pragma omp atomic compare relaxed
+  ullx = ulle < ullx ? ulle : ullx;
+#pragma omp atomic compare relaxed
+  if (ullx > ulle)
+    ullx = ulle;
+#pragma omp atomic compare relaxed
+  if (ullx < ulle)
+    ullx = ulle;
+#pragma omp atomic compare relaxed
+  if (ulle > ullx)
+    ullx = ulle;
+#pragma omp atomic compare relaxed
+  if (ulle < ullx)
+    ullx = ulle;
+
+#pragma omp atomic compare relaxed
+  ullx = ullx == ulle ? ulld : ullx;
+#pragma omp atomic compare relaxed
+  ullx = ulle == ullx ? ulld : ullx;
+#pragma omp atomic compare relaxed
+  if (ullx == ulle)
+    ullx = ulld;
+#pragma omp atomic compare relaxed
+  if (ulle == ullx)
+    ullx = ulld;
+
+#pragma omp atomic compare release
+  llx = llx > lle ? lle : llx;
+#pragma omp atomic compare release
+  llx = llx < lle ? lle : llx;
+#pragma omp atomic compare release
+  llx = lle > llx ? lle : llx;
+#pragma omp atomic compare release
+  llx = lle < llx ? lle : llx;
+#pragma omp atomic compare release
+  if (llx > lle)
+    llx = lle;
+#pragma omp atomic compare release
+  if (llx < lle)
+    llx = lle;
+#pragma omp atomic compare release
+  if (lle > llx)
+    llx = lle;
+#pragma omp atomic compare release
+  if (lle < llx)
+    llx = lle;
+
+#pragma omp atomic compare release
+  llx = llx == lle ? lld : llx;
+#pragma omp atomic compare release
+  llx = lle == llx ? lld : llx;
+#pragma omp atomic compare release
+  if (llx == lle)
+    llx = lld;
+#pragma omp atomic compare release
+  if (lle == llx)
+    llx = lld;
+
+#pragma omp atomic compare release
+  ullx = ullx > ulle ? ulle : ullx;
+#pragma omp atomic compare release
+  ullx = ullx < ulle ? ulle : ullx;
+#pragma omp atomic compare release
+  ullx = ulle > ullx ? ulle : ullx;
+#pragma omp atomic compare release
+  ullx = ulle < ullx ? ulle : ullx;
+#pragma omp atomic compare release
+  if (ullx > ulle)
+    ullx = ulle;
+#pragma omp atomic compare release
+  if (ullx < ulle)
+    ullx = ulle;
+#pragma omp atomic compare release
+  if (ulle > ullx)
+    ullx = ulle;
+#pragma omp atomic compare release
+  if (ulle < ullx)
+    ullx = ulle;
+
+#pragma omp atomic compare release
+  ullx = ullx == ulle ? ulld : ullx;
+#pragma omp atomic compare release
+  ullx = ulle == ullx ? ulld : ullx;
+#pragma omp atomic compare release
+  if (ullx == ulle)
+    ullx = ulld;
+#pragma omp atomic compare release
+  if (ulle == ullx)
+    ullx = ulld;
+
+#pragma omp atomic compare seq_cst
+  llx = llx > lle ? lle : llx;
+#pragma omp atomic compare seq_cst
+  llx = llx < lle ? lle : llx;
+#pragma omp atomic compare seq_cst
+  llx = lle > llx ? lle : llx;
+#pragma omp atomic compare seq_cst
+  llx = lle < llx ? lle : llx;
+#pragma omp atomic compare seq_cst
+  if (llx > lle)
+    llx = lle;
+#pragma omp atomic compare seq_cst
+  if (llx < lle)
+    llx = lle;
+#pragma omp atomic compare seq_cst
+  if (lle > llx)
+    llx = lle;
+#pragma omp atomic compare seq_cst
+  if (lle < llx)
+    llx = lle;
+
+#pragma omp atomic compare seq_cst
+  llx = llx == lle ? lld : llx;
+#pragma omp atomic compare seq_cst
+  llx = lle == llx ? lld : llx;
+#pragma omp atomic compare seq_cst
+  if (llx == lle)
+    llx = lld;
+#pragma omp atomic compare seq_cst
+  if (lle == llx)
+    llx = lld;
+
+#pragma omp atomic compare seq_cst
+  ullx = ullx > ulle ? ulle : ullx;
+#pragma omp atomic compare seq_cst
+  ullx = ullx < ulle ? ulle : ullx;
+#pragma omp atomic compare seq_cst
+  ullx = ulle > ullx ? ulle : ullx;
+#pragma omp atomic compare seq_cst
+  ullx = ulle < ullx ? ulle : ullx;
+#pragma omp atomic compare seq_cst
+  if (ullx > ulle)
+    ullx = ulle;
+#pragma omp atomic compare seq_cst
+  if (ullx < ulle)
+    ullx = ulle;
+#pragma omp atomic compare seq_cst
+  if (ulle > ullx)
+    ullx = ulle;
+#pragma omp atomic compare seq_cst
+  if (ulle < ullx)
+    ullx = ulle;
+
+#pragma omp atomic compare seq_cst
+  ullx = ullx == ulle ? ulld : ullx;
+#pragma omp atomic compare seq_cst
+  ullx = ulle == ullx ? ulld : ullx;
+#pragma omp atomic compare seq_cst
+  if (ullx == ulle)
+    ullx = ulld;
+#pragma omp atomic compare seq_cst
+  if (ulle == ullx)
+    ullx = ulld;
+}
+
+#endif
+// CHECK-LABEL: define {{[^@]+}}@foo
+// CHECK-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[CX:%.*]] = alloca i8, align 1
+// CHECK-NEXT:    [[CE:%.*]] = alloca i8, align 1
+// CHECK-NEXT:    [[CD:%.*]] = alloca i8, align 1
+// CHECK-NEXT:    [[UCX:%.*]] = alloca i8, align 1
+// CHECK-NEXT:    [[UCE:%.*]] = alloca i8, align 1
+// CHECK-NEXT:    [[UCD:%.*]] = alloca i8, align 1
+// CHECK-NEXT:    [[SX:%.*]] = alloca i16, align 2
+// CHECK-NEXT:    [[SE:%.*]] = alloca i16, align 2
+// CHECK-NEXT:    [[SD:%.*]] = alloca i16, align 2
+// CHECK-NEXT:    [[USX:%.*]] = alloca i16, align 2
+// CHECK-NEXT:    [[USE:%.*]] = alloca i16, align 2
+// CHECK-NEXT:    [[USD:%.*]] = alloca i16, align 2
+// CHECK-NEXT:    [[IX:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[IE:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[ID:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[UIX:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[UIE:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[UID:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[LX:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[LE:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[LD:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[ULX:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[ULE:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[ULD:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[LLX:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[LLE:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[LLD:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[ULLX:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[ULLE:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[ULLD:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[FX:%.*]] = alloca float, align 4
+// CHECK-NEXT:    [[FE:%.*]] = alloca float, align 4
+// CHECK-NEXT:    [[FD:%.*]] = alloca float, align 4
+// CHECK-NEXT:    [[DX:%.*]] = alloca double, align 8
+// CHECK-NEXT:    [[DE:%.*]] = alloca double, align 8
+// CHECK-NEXT:    [[DD:%.*]] = alloca double, align 8
+// CHECK-NEXT:    [[TMP0:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP0]] monotonic, align 1
+// CHECK-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP2]] monotonic, align 1
+// CHECK-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP5:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP4]] monotonic, align 1
+// CHECK-NEXT:    [[TMP6:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP7:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP6]] monotonic, align 1
+// CHECK-NEXT:    [[TMP8:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP8]] monotonic, align 1
+// CHECK-NEXT:    [[TMP10:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP11:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP10]] monotonic, align 1
+// CHECK-NEXT:    [[TMP12:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP12]] monotonic, align 1
+// CHECK-NEXT:    [[TMP14:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP15:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP14]] monotonic, align 1
+// CHECK-NEXT:    [[TMP16:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP17:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP16]], i8 [[TMP17]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP19:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP20:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP21:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP19]], i8 [[TMP20]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP23:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP24:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP22]], i8 [[TMP23]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP25:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP26:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP27:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP25]], i8 [[TMP26]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP28:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP29:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP28]] monotonic, align 1
+// CHECK-NEXT:    [[TMP30:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP30]] monotonic, align 1
+// CHECK-NEXT:    [[TMP32:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP33:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP32]] monotonic, align 1
+// CHECK-NEXT:    [[TMP34:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP34]] monotonic, align 1
+// CHECK-NEXT:    [[TMP36:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP37:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP36]] monotonic, align 1
+// CHECK-NEXT:    [[TMP38:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP39:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP38]] monotonic, align 1
+// CHECK-NEXT:    [[TMP40:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP41:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP40]] monotonic, align 1
+// CHECK-NEXT:    [[TMP42:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP43:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP42]] monotonic, align 1
+// CHECK-NEXT:    [[TMP44:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP45:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP46:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP44]], i8 [[TMP45]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP47:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP48:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP49:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP47]], i8 [[TMP48]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP50:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP51:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP52:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP50]], i8 [[TMP51]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP53:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP54:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP55:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP53]], i8 [[TMP54]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP56:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP56]] acq_rel, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1:[0-9]+]])
+// CHECK-NEXT:    [[TMP58:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP59:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP58]] acq_rel, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP60:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP61:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP60]] acq_rel, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP62:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP63:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP62]] acq_rel, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP64:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP65:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP64]] acq_rel, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP66:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP66]] acq_rel, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP68:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP68]] acq_rel, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP70:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP71:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP70]] acq_rel, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP72:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP73:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP74:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP72]], i8 [[TMP73]] acq_rel acquire, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP75:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP76:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP77:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP75]], i8 [[TMP76]] acq_rel acquire, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP78:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP79:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP80:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP78]], i8 [[TMP79]] acq_rel acquire, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP81:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP82:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP83:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP81]], i8 [[TMP82]] acq_rel acquire, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP84:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP85:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP84]] acq_rel, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP86:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP87:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP86]] acq_rel, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP88:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP88]] acq_rel, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP90:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP90]] acq_rel, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP92:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP93:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP92]] acq_rel, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP94:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP95:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP94]] acq_rel, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP96:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP96]] acq_rel, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP98:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP99:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP98]] acq_rel, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP100:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP101:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP102:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP100]], i8 [[TMP101]] acq_rel acquire, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP103:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP104:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP105:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP103]], i8 [[TMP104]] acq_rel acquire, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP106:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP107:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP108:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP106]], i8 [[TMP107]] acq_rel acquire, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP109:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP110:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP111:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP109]], i8 [[TMP110]] acq_rel acquire, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP112:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP112]] acquire, align 1
+// CHECK-NEXT:    [[TMP114:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP115:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP114]] acquire, align 1
+// CHECK-NEXT:    [[TMP116:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP117:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP116]] acquire, align 1
+// CHECK-NEXT:    [[TMP118:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP118]] acquire, align 1
+// CHECK-NEXT:    [[TMP120:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP121:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP120]] acquire, align 1
+// CHECK-NEXT:    [[TMP122:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP122]] acquire, align 1
+// CHECK-NEXT:    [[TMP124:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP125:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP124]] acquire, align 1
+// CHECK-NEXT:    [[TMP126:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP127:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP126]] acquire, align 1
+// CHECK-NEXT:    [[TMP128:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP129:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP130:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP128]], i8 [[TMP129]] acquire acquire, align 1
+// CHECK-NEXT:    [[TMP131:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP132:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP133:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP131]], i8 [[TMP132]] acquire acquire, align 1
+// CHECK-NEXT:    [[TMP134:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP135:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP136:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP134]], i8 [[TMP135]] acquire acquire, align 1
+// CHECK-NEXT:    [[TMP137:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP138:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP139:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP137]], i8 [[TMP138]] acquire acquire, align 1
+// CHECK-NEXT:    [[TMP140:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP141:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP140]] acquire, align 1
+// CHECK-NEXT:    [[TMP142:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP143:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP142]] acquire, align 1
+// CHECK-NEXT:    [[TMP144:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP145:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP144]] acquire, align 1
+// CHECK-NEXT:    [[TMP146:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP147:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP146]] acquire, align 1
+// CHECK-NEXT:    [[TMP148:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP149:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP148]] acquire, align 1
+// CHECK-NEXT:    [[TMP150:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP151:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP150]] acquire, align 1
+// CHECK-NEXT:    [[TMP152:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP153:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP152]] acquire, align 1
+// CHECK-NEXT:    [[TMP154:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP155:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP154]] acquire, align 1
+// CHECK-NEXT:    [[TMP156:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP157:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP158:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP156]], i8 [[TMP157]] acquire acquire, align 1
+// CHECK-NEXT:    [[TMP159:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP160:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP161:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP159]], i8 [[TMP160]] acquire acquire, align 1
+// CHECK-NEXT:    [[TMP162:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP163:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP164:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP162]], i8 [[TMP163]] acquire acquire, align 1
+// CHECK-NEXT:    [[TMP165:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP166:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP167:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP165]], i8 [[TMP166]] acquire acquire, align 1
+// CHECK-NEXT:    [[TMP168:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP169:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP168]] monotonic, align 1
+// CHECK-NEXT:    [[TMP170:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP171:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP170]] monotonic, align 1
+// CHECK-NEXT:    [[TMP172:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP173:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP172]] monotonic, align 1
+// CHECK-NEXT:    [[TMP174:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP175:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP174]] monotonic, align 1
+// CHECK-NEXT:    [[TMP176:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP177:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP176]] monotonic, align 1
+// CHECK-NEXT:    [[TMP178:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP179:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP178]] monotonic, align 1
+// CHECK-NEXT:    [[TMP180:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP181:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP180]] monotonic, align 1
+// CHECK-NEXT:    [[TMP182:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP183:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP182]] monotonic, align 1
+// CHECK-NEXT:    [[TMP184:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP185:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP186:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP184]], i8 [[TMP185]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP187:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP188:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP189:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP187]], i8 [[TMP188]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP190:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP191:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP192:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP190]], i8 [[TMP191]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP193:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP194:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP195:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP193]], i8 [[TMP194]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP196:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP197:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP196]] monotonic, align 1
+// CHECK-NEXT:    [[TMP198:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP199:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP198]] monotonic, align 1
+// CHECK-NEXT:    [[TMP200:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP201:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP200]] monotonic, align 1
+// CHECK-NEXT:    [[TMP202:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP203:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP202]] monotonic, align 1
+// CHECK-NEXT:    [[TMP204:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP205:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP204]] monotonic, align 1
+// CHECK-NEXT:    [[TMP206:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP207:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP206]] monotonic, align 1
+// CHECK-NEXT:    [[TMP208:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP209:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP208]] monotonic, align 1
+// CHECK-NEXT:    [[TMP210:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP211:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP210]] monotonic, align 1
+// CHECK-NEXT:    [[TMP212:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP213:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP214:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP212]], i8 [[TMP213]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP215:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP216:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP217:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP215]], i8 [[TMP216]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP218:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP219:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP220:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP218]], i8 [[TMP219]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP221:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP222:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP223:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP221]], i8 [[TMP222]] monotonic monotonic, align 1
+// CHECK-NEXT:    [[TMP224:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP225:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP224]] release, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP226:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP227:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP226]] release, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP228:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP229:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP228]] release, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP230:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP231:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP230]] release, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP232:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP233:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP232]] release, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP234:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP235:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP234]] release, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP236:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP237:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP236]] release, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP238:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP239:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP238]] release, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP240:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP241:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP242:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP240]], i8 [[TMP241]] release monotonic, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP243:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP244:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP245:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP243]], i8 [[TMP244]] release monotonic, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP246:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP247:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP248:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP246]], i8 [[TMP247]] release monotonic, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP249:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP250:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP251:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP249]], i8 [[TMP250]] release monotonic, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP252:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP253:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP252]] release, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP254:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP255:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP254]] release, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP256:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP257:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP256]] release, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP258:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP259:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP258]] release, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP260:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP261:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP260]] release, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP262:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP263:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP262]] release, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP264:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP265:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP264]] release, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP266:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP267:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP266]] release, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP268:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP269:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP270:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP268]], i8 [[TMP269]] release monotonic, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP271:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP272:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP273:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP271]], i8 [[TMP272]] release monotonic, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP274:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP275:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP276:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP274]], i8 [[TMP275]] release monotonic, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP277:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP278:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP279:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP277]], i8 [[TMP278]] release monotonic, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP280:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP281:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP280]] seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP282:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP283:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP282]] seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP284:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP285:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP284]] seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP286:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP287:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP286]] seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP288:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP289:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP288]] seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP290:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP291:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP290]] seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP292:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP293:%.*]] = atomicrmw umax i8* [[CX]], i8 [[TMP292]] seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP294:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP295:%.*]] = atomicrmw umin i8* [[CX]], i8 [[TMP294]] seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP296:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP297:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP298:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP296]], i8 [[TMP297]] seq_cst seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP299:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP300:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP301:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP299]], i8 [[TMP300]] seq_cst seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP302:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP303:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP304:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP302]], i8 [[TMP303]] seq_cst seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP305:%.*]] = load i8, i8* [[CE]], align 1
+// CHECK-NEXT:    [[TMP306:%.*]] = load i8, i8* [[CD]], align 1
+// CHECK-NEXT:    [[TMP307:%.*]] = cmpxchg i8* [[CX]], i8 [[TMP305]], i8 [[TMP306]] seq_cst seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP308:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP309:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP308]] seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP310:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP311:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP310]] seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP312:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP313:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP312]] seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP314:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP315:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP314]] seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP316:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP317:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP316]] seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP318:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP319:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP318]] seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP320:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP321:%.*]] = atomicrmw umax i8* [[UCX]], i8 [[TMP320]] seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP322:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP323:%.*]] = atomicrmw umin i8* [[UCX]], i8 [[TMP322]] seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP324:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP325:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP326:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP324]], i8 [[TMP325]] seq_cst seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP327:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP328:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP329:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP327]], i8 [[TMP328]] seq_cst seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP330:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP331:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP332:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP330]], i8 [[TMP331]] seq_cst seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP333:%.*]] = load i8, i8* [[UCE]], align 1
+// CHECK-NEXT:    [[TMP334:%.*]] = load i8, i8* [[UCD]], align 1
+// CHECK-NEXT:    [[TMP335:%.*]] = cmpxchg i8* [[UCX]], i8 [[TMP333]], i8 [[TMP334]] seq_cst seq_cst, align 1
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP336:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP337:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP336]] monotonic, align 2
+// CHECK-NEXT:    [[TMP338:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP339:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP338]] monotonic, align 2
+// CHECK-NEXT:    [[TMP340:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP341:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP340]] monotonic, align 2
+// CHECK-NEXT:    [[TMP342:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP343:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP342]] monotonic, align 2
+// CHECK-NEXT:    [[TMP344:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP345:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP344]] monotonic, align 2
+// CHECK-NEXT:    [[TMP346:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP347:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP346]] monotonic, align 2
+// CHECK-NEXT:    [[TMP348:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP349:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP348]] monotonic, align 2
+// CHECK-NEXT:    [[TMP350:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP351:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP350]] monotonic, align 2
+// CHECK-NEXT:    [[TMP352:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP353:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP354:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP352]], i16 [[TMP353]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP355:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP356:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP357:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP355]], i16 [[TMP356]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP358:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP359:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP360:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP358]], i16 [[TMP359]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP361:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP362:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP363:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP361]], i16 [[TMP362]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP364:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP365:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP364]] monotonic, align 2
+// CHECK-NEXT:    [[TMP366:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP367:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP366]] monotonic, align 2
+// CHECK-NEXT:    [[TMP368:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP369:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP368]] monotonic, align 2
+// CHECK-NEXT:    [[TMP370:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP371:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP370]] monotonic, align 2
+// CHECK-NEXT:    [[TMP372:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP373:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP372]] monotonic, align 2
+// CHECK-NEXT:    [[TMP374:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP375:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP374]] monotonic, align 2
+// CHECK-NEXT:    [[TMP376:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP377:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP376]] monotonic, align 2
+// CHECK-NEXT:    [[TMP378:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP379:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP378]] monotonic, align 2
+// CHECK-NEXT:    [[TMP380:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP381:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP382:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP380]], i16 [[TMP381]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP383:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP384:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP385:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP383]], i16 [[TMP384]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP386:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP387:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP388:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP386]], i16 [[TMP387]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP389:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP390:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP391:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP389]], i16 [[TMP390]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP392:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP393:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP392]] acq_rel, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP394:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP395:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP394]] acq_rel, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP396:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP397:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP396]] acq_rel, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP398:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP399:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP398]] acq_rel, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP400:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP401:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP400]] acq_rel, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP402:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP403:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP402]] acq_rel, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP404:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP405:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP404]] acq_rel, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP406:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP407:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP406]] acq_rel, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP408:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP409:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP410:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP408]], i16 [[TMP409]] acq_rel acquire, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP411:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP412:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP413:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP411]], i16 [[TMP412]] acq_rel acquire, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP414:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP415:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP416:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP414]], i16 [[TMP415]] acq_rel acquire, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP417:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP418:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP419:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP417]], i16 [[TMP418]] acq_rel acquire, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP420:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP421:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP420]] acq_rel, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP422:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP423:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP422]] acq_rel, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP424:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP425:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP424]] acq_rel, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP426:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP427:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP426]] acq_rel, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP428:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP429:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP428]] acq_rel, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP430:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP431:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP430]] acq_rel, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP432:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP433:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP432]] acq_rel, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP434:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP435:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP434]] acq_rel, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP436:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP437:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP438:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP436]], i16 [[TMP437]] acq_rel acquire, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP439:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP440:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP441:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP439]], i16 [[TMP440]] acq_rel acquire, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP442:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP443:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP444:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP442]], i16 [[TMP443]] acq_rel acquire, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP445:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP446:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP447:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP445]], i16 [[TMP446]] acq_rel acquire, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP448:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP449:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP448]] acquire, align 2
+// CHECK-NEXT:    [[TMP450:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP451:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP450]] acquire, align 2
+// CHECK-NEXT:    [[TMP452:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP453:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP452]] acquire, align 2
+// CHECK-NEXT:    [[TMP454:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP455:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP454]] acquire, align 2
+// CHECK-NEXT:    [[TMP456:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP457:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP456]] acquire, align 2
+// CHECK-NEXT:    [[TMP458:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP459:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP458]] acquire, align 2
+// CHECK-NEXT:    [[TMP460:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP461:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP460]] acquire, align 2
+// CHECK-NEXT:    [[TMP462:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP463:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP462]] acquire, align 2
+// CHECK-NEXT:    [[TMP464:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP465:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP466:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP464]], i16 [[TMP465]] acquire acquire, align 2
+// CHECK-NEXT:    [[TMP467:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP468:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP469:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP467]], i16 [[TMP468]] acquire acquire, align 2
+// CHECK-NEXT:    [[TMP470:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP471:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP472:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP470]], i16 [[TMP471]] acquire acquire, align 2
+// CHECK-NEXT:    [[TMP473:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP474:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP475:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP473]], i16 [[TMP474]] acquire acquire, align 2
+// CHECK-NEXT:    [[TMP476:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP477:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP476]] acquire, align 2
+// CHECK-NEXT:    [[TMP478:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP479:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP478]] acquire, align 2
+// CHECK-NEXT:    [[TMP480:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP481:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP480]] acquire, align 2
+// CHECK-NEXT:    [[TMP482:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP483:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP482]] acquire, align 2
+// CHECK-NEXT:    [[TMP484:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP485:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP484]] acquire, align 2
+// CHECK-NEXT:    [[TMP486:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP487:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP486]] acquire, align 2
+// CHECK-NEXT:    [[TMP488:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP489:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP488]] acquire, align 2
+// CHECK-NEXT:    [[TMP490:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP491:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP490]] acquire, align 2
+// CHECK-NEXT:    [[TMP492:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP493:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP494:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP492]], i16 [[TMP493]] acquire acquire, align 2
+// CHECK-NEXT:    [[TMP495:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP496:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP497:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP495]], i16 [[TMP496]] acquire acquire, align 2
+// CHECK-NEXT:    [[TMP498:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP499:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP500:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP498]], i16 [[TMP499]] acquire acquire, align 2
+// CHECK-NEXT:    [[TMP501:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP502:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP503:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP501]], i16 [[TMP502]] acquire acquire, align 2
+// CHECK-NEXT:    [[TMP504:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP505:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP504]] monotonic, align 2
+// CHECK-NEXT:    [[TMP506:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP507:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP506]] monotonic, align 2
+// CHECK-NEXT:    [[TMP508:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP509:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP508]] monotonic, align 2
+// CHECK-NEXT:    [[TMP510:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP511:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP510]] monotonic, align 2
+// CHECK-NEXT:    [[TMP512:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP513:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP512]] monotonic, align 2
+// CHECK-NEXT:    [[TMP514:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP515:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP514]] monotonic, align 2
+// CHECK-NEXT:    [[TMP516:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP517:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP516]] monotonic, align 2
+// CHECK-NEXT:    [[TMP518:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP519:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP518]] monotonic, align 2
+// CHECK-NEXT:    [[TMP520:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP521:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP522:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP520]], i16 [[TMP521]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP523:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP524:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP525:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP523]], i16 [[TMP524]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP526:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP527:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP528:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP526]], i16 [[TMP527]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP529:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP530:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP531:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP529]], i16 [[TMP530]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP532:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP533:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP532]] monotonic, align 2
+// CHECK-NEXT:    [[TMP534:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP535:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP534]] monotonic, align 2
+// CHECK-NEXT:    [[TMP536:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP537:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP536]] monotonic, align 2
+// CHECK-NEXT:    [[TMP538:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP539:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP538]] monotonic, align 2
+// CHECK-NEXT:    [[TMP540:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP541:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP540]] monotonic, align 2
+// CHECK-NEXT:    [[TMP542:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP543:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP542]] monotonic, align 2
+// CHECK-NEXT:    [[TMP544:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP545:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP544]] monotonic, align 2
+// CHECK-NEXT:    [[TMP546:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP547:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP546]] monotonic, align 2
+// CHECK-NEXT:    [[TMP548:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP549:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP550:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP548]], i16 [[TMP549]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP551:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP552:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP553:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP551]], i16 [[TMP552]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP554:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP555:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP556:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP554]], i16 [[TMP555]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP557:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP558:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP559:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP557]], i16 [[TMP558]] monotonic monotonic, align 2
+// CHECK-NEXT:    [[TMP560:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP561:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP560]] release, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP562:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP563:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP562]] release, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP564:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP565:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP564]] release, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP566:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP567:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP566]] release, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP568:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP569:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP568]] release, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP570:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP571:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP570]] release, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP572:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP573:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP572]] release, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP574:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP575:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP574]] release, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP576:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP577:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP578:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP576]], i16 [[TMP577]] release monotonic, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP579:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP580:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP581:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP579]], i16 [[TMP580]] release monotonic, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP582:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP583:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP584:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP582]], i16 [[TMP583]] release monotonic, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP585:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP586:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP587:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP585]], i16 [[TMP586]] release monotonic, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP588:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP589:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP588]] release, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP590:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP591:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP590]] release, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP592:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP593:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP592]] release, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP594:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP595:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP594]] release, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP596:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP597:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP596]] release, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP598:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP599:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP598]] release, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP600:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP601:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP600]] release, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP602:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP603:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP602]] release, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP604:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP605:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP606:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP604]], i16 [[TMP605]] release monotonic, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP607:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP608:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP609:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP607]], i16 [[TMP608]] release monotonic, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP610:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP611:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP612:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP610]], i16 [[TMP611]] release monotonic, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP613:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP614:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP615:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP613]], i16 [[TMP614]] release monotonic, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP616:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP617:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP616]] seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP618:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP619:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP618]] seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP620:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP621:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP620]] seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP622:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP623:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP622]] seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP624:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP625:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP624]] seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP626:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP627:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP626]] seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP628:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP629:%.*]] = atomicrmw umax i16* [[SX]], i16 [[TMP628]] seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP630:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP631:%.*]] = atomicrmw umin i16* [[SX]], i16 [[TMP630]] seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP632:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP633:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP634:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP632]], i16 [[TMP633]] seq_cst seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP635:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP636:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP637:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP635]], i16 [[TMP636]] seq_cst seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP638:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP639:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP640:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP638]], i16 [[TMP639]] seq_cst seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP641:%.*]] = load i16, i16* [[SE]], align 2
+// CHECK-NEXT:    [[TMP642:%.*]] = load i16, i16* [[SD]], align 2
+// CHECK-NEXT:    [[TMP643:%.*]] = cmpxchg i16* [[SX]], i16 [[TMP641]], i16 [[TMP642]] seq_cst seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP644:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP645:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP644]] seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP646:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP647:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP646]] seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP648:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP649:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP648]] seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP650:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP651:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP650]] seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP652:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP653:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP652]] seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP654:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP655:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP654]] seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP656:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP657:%.*]] = atomicrmw umax i16* [[USX]], i16 [[TMP656]] seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP658:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP659:%.*]] = atomicrmw umin i16* [[USX]], i16 [[TMP658]] seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP660:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP661:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP662:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP660]], i16 [[TMP661]] seq_cst seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP663:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP664:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP665:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP663]], i16 [[TMP664]] seq_cst seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP666:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP667:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP668:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP666]], i16 [[TMP667]] seq_cst seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP669:%.*]] = load i16, i16* [[USE]], align 2
+// CHECK-NEXT:    [[TMP670:%.*]] = load i16, i16* [[USD]], align 2
+// CHECK-NEXT:    [[TMP671:%.*]] = cmpxchg i16* [[USX]], i16 [[TMP669]], i16 [[TMP670]] seq_cst seq_cst, align 2
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP672:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP673:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP672]] monotonic, align 4
+// CHECK-NEXT:    [[TMP674:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP675:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP674]] monotonic, align 4
+// CHECK-NEXT:    [[TMP676:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP677:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP676]] monotonic, align 4
+// CHECK-NEXT:    [[TMP678:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP679:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP678]] monotonic, align 4
+// CHECK-NEXT:    [[TMP680:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP681:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP680]] monotonic, align 4
+// CHECK-NEXT:    [[TMP682:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP683:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP682]] monotonic, align 4
+// CHECK-NEXT:    [[TMP684:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP685:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP684]] monotonic, align 4
+// CHECK-NEXT:    [[TMP686:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP687:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP686]] monotonic, align 4
+// CHECK-NEXT:    [[TMP688:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP689:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP690:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP688]], i32 [[TMP689]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP691:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP692:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP693:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP691]], i32 [[TMP692]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP694:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP695:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP696:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP694]], i32 [[TMP695]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP697:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP698:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP699:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP697]], i32 [[TMP698]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP700:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP701:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP700]] monotonic, align 4
+// CHECK-NEXT:    [[TMP702:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP703:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP702]] monotonic, align 4
+// CHECK-NEXT:    [[TMP704:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP705:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP704]] monotonic, align 4
+// CHECK-NEXT:    [[TMP706:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP707:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP706]] monotonic, align 4
+// CHECK-NEXT:    [[TMP708:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP709:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP708]] monotonic, align 4
+// CHECK-NEXT:    [[TMP710:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP711:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP710]] monotonic, align 4
+// CHECK-NEXT:    [[TMP712:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP713:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP712]] monotonic, align 4
+// CHECK-NEXT:    [[TMP714:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP715:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP714]] monotonic, align 4
+// CHECK-NEXT:    [[TMP716:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP717:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP718:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP716]], i32 [[TMP717]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP719:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP720:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP721:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP719]], i32 [[TMP720]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP722:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP723:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP724:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP722]], i32 [[TMP723]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP725:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP726:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP727:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP725]], i32 [[TMP726]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP728:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP729:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP728]] acq_rel, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP730:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP731:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP730]] acq_rel, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP732:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP733:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP732]] acq_rel, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP734:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP735:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP734]] acq_rel, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP736:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP737:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP736]] acq_rel, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP738:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP739:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP738]] acq_rel, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP740:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP741:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP740]] acq_rel, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP742:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP743:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP742]] acq_rel, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP744:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP745:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP746:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP744]], i32 [[TMP745]] acq_rel acquire, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP747:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP748:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP749:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP747]], i32 [[TMP748]] acq_rel acquire, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP750:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP751:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP752:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP750]], i32 [[TMP751]] acq_rel acquire, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP753:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP754:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP755:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP753]], i32 [[TMP754]] acq_rel acquire, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP756:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP757:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP756]] acq_rel, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP758:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP759:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP758]] acq_rel, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP760:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP761:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP760]] acq_rel, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP762:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP763:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP762]] acq_rel, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP764:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP765:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP764]] acq_rel, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP766:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP767:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP766]] acq_rel, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP768:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP769:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP768]] acq_rel, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP770:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP771:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP770]] acq_rel, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP772:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP773:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP774:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP772]], i32 [[TMP773]] acq_rel acquire, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP775:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP776:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP777:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP775]], i32 [[TMP776]] acq_rel acquire, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP778:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP779:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP780:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP778]], i32 [[TMP779]] acq_rel acquire, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP781:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP782:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP783:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP781]], i32 [[TMP782]] acq_rel acquire, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP784:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP785:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP784]] acquire, align 4
+// CHECK-NEXT:    [[TMP786:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP787:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP786]] acquire, align 4
+// CHECK-NEXT:    [[TMP788:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP789:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP788]] acquire, align 4
+// CHECK-NEXT:    [[TMP790:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP791:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP790]] acquire, align 4
+// CHECK-NEXT:    [[TMP792:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP793:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP792]] acquire, align 4
+// CHECK-NEXT:    [[TMP794:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP795:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP794]] acquire, align 4
+// CHECK-NEXT:    [[TMP796:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP797:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP796]] acquire, align 4
+// CHECK-NEXT:    [[TMP798:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP799:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP798]] acquire, align 4
+// CHECK-NEXT:    [[TMP800:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP801:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP802:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP800]], i32 [[TMP801]] acquire acquire, align 4
+// CHECK-NEXT:    [[TMP803:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP804:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP805:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP803]], i32 [[TMP804]] acquire acquire, align 4
+// CHECK-NEXT:    [[TMP806:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP807:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP808:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP806]], i32 [[TMP807]] acquire acquire, align 4
+// CHECK-NEXT:    [[TMP809:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP810:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP811:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP809]], i32 [[TMP810]] acquire acquire, align 4
+// CHECK-NEXT:    [[TMP812:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP813:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP812]] acquire, align 4
+// CHECK-NEXT:    [[TMP814:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP815:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP814]] acquire, align 4
+// CHECK-NEXT:    [[TMP816:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP817:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP816]] acquire, align 4
+// CHECK-NEXT:    [[TMP818:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP819:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP818]] acquire, align 4
+// CHECK-NEXT:    [[TMP820:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP821:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP820]] acquire, align 4
+// CHECK-NEXT:    [[TMP822:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP823:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP822]] acquire, align 4
+// CHECK-NEXT:    [[TMP824:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP825:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP824]] acquire, align 4
+// CHECK-NEXT:    [[TMP826:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP827:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP826]] acquire, align 4
+// CHECK-NEXT:    [[TMP828:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP829:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP830:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP828]], i32 [[TMP829]] acquire acquire, align 4
+// CHECK-NEXT:    [[TMP831:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP832:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP833:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP831]], i32 [[TMP832]] acquire acquire, align 4
+// CHECK-NEXT:    [[TMP834:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP835:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP836:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP834]], i32 [[TMP835]] acquire acquire, align 4
+// CHECK-NEXT:    [[TMP837:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP838:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP839:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP837]], i32 [[TMP838]] acquire acquire, align 4
+// CHECK-NEXT:    [[TMP840:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP841:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP840]] monotonic, align 4
+// CHECK-NEXT:    [[TMP842:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP843:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP842]] monotonic, align 4
+// CHECK-NEXT:    [[TMP844:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP845:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP844]] monotonic, align 4
+// CHECK-NEXT:    [[TMP846:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP847:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP846]] monotonic, align 4
+// CHECK-NEXT:    [[TMP848:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP849:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP848]] monotonic, align 4
+// CHECK-NEXT:    [[TMP850:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP851:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP850]] monotonic, align 4
+// CHECK-NEXT:    [[TMP852:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP853:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP852]] monotonic, align 4
+// CHECK-NEXT:    [[TMP854:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP855:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP854]] monotonic, align 4
+// CHECK-NEXT:    [[TMP856:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP857:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP858:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP856]], i32 [[TMP857]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP859:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP860:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP861:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP859]], i32 [[TMP860]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP862:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP863:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP864:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP862]], i32 [[TMP863]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP865:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP866:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP867:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP865]], i32 [[TMP866]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP868:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP869:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP868]] monotonic, align 4
+// CHECK-NEXT:    [[TMP870:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP871:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP870]] monotonic, align 4
+// CHECK-NEXT:    [[TMP872:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP873:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP872]] monotonic, align 4
+// CHECK-NEXT:    [[TMP874:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP875:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP874]] monotonic, align 4
+// CHECK-NEXT:    [[TMP876:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP877:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP876]] monotonic, align 4
+// CHECK-NEXT:    [[TMP878:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP879:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP878]] monotonic, align 4
+// CHECK-NEXT:    [[TMP880:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP881:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP880]] monotonic, align 4
+// CHECK-NEXT:    [[TMP882:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP883:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP882]] monotonic, align 4
+// CHECK-NEXT:    [[TMP884:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP885:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP886:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP884]], i32 [[TMP885]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP887:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP888:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP889:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP887]], i32 [[TMP888]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP890:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP891:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP892:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP890]], i32 [[TMP891]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP893:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP894:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP895:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP893]], i32 [[TMP894]] monotonic monotonic, align 4
+// CHECK-NEXT:    [[TMP896:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP897:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP896]] release, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP898:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP899:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP898]] release, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP900:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP901:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP900]] release, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP902:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP903:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP902]] release, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP904:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP905:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP904]] release, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP906:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP907:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP906]] release, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP908:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP909:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP908]] release, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP910:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP911:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP910]] release, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP912:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP913:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP914:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP912]], i32 [[TMP913]] release monotonic, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP915:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP916:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP917:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP915]], i32 [[TMP916]] release monotonic, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP918:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP919:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP920:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP918]], i32 [[TMP919]] release monotonic, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP921:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP922:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP923:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP921]], i32 [[TMP922]] release monotonic, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP924:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP925:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP924]] release, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP926:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP927:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP926]] release, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP928:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP929:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP928]] release, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP930:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP931:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP930]] release, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP932:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP933:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP932]] release, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP934:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP935:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP934]] release, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP936:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP937:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP936]] release, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP938:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP939:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP938]] release, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP940:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP941:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP942:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP940]], i32 [[TMP941]] release monotonic, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP943:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP944:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP945:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP943]], i32 [[TMP944]] release monotonic, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP946:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP947:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP948:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP946]], i32 [[TMP947]] release monotonic, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP949:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP950:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP951:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP949]], i32 [[TMP950]] release monotonic, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP952:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP953:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP952]] seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP954:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP955:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP954]] seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP956:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP957:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP956]] seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP958:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP959:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP958]] seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP960:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP961:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP960]] seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP962:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP963:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP962]] seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP964:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP965:%.*]] = atomicrmw umax i32* [[IX]], i32 [[TMP964]] seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP966:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP967:%.*]] = atomicrmw umin i32* [[IX]], i32 [[TMP966]] seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP968:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP969:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP970:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP968]], i32 [[TMP969]] seq_cst seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP971:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP972:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP973:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP971]], i32 [[TMP972]] seq_cst seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP974:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP975:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP976:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP974]], i32 [[TMP975]] seq_cst seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP977:%.*]] = load i32, i32* [[IE]], align 4
+// CHECK-NEXT:    [[TMP978:%.*]] = load i32, i32* [[ID]], align 4
+// CHECK-NEXT:    [[TMP979:%.*]] = cmpxchg i32* [[IX]], i32 [[TMP977]], i32 [[TMP978]] seq_cst seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP980:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP981:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP980]] seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP982:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP983:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP982]] seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP984:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP985:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP984]] seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP986:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP987:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP986]] seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP988:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP989:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP988]] seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP990:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP991:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP990]] seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP992:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP993:%.*]] = atomicrmw umax i32* [[UIX]], i32 [[TMP992]] seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP994:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP995:%.*]] = atomicrmw umin i32* [[UIX]], i32 [[TMP994]] seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP996:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP997:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP998:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP996]], i32 [[TMP997]] seq_cst seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP999:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP1000:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP1001:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP999]], i32 [[TMP1000]] seq_cst seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1002:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP1003:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP1004:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP1002]], i32 [[TMP1003]] seq_cst seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1005:%.*]] = load i32, i32* [[UIE]], align 4
+// CHECK-NEXT:    [[TMP1006:%.*]] = load i32, i32* [[UID]], align 4
+// CHECK-NEXT:    [[TMP1007:%.*]] = cmpxchg i32* [[UIX]], i32 [[TMP1005]], i32 [[TMP1006]] seq_cst seq_cst, align 4
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1008:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1009:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1008]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1010:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1011:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1010]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1012:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1013:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1012]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1014:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1015:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1014]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1016:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1017:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1016]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1018:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1019:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1018]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1020:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1021:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1020]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1022:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1023:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1022]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1024:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1025:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1026:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1024]], i64 [[TMP1025]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1027:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1028:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1029:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1027]], i64 [[TMP1028]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1030:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1031:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1032:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1030]], i64 [[TMP1031]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1033:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1034:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1035:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1033]], i64 [[TMP1034]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1036:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1037:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1036]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1038:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1039:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1038]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1040:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1041:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1040]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1042:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1043:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1042]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1044:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1045:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1044]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1046:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1047:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1046]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1048:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1049:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1048]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1050:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1051:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1050]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1052:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1053:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1054:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1052]], i64 [[TMP1053]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1055:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1056:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1057:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1055]], i64 [[TMP1056]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1058:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1059:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1060:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1058]], i64 [[TMP1059]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1061:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1062:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1063:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1061]], i64 [[TMP1062]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1064:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1065:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1064]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1066:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1067:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1066]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1068:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1069:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1068]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1070:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1071:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1070]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1072:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1073:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1072]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1074:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1075:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1074]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1076:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1077:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1076]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1078:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1079:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1078]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1080:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1081:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1082:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1080]], i64 [[TMP1081]] acq_rel acquire, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1083:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1084:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1085:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1083]], i64 [[TMP1084]] acq_rel acquire, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1086:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1087:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1088:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1086]], i64 [[TMP1087]] acq_rel acquire, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1089:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1090:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1091:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1089]], i64 [[TMP1090]] acq_rel acquire, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1092:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1093:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1092]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1094:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1095:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1094]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1096:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1097:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1096]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1098:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1099:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1098]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1100:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1101:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1100]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1102:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1103:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1102]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1104:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1105:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1104]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1106:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1107:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1106]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1108:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1109:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1110:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1108]], i64 [[TMP1109]] acq_rel acquire, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1111:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1112:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1113:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1111]], i64 [[TMP1112]] acq_rel acquire, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1114:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1115:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1116:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1114]], i64 [[TMP1115]] acq_rel acquire, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1117:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1118:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1119:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1117]], i64 [[TMP1118]] acq_rel acquire, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1120:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1121:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1120]] acquire, align 8
+// CHECK-NEXT:    [[TMP1122:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1123:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1122]] acquire, align 8
+// CHECK-NEXT:    [[TMP1124:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1125:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1124]] acquire, align 8
+// CHECK-NEXT:    [[TMP1126:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1127:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1126]] acquire, align 8
+// CHECK-NEXT:    [[TMP1128:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1129:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1128]] acquire, align 8
+// CHECK-NEXT:    [[TMP1130:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1131:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1130]] acquire, align 8
+// CHECK-NEXT:    [[TMP1132:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1133:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1132]] acquire, align 8
+// CHECK-NEXT:    [[TMP1134:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1135:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1134]] acquire, align 8
+// CHECK-NEXT:    [[TMP1136:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1137:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1138:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1136]], i64 [[TMP1137]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP1139:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1140:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1141:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1139]], i64 [[TMP1140]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP1142:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1143:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1144:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1142]], i64 [[TMP1143]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP1145:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1146:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1147:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1145]], i64 [[TMP1146]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP1148:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1149:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1148]] acquire, align 8
+// CHECK-NEXT:    [[TMP1150:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1151:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1150]] acquire, align 8
+// CHECK-NEXT:    [[TMP1152:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1153:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1152]] acquire, align 8
+// CHECK-NEXT:    [[TMP1154:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1155:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1154]] acquire, align 8
+// CHECK-NEXT:    [[TMP1156:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1157:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1156]] acquire, align 8
+// CHECK-NEXT:    [[TMP1158:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1159:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1158]] acquire, align 8
+// CHECK-NEXT:    [[TMP1160:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1161:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1160]] acquire, align 8
+// CHECK-NEXT:    [[TMP1162:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1163:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1162]] acquire, align 8
+// CHECK-NEXT:    [[TMP1164:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1165:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1166:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1164]], i64 [[TMP1165]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP1167:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1168:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1169:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1167]], i64 [[TMP1168]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP1170:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1171:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1172:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1170]], i64 [[TMP1171]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP1173:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1174:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1175:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1173]], i64 [[TMP1174]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP1176:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1177:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1176]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1178:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1179:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1178]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1180:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1181:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1180]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1182:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1183:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1182]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1184:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1185:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1184]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1186:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1187:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1186]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1188:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1189:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1188]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1190:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1191:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1190]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1192:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1193:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1194:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1192]], i64 [[TMP1193]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1195:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1196:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1197:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1195]], i64 [[TMP1196]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1198:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1199:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1200:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1198]], i64 [[TMP1199]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1201:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1202:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1203:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1201]], i64 [[TMP1202]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1204:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1205:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1204]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1206:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1207:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1206]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1208:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1209:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1208]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1210:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1211:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1210]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1212:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1213:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1212]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1214:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1215:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1214]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1216:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1217:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1216]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1218:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1219:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1218]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1220:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1221:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1222:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1220]], i64 [[TMP1221]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1223:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1224:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1225:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1223]], i64 [[TMP1224]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1226:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1227:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1228:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1226]], i64 [[TMP1227]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1229:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1230:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1231:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1229]], i64 [[TMP1230]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1232:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1233:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1232]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1234:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1235:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1234]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1236:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1237:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1236]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1238:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1239:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1238]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1240:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1241:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1240]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1242:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1243:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1242]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1244:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1245:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1244]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1246:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1247:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1246]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1248:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1249:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1250:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1248]], i64 [[TMP1249]] release monotonic, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1251:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1252:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1253:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1251]], i64 [[TMP1252]] release monotonic, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1254:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1255:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1256:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1254]], i64 [[TMP1255]] release monotonic, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1257:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1258:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1259:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1257]], i64 [[TMP1258]] release monotonic, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1260:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1261:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1260]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1262:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1263:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1262]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1264:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1265:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1264]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1266:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1267:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1266]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1268:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1269:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1268]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1270:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1271:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1270]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1272:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1273:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1272]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1274:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1275:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1274]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1276:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1277:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1278:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1276]], i64 [[TMP1277]] release monotonic, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1279:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1280:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1281:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1279]], i64 [[TMP1280]] release monotonic, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1282:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1283:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1284:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1282]], i64 [[TMP1283]] release monotonic, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1285:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1286:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1287:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1285]], i64 [[TMP1286]] release monotonic, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1288:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1289:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1288]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1290:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1291:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1290]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1292:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1293:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1292]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1294:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1295:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1294]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1296:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1297:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1296]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1298:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1299:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1298]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1300:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1301:%.*]] = atomicrmw umax i64* [[LX]], i64 [[TMP1300]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1302:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1303:%.*]] = atomicrmw umin i64* [[LX]], i64 [[TMP1302]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1304:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1305:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1306:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1304]], i64 [[TMP1305]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1307:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1308:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1309:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1307]], i64 [[TMP1308]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1310:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1311:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1312:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1310]], i64 [[TMP1311]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1313:%.*]] = load i64, i64* [[LE]], align 8
+// CHECK-NEXT:    [[TMP1314:%.*]] = load i64, i64* [[LD]], align 8
+// CHECK-NEXT:    [[TMP1315:%.*]] = cmpxchg i64* [[LX]], i64 [[TMP1313]], i64 [[TMP1314]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1316:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1317:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1316]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1318:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1319:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1318]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1320:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1321:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1320]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1322:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1323:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1322]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1324:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1325:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1324]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1326:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1327:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1326]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1328:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1329:%.*]] = atomicrmw umax i64* [[ULX]], i64 [[TMP1328]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1330:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1331:%.*]] = atomicrmw umin i64* [[ULX]], i64 [[TMP1330]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1332:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1333:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1334:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1332]], i64 [[TMP1333]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1335:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1336:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1337:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1335]], i64 [[TMP1336]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1338:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1339:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1340:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1338]], i64 [[TMP1339]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1341:%.*]] = load i64, i64* [[ULE]], align 8
+// CHECK-NEXT:    [[TMP1342:%.*]] = load i64, i64* [[ULD]], align 8
+// CHECK-NEXT:    [[TMP1343:%.*]] = cmpxchg i64* [[ULX]], i64 [[TMP1341]], i64 [[TMP1342]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1344:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1345:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1344]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1346:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1347:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1346]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1348:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1349:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1348]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1350:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1351:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1350]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1352:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1353:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1352]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1354:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1355:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1354]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1356:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1357:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1356]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1358:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1359:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1358]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1360:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1361:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1362:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1360]], i64 [[TMP1361]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1363:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1364:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1365:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1363]], i64 [[TMP1364]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1366:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1367:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1368:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1366]], i64 [[TMP1367]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1369:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1370:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1371:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1369]], i64 [[TMP1370]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1372:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1373:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1372]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1374:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1375:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1374]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1376:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1377:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1376]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1378:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1379:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1378]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1380:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1381:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1380]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1382:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1383:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1382]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1384:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1385:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1384]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1386:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1387:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1386]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1388:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1389:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1390:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1388]], i64 [[TMP1389]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1391:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1392:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1393:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1391]], i64 [[TMP1392]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1394:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1395:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1396:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1394]], i64 [[TMP1395]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1397:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1398:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1399:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1397]], i64 [[TMP1398]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1400:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1401:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1400]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1402:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1403:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1402]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1404:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1405:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1404]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1406:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1407:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1406]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1408:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1409:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1408]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1410:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1411:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1410]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1412:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1413:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1412]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1414:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1415:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1414]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1416:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1417:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1418:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1416]], i64 [[TMP1417]] acq_rel acquire, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1419:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1420:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1421:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1419]], i64 [[TMP1420]] acq_rel acquire, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1422:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1423:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1424:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1422]], i64 [[TMP1423]] acq_rel acquire, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1425:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1426:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1427:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1425]], i64 [[TMP1426]] acq_rel acquire, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1428:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1429:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1428]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1430:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1431:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1430]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1432:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1433:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1432]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1434:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1435:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1434]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1436:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1437:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1436]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1438:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1439:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1438]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1440:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1441:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1440]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1442:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1443:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1442]] acq_rel, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1444:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1445:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1446:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1444]], i64 [[TMP1445]] acq_rel acquire, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1447:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1448:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1449:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1447]], i64 [[TMP1448]] acq_rel acquire, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1450:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1451:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1452:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1450]], i64 [[TMP1451]] acq_rel acquire, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1453:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1454:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1455:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1453]], i64 [[TMP1454]] acq_rel acquire, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1456:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1457:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1456]] acquire, align 8
+// CHECK-NEXT:    [[TMP1458:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1459:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1458]] acquire, align 8
+// CHECK-NEXT:    [[TMP1460:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1461:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1460]] acquire, align 8
+// CHECK-NEXT:    [[TMP1462:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1463:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1462]] acquire, align 8
+// CHECK-NEXT:    [[TMP1464:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1465:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1464]] acquire, align 8
+// CHECK-NEXT:    [[TMP1466:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1467:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1466]] acquire, align 8
+// CHECK-NEXT:    [[TMP1468:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1469:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1468]] acquire, align 8
+// CHECK-NEXT:    [[TMP1470:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1471:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1470]] acquire, align 8
+// CHECK-NEXT:    [[TMP1472:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1473:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1474:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1472]], i64 [[TMP1473]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP1475:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1476:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1477:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1475]], i64 [[TMP1476]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP1478:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1479:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1480:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1478]], i64 [[TMP1479]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP1481:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1482:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1483:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1481]], i64 [[TMP1482]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP1484:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1485:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1484]] acquire, align 8
+// CHECK-NEXT:    [[TMP1486:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1487:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1486]] acquire, align 8
+// CHECK-NEXT:    [[TMP1488:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1489:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1488]] acquire, align 8
+// CHECK-NEXT:    [[TMP1490:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1491:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1490]] acquire, align 8
+// CHECK-NEXT:    [[TMP1492:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1493:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1492]] acquire, align 8
+// CHECK-NEXT:    [[TMP1494:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1495:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1494]] acquire, align 8
+// CHECK-NEXT:    [[TMP1496:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1497:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1496]] acquire, align 8
+// CHECK-NEXT:    [[TMP1498:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1499:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1498]] acquire, align 8
+// CHECK-NEXT:    [[TMP1500:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1501:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1502:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1500]], i64 [[TMP1501]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP1503:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1504:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1505:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1503]], i64 [[TMP1504]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP1506:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1507:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1508:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1506]], i64 [[TMP1507]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP1509:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1510:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1511:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1509]], i64 [[TMP1510]] acquire acquire, align 8
+// CHECK-NEXT:    [[TMP1512:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1513:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1512]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1514:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1515:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1514]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1516:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1517:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1516]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1518:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1519:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1518]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1520:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1521:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1520]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1522:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1523:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1522]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1524:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1525:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1524]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1526:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1527:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1526]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1528:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1529:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1530:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1528]], i64 [[TMP1529]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1531:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1532:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1533:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1531]], i64 [[TMP1532]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1534:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1535:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1536:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1534]], i64 [[TMP1535]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1537:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1538:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1539:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1537]], i64 [[TMP1538]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1540:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1541:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1540]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1542:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1543:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1542]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1544:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1545:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1544]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1546:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1547:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1546]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1548:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1549:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1548]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1550:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1551:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1550]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1552:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1553:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1552]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1554:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1555:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1554]] monotonic, align 8
+// CHECK-NEXT:    [[TMP1556:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1557:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1558:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1556]], i64 [[TMP1557]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1559:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1560:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1561:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1559]], i64 [[TMP1560]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1562:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1563:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1564:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1562]], i64 [[TMP1563]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1565:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1566:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1567:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1565]], i64 [[TMP1566]] monotonic monotonic, align 8
+// CHECK-NEXT:    [[TMP1568:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1569:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1568]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1570:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1571:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1570]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1572:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1573:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1572]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1574:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1575:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1574]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1576:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1577:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1576]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1578:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1579:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1578]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1580:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1581:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1580]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1582:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1583:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1582]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1584:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1585:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1586:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1584]], i64 [[TMP1585]] release monotonic, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1587:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1588:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1589:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1587]], i64 [[TMP1588]] release monotonic, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1590:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1591:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1592:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1590]], i64 [[TMP1591]] release monotonic, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1593:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1594:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1595:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1593]], i64 [[TMP1594]] release monotonic, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1596:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1597:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1596]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1598:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1599:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1598]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1600:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1601:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1600]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1602:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1603:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1602]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1604:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1605:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1604]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1606:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1607:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1606]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1608:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1609:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1608]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1610:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1611:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1610]] release, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1612:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1613:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1614:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1612]], i64 [[TMP1613]] release monotonic, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1615:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1616:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1617:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1615]], i64 [[TMP1616]] release monotonic, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1618:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1619:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1620:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1618]], i64 [[TMP1619]] release monotonic, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1621:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1622:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1623:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1621]], i64 [[TMP1622]] release monotonic, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1624:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1625:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1624]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1626:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1627:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1626]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1628:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1629:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1628]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1630:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1631:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1630]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1632:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1633:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1632]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1634:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1635:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1634]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1636:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1637:%.*]] = atomicrmw umax i64* [[LLX]], i64 [[TMP1636]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1638:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1639:%.*]] = atomicrmw umin i64* [[LLX]], i64 [[TMP1638]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1640:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1641:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1642:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1640]], i64 [[TMP1641]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1643:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1644:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1645:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1643]], i64 [[TMP1644]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1646:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1647:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1648:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1646]], i64 [[TMP1647]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1649:%.*]] = load i64, i64* [[LLE]], align 8
+// CHECK-NEXT:    [[TMP1650:%.*]] = load i64, i64* [[LLD]], align 8
+// CHECK-NEXT:    [[TMP1651:%.*]] = cmpxchg i64* [[LLX]], i64 [[TMP1649]], i64 [[TMP1650]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1652:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1653:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1652]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1654:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1655:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1654]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1656:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1657:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1656]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1658:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1659:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1658]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1660:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1661:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1660]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1662:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1663:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1662]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1664:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1665:%.*]] = atomicrmw umax i64* [[ULLX]], i64 [[TMP1664]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1666:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1667:%.*]] = atomicrmw umin i64* [[ULLX]], i64 [[TMP1666]] seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1668:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1669:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1670:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1668]], i64 [[TMP1669]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1671:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1672:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1673:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1671]], i64 [[TMP1672]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1674:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1675:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1676:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1674]], i64 [[TMP1675]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    [[TMP1677:%.*]] = load i64, i64* [[ULLE]], align 8
+// CHECK-NEXT:    [[TMP1678:%.*]] = load i64, i64* [[ULLD]], align 8
+// CHECK-NEXT:    [[TMP1679:%.*]] = cmpxchg i64* [[ULLX]], i64 [[TMP1677]], i64 [[TMP1678]] seq_cst seq_cst, align 8
+// CHECK-NEXT:    call void @__kmpc_flush(%struct.ident_t* @[[GLOB1]])
+// CHECK-NEXT:    ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@foo
+// SIMD-ONLY0-SAME: () #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY0-NEXT:  entry:
+// SIMD-ONLY0-NEXT:    [[CX:%.*]] = alloca i8, align 1
+// SIMD-ONLY0-NEXT:    [[CE:%.*]] = alloca i8, align 1
+// SIMD-ONLY0-NEXT:    [[CD:%.*]] = alloca i8, align 1
+// SIMD-ONLY0-NEXT:    [[UCX:%.*]] = alloca i8, align 1
+// SIMD-ONLY0-NEXT:    [[UCE:%.*]] = alloca i8, align 1
+// SIMD-ONLY0-NEXT:    [[UCD:%.*]] = alloca i8, align 1
+// SIMD-ONLY0-NEXT:    [[SX:%.*]] = alloca i16, align 2
+// SIMD-ONLY0-NEXT:    [[SE:%.*]] = alloca i16, align 2
+// SIMD-ONLY0-NEXT:    [[SD:%.*]] = alloca i16, align 2
+// SIMD-ONLY0-NEXT:    [[USX:%.*]] = alloca i16, align 2
+// SIMD-ONLY0-NEXT:    [[USE:%.*]] = alloca i16, align 2
+// SIMD-ONLY0-NEXT:    [[USD:%.*]] = alloca i16, align 2
+// SIMD-ONLY0-NEXT:    [[IX:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT:    [[IE:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT:    [[ID:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT:    [[UIX:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT:    [[UIE:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT:    [[UID:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT:    [[LX:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT:    [[LE:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT:    [[LD:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT:    [[ULX:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT:    [[ULE:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT:    [[ULD:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT:    [[LLX:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT:    [[LLE:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT:    [[LLD:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT:    [[ULLX:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT:    [[ULLE:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT:    [[ULLD:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT:    [[FX:%.*]] = alloca float, align 4
+// SIMD-ONLY0-NEXT:    [[FE:%.*]] = alloca float, align 4
+// SIMD-ONLY0-NEXT:    [[FD:%.*]] = alloca float, align 4
+// SIMD-ONLY0-NEXT:    [[DX:%.*]] = alloca double, align 8
+// SIMD-ONLY0-NEXT:    [[DE:%.*]] = alloca double, align 8
+// SIMD-ONLY0-NEXT:    [[DD:%.*]] = alloca double, align 8
+// SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV:%.*]] = sext i8 [[TMP0]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1:%.*]] = sext i8 [[TMP1]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[CONV]], [[CONV1]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// SIMD-ONLY0:       cond.true:
+// SIMD-ONLY0-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END:%.*]]
+// SIMD-ONLY0:       cond.false:
+// SIMD-ONLY0-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV4:%.*]] = sext i8 [[TMP3]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END]]
+// SIMD-ONLY0:       cond.end:
+// SIMD-ONLY0-NEXT:    [[COND:%.*]] = phi i32 [ [[CONV3]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ]
+// SIMD-ONLY0-NEXT:    [[CONV5:%.*]] = trunc i32 [[COND]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV5]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV6:%.*]] = sext i8 [[TMP4]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV7:%.*]] = sext i8 [[TMP5]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP8:%.*]] = icmp slt i32 [[CONV6]], [[CONV7]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP8]], label [[COND_TRUE10:%.*]], label [[COND_FALSE12:%.*]]
+// SIMD-ONLY0:       cond.true10:
+// SIMD-ONLY0-NEXT:    [[TMP6:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV11:%.*]] = sext i8 [[TMP6]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END14:%.*]]
+// SIMD-ONLY0:       cond.false12:
+// SIMD-ONLY0-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP7]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END14]]
+// SIMD-ONLY0:       cond.end14:
+// SIMD-ONLY0-NEXT:    [[COND15:%.*]] = phi i32 [ [[CONV11]], [[COND_TRUE10]] ], [ [[CONV13]], [[COND_FALSE12]] ]
+// SIMD-ONLY0-NEXT:    [[CONV16:%.*]] = trunc i32 [[COND15]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV16]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP8:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP8]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP9]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP19:%.*]] = icmp sgt i32 [[CONV17]], [[CONV18]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP19]], label [[COND_TRUE21:%.*]], label [[COND_FALSE23:%.*]]
+// SIMD-ONLY0:       cond.true21:
+// SIMD-ONLY0-NEXT:    [[TMP10:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV22:%.*]] = sext i8 [[TMP10]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END25:%.*]]
+// SIMD-ONLY0:       cond.false23:
+// SIMD-ONLY0-NEXT:    [[TMP11:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV24:%.*]] = sext i8 [[TMP11]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END25]]
+// SIMD-ONLY0:       cond.end25:
+// SIMD-ONLY0-NEXT:    [[COND26:%.*]] = phi i32 [ [[CONV22]], [[COND_TRUE21]] ], [ [[CONV24]], [[COND_FALSE23]] ]
+// SIMD-ONLY0-NEXT:    [[CONV27:%.*]] = trunc i32 [[COND26]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV27]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP12:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV28:%.*]] = sext i8 [[TMP12]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP13:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV29:%.*]] = sext i8 [[TMP13]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP30:%.*]] = icmp slt i32 [[CONV28]], [[CONV29]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP30]], label [[COND_TRUE32:%.*]], label [[COND_FALSE34:%.*]]
+// SIMD-ONLY0:       cond.true32:
+// SIMD-ONLY0-NEXT:    [[TMP14:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV33:%.*]] = sext i8 [[TMP14]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END36:%.*]]
+// SIMD-ONLY0:       cond.false34:
+// SIMD-ONLY0-NEXT:    [[TMP15:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV35:%.*]] = sext i8 [[TMP15]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END36]]
+// SIMD-ONLY0:       cond.end36:
+// SIMD-ONLY0-NEXT:    [[COND37:%.*]] = phi i32 [ [[CONV33]], [[COND_TRUE32]] ], [ [[CONV35]], [[COND_FALSE34]] ]
+// SIMD-ONLY0-NEXT:    [[CONV38:%.*]] = trunc i32 [[COND37]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV38]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP16:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV39:%.*]] = sext i8 [[TMP16]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP17:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV40:%.*]] = sext i8 [[TMP17]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP41:%.*]] = icmp sgt i32 [[CONV39]], [[CONV40]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP41]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+// SIMD-ONLY0:       if.then:
+// SIMD-ONLY0-NEXT:    [[TMP18:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP18]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END]]
+// SIMD-ONLY0:       if.end:
+// SIMD-ONLY0-NEXT:    [[TMP19:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV43:%.*]] = sext i8 [[TMP19]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP20:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV44:%.*]] = sext i8 [[TMP20]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP45:%.*]] = icmp slt i32 [[CONV43]], [[CONV44]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP45]], label [[IF_THEN47:%.*]], label [[IF_END48:%.*]]
+// SIMD-ONLY0:       if.then47:
+// SIMD-ONLY0-NEXT:    [[TMP21:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP21]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END48]]
+// SIMD-ONLY0:       if.end48:
+// SIMD-ONLY0-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV49:%.*]] = sext i8 [[TMP22]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP23:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP23]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP51:%.*]] = icmp sgt i32 [[CONV49]], [[CONV50]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP51]], label [[IF_THEN53:%.*]], label [[IF_END54:%.*]]
+// SIMD-ONLY0:       if.then53:
+// SIMD-ONLY0-NEXT:    [[TMP24:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP24]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END54]]
+// SIMD-ONLY0:       if.end54:
+// SIMD-ONLY0-NEXT:    [[TMP25:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV55:%.*]] = sext i8 [[TMP25]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP26:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV56:%.*]] = sext i8 [[TMP26]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP57:%.*]] = icmp slt i32 [[CONV55]], [[CONV56]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP57]], label [[IF_THEN59:%.*]], label [[IF_END60:%.*]]
+// SIMD-ONLY0:       if.then59:
+// SIMD-ONLY0-NEXT:    [[TMP27:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP27]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END60]]
+// SIMD-ONLY0:       if.end60:
+// SIMD-ONLY0-NEXT:    [[TMP28:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV61:%.*]] = sext i8 [[TMP28]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP29:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV62:%.*]] = sext i8 [[TMP29]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP63:%.*]] = icmp eq i32 [[CONV61]], [[CONV62]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP63]], label [[COND_TRUE65:%.*]], label [[COND_FALSE67:%.*]]
+// SIMD-ONLY0:       cond.true65:
+// SIMD-ONLY0-NEXT:    [[TMP30:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV66:%.*]] = sext i8 [[TMP30]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END69:%.*]]
+// SIMD-ONLY0:       cond.false67:
+// SIMD-ONLY0-NEXT:    [[TMP31:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV68:%.*]] = sext i8 [[TMP31]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END69]]
+// SIMD-ONLY0:       cond.end69:
+// SIMD-ONLY0-NEXT:    [[COND70:%.*]] = phi i32 [ [[CONV66]], [[COND_TRUE65]] ], [ [[CONV68]], [[COND_FALSE67]] ]
+// SIMD-ONLY0-NEXT:    [[CONV71:%.*]] = trunc i32 [[COND70]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV71]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP32:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV72:%.*]] = sext i8 [[TMP32]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP33:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV73:%.*]] = sext i8 [[TMP33]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP74:%.*]] = icmp eq i32 [[CONV72]], [[CONV73]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP74]], label [[COND_TRUE76:%.*]], label [[COND_FALSE78:%.*]]
+// SIMD-ONLY0:       cond.true76:
+// SIMD-ONLY0-NEXT:    [[TMP34:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV77:%.*]] = sext i8 [[TMP34]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END80:%.*]]
+// SIMD-ONLY0:       cond.false78:
+// SIMD-ONLY0-NEXT:    [[TMP35:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP35]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END80]]
+// SIMD-ONLY0:       cond.end80:
+// SIMD-ONLY0-NEXT:    [[COND81:%.*]] = phi i32 [ [[CONV77]], [[COND_TRUE76]] ], [ [[CONV79]], [[COND_FALSE78]] ]
+// SIMD-ONLY0-NEXT:    [[CONV82:%.*]] = trunc i32 [[COND81]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV82]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP36:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV83:%.*]] = sext i8 [[TMP36]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP37:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV84:%.*]] = sext i8 [[TMP37]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP85:%.*]] = icmp eq i32 [[CONV83]], [[CONV84]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP85]], label [[IF_THEN87:%.*]], label [[IF_END88:%.*]]
+// SIMD-ONLY0:       if.then87:
+// SIMD-ONLY0-NEXT:    [[TMP38:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP38]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END88]]
+// SIMD-ONLY0:       if.end88:
+// SIMD-ONLY0-NEXT:    [[TMP39:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV89:%.*]] = sext i8 [[TMP39]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP40:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV90:%.*]] = sext i8 [[TMP40]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP91:%.*]] = icmp eq i32 [[CONV89]], [[CONV90]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP91]], label [[IF_THEN93:%.*]], label [[IF_END94:%.*]]
+// SIMD-ONLY0:       if.then93:
+// SIMD-ONLY0-NEXT:    [[TMP41:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP41]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END94]]
+// SIMD-ONLY0:       if.end94:
+// SIMD-ONLY0-NEXT:    [[TMP42:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV95:%.*]] = zext i8 [[TMP42]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP43:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV96:%.*]] = zext i8 [[TMP43]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP97:%.*]] = icmp sgt i32 [[CONV95]], [[CONV96]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP97]], label [[COND_TRUE99:%.*]], label [[COND_FALSE101:%.*]]
+// SIMD-ONLY0:       cond.true99:
+// SIMD-ONLY0-NEXT:    [[TMP44:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV100:%.*]] = zext i8 [[TMP44]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END103:%.*]]
+// SIMD-ONLY0:       cond.false101:
+// SIMD-ONLY0-NEXT:    [[TMP45:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV102:%.*]] = zext i8 [[TMP45]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END103]]
+// SIMD-ONLY0:       cond.end103:
+// SIMD-ONLY0-NEXT:    [[COND104:%.*]] = phi i32 [ [[CONV100]], [[COND_TRUE99]] ], [ [[CONV102]], [[COND_FALSE101]] ]
+// SIMD-ONLY0-NEXT:    [[CONV105:%.*]] = trunc i32 [[COND104]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV105]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP46:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV106:%.*]] = zext i8 [[TMP46]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP47:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV107:%.*]] = zext i8 [[TMP47]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP108:%.*]] = icmp slt i32 [[CONV106]], [[CONV107]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP108]], label [[COND_TRUE110:%.*]], label [[COND_FALSE112:%.*]]
+// SIMD-ONLY0:       cond.true110:
+// SIMD-ONLY0-NEXT:    [[TMP48:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV111:%.*]] = zext i8 [[TMP48]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END114:%.*]]
+// SIMD-ONLY0:       cond.false112:
+// SIMD-ONLY0-NEXT:    [[TMP49:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV113:%.*]] = zext i8 [[TMP49]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END114]]
+// SIMD-ONLY0:       cond.end114:
+// SIMD-ONLY0-NEXT:    [[COND115:%.*]] = phi i32 [ [[CONV111]], [[COND_TRUE110]] ], [ [[CONV113]], [[COND_FALSE112]] ]
+// SIMD-ONLY0-NEXT:    [[CONV116:%.*]] = trunc i32 [[COND115]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV116]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP50:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV117:%.*]] = zext i8 [[TMP50]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP51:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV118:%.*]] = zext i8 [[TMP51]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP119:%.*]] = icmp sgt i32 [[CONV117]], [[CONV118]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP119]], label [[COND_TRUE121:%.*]], label [[COND_FALSE123:%.*]]
+// SIMD-ONLY0:       cond.true121:
+// SIMD-ONLY0-NEXT:    [[TMP52:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV122:%.*]] = zext i8 [[TMP52]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END125:%.*]]
+// SIMD-ONLY0:       cond.false123:
+// SIMD-ONLY0-NEXT:    [[TMP53:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV124:%.*]] = zext i8 [[TMP53]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END125]]
+// SIMD-ONLY0:       cond.end125:
+// SIMD-ONLY0-NEXT:    [[COND126:%.*]] = phi i32 [ [[CONV122]], [[COND_TRUE121]] ], [ [[CONV124]], [[COND_FALSE123]] ]
+// SIMD-ONLY0-NEXT:    [[CONV127:%.*]] = trunc i32 [[COND126]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV127]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP54:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV128:%.*]] = zext i8 [[TMP54]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP55:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV129:%.*]] = zext i8 [[TMP55]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP130:%.*]] = icmp slt i32 [[CONV128]], [[CONV129]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP130]], label [[COND_TRUE132:%.*]], label [[COND_FALSE134:%.*]]
+// SIMD-ONLY0:       cond.true132:
+// SIMD-ONLY0-NEXT:    [[TMP56:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV133:%.*]] = zext i8 [[TMP56]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END136:%.*]]
+// SIMD-ONLY0:       cond.false134:
+// SIMD-ONLY0-NEXT:    [[TMP57:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV135:%.*]] = zext i8 [[TMP57]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END136]]
+// SIMD-ONLY0:       cond.end136:
+// SIMD-ONLY0-NEXT:    [[COND137:%.*]] = phi i32 [ [[CONV133]], [[COND_TRUE132]] ], [ [[CONV135]], [[COND_FALSE134]] ]
+// SIMD-ONLY0-NEXT:    [[CONV138:%.*]] = trunc i32 [[COND137]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV138]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP58:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV139:%.*]] = zext i8 [[TMP58]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP59:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV140:%.*]] = zext i8 [[TMP59]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP141:%.*]] = icmp sgt i32 [[CONV139]], [[CONV140]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP141]], label [[IF_THEN143:%.*]], label [[IF_END144:%.*]]
+// SIMD-ONLY0:       if.then143:
+// SIMD-ONLY0-NEXT:    [[TMP60:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP60]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END144]]
+// SIMD-ONLY0:       if.end144:
+// SIMD-ONLY0-NEXT:    [[TMP61:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV145:%.*]] = zext i8 [[TMP61]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP62:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV146:%.*]] = zext i8 [[TMP62]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP147:%.*]] = icmp slt i32 [[CONV145]], [[CONV146]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP147]], label [[IF_THEN149:%.*]], label [[IF_END150:%.*]]
+// SIMD-ONLY0:       if.then149:
+// SIMD-ONLY0-NEXT:    [[TMP63:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP63]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END150]]
+// SIMD-ONLY0:       if.end150:
+// SIMD-ONLY0-NEXT:    [[TMP64:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV151:%.*]] = zext i8 [[TMP64]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP65:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV152:%.*]] = zext i8 [[TMP65]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP153:%.*]] = icmp sgt i32 [[CONV151]], [[CONV152]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP153]], label [[IF_THEN155:%.*]], label [[IF_END156:%.*]]
+// SIMD-ONLY0:       if.then155:
+// SIMD-ONLY0-NEXT:    [[TMP66:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP66]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END156]]
+// SIMD-ONLY0:       if.end156:
+// SIMD-ONLY0-NEXT:    [[TMP67:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV157:%.*]] = zext i8 [[TMP67]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP68:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV158:%.*]] = zext i8 [[TMP68]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP159:%.*]] = icmp slt i32 [[CONV157]], [[CONV158]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP159]], label [[IF_THEN161:%.*]], label [[IF_END162:%.*]]
+// SIMD-ONLY0:       if.then161:
+// SIMD-ONLY0-NEXT:    [[TMP69:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP69]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END162]]
+// SIMD-ONLY0:       if.end162:
+// SIMD-ONLY0-NEXT:    [[TMP70:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV163:%.*]] = zext i8 [[TMP70]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP71:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV164:%.*]] = zext i8 [[TMP71]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP165:%.*]] = icmp eq i32 [[CONV163]], [[CONV164]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP165]], label [[COND_TRUE167:%.*]], label [[COND_FALSE169:%.*]]
+// SIMD-ONLY0:       cond.true167:
+// SIMD-ONLY0-NEXT:    [[TMP72:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV168:%.*]] = zext i8 [[TMP72]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END171:%.*]]
+// SIMD-ONLY0:       cond.false169:
+// SIMD-ONLY0-NEXT:    [[TMP73:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV170:%.*]] = zext i8 [[TMP73]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END171]]
+// SIMD-ONLY0:       cond.end171:
+// SIMD-ONLY0-NEXT:    [[COND172:%.*]] = phi i32 [ [[CONV168]], [[COND_TRUE167]] ], [ [[CONV170]], [[COND_FALSE169]] ]
+// SIMD-ONLY0-NEXT:    [[CONV173:%.*]] = trunc i32 [[COND172]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV173]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP74:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV174:%.*]] = zext i8 [[TMP74]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP75:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV175:%.*]] = zext i8 [[TMP75]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP176:%.*]] = icmp eq i32 [[CONV174]], [[CONV175]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP176]], label [[COND_TRUE178:%.*]], label [[COND_FALSE180:%.*]]
+// SIMD-ONLY0:       cond.true178:
+// SIMD-ONLY0-NEXT:    [[TMP76:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV179:%.*]] = zext i8 [[TMP76]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END182:%.*]]
+// SIMD-ONLY0:       cond.false180:
+// SIMD-ONLY0-NEXT:    [[TMP77:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV181:%.*]] = zext i8 [[TMP77]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END182]]
+// SIMD-ONLY0:       cond.end182:
+// SIMD-ONLY0-NEXT:    [[COND183:%.*]] = phi i32 [ [[CONV179]], [[COND_TRUE178]] ], [ [[CONV181]], [[COND_FALSE180]] ]
+// SIMD-ONLY0-NEXT:    [[CONV184:%.*]] = trunc i32 [[COND183]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV184]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP78:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV185:%.*]] = zext i8 [[TMP78]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP79:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV186:%.*]] = zext i8 [[TMP79]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP187:%.*]] = icmp eq i32 [[CONV185]], [[CONV186]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP187]], label [[IF_THEN189:%.*]], label [[IF_END190:%.*]]
+// SIMD-ONLY0:       if.then189:
+// SIMD-ONLY0-NEXT:    [[TMP80:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP80]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END190]]
+// SIMD-ONLY0:       if.end190:
+// SIMD-ONLY0-NEXT:    [[TMP81:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV191:%.*]] = zext i8 [[TMP81]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP82:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV192:%.*]] = zext i8 [[TMP82]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP193:%.*]] = icmp eq i32 [[CONV191]], [[CONV192]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP193]], label [[IF_THEN195:%.*]], label [[IF_END196:%.*]]
+// SIMD-ONLY0:       if.then195:
+// SIMD-ONLY0-NEXT:    [[TMP83:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP83]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END196]]
+// SIMD-ONLY0:       if.end196:
+// SIMD-ONLY0-NEXT:    [[TMP84:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV197:%.*]] = sext i8 [[TMP84]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP85:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV198:%.*]] = sext i8 [[TMP85]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP199:%.*]] = icmp sgt i32 [[CONV197]], [[CONV198]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP199]], label [[COND_TRUE201:%.*]], label [[COND_FALSE203:%.*]]
+// SIMD-ONLY0:       cond.true201:
+// SIMD-ONLY0-NEXT:    [[TMP86:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV202:%.*]] = sext i8 [[TMP86]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END205:%.*]]
+// SIMD-ONLY0:       cond.false203:
+// SIMD-ONLY0-NEXT:    [[TMP87:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV204:%.*]] = sext i8 [[TMP87]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END205]]
+// SIMD-ONLY0:       cond.end205:
+// SIMD-ONLY0-NEXT:    [[COND206:%.*]] = phi i32 [ [[CONV202]], [[COND_TRUE201]] ], [ [[CONV204]], [[COND_FALSE203]] ]
+// SIMD-ONLY0-NEXT:    [[CONV207:%.*]] = trunc i32 [[COND206]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV207]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP88:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV208:%.*]] = sext i8 [[TMP88]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP89:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV209:%.*]] = sext i8 [[TMP89]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP210:%.*]] = icmp slt i32 [[CONV208]], [[CONV209]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP210]], label [[COND_TRUE212:%.*]], label [[COND_FALSE214:%.*]]
+// SIMD-ONLY0:       cond.true212:
+// SIMD-ONLY0-NEXT:    [[TMP90:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV213:%.*]] = sext i8 [[TMP90]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END216:%.*]]
+// SIMD-ONLY0:       cond.false214:
+// SIMD-ONLY0-NEXT:    [[TMP91:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV215:%.*]] = sext i8 [[TMP91]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END216]]
+// SIMD-ONLY0:       cond.end216:
+// SIMD-ONLY0-NEXT:    [[COND217:%.*]] = phi i32 [ [[CONV213]], [[COND_TRUE212]] ], [ [[CONV215]], [[COND_FALSE214]] ]
+// SIMD-ONLY0-NEXT:    [[CONV218:%.*]] = trunc i32 [[COND217]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV218]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP92:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV219:%.*]] = sext i8 [[TMP92]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP93:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV220:%.*]] = sext i8 [[TMP93]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP221:%.*]] = icmp sgt i32 [[CONV219]], [[CONV220]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP221]], label [[COND_TRUE223:%.*]], label [[COND_FALSE225:%.*]]
+// SIMD-ONLY0:       cond.true223:
+// SIMD-ONLY0-NEXT:    [[TMP94:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV224:%.*]] = sext i8 [[TMP94]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END227:%.*]]
+// SIMD-ONLY0:       cond.false225:
+// SIMD-ONLY0-NEXT:    [[TMP95:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV226:%.*]] = sext i8 [[TMP95]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END227]]
+// SIMD-ONLY0:       cond.end227:
+// SIMD-ONLY0-NEXT:    [[COND228:%.*]] = phi i32 [ [[CONV224]], [[COND_TRUE223]] ], [ [[CONV226]], [[COND_FALSE225]] ]
+// SIMD-ONLY0-NEXT:    [[CONV229:%.*]] = trunc i32 [[COND228]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV229]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP96:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV230:%.*]] = sext i8 [[TMP96]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP97:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV231:%.*]] = sext i8 [[TMP97]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP232:%.*]] = icmp slt i32 [[CONV230]], [[CONV231]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP232]], label [[COND_TRUE234:%.*]], label [[COND_FALSE236:%.*]]
+// SIMD-ONLY0:       cond.true234:
+// SIMD-ONLY0-NEXT:    [[TMP98:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV235:%.*]] = sext i8 [[TMP98]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END238:%.*]]
+// SIMD-ONLY0:       cond.false236:
+// SIMD-ONLY0-NEXT:    [[TMP99:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV237:%.*]] = sext i8 [[TMP99]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END238]]
+// SIMD-ONLY0:       cond.end238:
+// SIMD-ONLY0-NEXT:    [[COND239:%.*]] = phi i32 [ [[CONV235]], [[COND_TRUE234]] ], [ [[CONV237]], [[COND_FALSE236]] ]
+// SIMD-ONLY0-NEXT:    [[CONV240:%.*]] = trunc i32 [[COND239]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV240]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP100:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV241:%.*]] = sext i8 [[TMP100]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP101:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV242:%.*]] = sext i8 [[TMP101]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP243:%.*]] = icmp sgt i32 [[CONV241]], [[CONV242]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP243]], label [[IF_THEN245:%.*]], label [[IF_END246:%.*]]
+// SIMD-ONLY0:       if.then245:
+// SIMD-ONLY0-NEXT:    [[TMP102:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP102]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END246]]
+// SIMD-ONLY0:       if.end246:
+// SIMD-ONLY0-NEXT:    [[TMP103:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV247:%.*]] = sext i8 [[TMP103]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP104:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV248:%.*]] = sext i8 [[TMP104]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP249:%.*]] = icmp slt i32 [[CONV247]], [[CONV248]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP249]], label [[IF_THEN251:%.*]], label [[IF_END252:%.*]]
+// SIMD-ONLY0:       if.then251:
+// SIMD-ONLY0-NEXT:    [[TMP105:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP105]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END252]]
+// SIMD-ONLY0:       if.end252:
+// SIMD-ONLY0-NEXT:    [[TMP106:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV253:%.*]] = sext i8 [[TMP106]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP107:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV254:%.*]] = sext i8 [[TMP107]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP255:%.*]] = icmp sgt i32 [[CONV253]], [[CONV254]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP255]], label [[IF_THEN257:%.*]], label [[IF_END258:%.*]]
+// SIMD-ONLY0:       if.then257:
+// SIMD-ONLY0-NEXT:    [[TMP108:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP108]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END258]]
+// SIMD-ONLY0:       if.end258:
+// SIMD-ONLY0-NEXT:    [[TMP109:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV259:%.*]] = sext i8 [[TMP109]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP110:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV260:%.*]] = sext i8 [[TMP110]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP261:%.*]] = icmp slt i32 [[CONV259]], [[CONV260]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP261]], label [[IF_THEN263:%.*]], label [[IF_END264:%.*]]
+// SIMD-ONLY0:       if.then263:
+// SIMD-ONLY0-NEXT:    [[TMP111:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP111]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END264]]
+// SIMD-ONLY0:       if.end264:
+// SIMD-ONLY0-NEXT:    [[TMP112:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV265:%.*]] = sext i8 [[TMP112]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP113:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV266:%.*]] = sext i8 [[TMP113]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP267:%.*]] = icmp eq i32 [[CONV265]], [[CONV266]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP267]], label [[COND_TRUE269:%.*]], label [[COND_FALSE271:%.*]]
+// SIMD-ONLY0:       cond.true269:
+// SIMD-ONLY0-NEXT:    [[TMP114:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV270:%.*]] = sext i8 [[TMP114]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END273:%.*]]
+// SIMD-ONLY0:       cond.false271:
+// SIMD-ONLY0-NEXT:    [[TMP115:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV272:%.*]] = sext i8 [[TMP115]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END273]]
+// SIMD-ONLY0:       cond.end273:
+// SIMD-ONLY0-NEXT:    [[COND274:%.*]] = phi i32 [ [[CONV270]], [[COND_TRUE269]] ], [ [[CONV272]], [[COND_FALSE271]] ]
+// SIMD-ONLY0-NEXT:    [[CONV275:%.*]] = trunc i32 [[COND274]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV275]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP116:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV276:%.*]] = sext i8 [[TMP116]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP117:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV277:%.*]] = sext i8 [[TMP117]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP278:%.*]] = icmp eq i32 [[CONV276]], [[CONV277]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP278]], label [[COND_TRUE280:%.*]], label [[COND_FALSE282:%.*]]
+// SIMD-ONLY0:       cond.true280:
+// SIMD-ONLY0-NEXT:    [[TMP118:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV281:%.*]] = sext i8 [[TMP118]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END284:%.*]]
+// SIMD-ONLY0:       cond.false282:
+// SIMD-ONLY0-NEXT:    [[TMP119:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV283:%.*]] = sext i8 [[TMP119]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END284]]
+// SIMD-ONLY0:       cond.end284:
+// SIMD-ONLY0-NEXT:    [[COND285:%.*]] = phi i32 [ [[CONV281]], [[COND_TRUE280]] ], [ [[CONV283]], [[COND_FALSE282]] ]
+// SIMD-ONLY0-NEXT:    [[CONV286:%.*]] = trunc i32 [[COND285]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV286]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP120:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV287:%.*]] = sext i8 [[TMP120]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP121:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV288:%.*]] = sext i8 [[TMP121]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP289:%.*]] = icmp eq i32 [[CONV287]], [[CONV288]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP289]], label [[IF_THEN291:%.*]], label [[IF_END292:%.*]]
+// SIMD-ONLY0:       if.then291:
+// SIMD-ONLY0-NEXT:    [[TMP122:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP122]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END292]]
+// SIMD-ONLY0:       if.end292:
+// SIMD-ONLY0-NEXT:    [[TMP123:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV293:%.*]] = sext i8 [[TMP123]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP124:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV294:%.*]] = sext i8 [[TMP124]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP295:%.*]] = icmp eq i32 [[CONV293]], [[CONV294]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP295]], label [[IF_THEN297:%.*]], label [[IF_END298:%.*]]
+// SIMD-ONLY0:       if.then297:
+// SIMD-ONLY0-NEXT:    [[TMP125:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP125]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END298]]
+// SIMD-ONLY0:       if.end298:
+// SIMD-ONLY0-NEXT:    [[TMP126:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV299:%.*]] = zext i8 [[TMP126]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP127:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV300:%.*]] = zext i8 [[TMP127]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP301:%.*]] = icmp sgt i32 [[CONV299]], [[CONV300]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP301]], label [[COND_TRUE303:%.*]], label [[COND_FALSE305:%.*]]
+// SIMD-ONLY0:       cond.true303:
+// SIMD-ONLY0-NEXT:    [[TMP128:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV304:%.*]] = zext i8 [[TMP128]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END307:%.*]]
+// SIMD-ONLY0:       cond.false305:
+// SIMD-ONLY0-NEXT:    [[TMP129:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV306:%.*]] = zext i8 [[TMP129]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END307]]
+// SIMD-ONLY0:       cond.end307:
+// SIMD-ONLY0-NEXT:    [[COND308:%.*]] = phi i32 [ [[CONV304]], [[COND_TRUE303]] ], [ [[CONV306]], [[COND_FALSE305]] ]
+// SIMD-ONLY0-NEXT:    [[CONV309:%.*]] = trunc i32 [[COND308]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV309]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP130:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV310:%.*]] = zext i8 [[TMP130]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP131:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV311:%.*]] = zext i8 [[TMP131]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP312:%.*]] = icmp slt i32 [[CONV310]], [[CONV311]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP312]], label [[COND_TRUE314:%.*]], label [[COND_FALSE316:%.*]]
+// SIMD-ONLY0:       cond.true314:
+// SIMD-ONLY0-NEXT:    [[TMP132:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV315:%.*]] = zext i8 [[TMP132]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END318:%.*]]
+// SIMD-ONLY0:       cond.false316:
+// SIMD-ONLY0-NEXT:    [[TMP133:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV317:%.*]] = zext i8 [[TMP133]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END318]]
+// SIMD-ONLY0:       cond.end318:
+// SIMD-ONLY0-NEXT:    [[COND319:%.*]] = phi i32 [ [[CONV315]], [[COND_TRUE314]] ], [ [[CONV317]], [[COND_FALSE316]] ]
+// SIMD-ONLY0-NEXT:    [[CONV320:%.*]] = trunc i32 [[COND319]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV320]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP134:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV321:%.*]] = zext i8 [[TMP134]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP135:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV322:%.*]] = zext i8 [[TMP135]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP323:%.*]] = icmp sgt i32 [[CONV321]], [[CONV322]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP323]], label [[COND_TRUE325:%.*]], label [[COND_FALSE327:%.*]]
+// SIMD-ONLY0:       cond.true325:
+// SIMD-ONLY0-NEXT:    [[TMP136:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV326:%.*]] = zext i8 [[TMP136]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END329:%.*]]
+// SIMD-ONLY0:       cond.false327:
+// SIMD-ONLY0-NEXT:    [[TMP137:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV328:%.*]] = zext i8 [[TMP137]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END329]]
+// SIMD-ONLY0:       cond.end329:
+// SIMD-ONLY0-NEXT:    [[COND330:%.*]] = phi i32 [ [[CONV326]], [[COND_TRUE325]] ], [ [[CONV328]], [[COND_FALSE327]] ]
+// SIMD-ONLY0-NEXT:    [[CONV331:%.*]] = trunc i32 [[COND330]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV331]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP138:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV332:%.*]] = zext i8 [[TMP138]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP139:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV333:%.*]] = zext i8 [[TMP139]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP334:%.*]] = icmp slt i32 [[CONV332]], [[CONV333]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP334]], label [[COND_TRUE336:%.*]], label [[COND_FALSE338:%.*]]
+// SIMD-ONLY0:       cond.true336:
+// SIMD-ONLY0-NEXT:    [[TMP140:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV337:%.*]] = zext i8 [[TMP140]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END340:%.*]]
+// SIMD-ONLY0:       cond.false338:
+// SIMD-ONLY0-NEXT:    [[TMP141:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV339:%.*]] = zext i8 [[TMP141]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END340]]
+// SIMD-ONLY0:       cond.end340:
+// SIMD-ONLY0-NEXT:    [[COND341:%.*]] = phi i32 [ [[CONV337]], [[COND_TRUE336]] ], [ [[CONV339]], [[COND_FALSE338]] ]
+// SIMD-ONLY0-NEXT:    [[CONV342:%.*]] = trunc i32 [[COND341]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV342]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP142:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV343:%.*]] = zext i8 [[TMP142]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP143:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV344:%.*]] = zext i8 [[TMP143]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP345:%.*]] = icmp sgt i32 [[CONV343]], [[CONV344]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP345]], label [[IF_THEN347:%.*]], label [[IF_END348:%.*]]
+// SIMD-ONLY0:       if.then347:
+// SIMD-ONLY0-NEXT:    [[TMP144:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP144]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END348]]
+// SIMD-ONLY0:       if.end348:
+// SIMD-ONLY0-NEXT:    [[TMP145:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV349:%.*]] = zext i8 [[TMP145]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP146:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV350:%.*]] = zext i8 [[TMP146]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP351:%.*]] = icmp slt i32 [[CONV349]], [[CONV350]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP351]], label [[IF_THEN353:%.*]], label [[IF_END354:%.*]]
+// SIMD-ONLY0:       if.then353:
+// SIMD-ONLY0-NEXT:    [[TMP147:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP147]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END354]]
+// SIMD-ONLY0:       if.end354:
+// SIMD-ONLY0-NEXT:    [[TMP148:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV355:%.*]] = zext i8 [[TMP148]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP149:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV356:%.*]] = zext i8 [[TMP149]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP357:%.*]] = icmp sgt i32 [[CONV355]], [[CONV356]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP357]], label [[IF_THEN359:%.*]], label [[IF_END360:%.*]]
+// SIMD-ONLY0:       if.then359:
+// SIMD-ONLY0-NEXT:    [[TMP150:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP150]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END360]]
+// SIMD-ONLY0:       if.end360:
+// SIMD-ONLY0-NEXT:    [[TMP151:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV361:%.*]] = zext i8 [[TMP151]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP152:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV362:%.*]] = zext i8 [[TMP152]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP363:%.*]] = icmp slt i32 [[CONV361]], [[CONV362]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP363]], label [[IF_THEN365:%.*]], label [[IF_END366:%.*]]
+// SIMD-ONLY0:       if.then365:
+// SIMD-ONLY0-NEXT:    [[TMP153:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP153]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END366]]
+// SIMD-ONLY0:       if.end366:
+// SIMD-ONLY0-NEXT:    [[TMP154:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV367:%.*]] = zext i8 [[TMP154]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP155:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV368:%.*]] = zext i8 [[TMP155]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP369:%.*]] = icmp eq i32 [[CONV367]], [[CONV368]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP369]], label [[COND_TRUE371:%.*]], label [[COND_FALSE373:%.*]]
+// SIMD-ONLY0:       cond.true371:
+// SIMD-ONLY0-NEXT:    [[TMP156:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV372:%.*]] = zext i8 [[TMP156]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END375:%.*]]
+// SIMD-ONLY0:       cond.false373:
+// SIMD-ONLY0-NEXT:    [[TMP157:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV374:%.*]] = zext i8 [[TMP157]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END375]]
+// SIMD-ONLY0:       cond.end375:
+// SIMD-ONLY0-NEXT:    [[COND376:%.*]] = phi i32 [ [[CONV372]], [[COND_TRUE371]] ], [ [[CONV374]], [[COND_FALSE373]] ]
+// SIMD-ONLY0-NEXT:    [[CONV377:%.*]] = trunc i32 [[COND376]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV377]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP158:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV378:%.*]] = zext i8 [[TMP158]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP159:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV379:%.*]] = zext i8 [[TMP159]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP380:%.*]] = icmp eq i32 [[CONV378]], [[CONV379]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP380]], label [[COND_TRUE382:%.*]], label [[COND_FALSE384:%.*]]
+// SIMD-ONLY0:       cond.true382:
+// SIMD-ONLY0-NEXT:    [[TMP160:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV383:%.*]] = zext i8 [[TMP160]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END386:%.*]]
+// SIMD-ONLY0:       cond.false384:
+// SIMD-ONLY0-NEXT:    [[TMP161:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV385:%.*]] = zext i8 [[TMP161]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END386]]
+// SIMD-ONLY0:       cond.end386:
+// SIMD-ONLY0-NEXT:    [[COND387:%.*]] = phi i32 [ [[CONV383]], [[COND_TRUE382]] ], [ [[CONV385]], [[COND_FALSE384]] ]
+// SIMD-ONLY0-NEXT:    [[CONV388:%.*]] = trunc i32 [[COND387]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV388]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP162:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV389:%.*]] = zext i8 [[TMP162]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP163:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV390:%.*]] = zext i8 [[TMP163]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP391:%.*]] = icmp eq i32 [[CONV389]], [[CONV390]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP391]], label [[IF_THEN393:%.*]], label [[IF_END394:%.*]]
+// SIMD-ONLY0:       if.then393:
+// SIMD-ONLY0-NEXT:    [[TMP164:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP164]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END394]]
+// SIMD-ONLY0:       if.end394:
+// SIMD-ONLY0-NEXT:    [[TMP165:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV395:%.*]] = zext i8 [[TMP165]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP166:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV396:%.*]] = zext i8 [[TMP166]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP397:%.*]] = icmp eq i32 [[CONV395]], [[CONV396]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP397]], label [[IF_THEN399:%.*]], label [[IF_END400:%.*]]
+// SIMD-ONLY0:       if.then399:
+// SIMD-ONLY0-NEXT:    [[TMP167:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP167]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END400]]
+// SIMD-ONLY0:       if.end400:
+// SIMD-ONLY0-NEXT:    [[TMP168:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV401:%.*]] = sext i8 [[TMP168]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP169:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV402:%.*]] = sext i8 [[TMP169]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP403:%.*]] = icmp sgt i32 [[CONV401]], [[CONV402]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP403]], label [[COND_TRUE405:%.*]], label [[COND_FALSE407:%.*]]
+// SIMD-ONLY0:       cond.true405:
+// SIMD-ONLY0-NEXT:    [[TMP170:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV406:%.*]] = sext i8 [[TMP170]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END409:%.*]]
+// SIMD-ONLY0:       cond.false407:
+// SIMD-ONLY0-NEXT:    [[TMP171:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV408:%.*]] = sext i8 [[TMP171]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END409]]
+// SIMD-ONLY0:       cond.end409:
+// SIMD-ONLY0-NEXT:    [[COND410:%.*]] = phi i32 [ [[CONV406]], [[COND_TRUE405]] ], [ [[CONV408]], [[COND_FALSE407]] ]
+// SIMD-ONLY0-NEXT:    [[CONV411:%.*]] = trunc i32 [[COND410]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV411]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP172:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV412:%.*]] = sext i8 [[TMP172]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP173:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV413:%.*]] = sext i8 [[TMP173]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP414:%.*]] = icmp slt i32 [[CONV412]], [[CONV413]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP414]], label [[COND_TRUE416:%.*]], label [[COND_FALSE418:%.*]]
+// SIMD-ONLY0:       cond.true416:
+// SIMD-ONLY0-NEXT:    [[TMP174:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV417:%.*]] = sext i8 [[TMP174]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END420:%.*]]
+// SIMD-ONLY0:       cond.false418:
+// SIMD-ONLY0-NEXT:    [[TMP175:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV419:%.*]] = sext i8 [[TMP175]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END420]]
+// SIMD-ONLY0:       cond.end420:
+// SIMD-ONLY0-NEXT:    [[COND421:%.*]] = phi i32 [ [[CONV417]], [[COND_TRUE416]] ], [ [[CONV419]], [[COND_FALSE418]] ]
+// SIMD-ONLY0-NEXT:    [[CONV422:%.*]] = trunc i32 [[COND421]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV422]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP176:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV423:%.*]] = sext i8 [[TMP176]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP177:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV424:%.*]] = sext i8 [[TMP177]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP425:%.*]] = icmp sgt i32 [[CONV423]], [[CONV424]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP425]], label [[COND_TRUE427:%.*]], label [[COND_FALSE429:%.*]]
+// SIMD-ONLY0:       cond.true427:
+// SIMD-ONLY0-NEXT:    [[TMP178:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV428:%.*]] = sext i8 [[TMP178]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END431:%.*]]
+// SIMD-ONLY0:       cond.false429:
+// SIMD-ONLY0-NEXT:    [[TMP179:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV430:%.*]] = sext i8 [[TMP179]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END431]]
+// SIMD-ONLY0:       cond.end431:
+// SIMD-ONLY0-NEXT:    [[COND432:%.*]] = phi i32 [ [[CONV428]], [[COND_TRUE427]] ], [ [[CONV430]], [[COND_FALSE429]] ]
+// SIMD-ONLY0-NEXT:    [[CONV433:%.*]] = trunc i32 [[COND432]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV433]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP180:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV434:%.*]] = sext i8 [[TMP180]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP181:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV435:%.*]] = sext i8 [[TMP181]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP436:%.*]] = icmp slt i32 [[CONV434]], [[CONV435]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP436]], label [[COND_TRUE438:%.*]], label [[COND_FALSE440:%.*]]
+// SIMD-ONLY0:       cond.true438:
+// SIMD-ONLY0-NEXT:    [[TMP182:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV439:%.*]] = sext i8 [[TMP182]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END442:%.*]]
+// SIMD-ONLY0:       cond.false440:
+// SIMD-ONLY0-NEXT:    [[TMP183:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV441:%.*]] = sext i8 [[TMP183]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END442]]
+// SIMD-ONLY0:       cond.end442:
+// SIMD-ONLY0-NEXT:    [[COND443:%.*]] = phi i32 [ [[CONV439]], [[COND_TRUE438]] ], [ [[CONV441]], [[COND_FALSE440]] ]
+// SIMD-ONLY0-NEXT:    [[CONV444:%.*]] = trunc i32 [[COND443]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV444]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP184:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV445:%.*]] = sext i8 [[TMP184]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP185:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV446:%.*]] = sext i8 [[TMP185]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP447:%.*]] = icmp sgt i32 [[CONV445]], [[CONV446]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP447]], label [[IF_THEN449:%.*]], label [[IF_END450:%.*]]
+// SIMD-ONLY0:       if.then449:
+// SIMD-ONLY0-NEXT:    [[TMP186:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP186]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END450]]
+// SIMD-ONLY0:       if.end450:
+// SIMD-ONLY0-NEXT:    [[TMP187:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV451:%.*]] = sext i8 [[TMP187]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP188:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV452:%.*]] = sext i8 [[TMP188]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP453:%.*]] = icmp slt i32 [[CONV451]], [[CONV452]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP453]], label [[IF_THEN455:%.*]], label [[IF_END456:%.*]]
+// SIMD-ONLY0:       if.then455:
+// SIMD-ONLY0-NEXT:    [[TMP189:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP189]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END456]]
+// SIMD-ONLY0:       if.end456:
+// SIMD-ONLY0-NEXT:    [[TMP190:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV457:%.*]] = sext i8 [[TMP190]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP191:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV458:%.*]] = sext i8 [[TMP191]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP459:%.*]] = icmp sgt i32 [[CONV457]], [[CONV458]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP459]], label [[IF_THEN461:%.*]], label [[IF_END462:%.*]]
+// SIMD-ONLY0:       if.then461:
+// SIMD-ONLY0-NEXT:    [[TMP192:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP192]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END462]]
+// SIMD-ONLY0:       if.end462:
+// SIMD-ONLY0-NEXT:    [[TMP193:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV463:%.*]] = sext i8 [[TMP193]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP194:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV464:%.*]] = sext i8 [[TMP194]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP465:%.*]] = icmp slt i32 [[CONV463]], [[CONV464]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP465]], label [[IF_THEN467:%.*]], label [[IF_END468:%.*]]
+// SIMD-ONLY0:       if.then467:
+// SIMD-ONLY0-NEXT:    [[TMP195:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP195]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END468]]
+// SIMD-ONLY0:       if.end468:
+// SIMD-ONLY0-NEXT:    [[TMP196:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV469:%.*]] = sext i8 [[TMP196]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP197:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV470:%.*]] = sext i8 [[TMP197]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP471:%.*]] = icmp eq i32 [[CONV469]], [[CONV470]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP471]], label [[COND_TRUE473:%.*]], label [[COND_FALSE475:%.*]]
+// SIMD-ONLY0:       cond.true473:
+// SIMD-ONLY0-NEXT:    [[TMP198:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV474:%.*]] = sext i8 [[TMP198]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END477:%.*]]
+// SIMD-ONLY0:       cond.false475:
+// SIMD-ONLY0-NEXT:    [[TMP199:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV476:%.*]] = sext i8 [[TMP199]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END477]]
+// SIMD-ONLY0:       cond.end477:
+// SIMD-ONLY0-NEXT:    [[COND478:%.*]] = phi i32 [ [[CONV474]], [[COND_TRUE473]] ], [ [[CONV476]], [[COND_FALSE475]] ]
+// SIMD-ONLY0-NEXT:    [[CONV479:%.*]] = trunc i32 [[COND478]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV479]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP200:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV480:%.*]] = sext i8 [[TMP200]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP201:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV481:%.*]] = sext i8 [[TMP201]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP482:%.*]] = icmp eq i32 [[CONV480]], [[CONV481]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP482]], label [[COND_TRUE484:%.*]], label [[COND_FALSE486:%.*]]
+// SIMD-ONLY0:       cond.true484:
+// SIMD-ONLY0-NEXT:    [[TMP202:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV485:%.*]] = sext i8 [[TMP202]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END488:%.*]]
+// SIMD-ONLY0:       cond.false486:
+// SIMD-ONLY0-NEXT:    [[TMP203:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV487:%.*]] = sext i8 [[TMP203]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END488]]
+// SIMD-ONLY0:       cond.end488:
+// SIMD-ONLY0-NEXT:    [[COND489:%.*]] = phi i32 [ [[CONV485]], [[COND_TRUE484]] ], [ [[CONV487]], [[COND_FALSE486]] ]
+// SIMD-ONLY0-NEXT:    [[CONV490:%.*]] = trunc i32 [[COND489]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV490]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP204:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV491:%.*]] = sext i8 [[TMP204]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP205:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV492:%.*]] = sext i8 [[TMP205]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP493:%.*]] = icmp eq i32 [[CONV491]], [[CONV492]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP493]], label [[IF_THEN495:%.*]], label [[IF_END496:%.*]]
+// SIMD-ONLY0:       if.then495:
+// SIMD-ONLY0-NEXT:    [[TMP206:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP206]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END496]]
+// SIMD-ONLY0:       if.end496:
+// SIMD-ONLY0-NEXT:    [[TMP207:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV497:%.*]] = sext i8 [[TMP207]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP208:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV498:%.*]] = sext i8 [[TMP208]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP499:%.*]] = icmp eq i32 [[CONV497]], [[CONV498]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP499]], label [[IF_THEN501:%.*]], label [[IF_END502:%.*]]
+// SIMD-ONLY0:       if.then501:
+// SIMD-ONLY0-NEXT:    [[TMP209:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP209]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END502]]
+// SIMD-ONLY0:       if.end502:
+// SIMD-ONLY0-NEXT:    [[TMP210:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV503:%.*]] = zext i8 [[TMP210]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP211:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV504:%.*]] = zext i8 [[TMP211]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP505:%.*]] = icmp sgt i32 [[CONV503]], [[CONV504]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP505]], label [[COND_TRUE507:%.*]], label [[COND_FALSE509:%.*]]
+// SIMD-ONLY0:       cond.true507:
+// SIMD-ONLY0-NEXT:    [[TMP212:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV508:%.*]] = zext i8 [[TMP212]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END511:%.*]]
+// SIMD-ONLY0:       cond.false509:
+// SIMD-ONLY0-NEXT:    [[TMP213:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV510:%.*]] = zext i8 [[TMP213]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END511]]
+// SIMD-ONLY0:       cond.end511:
+// SIMD-ONLY0-NEXT:    [[COND512:%.*]] = phi i32 [ [[CONV508]], [[COND_TRUE507]] ], [ [[CONV510]], [[COND_FALSE509]] ]
+// SIMD-ONLY0-NEXT:    [[CONV513:%.*]] = trunc i32 [[COND512]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV513]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP214:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV514:%.*]] = zext i8 [[TMP214]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP215:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV515:%.*]] = zext i8 [[TMP215]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP516:%.*]] = icmp slt i32 [[CONV514]], [[CONV515]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP516]], label [[COND_TRUE518:%.*]], label [[COND_FALSE520:%.*]]
+// SIMD-ONLY0:       cond.true518:
+// SIMD-ONLY0-NEXT:    [[TMP216:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV519:%.*]] = zext i8 [[TMP216]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END522:%.*]]
+// SIMD-ONLY0:       cond.false520:
+// SIMD-ONLY0-NEXT:    [[TMP217:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV521:%.*]] = zext i8 [[TMP217]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END522]]
+// SIMD-ONLY0:       cond.end522:
+// SIMD-ONLY0-NEXT:    [[COND523:%.*]] = phi i32 [ [[CONV519]], [[COND_TRUE518]] ], [ [[CONV521]], [[COND_FALSE520]] ]
+// SIMD-ONLY0-NEXT:    [[CONV524:%.*]] = trunc i32 [[COND523]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV524]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP218:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV525:%.*]] = zext i8 [[TMP218]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP219:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV526:%.*]] = zext i8 [[TMP219]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP527:%.*]] = icmp sgt i32 [[CONV525]], [[CONV526]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP527]], label [[COND_TRUE529:%.*]], label [[COND_FALSE531:%.*]]
+// SIMD-ONLY0:       cond.true529:
+// SIMD-ONLY0-NEXT:    [[TMP220:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV530:%.*]] = zext i8 [[TMP220]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END533:%.*]]
+// SIMD-ONLY0:       cond.false531:
+// SIMD-ONLY0-NEXT:    [[TMP221:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV532:%.*]] = zext i8 [[TMP221]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END533]]
+// SIMD-ONLY0:       cond.end533:
+// SIMD-ONLY0-NEXT:    [[COND534:%.*]] = phi i32 [ [[CONV530]], [[COND_TRUE529]] ], [ [[CONV532]], [[COND_FALSE531]] ]
+// SIMD-ONLY0-NEXT:    [[CONV535:%.*]] = trunc i32 [[COND534]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV535]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP222:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV536:%.*]] = zext i8 [[TMP222]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP223:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV537:%.*]] = zext i8 [[TMP223]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP538:%.*]] = icmp slt i32 [[CONV536]], [[CONV537]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP538]], label [[COND_TRUE540:%.*]], label [[COND_FALSE542:%.*]]
+// SIMD-ONLY0:       cond.true540:
+// SIMD-ONLY0-NEXT:    [[TMP224:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV541:%.*]] = zext i8 [[TMP224]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END544:%.*]]
+// SIMD-ONLY0:       cond.false542:
+// SIMD-ONLY0-NEXT:    [[TMP225:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV543:%.*]] = zext i8 [[TMP225]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END544]]
+// SIMD-ONLY0:       cond.end544:
+// SIMD-ONLY0-NEXT:    [[COND545:%.*]] = phi i32 [ [[CONV541]], [[COND_TRUE540]] ], [ [[CONV543]], [[COND_FALSE542]] ]
+// SIMD-ONLY0-NEXT:    [[CONV546:%.*]] = trunc i32 [[COND545]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV546]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP226:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV547:%.*]] = zext i8 [[TMP226]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP227:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV548:%.*]] = zext i8 [[TMP227]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP549:%.*]] = icmp sgt i32 [[CONV547]], [[CONV548]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP549]], label [[IF_THEN551:%.*]], label [[IF_END552:%.*]]
+// SIMD-ONLY0:       if.then551:
+// SIMD-ONLY0-NEXT:    [[TMP228:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP228]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END552]]
+// SIMD-ONLY0:       if.end552:
+// SIMD-ONLY0-NEXT:    [[TMP229:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV553:%.*]] = zext i8 [[TMP229]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP230:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV554:%.*]] = zext i8 [[TMP230]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP555:%.*]] = icmp slt i32 [[CONV553]], [[CONV554]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP555]], label [[IF_THEN557:%.*]], label [[IF_END558:%.*]]
+// SIMD-ONLY0:       if.then557:
+// SIMD-ONLY0-NEXT:    [[TMP231:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP231]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END558]]
+// SIMD-ONLY0:       if.end558:
+// SIMD-ONLY0-NEXT:    [[TMP232:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV559:%.*]] = zext i8 [[TMP232]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP233:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV560:%.*]] = zext i8 [[TMP233]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP561:%.*]] = icmp sgt i32 [[CONV559]], [[CONV560]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP561]], label [[IF_THEN563:%.*]], label [[IF_END564:%.*]]
+// SIMD-ONLY0:       if.then563:
+// SIMD-ONLY0-NEXT:    [[TMP234:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP234]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END564]]
+// SIMD-ONLY0:       if.end564:
+// SIMD-ONLY0-NEXT:    [[TMP235:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV565:%.*]] = zext i8 [[TMP235]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP236:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV566:%.*]] = zext i8 [[TMP236]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP567:%.*]] = icmp slt i32 [[CONV565]], [[CONV566]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP567]], label [[IF_THEN569:%.*]], label [[IF_END570:%.*]]
+// SIMD-ONLY0:       if.then569:
+// SIMD-ONLY0-NEXT:    [[TMP237:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP237]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END570]]
+// SIMD-ONLY0:       if.end570:
+// SIMD-ONLY0-NEXT:    [[TMP238:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV571:%.*]] = zext i8 [[TMP238]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP239:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV572:%.*]] = zext i8 [[TMP239]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP573:%.*]] = icmp eq i32 [[CONV571]], [[CONV572]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP573]], label [[COND_TRUE575:%.*]], label [[COND_FALSE577:%.*]]
+// SIMD-ONLY0:       cond.true575:
+// SIMD-ONLY0-NEXT:    [[TMP240:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV576:%.*]] = zext i8 [[TMP240]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END579:%.*]]
+// SIMD-ONLY0:       cond.false577:
+// SIMD-ONLY0-NEXT:    [[TMP241:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV578:%.*]] = zext i8 [[TMP241]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END579]]
+// SIMD-ONLY0:       cond.end579:
+// SIMD-ONLY0-NEXT:    [[COND580:%.*]] = phi i32 [ [[CONV576]], [[COND_TRUE575]] ], [ [[CONV578]], [[COND_FALSE577]] ]
+// SIMD-ONLY0-NEXT:    [[CONV581:%.*]] = trunc i32 [[COND580]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV581]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP242:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV582:%.*]] = zext i8 [[TMP242]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP243:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV583:%.*]] = zext i8 [[TMP243]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP584:%.*]] = icmp eq i32 [[CONV582]], [[CONV583]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP584]], label [[COND_TRUE586:%.*]], label [[COND_FALSE588:%.*]]
+// SIMD-ONLY0:       cond.true586:
+// SIMD-ONLY0-NEXT:    [[TMP244:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV587:%.*]] = zext i8 [[TMP244]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END590:%.*]]
+// SIMD-ONLY0:       cond.false588:
+// SIMD-ONLY0-NEXT:    [[TMP245:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV589:%.*]] = zext i8 [[TMP245]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END590]]
+// SIMD-ONLY0:       cond.end590:
+// SIMD-ONLY0-NEXT:    [[COND591:%.*]] = phi i32 [ [[CONV587]], [[COND_TRUE586]] ], [ [[CONV589]], [[COND_FALSE588]] ]
+// SIMD-ONLY0-NEXT:    [[CONV592:%.*]] = trunc i32 [[COND591]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV592]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP246:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV593:%.*]] = zext i8 [[TMP246]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP247:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV594:%.*]] = zext i8 [[TMP247]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP595:%.*]] = icmp eq i32 [[CONV593]], [[CONV594]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP595]], label [[IF_THEN597:%.*]], label [[IF_END598:%.*]]
+// SIMD-ONLY0:       if.then597:
+// SIMD-ONLY0-NEXT:    [[TMP248:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP248]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END598]]
+// SIMD-ONLY0:       if.end598:
+// SIMD-ONLY0-NEXT:    [[TMP249:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV599:%.*]] = zext i8 [[TMP249]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP250:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV600:%.*]] = zext i8 [[TMP250]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP601:%.*]] = icmp eq i32 [[CONV599]], [[CONV600]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP601]], label [[IF_THEN603:%.*]], label [[IF_END604:%.*]]
+// SIMD-ONLY0:       if.then603:
+// SIMD-ONLY0-NEXT:    [[TMP251:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP251]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END604]]
+// SIMD-ONLY0:       if.end604:
+// SIMD-ONLY0-NEXT:    [[TMP252:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV605:%.*]] = sext i8 [[TMP252]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP253:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV606:%.*]] = sext i8 [[TMP253]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP607:%.*]] = icmp sgt i32 [[CONV605]], [[CONV606]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP607]], label [[COND_TRUE609:%.*]], label [[COND_FALSE611:%.*]]
+// SIMD-ONLY0:       cond.true609:
+// SIMD-ONLY0-NEXT:    [[TMP254:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV610:%.*]] = sext i8 [[TMP254]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END613:%.*]]
+// SIMD-ONLY0:       cond.false611:
+// SIMD-ONLY0-NEXT:    [[TMP255:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV612:%.*]] = sext i8 [[TMP255]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END613]]
+// SIMD-ONLY0:       cond.end613:
+// SIMD-ONLY0-NEXT:    [[COND614:%.*]] = phi i32 [ [[CONV610]], [[COND_TRUE609]] ], [ [[CONV612]], [[COND_FALSE611]] ]
+// SIMD-ONLY0-NEXT:    [[CONV615:%.*]] = trunc i32 [[COND614]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV615]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP256:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV616:%.*]] = sext i8 [[TMP256]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP257:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV617:%.*]] = sext i8 [[TMP257]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP618:%.*]] = icmp slt i32 [[CONV616]], [[CONV617]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP618]], label [[COND_TRUE620:%.*]], label [[COND_FALSE622:%.*]]
+// SIMD-ONLY0:       cond.true620:
+// SIMD-ONLY0-NEXT:    [[TMP258:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV621:%.*]] = sext i8 [[TMP258]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END624:%.*]]
+// SIMD-ONLY0:       cond.false622:
+// SIMD-ONLY0-NEXT:    [[TMP259:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV623:%.*]] = sext i8 [[TMP259]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END624]]
+// SIMD-ONLY0:       cond.end624:
+// SIMD-ONLY0-NEXT:    [[COND625:%.*]] = phi i32 [ [[CONV621]], [[COND_TRUE620]] ], [ [[CONV623]], [[COND_FALSE622]] ]
+// SIMD-ONLY0-NEXT:    [[CONV626:%.*]] = trunc i32 [[COND625]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV626]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP260:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV627:%.*]] = sext i8 [[TMP260]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP261:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV628:%.*]] = sext i8 [[TMP261]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP629:%.*]] = icmp sgt i32 [[CONV627]], [[CONV628]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP629]], label [[COND_TRUE631:%.*]], label [[COND_FALSE633:%.*]]
+// SIMD-ONLY0:       cond.true631:
+// SIMD-ONLY0-NEXT:    [[TMP262:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV632:%.*]] = sext i8 [[TMP262]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END635:%.*]]
+// SIMD-ONLY0:       cond.false633:
+// SIMD-ONLY0-NEXT:    [[TMP263:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV634:%.*]] = sext i8 [[TMP263]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END635]]
+// SIMD-ONLY0:       cond.end635:
+// SIMD-ONLY0-NEXT:    [[COND636:%.*]] = phi i32 [ [[CONV632]], [[COND_TRUE631]] ], [ [[CONV634]], [[COND_FALSE633]] ]
+// SIMD-ONLY0-NEXT:    [[CONV637:%.*]] = trunc i32 [[COND636]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV637]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP264:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV638:%.*]] = sext i8 [[TMP264]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP265:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV639:%.*]] = sext i8 [[TMP265]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP640:%.*]] = icmp slt i32 [[CONV638]], [[CONV639]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP640]], label [[COND_TRUE642:%.*]], label [[COND_FALSE644:%.*]]
+// SIMD-ONLY0:       cond.true642:
+// SIMD-ONLY0-NEXT:    [[TMP266:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV643:%.*]] = sext i8 [[TMP266]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END646:%.*]]
+// SIMD-ONLY0:       cond.false644:
+// SIMD-ONLY0-NEXT:    [[TMP267:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV645:%.*]] = sext i8 [[TMP267]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END646]]
+// SIMD-ONLY0:       cond.end646:
+// SIMD-ONLY0-NEXT:    [[COND647:%.*]] = phi i32 [ [[CONV643]], [[COND_TRUE642]] ], [ [[CONV645]], [[COND_FALSE644]] ]
+// SIMD-ONLY0-NEXT:    [[CONV648:%.*]] = trunc i32 [[COND647]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV648]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP268:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV649:%.*]] = sext i8 [[TMP268]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP269:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV650:%.*]] = sext i8 [[TMP269]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP651:%.*]] = icmp sgt i32 [[CONV649]], [[CONV650]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP651]], label [[IF_THEN653:%.*]], label [[IF_END654:%.*]]
+// SIMD-ONLY0:       if.then653:
+// SIMD-ONLY0-NEXT:    [[TMP270:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP270]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END654]]
+// SIMD-ONLY0:       if.end654:
+// SIMD-ONLY0-NEXT:    [[TMP271:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV655:%.*]] = sext i8 [[TMP271]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP272:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV656:%.*]] = sext i8 [[TMP272]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP657:%.*]] = icmp slt i32 [[CONV655]], [[CONV656]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP657]], label [[IF_THEN659:%.*]], label [[IF_END660:%.*]]
+// SIMD-ONLY0:       if.then659:
+// SIMD-ONLY0-NEXT:    [[TMP273:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP273]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END660]]
+// SIMD-ONLY0:       if.end660:
+// SIMD-ONLY0-NEXT:    [[TMP274:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV661:%.*]] = sext i8 [[TMP274]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP275:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV662:%.*]] = sext i8 [[TMP275]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP663:%.*]] = icmp sgt i32 [[CONV661]], [[CONV662]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP663]], label [[IF_THEN665:%.*]], label [[IF_END666:%.*]]
+// SIMD-ONLY0:       if.then665:
+// SIMD-ONLY0-NEXT:    [[TMP276:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP276]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END666]]
+// SIMD-ONLY0:       if.end666:
+// SIMD-ONLY0-NEXT:    [[TMP277:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV667:%.*]] = sext i8 [[TMP277]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP278:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV668:%.*]] = sext i8 [[TMP278]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP669:%.*]] = icmp slt i32 [[CONV667]], [[CONV668]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP669]], label [[IF_THEN671:%.*]], label [[IF_END672:%.*]]
+// SIMD-ONLY0:       if.then671:
+// SIMD-ONLY0-NEXT:    [[TMP279:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP279]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END672]]
+// SIMD-ONLY0:       if.end672:
+// SIMD-ONLY0-NEXT:    [[TMP280:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV673:%.*]] = sext i8 [[TMP280]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP281:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV674:%.*]] = sext i8 [[TMP281]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP675:%.*]] = icmp eq i32 [[CONV673]], [[CONV674]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP675]], label [[COND_TRUE677:%.*]], label [[COND_FALSE679:%.*]]
+// SIMD-ONLY0:       cond.true677:
+// SIMD-ONLY0-NEXT:    [[TMP282:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV678:%.*]] = sext i8 [[TMP282]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END681:%.*]]
+// SIMD-ONLY0:       cond.false679:
+// SIMD-ONLY0-NEXT:    [[TMP283:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV680:%.*]] = sext i8 [[TMP283]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END681]]
+// SIMD-ONLY0:       cond.end681:
+// SIMD-ONLY0-NEXT:    [[COND682:%.*]] = phi i32 [ [[CONV678]], [[COND_TRUE677]] ], [ [[CONV680]], [[COND_FALSE679]] ]
+// SIMD-ONLY0-NEXT:    [[CONV683:%.*]] = trunc i32 [[COND682]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV683]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP284:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV684:%.*]] = sext i8 [[TMP284]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP285:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV685:%.*]] = sext i8 [[TMP285]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP686:%.*]] = icmp eq i32 [[CONV684]], [[CONV685]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP686]], label [[COND_TRUE688:%.*]], label [[COND_FALSE690:%.*]]
+// SIMD-ONLY0:       cond.true688:
+// SIMD-ONLY0-NEXT:    [[TMP286:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV689:%.*]] = sext i8 [[TMP286]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END692:%.*]]
+// SIMD-ONLY0:       cond.false690:
+// SIMD-ONLY0-NEXT:    [[TMP287:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV691:%.*]] = sext i8 [[TMP287]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END692]]
+// SIMD-ONLY0:       cond.end692:
+// SIMD-ONLY0-NEXT:    [[COND693:%.*]] = phi i32 [ [[CONV689]], [[COND_TRUE688]] ], [ [[CONV691]], [[COND_FALSE690]] ]
+// SIMD-ONLY0-NEXT:    [[CONV694:%.*]] = trunc i32 [[COND693]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV694]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP288:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV695:%.*]] = sext i8 [[TMP288]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP289:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV696:%.*]] = sext i8 [[TMP289]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP697:%.*]] = icmp eq i32 [[CONV695]], [[CONV696]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP697]], label [[IF_THEN699:%.*]], label [[IF_END700:%.*]]
+// SIMD-ONLY0:       if.then699:
+// SIMD-ONLY0-NEXT:    [[TMP290:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP290]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END700]]
+// SIMD-ONLY0:       if.end700:
+// SIMD-ONLY0-NEXT:    [[TMP291:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV701:%.*]] = sext i8 [[TMP291]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP292:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV702:%.*]] = sext i8 [[TMP292]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP703:%.*]] = icmp eq i32 [[CONV701]], [[CONV702]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP703]], label [[IF_THEN705:%.*]], label [[IF_END706:%.*]]
+// SIMD-ONLY0:       if.then705:
+// SIMD-ONLY0-NEXT:    [[TMP293:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP293]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END706]]
+// SIMD-ONLY0:       if.end706:
+// SIMD-ONLY0-NEXT:    [[TMP294:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV707:%.*]] = zext i8 [[TMP294]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP295:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV708:%.*]] = zext i8 [[TMP295]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP709:%.*]] = icmp sgt i32 [[CONV707]], [[CONV708]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP709]], label [[COND_TRUE711:%.*]], label [[COND_FALSE713:%.*]]
+// SIMD-ONLY0:       cond.true711:
+// SIMD-ONLY0-NEXT:    [[TMP296:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV712:%.*]] = zext i8 [[TMP296]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END715:%.*]]
+// SIMD-ONLY0:       cond.false713:
+// SIMD-ONLY0-NEXT:    [[TMP297:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV714:%.*]] = zext i8 [[TMP297]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END715]]
+// SIMD-ONLY0:       cond.end715:
+// SIMD-ONLY0-NEXT:    [[COND716:%.*]] = phi i32 [ [[CONV712]], [[COND_TRUE711]] ], [ [[CONV714]], [[COND_FALSE713]] ]
+// SIMD-ONLY0-NEXT:    [[CONV717:%.*]] = trunc i32 [[COND716]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV717]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP298:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV718:%.*]] = zext i8 [[TMP298]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP299:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV719:%.*]] = zext i8 [[TMP299]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP720:%.*]] = icmp slt i32 [[CONV718]], [[CONV719]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP720]], label [[COND_TRUE722:%.*]], label [[COND_FALSE724:%.*]]
+// SIMD-ONLY0:       cond.true722:
+// SIMD-ONLY0-NEXT:    [[TMP300:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV723:%.*]] = zext i8 [[TMP300]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END726:%.*]]
+// SIMD-ONLY0:       cond.false724:
+// SIMD-ONLY0-NEXT:    [[TMP301:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV725:%.*]] = zext i8 [[TMP301]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END726]]
+// SIMD-ONLY0:       cond.end726:
+// SIMD-ONLY0-NEXT:    [[COND727:%.*]] = phi i32 [ [[CONV723]], [[COND_TRUE722]] ], [ [[CONV725]], [[COND_FALSE724]] ]
+// SIMD-ONLY0-NEXT:    [[CONV728:%.*]] = trunc i32 [[COND727]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV728]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP302:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV729:%.*]] = zext i8 [[TMP302]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP303:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV730:%.*]] = zext i8 [[TMP303]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP731:%.*]] = icmp sgt i32 [[CONV729]], [[CONV730]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP731]], label [[COND_TRUE733:%.*]], label [[COND_FALSE735:%.*]]
+// SIMD-ONLY0:       cond.true733:
+// SIMD-ONLY0-NEXT:    [[TMP304:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV734:%.*]] = zext i8 [[TMP304]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END737:%.*]]
+// SIMD-ONLY0:       cond.false735:
+// SIMD-ONLY0-NEXT:    [[TMP305:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV736:%.*]] = zext i8 [[TMP305]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END737]]
+// SIMD-ONLY0:       cond.end737:
+// SIMD-ONLY0-NEXT:    [[COND738:%.*]] = phi i32 [ [[CONV734]], [[COND_TRUE733]] ], [ [[CONV736]], [[COND_FALSE735]] ]
+// SIMD-ONLY0-NEXT:    [[CONV739:%.*]] = trunc i32 [[COND738]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV739]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP306:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV740:%.*]] = zext i8 [[TMP306]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP307:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV741:%.*]] = zext i8 [[TMP307]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP742:%.*]] = icmp slt i32 [[CONV740]], [[CONV741]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP742]], label [[COND_TRUE744:%.*]], label [[COND_FALSE746:%.*]]
+// SIMD-ONLY0:       cond.true744:
+// SIMD-ONLY0-NEXT:    [[TMP308:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV745:%.*]] = zext i8 [[TMP308]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END748:%.*]]
+// SIMD-ONLY0:       cond.false746:
+// SIMD-ONLY0-NEXT:    [[TMP309:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV747:%.*]] = zext i8 [[TMP309]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END748]]
+// SIMD-ONLY0:       cond.end748:
+// SIMD-ONLY0-NEXT:    [[COND749:%.*]] = phi i32 [ [[CONV745]], [[COND_TRUE744]] ], [ [[CONV747]], [[COND_FALSE746]] ]
+// SIMD-ONLY0-NEXT:    [[CONV750:%.*]] = trunc i32 [[COND749]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV750]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP310:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV751:%.*]] = zext i8 [[TMP310]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP311:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV752:%.*]] = zext i8 [[TMP311]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP753:%.*]] = icmp sgt i32 [[CONV751]], [[CONV752]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP753]], label [[IF_THEN755:%.*]], label [[IF_END756:%.*]]
+// SIMD-ONLY0:       if.then755:
+// SIMD-ONLY0-NEXT:    [[TMP312:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP312]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END756]]
+// SIMD-ONLY0:       if.end756:
+// SIMD-ONLY0-NEXT:    [[TMP313:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV757:%.*]] = zext i8 [[TMP313]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP314:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV758:%.*]] = zext i8 [[TMP314]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP759:%.*]] = icmp slt i32 [[CONV757]], [[CONV758]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP759]], label [[IF_THEN761:%.*]], label [[IF_END762:%.*]]
+// SIMD-ONLY0:       if.then761:
+// SIMD-ONLY0-NEXT:    [[TMP315:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP315]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END762]]
+// SIMD-ONLY0:       if.end762:
+// SIMD-ONLY0-NEXT:    [[TMP316:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV763:%.*]] = zext i8 [[TMP316]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP317:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV764:%.*]] = zext i8 [[TMP317]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP765:%.*]] = icmp sgt i32 [[CONV763]], [[CONV764]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP765]], label [[IF_THEN767:%.*]], label [[IF_END768:%.*]]
+// SIMD-ONLY0:       if.then767:
+// SIMD-ONLY0-NEXT:    [[TMP318:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP318]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END768]]
+// SIMD-ONLY0:       if.end768:
+// SIMD-ONLY0-NEXT:    [[TMP319:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV769:%.*]] = zext i8 [[TMP319]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP320:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV770:%.*]] = zext i8 [[TMP320]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP771:%.*]] = icmp slt i32 [[CONV769]], [[CONV770]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP771]], label [[IF_THEN773:%.*]], label [[IF_END774:%.*]]
+// SIMD-ONLY0:       if.then773:
+// SIMD-ONLY0-NEXT:    [[TMP321:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP321]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END774]]
+// SIMD-ONLY0:       if.end774:
+// SIMD-ONLY0-NEXT:    [[TMP322:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV775:%.*]] = zext i8 [[TMP322]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP323:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV776:%.*]] = zext i8 [[TMP323]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP777:%.*]] = icmp eq i32 [[CONV775]], [[CONV776]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP777]], label [[COND_TRUE779:%.*]], label [[COND_FALSE781:%.*]]
+// SIMD-ONLY0:       cond.true779:
+// SIMD-ONLY0-NEXT:    [[TMP324:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV780:%.*]] = zext i8 [[TMP324]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END783:%.*]]
+// SIMD-ONLY0:       cond.false781:
+// SIMD-ONLY0-NEXT:    [[TMP325:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV782:%.*]] = zext i8 [[TMP325]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END783]]
+// SIMD-ONLY0:       cond.end783:
+// SIMD-ONLY0-NEXT:    [[COND784:%.*]] = phi i32 [ [[CONV780]], [[COND_TRUE779]] ], [ [[CONV782]], [[COND_FALSE781]] ]
+// SIMD-ONLY0-NEXT:    [[CONV785:%.*]] = trunc i32 [[COND784]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV785]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP326:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV786:%.*]] = zext i8 [[TMP326]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP327:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV787:%.*]] = zext i8 [[TMP327]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP788:%.*]] = icmp eq i32 [[CONV786]], [[CONV787]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP788]], label [[COND_TRUE790:%.*]], label [[COND_FALSE792:%.*]]
+// SIMD-ONLY0:       cond.true790:
+// SIMD-ONLY0-NEXT:    [[TMP328:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV791:%.*]] = zext i8 [[TMP328]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END794:%.*]]
+// SIMD-ONLY0:       cond.false792:
+// SIMD-ONLY0-NEXT:    [[TMP329:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV793:%.*]] = zext i8 [[TMP329]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END794]]
+// SIMD-ONLY0:       cond.end794:
+// SIMD-ONLY0-NEXT:    [[COND795:%.*]] = phi i32 [ [[CONV791]], [[COND_TRUE790]] ], [ [[CONV793]], [[COND_FALSE792]] ]
+// SIMD-ONLY0-NEXT:    [[CONV796:%.*]] = trunc i32 [[COND795]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV796]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP330:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV797:%.*]] = zext i8 [[TMP330]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP331:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV798:%.*]] = zext i8 [[TMP331]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP799:%.*]] = icmp eq i32 [[CONV797]], [[CONV798]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP799]], label [[IF_THEN801:%.*]], label [[IF_END802:%.*]]
+// SIMD-ONLY0:       if.then801:
+// SIMD-ONLY0-NEXT:    [[TMP332:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP332]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END802]]
+// SIMD-ONLY0:       if.end802:
+// SIMD-ONLY0-NEXT:    [[TMP333:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV803:%.*]] = zext i8 [[TMP333]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP334:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV804:%.*]] = zext i8 [[TMP334]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP805:%.*]] = icmp eq i32 [[CONV803]], [[CONV804]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP805]], label [[IF_THEN807:%.*]], label [[IF_END808:%.*]]
+// SIMD-ONLY0:       if.then807:
+// SIMD-ONLY0-NEXT:    [[TMP335:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP335]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END808]]
+// SIMD-ONLY0:       if.end808:
+// SIMD-ONLY0-NEXT:    [[TMP336:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV809:%.*]] = sext i8 [[TMP336]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP337:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV810:%.*]] = sext i8 [[TMP337]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP811:%.*]] = icmp sgt i32 [[CONV809]], [[CONV810]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP811]], label [[COND_TRUE813:%.*]], label [[COND_FALSE815:%.*]]
+// SIMD-ONLY0:       cond.true813:
+// SIMD-ONLY0-NEXT:    [[TMP338:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV814:%.*]] = sext i8 [[TMP338]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END817:%.*]]
+// SIMD-ONLY0:       cond.false815:
+// SIMD-ONLY0-NEXT:    [[TMP339:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV816:%.*]] = sext i8 [[TMP339]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END817]]
+// SIMD-ONLY0:       cond.end817:
+// SIMD-ONLY0-NEXT:    [[COND818:%.*]] = phi i32 [ [[CONV814]], [[COND_TRUE813]] ], [ [[CONV816]], [[COND_FALSE815]] ]
+// SIMD-ONLY0-NEXT:    [[CONV819:%.*]] = trunc i32 [[COND818]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV819]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP340:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV820:%.*]] = sext i8 [[TMP340]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP341:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV821:%.*]] = sext i8 [[TMP341]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP822:%.*]] = icmp slt i32 [[CONV820]], [[CONV821]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP822]], label [[COND_TRUE824:%.*]], label [[COND_FALSE826:%.*]]
+// SIMD-ONLY0:       cond.true824:
+// SIMD-ONLY0-NEXT:    [[TMP342:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV825:%.*]] = sext i8 [[TMP342]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END828:%.*]]
+// SIMD-ONLY0:       cond.false826:
+// SIMD-ONLY0-NEXT:    [[TMP343:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV827:%.*]] = sext i8 [[TMP343]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END828]]
+// SIMD-ONLY0:       cond.end828:
+// SIMD-ONLY0-NEXT:    [[COND829:%.*]] = phi i32 [ [[CONV825]], [[COND_TRUE824]] ], [ [[CONV827]], [[COND_FALSE826]] ]
+// SIMD-ONLY0-NEXT:    [[CONV830:%.*]] = trunc i32 [[COND829]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV830]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP344:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV831:%.*]] = sext i8 [[TMP344]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP345:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV832:%.*]] = sext i8 [[TMP345]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP833:%.*]] = icmp sgt i32 [[CONV831]], [[CONV832]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP833]], label [[COND_TRUE835:%.*]], label [[COND_FALSE837:%.*]]
+// SIMD-ONLY0:       cond.true835:
+// SIMD-ONLY0-NEXT:    [[TMP346:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV836:%.*]] = sext i8 [[TMP346]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END839:%.*]]
+// SIMD-ONLY0:       cond.false837:
+// SIMD-ONLY0-NEXT:    [[TMP347:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV838:%.*]] = sext i8 [[TMP347]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END839]]
+// SIMD-ONLY0:       cond.end839:
+// SIMD-ONLY0-NEXT:    [[COND840:%.*]] = phi i32 [ [[CONV836]], [[COND_TRUE835]] ], [ [[CONV838]], [[COND_FALSE837]] ]
+// SIMD-ONLY0-NEXT:    [[CONV841:%.*]] = trunc i32 [[COND840]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV841]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP348:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV842:%.*]] = sext i8 [[TMP348]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP349:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV843:%.*]] = sext i8 [[TMP349]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP844:%.*]] = icmp slt i32 [[CONV842]], [[CONV843]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP844]], label [[COND_TRUE846:%.*]], label [[COND_FALSE848:%.*]]
+// SIMD-ONLY0:       cond.true846:
+// SIMD-ONLY0-NEXT:    [[TMP350:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV847:%.*]] = sext i8 [[TMP350]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END850:%.*]]
+// SIMD-ONLY0:       cond.false848:
+// SIMD-ONLY0-NEXT:    [[TMP351:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV849:%.*]] = sext i8 [[TMP351]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END850]]
+// SIMD-ONLY0:       cond.end850:
+// SIMD-ONLY0-NEXT:    [[COND851:%.*]] = phi i32 [ [[CONV847]], [[COND_TRUE846]] ], [ [[CONV849]], [[COND_FALSE848]] ]
+// SIMD-ONLY0-NEXT:    [[CONV852:%.*]] = trunc i32 [[COND851]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV852]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP352:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV853:%.*]] = sext i8 [[TMP352]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP353:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV854:%.*]] = sext i8 [[TMP353]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP855:%.*]] = icmp sgt i32 [[CONV853]], [[CONV854]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP855]], label [[IF_THEN857:%.*]], label [[IF_END858:%.*]]
+// SIMD-ONLY0:       if.then857:
+// SIMD-ONLY0-NEXT:    [[TMP354:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP354]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END858]]
+// SIMD-ONLY0:       if.end858:
+// SIMD-ONLY0-NEXT:    [[TMP355:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV859:%.*]] = sext i8 [[TMP355]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP356:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV860:%.*]] = sext i8 [[TMP356]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP861:%.*]] = icmp slt i32 [[CONV859]], [[CONV860]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP861]], label [[IF_THEN863:%.*]], label [[IF_END864:%.*]]
+// SIMD-ONLY0:       if.then863:
+// SIMD-ONLY0-NEXT:    [[TMP357:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP357]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END864]]
+// SIMD-ONLY0:       if.end864:
+// SIMD-ONLY0-NEXT:    [[TMP358:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV865:%.*]] = sext i8 [[TMP358]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP359:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV866:%.*]] = sext i8 [[TMP359]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP867:%.*]] = icmp sgt i32 [[CONV865]], [[CONV866]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP867]], label [[IF_THEN869:%.*]], label [[IF_END870:%.*]]
+// SIMD-ONLY0:       if.then869:
+// SIMD-ONLY0-NEXT:    [[TMP360:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP360]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END870]]
+// SIMD-ONLY0:       if.end870:
+// SIMD-ONLY0-NEXT:    [[TMP361:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV871:%.*]] = sext i8 [[TMP361]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP362:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV872:%.*]] = sext i8 [[TMP362]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP873:%.*]] = icmp slt i32 [[CONV871]], [[CONV872]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP873]], label [[IF_THEN875:%.*]], label [[IF_END876:%.*]]
+// SIMD-ONLY0:       if.then875:
+// SIMD-ONLY0-NEXT:    [[TMP363:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP363]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END876]]
+// SIMD-ONLY0:       if.end876:
+// SIMD-ONLY0-NEXT:    [[TMP364:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV877:%.*]] = sext i8 [[TMP364]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP365:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV878:%.*]] = sext i8 [[TMP365]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP879:%.*]] = icmp eq i32 [[CONV877]], [[CONV878]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP879]], label [[COND_TRUE881:%.*]], label [[COND_FALSE883:%.*]]
+// SIMD-ONLY0:       cond.true881:
+// SIMD-ONLY0-NEXT:    [[TMP366:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV882:%.*]] = sext i8 [[TMP366]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END885:%.*]]
+// SIMD-ONLY0:       cond.false883:
+// SIMD-ONLY0-NEXT:    [[TMP367:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV884:%.*]] = sext i8 [[TMP367]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END885]]
+// SIMD-ONLY0:       cond.end885:
+// SIMD-ONLY0-NEXT:    [[COND886:%.*]] = phi i32 [ [[CONV882]], [[COND_TRUE881]] ], [ [[CONV884]], [[COND_FALSE883]] ]
+// SIMD-ONLY0-NEXT:    [[CONV887:%.*]] = trunc i32 [[COND886]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV887]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP368:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV888:%.*]] = sext i8 [[TMP368]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP369:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV889:%.*]] = sext i8 [[TMP369]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP890:%.*]] = icmp eq i32 [[CONV888]], [[CONV889]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP890]], label [[COND_TRUE892:%.*]], label [[COND_FALSE894:%.*]]
+// SIMD-ONLY0:       cond.true892:
+// SIMD-ONLY0-NEXT:    [[TMP370:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV893:%.*]] = sext i8 [[TMP370]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END896:%.*]]
+// SIMD-ONLY0:       cond.false894:
+// SIMD-ONLY0-NEXT:    [[TMP371:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV895:%.*]] = sext i8 [[TMP371]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END896]]
+// SIMD-ONLY0:       cond.end896:
+// SIMD-ONLY0-NEXT:    [[COND897:%.*]] = phi i32 [ [[CONV893]], [[COND_TRUE892]] ], [ [[CONV895]], [[COND_FALSE894]] ]
+// SIMD-ONLY0-NEXT:    [[CONV898:%.*]] = trunc i32 [[COND897]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV898]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP372:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV899:%.*]] = sext i8 [[TMP372]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP373:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV900:%.*]] = sext i8 [[TMP373]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP901:%.*]] = icmp eq i32 [[CONV899]], [[CONV900]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP901]], label [[IF_THEN903:%.*]], label [[IF_END904:%.*]]
+// SIMD-ONLY0:       if.then903:
+// SIMD-ONLY0-NEXT:    [[TMP374:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP374]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END904]]
+// SIMD-ONLY0:       if.end904:
+// SIMD-ONLY0-NEXT:    [[TMP375:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV905:%.*]] = sext i8 [[TMP375]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP376:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV906:%.*]] = sext i8 [[TMP376]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP907:%.*]] = icmp eq i32 [[CONV905]], [[CONV906]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP907]], label [[IF_THEN909:%.*]], label [[IF_END910:%.*]]
+// SIMD-ONLY0:       if.then909:
+// SIMD-ONLY0-NEXT:    [[TMP377:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP377]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END910]]
+// SIMD-ONLY0:       if.end910:
+// SIMD-ONLY0-NEXT:    [[TMP378:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV911:%.*]] = zext i8 [[TMP378]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP379:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV912:%.*]] = zext i8 [[TMP379]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP913:%.*]] = icmp sgt i32 [[CONV911]], [[CONV912]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP913]], label [[COND_TRUE915:%.*]], label [[COND_FALSE917:%.*]]
+// SIMD-ONLY0:       cond.true915:
+// SIMD-ONLY0-NEXT:    [[TMP380:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV916:%.*]] = zext i8 [[TMP380]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END919:%.*]]
+// SIMD-ONLY0:       cond.false917:
+// SIMD-ONLY0-NEXT:    [[TMP381:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV918:%.*]] = zext i8 [[TMP381]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END919]]
+// SIMD-ONLY0:       cond.end919:
+// SIMD-ONLY0-NEXT:    [[COND920:%.*]] = phi i32 [ [[CONV916]], [[COND_TRUE915]] ], [ [[CONV918]], [[COND_FALSE917]] ]
+// SIMD-ONLY0-NEXT:    [[CONV921:%.*]] = trunc i32 [[COND920]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV921]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP382:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV922:%.*]] = zext i8 [[TMP382]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP383:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV923:%.*]] = zext i8 [[TMP383]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP924:%.*]] = icmp slt i32 [[CONV922]], [[CONV923]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP924]], label [[COND_TRUE926:%.*]], label [[COND_FALSE928:%.*]]
+// SIMD-ONLY0:       cond.true926:
+// SIMD-ONLY0-NEXT:    [[TMP384:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV927:%.*]] = zext i8 [[TMP384]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END930:%.*]]
+// SIMD-ONLY0:       cond.false928:
+// SIMD-ONLY0-NEXT:    [[TMP385:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV929:%.*]] = zext i8 [[TMP385]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END930]]
+// SIMD-ONLY0:       cond.end930:
+// SIMD-ONLY0-NEXT:    [[COND931:%.*]] = phi i32 [ [[CONV927]], [[COND_TRUE926]] ], [ [[CONV929]], [[COND_FALSE928]] ]
+// SIMD-ONLY0-NEXT:    [[CONV932:%.*]] = trunc i32 [[COND931]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV932]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP386:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV933:%.*]] = zext i8 [[TMP386]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP387:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV934:%.*]] = zext i8 [[TMP387]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP935:%.*]] = icmp sgt i32 [[CONV933]], [[CONV934]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP935]], label [[COND_TRUE937:%.*]], label [[COND_FALSE939:%.*]]
+// SIMD-ONLY0:       cond.true937:
+// SIMD-ONLY0-NEXT:    [[TMP388:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV938:%.*]] = zext i8 [[TMP388]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END941:%.*]]
+// SIMD-ONLY0:       cond.false939:
+// SIMD-ONLY0-NEXT:    [[TMP389:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV940:%.*]] = zext i8 [[TMP389]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END941]]
+// SIMD-ONLY0:       cond.end941:
+// SIMD-ONLY0-NEXT:    [[COND942:%.*]] = phi i32 [ [[CONV938]], [[COND_TRUE937]] ], [ [[CONV940]], [[COND_FALSE939]] ]
+// SIMD-ONLY0-NEXT:    [[CONV943:%.*]] = trunc i32 [[COND942]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV943]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP390:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV944:%.*]] = zext i8 [[TMP390]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP391:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV945:%.*]] = zext i8 [[TMP391]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP946:%.*]] = icmp slt i32 [[CONV944]], [[CONV945]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP946]], label [[COND_TRUE948:%.*]], label [[COND_FALSE950:%.*]]
+// SIMD-ONLY0:       cond.true948:
+// SIMD-ONLY0-NEXT:    [[TMP392:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV949:%.*]] = zext i8 [[TMP392]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END952:%.*]]
+// SIMD-ONLY0:       cond.false950:
+// SIMD-ONLY0-NEXT:    [[TMP393:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV951:%.*]] = zext i8 [[TMP393]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END952]]
+// SIMD-ONLY0:       cond.end952:
+// SIMD-ONLY0-NEXT:    [[COND953:%.*]] = phi i32 [ [[CONV949]], [[COND_TRUE948]] ], [ [[CONV951]], [[COND_FALSE950]] ]
+// SIMD-ONLY0-NEXT:    [[CONV954:%.*]] = trunc i32 [[COND953]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV954]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP394:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV955:%.*]] = zext i8 [[TMP394]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP395:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV956:%.*]] = zext i8 [[TMP395]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP957:%.*]] = icmp sgt i32 [[CONV955]], [[CONV956]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP957]], label [[IF_THEN959:%.*]], label [[IF_END960:%.*]]
+// SIMD-ONLY0:       if.then959:
+// SIMD-ONLY0-NEXT:    [[TMP396:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP396]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END960]]
+// SIMD-ONLY0:       if.end960:
+// SIMD-ONLY0-NEXT:    [[TMP397:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV961:%.*]] = zext i8 [[TMP397]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP398:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV962:%.*]] = zext i8 [[TMP398]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP963:%.*]] = icmp slt i32 [[CONV961]], [[CONV962]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP963]], label [[IF_THEN965:%.*]], label [[IF_END966:%.*]]
+// SIMD-ONLY0:       if.then965:
+// SIMD-ONLY0-NEXT:    [[TMP399:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP399]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END966]]
+// SIMD-ONLY0:       if.end966:
+// SIMD-ONLY0-NEXT:    [[TMP400:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV967:%.*]] = zext i8 [[TMP400]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP401:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV968:%.*]] = zext i8 [[TMP401]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP969:%.*]] = icmp sgt i32 [[CONV967]], [[CONV968]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP969]], label [[IF_THEN971:%.*]], label [[IF_END972:%.*]]
+// SIMD-ONLY0:       if.then971:
+// SIMD-ONLY0-NEXT:    [[TMP402:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP402]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END972]]
+// SIMD-ONLY0:       if.end972:
+// SIMD-ONLY0-NEXT:    [[TMP403:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV973:%.*]] = zext i8 [[TMP403]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP404:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV974:%.*]] = zext i8 [[TMP404]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP975:%.*]] = icmp slt i32 [[CONV973]], [[CONV974]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP975]], label [[IF_THEN977:%.*]], label [[IF_END978:%.*]]
+// SIMD-ONLY0:       if.then977:
+// SIMD-ONLY0-NEXT:    [[TMP405:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP405]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END978]]
+// SIMD-ONLY0:       if.end978:
+// SIMD-ONLY0-NEXT:    [[TMP406:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV979:%.*]] = zext i8 [[TMP406]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP407:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV980:%.*]] = zext i8 [[TMP407]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP981:%.*]] = icmp eq i32 [[CONV979]], [[CONV980]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP981]], label [[COND_TRUE983:%.*]], label [[COND_FALSE985:%.*]]
+// SIMD-ONLY0:       cond.true983:
+// SIMD-ONLY0-NEXT:    [[TMP408:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV984:%.*]] = zext i8 [[TMP408]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END987:%.*]]
+// SIMD-ONLY0:       cond.false985:
+// SIMD-ONLY0-NEXT:    [[TMP409:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV986:%.*]] = zext i8 [[TMP409]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END987]]
+// SIMD-ONLY0:       cond.end987:
+// SIMD-ONLY0-NEXT:    [[COND988:%.*]] = phi i32 [ [[CONV984]], [[COND_TRUE983]] ], [ [[CONV986]], [[COND_FALSE985]] ]
+// SIMD-ONLY0-NEXT:    [[CONV989:%.*]] = trunc i32 [[COND988]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV989]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP410:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV990:%.*]] = zext i8 [[TMP410]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP411:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV991:%.*]] = zext i8 [[TMP411]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP992:%.*]] = icmp eq i32 [[CONV990]], [[CONV991]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP992]], label [[COND_TRUE994:%.*]], label [[COND_FALSE996:%.*]]
+// SIMD-ONLY0:       cond.true994:
+// SIMD-ONLY0-NEXT:    [[TMP412:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV995:%.*]] = zext i8 [[TMP412]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END998:%.*]]
+// SIMD-ONLY0:       cond.false996:
+// SIMD-ONLY0-NEXT:    [[TMP413:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV997:%.*]] = zext i8 [[TMP413]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END998]]
+// SIMD-ONLY0:       cond.end998:
+// SIMD-ONLY0-NEXT:    [[COND999:%.*]] = phi i32 [ [[CONV995]], [[COND_TRUE994]] ], [ [[CONV997]], [[COND_FALSE996]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1000:%.*]] = trunc i32 [[COND999]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV1000]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP414:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1001:%.*]] = zext i8 [[TMP414]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP415:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1002:%.*]] = zext i8 [[TMP415]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1003:%.*]] = icmp eq i32 [[CONV1001]], [[CONV1002]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1003]], label [[IF_THEN1005:%.*]], label [[IF_END1006:%.*]]
+// SIMD-ONLY0:       if.then1005:
+// SIMD-ONLY0-NEXT:    [[TMP416:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP416]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END1006]]
+// SIMD-ONLY0:       if.end1006:
+// SIMD-ONLY0-NEXT:    [[TMP417:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1007:%.*]] = zext i8 [[TMP417]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP418:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1008:%.*]] = zext i8 [[TMP418]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1009:%.*]] = icmp eq i32 [[CONV1007]], [[CONV1008]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1009]], label [[IF_THEN1011:%.*]], label [[IF_END1012:%.*]]
+// SIMD-ONLY0:       if.then1011:
+// SIMD-ONLY0-NEXT:    [[TMP419:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP419]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END1012]]
+// SIMD-ONLY0:       if.end1012:
+// SIMD-ONLY0-NEXT:    [[TMP420:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1013:%.*]] = sext i8 [[TMP420]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP421:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1014:%.*]] = sext i8 [[TMP421]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1015:%.*]] = icmp sgt i32 [[CONV1013]], [[CONV1014]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1015]], label [[COND_TRUE1017:%.*]], label [[COND_FALSE1019:%.*]]
+// SIMD-ONLY0:       cond.true1017:
+// SIMD-ONLY0-NEXT:    [[TMP422:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1018:%.*]] = sext i8 [[TMP422]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1021:%.*]]
+// SIMD-ONLY0:       cond.false1019:
+// SIMD-ONLY0-NEXT:    [[TMP423:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1020:%.*]] = sext i8 [[TMP423]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1021]]
+// SIMD-ONLY0:       cond.end1021:
+// SIMD-ONLY0-NEXT:    [[COND1022:%.*]] = phi i32 [ [[CONV1018]], [[COND_TRUE1017]] ], [ [[CONV1020]], [[COND_FALSE1019]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1023:%.*]] = trunc i32 [[COND1022]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV1023]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP424:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1024:%.*]] = sext i8 [[TMP424]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP425:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1025:%.*]] = sext i8 [[TMP425]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1026:%.*]] = icmp slt i32 [[CONV1024]], [[CONV1025]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1026]], label [[COND_TRUE1028:%.*]], label [[COND_FALSE1030:%.*]]
+// SIMD-ONLY0:       cond.true1028:
+// SIMD-ONLY0-NEXT:    [[TMP426:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1029:%.*]] = sext i8 [[TMP426]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1032:%.*]]
+// SIMD-ONLY0:       cond.false1030:
+// SIMD-ONLY0-NEXT:    [[TMP427:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1031:%.*]] = sext i8 [[TMP427]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1032]]
+// SIMD-ONLY0:       cond.end1032:
+// SIMD-ONLY0-NEXT:    [[COND1033:%.*]] = phi i32 [ [[CONV1029]], [[COND_TRUE1028]] ], [ [[CONV1031]], [[COND_FALSE1030]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1034:%.*]] = trunc i32 [[COND1033]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV1034]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP428:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1035:%.*]] = sext i8 [[TMP428]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP429:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1036:%.*]] = sext i8 [[TMP429]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1037:%.*]] = icmp sgt i32 [[CONV1035]], [[CONV1036]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1037]], label [[COND_TRUE1039:%.*]], label [[COND_FALSE1041:%.*]]
+// SIMD-ONLY0:       cond.true1039:
+// SIMD-ONLY0-NEXT:    [[TMP430:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1040:%.*]] = sext i8 [[TMP430]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1043:%.*]]
+// SIMD-ONLY0:       cond.false1041:
+// SIMD-ONLY0-NEXT:    [[TMP431:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1042:%.*]] = sext i8 [[TMP431]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1043]]
+// SIMD-ONLY0:       cond.end1043:
+// SIMD-ONLY0-NEXT:    [[COND1044:%.*]] = phi i32 [ [[CONV1040]], [[COND_TRUE1039]] ], [ [[CONV1042]], [[COND_FALSE1041]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1045:%.*]] = trunc i32 [[COND1044]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV1045]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP432:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1046:%.*]] = sext i8 [[TMP432]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP433:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1047:%.*]] = sext i8 [[TMP433]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1048:%.*]] = icmp slt i32 [[CONV1046]], [[CONV1047]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1048]], label [[COND_TRUE1050:%.*]], label [[COND_FALSE1052:%.*]]
+// SIMD-ONLY0:       cond.true1050:
+// SIMD-ONLY0-NEXT:    [[TMP434:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1051:%.*]] = sext i8 [[TMP434]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1054:%.*]]
+// SIMD-ONLY0:       cond.false1052:
+// SIMD-ONLY0-NEXT:    [[TMP435:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1053:%.*]] = sext i8 [[TMP435]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1054]]
+// SIMD-ONLY0:       cond.end1054:
+// SIMD-ONLY0-NEXT:    [[COND1055:%.*]] = phi i32 [ [[CONV1051]], [[COND_TRUE1050]] ], [ [[CONV1053]], [[COND_FALSE1052]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1056:%.*]] = trunc i32 [[COND1055]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV1056]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP436:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1057:%.*]] = sext i8 [[TMP436]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP437:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1058:%.*]] = sext i8 [[TMP437]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1059:%.*]] = icmp sgt i32 [[CONV1057]], [[CONV1058]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1059]], label [[IF_THEN1061:%.*]], label [[IF_END1062:%.*]]
+// SIMD-ONLY0:       if.then1061:
+// SIMD-ONLY0-NEXT:    [[TMP438:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP438]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END1062]]
+// SIMD-ONLY0:       if.end1062:
+// SIMD-ONLY0-NEXT:    [[TMP439:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1063:%.*]] = sext i8 [[TMP439]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP440:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1064:%.*]] = sext i8 [[TMP440]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1065:%.*]] = icmp slt i32 [[CONV1063]], [[CONV1064]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1065]], label [[IF_THEN1067:%.*]], label [[IF_END1068:%.*]]
+// SIMD-ONLY0:       if.then1067:
+// SIMD-ONLY0-NEXT:    [[TMP441:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP441]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END1068]]
+// SIMD-ONLY0:       if.end1068:
+// SIMD-ONLY0-NEXT:    [[TMP442:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1069:%.*]] = sext i8 [[TMP442]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP443:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1070:%.*]] = sext i8 [[TMP443]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1071:%.*]] = icmp sgt i32 [[CONV1069]], [[CONV1070]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1071]], label [[IF_THEN1073:%.*]], label [[IF_END1074:%.*]]
+// SIMD-ONLY0:       if.then1073:
+// SIMD-ONLY0-NEXT:    [[TMP444:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP444]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END1074]]
+// SIMD-ONLY0:       if.end1074:
+// SIMD-ONLY0-NEXT:    [[TMP445:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1075:%.*]] = sext i8 [[TMP445]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP446:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1076:%.*]] = sext i8 [[TMP446]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1077:%.*]] = icmp slt i32 [[CONV1075]], [[CONV1076]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1077]], label [[IF_THEN1079:%.*]], label [[IF_END1080:%.*]]
+// SIMD-ONLY0:       if.then1079:
+// SIMD-ONLY0-NEXT:    [[TMP447:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP447]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END1080]]
+// SIMD-ONLY0:       if.end1080:
+// SIMD-ONLY0-NEXT:    [[TMP448:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1081:%.*]] = sext i8 [[TMP448]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP449:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1082:%.*]] = sext i8 [[TMP449]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1083:%.*]] = icmp eq i32 [[CONV1081]], [[CONV1082]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1083]], label [[COND_TRUE1085:%.*]], label [[COND_FALSE1087:%.*]]
+// SIMD-ONLY0:       cond.true1085:
+// SIMD-ONLY0-NEXT:    [[TMP450:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1086:%.*]] = sext i8 [[TMP450]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1089:%.*]]
+// SIMD-ONLY0:       cond.false1087:
+// SIMD-ONLY0-NEXT:    [[TMP451:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1088:%.*]] = sext i8 [[TMP451]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1089]]
+// SIMD-ONLY0:       cond.end1089:
+// SIMD-ONLY0-NEXT:    [[COND1090:%.*]] = phi i32 [ [[CONV1086]], [[COND_TRUE1085]] ], [ [[CONV1088]], [[COND_FALSE1087]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1091:%.*]] = trunc i32 [[COND1090]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV1091]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP452:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1092:%.*]] = sext i8 [[TMP452]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP453:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1093:%.*]] = sext i8 [[TMP453]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1094:%.*]] = icmp eq i32 [[CONV1092]], [[CONV1093]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1094]], label [[COND_TRUE1096:%.*]], label [[COND_FALSE1098:%.*]]
+// SIMD-ONLY0:       cond.true1096:
+// SIMD-ONLY0-NEXT:    [[TMP454:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1097:%.*]] = sext i8 [[TMP454]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1100:%.*]]
+// SIMD-ONLY0:       cond.false1098:
+// SIMD-ONLY0-NEXT:    [[TMP455:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1099:%.*]] = sext i8 [[TMP455]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1100]]
+// SIMD-ONLY0:       cond.end1100:
+// SIMD-ONLY0-NEXT:    [[COND1101:%.*]] = phi i32 [ [[CONV1097]], [[COND_TRUE1096]] ], [ [[CONV1099]], [[COND_FALSE1098]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1102:%.*]] = trunc i32 [[COND1101]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV1102]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP456:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1103:%.*]] = sext i8 [[TMP456]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP457:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1104:%.*]] = sext i8 [[TMP457]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1105:%.*]] = icmp eq i32 [[CONV1103]], [[CONV1104]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1105]], label [[IF_THEN1107:%.*]], label [[IF_END1108:%.*]]
+// SIMD-ONLY0:       if.then1107:
+// SIMD-ONLY0-NEXT:    [[TMP458:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP458]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END1108]]
+// SIMD-ONLY0:       if.end1108:
+// SIMD-ONLY0-NEXT:    [[TMP459:%.*]] = load i8, i8* [[CE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1109:%.*]] = sext i8 [[TMP459]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP460:%.*]] = load i8, i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1110:%.*]] = sext i8 [[TMP460]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1111:%.*]] = icmp eq i32 [[CONV1109]], [[CONV1110]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1111]], label [[IF_THEN1113:%.*]], label [[IF_END1114:%.*]]
+// SIMD-ONLY0:       if.then1113:
+// SIMD-ONLY0-NEXT:    [[TMP461:%.*]] = load i8, i8* [[CD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP461]], i8* [[CX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END1114]]
+// SIMD-ONLY0:       if.end1114:
+// SIMD-ONLY0-NEXT:    [[TMP462:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1115:%.*]] = zext i8 [[TMP462]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP463:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1116:%.*]] = zext i8 [[TMP463]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1117:%.*]] = icmp sgt i32 [[CONV1115]], [[CONV1116]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1117]], label [[COND_TRUE1119:%.*]], label [[COND_FALSE1121:%.*]]
+// SIMD-ONLY0:       cond.true1119:
+// SIMD-ONLY0-NEXT:    [[TMP464:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1120:%.*]] = zext i8 [[TMP464]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1123:%.*]]
+// SIMD-ONLY0:       cond.false1121:
+// SIMD-ONLY0-NEXT:    [[TMP465:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1122:%.*]] = zext i8 [[TMP465]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1123]]
+// SIMD-ONLY0:       cond.end1123:
+// SIMD-ONLY0-NEXT:    [[COND1124:%.*]] = phi i32 [ [[CONV1120]], [[COND_TRUE1119]] ], [ [[CONV1122]], [[COND_FALSE1121]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1125:%.*]] = trunc i32 [[COND1124]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV1125]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP466:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1126:%.*]] = zext i8 [[TMP466]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP467:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1127:%.*]] = zext i8 [[TMP467]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1128:%.*]] = icmp slt i32 [[CONV1126]], [[CONV1127]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1128]], label [[COND_TRUE1130:%.*]], label [[COND_FALSE1132:%.*]]
+// SIMD-ONLY0:       cond.true1130:
+// SIMD-ONLY0-NEXT:    [[TMP468:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1131:%.*]] = zext i8 [[TMP468]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1134:%.*]]
+// SIMD-ONLY0:       cond.false1132:
+// SIMD-ONLY0-NEXT:    [[TMP469:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1133:%.*]] = zext i8 [[TMP469]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1134]]
+// SIMD-ONLY0:       cond.end1134:
+// SIMD-ONLY0-NEXT:    [[COND1135:%.*]] = phi i32 [ [[CONV1131]], [[COND_TRUE1130]] ], [ [[CONV1133]], [[COND_FALSE1132]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1136:%.*]] = trunc i32 [[COND1135]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV1136]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP470:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1137:%.*]] = zext i8 [[TMP470]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP471:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1138:%.*]] = zext i8 [[TMP471]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1139:%.*]] = icmp sgt i32 [[CONV1137]], [[CONV1138]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1139]], label [[COND_TRUE1141:%.*]], label [[COND_FALSE1143:%.*]]
+// SIMD-ONLY0:       cond.true1141:
+// SIMD-ONLY0-NEXT:    [[TMP472:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1142:%.*]] = zext i8 [[TMP472]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1145:%.*]]
+// SIMD-ONLY0:       cond.false1143:
+// SIMD-ONLY0-NEXT:    [[TMP473:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1144:%.*]] = zext i8 [[TMP473]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1145]]
+// SIMD-ONLY0:       cond.end1145:
+// SIMD-ONLY0-NEXT:    [[COND1146:%.*]] = phi i32 [ [[CONV1142]], [[COND_TRUE1141]] ], [ [[CONV1144]], [[COND_FALSE1143]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1147:%.*]] = trunc i32 [[COND1146]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV1147]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP474:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1148:%.*]] = zext i8 [[TMP474]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP475:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1149:%.*]] = zext i8 [[TMP475]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1150:%.*]] = icmp slt i32 [[CONV1148]], [[CONV1149]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1150]], label [[COND_TRUE1152:%.*]], label [[COND_FALSE1154:%.*]]
+// SIMD-ONLY0:       cond.true1152:
+// SIMD-ONLY0-NEXT:    [[TMP476:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1153:%.*]] = zext i8 [[TMP476]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1156:%.*]]
+// SIMD-ONLY0:       cond.false1154:
+// SIMD-ONLY0-NEXT:    [[TMP477:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1155:%.*]] = zext i8 [[TMP477]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1156]]
+// SIMD-ONLY0:       cond.end1156:
+// SIMD-ONLY0-NEXT:    [[COND1157:%.*]] = phi i32 [ [[CONV1153]], [[COND_TRUE1152]] ], [ [[CONV1155]], [[COND_FALSE1154]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1158:%.*]] = trunc i32 [[COND1157]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV1158]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP478:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1159:%.*]] = zext i8 [[TMP478]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP479:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1160:%.*]] = zext i8 [[TMP479]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1161:%.*]] = icmp sgt i32 [[CONV1159]], [[CONV1160]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1161]], label [[IF_THEN1163:%.*]], label [[IF_END1164:%.*]]
+// SIMD-ONLY0:       if.then1163:
+// SIMD-ONLY0-NEXT:    [[TMP480:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP480]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END1164]]
+// SIMD-ONLY0:       if.end1164:
+// SIMD-ONLY0-NEXT:    [[TMP481:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1165:%.*]] = zext i8 [[TMP481]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP482:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1166:%.*]] = zext i8 [[TMP482]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1167:%.*]] = icmp slt i32 [[CONV1165]], [[CONV1166]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1167]], label [[IF_THEN1169:%.*]], label [[IF_END1170:%.*]]
+// SIMD-ONLY0:       if.then1169:
+// SIMD-ONLY0-NEXT:    [[TMP483:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP483]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END1170]]
+// SIMD-ONLY0:       if.end1170:
+// SIMD-ONLY0-NEXT:    [[TMP484:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1171:%.*]] = zext i8 [[TMP484]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP485:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1172:%.*]] = zext i8 [[TMP485]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1173:%.*]] = icmp sgt i32 [[CONV1171]], [[CONV1172]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1173]], label [[IF_THEN1175:%.*]], label [[IF_END1176:%.*]]
+// SIMD-ONLY0:       if.then1175:
+// SIMD-ONLY0-NEXT:    [[TMP486:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP486]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END1176]]
+// SIMD-ONLY0:       if.end1176:
+// SIMD-ONLY0-NEXT:    [[TMP487:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1177:%.*]] = zext i8 [[TMP487]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP488:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1178:%.*]] = zext i8 [[TMP488]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1179:%.*]] = icmp slt i32 [[CONV1177]], [[CONV1178]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1179]], label [[IF_THEN1181:%.*]], label [[IF_END1182:%.*]]
+// SIMD-ONLY0:       if.then1181:
+// SIMD-ONLY0-NEXT:    [[TMP489:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP489]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END1182]]
+// SIMD-ONLY0:       if.end1182:
+// SIMD-ONLY0-NEXT:    [[TMP490:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1183:%.*]] = zext i8 [[TMP490]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP491:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1184:%.*]] = zext i8 [[TMP491]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1185:%.*]] = icmp eq i32 [[CONV1183]], [[CONV1184]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1185]], label [[COND_TRUE1187:%.*]], label [[COND_FALSE1189:%.*]]
+// SIMD-ONLY0:       cond.true1187:
+// SIMD-ONLY0-NEXT:    [[TMP492:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1188:%.*]] = zext i8 [[TMP492]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1191:%.*]]
+// SIMD-ONLY0:       cond.false1189:
+// SIMD-ONLY0-NEXT:    [[TMP493:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1190:%.*]] = zext i8 [[TMP493]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1191]]
+// SIMD-ONLY0:       cond.end1191:
+// SIMD-ONLY0-NEXT:    [[COND1192:%.*]] = phi i32 [ [[CONV1188]], [[COND_TRUE1187]] ], [ [[CONV1190]], [[COND_FALSE1189]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1193:%.*]] = trunc i32 [[COND1192]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV1193]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP494:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1194:%.*]] = zext i8 [[TMP494]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP495:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1195:%.*]] = zext i8 [[TMP495]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1196:%.*]] = icmp eq i32 [[CONV1194]], [[CONV1195]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1196]], label [[COND_TRUE1198:%.*]], label [[COND_FALSE1200:%.*]]
+// SIMD-ONLY0:       cond.true1198:
+// SIMD-ONLY0-NEXT:    [[TMP496:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1199:%.*]] = zext i8 [[TMP496]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1202:%.*]]
+// SIMD-ONLY0:       cond.false1200:
+// SIMD-ONLY0-NEXT:    [[TMP497:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1201:%.*]] = zext i8 [[TMP497]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1202]]
+// SIMD-ONLY0:       cond.end1202:
+// SIMD-ONLY0-NEXT:    [[COND1203:%.*]] = phi i32 [ [[CONV1199]], [[COND_TRUE1198]] ], [ [[CONV1201]], [[COND_FALSE1200]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1204:%.*]] = trunc i32 [[COND1203]] to i8
+// SIMD-ONLY0-NEXT:    store i8 [[CONV1204]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[TMP498:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1205:%.*]] = zext i8 [[TMP498]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP499:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1206:%.*]] = zext i8 [[TMP499]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1207:%.*]] = icmp eq i32 [[CONV1205]], [[CONV1206]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1207]], label [[IF_THEN1209:%.*]], label [[IF_END1210:%.*]]
+// SIMD-ONLY0:       if.then1209:
+// SIMD-ONLY0-NEXT:    [[TMP500:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP500]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END1210]]
+// SIMD-ONLY0:       if.end1210:
+// SIMD-ONLY0-NEXT:    [[TMP501:%.*]] = load i8, i8* [[UCE]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1211:%.*]] = zext i8 [[TMP501]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP502:%.*]] = load i8, i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    [[CONV1212:%.*]] = zext i8 [[TMP502]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1213:%.*]] = icmp eq i32 [[CONV1211]], [[CONV1212]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1213]], label [[IF_THEN1215:%.*]], label [[IF_END1216:%.*]]
+// SIMD-ONLY0:       if.then1215:
+// SIMD-ONLY0-NEXT:    [[TMP503:%.*]] = load i8, i8* [[UCD]], align 1
+// SIMD-ONLY0-NEXT:    store i8 [[TMP503]], i8* [[UCX]], align 1
+// SIMD-ONLY0-NEXT:    br label [[IF_END1216]]
+// SIMD-ONLY0:       if.end1216:
+// SIMD-ONLY0-NEXT:    [[TMP504:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1217:%.*]] = sext i16 [[TMP504]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP505:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1218:%.*]] = sext i16 [[TMP505]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1219:%.*]] = icmp sgt i32 [[CONV1217]], [[CONV1218]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1219]], label [[COND_TRUE1221:%.*]], label [[COND_FALSE1223:%.*]]
+// SIMD-ONLY0:       cond.true1221:
+// SIMD-ONLY0-NEXT:    [[TMP506:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1222:%.*]] = sext i16 [[TMP506]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1225:%.*]]
+// SIMD-ONLY0:       cond.false1223:
+// SIMD-ONLY0-NEXT:    [[TMP507:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1224:%.*]] = sext i16 [[TMP507]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1225]]
+// SIMD-ONLY0:       cond.end1225:
+// SIMD-ONLY0-NEXT:    [[COND1226:%.*]] = phi i32 [ [[CONV1222]], [[COND_TRUE1221]] ], [ [[CONV1224]], [[COND_FALSE1223]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1227:%.*]] = trunc i32 [[COND1226]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1227]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP508:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1228:%.*]] = sext i16 [[TMP508]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP509:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1229:%.*]] = sext i16 [[TMP509]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1230:%.*]] = icmp slt i32 [[CONV1228]], [[CONV1229]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1230]], label [[COND_TRUE1232:%.*]], label [[COND_FALSE1234:%.*]]
+// SIMD-ONLY0:       cond.true1232:
+// SIMD-ONLY0-NEXT:    [[TMP510:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1233:%.*]] = sext i16 [[TMP510]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1236:%.*]]
+// SIMD-ONLY0:       cond.false1234:
+// SIMD-ONLY0-NEXT:    [[TMP511:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1235:%.*]] = sext i16 [[TMP511]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1236]]
+// SIMD-ONLY0:       cond.end1236:
+// SIMD-ONLY0-NEXT:    [[COND1237:%.*]] = phi i32 [ [[CONV1233]], [[COND_TRUE1232]] ], [ [[CONV1235]], [[COND_FALSE1234]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1238:%.*]] = trunc i32 [[COND1237]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1238]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP512:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1239:%.*]] = sext i16 [[TMP512]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP513:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1240:%.*]] = sext i16 [[TMP513]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1241:%.*]] = icmp sgt i32 [[CONV1239]], [[CONV1240]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1241]], label [[COND_TRUE1243:%.*]], label [[COND_FALSE1245:%.*]]
+// SIMD-ONLY0:       cond.true1243:
+// SIMD-ONLY0-NEXT:    [[TMP514:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1244:%.*]] = sext i16 [[TMP514]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1247:%.*]]
+// SIMD-ONLY0:       cond.false1245:
+// SIMD-ONLY0-NEXT:    [[TMP515:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1246:%.*]] = sext i16 [[TMP515]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1247]]
+// SIMD-ONLY0:       cond.end1247:
+// SIMD-ONLY0-NEXT:    [[COND1248:%.*]] = phi i32 [ [[CONV1244]], [[COND_TRUE1243]] ], [ [[CONV1246]], [[COND_FALSE1245]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1249:%.*]] = trunc i32 [[COND1248]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1249]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP516:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1250:%.*]] = sext i16 [[TMP516]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP517:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1251:%.*]] = sext i16 [[TMP517]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1252:%.*]] = icmp slt i32 [[CONV1250]], [[CONV1251]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1252]], label [[COND_TRUE1254:%.*]], label [[COND_FALSE1256:%.*]]
+// SIMD-ONLY0:       cond.true1254:
+// SIMD-ONLY0-NEXT:    [[TMP518:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1255:%.*]] = sext i16 [[TMP518]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1258:%.*]]
+// SIMD-ONLY0:       cond.false1256:
+// SIMD-ONLY0-NEXT:    [[TMP519:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1257:%.*]] = sext i16 [[TMP519]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1258]]
+// SIMD-ONLY0:       cond.end1258:
+// SIMD-ONLY0-NEXT:    [[COND1259:%.*]] = phi i32 [ [[CONV1255]], [[COND_TRUE1254]] ], [ [[CONV1257]], [[COND_FALSE1256]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1260:%.*]] = trunc i32 [[COND1259]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1260]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP520:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1261:%.*]] = sext i16 [[TMP520]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP521:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1262:%.*]] = sext i16 [[TMP521]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1263:%.*]] = icmp sgt i32 [[CONV1261]], [[CONV1262]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1263]], label [[IF_THEN1265:%.*]], label [[IF_END1266:%.*]]
+// SIMD-ONLY0:       if.then1265:
+// SIMD-ONLY0-NEXT:    [[TMP522:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP522]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1266]]
+// SIMD-ONLY0:       if.end1266:
+// SIMD-ONLY0-NEXT:    [[TMP523:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1267:%.*]] = sext i16 [[TMP523]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP524:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1268:%.*]] = sext i16 [[TMP524]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1269:%.*]] = icmp slt i32 [[CONV1267]], [[CONV1268]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1269]], label [[IF_THEN1271:%.*]], label [[IF_END1272:%.*]]
+// SIMD-ONLY0:       if.then1271:
+// SIMD-ONLY0-NEXT:    [[TMP525:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP525]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1272]]
+// SIMD-ONLY0:       if.end1272:
+// SIMD-ONLY0-NEXT:    [[TMP526:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1273:%.*]] = sext i16 [[TMP526]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP527:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1274:%.*]] = sext i16 [[TMP527]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1275:%.*]] = icmp sgt i32 [[CONV1273]], [[CONV1274]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1275]], label [[IF_THEN1277:%.*]], label [[IF_END1278:%.*]]
+// SIMD-ONLY0:       if.then1277:
+// SIMD-ONLY0-NEXT:    [[TMP528:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP528]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1278]]
+// SIMD-ONLY0:       if.end1278:
+// SIMD-ONLY0-NEXT:    [[TMP529:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1279:%.*]] = sext i16 [[TMP529]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP530:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1280:%.*]] = sext i16 [[TMP530]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1281:%.*]] = icmp slt i32 [[CONV1279]], [[CONV1280]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1281]], label [[IF_THEN1283:%.*]], label [[IF_END1284:%.*]]
+// SIMD-ONLY0:       if.then1283:
+// SIMD-ONLY0-NEXT:    [[TMP531:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP531]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1284]]
+// SIMD-ONLY0:       if.end1284:
+// SIMD-ONLY0-NEXT:    [[TMP532:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1285:%.*]] = sext i16 [[TMP532]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP533:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1286:%.*]] = sext i16 [[TMP533]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1287:%.*]] = icmp eq i32 [[CONV1285]], [[CONV1286]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1287]], label [[COND_TRUE1289:%.*]], label [[COND_FALSE1291:%.*]]
+// SIMD-ONLY0:       cond.true1289:
+// SIMD-ONLY0-NEXT:    [[TMP534:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1290:%.*]] = sext i16 [[TMP534]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1293:%.*]]
+// SIMD-ONLY0:       cond.false1291:
+// SIMD-ONLY0-NEXT:    [[TMP535:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1292:%.*]] = sext i16 [[TMP535]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1293]]
+// SIMD-ONLY0:       cond.end1293:
+// SIMD-ONLY0-NEXT:    [[COND1294:%.*]] = phi i32 [ [[CONV1290]], [[COND_TRUE1289]] ], [ [[CONV1292]], [[COND_FALSE1291]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1295:%.*]] = trunc i32 [[COND1294]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1295]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP536:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1296:%.*]] = sext i16 [[TMP536]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP537:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1297:%.*]] = sext i16 [[TMP537]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1298:%.*]] = icmp eq i32 [[CONV1296]], [[CONV1297]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1298]], label [[COND_TRUE1300:%.*]], label [[COND_FALSE1302:%.*]]
+// SIMD-ONLY0:       cond.true1300:
+// SIMD-ONLY0-NEXT:    [[TMP538:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1301:%.*]] = sext i16 [[TMP538]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1304:%.*]]
+// SIMD-ONLY0:       cond.false1302:
+// SIMD-ONLY0-NEXT:    [[TMP539:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1303:%.*]] = sext i16 [[TMP539]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1304]]
+// SIMD-ONLY0:       cond.end1304:
+// SIMD-ONLY0-NEXT:    [[COND1305:%.*]] = phi i32 [ [[CONV1301]], [[COND_TRUE1300]] ], [ [[CONV1303]], [[COND_FALSE1302]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1306:%.*]] = trunc i32 [[COND1305]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1306]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP540:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1307:%.*]] = sext i16 [[TMP540]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP541:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1308:%.*]] = sext i16 [[TMP541]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1309:%.*]] = icmp eq i32 [[CONV1307]], [[CONV1308]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1309]], label [[IF_THEN1311:%.*]], label [[IF_END1312:%.*]]
+// SIMD-ONLY0:       if.then1311:
+// SIMD-ONLY0-NEXT:    [[TMP542:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP542]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1312]]
+// SIMD-ONLY0:       if.end1312:
+// SIMD-ONLY0-NEXT:    [[TMP543:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1313:%.*]] = sext i16 [[TMP543]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP544:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1314:%.*]] = sext i16 [[TMP544]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1315:%.*]] = icmp eq i32 [[CONV1313]], [[CONV1314]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1315]], label [[IF_THEN1317:%.*]], label [[IF_END1318:%.*]]
+// SIMD-ONLY0:       if.then1317:
+// SIMD-ONLY0-NEXT:    [[TMP545:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP545]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1318]]
+// SIMD-ONLY0:       if.end1318:
+// SIMD-ONLY0-NEXT:    [[TMP546:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1319:%.*]] = zext i16 [[TMP546]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP547:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1320:%.*]] = zext i16 [[TMP547]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1321:%.*]] = icmp sgt i32 [[CONV1319]], [[CONV1320]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1321]], label [[COND_TRUE1323:%.*]], label [[COND_FALSE1325:%.*]]
+// SIMD-ONLY0:       cond.true1323:
+// SIMD-ONLY0-NEXT:    [[TMP548:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1324:%.*]] = zext i16 [[TMP548]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1327:%.*]]
+// SIMD-ONLY0:       cond.false1325:
+// SIMD-ONLY0-NEXT:    [[TMP549:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1326:%.*]] = zext i16 [[TMP549]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1327]]
+// SIMD-ONLY0:       cond.end1327:
+// SIMD-ONLY0-NEXT:    [[COND1328:%.*]] = phi i32 [ [[CONV1324]], [[COND_TRUE1323]] ], [ [[CONV1326]], [[COND_FALSE1325]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1329:%.*]] = trunc i32 [[COND1328]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1329]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP550:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1330:%.*]] = zext i16 [[TMP550]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP551:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1331:%.*]] = zext i16 [[TMP551]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1332:%.*]] = icmp slt i32 [[CONV1330]], [[CONV1331]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1332]], label [[COND_TRUE1334:%.*]], label [[COND_FALSE1336:%.*]]
+// SIMD-ONLY0:       cond.true1334:
+// SIMD-ONLY0-NEXT:    [[TMP552:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1335:%.*]] = zext i16 [[TMP552]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1338:%.*]]
+// SIMD-ONLY0:       cond.false1336:
+// SIMD-ONLY0-NEXT:    [[TMP553:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1337:%.*]] = zext i16 [[TMP553]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1338]]
+// SIMD-ONLY0:       cond.end1338:
+// SIMD-ONLY0-NEXT:    [[COND1339:%.*]] = phi i32 [ [[CONV1335]], [[COND_TRUE1334]] ], [ [[CONV1337]], [[COND_FALSE1336]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1340:%.*]] = trunc i32 [[COND1339]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1340]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP554:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1341:%.*]] = zext i16 [[TMP554]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP555:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1342:%.*]] = zext i16 [[TMP555]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1343:%.*]] = icmp sgt i32 [[CONV1341]], [[CONV1342]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1343]], label [[COND_TRUE1345:%.*]], label [[COND_FALSE1347:%.*]]
+// SIMD-ONLY0:       cond.true1345:
+// SIMD-ONLY0-NEXT:    [[TMP556:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1346:%.*]] = zext i16 [[TMP556]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1349:%.*]]
+// SIMD-ONLY0:       cond.false1347:
+// SIMD-ONLY0-NEXT:    [[TMP557:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1348:%.*]] = zext i16 [[TMP557]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1349]]
+// SIMD-ONLY0:       cond.end1349:
+// SIMD-ONLY0-NEXT:    [[COND1350:%.*]] = phi i32 [ [[CONV1346]], [[COND_TRUE1345]] ], [ [[CONV1348]], [[COND_FALSE1347]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1351:%.*]] = trunc i32 [[COND1350]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1351]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP558:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1352:%.*]] = zext i16 [[TMP558]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP559:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1353:%.*]] = zext i16 [[TMP559]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1354:%.*]] = icmp slt i32 [[CONV1352]], [[CONV1353]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1354]], label [[COND_TRUE1356:%.*]], label [[COND_FALSE1358:%.*]]
+// SIMD-ONLY0:       cond.true1356:
+// SIMD-ONLY0-NEXT:    [[TMP560:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1357:%.*]] = zext i16 [[TMP560]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1360:%.*]]
+// SIMD-ONLY0:       cond.false1358:
+// SIMD-ONLY0-NEXT:    [[TMP561:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1359:%.*]] = zext i16 [[TMP561]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1360]]
+// SIMD-ONLY0:       cond.end1360:
+// SIMD-ONLY0-NEXT:    [[COND1361:%.*]] = phi i32 [ [[CONV1357]], [[COND_TRUE1356]] ], [ [[CONV1359]], [[COND_FALSE1358]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1362:%.*]] = trunc i32 [[COND1361]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1362]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP562:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1363:%.*]] = zext i16 [[TMP562]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP563:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1364:%.*]] = zext i16 [[TMP563]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1365:%.*]] = icmp sgt i32 [[CONV1363]], [[CONV1364]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1365]], label [[IF_THEN1367:%.*]], label [[IF_END1368:%.*]]
+// SIMD-ONLY0:       if.then1367:
+// SIMD-ONLY0-NEXT:    [[TMP564:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP564]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1368]]
+// SIMD-ONLY0:       if.end1368:
+// SIMD-ONLY0-NEXT:    [[TMP565:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1369:%.*]] = zext i16 [[TMP565]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP566:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1370:%.*]] = zext i16 [[TMP566]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1371:%.*]] = icmp slt i32 [[CONV1369]], [[CONV1370]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1371]], label [[IF_THEN1373:%.*]], label [[IF_END1374:%.*]]
+// SIMD-ONLY0:       if.then1373:
+// SIMD-ONLY0-NEXT:    [[TMP567:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP567]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1374]]
+// SIMD-ONLY0:       if.end1374:
+// SIMD-ONLY0-NEXT:    [[TMP568:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1375:%.*]] = zext i16 [[TMP568]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP569:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1376:%.*]] = zext i16 [[TMP569]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1377:%.*]] = icmp sgt i32 [[CONV1375]], [[CONV1376]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1377]], label [[IF_THEN1379:%.*]], label [[IF_END1380:%.*]]
+// SIMD-ONLY0:       if.then1379:
+// SIMD-ONLY0-NEXT:    [[TMP570:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP570]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1380]]
+// SIMD-ONLY0:       if.end1380:
+// SIMD-ONLY0-NEXT:    [[TMP571:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1381:%.*]] = zext i16 [[TMP571]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP572:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1382:%.*]] = zext i16 [[TMP572]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1383:%.*]] = icmp slt i32 [[CONV1381]], [[CONV1382]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1383]], label [[IF_THEN1385:%.*]], label [[IF_END1386:%.*]]
+// SIMD-ONLY0:       if.then1385:
+// SIMD-ONLY0-NEXT:    [[TMP573:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP573]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1386]]
+// SIMD-ONLY0:       if.end1386:
+// SIMD-ONLY0-NEXT:    [[TMP574:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1387:%.*]] = zext i16 [[TMP574]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP575:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1388:%.*]] = zext i16 [[TMP575]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1389:%.*]] = icmp eq i32 [[CONV1387]], [[CONV1388]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1389]], label [[COND_TRUE1391:%.*]], label [[COND_FALSE1393:%.*]]
+// SIMD-ONLY0:       cond.true1391:
+// SIMD-ONLY0-NEXT:    [[TMP576:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1392:%.*]] = zext i16 [[TMP576]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1395:%.*]]
+// SIMD-ONLY0:       cond.false1393:
+// SIMD-ONLY0-NEXT:    [[TMP577:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1394:%.*]] = zext i16 [[TMP577]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1395]]
+// SIMD-ONLY0:       cond.end1395:
+// SIMD-ONLY0-NEXT:    [[COND1396:%.*]] = phi i32 [ [[CONV1392]], [[COND_TRUE1391]] ], [ [[CONV1394]], [[COND_FALSE1393]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1397:%.*]] = trunc i32 [[COND1396]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1397]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP578:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1398:%.*]] = zext i16 [[TMP578]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP579:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1399:%.*]] = zext i16 [[TMP579]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1400:%.*]] = icmp eq i32 [[CONV1398]], [[CONV1399]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1400]], label [[COND_TRUE1402:%.*]], label [[COND_FALSE1404:%.*]]
+// SIMD-ONLY0:       cond.true1402:
+// SIMD-ONLY0-NEXT:    [[TMP580:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1403:%.*]] = zext i16 [[TMP580]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1406:%.*]]
+// SIMD-ONLY0:       cond.false1404:
+// SIMD-ONLY0-NEXT:    [[TMP581:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1405:%.*]] = zext i16 [[TMP581]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1406]]
+// SIMD-ONLY0:       cond.end1406:
+// SIMD-ONLY0-NEXT:    [[COND1407:%.*]] = phi i32 [ [[CONV1403]], [[COND_TRUE1402]] ], [ [[CONV1405]], [[COND_FALSE1404]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1408:%.*]] = trunc i32 [[COND1407]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1408]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP582:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1409:%.*]] = zext i16 [[TMP582]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP583:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1410:%.*]] = zext i16 [[TMP583]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1411:%.*]] = icmp eq i32 [[CONV1409]], [[CONV1410]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1411]], label [[IF_THEN1413:%.*]], label [[IF_END1414:%.*]]
+// SIMD-ONLY0:       if.then1413:
+// SIMD-ONLY0-NEXT:    [[TMP584:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP584]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1414]]
+// SIMD-ONLY0:       if.end1414:
+// SIMD-ONLY0-NEXT:    [[TMP585:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1415:%.*]] = zext i16 [[TMP585]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP586:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1416:%.*]] = zext i16 [[TMP586]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1417:%.*]] = icmp eq i32 [[CONV1415]], [[CONV1416]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1417]], label [[IF_THEN1419:%.*]], label [[IF_END1420:%.*]]
+// SIMD-ONLY0:       if.then1419:
+// SIMD-ONLY0-NEXT:    [[TMP587:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP587]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1420]]
+// SIMD-ONLY0:       if.end1420:
+// SIMD-ONLY0-NEXT:    [[TMP588:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1421:%.*]] = sext i16 [[TMP588]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP589:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1422:%.*]] = sext i16 [[TMP589]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1423:%.*]] = icmp sgt i32 [[CONV1421]], [[CONV1422]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1423]], label [[COND_TRUE1425:%.*]], label [[COND_FALSE1427:%.*]]
+// SIMD-ONLY0:       cond.true1425:
+// SIMD-ONLY0-NEXT:    [[TMP590:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1426:%.*]] = sext i16 [[TMP590]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1429:%.*]]
+// SIMD-ONLY0:       cond.false1427:
+// SIMD-ONLY0-NEXT:    [[TMP591:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1428:%.*]] = sext i16 [[TMP591]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1429]]
+// SIMD-ONLY0:       cond.end1429:
+// SIMD-ONLY0-NEXT:    [[COND1430:%.*]] = phi i32 [ [[CONV1426]], [[COND_TRUE1425]] ], [ [[CONV1428]], [[COND_FALSE1427]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1431:%.*]] = trunc i32 [[COND1430]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1431]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP592:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1432:%.*]] = sext i16 [[TMP592]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP593:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1433:%.*]] = sext i16 [[TMP593]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1434:%.*]] = icmp slt i32 [[CONV1432]], [[CONV1433]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1434]], label [[COND_TRUE1436:%.*]], label [[COND_FALSE1438:%.*]]
+// SIMD-ONLY0:       cond.true1436:
+// SIMD-ONLY0-NEXT:    [[TMP594:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1437:%.*]] = sext i16 [[TMP594]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1440:%.*]]
+// SIMD-ONLY0:       cond.false1438:
+// SIMD-ONLY0-NEXT:    [[TMP595:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1439:%.*]] = sext i16 [[TMP595]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1440]]
+// SIMD-ONLY0:       cond.end1440:
+// SIMD-ONLY0-NEXT:    [[COND1441:%.*]] = phi i32 [ [[CONV1437]], [[COND_TRUE1436]] ], [ [[CONV1439]], [[COND_FALSE1438]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1442:%.*]] = trunc i32 [[COND1441]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1442]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP596:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1443:%.*]] = sext i16 [[TMP596]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP597:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1444:%.*]] = sext i16 [[TMP597]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1445:%.*]] = icmp sgt i32 [[CONV1443]], [[CONV1444]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1445]], label [[COND_TRUE1447:%.*]], label [[COND_FALSE1449:%.*]]
+// SIMD-ONLY0:       cond.true1447:
+// SIMD-ONLY0-NEXT:    [[TMP598:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1448:%.*]] = sext i16 [[TMP598]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1451:%.*]]
+// SIMD-ONLY0:       cond.false1449:
+// SIMD-ONLY0-NEXT:    [[TMP599:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1450:%.*]] = sext i16 [[TMP599]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1451]]
+// SIMD-ONLY0:       cond.end1451:
+// SIMD-ONLY0-NEXT:    [[COND1452:%.*]] = phi i32 [ [[CONV1448]], [[COND_TRUE1447]] ], [ [[CONV1450]], [[COND_FALSE1449]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1453:%.*]] = trunc i32 [[COND1452]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1453]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP600:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1454:%.*]] = sext i16 [[TMP600]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP601:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1455:%.*]] = sext i16 [[TMP601]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1456:%.*]] = icmp slt i32 [[CONV1454]], [[CONV1455]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1456]], label [[COND_TRUE1458:%.*]], label [[COND_FALSE1460:%.*]]
+// SIMD-ONLY0:       cond.true1458:
+// SIMD-ONLY0-NEXT:    [[TMP602:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1459:%.*]] = sext i16 [[TMP602]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1462:%.*]]
+// SIMD-ONLY0:       cond.false1460:
+// SIMD-ONLY0-NEXT:    [[TMP603:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1461:%.*]] = sext i16 [[TMP603]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1462]]
+// SIMD-ONLY0:       cond.end1462:
+// SIMD-ONLY0-NEXT:    [[COND1463:%.*]] = phi i32 [ [[CONV1459]], [[COND_TRUE1458]] ], [ [[CONV1461]], [[COND_FALSE1460]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1464:%.*]] = trunc i32 [[COND1463]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1464]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP604:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1465:%.*]] = sext i16 [[TMP604]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP605:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1466:%.*]] = sext i16 [[TMP605]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1467:%.*]] = icmp sgt i32 [[CONV1465]], [[CONV1466]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1467]], label [[IF_THEN1469:%.*]], label [[IF_END1470:%.*]]
+// SIMD-ONLY0:       if.then1469:
+// SIMD-ONLY0-NEXT:    [[TMP606:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP606]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1470]]
+// SIMD-ONLY0:       if.end1470:
+// SIMD-ONLY0-NEXT:    [[TMP607:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1471:%.*]] = sext i16 [[TMP607]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP608:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1472:%.*]] = sext i16 [[TMP608]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1473:%.*]] = icmp slt i32 [[CONV1471]], [[CONV1472]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1473]], label [[IF_THEN1475:%.*]], label [[IF_END1476:%.*]]
+// SIMD-ONLY0:       if.then1475:
+// SIMD-ONLY0-NEXT:    [[TMP609:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP609]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1476]]
+// SIMD-ONLY0:       if.end1476:
+// SIMD-ONLY0-NEXT:    [[TMP610:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1477:%.*]] = sext i16 [[TMP610]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP611:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1478:%.*]] = sext i16 [[TMP611]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1479:%.*]] = icmp sgt i32 [[CONV1477]], [[CONV1478]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1479]], label [[IF_THEN1481:%.*]], label [[IF_END1482:%.*]]
+// SIMD-ONLY0:       if.then1481:
+// SIMD-ONLY0-NEXT:    [[TMP612:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP612]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1482]]
+// SIMD-ONLY0:       if.end1482:
+// SIMD-ONLY0-NEXT:    [[TMP613:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1483:%.*]] = sext i16 [[TMP613]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP614:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1484:%.*]] = sext i16 [[TMP614]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1485:%.*]] = icmp slt i32 [[CONV1483]], [[CONV1484]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1485]], label [[IF_THEN1487:%.*]], label [[IF_END1488:%.*]]
+// SIMD-ONLY0:       if.then1487:
+// SIMD-ONLY0-NEXT:    [[TMP615:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP615]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1488]]
+// SIMD-ONLY0:       if.end1488:
+// SIMD-ONLY0-NEXT:    [[TMP616:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1489:%.*]] = sext i16 [[TMP616]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP617:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1490:%.*]] = sext i16 [[TMP617]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1491:%.*]] = icmp eq i32 [[CONV1489]], [[CONV1490]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1491]], label [[COND_TRUE1493:%.*]], label [[COND_FALSE1495:%.*]]
+// SIMD-ONLY0:       cond.true1493:
+// SIMD-ONLY0-NEXT:    [[TMP618:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1494:%.*]] = sext i16 [[TMP618]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1497:%.*]]
+// SIMD-ONLY0:       cond.false1495:
+// SIMD-ONLY0-NEXT:    [[TMP619:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1496:%.*]] = sext i16 [[TMP619]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1497]]
+// SIMD-ONLY0:       cond.end1497:
+// SIMD-ONLY0-NEXT:    [[COND1498:%.*]] = phi i32 [ [[CONV1494]], [[COND_TRUE1493]] ], [ [[CONV1496]], [[COND_FALSE1495]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1499:%.*]] = trunc i32 [[COND1498]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1499]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP620:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1500:%.*]] = sext i16 [[TMP620]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP621:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1501:%.*]] = sext i16 [[TMP621]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1502:%.*]] = icmp eq i32 [[CONV1500]], [[CONV1501]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1502]], label [[COND_TRUE1504:%.*]], label [[COND_FALSE1506:%.*]]
+// SIMD-ONLY0:       cond.true1504:
+// SIMD-ONLY0-NEXT:    [[TMP622:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1505:%.*]] = sext i16 [[TMP622]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1508:%.*]]
+// SIMD-ONLY0:       cond.false1506:
+// SIMD-ONLY0-NEXT:    [[TMP623:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1507:%.*]] = sext i16 [[TMP623]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1508]]
+// SIMD-ONLY0:       cond.end1508:
+// SIMD-ONLY0-NEXT:    [[COND1509:%.*]] = phi i32 [ [[CONV1505]], [[COND_TRUE1504]] ], [ [[CONV1507]], [[COND_FALSE1506]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1510:%.*]] = trunc i32 [[COND1509]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1510]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP624:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1511:%.*]] = sext i16 [[TMP624]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP625:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1512:%.*]] = sext i16 [[TMP625]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1513:%.*]] = icmp eq i32 [[CONV1511]], [[CONV1512]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1513]], label [[IF_THEN1515:%.*]], label [[IF_END1516:%.*]]
+// SIMD-ONLY0:       if.then1515:
+// SIMD-ONLY0-NEXT:    [[TMP626:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP626]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1516]]
+// SIMD-ONLY0:       if.end1516:
+// SIMD-ONLY0-NEXT:    [[TMP627:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1517:%.*]] = sext i16 [[TMP627]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP628:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1518:%.*]] = sext i16 [[TMP628]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1519:%.*]] = icmp eq i32 [[CONV1517]], [[CONV1518]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1519]], label [[IF_THEN1521:%.*]], label [[IF_END1522:%.*]]
+// SIMD-ONLY0:       if.then1521:
+// SIMD-ONLY0-NEXT:    [[TMP629:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP629]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1522]]
+// SIMD-ONLY0:       if.end1522:
+// SIMD-ONLY0-NEXT:    [[TMP630:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1523:%.*]] = zext i16 [[TMP630]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP631:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1524:%.*]] = zext i16 [[TMP631]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1525:%.*]] = icmp sgt i32 [[CONV1523]], [[CONV1524]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1525]], label [[COND_TRUE1527:%.*]], label [[COND_FALSE1529:%.*]]
+// SIMD-ONLY0:       cond.true1527:
+// SIMD-ONLY0-NEXT:    [[TMP632:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1528:%.*]] = zext i16 [[TMP632]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1531:%.*]]
+// SIMD-ONLY0:       cond.false1529:
+// SIMD-ONLY0-NEXT:    [[TMP633:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1530:%.*]] = zext i16 [[TMP633]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1531]]
+// SIMD-ONLY0:       cond.end1531:
+// SIMD-ONLY0-NEXT:    [[COND1532:%.*]] = phi i32 [ [[CONV1528]], [[COND_TRUE1527]] ], [ [[CONV1530]], [[COND_FALSE1529]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1533:%.*]] = trunc i32 [[COND1532]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1533]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP634:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1534:%.*]] = zext i16 [[TMP634]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP635:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1535:%.*]] = zext i16 [[TMP635]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1536:%.*]] = icmp slt i32 [[CONV1534]], [[CONV1535]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1536]], label [[COND_TRUE1538:%.*]], label [[COND_FALSE1540:%.*]]
+// SIMD-ONLY0:       cond.true1538:
+// SIMD-ONLY0-NEXT:    [[TMP636:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1539:%.*]] = zext i16 [[TMP636]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1542:%.*]]
+// SIMD-ONLY0:       cond.false1540:
+// SIMD-ONLY0-NEXT:    [[TMP637:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1541:%.*]] = zext i16 [[TMP637]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1542]]
+// SIMD-ONLY0:       cond.end1542:
+// SIMD-ONLY0-NEXT:    [[COND1543:%.*]] = phi i32 [ [[CONV1539]], [[COND_TRUE1538]] ], [ [[CONV1541]], [[COND_FALSE1540]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1544:%.*]] = trunc i32 [[COND1543]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1544]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP638:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1545:%.*]] = zext i16 [[TMP638]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP639:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1546:%.*]] = zext i16 [[TMP639]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1547:%.*]] = icmp sgt i32 [[CONV1545]], [[CONV1546]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1547]], label [[COND_TRUE1549:%.*]], label [[COND_FALSE1551:%.*]]
+// SIMD-ONLY0:       cond.true1549:
+// SIMD-ONLY0-NEXT:    [[TMP640:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1550:%.*]] = zext i16 [[TMP640]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1553:%.*]]
+// SIMD-ONLY0:       cond.false1551:
+// SIMD-ONLY0-NEXT:    [[TMP641:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1552:%.*]] = zext i16 [[TMP641]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1553]]
+// SIMD-ONLY0:       cond.end1553:
+// SIMD-ONLY0-NEXT:    [[COND1554:%.*]] = phi i32 [ [[CONV1550]], [[COND_TRUE1549]] ], [ [[CONV1552]], [[COND_FALSE1551]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1555:%.*]] = trunc i32 [[COND1554]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1555]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP642:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1556:%.*]] = zext i16 [[TMP642]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP643:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1557:%.*]] = zext i16 [[TMP643]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1558:%.*]] = icmp slt i32 [[CONV1556]], [[CONV1557]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1558]], label [[COND_TRUE1560:%.*]], label [[COND_FALSE1562:%.*]]
+// SIMD-ONLY0:       cond.true1560:
+// SIMD-ONLY0-NEXT:    [[TMP644:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1561:%.*]] = zext i16 [[TMP644]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1564:%.*]]
+// SIMD-ONLY0:       cond.false1562:
+// SIMD-ONLY0-NEXT:    [[TMP645:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1563:%.*]] = zext i16 [[TMP645]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1564]]
+// SIMD-ONLY0:       cond.end1564:
+// SIMD-ONLY0-NEXT:    [[COND1565:%.*]] = phi i32 [ [[CONV1561]], [[COND_TRUE1560]] ], [ [[CONV1563]], [[COND_FALSE1562]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1566:%.*]] = trunc i32 [[COND1565]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1566]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP646:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1567:%.*]] = zext i16 [[TMP646]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP647:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1568:%.*]] = zext i16 [[TMP647]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1569:%.*]] = icmp sgt i32 [[CONV1567]], [[CONV1568]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1569]], label [[IF_THEN1571:%.*]], label [[IF_END1572:%.*]]
+// SIMD-ONLY0:       if.then1571:
+// SIMD-ONLY0-NEXT:    [[TMP648:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP648]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1572]]
+// SIMD-ONLY0:       if.end1572:
+// SIMD-ONLY0-NEXT:    [[TMP649:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1573:%.*]] = zext i16 [[TMP649]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP650:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1574:%.*]] = zext i16 [[TMP650]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1575:%.*]] = icmp slt i32 [[CONV1573]], [[CONV1574]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1575]], label [[IF_THEN1577:%.*]], label [[IF_END1578:%.*]]
+// SIMD-ONLY0:       if.then1577:
+// SIMD-ONLY0-NEXT:    [[TMP651:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP651]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1578]]
+// SIMD-ONLY0:       if.end1578:
+// SIMD-ONLY0-NEXT:    [[TMP652:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1579:%.*]] = zext i16 [[TMP652]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP653:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1580:%.*]] = zext i16 [[TMP653]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1581:%.*]] = icmp sgt i32 [[CONV1579]], [[CONV1580]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1581]], label [[IF_THEN1583:%.*]], label [[IF_END1584:%.*]]
+// SIMD-ONLY0:       if.then1583:
+// SIMD-ONLY0-NEXT:    [[TMP654:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP654]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1584]]
+// SIMD-ONLY0:       if.end1584:
+// SIMD-ONLY0-NEXT:    [[TMP655:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1585:%.*]] = zext i16 [[TMP655]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP656:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1586:%.*]] = zext i16 [[TMP656]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1587:%.*]] = icmp slt i32 [[CONV1585]], [[CONV1586]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1587]], label [[IF_THEN1589:%.*]], label [[IF_END1590:%.*]]
+// SIMD-ONLY0:       if.then1589:
+// SIMD-ONLY0-NEXT:    [[TMP657:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP657]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1590]]
+// SIMD-ONLY0:       if.end1590:
+// SIMD-ONLY0-NEXT:    [[TMP658:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1591:%.*]] = zext i16 [[TMP658]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP659:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1592:%.*]] = zext i16 [[TMP659]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1593:%.*]] = icmp eq i32 [[CONV1591]], [[CONV1592]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1593]], label [[COND_TRUE1595:%.*]], label [[COND_FALSE1597:%.*]]
+// SIMD-ONLY0:       cond.true1595:
+// SIMD-ONLY0-NEXT:    [[TMP660:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1596:%.*]] = zext i16 [[TMP660]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1599:%.*]]
+// SIMD-ONLY0:       cond.false1597:
+// SIMD-ONLY0-NEXT:    [[TMP661:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1598:%.*]] = zext i16 [[TMP661]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1599]]
+// SIMD-ONLY0:       cond.end1599:
+// SIMD-ONLY0-NEXT:    [[COND1600:%.*]] = phi i32 [ [[CONV1596]], [[COND_TRUE1595]] ], [ [[CONV1598]], [[COND_FALSE1597]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1601:%.*]] = trunc i32 [[COND1600]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1601]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP662:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1602:%.*]] = zext i16 [[TMP662]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP663:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1603:%.*]] = zext i16 [[TMP663]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1604:%.*]] = icmp eq i32 [[CONV1602]], [[CONV1603]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1604]], label [[COND_TRUE1606:%.*]], label [[COND_FALSE1608:%.*]]
+// SIMD-ONLY0:       cond.true1606:
+// SIMD-ONLY0-NEXT:    [[TMP664:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1607:%.*]] = zext i16 [[TMP664]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1610:%.*]]
+// SIMD-ONLY0:       cond.false1608:
+// SIMD-ONLY0-NEXT:    [[TMP665:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1609:%.*]] = zext i16 [[TMP665]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1610]]
+// SIMD-ONLY0:       cond.end1610:
+// SIMD-ONLY0-NEXT:    [[COND1611:%.*]] = phi i32 [ [[CONV1607]], [[COND_TRUE1606]] ], [ [[CONV1609]], [[COND_FALSE1608]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1612:%.*]] = trunc i32 [[COND1611]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1612]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP666:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1613:%.*]] = zext i16 [[TMP666]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP667:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1614:%.*]] = zext i16 [[TMP667]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1615:%.*]] = icmp eq i32 [[CONV1613]], [[CONV1614]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1615]], label [[IF_THEN1617:%.*]], label [[IF_END1618:%.*]]
+// SIMD-ONLY0:       if.then1617:
+// SIMD-ONLY0-NEXT:    [[TMP668:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP668]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1618]]
+// SIMD-ONLY0:       if.end1618:
+// SIMD-ONLY0-NEXT:    [[TMP669:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1619:%.*]] = zext i16 [[TMP669]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP670:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1620:%.*]] = zext i16 [[TMP670]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1621:%.*]] = icmp eq i32 [[CONV1619]], [[CONV1620]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1621]], label [[IF_THEN1623:%.*]], label [[IF_END1624:%.*]]
+// SIMD-ONLY0:       if.then1623:
+// SIMD-ONLY0-NEXT:    [[TMP671:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP671]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1624]]
+// SIMD-ONLY0:       if.end1624:
+// SIMD-ONLY0-NEXT:    [[TMP672:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1625:%.*]] = sext i16 [[TMP672]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP673:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1626:%.*]] = sext i16 [[TMP673]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1627:%.*]] = icmp sgt i32 [[CONV1625]], [[CONV1626]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1627]], label [[COND_TRUE1629:%.*]], label [[COND_FALSE1631:%.*]]
+// SIMD-ONLY0:       cond.true1629:
+// SIMD-ONLY0-NEXT:    [[TMP674:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1630:%.*]] = sext i16 [[TMP674]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1633:%.*]]
+// SIMD-ONLY0:       cond.false1631:
+// SIMD-ONLY0-NEXT:    [[TMP675:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1632:%.*]] = sext i16 [[TMP675]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1633]]
+// SIMD-ONLY0:       cond.end1633:
+// SIMD-ONLY0-NEXT:    [[COND1634:%.*]] = phi i32 [ [[CONV1630]], [[COND_TRUE1629]] ], [ [[CONV1632]], [[COND_FALSE1631]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1635:%.*]] = trunc i32 [[COND1634]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1635]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP676:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1636:%.*]] = sext i16 [[TMP676]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP677:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1637:%.*]] = sext i16 [[TMP677]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1638:%.*]] = icmp slt i32 [[CONV1636]], [[CONV1637]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1638]], label [[COND_TRUE1640:%.*]], label [[COND_FALSE1642:%.*]]
+// SIMD-ONLY0:       cond.true1640:
+// SIMD-ONLY0-NEXT:    [[TMP678:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1641:%.*]] = sext i16 [[TMP678]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1644:%.*]]
+// SIMD-ONLY0:       cond.false1642:
+// SIMD-ONLY0-NEXT:    [[TMP679:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1643:%.*]] = sext i16 [[TMP679]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1644]]
+// SIMD-ONLY0:       cond.end1644:
+// SIMD-ONLY0-NEXT:    [[COND1645:%.*]] = phi i32 [ [[CONV1641]], [[COND_TRUE1640]] ], [ [[CONV1643]], [[COND_FALSE1642]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1646:%.*]] = trunc i32 [[COND1645]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1646]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP680:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1647:%.*]] = sext i16 [[TMP680]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP681:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1648:%.*]] = sext i16 [[TMP681]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1649:%.*]] = icmp sgt i32 [[CONV1647]], [[CONV1648]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1649]], label [[COND_TRUE1651:%.*]], label [[COND_FALSE1653:%.*]]
+// SIMD-ONLY0:       cond.true1651:
+// SIMD-ONLY0-NEXT:    [[TMP682:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1652:%.*]] = sext i16 [[TMP682]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1655:%.*]]
+// SIMD-ONLY0:       cond.false1653:
+// SIMD-ONLY0-NEXT:    [[TMP683:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1654:%.*]] = sext i16 [[TMP683]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1655]]
+// SIMD-ONLY0:       cond.end1655:
+// SIMD-ONLY0-NEXT:    [[COND1656:%.*]] = phi i32 [ [[CONV1652]], [[COND_TRUE1651]] ], [ [[CONV1654]], [[COND_FALSE1653]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1657:%.*]] = trunc i32 [[COND1656]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1657]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP684:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1658:%.*]] = sext i16 [[TMP684]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP685:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1659:%.*]] = sext i16 [[TMP685]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1660:%.*]] = icmp slt i32 [[CONV1658]], [[CONV1659]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1660]], label [[COND_TRUE1662:%.*]], label [[COND_FALSE1664:%.*]]
+// SIMD-ONLY0:       cond.true1662:
+// SIMD-ONLY0-NEXT:    [[TMP686:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1663:%.*]] = sext i16 [[TMP686]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1666:%.*]]
+// SIMD-ONLY0:       cond.false1664:
+// SIMD-ONLY0-NEXT:    [[TMP687:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1665:%.*]] = sext i16 [[TMP687]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1666]]
+// SIMD-ONLY0:       cond.end1666:
+// SIMD-ONLY0-NEXT:    [[COND1667:%.*]] = phi i32 [ [[CONV1663]], [[COND_TRUE1662]] ], [ [[CONV1665]], [[COND_FALSE1664]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1668:%.*]] = trunc i32 [[COND1667]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1668]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP688:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1669:%.*]] = sext i16 [[TMP688]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP689:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1670:%.*]] = sext i16 [[TMP689]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1671:%.*]] = icmp sgt i32 [[CONV1669]], [[CONV1670]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1671]], label [[IF_THEN1673:%.*]], label [[IF_END1674:%.*]]
+// SIMD-ONLY0:       if.then1673:
+// SIMD-ONLY0-NEXT:    [[TMP690:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP690]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1674]]
+// SIMD-ONLY0:       if.end1674:
+// SIMD-ONLY0-NEXT:    [[TMP691:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1675:%.*]] = sext i16 [[TMP691]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP692:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1676:%.*]] = sext i16 [[TMP692]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1677:%.*]] = icmp slt i32 [[CONV1675]], [[CONV1676]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1677]], label [[IF_THEN1679:%.*]], label [[IF_END1680:%.*]]
+// SIMD-ONLY0:       if.then1679:
+// SIMD-ONLY0-NEXT:    [[TMP693:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP693]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1680]]
+// SIMD-ONLY0:       if.end1680:
+// SIMD-ONLY0-NEXT:    [[TMP694:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1681:%.*]] = sext i16 [[TMP694]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP695:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1682:%.*]] = sext i16 [[TMP695]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1683:%.*]] = icmp sgt i32 [[CONV1681]], [[CONV1682]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1683]], label [[IF_THEN1685:%.*]], label [[IF_END1686:%.*]]
+// SIMD-ONLY0:       if.then1685:
+// SIMD-ONLY0-NEXT:    [[TMP696:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP696]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1686]]
+// SIMD-ONLY0:       if.end1686:
+// SIMD-ONLY0-NEXT:    [[TMP697:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1687:%.*]] = sext i16 [[TMP697]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP698:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1688:%.*]] = sext i16 [[TMP698]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1689:%.*]] = icmp slt i32 [[CONV1687]], [[CONV1688]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1689]], label [[IF_THEN1691:%.*]], label [[IF_END1692:%.*]]
+// SIMD-ONLY0:       if.then1691:
+// SIMD-ONLY0-NEXT:    [[TMP699:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP699]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1692]]
+// SIMD-ONLY0:       if.end1692:
+// SIMD-ONLY0-NEXT:    [[TMP700:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1693:%.*]] = sext i16 [[TMP700]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP701:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1694:%.*]] = sext i16 [[TMP701]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1695:%.*]] = icmp eq i32 [[CONV1693]], [[CONV1694]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1695]], label [[COND_TRUE1697:%.*]], label [[COND_FALSE1699:%.*]]
+// SIMD-ONLY0:       cond.true1697:
+// SIMD-ONLY0-NEXT:    [[TMP702:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1698:%.*]] = sext i16 [[TMP702]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1701:%.*]]
+// SIMD-ONLY0:       cond.false1699:
+// SIMD-ONLY0-NEXT:    [[TMP703:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1700:%.*]] = sext i16 [[TMP703]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1701]]
+// SIMD-ONLY0:       cond.end1701:
+// SIMD-ONLY0-NEXT:    [[COND1702:%.*]] = phi i32 [ [[CONV1698]], [[COND_TRUE1697]] ], [ [[CONV1700]], [[COND_FALSE1699]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1703:%.*]] = trunc i32 [[COND1702]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1703]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP704:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1704:%.*]] = sext i16 [[TMP704]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP705:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1705:%.*]] = sext i16 [[TMP705]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1706:%.*]] = icmp eq i32 [[CONV1704]], [[CONV1705]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1706]], label [[COND_TRUE1708:%.*]], label [[COND_FALSE1710:%.*]]
+// SIMD-ONLY0:       cond.true1708:
+// SIMD-ONLY0-NEXT:    [[TMP706:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1709:%.*]] = sext i16 [[TMP706]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1712:%.*]]
+// SIMD-ONLY0:       cond.false1710:
+// SIMD-ONLY0-NEXT:    [[TMP707:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1711:%.*]] = sext i16 [[TMP707]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1712]]
+// SIMD-ONLY0:       cond.end1712:
+// SIMD-ONLY0-NEXT:    [[COND1713:%.*]] = phi i32 [ [[CONV1709]], [[COND_TRUE1708]] ], [ [[CONV1711]], [[COND_FALSE1710]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1714:%.*]] = trunc i32 [[COND1713]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1714]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP708:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1715:%.*]] = sext i16 [[TMP708]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP709:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1716:%.*]] = sext i16 [[TMP709]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1717:%.*]] = icmp eq i32 [[CONV1715]], [[CONV1716]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1717]], label [[IF_THEN1719:%.*]], label [[IF_END1720:%.*]]
+// SIMD-ONLY0:       if.then1719:
+// SIMD-ONLY0-NEXT:    [[TMP710:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP710]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1720]]
+// SIMD-ONLY0:       if.end1720:
+// SIMD-ONLY0-NEXT:    [[TMP711:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1721:%.*]] = sext i16 [[TMP711]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP712:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1722:%.*]] = sext i16 [[TMP712]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1723:%.*]] = icmp eq i32 [[CONV1721]], [[CONV1722]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1723]], label [[IF_THEN1725:%.*]], label [[IF_END1726:%.*]]
+// SIMD-ONLY0:       if.then1725:
+// SIMD-ONLY0-NEXT:    [[TMP713:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP713]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1726]]
+// SIMD-ONLY0:       if.end1726:
+// SIMD-ONLY0-NEXT:    [[TMP714:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1727:%.*]] = zext i16 [[TMP714]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP715:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1728:%.*]] = zext i16 [[TMP715]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1729:%.*]] = icmp sgt i32 [[CONV1727]], [[CONV1728]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1729]], label [[COND_TRUE1731:%.*]], label [[COND_FALSE1733:%.*]]
+// SIMD-ONLY0:       cond.true1731:
+// SIMD-ONLY0-NEXT:    [[TMP716:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1732:%.*]] = zext i16 [[TMP716]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1735:%.*]]
+// SIMD-ONLY0:       cond.false1733:
+// SIMD-ONLY0-NEXT:    [[TMP717:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1734:%.*]] = zext i16 [[TMP717]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1735]]
+// SIMD-ONLY0:       cond.end1735:
+// SIMD-ONLY0-NEXT:    [[COND1736:%.*]] = phi i32 [ [[CONV1732]], [[COND_TRUE1731]] ], [ [[CONV1734]], [[COND_FALSE1733]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1737:%.*]] = trunc i32 [[COND1736]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1737]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP718:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1738:%.*]] = zext i16 [[TMP718]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP719:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1739:%.*]] = zext i16 [[TMP719]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1740:%.*]] = icmp slt i32 [[CONV1738]], [[CONV1739]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1740]], label [[COND_TRUE1742:%.*]], label [[COND_FALSE1744:%.*]]
+// SIMD-ONLY0:       cond.true1742:
+// SIMD-ONLY0-NEXT:    [[TMP720:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1743:%.*]] = zext i16 [[TMP720]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1746:%.*]]
+// SIMD-ONLY0:       cond.false1744:
+// SIMD-ONLY0-NEXT:    [[TMP721:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1745:%.*]] = zext i16 [[TMP721]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1746]]
+// SIMD-ONLY0:       cond.end1746:
+// SIMD-ONLY0-NEXT:    [[COND1747:%.*]] = phi i32 [ [[CONV1743]], [[COND_TRUE1742]] ], [ [[CONV1745]], [[COND_FALSE1744]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1748:%.*]] = trunc i32 [[COND1747]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1748]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP722:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1749:%.*]] = zext i16 [[TMP722]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP723:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1750:%.*]] = zext i16 [[TMP723]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1751:%.*]] = icmp sgt i32 [[CONV1749]], [[CONV1750]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1751]], label [[COND_TRUE1753:%.*]], label [[COND_FALSE1755:%.*]]
+// SIMD-ONLY0:       cond.true1753:
+// SIMD-ONLY0-NEXT:    [[TMP724:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1754:%.*]] = zext i16 [[TMP724]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1757:%.*]]
+// SIMD-ONLY0:       cond.false1755:
+// SIMD-ONLY0-NEXT:    [[TMP725:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1756:%.*]] = zext i16 [[TMP725]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1757]]
+// SIMD-ONLY0:       cond.end1757:
+// SIMD-ONLY0-NEXT:    [[COND1758:%.*]] = phi i32 [ [[CONV1754]], [[COND_TRUE1753]] ], [ [[CONV1756]], [[COND_FALSE1755]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1759:%.*]] = trunc i32 [[COND1758]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1759]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP726:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1760:%.*]] = zext i16 [[TMP726]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP727:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1761:%.*]] = zext i16 [[TMP727]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1762:%.*]] = icmp slt i32 [[CONV1760]], [[CONV1761]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1762]], label [[COND_TRUE1764:%.*]], label [[COND_FALSE1766:%.*]]
+// SIMD-ONLY0:       cond.true1764:
+// SIMD-ONLY0-NEXT:    [[TMP728:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1765:%.*]] = zext i16 [[TMP728]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1768:%.*]]
+// SIMD-ONLY0:       cond.false1766:
+// SIMD-ONLY0-NEXT:    [[TMP729:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1767:%.*]] = zext i16 [[TMP729]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1768]]
+// SIMD-ONLY0:       cond.end1768:
+// SIMD-ONLY0-NEXT:    [[COND1769:%.*]] = phi i32 [ [[CONV1765]], [[COND_TRUE1764]] ], [ [[CONV1767]], [[COND_FALSE1766]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1770:%.*]] = trunc i32 [[COND1769]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1770]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP730:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1771:%.*]] = zext i16 [[TMP730]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP731:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1772:%.*]] = zext i16 [[TMP731]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1773:%.*]] = icmp sgt i32 [[CONV1771]], [[CONV1772]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1773]], label [[IF_THEN1775:%.*]], label [[IF_END1776:%.*]]
+// SIMD-ONLY0:       if.then1775:
+// SIMD-ONLY0-NEXT:    [[TMP732:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP732]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1776]]
+// SIMD-ONLY0:       if.end1776:
+// SIMD-ONLY0-NEXT:    [[TMP733:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1777:%.*]] = zext i16 [[TMP733]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP734:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1778:%.*]] = zext i16 [[TMP734]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1779:%.*]] = icmp slt i32 [[CONV1777]], [[CONV1778]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1779]], label [[IF_THEN1781:%.*]], label [[IF_END1782:%.*]]
+// SIMD-ONLY0:       if.then1781:
+// SIMD-ONLY0-NEXT:    [[TMP735:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP735]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1782]]
+// SIMD-ONLY0:       if.end1782:
+// SIMD-ONLY0-NEXT:    [[TMP736:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1783:%.*]] = zext i16 [[TMP736]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP737:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1784:%.*]] = zext i16 [[TMP737]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1785:%.*]] = icmp sgt i32 [[CONV1783]], [[CONV1784]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1785]], label [[IF_THEN1787:%.*]], label [[IF_END1788:%.*]]
+// SIMD-ONLY0:       if.then1787:
+// SIMD-ONLY0-NEXT:    [[TMP738:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP738]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1788]]
+// SIMD-ONLY0:       if.end1788:
+// SIMD-ONLY0-NEXT:    [[TMP739:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1789:%.*]] = zext i16 [[TMP739]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP740:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1790:%.*]] = zext i16 [[TMP740]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1791:%.*]] = icmp slt i32 [[CONV1789]], [[CONV1790]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1791]], label [[IF_THEN1793:%.*]], label [[IF_END1794:%.*]]
+// SIMD-ONLY0:       if.then1793:
+// SIMD-ONLY0-NEXT:    [[TMP741:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP741]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1794]]
+// SIMD-ONLY0:       if.end1794:
+// SIMD-ONLY0-NEXT:    [[TMP742:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1795:%.*]] = zext i16 [[TMP742]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP743:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1796:%.*]] = zext i16 [[TMP743]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1797:%.*]] = icmp eq i32 [[CONV1795]], [[CONV1796]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1797]], label [[COND_TRUE1799:%.*]], label [[COND_FALSE1801:%.*]]
+// SIMD-ONLY0:       cond.true1799:
+// SIMD-ONLY0-NEXT:    [[TMP744:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1800:%.*]] = zext i16 [[TMP744]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1803:%.*]]
+// SIMD-ONLY0:       cond.false1801:
+// SIMD-ONLY0-NEXT:    [[TMP745:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1802:%.*]] = zext i16 [[TMP745]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1803]]
+// SIMD-ONLY0:       cond.end1803:
+// SIMD-ONLY0-NEXT:    [[COND1804:%.*]] = phi i32 [ [[CONV1800]], [[COND_TRUE1799]] ], [ [[CONV1802]], [[COND_FALSE1801]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1805:%.*]] = trunc i32 [[COND1804]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1805]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP746:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1806:%.*]] = zext i16 [[TMP746]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP747:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1807:%.*]] = zext i16 [[TMP747]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1808:%.*]] = icmp eq i32 [[CONV1806]], [[CONV1807]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1808]], label [[COND_TRUE1810:%.*]], label [[COND_FALSE1812:%.*]]
+// SIMD-ONLY0:       cond.true1810:
+// SIMD-ONLY0-NEXT:    [[TMP748:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1811:%.*]] = zext i16 [[TMP748]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1814:%.*]]
+// SIMD-ONLY0:       cond.false1812:
+// SIMD-ONLY0-NEXT:    [[TMP749:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1813:%.*]] = zext i16 [[TMP749]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1814]]
+// SIMD-ONLY0:       cond.end1814:
+// SIMD-ONLY0-NEXT:    [[COND1815:%.*]] = phi i32 [ [[CONV1811]], [[COND_TRUE1810]] ], [ [[CONV1813]], [[COND_FALSE1812]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1816:%.*]] = trunc i32 [[COND1815]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1816]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP750:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1817:%.*]] = zext i16 [[TMP750]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP751:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1818:%.*]] = zext i16 [[TMP751]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1819:%.*]] = icmp eq i32 [[CONV1817]], [[CONV1818]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1819]], label [[IF_THEN1821:%.*]], label [[IF_END1822:%.*]]
+// SIMD-ONLY0:       if.then1821:
+// SIMD-ONLY0-NEXT:    [[TMP752:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP752]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1822]]
+// SIMD-ONLY0:       if.end1822:
+// SIMD-ONLY0-NEXT:    [[TMP753:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1823:%.*]] = zext i16 [[TMP753]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP754:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1824:%.*]] = zext i16 [[TMP754]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1825:%.*]] = icmp eq i32 [[CONV1823]], [[CONV1824]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1825]], label [[IF_THEN1827:%.*]], label [[IF_END1828:%.*]]
+// SIMD-ONLY0:       if.then1827:
+// SIMD-ONLY0-NEXT:    [[TMP755:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP755]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1828]]
+// SIMD-ONLY0:       if.end1828:
+// SIMD-ONLY0-NEXT:    [[TMP756:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1829:%.*]] = sext i16 [[TMP756]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP757:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1830:%.*]] = sext i16 [[TMP757]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1831:%.*]] = icmp sgt i32 [[CONV1829]], [[CONV1830]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1831]], label [[COND_TRUE1833:%.*]], label [[COND_FALSE1835:%.*]]
+// SIMD-ONLY0:       cond.true1833:
+// SIMD-ONLY0-NEXT:    [[TMP758:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1834:%.*]] = sext i16 [[TMP758]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1837:%.*]]
+// SIMD-ONLY0:       cond.false1835:
+// SIMD-ONLY0-NEXT:    [[TMP759:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1836:%.*]] = sext i16 [[TMP759]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1837]]
+// SIMD-ONLY0:       cond.end1837:
+// SIMD-ONLY0-NEXT:    [[COND1838:%.*]] = phi i32 [ [[CONV1834]], [[COND_TRUE1833]] ], [ [[CONV1836]], [[COND_FALSE1835]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1839:%.*]] = trunc i32 [[COND1838]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1839]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP760:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1840:%.*]] = sext i16 [[TMP760]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP761:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1841:%.*]] = sext i16 [[TMP761]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1842:%.*]] = icmp slt i32 [[CONV1840]], [[CONV1841]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1842]], label [[COND_TRUE1844:%.*]], label [[COND_FALSE1846:%.*]]
+// SIMD-ONLY0:       cond.true1844:
+// SIMD-ONLY0-NEXT:    [[TMP762:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1845:%.*]] = sext i16 [[TMP762]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1848:%.*]]
+// SIMD-ONLY0:       cond.false1846:
+// SIMD-ONLY0-NEXT:    [[TMP763:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1847:%.*]] = sext i16 [[TMP763]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1848]]
+// SIMD-ONLY0:       cond.end1848:
+// SIMD-ONLY0-NEXT:    [[COND1849:%.*]] = phi i32 [ [[CONV1845]], [[COND_TRUE1844]] ], [ [[CONV1847]], [[COND_FALSE1846]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1850:%.*]] = trunc i32 [[COND1849]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1850]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP764:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1851:%.*]] = sext i16 [[TMP764]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP765:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1852:%.*]] = sext i16 [[TMP765]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1853:%.*]] = icmp sgt i32 [[CONV1851]], [[CONV1852]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1853]], label [[COND_TRUE1855:%.*]], label [[COND_FALSE1857:%.*]]
+// SIMD-ONLY0:       cond.true1855:
+// SIMD-ONLY0-NEXT:    [[TMP766:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1856:%.*]] = sext i16 [[TMP766]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1859:%.*]]
+// SIMD-ONLY0:       cond.false1857:
+// SIMD-ONLY0-NEXT:    [[TMP767:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1858:%.*]] = sext i16 [[TMP767]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1859]]
+// SIMD-ONLY0:       cond.end1859:
+// SIMD-ONLY0-NEXT:    [[COND1860:%.*]] = phi i32 [ [[CONV1856]], [[COND_TRUE1855]] ], [ [[CONV1858]], [[COND_FALSE1857]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1861:%.*]] = trunc i32 [[COND1860]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1861]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP768:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1862:%.*]] = sext i16 [[TMP768]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP769:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1863:%.*]] = sext i16 [[TMP769]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1864:%.*]] = icmp slt i32 [[CONV1862]], [[CONV1863]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1864]], label [[COND_TRUE1866:%.*]], label [[COND_FALSE1868:%.*]]
+// SIMD-ONLY0:       cond.true1866:
+// SIMD-ONLY0-NEXT:    [[TMP770:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1867:%.*]] = sext i16 [[TMP770]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1870:%.*]]
+// SIMD-ONLY0:       cond.false1868:
+// SIMD-ONLY0-NEXT:    [[TMP771:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1869:%.*]] = sext i16 [[TMP771]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1870]]
+// SIMD-ONLY0:       cond.end1870:
+// SIMD-ONLY0-NEXT:    [[COND1871:%.*]] = phi i32 [ [[CONV1867]], [[COND_TRUE1866]] ], [ [[CONV1869]], [[COND_FALSE1868]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1872:%.*]] = trunc i32 [[COND1871]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1872]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP772:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1873:%.*]] = sext i16 [[TMP772]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP773:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1874:%.*]] = sext i16 [[TMP773]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1875:%.*]] = icmp sgt i32 [[CONV1873]], [[CONV1874]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1875]], label [[IF_THEN1877:%.*]], label [[IF_END1878:%.*]]
+// SIMD-ONLY0:       if.then1877:
+// SIMD-ONLY0-NEXT:    [[TMP774:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP774]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1878]]
+// SIMD-ONLY0:       if.end1878:
+// SIMD-ONLY0-NEXT:    [[TMP775:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1879:%.*]] = sext i16 [[TMP775]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP776:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1880:%.*]] = sext i16 [[TMP776]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1881:%.*]] = icmp slt i32 [[CONV1879]], [[CONV1880]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1881]], label [[IF_THEN1883:%.*]], label [[IF_END1884:%.*]]
+// SIMD-ONLY0:       if.then1883:
+// SIMD-ONLY0-NEXT:    [[TMP777:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP777]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1884]]
+// SIMD-ONLY0:       if.end1884:
+// SIMD-ONLY0-NEXT:    [[TMP778:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1885:%.*]] = sext i16 [[TMP778]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP779:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1886:%.*]] = sext i16 [[TMP779]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1887:%.*]] = icmp sgt i32 [[CONV1885]], [[CONV1886]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1887]], label [[IF_THEN1889:%.*]], label [[IF_END1890:%.*]]
+// SIMD-ONLY0:       if.then1889:
+// SIMD-ONLY0-NEXT:    [[TMP780:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP780]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1890]]
+// SIMD-ONLY0:       if.end1890:
+// SIMD-ONLY0-NEXT:    [[TMP781:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1891:%.*]] = sext i16 [[TMP781]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP782:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1892:%.*]] = sext i16 [[TMP782]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1893:%.*]] = icmp slt i32 [[CONV1891]], [[CONV1892]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1893]], label [[IF_THEN1895:%.*]], label [[IF_END1896:%.*]]
+// SIMD-ONLY0:       if.then1895:
+// SIMD-ONLY0-NEXT:    [[TMP783:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP783]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1896]]
+// SIMD-ONLY0:       if.end1896:
+// SIMD-ONLY0-NEXT:    [[TMP784:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1897:%.*]] = sext i16 [[TMP784]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP785:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1898:%.*]] = sext i16 [[TMP785]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1899:%.*]] = icmp eq i32 [[CONV1897]], [[CONV1898]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1899]], label [[COND_TRUE1901:%.*]], label [[COND_FALSE1903:%.*]]
+// SIMD-ONLY0:       cond.true1901:
+// SIMD-ONLY0-NEXT:    [[TMP786:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1902:%.*]] = sext i16 [[TMP786]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1905:%.*]]
+// SIMD-ONLY0:       cond.false1903:
+// SIMD-ONLY0-NEXT:    [[TMP787:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1904:%.*]] = sext i16 [[TMP787]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1905]]
+// SIMD-ONLY0:       cond.end1905:
+// SIMD-ONLY0-NEXT:    [[COND1906:%.*]] = phi i32 [ [[CONV1902]], [[COND_TRUE1901]] ], [ [[CONV1904]], [[COND_FALSE1903]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1907:%.*]] = trunc i32 [[COND1906]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1907]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP788:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1908:%.*]] = sext i16 [[TMP788]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP789:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1909:%.*]] = sext i16 [[TMP789]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1910:%.*]] = icmp eq i32 [[CONV1908]], [[CONV1909]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1910]], label [[COND_TRUE1912:%.*]], label [[COND_FALSE1914:%.*]]
+// SIMD-ONLY0:       cond.true1912:
+// SIMD-ONLY0-NEXT:    [[TMP790:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1913:%.*]] = sext i16 [[TMP790]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1916:%.*]]
+// SIMD-ONLY0:       cond.false1914:
+// SIMD-ONLY0-NEXT:    [[TMP791:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1915:%.*]] = sext i16 [[TMP791]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1916]]
+// SIMD-ONLY0:       cond.end1916:
+// SIMD-ONLY0-NEXT:    [[COND1917:%.*]] = phi i32 [ [[CONV1913]], [[COND_TRUE1912]] ], [ [[CONV1915]], [[COND_FALSE1914]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1918:%.*]] = trunc i32 [[COND1917]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1918]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP792:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1919:%.*]] = sext i16 [[TMP792]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP793:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1920:%.*]] = sext i16 [[TMP793]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1921:%.*]] = icmp eq i32 [[CONV1919]], [[CONV1920]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1921]], label [[IF_THEN1923:%.*]], label [[IF_END1924:%.*]]
+// SIMD-ONLY0:       if.then1923:
+// SIMD-ONLY0-NEXT:    [[TMP794:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP794]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1924]]
+// SIMD-ONLY0:       if.end1924:
+// SIMD-ONLY0-NEXT:    [[TMP795:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1925:%.*]] = sext i16 [[TMP795]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP796:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1926:%.*]] = sext i16 [[TMP796]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1927:%.*]] = icmp eq i32 [[CONV1925]], [[CONV1926]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1927]], label [[IF_THEN1929:%.*]], label [[IF_END1930:%.*]]
+// SIMD-ONLY0:       if.then1929:
+// SIMD-ONLY0-NEXT:    [[TMP797:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP797]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1930]]
+// SIMD-ONLY0:       if.end1930:
+// SIMD-ONLY0-NEXT:    [[TMP798:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1931:%.*]] = zext i16 [[TMP798]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP799:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1932:%.*]] = zext i16 [[TMP799]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1933:%.*]] = icmp sgt i32 [[CONV1931]], [[CONV1932]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1933]], label [[COND_TRUE1935:%.*]], label [[COND_FALSE1937:%.*]]
+// SIMD-ONLY0:       cond.true1935:
+// SIMD-ONLY0-NEXT:    [[TMP800:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1936:%.*]] = zext i16 [[TMP800]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1939:%.*]]
+// SIMD-ONLY0:       cond.false1937:
+// SIMD-ONLY0-NEXT:    [[TMP801:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1938:%.*]] = zext i16 [[TMP801]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1939]]
+// SIMD-ONLY0:       cond.end1939:
+// SIMD-ONLY0-NEXT:    [[COND1940:%.*]] = phi i32 [ [[CONV1936]], [[COND_TRUE1935]] ], [ [[CONV1938]], [[COND_FALSE1937]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1941:%.*]] = trunc i32 [[COND1940]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1941]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP802:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1942:%.*]] = zext i16 [[TMP802]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP803:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1943:%.*]] = zext i16 [[TMP803]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1944:%.*]] = icmp slt i32 [[CONV1942]], [[CONV1943]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1944]], label [[COND_TRUE1946:%.*]], label [[COND_FALSE1948:%.*]]
+// SIMD-ONLY0:       cond.true1946:
+// SIMD-ONLY0-NEXT:    [[TMP804:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1947:%.*]] = zext i16 [[TMP804]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1950:%.*]]
+// SIMD-ONLY0:       cond.false1948:
+// SIMD-ONLY0-NEXT:    [[TMP805:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1949:%.*]] = zext i16 [[TMP805]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1950]]
+// SIMD-ONLY0:       cond.end1950:
+// SIMD-ONLY0-NEXT:    [[COND1951:%.*]] = phi i32 [ [[CONV1947]], [[COND_TRUE1946]] ], [ [[CONV1949]], [[COND_FALSE1948]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1952:%.*]] = trunc i32 [[COND1951]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1952]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP806:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1953:%.*]] = zext i16 [[TMP806]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP807:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1954:%.*]] = zext i16 [[TMP807]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1955:%.*]] = icmp sgt i32 [[CONV1953]], [[CONV1954]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1955]], label [[COND_TRUE1957:%.*]], label [[COND_FALSE1959:%.*]]
+// SIMD-ONLY0:       cond.true1957:
+// SIMD-ONLY0-NEXT:    [[TMP808:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1958:%.*]] = zext i16 [[TMP808]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1961:%.*]]
+// SIMD-ONLY0:       cond.false1959:
+// SIMD-ONLY0-NEXT:    [[TMP809:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1960:%.*]] = zext i16 [[TMP809]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1961]]
+// SIMD-ONLY0:       cond.end1961:
+// SIMD-ONLY0-NEXT:    [[COND1962:%.*]] = phi i32 [ [[CONV1958]], [[COND_TRUE1957]] ], [ [[CONV1960]], [[COND_FALSE1959]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1963:%.*]] = trunc i32 [[COND1962]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1963]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP810:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1964:%.*]] = zext i16 [[TMP810]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP811:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1965:%.*]] = zext i16 [[TMP811]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1966:%.*]] = icmp slt i32 [[CONV1964]], [[CONV1965]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1966]], label [[COND_TRUE1968:%.*]], label [[COND_FALSE1970:%.*]]
+// SIMD-ONLY0:       cond.true1968:
+// SIMD-ONLY0-NEXT:    [[TMP812:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1969:%.*]] = zext i16 [[TMP812]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1972:%.*]]
+// SIMD-ONLY0:       cond.false1970:
+// SIMD-ONLY0-NEXT:    [[TMP813:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1971:%.*]] = zext i16 [[TMP813]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END1972]]
+// SIMD-ONLY0:       cond.end1972:
+// SIMD-ONLY0-NEXT:    [[COND1973:%.*]] = phi i32 [ [[CONV1969]], [[COND_TRUE1968]] ], [ [[CONV1971]], [[COND_FALSE1970]] ]
+// SIMD-ONLY0-NEXT:    [[CONV1974:%.*]] = trunc i32 [[COND1973]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV1974]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP814:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1975:%.*]] = zext i16 [[TMP814]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP815:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1976:%.*]] = zext i16 [[TMP815]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1977:%.*]] = icmp sgt i32 [[CONV1975]], [[CONV1976]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1977]], label [[IF_THEN1979:%.*]], label [[IF_END1980:%.*]]
+// SIMD-ONLY0:       if.then1979:
+// SIMD-ONLY0-NEXT:    [[TMP816:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP816]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1980]]
+// SIMD-ONLY0:       if.end1980:
+// SIMD-ONLY0-NEXT:    [[TMP817:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1981:%.*]] = zext i16 [[TMP817]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP818:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1982:%.*]] = zext i16 [[TMP818]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1983:%.*]] = icmp slt i32 [[CONV1981]], [[CONV1982]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1983]], label [[IF_THEN1985:%.*]], label [[IF_END1986:%.*]]
+// SIMD-ONLY0:       if.then1985:
+// SIMD-ONLY0-NEXT:    [[TMP819:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP819]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1986]]
+// SIMD-ONLY0:       if.end1986:
+// SIMD-ONLY0-NEXT:    [[TMP820:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1987:%.*]] = zext i16 [[TMP820]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP821:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1988:%.*]] = zext i16 [[TMP821]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1989:%.*]] = icmp sgt i32 [[CONV1987]], [[CONV1988]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1989]], label [[IF_THEN1991:%.*]], label [[IF_END1992:%.*]]
+// SIMD-ONLY0:       if.then1991:
+// SIMD-ONLY0-NEXT:    [[TMP822:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP822]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1992]]
+// SIMD-ONLY0:       if.end1992:
+// SIMD-ONLY0-NEXT:    [[TMP823:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1993:%.*]] = zext i16 [[TMP823]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP824:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1994:%.*]] = zext i16 [[TMP824]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP1995:%.*]] = icmp slt i32 [[CONV1993]], [[CONV1994]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP1995]], label [[IF_THEN1997:%.*]], label [[IF_END1998:%.*]]
+// SIMD-ONLY0:       if.then1997:
+// SIMD-ONLY0-NEXT:    [[TMP825:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP825]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END1998]]
+// SIMD-ONLY0:       if.end1998:
+// SIMD-ONLY0-NEXT:    [[TMP826:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV1999:%.*]] = zext i16 [[TMP826]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP827:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2000:%.*]] = zext i16 [[TMP827]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2001:%.*]] = icmp eq i32 [[CONV1999]], [[CONV2000]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2001]], label [[COND_TRUE2003:%.*]], label [[COND_FALSE2005:%.*]]
+// SIMD-ONLY0:       cond.true2003:
+// SIMD-ONLY0-NEXT:    [[TMP828:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2004:%.*]] = zext i16 [[TMP828]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2007:%.*]]
+// SIMD-ONLY0:       cond.false2005:
+// SIMD-ONLY0-NEXT:    [[TMP829:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2006:%.*]] = zext i16 [[TMP829]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2007]]
+// SIMD-ONLY0:       cond.end2007:
+// SIMD-ONLY0-NEXT:    [[COND2008:%.*]] = phi i32 [ [[CONV2004]], [[COND_TRUE2003]] ], [ [[CONV2006]], [[COND_FALSE2005]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2009:%.*]] = trunc i32 [[COND2008]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2009]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP830:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2010:%.*]] = zext i16 [[TMP830]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP831:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2011:%.*]] = zext i16 [[TMP831]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2012:%.*]] = icmp eq i32 [[CONV2010]], [[CONV2011]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2012]], label [[COND_TRUE2014:%.*]], label [[COND_FALSE2016:%.*]]
+// SIMD-ONLY0:       cond.true2014:
+// SIMD-ONLY0-NEXT:    [[TMP832:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2015:%.*]] = zext i16 [[TMP832]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2018:%.*]]
+// SIMD-ONLY0:       cond.false2016:
+// SIMD-ONLY0-NEXT:    [[TMP833:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2017:%.*]] = zext i16 [[TMP833]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2018]]
+// SIMD-ONLY0:       cond.end2018:
+// SIMD-ONLY0-NEXT:    [[COND2019:%.*]] = phi i32 [ [[CONV2015]], [[COND_TRUE2014]] ], [ [[CONV2017]], [[COND_FALSE2016]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2020:%.*]] = trunc i32 [[COND2019]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2020]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP834:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2021:%.*]] = zext i16 [[TMP834]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP835:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2022:%.*]] = zext i16 [[TMP835]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2023:%.*]] = icmp eq i32 [[CONV2021]], [[CONV2022]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2023]], label [[IF_THEN2025:%.*]], label [[IF_END2026:%.*]]
+// SIMD-ONLY0:       if.then2025:
+// SIMD-ONLY0-NEXT:    [[TMP836:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP836]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2026]]
+// SIMD-ONLY0:       if.end2026:
+// SIMD-ONLY0-NEXT:    [[TMP837:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2027:%.*]] = zext i16 [[TMP837]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP838:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2028:%.*]] = zext i16 [[TMP838]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2029:%.*]] = icmp eq i32 [[CONV2027]], [[CONV2028]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2029]], label [[IF_THEN2031:%.*]], label [[IF_END2032:%.*]]
+// SIMD-ONLY0:       if.then2031:
+// SIMD-ONLY0-NEXT:    [[TMP839:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP839]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2032]]
+// SIMD-ONLY0:       if.end2032:
+// SIMD-ONLY0-NEXT:    [[TMP840:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2033:%.*]] = sext i16 [[TMP840]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP841:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2034:%.*]] = sext i16 [[TMP841]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2035:%.*]] = icmp sgt i32 [[CONV2033]], [[CONV2034]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2035]], label [[COND_TRUE2037:%.*]], label [[COND_FALSE2039:%.*]]
+// SIMD-ONLY0:       cond.true2037:
+// SIMD-ONLY0-NEXT:    [[TMP842:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2038:%.*]] = sext i16 [[TMP842]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2041:%.*]]
+// SIMD-ONLY0:       cond.false2039:
+// SIMD-ONLY0-NEXT:    [[TMP843:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2040:%.*]] = sext i16 [[TMP843]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2041]]
+// SIMD-ONLY0:       cond.end2041:
+// SIMD-ONLY0-NEXT:    [[COND2042:%.*]] = phi i32 [ [[CONV2038]], [[COND_TRUE2037]] ], [ [[CONV2040]], [[COND_FALSE2039]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2043:%.*]] = trunc i32 [[COND2042]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2043]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP844:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2044:%.*]] = sext i16 [[TMP844]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP845:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2045:%.*]] = sext i16 [[TMP845]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2046:%.*]] = icmp slt i32 [[CONV2044]], [[CONV2045]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2046]], label [[COND_TRUE2048:%.*]], label [[COND_FALSE2050:%.*]]
+// SIMD-ONLY0:       cond.true2048:
+// SIMD-ONLY0-NEXT:    [[TMP846:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2049:%.*]] = sext i16 [[TMP846]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2052:%.*]]
+// SIMD-ONLY0:       cond.false2050:
+// SIMD-ONLY0-NEXT:    [[TMP847:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2051:%.*]] = sext i16 [[TMP847]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2052]]
+// SIMD-ONLY0:       cond.end2052:
+// SIMD-ONLY0-NEXT:    [[COND2053:%.*]] = phi i32 [ [[CONV2049]], [[COND_TRUE2048]] ], [ [[CONV2051]], [[COND_FALSE2050]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2054:%.*]] = trunc i32 [[COND2053]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2054]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP848:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2055:%.*]] = sext i16 [[TMP848]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP849:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2056:%.*]] = sext i16 [[TMP849]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2057:%.*]] = icmp sgt i32 [[CONV2055]], [[CONV2056]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2057]], label [[COND_TRUE2059:%.*]], label [[COND_FALSE2061:%.*]]
+// SIMD-ONLY0:       cond.true2059:
+// SIMD-ONLY0-NEXT:    [[TMP850:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2060:%.*]] = sext i16 [[TMP850]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2063:%.*]]
+// SIMD-ONLY0:       cond.false2061:
+// SIMD-ONLY0-NEXT:    [[TMP851:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2062:%.*]] = sext i16 [[TMP851]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2063]]
+// SIMD-ONLY0:       cond.end2063:
+// SIMD-ONLY0-NEXT:    [[COND2064:%.*]] = phi i32 [ [[CONV2060]], [[COND_TRUE2059]] ], [ [[CONV2062]], [[COND_FALSE2061]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2065:%.*]] = trunc i32 [[COND2064]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2065]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP852:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2066:%.*]] = sext i16 [[TMP852]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP853:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2067:%.*]] = sext i16 [[TMP853]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2068:%.*]] = icmp slt i32 [[CONV2066]], [[CONV2067]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2068]], label [[COND_TRUE2070:%.*]], label [[COND_FALSE2072:%.*]]
+// SIMD-ONLY0:       cond.true2070:
+// SIMD-ONLY0-NEXT:    [[TMP854:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2071:%.*]] = sext i16 [[TMP854]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2074:%.*]]
+// SIMD-ONLY0:       cond.false2072:
+// SIMD-ONLY0-NEXT:    [[TMP855:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2073:%.*]] = sext i16 [[TMP855]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2074]]
+// SIMD-ONLY0:       cond.end2074:
+// SIMD-ONLY0-NEXT:    [[COND2075:%.*]] = phi i32 [ [[CONV2071]], [[COND_TRUE2070]] ], [ [[CONV2073]], [[COND_FALSE2072]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2076:%.*]] = trunc i32 [[COND2075]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2076]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP856:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2077:%.*]] = sext i16 [[TMP856]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP857:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2078:%.*]] = sext i16 [[TMP857]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2079:%.*]] = icmp sgt i32 [[CONV2077]], [[CONV2078]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2079]], label [[IF_THEN2081:%.*]], label [[IF_END2082:%.*]]
+// SIMD-ONLY0:       if.then2081:
+// SIMD-ONLY0-NEXT:    [[TMP858:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP858]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2082]]
+// SIMD-ONLY0:       if.end2082:
+// SIMD-ONLY0-NEXT:    [[TMP859:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2083:%.*]] = sext i16 [[TMP859]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP860:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2084:%.*]] = sext i16 [[TMP860]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2085:%.*]] = icmp slt i32 [[CONV2083]], [[CONV2084]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2085]], label [[IF_THEN2087:%.*]], label [[IF_END2088:%.*]]
+// SIMD-ONLY0:       if.then2087:
+// SIMD-ONLY0-NEXT:    [[TMP861:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP861]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2088]]
+// SIMD-ONLY0:       if.end2088:
+// SIMD-ONLY0-NEXT:    [[TMP862:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2089:%.*]] = sext i16 [[TMP862]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP863:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2090:%.*]] = sext i16 [[TMP863]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2091:%.*]] = icmp sgt i32 [[CONV2089]], [[CONV2090]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2091]], label [[IF_THEN2093:%.*]], label [[IF_END2094:%.*]]
+// SIMD-ONLY0:       if.then2093:
+// SIMD-ONLY0-NEXT:    [[TMP864:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP864]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2094]]
+// SIMD-ONLY0:       if.end2094:
+// SIMD-ONLY0-NEXT:    [[TMP865:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2095:%.*]] = sext i16 [[TMP865]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP866:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2096:%.*]] = sext i16 [[TMP866]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2097:%.*]] = icmp slt i32 [[CONV2095]], [[CONV2096]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2097]], label [[IF_THEN2099:%.*]], label [[IF_END2100:%.*]]
+// SIMD-ONLY0:       if.then2099:
+// SIMD-ONLY0-NEXT:    [[TMP867:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP867]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2100]]
+// SIMD-ONLY0:       if.end2100:
+// SIMD-ONLY0-NEXT:    [[TMP868:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2101:%.*]] = sext i16 [[TMP868]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP869:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2102:%.*]] = sext i16 [[TMP869]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2103:%.*]] = icmp eq i32 [[CONV2101]], [[CONV2102]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2103]], label [[COND_TRUE2105:%.*]], label [[COND_FALSE2107:%.*]]
+// SIMD-ONLY0:       cond.true2105:
+// SIMD-ONLY0-NEXT:    [[TMP870:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2106:%.*]] = sext i16 [[TMP870]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2109:%.*]]
+// SIMD-ONLY0:       cond.false2107:
+// SIMD-ONLY0-NEXT:    [[TMP871:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2108:%.*]] = sext i16 [[TMP871]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2109]]
+// SIMD-ONLY0:       cond.end2109:
+// SIMD-ONLY0-NEXT:    [[COND2110:%.*]] = phi i32 [ [[CONV2106]], [[COND_TRUE2105]] ], [ [[CONV2108]], [[COND_FALSE2107]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2111:%.*]] = trunc i32 [[COND2110]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2111]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP872:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2112:%.*]] = sext i16 [[TMP872]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP873:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2113:%.*]] = sext i16 [[TMP873]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2114:%.*]] = icmp eq i32 [[CONV2112]], [[CONV2113]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2114]], label [[COND_TRUE2116:%.*]], label [[COND_FALSE2118:%.*]]
+// SIMD-ONLY0:       cond.true2116:
+// SIMD-ONLY0-NEXT:    [[TMP874:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2117:%.*]] = sext i16 [[TMP874]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2120:%.*]]
+// SIMD-ONLY0:       cond.false2118:
+// SIMD-ONLY0-NEXT:    [[TMP875:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2119:%.*]] = sext i16 [[TMP875]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2120]]
+// SIMD-ONLY0:       cond.end2120:
+// SIMD-ONLY0-NEXT:    [[COND2121:%.*]] = phi i32 [ [[CONV2117]], [[COND_TRUE2116]] ], [ [[CONV2119]], [[COND_FALSE2118]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2122:%.*]] = trunc i32 [[COND2121]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2122]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP876:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2123:%.*]] = sext i16 [[TMP876]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP877:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2124:%.*]] = sext i16 [[TMP877]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2125:%.*]] = icmp eq i32 [[CONV2123]], [[CONV2124]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2125]], label [[IF_THEN2127:%.*]], label [[IF_END2128:%.*]]
+// SIMD-ONLY0:       if.then2127:
+// SIMD-ONLY0-NEXT:    [[TMP878:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP878]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2128]]
+// SIMD-ONLY0:       if.end2128:
+// SIMD-ONLY0-NEXT:    [[TMP879:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2129:%.*]] = sext i16 [[TMP879]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP880:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2130:%.*]] = sext i16 [[TMP880]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2131:%.*]] = icmp eq i32 [[CONV2129]], [[CONV2130]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2131]], label [[IF_THEN2133:%.*]], label [[IF_END2134:%.*]]
+// SIMD-ONLY0:       if.then2133:
+// SIMD-ONLY0-NEXT:    [[TMP881:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP881]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2134]]
+// SIMD-ONLY0:       if.end2134:
+// SIMD-ONLY0-NEXT:    [[TMP882:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2135:%.*]] = zext i16 [[TMP882]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP883:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2136:%.*]] = zext i16 [[TMP883]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2137:%.*]] = icmp sgt i32 [[CONV2135]], [[CONV2136]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2137]], label [[COND_TRUE2139:%.*]], label [[COND_FALSE2141:%.*]]
+// SIMD-ONLY0:       cond.true2139:
+// SIMD-ONLY0-NEXT:    [[TMP884:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2140:%.*]] = zext i16 [[TMP884]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2143:%.*]]
+// SIMD-ONLY0:       cond.false2141:
+// SIMD-ONLY0-NEXT:    [[TMP885:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2142:%.*]] = zext i16 [[TMP885]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2143]]
+// SIMD-ONLY0:       cond.end2143:
+// SIMD-ONLY0-NEXT:    [[COND2144:%.*]] = phi i32 [ [[CONV2140]], [[COND_TRUE2139]] ], [ [[CONV2142]], [[COND_FALSE2141]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2145:%.*]] = trunc i32 [[COND2144]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2145]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP886:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2146:%.*]] = zext i16 [[TMP886]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP887:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2147:%.*]] = zext i16 [[TMP887]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2148:%.*]] = icmp slt i32 [[CONV2146]], [[CONV2147]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2148]], label [[COND_TRUE2150:%.*]], label [[COND_FALSE2152:%.*]]
+// SIMD-ONLY0:       cond.true2150:
+// SIMD-ONLY0-NEXT:    [[TMP888:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2151:%.*]] = zext i16 [[TMP888]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2154:%.*]]
+// SIMD-ONLY0:       cond.false2152:
+// SIMD-ONLY0-NEXT:    [[TMP889:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2153:%.*]] = zext i16 [[TMP889]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2154]]
+// SIMD-ONLY0:       cond.end2154:
+// SIMD-ONLY0-NEXT:    [[COND2155:%.*]] = phi i32 [ [[CONV2151]], [[COND_TRUE2150]] ], [ [[CONV2153]], [[COND_FALSE2152]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2156:%.*]] = trunc i32 [[COND2155]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2156]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP890:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2157:%.*]] = zext i16 [[TMP890]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP891:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2158:%.*]] = zext i16 [[TMP891]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2159:%.*]] = icmp sgt i32 [[CONV2157]], [[CONV2158]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2159]], label [[COND_TRUE2161:%.*]], label [[COND_FALSE2163:%.*]]
+// SIMD-ONLY0:       cond.true2161:
+// SIMD-ONLY0-NEXT:    [[TMP892:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2162:%.*]] = zext i16 [[TMP892]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2165:%.*]]
+// SIMD-ONLY0:       cond.false2163:
+// SIMD-ONLY0-NEXT:    [[TMP893:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2164:%.*]] = zext i16 [[TMP893]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2165]]
+// SIMD-ONLY0:       cond.end2165:
+// SIMD-ONLY0-NEXT:    [[COND2166:%.*]] = phi i32 [ [[CONV2162]], [[COND_TRUE2161]] ], [ [[CONV2164]], [[COND_FALSE2163]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2167:%.*]] = trunc i32 [[COND2166]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2167]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP894:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2168:%.*]] = zext i16 [[TMP894]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP895:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2169:%.*]] = zext i16 [[TMP895]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2170:%.*]] = icmp slt i32 [[CONV2168]], [[CONV2169]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2170]], label [[COND_TRUE2172:%.*]], label [[COND_FALSE2174:%.*]]
+// SIMD-ONLY0:       cond.true2172:
+// SIMD-ONLY0-NEXT:    [[TMP896:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2173:%.*]] = zext i16 [[TMP896]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2176:%.*]]
+// SIMD-ONLY0:       cond.false2174:
+// SIMD-ONLY0-NEXT:    [[TMP897:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2175:%.*]] = zext i16 [[TMP897]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2176]]
+// SIMD-ONLY0:       cond.end2176:
+// SIMD-ONLY0-NEXT:    [[COND2177:%.*]] = phi i32 [ [[CONV2173]], [[COND_TRUE2172]] ], [ [[CONV2175]], [[COND_FALSE2174]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2178:%.*]] = trunc i32 [[COND2177]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2178]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP898:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2179:%.*]] = zext i16 [[TMP898]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP899:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2180:%.*]] = zext i16 [[TMP899]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2181:%.*]] = icmp sgt i32 [[CONV2179]], [[CONV2180]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2181]], label [[IF_THEN2183:%.*]], label [[IF_END2184:%.*]]
+// SIMD-ONLY0:       if.then2183:
+// SIMD-ONLY0-NEXT:    [[TMP900:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP900]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2184]]
+// SIMD-ONLY0:       if.end2184:
+// SIMD-ONLY0-NEXT:    [[TMP901:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2185:%.*]] = zext i16 [[TMP901]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP902:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2186:%.*]] = zext i16 [[TMP902]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2187:%.*]] = icmp slt i32 [[CONV2185]], [[CONV2186]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2187]], label [[IF_THEN2189:%.*]], label [[IF_END2190:%.*]]
+// SIMD-ONLY0:       if.then2189:
+// SIMD-ONLY0-NEXT:    [[TMP903:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP903]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2190]]
+// SIMD-ONLY0:       if.end2190:
+// SIMD-ONLY0-NEXT:    [[TMP904:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2191:%.*]] = zext i16 [[TMP904]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP905:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2192:%.*]] = zext i16 [[TMP905]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2193:%.*]] = icmp sgt i32 [[CONV2191]], [[CONV2192]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2193]], label [[IF_THEN2195:%.*]], label [[IF_END2196:%.*]]
+// SIMD-ONLY0:       if.then2195:
+// SIMD-ONLY0-NEXT:    [[TMP906:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP906]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2196]]
+// SIMD-ONLY0:       if.end2196:
+// SIMD-ONLY0-NEXT:    [[TMP907:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2197:%.*]] = zext i16 [[TMP907]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP908:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2198:%.*]] = zext i16 [[TMP908]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2199:%.*]] = icmp slt i32 [[CONV2197]], [[CONV2198]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2199]], label [[IF_THEN2201:%.*]], label [[IF_END2202:%.*]]
+// SIMD-ONLY0:       if.then2201:
+// SIMD-ONLY0-NEXT:    [[TMP909:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP909]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2202]]
+// SIMD-ONLY0:       if.end2202:
+// SIMD-ONLY0-NEXT:    [[TMP910:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2203:%.*]] = zext i16 [[TMP910]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP911:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2204:%.*]] = zext i16 [[TMP911]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2205:%.*]] = icmp eq i32 [[CONV2203]], [[CONV2204]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2205]], label [[COND_TRUE2207:%.*]], label [[COND_FALSE2209:%.*]]
+// SIMD-ONLY0:       cond.true2207:
+// SIMD-ONLY0-NEXT:    [[TMP912:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2208:%.*]] = zext i16 [[TMP912]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2211:%.*]]
+// SIMD-ONLY0:       cond.false2209:
+// SIMD-ONLY0-NEXT:    [[TMP913:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2210:%.*]] = zext i16 [[TMP913]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2211]]
+// SIMD-ONLY0:       cond.end2211:
+// SIMD-ONLY0-NEXT:    [[COND2212:%.*]] = phi i32 [ [[CONV2208]], [[COND_TRUE2207]] ], [ [[CONV2210]], [[COND_FALSE2209]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2213:%.*]] = trunc i32 [[COND2212]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2213]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP914:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2214:%.*]] = zext i16 [[TMP914]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP915:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2215:%.*]] = zext i16 [[TMP915]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2216:%.*]] = icmp eq i32 [[CONV2214]], [[CONV2215]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2216]], label [[COND_TRUE2218:%.*]], label [[COND_FALSE2220:%.*]]
+// SIMD-ONLY0:       cond.true2218:
+// SIMD-ONLY0-NEXT:    [[TMP916:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2219:%.*]] = zext i16 [[TMP916]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2222:%.*]]
+// SIMD-ONLY0:       cond.false2220:
+// SIMD-ONLY0-NEXT:    [[TMP917:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2221:%.*]] = zext i16 [[TMP917]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2222]]
+// SIMD-ONLY0:       cond.end2222:
+// SIMD-ONLY0-NEXT:    [[COND2223:%.*]] = phi i32 [ [[CONV2219]], [[COND_TRUE2218]] ], [ [[CONV2221]], [[COND_FALSE2220]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2224:%.*]] = trunc i32 [[COND2223]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2224]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP918:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2225:%.*]] = zext i16 [[TMP918]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP919:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2226:%.*]] = zext i16 [[TMP919]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2227:%.*]] = icmp eq i32 [[CONV2225]], [[CONV2226]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2227]], label [[IF_THEN2229:%.*]], label [[IF_END2230:%.*]]
+// SIMD-ONLY0:       if.then2229:
+// SIMD-ONLY0-NEXT:    [[TMP920:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP920]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2230]]
+// SIMD-ONLY0:       if.end2230:
+// SIMD-ONLY0-NEXT:    [[TMP921:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2231:%.*]] = zext i16 [[TMP921]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP922:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2232:%.*]] = zext i16 [[TMP922]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2233:%.*]] = icmp eq i32 [[CONV2231]], [[CONV2232]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2233]], label [[IF_THEN2235:%.*]], label [[IF_END2236:%.*]]
+// SIMD-ONLY0:       if.then2235:
+// SIMD-ONLY0-NEXT:    [[TMP923:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP923]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2236]]
+// SIMD-ONLY0:       if.end2236:
+// SIMD-ONLY0-NEXT:    [[TMP924:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2237:%.*]] = sext i16 [[TMP924]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP925:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2238:%.*]] = sext i16 [[TMP925]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2239:%.*]] = icmp sgt i32 [[CONV2237]], [[CONV2238]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2239]], label [[COND_TRUE2241:%.*]], label [[COND_FALSE2243:%.*]]
+// SIMD-ONLY0:       cond.true2241:
+// SIMD-ONLY0-NEXT:    [[TMP926:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2242:%.*]] = sext i16 [[TMP926]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2245:%.*]]
+// SIMD-ONLY0:       cond.false2243:
+// SIMD-ONLY0-NEXT:    [[TMP927:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2244:%.*]] = sext i16 [[TMP927]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2245]]
+// SIMD-ONLY0:       cond.end2245:
+// SIMD-ONLY0-NEXT:    [[COND2246:%.*]] = phi i32 [ [[CONV2242]], [[COND_TRUE2241]] ], [ [[CONV2244]], [[COND_FALSE2243]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2247:%.*]] = trunc i32 [[COND2246]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2247]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP928:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2248:%.*]] = sext i16 [[TMP928]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP929:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2249:%.*]] = sext i16 [[TMP929]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2250:%.*]] = icmp slt i32 [[CONV2248]], [[CONV2249]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2250]], label [[COND_TRUE2252:%.*]], label [[COND_FALSE2254:%.*]]
+// SIMD-ONLY0:       cond.true2252:
+// SIMD-ONLY0-NEXT:    [[TMP930:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2253:%.*]] = sext i16 [[TMP930]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2256:%.*]]
+// SIMD-ONLY0:       cond.false2254:
+// SIMD-ONLY0-NEXT:    [[TMP931:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2255:%.*]] = sext i16 [[TMP931]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2256]]
+// SIMD-ONLY0:       cond.end2256:
+// SIMD-ONLY0-NEXT:    [[COND2257:%.*]] = phi i32 [ [[CONV2253]], [[COND_TRUE2252]] ], [ [[CONV2255]], [[COND_FALSE2254]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2258:%.*]] = trunc i32 [[COND2257]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2258]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP932:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2259:%.*]] = sext i16 [[TMP932]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP933:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2260:%.*]] = sext i16 [[TMP933]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2261:%.*]] = icmp sgt i32 [[CONV2259]], [[CONV2260]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2261]], label [[COND_TRUE2263:%.*]], label [[COND_FALSE2265:%.*]]
+// SIMD-ONLY0:       cond.true2263:
+// SIMD-ONLY0-NEXT:    [[TMP934:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2264:%.*]] = sext i16 [[TMP934]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2267:%.*]]
+// SIMD-ONLY0:       cond.false2265:
+// SIMD-ONLY0-NEXT:    [[TMP935:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2266:%.*]] = sext i16 [[TMP935]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2267]]
+// SIMD-ONLY0:       cond.end2267:
+// SIMD-ONLY0-NEXT:    [[COND2268:%.*]] = phi i32 [ [[CONV2264]], [[COND_TRUE2263]] ], [ [[CONV2266]], [[COND_FALSE2265]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2269:%.*]] = trunc i32 [[COND2268]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2269]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP936:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2270:%.*]] = sext i16 [[TMP936]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP937:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2271:%.*]] = sext i16 [[TMP937]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2272:%.*]] = icmp slt i32 [[CONV2270]], [[CONV2271]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2272]], label [[COND_TRUE2274:%.*]], label [[COND_FALSE2276:%.*]]
+// SIMD-ONLY0:       cond.true2274:
+// SIMD-ONLY0-NEXT:    [[TMP938:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2275:%.*]] = sext i16 [[TMP938]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2278:%.*]]
+// SIMD-ONLY0:       cond.false2276:
+// SIMD-ONLY0-NEXT:    [[TMP939:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2277:%.*]] = sext i16 [[TMP939]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2278]]
+// SIMD-ONLY0:       cond.end2278:
+// SIMD-ONLY0-NEXT:    [[COND2279:%.*]] = phi i32 [ [[CONV2275]], [[COND_TRUE2274]] ], [ [[CONV2277]], [[COND_FALSE2276]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2280:%.*]] = trunc i32 [[COND2279]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2280]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP940:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2281:%.*]] = sext i16 [[TMP940]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP941:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2282:%.*]] = sext i16 [[TMP941]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2283:%.*]] = icmp sgt i32 [[CONV2281]], [[CONV2282]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2283]], label [[IF_THEN2285:%.*]], label [[IF_END2286:%.*]]
+// SIMD-ONLY0:       if.then2285:
+// SIMD-ONLY0-NEXT:    [[TMP942:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP942]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2286]]
+// SIMD-ONLY0:       if.end2286:
+// SIMD-ONLY0-NEXT:    [[TMP943:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2287:%.*]] = sext i16 [[TMP943]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP944:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2288:%.*]] = sext i16 [[TMP944]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2289:%.*]] = icmp slt i32 [[CONV2287]], [[CONV2288]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2289]], label [[IF_THEN2291:%.*]], label [[IF_END2292:%.*]]
+// SIMD-ONLY0:       if.then2291:
+// SIMD-ONLY0-NEXT:    [[TMP945:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP945]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2292]]
+// SIMD-ONLY0:       if.end2292:
+// SIMD-ONLY0-NEXT:    [[TMP946:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2293:%.*]] = sext i16 [[TMP946]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP947:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2294:%.*]] = sext i16 [[TMP947]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2295:%.*]] = icmp sgt i32 [[CONV2293]], [[CONV2294]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2295]], label [[IF_THEN2297:%.*]], label [[IF_END2298:%.*]]
+// SIMD-ONLY0:       if.then2297:
+// SIMD-ONLY0-NEXT:    [[TMP948:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP948]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2298]]
+// SIMD-ONLY0:       if.end2298:
+// SIMD-ONLY0-NEXT:    [[TMP949:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2299:%.*]] = sext i16 [[TMP949]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP950:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2300:%.*]] = sext i16 [[TMP950]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2301:%.*]] = icmp slt i32 [[CONV2299]], [[CONV2300]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2301]], label [[IF_THEN2303:%.*]], label [[IF_END2304:%.*]]
+// SIMD-ONLY0:       if.then2303:
+// SIMD-ONLY0-NEXT:    [[TMP951:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP951]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2304]]
+// SIMD-ONLY0:       if.end2304:
+// SIMD-ONLY0-NEXT:    [[TMP952:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2305:%.*]] = sext i16 [[TMP952]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP953:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2306:%.*]] = sext i16 [[TMP953]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2307:%.*]] = icmp eq i32 [[CONV2305]], [[CONV2306]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2307]], label [[COND_TRUE2309:%.*]], label [[COND_FALSE2311:%.*]]
+// SIMD-ONLY0:       cond.true2309:
+// SIMD-ONLY0-NEXT:    [[TMP954:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2310:%.*]] = sext i16 [[TMP954]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2313:%.*]]
+// SIMD-ONLY0:       cond.false2311:
+// SIMD-ONLY0-NEXT:    [[TMP955:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2312:%.*]] = sext i16 [[TMP955]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2313]]
+// SIMD-ONLY0:       cond.end2313:
+// SIMD-ONLY0-NEXT:    [[COND2314:%.*]] = phi i32 [ [[CONV2310]], [[COND_TRUE2309]] ], [ [[CONV2312]], [[COND_FALSE2311]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2315:%.*]] = trunc i32 [[COND2314]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2315]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP956:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2316:%.*]] = sext i16 [[TMP956]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP957:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2317:%.*]] = sext i16 [[TMP957]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2318:%.*]] = icmp eq i32 [[CONV2316]], [[CONV2317]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2318]], label [[COND_TRUE2320:%.*]], label [[COND_FALSE2322:%.*]]
+// SIMD-ONLY0:       cond.true2320:
+// SIMD-ONLY0-NEXT:    [[TMP958:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2321:%.*]] = sext i16 [[TMP958]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2324:%.*]]
+// SIMD-ONLY0:       cond.false2322:
+// SIMD-ONLY0-NEXT:    [[TMP959:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2323:%.*]] = sext i16 [[TMP959]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2324]]
+// SIMD-ONLY0:       cond.end2324:
+// SIMD-ONLY0-NEXT:    [[COND2325:%.*]] = phi i32 [ [[CONV2321]], [[COND_TRUE2320]] ], [ [[CONV2323]], [[COND_FALSE2322]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2326:%.*]] = trunc i32 [[COND2325]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2326]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP960:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2327:%.*]] = sext i16 [[TMP960]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP961:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2328:%.*]] = sext i16 [[TMP961]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2329:%.*]] = icmp eq i32 [[CONV2327]], [[CONV2328]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2329]], label [[IF_THEN2331:%.*]], label [[IF_END2332:%.*]]
+// SIMD-ONLY0:       if.then2331:
+// SIMD-ONLY0-NEXT:    [[TMP962:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP962]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2332]]
+// SIMD-ONLY0:       if.end2332:
+// SIMD-ONLY0-NEXT:    [[TMP963:%.*]] = load i16, i16* [[SE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2333:%.*]] = sext i16 [[TMP963]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP964:%.*]] = load i16, i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2334:%.*]] = sext i16 [[TMP964]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2335:%.*]] = icmp eq i32 [[CONV2333]], [[CONV2334]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2335]], label [[IF_THEN2337:%.*]], label [[IF_END2338:%.*]]
+// SIMD-ONLY0:       if.then2337:
+// SIMD-ONLY0-NEXT:    [[TMP965:%.*]] = load i16, i16* [[SD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP965]], i16* [[SX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2338]]
+// SIMD-ONLY0:       if.end2338:
+// SIMD-ONLY0-NEXT:    [[TMP966:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2339:%.*]] = zext i16 [[TMP966]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP967:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2340:%.*]] = zext i16 [[TMP967]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2341:%.*]] = icmp sgt i32 [[CONV2339]], [[CONV2340]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2341]], label [[COND_TRUE2343:%.*]], label [[COND_FALSE2345:%.*]]
+// SIMD-ONLY0:       cond.true2343:
+// SIMD-ONLY0-NEXT:    [[TMP968:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2344:%.*]] = zext i16 [[TMP968]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2347:%.*]]
+// SIMD-ONLY0:       cond.false2345:
+// SIMD-ONLY0-NEXT:    [[TMP969:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2346:%.*]] = zext i16 [[TMP969]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2347]]
+// SIMD-ONLY0:       cond.end2347:
+// SIMD-ONLY0-NEXT:    [[COND2348:%.*]] = phi i32 [ [[CONV2344]], [[COND_TRUE2343]] ], [ [[CONV2346]], [[COND_FALSE2345]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2349:%.*]] = trunc i32 [[COND2348]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2349]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP970:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2350:%.*]] = zext i16 [[TMP970]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP971:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2351:%.*]] = zext i16 [[TMP971]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2352:%.*]] = icmp slt i32 [[CONV2350]], [[CONV2351]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2352]], label [[COND_TRUE2354:%.*]], label [[COND_FALSE2356:%.*]]
+// SIMD-ONLY0:       cond.true2354:
+// SIMD-ONLY0-NEXT:    [[TMP972:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2355:%.*]] = zext i16 [[TMP972]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2358:%.*]]
+// SIMD-ONLY0:       cond.false2356:
+// SIMD-ONLY0-NEXT:    [[TMP973:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2357:%.*]] = zext i16 [[TMP973]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2358]]
+// SIMD-ONLY0:       cond.end2358:
+// SIMD-ONLY0-NEXT:    [[COND2359:%.*]] = phi i32 [ [[CONV2355]], [[COND_TRUE2354]] ], [ [[CONV2357]], [[COND_FALSE2356]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2360:%.*]] = trunc i32 [[COND2359]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2360]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP974:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2361:%.*]] = zext i16 [[TMP974]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP975:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2362:%.*]] = zext i16 [[TMP975]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2363:%.*]] = icmp sgt i32 [[CONV2361]], [[CONV2362]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2363]], label [[COND_TRUE2365:%.*]], label [[COND_FALSE2367:%.*]]
+// SIMD-ONLY0:       cond.true2365:
+// SIMD-ONLY0-NEXT:    [[TMP976:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2366:%.*]] = zext i16 [[TMP976]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2369:%.*]]
+// SIMD-ONLY0:       cond.false2367:
+// SIMD-ONLY0-NEXT:    [[TMP977:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2368:%.*]] = zext i16 [[TMP977]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2369]]
+// SIMD-ONLY0:       cond.end2369:
+// SIMD-ONLY0-NEXT:    [[COND2370:%.*]] = phi i32 [ [[CONV2366]], [[COND_TRUE2365]] ], [ [[CONV2368]], [[COND_FALSE2367]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2371:%.*]] = trunc i32 [[COND2370]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2371]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP978:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2372:%.*]] = zext i16 [[TMP978]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP979:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2373:%.*]] = zext i16 [[TMP979]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2374:%.*]] = icmp slt i32 [[CONV2372]], [[CONV2373]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2374]], label [[COND_TRUE2376:%.*]], label [[COND_FALSE2378:%.*]]
+// SIMD-ONLY0:       cond.true2376:
+// SIMD-ONLY0-NEXT:    [[TMP980:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2377:%.*]] = zext i16 [[TMP980]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2380:%.*]]
+// SIMD-ONLY0:       cond.false2378:
+// SIMD-ONLY0-NEXT:    [[TMP981:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2379:%.*]] = zext i16 [[TMP981]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2380]]
+// SIMD-ONLY0:       cond.end2380:
+// SIMD-ONLY0-NEXT:    [[COND2381:%.*]] = phi i32 [ [[CONV2377]], [[COND_TRUE2376]] ], [ [[CONV2379]], [[COND_FALSE2378]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2382:%.*]] = trunc i32 [[COND2381]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2382]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP982:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2383:%.*]] = zext i16 [[TMP982]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP983:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2384:%.*]] = zext i16 [[TMP983]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2385:%.*]] = icmp sgt i32 [[CONV2383]], [[CONV2384]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2385]], label [[IF_THEN2387:%.*]], label [[IF_END2388:%.*]]
+// SIMD-ONLY0:       if.then2387:
+// SIMD-ONLY0-NEXT:    [[TMP984:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP984]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2388]]
+// SIMD-ONLY0:       if.end2388:
+// SIMD-ONLY0-NEXT:    [[TMP985:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2389:%.*]] = zext i16 [[TMP985]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP986:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2390:%.*]] = zext i16 [[TMP986]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2391:%.*]] = icmp slt i32 [[CONV2389]], [[CONV2390]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2391]], label [[IF_THEN2393:%.*]], label [[IF_END2394:%.*]]
+// SIMD-ONLY0:       if.then2393:
+// SIMD-ONLY0-NEXT:    [[TMP987:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP987]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2394]]
+// SIMD-ONLY0:       if.end2394:
+// SIMD-ONLY0-NEXT:    [[TMP988:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2395:%.*]] = zext i16 [[TMP988]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP989:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2396:%.*]] = zext i16 [[TMP989]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2397:%.*]] = icmp sgt i32 [[CONV2395]], [[CONV2396]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2397]], label [[IF_THEN2399:%.*]], label [[IF_END2400:%.*]]
+// SIMD-ONLY0:       if.then2399:
+// SIMD-ONLY0-NEXT:    [[TMP990:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP990]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2400]]
+// SIMD-ONLY0:       if.end2400:
+// SIMD-ONLY0-NEXT:    [[TMP991:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2401:%.*]] = zext i16 [[TMP991]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP992:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2402:%.*]] = zext i16 [[TMP992]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2403:%.*]] = icmp slt i32 [[CONV2401]], [[CONV2402]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2403]], label [[IF_THEN2405:%.*]], label [[IF_END2406:%.*]]
+// SIMD-ONLY0:       if.then2405:
+// SIMD-ONLY0-NEXT:    [[TMP993:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP993]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2406]]
+// SIMD-ONLY0:       if.end2406:
+// SIMD-ONLY0-NEXT:    [[TMP994:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2407:%.*]] = zext i16 [[TMP994]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP995:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2408:%.*]] = zext i16 [[TMP995]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2409:%.*]] = icmp eq i32 [[CONV2407]], [[CONV2408]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2409]], label [[COND_TRUE2411:%.*]], label [[COND_FALSE2413:%.*]]
+// SIMD-ONLY0:       cond.true2411:
+// SIMD-ONLY0-NEXT:    [[TMP996:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2412:%.*]] = zext i16 [[TMP996]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2415:%.*]]
+// SIMD-ONLY0:       cond.false2413:
+// SIMD-ONLY0-NEXT:    [[TMP997:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2414:%.*]] = zext i16 [[TMP997]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2415]]
+// SIMD-ONLY0:       cond.end2415:
+// SIMD-ONLY0-NEXT:    [[COND2416:%.*]] = phi i32 [ [[CONV2412]], [[COND_TRUE2411]] ], [ [[CONV2414]], [[COND_FALSE2413]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2417:%.*]] = trunc i32 [[COND2416]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2417]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP998:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2418:%.*]] = zext i16 [[TMP998]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP999:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2419:%.*]] = zext i16 [[TMP999]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2420:%.*]] = icmp eq i32 [[CONV2418]], [[CONV2419]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2420]], label [[COND_TRUE2422:%.*]], label [[COND_FALSE2424:%.*]]
+// SIMD-ONLY0:       cond.true2422:
+// SIMD-ONLY0-NEXT:    [[TMP1000:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2423:%.*]] = zext i16 [[TMP1000]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2426:%.*]]
+// SIMD-ONLY0:       cond.false2424:
+// SIMD-ONLY0-NEXT:    [[TMP1001:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2425:%.*]] = zext i16 [[TMP1001]] to i32
+// SIMD-ONLY0-NEXT:    br label [[COND_END2426]]
+// SIMD-ONLY0:       cond.end2426:
+// SIMD-ONLY0-NEXT:    [[COND2427:%.*]] = phi i32 [ [[CONV2423]], [[COND_TRUE2422]] ], [ [[CONV2425]], [[COND_FALSE2424]] ]
+// SIMD-ONLY0-NEXT:    [[CONV2428:%.*]] = trunc i32 [[COND2427]] to i16
+// SIMD-ONLY0-NEXT:    store i16 [[CONV2428]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[TMP1002:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2429:%.*]] = zext i16 [[TMP1002]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP1003:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2430:%.*]] = zext i16 [[TMP1003]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2431:%.*]] = icmp eq i32 [[CONV2429]], [[CONV2430]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2431]], label [[IF_THEN2433:%.*]], label [[IF_END2434:%.*]]
+// SIMD-ONLY0:       if.then2433:
+// SIMD-ONLY0-NEXT:    [[TMP1004:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP1004]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2434]]
+// SIMD-ONLY0:       if.end2434:
+// SIMD-ONLY0-NEXT:    [[TMP1005:%.*]] = load i16, i16* [[USE]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2435:%.*]] = zext i16 [[TMP1005]] to i32
+// SIMD-ONLY0-NEXT:    [[TMP1006:%.*]] = load i16, i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    [[CONV2436:%.*]] = zext i16 [[TMP1006]] to i32
+// SIMD-ONLY0-NEXT:    [[CMP2437:%.*]] = icmp eq i32 [[CONV2435]], [[CONV2436]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2437]], label [[IF_THEN2439:%.*]], label [[IF_END2440:%.*]]
+// SIMD-ONLY0:       if.then2439:
+// SIMD-ONLY0-NEXT:    [[TMP1007:%.*]] = load i16, i16* [[USD]], align 2
+// SIMD-ONLY0-NEXT:    store i16 [[TMP1007]], i16* [[USX]], align 2
+// SIMD-ONLY0-NEXT:    br label [[IF_END2440]]
+// SIMD-ONLY0:       if.end2440:
+// SIMD-ONLY0-NEXT:    [[TMP1008:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1009:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2441:%.*]] = icmp sgt i32 [[TMP1008]], [[TMP1009]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2441]], label [[COND_TRUE2443:%.*]], label [[COND_FALSE2444:%.*]]
+// SIMD-ONLY0:       cond.true2443:
+// SIMD-ONLY0-NEXT:    [[TMP1010:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2445:%.*]]
+// SIMD-ONLY0:       cond.false2444:
+// SIMD-ONLY0-NEXT:    [[TMP1011:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2445]]
+// SIMD-ONLY0:       cond.end2445:
+// SIMD-ONLY0-NEXT:    [[COND2446:%.*]] = phi i32 [ [[TMP1010]], [[COND_TRUE2443]] ], [ [[TMP1011]], [[COND_FALSE2444]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2446]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1012:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1013:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2447:%.*]] = icmp slt i32 [[TMP1012]], [[TMP1013]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2447]], label [[COND_TRUE2449:%.*]], label [[COND_FALSE2450:%.*]]
+// SIMD-ONLY0:       cond.true2449:
+// SIMD-ONLY0-NEXT:    [[TMP1014:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2451:%.*]]
+// SIMD-ONLY0:       cond.false2450:
+// SIMD-ONLY0-NEXT:    [[TMP1015:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2451]]
+// SIMD-ONLY0:       cond.end2451:
+// SIMD-ONLY0-NEXT:    [[COND2452:%.*]] = phi i32 [ [[TMP1014]], [[COND_TRUE2449]] ], [ [[TMP1015]], [[COND_FALSE2450]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2452]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1016:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1017:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2453:%.*]] = icmp sgt i32 [[TMP1016]], [[TMP1017]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2453]], label [[COND_TRUE2455:%.*]], label [[COND_FALSE2456:%.*]]
+// SIMD-ONLY0:       cond.true2455:
+// SIMD-ONLY0-NEXT:    [[TMP1018:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2457:%.*]]
+// SIMD-ONLY0:       cond.false2456:
+// SIMD-ONLY0-NEXT:    [[TMP1019:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2457]]
+// SIMD-ONLY0:       cond.end2457:
+// SIMD-ONLY0-NEXT:    [[COND2458:%.*]] = phi i32 [ [[TMP1018]], [[COND_TRUE2455]] ], [ [[TMP1019]], [[COND_FALSE2456]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2458]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1020:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1021:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2459:%.*]] = icmp slt i32 [[TMP1020]], [[TMP1021]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2459]], label [[COND_TRUE2461:%.*]], label [[COND_FALSE2462:%.*]]
+// SIMD-ONLY0:       cond.true2461:
+// SIMD-ONLY0-NEXT:    [[TMP1022:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2463:%.*]]
+// SIMD-ONLY0:       cond.false2462:
+// SIMD-ONLY0-NEXT:    [[TMP1023:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2463]]
+// SIMD-ONLY0:       cond.end2463:
+// SIMD-ONLY0-NEXT:    [[COND2464:%.*]] = phi i32 [ [[TMP1022]], [[COND_TRUE2461]] ], [ [[TMP1023]], [[COND_FALSE2462]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2464]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1024:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1025:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2465:%.*]] = icmp sgt i32 [[TMP1024]], [[TMP1025]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2465]], label [[IF_THEN2467:%.*]], label [[IF_END2468:%.*]]
+// SIMD-ONLY0:       if.then2467:
+// SIMD-ONLY0-NEXT:    [[TMP1026:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1026]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2468]]
+// SIMD-ONLY0:       if.end2468:
+// SIMD-ONLY0-NEXT:    [[TMP1027:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1028:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2469:%.*]] = icmp slt i32 [[TMP1027]], [[TMP1028]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2469]], label [[IF_THEN2471:%.*]], label [[IF_END2472:%.*]]
+// SIMD-ONLY0:       if.then2471:
+// SIMD-ONLY0-NEXT:    [[TMP1029:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1029]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2472]]
+// SIMD-ONLY0:       if.end2472:
+// SIMD-ONLY0-NEXT:    [[TMP1030:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1031:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2473:%.*]] = icmp sgt i32 [[TMP1030]], [[TMP1031]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2473]], label [[IF_THEN2475:%.*]], label [[IF_END2476:%.*]]
+// SIMD-ONLY0:       if.then2475:
+// SIMD-ONLY0-NEXT:    [[TMP1032:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1032]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2476]]
+// SIMD-ONLY0:       if.end2476:
+// SIMD-ONLY0-NEXT:    [[TMP1033:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1034:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2477:%.*]] = icmp slt i32 [[TMP1033]], [[TMP1034]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2477]], label [[IF_THEN2479:%.*]], label [[IF_END2480:%.*]]
+// SIMD-ONLY0:       if.then2479:
+// SIMD-ONLY0-NEXT:    [[TMP1035:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1035]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2480]]
+// SIMD-ONLY0:       if.end2480:
+// SIMD-ONLY0-NEXT:    [[TMP1036:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1037:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2481:%.*]] = icmp eq i32 [[TMP1036]], [[TMP1037]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2481]], label [[COND_TRUE2483:%.*]], label [[COND_FALSE2484:%.*]]
+// SIMD-ONLY0:       cond.true2483:
+// SIMD-ONLY0-NEXT:    [[TMP1038:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2485:%.*]]
+// SIMD-ONLY0:       cond.false2484:
+// SIMD-ONLY0-NEXT:    [[TMP1039:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2485]]
+// SIMD-ONLY0:       cond.end2485:
+// SIMD-ONLY0-NEXT:    [[COND2486:%.*]] = phi i32 [ [[TMP1038]], [[COND_TRUE2483]] ], [ [[TMP1039]], [[COND_FALSE2484]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2486]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1040:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1041:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2487:%.*]] = icmp eq i32 [[TMP1040]], [[TMP1041]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2487]], label [[COND_TRUE2489:%.*]], label [[COND_FALSE2490:%.*]]
+// SIMD-ONLY0:       cond.true2489:
+// SIMD-ONLY0-NEXT:    [[TMP1042:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2491:%.*]]
+// SIMD-ONLY0:       cond.false2490:
+// SIMD-ONLY0-NEXT:    [[TMP1043:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2491]]
+// SIMD-ONLY0:       cond.end2491:
+// SIMD-ONLY0-NEXT:    [[COND2492:%.*]] = phi i32 [ [[TMP1042]], [[COND_TRUE2489]] ], [ [[TMP1043]], [[COND_FALSE2490]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2492]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1044:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1045:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2493:%.*]] = icmp eq i32 [[TMP1044]], [[TMP1045]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2493]], label [[IF_THEN2495:%.*]], label [[IF_END2496:%.*]]
+// SIMD-ONLY0:       if.then2495:
+// SIMD-ONLY0-NEXT:    [[TMP1046:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1046]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2496]]
+// SIMD-ONLY0:       if.end2496:
+// SIMD-ONLY0-NEXT:    [[TMP1047:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1048:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2497:%.*]] = icmp eq i32 [[TMP1047]], [[TMP1048]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2497]], label [[IF_THEN2499:%.*]], label [[IF_END2500:%.*]]
+// SIMD-ONLY0:       if.then2499:
+// SIMD-ONLY0-NEXT:    [[TMP1049:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1049]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2500]]
+// SIMD-ONLY0:       if.end2500:
+// SIMD-ONLY0-NEXT:    [[TMP1050:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1051:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2501:%.*]] = icmp ugt i32 [[TMP1050]], [[TMP1051]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2501]], label [[COND_TRUE2503:%.*]], label [[COND_FALSE2504:%.*]]
+// SIMD-ONLY0:       cond.true2503:
+// SIMD-ONLY0-NEXT:    [[TMP1052:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2505:%.*]]
+// SIMD-ONLY0:       cond.false2504:
+// SIMD-ONLY0-NEXT:    [[TMP1053:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2505]]
+// SIMD-ONLY0:       cond.end2505:
+// SIMD-ONLY0-NEXT:    [[COND2506:%.*]] = phi i32 [ [[TMP1052]], [[COND_TRUE2503]] ], [ [[TMP1053]], [[COND_FALSE2504]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2506]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1054:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1055:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2507:%.*]] = icmp ult i32 [[TMP1054]], [[TMP1055]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2507]], label [[COND_TRUE2509:%.*]], label [[COND_FALSE2510:%.*]]
+// SIMD-ONLY0:       cond.true2509:
+// SIMD-ONLY0-NEXT:    [[TMP1056:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2511:%.*]]
+// SIMD-ONLY0:       cond.false2510:
+// SIMD-ONLY0-NEXT:    [[TMP1057:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2511]]
+// SIMD-ONLY0:       cond.end2511:
+// SIMD-ONLY0-NEXT:    [[COND2512:%.*]] = phi i32 [ [[TMP1056]], [[COND_TRUE2509]] ], [ [[TMP1057]], [[COND_FALSE2510]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2512]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1058:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1059:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2513:%.*]] = icmp ugt i32 [[TMP1058]], [[TMP1059]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2513]], label [[COND_TRUE2515:%.*]], label [[COND_FALSE2516:%.*]]
+// SIMD-ONLY0:       cond.true2515:
+// SIMD-ONLY0-NEXT:    [[TMP1060:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2517:%.*]]
+// SIMD-ONLY0:       cond.false2516:
+// SIMD-ONLY0-NEXT:    [[TMP1061:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2517]]
+// SIMD-ONLY0:       cond.end2517:
+// SIMD-ONLY0-NEXT:    [[COND2518:%.*]] = phi i32 [ [[TMP1060]], [[COND_TRUE2515]] ], [ [[TMP1061]], [[COND_FALSE2516]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2518]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1062:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1063:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2519:%.*]] = icmp ult i32 [[TMP1062]], [[TMP1063]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2519]], label [[COND_TRUE2521:%.*]], label [[COND_FALSE2522:%.*]]
+// SIMD-ONLY0:       cond.true2521:
+// SIMD-ONLY0-NEXT:    [[TMP1064:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2523:%.*]]
+// SIMD-ONLY0:       cond.false2522:
+// SIMD-ONLY0-NEXT:    [[TMP1065:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2523]]
+// SIMD-ONLY0:       cond.end2523:
+// SIMD-ONLY0-NEXT:    [[COND2524:%.*]] = phi i32 [ [[TMP1064]], [[COND_TRUE2521]] ], [ [[TMP1065]], [[COND_FALSE2522]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2524]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1066:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1067:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2525:%.*]] = icmp ugt i32 [[TMP1066]], [[TMP1067]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2525]], label [[IF_THEN2527:%.*]], label [[IF_END2528:%.*]]
+// SIMD-ONLY0:       if.then2527:
+// SIMD-ONLY0-NEXT:    [[TMP1068:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1068]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2528]]
+// SIMD-ONLY0:       if.end2528:
+// SIMD-ONLY0-NEXT:    [[TMP1069:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1070:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2529:%.*]] = icmp ult i32 [[TMP1069]], [[TMP1070]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2529]], label [[IF_THEN2531:%.*]], label [[IF_END2532:%.*]]
+// SIMD-ONLY0:       if.then2531:
+// SIMD-ONLY0-NEXT:    [[TMP1071:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1071]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2532]]
+// SIMD-ONLY0:       if.end2532:
+// SIMD-ONLY0-NEXT:    [[TMP1072:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1073:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2533:%.*]] = icmp ugt i32 [[TMP1072]], [[TMP1073]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2533]], label [[IF_THEN2535:%.*]], label [[IF_END2536:%.*]]
+// SIMD-ONLY0:       if.then2535:
+// SIMD-ONLY0-NEXT:    [[TMP1074:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1074]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2536]]
+// SIMD-ONLY0:       if.end2536:
+// SIMD-ONLY0-NEXT:    [[TMP1075:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1076:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2537:%.*]] = icmp ult i32 [[TMP1075]], [[TMP1076]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2537]], label [[IF_THEN2539:%.*]], label [[IF_END2540:%.*]]
+// SIMD-ONLY0:       if.then2539:
+// SIMD-ONLY0-NEXT:    [[TMP1077:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1077]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2540]]
+// SIMD-ONLY0:       if.end2540:
+// SIMD-ONLY0-NEXT:    [[TMP1078:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1079:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2541:%.*]] = icmp eq i32 [[TMP1078]], [[TMP1079]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2541]], label [[COND_TRUE2543:%.*]], label [[COND_FALSE2544:%.*]]
+// SIMD-ONLY0:       cond.true2543:
+// SIMD-ONLY0-NEXT:    [[TMP1080:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2545:%.*]]
+// SIMD-ONLY0:       cond.false2544:
+// SIMD-ONLY0-NEXT:    [[TMP1081:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2545]]
+// SIMD-ONLY0:       cond.end2545:
+// SIMD-ONLY0-NEXT:    [[COND2546:%.*]] = phi i32 [ [[TMP1080]], [[COND_TRUE2543]] ], [ [[TMP1081]], [[COND_FALSE2544]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2546]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1082:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1083:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2547:%.*]] = icmp eq i32 [[TMP1082]], [[TMP1083]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2547]], label [[COND_TRUE2549:%.*]], label [[COND_FALSE2550:%.*]]
+// SIMD-ONLY0:       cond.true2549:
+// SIMD-ONLY0-NEXT:    [[TMP1084:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2551:%.*]]
+// SIMD-ONLY0:       cond.false2550:
+// SIMD-ONLY0-NEXT:    [[TMP1085:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2551]]
+// SIMD-ONLY0:       cond.end2551:
+// SIMD-ONLY0-NEXT:    [[COND2552:%.*]] = phi i32 [ [[TMP1084]], [[COND_TRUE2549]] ], [ [[TMP1085]], [[COND_FALSE2550]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2552]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1086:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1087:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2553:%.*]] = icmp eq i32 [[TMP1086]], [[TMP1087]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2553]], label [[IF_THEN2555:%.*]], label [[IF_END2556:%.*]]
+// SIMD-ONLY0:       if.then2555:
+// SIMD-ONLY0-NEXT:    [[TMP1088:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1088]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2556]]
+// SIMD-ONLY0:       if.end2556:
+// SIMD-ONLY0-NEXT:    [[TMP1089:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1090:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2557:%.*]] = icmp eq i32 [[TMP1089]], [[TMP1090]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2557]], label [[IF_THEN2559:%.*]], label [[IF_END2560:%.*]]
+// SIMD-ONLY0:       if.then2559:
+// SIMD-ONLY0-NEXT:    [[TMP1091:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1091]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2560]]
+// SIMD-ONLY0:       if.end2560:
+// SIMD-ONLY0-NEXT:    [[TMP1092:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1093:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2561:%.*]] = icmp sgt i32 [[TMP1092]], [[TMP1093]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2561]], label [[COND_TRUE2563:%.*]], label [[COND_FALSE2564:%.*]]
+// SIMD-ONLY0:       cond.true2563:
+// SIMD-ONLY0-NEXT:    [[TMP1094:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2565:%.*]]
+// SIMD-ONLY0:       cond.false2564:
+// SIMD-ONLY0-NEXT:    [[TMP1095:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2565]]
+// SIMD-ONLY0:       cond.end2565:
+// SIMD-ONLY0-NEXT:    [[COND2566:%.*]] = phi i32 [ [[TMP1094]], [[COND_TRUE2563]] ], [ [[TMP1095]], [[COND_FALSE2564]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2566]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1096:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1097:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2567:%.*]] = icmp slt i32 [[TMP1096]], [[TMP1097]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2567]], label [[COND_TRUE2569:%.*]], label [[COND_FALSE2570:%.*]]
+// SIMD-ONLY0:       cond.true2569:
+// SIMD-ONLY0-NEXT:    [[TMP1098:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2571:%.*]]
+// SIMD-ONLY0:       cond.false2570:
+// SIMD-ONLY0-NEXT:    [[TMP1099:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2571]]
+// SIMD-ONLY0:       cond.end2571:
+// SIMD-ONLY0-NEXT:    [[COND2572:%.*]] = phi i32 [ [[TMP1098]], [[COND_TRUE2569]] ], [ [[TMP1099]], [[COND_FALSE2570]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2572]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1100:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1101:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2573:%.*]] = icmp sgt i32 [[TMP1100]], [[TMP1101]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2573]], label [[COND_TRUE2575:%.*]], label [[COND_FALSE2576:%.*]]
+// SIMD-ONLY0:       cond.true2575:
+// SIMD-ONLY0-NEXT:    [[TMP1102:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2577:%.*]]
+// SIMD-ONLY0:       cond.false2576:
+// SIMD-ONLY0-NEXT:    [[TMP1103:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2577]]
+// SIMD-ONLY0:       cond.end2577:
+// SIMD-ONLY0-NEXT:    [[COND2578:%.*]] = phi i32 [ [[TMP1102]], [[COND_TRUE2575]] ], [ [[TMP1103]], [[COND_FALSE2576]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2578]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1104:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1105:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2579:%.*]] = icmp slt i32 [[TMP1104]], [[TMP1105]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2579]], label [[COND_TRUE2581:%.*]], label [[COND_FALSE2582:%.*]]
+// SIMD-ONLY0:       cond.true2581:
+// SIMD-ONLY0-NEXT:    [[TMP1106:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2583:%.*]]
+// SIMD-ONLY0:       cond.false2582:
+// SIMD-ONLY0-NEXT:    [[TMP1107:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2583]]
+// SIMD-ONLY0:       cond.end2583:
+// SIMD-ONLY0-NEXT:    [[COND2584:%.*]] = phi i32 [ [[TMP1106]], [[COND_TRUE2581]] ], [ [[TMP1107]], [[COND_FALSE2582]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2584]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1108:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1109:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2585:%.*]] = icmp sgt i32 [[TMP1108]], [[TMP1109]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2585]], label [[IF_THEN2587:%.*]], label [[IF_END2588:%.*]]
+// SIMD-ONLY0:       if.then2587:
+// SIMD-ONLY0-NEXT:    [[TMP1110:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1110]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2588]]
+// SIMD-ONLY0:       if.end2588:
+// SIMD-ONLY0-NEXT:    [[TMP1111:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1112:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2589:%.*]] = icmp slt i32 [[TMP1111]], [[TMP1112]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2589]], label [[IF_THEN2591:%.*]], label [[IF_END2592:%.*]]
+// SIMD-ONLY0:       if.then2591:
+// SIMD-ONLY0-NEXT:    [[TMP1113:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1113]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2592]]
+// SIMD-ONLY0:       if.end2592:
+// SIMD-ONLY0-NEXT:    [[TMP1114:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1115:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2593:%.*]] = icmp sgt i32 [[TMP1114]], [[TMP1115]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2593]], label [[IF_THEN2595:%.*]], label [[IF_END2596:%.*]]
+// SIMD-ONLY0:       if.then2595:
+// SIMD-ONLY0-NEXT:    [[TMP1116:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1116]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2596]]
+// SIMD-ONLY0:       if.end2596:
+// SIMD-ONLY0-NEXT:    [[TMP1117:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1118:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2597:%.*]] = icmp slt i32 [[TMP1117]], [[TMP1118]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2597]], label [[IF_THEN2599:%.*]], label [[IF_END2600:%.*]]
+// SIMD-ONLY0:       if.then2599:
+// SIMD-ONLY0-NEXT:    [[TMP1119:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1119]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2600]]
+// SIMD-ONLY0:       if.end2600:
+// SIMD-ONLY0-NEXT:    [[TMP1120:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1121:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2601:%.*]] = icmp eq i32 [[TMP1120]], [[TMP1121]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2601]], label [[COND_TRUE2603:%.*]], label [[COND_FALSE2604:%.*]]
+// SIMD-ONLY0:       cond.true2603:
+// SIMD-ONLY0-NEXT:    [[TMP1122:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2605:%.*]]
+// SIMD-ONLY0:       cond.false2604:
+// SIMD-ONLY0-NEXT:    [[TMP1123:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2605]]
+// SIMD-ONLY0:       cond.end2605:
+// SIMD-ONLY0-NEXT:    [[COND2606:%.*]] = phi i32 [ [[TMP1122]], [[COND_TRUE2603]] ], [ [[TMP1123]], [[COND_FALSE2604]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2606]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1124:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1125:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2607:%.*]] = icmp eq i32 [[TMP1124]], [[TMP1125]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2607]], label [[COND_TRUE2609:%.*]], label [[COND_FALSE2610:%.*]]
+// SIMD-ONLY0:       cond.true2609:
+// SIMD-ONLY0-NEXT:    [[TMP1126:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2611:%.*]]
+// SIMD-ONLY0:       cond.false2610:
+// SIMD-ONLY0-NEXT:    [[TMP1127:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2611]]
+// SIMD-ONLY0:       cond.end2611:
+// SIMD-ONLY0-NEXT:    [[COND2612:%.*]] = phi i32 [ [[TMP1126]], [[COND_TRUE2609]] ], [ [[TMP1127]], [[COND_FALSE2610]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2612]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1128:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1129:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2613:%.*]] = icmp eq i32 [[TMP1128]], [[TMP1129]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2613]], label [[IF_THEN2615:%.*]], label [[IF_END2616:%.*]]
+// SIMD-ONLY0:       if.then2615:
+// SIMD-ONLY0-NEXT:    [[TMP1130:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1130]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2616]]
+// SIMD-ONLY0:       if.end2616:
+// SIMD-ONLY0-NEXT:    [[TMP1131:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1132:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2617:%.*]] = icmp eq i32 [[TMP1131]], [[TMP1132]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2617]], label [[IF_THEN2619:%.*]], label [[IF_END2620:%.*]]
+// SIMD-ONLY0:       if.then2619:
+// SIMD-ONLY0-NEXT:    [[TMP1133:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1133]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2620]]
+// SIMD-ONLY0:       if.end2620:
+// SIMD-ONLY0-NEXT:    [[TMP1134:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1135:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2621:%.*]] = icmp ugt i32 [[TMP1134]], [[TMP1135]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2621]], label [[COND_TRUE2623:%.*]], label [[COND_FALSE2624:%.*]]
+// SIMD-ONLY0:       cond.true2623:
+// SIMD-ONLY0-NEXT:    [[TMP1136:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2625:%.*]]
+// SIMD-ONLY0:       cond.false2624:
+// SIMD-ONLY0-NEXT:    [[TMP1137:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2625]]
+// SIMD-ONLY0:       cond.end2625:
+// SIMD-ONLY0-NEXT:    [[COND2626:%.*]] = phi i32 [ [[TMP1136]], [[COND_TRUE2623]] ], [ [[TMP1137]], [[COND_FALSE2624]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2626]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1138:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1139:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2627:%.*]] = icmp ult i32 [[TMP1138]], [[TMP1139]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2627]], label [[COND_TRUE2629:%.*]], label [[COND_FALSE2630:%.*]]
+// SIMD-ONLY0:       cond.true2629:
+// SIMD-ONLY0-NEXT:    [[TMP1140:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2631:%.*]]
+// SIMD-ONLY0:       cond.false2630:
+// SIMD-ONLY0-NEXT:    [[TMP1141:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2631]]
+// SIMD-ONLY0:       cond.end2631:
+// SIMD-ONLY0-NEXT:    [[COND2632:%.*]] = phi i32 [ [[TMP1140]], [[COND_TRUE2629]] ], [ [[TMP1141]], [[COND_FALSE2630]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2632]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1142:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1143:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2633:%.*]] = icmp ugt i32 [[TMP1142]], [[TMP1143]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2633]], label [[COND_TRUE2635:%.*]], label [[COND_FALSE2636:%.*]]
+// SIMD-ONLY0:       cond.true2635:
+// SIMD-ONLY0-NEXT:    [[TMP1144:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2637:%.*]]
+// SIMD-ONLY0:       cond.false2636:
+// SIMD-ONLY0-NEXT:    [[TMP1145:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2637]]
+// SIMD-ONLY0:       cond.end2637:
+// SIMD-ONLY0-NEXT:    [[COND2638:%.*]] = phi i32 [ [[TMP1144]], [[COND_TRUE2635]] ], [ [[TMP1145]], [[COND_FALSE2636]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2638]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1146:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1147:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2639:%.*]] = icmp ult i32 [[TMP1146]], [[TMP1147]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2639]], label [[COND_TRUE2641:%.*]], label [[COND_FALSE2642:%.*]]
+// SIMD-ONLY0:       cond.true2641:
+// SIMD-ONLY0-NEXT:    [[TMP1148:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2643:%.*]]
+// SIMD-ONLY0:       cond.false2642:
+// SIMD-ONLY0-NEXT:    [[TMP1149:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2643]]
+// SIMD-ONLY0:       cond.end2643:
+// SIMD-ONLY0-NEXT:    [[COND2644:%.*]] = phi i32 [ [[TMP1148]], [[COND_TRUE2641]] ], [ [[TMP1149]], [[COND_FALSE2642]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2644]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1150:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1151:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2645:%.*]] = icmp ugt i32 [[TMP1150]], [[TMP1151]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2645]], label [[IF_THEN2647:%.*]], label [[IF_END2648:%.*]]
+// SIMD-ONLY0:       if.then2647:
+// SIMD-ONLY0-NEXT:    [[TMP1152:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1152]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2648]]
+// SIMD-ONLY0:       if.end2648:
+// SIMD-ONLY0-NEXT:    [[TMP1153:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1154:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2649:%.*]] = icmp ult i32 [[TMP1153]], [[TMP1154]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2649]], label [[IF_THEN2651:%.*]], label [[IF_END2652:%.*]]
+// SIMD-ONLY0:       if.then2651:
+// SIMD-ONLY0-NEXT:    [[TMP1155:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1155]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2652]]
+// SIMD-ONLY0:       if.end2652:
+// SIMD-ONLY0-NEXT:    [[TMP1156:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1157:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2653:%.*]] = icmp ugt i32 [[TMP1156]], [[TMP1157]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2653]], label [[IF_THEN2655:%.*]], label [[IF_END2656:%.*]]
+// SIMD-ONLY0:       if.then2655:
+// SIMD-ONLY0-NEXT:    [[TMP1158:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1158]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2656]]
+// SIMD-ONLY0:       if.end2656:
+// SIMD-ONLY0-NEXT:    [[TMP1159:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1160:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2657:%.*]] = icmp ult i32 [[TMP1159]], [[TMP1160]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2657]], label [[IF_THEN2659:%.*]], label [[IF_END2660:%.*]]
+// SIMD-ONLY0:       if.then2659:
+// SIMD-ONLY0-NEXT:    [[TMP1161:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1161]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2660]]
+// SIMD-ONLY0:       if.end2660:
+// SIMD-ONLY0-NEXT:    [[TMP1162:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1163:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2661:%.*]] = icmp eq i32 [[TMP1162]], [[TMP1163]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2661]], label [[COND_TRUE2663:%.*]], label [[COND_FALSE2664:%.*]]
+// SIMD-ONLY0:       cond.true2663:
+// SIMD-ONLY0-NEXT:    [[TMP1164:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2665:%.*]]
+// SIMD-ONLY0:       cond.false2664:
+// SIMD-ONLY0-NEXT:    [[TMP1165:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2665]]
+// SIMD-ONLY0:       cond.end2665:
+// SIMD-ONLY0-NEXT:    [[COND2666:%.*]] = phi i32 [ [[TMP1164]], [[COND_TRUE2663]] ], [ [[TMP1165]], [[COND_FALSE2664]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2666]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1166:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1167:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2667:%.*]] = icmp eq i32 [[TMP1166]], [[TMP1167]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2667]], label [[COND_TRUE2669:%.*]], label [[COND_FALSE2670:%.*]]
+// SIMD-ONLY0:       cond.true2669:
+// SIMD-ONLY0-NEXT:    [[TMP1168:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2671:%.*]]
+// SIMD-ONLY0:       cond.false2670:
+// SIMD-ONLY0-NEXT:    [[TMP1169:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2671]]
+// SIMD-ONLY0:       cond.end2671:
+// SIMD-ONLY0-NEXT:    [[COND2672:%.*]] = phi i32 [ [[TMP1168]], [[COND_TRUE2669]] ], [ [[TMP1169]], [[COND_FALSE2670]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2672]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1170:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1171:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2673:%.*]] = icmp eq i32 [[TMP1170]], [[TMP1171]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2673]], label [[IF_THEN2675:%.*]], label [[IF_END2676:%.*]]
+// SIMD-ONLY0:       if.then2675:
+// SIMD-ONLY0-NEXT:    [[TMP1172:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1172]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2676]]
+// SIMD-ONLY0:       if.end2676:
+// SIMD-ONLY0-NEXT:    [[TMP1173:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1174:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2677:%.*]] = icmp eq i32 [[TMP1173]], [[TMP1174]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2677]], label [[IF_THEN2679:%.*]], label [[IF_END2680:%.*]]
+// SIMD-ONLY0:       if.then2679:
+// SIMD-ONLY0-NEXT:    [[TMP1175:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1175]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2680]]
+// SIMD-ONLY0:       if.end2680:
+// SIMD-ONLY0-NEXT:    [[TMP1176:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1177:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2681:%.*]] = icmp sgt i32 [[TMP1176]], [[TMP1177]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2681]], label [[COND_TRUE2683:%.*]], label [[COND_FALSE2684:%.*]]
+// SIMD-ONLY0:       cond.true2683:
+// SIMD-ONLY0-NEXT:    [[TMP1178:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2685:%.*]]
+// SIMD-ONLY0:       cond.false2684:
+// SIMD-ONLY0-NEXT:    [[TMP1179:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2685]]
+// SIMD-ONLY0:       cond.end2685:
+// SIMD-ONLY0-NEXT:    [[COND2686:%.*]] = phi i32 [ [[TMP1178]], [[COND_TRUE2683]] ], [ [[TMP1179]], [[COND_FALSE2684]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2686]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1180:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1181:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2687:%.*]] = icmp slt i32 [[TMP1180]], [[TMP1181]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2687]], label [[COND_TRUE2689:%.*]], label [[COND_FALSE2690:%.*]]
+// SIMD-ONLY0:       cond.true2689:
+// SIMD-ONLY0-NEXT:    [[TMP1182:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2691:%.*]]
+// SIMD-ONLY0:       cond.false2690:
+// SIMD-ONLY0-NEXT:    [[TMP1183:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2691]]
+// SIMD-ONLY0:       cond.end2691:
+// SIMD-ONLY0-NEXT:    [[COND2692:%.*]] = phi i32 [ [[TMP1182]], [[COND_TRUE2689]] ], [ [[TMP1183]], [[COND_FALSE2690]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2692]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1184:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1185:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2693:%.*]] = icmp sgt i32 [[TMP1184]], [[TMP1185]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2693]], label [[COND_TRUE2695:%.*]], label [[COND_FALSE2696:%.*]]
+// SIMD-ONLY0:       cond.true2695:
+// SIMD-ONLY0-NEXT:    [[TMP1186:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2697:%.*]]
+// SIMD-ONLY0:       cond.false2696:
+// SIMD-ONLY0-NEXT:    [[TMP1187:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2697]]
+// SIMD-ONLY0:       cond.end2697:
+// SIMD-ONLY0-NEXT:    [[COND2698:%.*]] = phi i32 [ [[TMP1186]], [[COND_TRUE2695]] ], [ [[TMP1187]], [[COND_FALSE2696]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2698]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1188:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1189:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2699:%.*]] = icmp slt i32 [[TMP1188]], [[TMP1189]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2699]], label [[COND_TRUE2701:%.*]], label [[COND_FALSE2702:%.*]]
+// SIMD-ONLY0:       cond.true2701:
+// SIMD-ONLY0-NEXT:    [[TMP1190:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2703:%.*]]
+// SIMD-ONLY0:       cond.false2702:
+// SIMD-ONLY0-NEXT:    [[TMP1191:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2703]]
+// SIMD-ONLY0:       cond.end2703:
+// SIMD-ONLY0-NEXT:    [[COND2704:%.*]] = phi i32 [ [[TMP1190]], [[COND_TRUE2701]] ], [ [[TMP1191]], [[COND_FALSE2702]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2704]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1192:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1193:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2705:%.*]] = icmp sgt i32 [[TMP1192]], [[TMP1193]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2705]], label [[IF_THEN2707:%.*]], label [[IF_END2708:%.*]]
+// SIMD-ONLY0:       if.then2707:
+// SIMD-ONLY0-NEXT:    [[TMP1194:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1194]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2708]]
+// SIMD-ONLY0:       if.end2708:
+// SIMD-ONLY0-NEXT:    [[TMP1195:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1196:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2709:%.*]] = icmp slt i32 [[TMP1195]], [[TMP1196]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2709]], label [[IF_THEN2711:%.*]], label [[IF_END2712:%.*]]
+// SIMD-ONLY0:       if.then2711:
+// SIMD-ONLY0-NEXT:    [[TMP1197:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1197]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2712]]
+// SIMD-ONLY0:       if.end2712:
+// SIMD-ONLY0-NEXT:    [[TMP1198:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1199:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2713:%.*]] = icmp sgt i32 [[TMP1198]], [[TMP1199]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2713]], label [[IF_THEN2715:%.*]], label [[IF_END2716:%.*]]
+// SIMD-ONLY0:       if.then2715:
+// SIMD-ONLY0-NEXT:    [[TMP1200:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1200]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2716]]
+// SIMD-ONLY0:       if.end2716:
+// SIMD-ONLY0-NEXT:    [[TMP1201:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1202:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2717:%.*]] = icmp slt i32 [[TMP1201]], [[TMP1202]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2717]], label [[IF_THEN2719:%.*]], label [[IF_END2720:%.*]]
+// SIMD-ONLY0:       if.then2719:
+// SIMD-ONLY0-NEXT:    [[TMP1203:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1203]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2720]]
+// SIMD-ONLY0:       if.end2720:
+// SIMD-ONLY0-NEXT:    [[TMP1204:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1205:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2721:%.*]] = icmp eq i32 [[TMP1204]], [[TMP1205]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2721]], label [[COND_TRUE2723:%.*]], label [[COND_FALSE2724:%.*]]
+// SIMD-ONLY0:       cond.true2723:
+// SIMD-ONLY0-NEXT:    [[TMP1206:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2725:%.*]]
+// SIMD-ONLY0:       cond.false2724:
+// SIMD-ONLY0-NEXT:    [[TMP1207:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2725]]
+// SIMD-ONLY0:       cond.end2725:
+// SIMD-ONLY0-NEXT:    [[COND2726:%.*]] = phi i32 [ [[TMP1206]], [[COND_TRUE2723]] ], [ [[TMP1207]], [[COND_FALSE2724]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2726]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1208:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1209:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2727:%.*]] = icmp eq i32 [[TMP1208]], [[TMP1209]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2727]], label [[COND_TRUE2729:%.*]], label [[COND_FALSE2730:%.*]]
+// SIMD-ONLY0:       cond.true2729:
+// SIMD-ONLY0-NEXT:    [[TMP1210:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2731:%.*]]
+// SIMD-ONLY0:       cond.false2730:
+// SIMD-ONLY0-NEXT:    [[TMP1211:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2731]]
+// SIMD-ONLY0:       cond.end2731:
+// SIMD-ONLY0-NEXT:    [[COND2732:%.*]] = phi i32 [ [[TMP1210]], [[COND_TRUE2729]] ], [ [[TMP1211]], [[COND_FALSE2730]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2732]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1212:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1213:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2733:%.*]] = icmp eq i32 [[TMP1212]], [[TMP1213]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2733]], label [[IF_THEN2735:%.*]], label [[IF_END2736:%.*]]
+// SIMD-ONLY0:       if.then2735:
+// SIMD-ONLY0-NEXT:    [[TMP1214:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1214]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2736]]
+// SIMD-ONLY0:       if.end2736:
+// SIMD-ONLY0-NEXT:    [[TMP1215:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1216:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2737:%.*]] = icmp eq i32 [[TMP1215]], [[TMP1216]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2737]], label [[IF_THEN2739:%.*]], label [[IF_END2740:%.*]]
+// SIMD-ONLY0:       if.then2739:
+// SIMD-ONLY0-NEXT:    [[TMP1217:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1217]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2740]]
+// SIMD-ONLY0:       if.end2740:
+// SIMD-ONLY0-NEXT:    [[TMP1218:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1219:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2741:%.*]] = icmp ugt i32 [[TMP1218]], [[TMP1219]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2741]], label [[COND_TRUE2743:%.*]], label [[COND_FALSE2744:%.*]]
+// SIMD-ONLY0:       cond.true2743:
+// SIMD-ONLY0-NEXT:    [[TMP1220:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2745:%.*]]
+// SIMD-ONLY0:       cond.false2744:
+// SIMD-ONLY0-NEXT:    [[TMP1221:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2745]]
+// SIMD-ONLY0:       cond.end2745:
+// SIMD-ONLY0-NEXT:    [[COND2746:%.*]] = phi i32 [ [[TMP1220]], [[COND_TRUE2743]] ], [ [[TMP1221]], [[COND_FALSE2744]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2746]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1222:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1223:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2747:%.*]] = icmp ult i32 [[TMP1222]], [[TMP1223]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2747]], label [[COND_TRUE2749:%.*]], label [[COND_FALSE2750:%.*]]
+// SIMD-ONLY0:       cond.true2749:
+// SIMD-ONLY0-NEXT:    [[TMP1224:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2751:%.*]]
+// SIMD-ONLY0:       cond.false2750:
+// SIMD-ONLY0-NEXT:    [[TMP1225:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2751]]
+// SIMD-ONLY0:       cond.end2751:
+// SIMD-ONLY0-NEXT:    [[COND2752:%.*]] = phi i32 [ [[TMP1224]], [[COND_TRUE2749]] ], [ [[TMP1225]], [[COND_FALSE2750]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2752]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1226:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1227:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2753:%.*]] = icmp ugt i32 [[TMP1226]], [[TMP1227]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2753]], label [[COND_TRUE2755:%.*]], label [[COND_FALSE2756:%.*]]
+// SIMD-ONLY0:       cond.true2755:
+// SIMD-ONLY0-NEXT:    [[TMP1228:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2757:%.*]]
+// SIMD-ONLY0:       cond.false2756:
+// SIMD-ONLY0-NEXT:    [[TMP1229:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2757]]
+// SIMD-ONLY0:       cond.end2757:
+// SIMD-ONLY0-NEXT:    [[COND2758:%.*]] = phi i32 [ [[TMP1228]], [[COND_TRUE2755]] ], [ [[TMP1229]], [[COND_FALSE2756]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2758]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1230:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1231:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2759:%.*]] = icmp ult i32 [[TMP1230]], [[TMP1231]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2759]], label [[COND_TRUE2761:%.*]], label [[COND_FALSE2762:%.*]]
+// SIMD-ONLY0:       cond.true2761:
+// SIMD-ONLY0-NEXT:    [[TMP1232:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2763:%.*]]
+// SIMD-ONLY0:       cond.false2762:
+// SIMD-ONLY0-NEXT:    [[TMP1233:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2763]]
+// SIMD-ONLY0:       cond.end2763:
+// SIMD-ONLY0-NEXT:    [[COND2764:%.*]] = phi i32 [ [[TMP1232]], [[COND_TRUE2761]] ], [ [[TMP1233]], [[COND_FALSE2762]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2764]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1234:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1235:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2765:%.*]] = icmp ugt i32 [[TMP1234]], [[TMP1235]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2765]], label [[IF_THEN2767:%.*]], label [[IF_END2768:%.*]]
+// SIMD-ONLY0:       if.then2767:
+// SIMD-ONLY0-NEXT:    [[TMP1236:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1236]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2768]]
+// SIMD-ONLY0:       if.end2768:
+// SIMD-ONLY0-NEXT:    [[TMP1237:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1238:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2769:%.*]] = icmp ult i32 [[TMP1237]], [[TMP1238]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2769]], label [[IF_THEN2771:%.*]], label [[IF_END2772:%.*]]
+// SIMD-ONLY0:       if.then2771:
+// SIMD-ONLY0-NEXT:    [[TMP1239:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1239]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2772]]
+// SIMD-ONLY0:       if.end2772:
+// SIMD-ONLY0-NEXT:    [[TMP1240:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1241:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2773:%.*]] = icmp ugt i32 [[TMP1240]], [[TMP1241]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2773]], label [[IF_THEN2775:%.*]], label [[IF_END2776:%.*]]
+// SIMD-ONLY0:       if.then2775:
+// SIMD-ONLY0-NEXT:    [[TMP1242:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1242]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2776]]
+// SIMD-ONLY0:       if.end2776:
+// SIMD-ONLY0-NEXT:    [[TMP1243:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1244:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2777:%.*]] = icmp ult i32 [[TMP1243]], [[TMP1244]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2777]], label [[IF_THEN2779:%.*]], label [[IF_END2780:%.*]]
+// SIMD-ONLY0:       if.then2779:
+// SIMD-ONLY0-NEXT:    [[TMP1245:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1245]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2780]]
+// SIMD-ONLY0:       if.end2780:
+// SIMD-ONLY0-NEXT:    [[TMP1246:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1247:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2781:%.*]] = icmp eq i32 [[TMP1246]], [[TMP1247]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2781]], label [[COND_TRUE2783:%.*]], label [[COND_FALSE2784:%.*]]
+// SIMD-ONLY0:       cond.true2783:
+// SIMD-ONLY0-NEXT:    [[TMP1248:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2785:%.*]]
+// SIMD-ONLY0:       cond.false2784:
+// SIMD-ONLY0-NEXT:    [[TMP1249:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2785]]
+// SIMD-ONLY0:       cond.end2785:
+// SIMD-ONLY0-NEXT:    [[COND2786:%.*]] = phi i32 [ [[TMP1248]], [[COND_TRUE2783]] ], [ [[TMP1249]], [[COND_FALSE2784]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2786]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1250:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1251:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2787:%.*]] = icmp eq i32 [[TMP1250]], [[TMP1251]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2787]], label [[COND_TRUE2789:%.*]], label [[COND_FALSE2790:%.*]]
+// SIMD-ONLY0:       cond.true2789:
+// SIMD-ONLY0-NEXT:    [[TMP1252:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2791:%.*]]
+// SIMD-ONLY0:       cond.false2790:
+// SIMD-ONLY0-NEXT:    [[TMP1253:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2791]]
+// SIMD-ONLY0:       cond.end2791:
+// SIMD-ONLY0-NEXT:    [[COND2792:%.*]] = phi i32 [ [[TMP1252]], [[COND_TRUE2789]] ], [ [[TMP1253]], [[COND_FALSE2790]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2792]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1254:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1255:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2793:%.*]] = icmp eq i32 [[TMP1254]], [[TMP1255]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2793]], label [[IF_THEN2795:%.*]], label [[IF_END2796:%.*]]
+// SIMD-ONLY0:       if.then2795:
+// SIMD-ONLY0-NEXT:    [[TMP1256:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1256]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2796]]
+// SIMD-ONLY0:       if.end2796:
+// SIMD-ONLY0-NEXT:    [[TMP1257:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1258:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2797:%.*]] = icmp eq i32 [[TMP1257]], [[TMP1258]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2797]], label [[IF_THEN2799:%.*]], label [[IF_END2800:%.*]]
+// SIMD-ONLY0:       if.then2799:
+// SIMD-ONLY0-NEXT:    [[TMP1259:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1259]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2800]]
+// SIMD-ONLY0:       if.end2800:
+// SIMD-ONLY0-NEXT:    [[TMP1260:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1261:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2801:%.*]] = icmp sgt i32 [[TMP1260]], [[TMP1261]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2801]], label [[COND_TRUE2803:%.*]], label [[COND_FALSE2804:%.*]]
+// SIMD-ONLY0:       cond.true2803:
+// SIMD-ONLY0-NEXT:    [[TMP1262:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2805:%.*]]
+// SIMD-ONLY0:       cond.false2804:
+// SIMD-ONLY0-NEXT:    [[TMP1263:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2805]]
+// SIMD-ONLY0:       cond.end2805:
+// SIMD-ONLY0-NEXT:    [[COND2806:%.*]] = phi i32 [ [[TMP1262]], [[COND_TRUE2803]] ], [ [[TMP1263]], [[COND_FALSE2804]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2806]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1264:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1265:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2807:%.*]] = icmp slt i32 [[TMP1264]], [[TMP1265]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2807]], label [[COND_TRUE2809:%.*]], label [[COND_FALSE2810:%.*]]
+// SIMD-ONLY0:       cond.true2809:
+// SIMD-ONLY0-NEXT:    [[TMP1266:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2811:%.*]]
+// SIMD-ONLY0:       cond.false2810:
+// SIMD-ONLY0-NEXT:    [[TMP1267:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2811]]
+// SIMD-ONLY0:       cond.end2811:
+// SIMD-ONLY0-NEXT:    [[COND2812:%.*]] = phi i32 [ [[TMP1266]], [[COND_TRUE2809]] ], [ [[TMP1267]], [[COND_FALSE2810]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2812]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1268:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1269:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2813:%.*]] = icmp sgt i32 [[TMP1268]], [[TMP1269]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2813]], label [[COND_TRUE2815:%.*]], label [[COND_FALSE2816:%.*]]
+// SIMD-ONLY0:       cond.true2815:
+// SIMD-ONLY0-NEXT:    [[TMP1270:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2817:%.*]]
+// SIMD-ONLY0:       cond.false2816:
+// SIMD-ONLY0-NEXT:    [[TMP1271:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2817]]
+// SIMD-ONLY0:       cond.end2817:
+// SIMD-ONLY0-NEXT:    [[COND2818:%.*]] = phi i32 [ [[TMP1270]], [[COND_TRUE2815]] ], [ [[TMP1271]], [[COND_FALSE2816]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2818]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1272:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1273:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2819:%.*]] = icmp slt i32 [[TMP1272]], [[TMP1273]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2819]], label [[COND_TRUE2821:%.*]], label [[COND_FALSE2822:%.*]]
+// SIMD-ONLY0:       cond.true2821:
+// SIMD-ONLY0-NEXT:    [[TMP1274:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2823:%.*]]
+// SIMD-ONLY0:       cond.false2822:
+// SIMD-ONLY0-NEXT:    [[TMP1275:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2823]]
+// SIMD-ONLY0:       cond.end2823:
+// SIMD-ONLY0-NEXT:    [[COND2824:%.*]] = phi i32 [ [[TMP1274]], [[COND_TRUE2821]] ], [ [[TMP1275]], [[COND_FALSE2822]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2824]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1276:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1277:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2825:%.*]] = icmp sgt i32 [[TMP1276]], [[TMP1277]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2825]], label [[IF_THEN2827:%.*]], label [[IF_END2828:%.*]]
+// SIMD-ONLY0:       if.then2827:
+// SIMD-ONLY0-NEXT:    [[TMP1278:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1278]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2828]]
+// SIMD-ONLY0:       if.end2828:
+// SIMD-ONLY0-NEXT:    [[TMP1279:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1280:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2829:%.*]] = icmp slt i32 [[TMP1279]], [[TMP1280]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2829]], label [[IF_THEN2831:%.*]], label [[IF_END2832:%.*]]
+// SIMD-ONLY0:       if.then2831:
+// SIMD-ONLY0-NEXT:    [[TMP1281:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1281]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2832]]
+// SIMD-ONLY0:       if.end2832:
+// SIMD-ONLY0-NEXT:    [[TMP1282:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1283:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2833:%.*]] = icmp sgt i32 [[TMP1282]], [[TMP1283]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2833]], label [[IF_THEN2835:%.*]], label [[IF_END2836:%.*]]
+// SIMD-ONLY0:       if.then2835:
+// SIMD-ONLY0-NEXT:    [[TMP1284:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1284]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2836]]
+// SIMD-ONLY0:       if.end2836:
+// SIMD-ONLY0-NEXT:    [[TMP1285:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1286:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2837:%.*]] = icmp slt i32 [[TMP1285]], [[TMP1286]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2837]], label [[IF_THEN2839:%.*]], label [[IF_END2840:%.*]]
+// SIMD-ONLY0:       if.then2839:
+// SIMD-ONLY0-NEXT:    [[TMP1287:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1287]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2840]]
+// SIMD-ONLY0:       if.end2840:
+// SIMD-ONLY0-NEXT:    [[TMP1288:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1289:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2841:%.*]] = icmp eq i32 [[TMP1288]], [[TMP1289]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2841]], label [[COND_TRUE2843:%.*]], label [[COND_FALSE2844:%.*]]
+// SIMD-ONLY0:       cond.true2843:
+// SIMD-ONLY0-NEXT:    [[TMP1290:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2845:%.*]]
+// SIMD-ONLY0:       cond.false2844:
+// SIMD-ONLY0-NEXT:    [[TMP1291:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2845]]
+// SIMD-ONLY0:       cond.end2845:
+// SIMD-ONLY0-NEXT:    [[COND2846:%.*]] = phi i32 [ [[TMP1290]], [[COND_TRUE2843]] ], [ [[TMP1291]], [[COND_FALSE2844]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2846]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1292:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1293:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2847:%.*]] = icmp eq i32 [[TMP1292]], [[TMP1293]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2847]], label [[COND_TRUE2849:%.*]], label [[COND_FALSE2850:%.*]]
+// SIMD-ONLY0:       cond.true2849:
+// SIMD-ONLY0-NEXT:    [[TMP1294:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2851:%.*]]
+// SIMD-ONLY0:       cond.false2850:
+// SIMD-ONLY0-NEXT:    [[TMP1295:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2851]]
+// SIMD-ONLY0:       cond.end2851:
+// SIMD-ONLY0-NEXT:    [[COND2852:%.*]] = phi i32 [ [[TMP1294]], [[COND_TRUE2849]] ], [ [[TMP1295]], [[COND_FALSE2850]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2852]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1296:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1297:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2853:%.*]] = icmp eq i32 [[TMP1296]], [[TMP1297]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2853]], label [[IF_THEN2855:%.*]], label [[IF_END2856:%.*]]
+// SIMD-ONLY0:       if.then2855:
+// SIMD-ONLY0-NEXT:    [[TMP1298:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1298]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2856]]
+// SIMD-ONLY0:       if.end2856:
+// SIMD-ONLY0-NEXT:    [[TMP1299:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1300:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2857:%.*]] = icmp eq i32 [[TMP1299]], [[TMP1300]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2857]], label [[IF_THEN2859:%.*]], label [[IF_END2860:%.*]]
+// SIMD-ONLY0:       if.then2859:
+// SIMD-ONLY0-NEXT:    [[TMP1301:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1301]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2860]]
+// SIMD-ONLY0:       if.end2860:
+// SIMD-ONLY0-NEXT:    [[TMP1302:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1303:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2861:%.*]] = icmp ugt i32 [[TMP1302]], [[TMP1303]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2861]], label [[COND_TRUE2863:%.*]], label [[COND_FALSE2864:%.*]]
+// SIMD-ONLY0:       cond.true2863:
+// SIMD-ONLY0-NEXT:    [[TMP1304:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2865:%.*]]
+// SIMD-ONLY0:       cond.false2864:
+// SIMD-ONLY0-NEXT:    [[TMP1305:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2865]]
+// SIMD-ONLY0:       cond.end2865:
+// SIMD-ONLY0-NEXT:    [[COND2866:%.*]] = phi i32 [ [[TMP1304]], [[COND_TRUE2863]] ], [ [[TMP1305]], [[COND_FALSE2864]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2866]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1306:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1307:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2867:%.*]] = icmp ult i32 [[TMP1306]], [[TMP1307]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2867]], label [[COND_TRUE2869:%.*]], label [[COND_FALSE2870:%.*]]
+// SIMD-ONLY0:       cond.true2869:
+// SIMD-ONLY0-NEXT:    [[TMP1308:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2871:%.*]]
+// SIMD-ONLY0:       cond.false2870:
+// SIMD-ONLY0-NEXT:    [[TMP1309:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2871]]
+// SIMD-ONLY0:       cond.end2871:
+// SIMD-ONLY0-NEXT:    [[COND2872:%.*]] = phi i32 [ [[TMP1308]], [[COND_TRUE2869]] ], [ [[TMP1309]], [[COND_FALSE2870]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2872]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1310:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1311:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2873:%.*]] = icmp ugt i32 [[TMP1310]], [[TMP1311]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2873]], label [[COND_TRUE2875:%.*]], label [[COND_FALSE2876:%.*]]
+// SIMD-ONLY0:       cond.true2875:
+// SIMD-ONLY0-NEXT:    [[TMP1312:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2877:%.*]]
+// SIMD-ONLY0:       cond.false2876:
+// SIMD-ONLY0-NEXT:    [[TMP1313:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2877]]
+// SIMD-ONLY0:       cond.end2877:
+// SIMD-ONLY0-NEXT:    [[COND2878:%.*]] = phi i32 [ [[TMP1312]], [[COND_TRUE2875]] ], [ [[TMP1313]], [[COND_FALSE2876]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2878]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1314:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1315:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2879:%.*]] = icmp ult i32 [[TMP1314]], [[TMP1315]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2879]], label [[COND_TRUE2881:%.*]], label [[COND_FALSE2882:%.*]]
+// SIMD-ONLY0:       cond.true2881:
+// SIMD-ONLY0-NEXT:    [[TMP1316:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2883:%.*]]
+// SIMD-ONLY0:       cond.false2882:
+// SIMD-ONLY0-NEXT:    [[TMP1317:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2883]]
+// SIMD-ONLY0:       cond.end2883:
+// SIMD-ONLY0-NEXT:    [[COND2884:%.*]] = phi i32 [ [[TMP1316]], [[COND_TRUE2881]] ], [ [[TMP1317]], [[COND_FALSE2882]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2884]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1318:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1319:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2885:%.*]] = icmp ugt i32 [[TMP1318]], [[TMP1319]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2885]], label [[IF_THEN2887:%.*]], label [[IF_END2888:%.*]]
+// SIMD-ONLY0:       if.then2887:
+// SIMD-ONLY0-NEXT:    [[TMP1320:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1320]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2888]]
+// SIMD-ONLY0:       if.end2888:
+// SIMD-ONLY0-NEXT:    [[TMP1321:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1322:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2889:%.*]] = icmp ult i32 [[TMP1321]], [[TMP1322]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2889]], label [[IF_THEN2891:%.*]], label [[IF_END2892:%.*]]
+// SIMD-ONLY0:       if.then2891:
+// SIMD-ONLY0-NEXT:    [[TMP1323:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1323]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2892]]
+// SIMD-ONLY0:       if.end2892:
+// SIMD-ONLY0-NEXT:    [[TMP1324:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1325:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2893:%.*]] = icmp ugt i32 [[TMP1324]], [[TMP1325]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2893]], label [[IF_THEN2895:%.*]], label [[IF_END2896:%.*]]
+// SIMD-ONLY0:       if.then2895:
+// SIMD-ONLY0-NEXT:    [[TMP1326:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1326]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2896]]
+// SIMD-ONLY0:       if.end2896:
+// SIMD-ONLY0-NEXT:    [[TMP1327:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1328:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2897:%.*]] = icmp ult i32 [[TMP1327]], [[TMP1328]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2897]], label [[IF_THEN2899:%.*]], label [[IF_END2900:%.*]]
+// SIMD-ONLY0:       if.then2899:
+// SIMD-ONLY0-NEXT:    [[TMP1329:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1329]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2900]]
+// SIMD-ONLY0:       if.end2900:
+// SIMD-ONLY0-NEXT:    [[TMP1330:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1331:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2901:%.*]] = icmp eq i32 [[TMP1330]], [[TMP1331]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2901]], label [[COND_TRUE2903:%.*]], label [[COND_FALSE2904:%.*]]
+// SIMD-ONLY0:       cond.true2903:
+// SIMD-ONLY0-NEXT:    [[TMP1332:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2905:%.*]]
+// SIMD-ONLY0:       cond.false2904:
+// SIMD-ONLY0-NEXT:    [[TMP1333:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2905]]
+// SIMD-ONLY0:       cond.end2905:
+// SIMD-ONLY0-NEXT:    [[COND2906:%.*]] = phi i32 [ [[TMP1332]], [[COND_TRUE2903]] ], [ [[TMP1333]], [[COND_FALSE2904]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2906]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1334:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1335:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2907:%.*]] = icmp eq i32 [[TMP1334]], [[TMP1335]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2907]], label [[COND_TRUE2909:%.*]], label [[COND_FALSE2910:%.*]]
+// SIMD-ONLY0:       cond.true2909:
+// SIMD-ONLY0-NEXT:    [[TMP1336:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2911:%.*]]
+// SIMD-ONLY0:       cond.false2910:
+// SIMD-ONLY0-NEXT:    [[TMP1337:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2911]]
+// SIMD-ONLY0:       cond.end2911:
+// SIMD-ONLY0-NEXT:    [[COND2912:%.*]] = phi i32 [ [[TMP1336]], [[COND_TRUE2909]] ], [ [[TMP1337]], [[COND_FALSE2910]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2912]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1338:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1339:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2913:%.*]] = icmp eq i32 [[TMP1338]], [[TMP1339]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2913]], label [[IF_THEN2915:%.*]], label [[IF_END2916:%.*]]
+// SIMD-ONLY0:       if.then2915:
+// SIMD-ONLY0-NEXT:    [[TMP1340:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1340]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2916]]
+// SIMD-ONLY0:       if.end2916:
+// SIMD-ONLY0-NEXT:    [[TMP1341:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1342:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2917:%.*]] = icmp eq i32 [[TMP1341]], [[TMP1342]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2917]], label [[IF_THEN2919:%.*]], label [[IF_END2920:%.*]]
+// SIMD-ONLY0:       if.then2919:
+// SIMD-ONLY0-NEXT:    [[TMP1343:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1343]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2920]]
+// SIMD-ONLY0:       if.end2920:
+// SIMD-ONLY0-NEXT:    [[TMP1344:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1345:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2921:%.*]] = icmp sgt i32 [[TMP1344]], [[TMP1345]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2921]], label [[COND_TRUE2923:%.*]], label [[COND_FALSE2924:%.*]]
+// SIMD-ONLY0:       cond.true2923:
+// SIMD-ONLY0-NEXT:    [[TMP1346:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2925:%.*]]
+// SIMD-ONLY0:       cond.false2924:
+// SIMD-ONLY0-NEXT:    [[TMP1347:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2925]]
+// SIMD-ONLY0:       cond.end2925:
+// SIMD-ONLY0-NEXT:    [[COND2926:%.*]] = phi i32 [ [[TMP1346]], [[COND_TRUE2923]] ], [ [[TMP1347]], [[COND_FALSE2924]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2926]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1348:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1349:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2927:%.*]] = icmp slt i32 [[TMP1348]], [[TMP1349]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2927]], label [[COND_TRUE2929:%.*]], label [[COND_FALSE2930:%.*]]
+// SIMD-ONLY0:       cond.true2929:
+// SIMD-ONLY0-NEXT:    [[TMP1350:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2931:%.*]]
+// SIMD-ONLY0:       cond.false2930:
+// SIMD-ONLY0-NEXT:    [[TMP1351:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2931]]
+// SIMD-ONLY0:       cond.end2931:
+// SIMD-ONLY0-NEXT:    [[COND2932:%.*]] = phi i32 [ [[TMP1350]], [[COND_TRUE2929]] ], [ [[TMP1351]], [[COND_FALSE2930]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2932]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1352:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1353:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2933:%.*]] = icmp sgt i32 [[TMP1352]], [[TMP1353]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2933]], label [[COND_TRUE2935:%.*]], label [[COND_FALSE2936:%.*]]
+// SIMD-ONLY0:       cond.true2935:
+// SIMD-ONLY0-NEXT:    [[TMP1354:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2937:%.*]]
+// SIMD-ONLY0:       cond.false2936:
+// SIMD-ONLY0-NEXT:    [[TMP1355:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2937]]
+// SIMD-ONLY0:       cond.end2937:
+// SIMD-ONLY0-NEXT:    [[COND2938:%.*]] = phi i32 [ [[TMP1354]], [[COND_TRUE2935]] ], [ [[TMP1355]], [[COND_FALSE2936]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2938]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1356:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1357:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2939:%.*]] = icmp slt i32 [[TMP1356]], [[TMP1357]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2939]], label [[COND_TRUE2941:%.*]], label [[COND_FALSE2942:%.*]]
+// SIMD-ONLY0:       cond.true2941:
+// SIMD-ONLY0-NEXT:    [[TMP1358:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2943:%.*]]
+// SIMD-ONLY0:       cond.false2942:
+// SIMD-ONLY0-NEXT:    [[TMP1359:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2943]]
+// SIMD-ONLY0:       cond.end2943:
+// SIMD-ONLY0-NEXT:    [[COND2944:%.*]] = phi i32 [ [[TMP1358]], [[COND_TRUE2941]] ], [ [[TMP1359]], [[COND_FALSE2942]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2944]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1360:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1361:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2945:%.*]] = icmp sgt i32 [[TMP1360]], [[TMP1361]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2945]], label [[IF_THEN2947:%.*]], label [[IF_END2948:%.*]]
+// SIMD-ONLY0:       if.then2947:
+// SIMD-ONLY0-NEXT:    [[TMP1362:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1362]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2948]]
+// SIMD-ONLY0:       if.end2948:
+// SIMD-ONLY0-NEXT:    [[TMP1363:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1364:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2949:%.*]] = icmp slt i32 [[TMP1363]], [[TMP1364]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2949]], label [[IF_THEN2951:%.*]], label [[IF_END2952:%.*]]
+// SIMD-ONLY0:       if.then2951:
+// SIMD-ONLY0-NEXT:    [[TMP1365:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1365]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2952]]
+// SIMD-ONLY0:       if.end2952:
+// SIMD-ONLY0-NEXT:    [[TMP1366:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1367:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2953:%.*]] = icmp sgt i32 [[TMP1366]], [[TMP1367]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2953]], label [[IF_THEN2955:%.*]], label [[IF_END2956:%.*]]
+// SIMD-ONLY0:       if.then2955:
+// SIMD-ONLY0-NEXT:    [[TMP1368:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1368]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2956]]
+// SIMD-ONLY0:       if.end2956:
+// SIMD-ONLY0-NEXT:    [[TMP1369:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1370:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2957:%.*]] = icmp slt i32 [[TMP1369]], [[TMP1370]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2957]], label [[IF_THEN2959:%.*]], label [[IF_END2960:%.*]]
+// SIMD-ONLY0:       if.then2959:
+// SIMD-ONLY0-NEXT:    [[TMP1371:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1371]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2960]]
+// SIMD-ONLY0:       if.end2960:
+// SIMD-ONLY0-NEXT:    [[TMP1372:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1373:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2961:%.*]] = icmp eq i32 [[TMP1372]], [[TMP1373]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2961]], label [[COND_TRUE2963:%.*]], label [[COND_FALSE2964:%.*]]
+// SIMD-ONLY0:       cond.true2963:
+// SIMD-ONLY0-NEXT:    [[TMP1374:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2965:%.*]]
+// SIMD-ONLY0:       cond.false2964:
+// SIMD-ONLY0-NEXT:    [[TMP1375:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2965]]
+// SIMD-ONLY0:       cond.end2965:
+// SIMD-ONLY0-NEXT:    [[COND2966:%.*]] = phi i32 [ [[TMP1374]], [[COND_TRUE2963]] ], [ [[TMP1375]], [[COND_FALSE2964]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2966]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1376:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1377:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2967:%.*]] = icmp eq i32 [[TMP1376]], [[TMP1377]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2967]], label [[COND_TRUE2969:%.*]], label [[COND_FALSE2970:%.*]]
+// SIMD-ONLY0:       cond.true2969:
+// SIMD-ONLY0-NEXT:    [[TMP1378:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2971:%.*]]
+// SIMD-ONLY0:       cond.false2970:
+// SIMD-ONLY0-NEXT:    [[TMP1379:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2971]]
+// SIMD-ONLY0:       cond.end2971:
+// SIMD-ONLY0-NEXT:    [[COND2972:%.*]] = phi i32 [ [[TMP1378]], [[COND_TRUE2969]] ], [ [[TMP1379]], [[COND_FALSE2970]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2972]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1380:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1381:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2973:%.*]] = icmp eq i32 [[TMP1380]], [[TMP1381]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2973]], label [[IF_THEN2975:%.*]], label [[IF_END2976:%.*]]
+// SIMD-ONLY0:       if.then2975:
+// SIMD-ONLY0-NEXT:    [[TMP1382:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1382]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2976]]
+// SIMD-ONLY0:       if.end2976:
+// SIMD-ONLY0-NEXT:    [[TMP1383:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1384:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2977:%.*]] = icmp eq i32 [[TMP1383]], [[TMP1384]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2977]], label [[IF_THEN2979:%.*]], label [[IF_END2980:%.*]]
+// SIMD-ONLY0:       if.then2979:
+// SIMD-ONLY0-NEXT:    [[TMP1385:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1385]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END2980]]
+// SIMD-ONLY0:       if.end2980:
+// SIMD-ONLY0-NEXT:    [[TMP1386:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1387:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2981:%.*]] = icmp ugt i32 [[TMP1386]], [[TMP1387]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2981]], label [[COND_TRUE2983:%.*]], label [[COND_FALSE2984:%.*]]
+// SIMD-ONLY0:       cond.true2983:
+// SIMD-ONLY0-NEXT:    [[TMP1388:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2985:%.*]]
+// SIMD-ONLY0:       cond.false2984:
+// SIMD-ONLY0-NEXT:    [[TMP1389:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2985]]
+// SIMD-ONLY0:       cond.end2985:
+// SIMD-ONLY0-NEXT:    [[COND2986:%.*]] = phi i32 [ [[TMP1388]], [[COND_TRUE2983]] ], [ [[TMP1389]], [[COND_FALSE2984]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2986]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1390:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1391:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2987:%.*]] = icmp ult i32 [[TMP1390]], [[TMP1391]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2987]], label [[COND_TRUE2989:%.*]], label [[COND_FALSE2990:%.*]]
+// SIMD-ONLY0:       cond.true2989:
+// SIMD-ONLY0-NEXT:    [[TMP1392:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2991:%.*]]
+// SIMD-ONLY0:       cond.false2990:
+// SIMD-ONLY0-NEXT:    [[TMP1393:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2991]]
+// SIMD-ONLY0:       cond.end2991:
+// SIMD-ONLY0-NEXT:    [[COND2992:%.*]] = phi i32 [ [[TMP1392]], [[COND_TRUE2989]] ], [ [[TMP1393]], [[COND_FALSE2990]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2992]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1394:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1395:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2993:%.*]] = icmp ugt i32 [[TMP1394]], [[TMP1395]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2993]], label [[COND_TRUE2995:%.*]], label [[COND_FALSE2996:%.*]]
+// SIMD-ONLY0:       cond.true2995:
+// SIMD-ONLY0-NEXT:    [[TMP1396:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2997:%.*]]
+// SIMD-ONLY0:       cond.false2996:
+// SIMD-ONLY0-NEXT:    [[TMP1397:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END2997]]
+// SIMD-ONLY0:       cond.end2997:
+// SIMD-ONLY0-NEXT:    [[COND2998:%.*]] = phi i32 [ [[TMP1396]], [[COND_TRUE2995]] ], [ [[TMP1397]], [[COND_FALSE2996]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND2998]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1398:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1399:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP2999:%.*]] = icmp ult i32 [[TMP1398]], [[TMP1399]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP2999]], label [[COND_TRUE3001:%.*]], label [[COND_FALSE3002:%.*]]
+// SIMD-ONLY0:       cond.true3001:
+// SIMD-ONLY0-NEXT:    [[TMP1400:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3003:%.*]]
+// SIMD-ONLY0:       cond.false3002:
+// SIMD-ONLY0-NEXT:    [[TMP1401:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3003]]
+// SIMD-ONLY0:       cond.end3003:
+// SIMD-ONLY0-NEXT:    [[COND3004:%.*]] = phi i32 [ [[TMP1400]], [[COND_TRUE3001]] ], [ [[TMP1401]], [[COND_FALSE3002]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND3004]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1402:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1403:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3005:%.*]] = icmp ugt i32 [[TMP1402]], [[TMP1403]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3005]], label [[IF_THEN3007:%.*]], label [[IF_END3008:%.*]]
+// SIMD-ONLY0:       if.then3007:
+// SIMD-ONLY0-NEXT:    [[TMP1404:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1404]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3008]]
+// SIMD-ONLY0:       if.end3008:
+// SIMD-ONLY0-NEXT:    [[TMP1405:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1406:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3009:%.*]] = icmp ult i32 [[TMP1405]], [[TMP1406]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3009]], label [[IF_THEN3011:%.*]], label [[IF_END3012:%.*]]
+// SIMD-ONLY0:       if.then3011:
+// SIMD-ONLY0-NEXT:    [[TMP1407:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1407]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3012]]
+// SIMD-ONLY0:       if.end3012:
+// SIMD-ONLY0-NEXT:    [[TMP1408:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1409:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3013:%.*]] = icmp ugt i32 [[TMP1408]], [[TMP1409]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3013]], label [[IF_THEN3015:%.*]], label [[IF_END3016:%.*]]
+// SIMD-ONLY0:       if.then3015:
+// SIMD-ONLY0-NEXT:    [[TMP1410:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1410]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3016]]
+// SIMD-ONLY0:       if.end3016:
+// SIMD-ONLY0-NEXT:    [[TMP1411:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1412:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3017:%.*]] = icmp ult i32 [[TMP1411]], [[TMP1412]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3017]], label [[IF_THEN3019:%.*]], label [[IF_END3020:%.*]]
+// SIMD-ONLY0:       if.then3019:
+// SIMD-ONLY0-NEXT:    [[TMP1413:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1413]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3020]]
+// SIMD-ONLY0:       if.end3020:
+// SIMD-ONLY0-NEXT:    [[TMP1414:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1415:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3021:%.*]] = icmp eq i32 [[TMP1414]], [[TMP1415]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3021]], label [[COND_TRUE3023:%.*]], label [[COND_FALSE3024:%.*]]
+// SIMD-ONLY0:       cond.true3023:
+// SIMD-ONLY0-NEXT:    [[TMP1416:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3025:%.*]]
+// SIMD-ONLY0:       cond.false3024:
+// SIMD-ONLY0-NEXT:    [[TMP1417:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3025]]
+// SIMD-ONLY0:       cond.end3025:
+// SIMD-ONLY0-NEXT:    [[COND3026:%.*]] = phi i32 [ [[TMP1416]], [[COND_TRUE3023]] ], [ [[TMP1417]], [[COND_FALSE3024]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND3026]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1418:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1419:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3027:%.*]] = icmp eq i32 [[TMP1418]], [[TMP1419]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3027]], label [[COND_TRUE3029:%.*]], label [[COND_FALSE3030:%.*]]
+// SIMD-ONLY0:       cond.true3029:
+// SIMD-ONLY0-NEXT:    [[TMP1420:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3031:%.*]]
+// SIMD-ONLY0:       cond.false3030:
+// SIMD-ONLY0-NEXT:    [[TMP1421:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3031]]
+// SIMD-ONLY0:       cond.end3031:
+// SIMD-ONLY0-NEXT:    [[COND3032:%.*]] = phi i32 [ [[TMP1420]], [[COND_TRUE3029]] ], [ [[TMP1421]], [[COND_FALSE3030]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND3032]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1422:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1423:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3033:%.*]] = icmp eq i32 [[TMP1422]], [[TMP1423]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3033]], label [[IF_THEN3035:%.*]], label [[IF_END3036:%.*]]
+// SIMD-ONLY0:       if.then3035:
+// SIMD-ONLY0-NEXT:    [[TMP1424:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1424]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3036]]
+// SIMD-ONLY0:       if.end3036:
+// SIMD-ONLY0-NEXT:    [[TMP1425:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1426:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3037:%.*]] = icmp eq i32 [[TMP1425]], [[TMP1426]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3037]], label [[IF_THEN3039:%.*]], label [[IF_END3040:%.*]]
+// SIMD-ONLY0:       if.then3039:
+// SIMD-ONLY0-NEXT:    [[TMP1427:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1427]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3040]]
+// SIMD-ONLY0:       if.end3040:
+// SIMD-ONLY0-NEXT:    [[TMP1428:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1429:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3041:%.*]] = icmp sgt i32 [[TMP1428]], [[TMP1429]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3041]], label [[COND_TRUE3043:%.*]], label [[COND_FALSE3044:%.*]]
+// SIMD-ONLY0:       cond.true3043:
+// SIMD-ONLY0-NEXT:    [[TMP1430:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3045:%.*]]
+// SIMD-ONLY0:       cond.false3044:
+// SIMD-ONLY0-NEXT:    [[TMP1431:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3045]]
+// SIMD-ONLY0:       cond.end3045:
+// SIMD-ONLY0-NEXT:    [[COND3046:%.*]] = phi i32 [ [[TMP1430]], [[COND_TRUE3043]] ], [ [[TMP1431]], [[COND_FALSE3044]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND3046]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1432:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1433:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3047:%.*]] = icmp slt i32 [[TMP1432]], [[TMP1433]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3047]], label [[COND_TRUE3049:%.*]], label [[COND_FALSE3050:%.*]]
+// SIMD-ONLY0:       cond.true3049:
+// SIMD-ONLY0-NEXT:    [[TMP1434:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3051:%.*]]
+// SIMD-ONLY0:       cond.false3050:
+// SIMD-ONLY0-NEXT:    [[TMP1435:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3051]]
+// SIMD-ONLY0:       cond.end3051:
+// SIMD-ONLY0-NEXT:    [[COND3052:%.*]] = phi i32 [ [[TMP1434]], [[COND_TRUE3049]] ], [ [[TMP1435]], [[COND_FALSE3050]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND3052]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1436:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1437:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3053:%.*]] = icmp sgt i32 [[TMP1436]], [[TMP1437]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3053]], label [[COND_TRUE3055:%.*]], label [[COND_FALSE3056:%.*]]
+// SIMD-ONLY0:       cond.true3055:
+// SIMD-ONLY0-NEXT:    [[TMP1438:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3057:%.*]]
+// SIMD-ONLY0:       cond.false3056:
+// SIMD-ONLY0-NEXT:    [[TMP1439:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3057]]
+// SIMD-ONLY0:       cond.end3057:
+// SIMD-ONLY0-NEXT:    [[COND3058:%.*]] = phi i32 [ [[TMP1438]], [[COND_TRUE3055]] ], [ [[TMP1439]], [[COND_FALSE3056]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND3058]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1440:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1441:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3059:%.*]] = icmp slt i32 [[TMP1440]], [[TMP1441]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3059]], label [[COND_TRUE3061:%.*]], label [[COND_FALSE3062:%.*]]
+// SIMD-ONLY0:       cond.true3061:
+// SIMD-ONLY0-NEXT:    [[TMP1442:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3063:%.*]]
+// SIMD-ONLY0:       cond.false3062:
+// SIMD-ONLY0-NEXT:    [[TMP1443:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3063]]
+// SIMD-ONLY0:       cond.end3063:
+// SIMD-ONLY0-NEXT:    [[COND3064:%.*]] = phi i32 [ [[TMP1442]], [[COND_TRUE3061]] ], [ [[TMP1443]], [[COND_FALSE3062]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND3064]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1444:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1445:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3065:%.*]] = icmp sgt i32 [[TMP1444]], [[TMP1445]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3065]], label [[IF_THEN3067:%.*]], label [[IF_END3068:%.*]]
+// SIMD-ONLY0:       if.then3067:
+// SIMD-ONLY0-NEXT:    [[TMP1446:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1446]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3068]]
+// SIMD-ONLY0:       if.end3068:
+// SIMD-ONLY0-NEXT:    [[TMP1447:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1448:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3069:%.*]] = icmp slt i32 [[TMP1447]], [[TMP1448]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3069]], label [[IF_THEN3071:%.*]], label [[IF_END3072:%.*]]
+// SIMD-ONLY0:       if.then3071:
+// SIMD-ONLY0-NEXT:    [[TMP1449:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1449]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3072]]
+// SIMD-ONLY0:       if.end3072:
+// SIMD-ONLY0-NEXT:    [[TMP1450:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1451:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3073:%.*]] = icmp sgt i32 [[TMP1450]], [[TMP1451]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3073]], label [[IF_THEN3075:%.*]], label [[IF_END3076:%.*]]
+// SIMD-ONLY0:       if.then3075:
+// SIMD-ONLY0-NEXT:    [[TMP1452:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1452]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3076]]
+// SIMD-ONLY0:       if.end3076:
+// SIMD-ONLY0-NEXT:    [[TMP1453:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1454:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3077:%.*]] = icmp slt i32 [[TMP1453]], [[TMP1454]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3077]], label [[IF_THEN3079:%.*]], label [[IF_END3080:%.*]]
+// SIMD-ONLY0:       if.then3079:
+// SIMD-ONLY0-NEXT:    [[TMP1455:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1455]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3080]]
+// SIMD-ONLY0:       if.end3080:
+// SIMD-ONLY0-NEXT:    [[TMP1456:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1457:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3081:%.*]] = icmp eq i32 [[TMP1456]], [[TMP1457]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3081]], label [[COND_TRUE3083:%.*]], label [[COND_FALSE3084:%.*]]
+// SIMD-ONLY0:       cond.true3083:
+// SIMD-ONLY0-NEXT:    [[TMP1458:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3085:%.*]]
+// SIMD-ONLY0:       cond.false3084:
+// SIMD-ONLY0-NEXT:    [[TMP1459:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3085]]
+// SIMD-ONLY0:       cond.end3085:
+// SIMD-ONLY0-NEXT:    [[COND3086:%.*]] = phi i32 [ [[TMP1458]], [[COND_TRUE3083]] ], [ [[TMP1459]], [[COND_FALSE3084]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND3086]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1460:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1461:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3087:%.*]] = icmp eq i32 [[TMP1460]], [[TMP1461]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3087]], label [[COND_TRUE3089:%.*]], label [[COND_FALSE3090:%.*]]
+// SIMD-ONLY0:       cond.true3089:
+// SIMD-ONLY0-NEXT:    [[TMP1462:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3091:%.*]]
+// SIMD-ONLY0:       cond.false3090:
+// SIMD-ONLY0-NEXT:    [[TMP1463:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3091]]
+// SIMD-ONLY0:       cond.end3091:
+// SIMD-ONLY0-NEXT:    [[COND3092:%.*]] = phi i32 [ [[TMP1462]], [[COND_TRUE3089]] ], [ [[TMP1463]], [[COND_FALSE3090]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND3092]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1464:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1465:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3093:%.*]] = icmp eq i32 [[TMP1464]], [[TMP1465]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3093]], label [[IF_THEN3095:%.*]], label [[IF_END3096:%.*]]
+// SIMD-ONLY0:       if.then3095:
+// SIMD-ONLY0-NEXT:    [[TMP1466:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1466]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3096]]
+// SIMD-ONLY0:       if.end3096:
+// SIMD-ONLY0-NEXT:    [[TMP1467:%.*]] = load i32, i32* [[IE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1468:%.*]] = load i32, i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3097:%.*]] = icmp eq i32 [[TMP1467]], [[TMP1468]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3097]], label [[IF_THEN3099:%.*]], label [[IF_END3100:%.*]]
+// SIMD-ONLY0:       if.then3099:
+// SIMD-ONLY0-NEXT:    [[TMP1469:%.*]] = load i32, i32* [[ID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1469]], i32* [[IX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3100]]
+// SIMD-ONLY0:       if.end3100:
+// SIMD-ONLY0-NEXT:    [[TMP1470:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1471:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3101:%.*]] = icmp ugt i32 [[TMP1470]], [[TMP1471]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3101]], label [[COND_TRUE3103:%.*]], label [[COND_FALSE3104:%.*]]
+// SIMD-ONLY0:       cond.true3103:
+// SIMD-ONLY0-NEXT:    [[TMP1472:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3105:%.*]]
+// SIMD-ONLY0:       cond.false3104:
+// SIMD-ONLY0-NEXT:    [[TMP1473:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3105]]
+// SIMD-ONLY0:       cond.end3105:
+// SIMD-ONLY0-NEXT:    [[COND3106:%.*]] = phi i32 [ [[TMP1472]], [[COND_TRUE3103]] ], [ [[TMP1473]], [[COND_FALSE3104]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND3106]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1474:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1475:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3107:%.*]] = icmp ult i32 [[TMP1474]], [[TMP1475]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3107]], label [[COND_TRUE3109:%.*]], label [[COND_FALSE3110:%.*]]
+// SIMD-ONLY0:       cond.true3109:
+// SIMD-ONLY0-NEXT:    [[TMP1476:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3111:%.*]]
+// SIMD-ONLY0:       cond.false3110:
+// SIMD-ONLY0-NEXT:    [[TMP1477:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3111]]
+// SIMD-ONLY0:       cond.end3111:
+// SIMD-ONLY0-NEXT:    [[COND3112:%.*]] = phi i32 [ [[TMP1476]], [[COND_TRUE3109]] ], [ [[TMP1477]], [[COND_FALSE3110]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND3112]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1478:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1479:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3113:%.*]] = icmp ugt i32 [[TMP1478]], [[TMP1479]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3113]], label [[COND_TRUE3115:%.*]], label [[COND_FALSE3116:%.*]]
+// SIMD-ONLY0:       cond.true3115:
+// SIMD-ONLY0-NEXT:    [[TMP1480:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3117:%.*]]
+// SIMD-ONLY0:       cond.false3116:
+// SIMD-ONLY0-NEXT:    [[TMP1481:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3117]]
+// SIMD-ONLY0:       cond.end3117:
+// SIMD-ONLY0-NEXT:    [[COND3118:%.*]] = phi i32 [ [[TMP1480]], [[COND_TRUE3115]] ], [ [[TMP1481]], [[COND_FALSE3116]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND3118]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1482:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1483:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3119:%.*]] = icmp ult i32 [[TMP1482]], [[TMP1483]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3119]], label [[COND_TRUE3121:%.*]], label [[COND_FALSE3122:%.*]]
+// SIMD-ONLY0:       cond.true3121:
+// SIMD-ONLY0-NEXT:    [[TMP1484:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3123:%.*]]
+// SIMD-ONLY0:       cond.false3122:
+// SIMD-ONLY0-NEXT:    [[TMP1485:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3123]]
+// SIMD-ONLY0:       cond.end3123:
+// SIMD-ONLY0-NEXT:    [[COND3124:%.*]] = phi i32 [ [[TMP1484]], [[COND_TRUE3121]] ], [ [[TMP1485]], [[COND_FALSE3122]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND3124]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1486:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1487:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3125:%.*]] = icmp ugt i32 [[TMP1486]], [[TMP1487]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3125]], label [[IF_THEN3127:%.*]], label [[IF_END3128:%.*]]
+// SIMD-ONLY0:       if.then3127:
+// SIMD-ONLY0-NEXT:    [[TMP1488:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1488]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3128]]
+// SIMD-ONLY0:       if.end3128:
+// SIMD-ONLY0-NEXT:    [[TMP1489:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1490:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3129:%.*]] = icmp ult i32 [[TMP1489]], [[TMP1490]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3129]], label [[IF_THEN3131:%.*]], label [[IF_END3132:%.*]]
+// SIMD-ONLY0:       if.then3131:
+// SIMD-ONLY0-NEXT:    [[TMP1491:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1491]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3132]]
+// SIMD-ONLY0:       if.end3132:
+// SIMD-ONLY0-NEXT:    [[TMP1492:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1493:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3133:%.*]] = icmp ugt i32 [[TMP1492]], [[TMP1493]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3133]], label [[IF_THEN3135:%.*]], label [[IF_END3136:%.*]]
+// SIMD-ONLY0:       if.then3135:
+// SIMD-ONLY0-NEXT:    [[TMP1494:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1494]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3136]]
+// SIMD-ONLY0:       if.end3136:
+// SIMD-ONLY0-NEXT:    [[TMP1495:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1496:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3137:%.*]] = icmp ult i32 [[TMP1495]], [[TMP1496]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3137]], label [[IF_THEN3139:%.*]], label [[IF_END3140:%.*]]
+// SIMD-ONLY0:       if.then3139:
+// SIMD-ONLY0-NEXT:    [[TMP1497:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1497]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3140]]
+// SIMD-ONLY0:       if.end3140:
+// SIMD-ONLY0-NEXT:    [[TMP1498:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1499:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3141:%.*]] = icmp eq i32 [[TMP1498]], [[TMP1499]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3141]], label [[COND_TRUE3143:%.*]], label [[COND_FALSE3144:%.*]]
+// SIMD-ONLY0:       cond.true3143:
+// SIMD-ONLY0-NEXT:    [[TMP1500:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3145:%.*]]
+// SIMD-ONLY0:       cond.false3144:
+// SIMD-ONLY0-NEXT:    [[TMP1501:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3145]]
+// SIMD-ONLY0:       cond.end3145:
+// SIMD-ONLY0-NEXT:    [[COND3146:%.*]] = phi i32 [ [[TMP1500]], [[COND_TRUE3143]] ], [ [[TMP1501]], [[COND_FALSE3144]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND3146]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1502:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1503:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3147:%.*]] = icmp eq i32 [[TMP1502]], [[TMP1503]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3147]], label [[COND_TRUE3149:%.*]], label [[COND_FALSE3150:%.*]]
+// SIMD-ONLY0:       cond.true3149:
+// SIMD-ONLY0-NEXT:    [[TMP1504:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3151:%.*]]
+// SIMD-ONLY0:       cond.false3150:
+// SIMD-ONLY0-NEXT:    [[TMP1505:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[COND_END3151]]
+// SIMD-ONLY0:       cond.end3151:
+// SIMD-ONLY0-NEXT:    [[COND3152:%.*]] = phi i32 [ [[TMP1504]], [[COND_TRUE3149]] ], [ [[TMP1505]], [[COND_FALSE3150]] ]
+// SIMD-ONLY0-NEXT:    store i32 [[COND3152]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1506:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1507:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3153:%.*]] = icmp eq i32 [[TMP1506]], [[TMP1507]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3153]], label [[IF_THEN3155:%.*]], label [[IF_END3156:%.*]]
+// SIMD-ONLY0:       if.then3155:
+// SIMD-ONLY0-NEXT:    [[TMP1508:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1508]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3156]]
+// SIMD-ONLY0:       if.end3156:
+// SIMD-ONLY0-NEXT:    [[TMP1509:%.*]] = load i32, i32* [[UIE]], align 4
+// SIMD-ONLY0-NEXT:    [[TMP1510:%.*]] = load i32, i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    [[CMP3157:%.*]] = icmp eq i32 [[TMP1509]], [[TMP1510]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3157]], label [[IF_THEN3159:%.*]], label [[IF_END3160:%.*]]
+// SIMD-ONLY0:       if.then3159:
+// SIMD-ONLY0-NEXT:    [[TMP1511:%.*]] = load i32, i32* [[UID]], align 4
+// SIMD-ONLY0-NEXT:    store i32 [[TMP1511]], i32* [[UIX]], align 4
+// SIMD-ONLY0-NEXT:    br label [[IF_END3160]]
+// SIMD-ONLY0:       if.end3160:
+// SIMD-ONLY0-NEXT:    [[TMP1512:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1513:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3161:%.*]] = icmp sgt i64 [[TMP1512]], [[TMP1513]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3161]], label [[COND_TRUE3163:%.*]], label [[COND_FALSE3164:%.*]]
+// SIMD-ONLY0:       cond.true3163:
+// SIMD-ONLY0-NEXT:    [[TMP1514:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3165:%.*]]
+// SIMD-ONLY0:       cond.false3164:
+// SIMD-ONLY0-NEXT:    [[TMP1515:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3165]]
+// SIMD-ONLY0:       cond.end3165:
+// SIMD-ONLY0-NEXT:    [[COND3166:%.*]] = phi i64 [ [[TMP1514]], [[COND_TRUE3163]] ], [ [[TMP1515]], [[COND_FALSE3164]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3166]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1516:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1517:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3167:%.*]] = icmp slt i64 [[TMP1516]], [[TMP1517]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3167]], label [[COND_TRUE3169:%.*]], label [[COND_FALSE3170:%.*]]
+// SIMD-ONLY0:       cond.true3169:
+// SIMD-ONLY0-NEXT:    [[TMP1518:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3171:%.*]]
+// SIMD-ONLY0:       cond.false3170:
+// SIMD-ONLY0-NEXT:    [[TMP1519:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3171]]
+// SIMD-ONLY0:       cond.end3171:
+// SIMD-ONLY0-NEXT:    [[COND3172:%.*]] = phi i64 [ [[TMP1518]], [[COND_TRUE3169]] ], [ [[TMP1519]], [[COND_FALSE3170]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3172]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1520:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1521:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3173:%.*]] = icmp sgt i64 [[TMP1520]], [[TMP1521]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3173]], label [[COND_TRUE3175:%.*]], label [[COND_FALSE3176:%.*]]
+// SIMD-ONLY0:       cond.true3175:
+// SIMD-ONLY0-NEXT:    [[TMP1522:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3177:%.*]]
+// SIMD-ONLY0:       cond.false3176:
+// SIMD-ONLY0-NEXT:    [[TMP1523:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3177]]
+// SIMD-ONLY0:       cond.end3177:
+// SIMD-ONLY0-NEXT:    [[COND3178:%.*]] = phi i64 [ [[TMP1522]], [[COND_TRUE3175]] ], [ [[TMP1523]], [[COND_FALSE3176]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3178]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1524:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1525:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3179:%.*]] = icmp slt i64 [[TMP1524]], [[TMP1525]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3179]], label [[COND_TRUE3181:%.*]], label [[COND_FALSE3182:%.*]]
+// SIMD-ONLY0:       cond.true3181:
+// SIMD-ONLY0-NEXT:    [[TMP1526:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3183:%.*]]
+// SIMD-ONLY0:       cond.false3182:
+// SIMD-ONLY0-NEXT:    [[TMP1527:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3183]]
+// SIMD-ONLY0:       cond.end3183:
+// SIMD-ONLY0-NEXT:    [[COND3184:%.*]] = phi i64 [ [[TMP1526]], [[COND_TRUE3181]] ], [ [[TMP1527]], [[COND_FALSE3182]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3184]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1528:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1529:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3185:%.*]] = icmp sgt i64 [[TMP1528]], [[TMP1529]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3185]], label [[IF_THEN3187:%.*]], label [[IF_END3188:%.*]]
+// SIMD-ONLY0:       if.then3187:
+// SIMD-ONLY0-NEXT:    [[TMP1530:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1530]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3188]]
+// SIMD-ONLY0:       if.end3188:
+// SIMD-ONLY0-NEXT:    [[TMP1531:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1532:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3189:%.*]] = icmp slt i64 [[TMP1531]], [[TMP1532]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3189]], label [[IF_THEN3191:%.*]], label [[IF_END3192:%.*]]
+// SIMD-ONLY0:       if.then3191:
+// SIMD-ONLY0-NEXT:    [[TMP1533:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1533]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3192]]
+// SIMD-ONLY0:       if.end3192:
+// SIMD-ONLY0-NEXT:    [[TMP1534:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1535:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3193:%.*]] = icmp sgt i64 [[TMP1534]], [[TMP1535]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3193]], label [[IF_THEN3195:%.*]], label [[IF_END3196:%.*]]
+// SIMD-ONLY0:       if.then3195:
+// SIMD-ONLY0-NEXT:    [[TMP1536:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1536]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3196]]
+// SIMD-ONLY0:       if.end3196:
+// SIMD-ONLY0-NEXT:    [[TMP1537:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1538:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3197:%.*]] = icmp slt i64 [[TMP1537]], [[TMP1538]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3197]], label [[IF_THEN3199:%.*]], label [[IF_END3200:%.*]]
+// SIMD-ONLY0:       if.then3199:
+// SIMD-ONLY0-NEXT:    [[TMP1539:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1539]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3200]]
+// SIMD-ONLY0:       if.end3200:
+// SIMD-ONLY0-NEXT:    [[TMP1540:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1541:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3201:%.*]] = icmp eq i64 [[TMP1540]], [[TMP1541]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3201]], label [[COND_TRUE3203:%.*]], label [[COND_FALSE3204:%.*]]
+// SIMD-ONLY0:       cond.true3203:
+// SIMD-ONLY0-NEXT:    [[TMP1542:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3205:%.*]]
+// SIMD-ONLY0:       cond.false3204:
+// SIMD-ONLY0-NEXT:    [[TMP1543:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3205]]
+// SIMD-ONLY0:       cond.end3205:
+// SIMD-ONLY0-NEXT:    [[COND3206:%.*]] = phi i64 [ [[TMP1542]], [[COND_TRUE3203]] ], [ [[TMP1543]], [[COND_FALSE3204]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3206]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1544:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1545:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3207:%.*]] = icmp eq i64 [[TMP1544]], [[TMP1545]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3207]], label [[COND_TRUE3209:%.*]], label [[COND_FALSE3210:%.*]]
+// SIMD-ONLY0:       cond.true3209:
+// SIMD-ONLY0-NEXT:    [[TMP1546:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3211:%.*]]
+// SIMD-ONLY0:       cond.false3210:
+// SIMD-ONLY0-NEXT:    [[TMP1547:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3211]]
+// SIMD-ONLY0:       cond.end3211:
+// SIMD-ONLY0-NEXT:    [[COND3212:%.*]] = phi i64 [ [[TMP1546]], [[COND_TRUE3209]] ], [ [[TMP1547]], [[COND_FALSE3210]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3212]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1548:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1549:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3213:%.*]] = icmp eq i64 [[TMP1548]], [[TMP1549]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3213]], label [[IF_THEN3215:%.*]], label [[IF_END3216:%.*]]
+// SIMD-ONLY0:       if.then3215:
+// SIMD-ONLY0-NEXT:    [[TMP1550:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1550]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3216]]
+// SIMD-ONLY0:       if.end3216:
+// SIMD-ONLY0-NEXT:    [[TMP1551:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1552:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3217:%.*]] = icmp eq i64 [[TMP1551]], [[TMP1552]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3217]], label [[IF_THEN3219:%.*]], label [[IF_END3220:%.*]]
+// SIMD-ONLY0:       if.then3219:
+// SIMD-ONLY0-NEXT:    [[TMP1553:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1553]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3220]]
+// SIMD-ONLY0:       if.end3220:
+// SIMD-ONLY0-NEXT:    [[TMP1554:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1555:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3221:%.*]] = icmp ugt i64 [[TMP1554]], [[TMP1555]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3221]], label [[COND_TRUE3223:%.*]], label [[COND_FALSE3224:%.*]]
+// SIMD-ONLY0:       cond.true3223:
+// SIMD-ONLY0-NEXT:    [[TMP1556:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3225:%.*]]
+// SIMD-ONLY0:       cond.false3224:
+// SIMD-ONLY0-NEXT:    [[TMP1557:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3225]]
+// SIMD-ONLY0:       cond.end3225:
+// SIMD-ONLY0-NEXT:    [[COND3226:%.*]] = phi i64 [ [[TMP1556]], [[COND_TRUE3223]] ], [ [[TMP1557]], [[COND_FALSE3224]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3226]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1558:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1559:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3227:%.*]] = icmp ult i64 [[TMP1558]], [[TMP1559]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3227]], label [[COND_TRUE3229:%.*]], label [[COND_FALSE3230:%.*]]
+// SIMD-ONLY0:       cond.true3229:
+// SIMD-ONLY0-NEXT:    [[TMP1560:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3231:%.*]]
+// SIMD-ONLY0:       cond.false3230:
+// SIMD-ONLY0-NEXT:    [[TMP1561:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3231]]
+// SIMD-ONLY0:       cond.end3231:
+// SIMD-ONLY0-NEXT:    [[COND3232:%.*]] = phi i64 [ [[TMP1560]], [[COND_TRUE3229]] ], [ [[TMP1561]], [[COND_FALSE3230]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3232]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1562:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1563:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3233:%.*]] = icmp ugt i64 [[TMP1562]], [[TMP1563]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3233]], label [[COND_TRUE3235:%.*]], label [[COND_FALSE3236:%.*]]
+// SIMD-ONLY0:       cond.true3235:
+// SIMD-ONLY0-NEXT:    [[TMP1564:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3237:%.*]]
+// SIMD-ONLY0:       cond.false3236:
+// SIMD-ONLY0-NEXT:    [[TMP1565:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3237]]
+// SIMD-ONLY0:       cond.end3237:
+// SIMD-ONLY0-NEXT:    [[COND3238:%.*]] = phi i64 [ [[TMP1564]], [[COND_TRUE3235]] ], [ [[TMP1565]], [[COND_FALSE3236]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3238]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1566:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1567:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3239:%.*]] = icmp ult i64 [[TMP1566]], [[TMP1567]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3239]], label [[COND_TRUE3241:%.*]], label [[COND_FALSE3242:%.*]]
+// SIMD-ONLY0:       cond.true3241:
+// SIMD-ONLY0-NEXT:    [[TMP1568:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3243:%.*]]
+// SIMD-ONLY0:       cond.false3242:
+// SIMD-ONLY0-NEXT:    [[TMP1569:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3243]]
+// SIMD-ONLY0:       cond.end3243:
+// SIMD-ONLY0-NEXT:    [[COND3244:%.*]] = phi i64 [ [[TMP1568]], [[COND_TRUE3241]] ], [ [[TMP1569]], [[COND_FALSE3242]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3244]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1570:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1571:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3245:%.*]] = icmp ugt i64 [[TMP1570]], [[TMP1571]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3245]], label [[IF_THEN3247:%.*]], label [[IF_END3248:%.*]]
+// SIMD-ONLY0:       if.then3247:
+// SIMD-ONLY0-NEXT:    [[TMP1572:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1572]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3248]]
+// SIMD-ONLY0:       if.end3248:
+// SIMD-ONLY0-NEXT:    [[TMP1573:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1574:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3249:%.*]] = icmp ult i64 [[TMP1573]], [[TMP1574]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3249]], label [[IF_THEN3251:%.*]], label [[IF_END3252:%.*]]
+// SIMD-ONLY0:       if.then3251:
+// SIMD-ONLY0-NEXT:    [[TMP1575:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1575]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3252]]
+// SIMD-ONLY0:       if.end3252:
+// SIMD-ONLY0-NEXT:    [[TMP1576:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1577:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3253:%.*]] = icmp ugt i64 [[TMP1576]], [[TMP1577]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3253]], label [[IF_THEN3255:%.*]], label [[IF_END3256:%.*]]
+// SIMD-ONLY0:       if.then3255:
+// SIMD-ONLY0-NEXT:    [[TMP1578:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1578]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3256]]
+// SIMD-ONLY0:       if.end3256:
+// SIMD-ONLY0-NEXT:    [[TMP1579:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1580:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3257:%.*]] = icmp ult i64 [[TMP1579]], [[TMP1580]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3257]], label [[IF_THEN3259:%.*]], label [[IF_END3260:%.*]]
+// SIMD-ONLY0:       if.then3259:
+// SIMD-ONLY0-NEXT:    [[TMP1581:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1581]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3260]]
+// SIMD-ONLY0:       if.end3260:
+// SIMD-ONLY0-NEXT:    [[TMP1582:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1583:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3261:%.*]] = icmp eq i64 [[TMP1582]], [[TMP1583]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3261]], label [[COND_TRUE3263:%.*]], label [[COND_FALSE3264:%.*]]
+// SIMD-ONLY0:       cond.true3263:
+// SIMD-ONLY0-NEXT:    [[TMP1584:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3265:%.*]]
+// SIMD-ONLY0:       cond.false3264:
+// SIMD-ONLY0-NEXT:    [[TMP1585:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3265]]
+// SIMD-ONLY0:       cond.end3265:
+// SIMD-ONLY0-NEXT:    [[COND3266:%.*]] = phi i64 [ [[TMP1584]], [[COND_TRUE3263]] ], [ [[TMP1585]], [[COND_FALSE3264]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3266]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1586:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1587:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3267:%.*]] = icmp eq i64 [[TMP1586]], [[TMP1587]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3267]], label [[COND_TRUE3269:%.*]], label [[COND_FALSE3270:%.*]]
+// SIMD-ONLY0:       cond.true3269:
+// SIMD-ONLY0-NEXT:    [[TMP1588:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3271:%.*]]
+// SIMD-ONLY0:       cond.false3270:
+// SIMD-ONLY0-NEXT:    [[TMP1589:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3271]]
+// SIMD-ONLY0:       cond.end3271:
+// SIMD-ONLY0-NEXT:    [[COND3272:%.*]] = phi i64 [ [[TMP1588]], [[COND_TRUE3269]] ], [ [[TMP1589]], [[COND_FALSE3270]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3272]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1590:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1591:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3273:%.*]] = icmp eq i64 [[TMP1590]], [[TMP1591]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3273]], label [[IF_THEN3275:%.*]], label [[IF_END3276:%.*]]
+// SIMD-ONLY0:       if.then3275:
+// SIMD-ONLY0-NEXT:    [[TMP1592:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1592]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3276]]
+// SIMD-ONLY0:       if.end3276:
+// SIMD-ONLY0-NEXT:    [[TMP1593:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1594:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3277:%.*]] = icmp eq i64 [[TMP1593]], [[TMP1594]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3277]], label [[IF_THEN3279:%.*]], label [[IF_END3280:%.*]]
+// SIMD-ONLY0:       if.then3279:
+// SIMD-ONLY0-NEXT:    [[TMP1595:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1595]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3280]]
+// SIMD-ONLY0:       if.end3280:
+// SIMD-ONLY0-NEXT:    [[TMP1596:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1597:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3281:%.*]] = icmp sgt i64 [[TMP1596]], [[TMP1597]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3281]], label [[COND_TRUE3283:%.*]], label [[COND_FALSE3284:%.*]]
+// SIMD-ONLY0:       cond.true3283:
+// SIMD-ONLY0-NEXT:    [[TMP1598:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3285:%.*]]
+// SIMD-ONLY0:       cond.false3284:
+// SIMD-ONLY0-NEXT:    [[TMP1599:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3285]]
+// SIMD-ONLY0:       cond.end3285:
+// SIMD-ONLY0-NEXT:    [[COND3286:%.*]] = phi i64 [ [[TMP1598]], [[COND_TRUE3283]] ], [ [[TMP1599]], [[COND_FALSE3284]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3286]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1600:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1601:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3287:%.*]] = icmp slt i64 [[TMP1600]], [[TMP1601]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3287]], label [[COND_TRUE3289:%.*]], label [[COND_FALSE3290:%.*]]
+// SIMD-ONLY0:       cond.true3289:
+// SIMD-ONLY0-NEXT:    [[TMP1602:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3291:%.*]]
+// SIMD-ONLY0:       cond.false3290:
+// SIMD-ONLY0-NEXT:    [[TMP1603:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3291]]
+// SIMD-ONLY0:       cond.end3291:
+// SIMD-ONLY0-NEXT:    [[COND3292:%.*]] = phi i64 [ [[TMP1602]], [[COND_TRUE3289]] ], [ [[TMP1603]], [[COND_FALSE3290]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3292]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1604:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1605:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3293:%.*]] = icmp sgt i64 [[TMP1604]], [[TMP1605]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3293]], label [[COND_TRUE3295:%.*]], label [[COND_FALSE3296:%.*]]
+// SIMD-ONLY0:       cond.true3295:
+// SIMD-ONLY0-NEXT:    [[TMP1606:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3297:%.*]]
+// SIMD-ONLY0:       cond.false3296:
+// SIMD-ONLY0-NEXT:    [[TMP1607:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3297]]
+// SIMD-ONLY0:       cond.end3297:
+// SIMD-ONLY0-NEXT:    [[COND3298:%.*]] = phi i64 [ [[TMP1606]], [[COND_TRUE3295]] ], [ [[TMP1607]], [[COND_FALSE3296]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3298]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1608:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1609:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3299:%.*]] = icmp slt i64 [[TMP1608]], [[TMP1609]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3299]], label [[COND_TRUE3301:%.*]], label [[COND_FALSE3302:%.*]]
+// SIMD-ONLY0:       cond.true3301:
+// SIMD-ONLY0-NEXT:    [[TMP1610:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3303:%.*]]
+// SIMD-ONLY0:       cond.false3302:
+// SIMD-ONLY0-NEXT:    [[TMP1611:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3303]]
+// SIMD-ONLY0:       cond.end3303:
+// SIMD-ONLY0-NEXT:    [[COND3304:%.*]] = phi i64 [ [[TMP1610]], [[COND_TRUE3301]] ], [ [[TMP1611]], [[COND_FALSE3302]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3304]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1612:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1613:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3305:%.*]] = icmp sgt i64 [[TMP1612]], [[TMP1613]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3305]], label [[IF_THEN3307:%.*]], label [[IF_END3308:%.*]]
+// SIMD-ONLY0:       if.then3307:
+// SIMD-ONLY0-NEXT:    [[TMP1614:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1614]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3308]]
+// SIMD-ONLY0:       if.end3308:
+// SIMD-ONLY0-NEXT:    [[TMP1615:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1616:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3309:%.*]] = icmp slt i64 [[TMP1615]], [[TMP1616]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3309]], label [[IF_THEN3311:%.*]], label [[IF_END3312:%.*]]
+// SIMD-ONLY0:       if.then3311:
+// SIMD-ONLY0-NEXT:    [[TMP1617:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1617]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3312]]
+// SIMD-ONLY0:       if.end3312:
+// SIMD-ONLY0-NEXT:    [[TMP1618:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1619:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3313:%.*]] = icmp sgt i64 [[TMP1618]], [[TMP1619]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3313]], label [[IF_THEN3315:%.*]], label [[IF_END3316:%.*]]
+// SIMD-ONLY0:       if.then3315:
+// SIMD-ONLY0-NEXT:    [[TMP1620:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1620]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3316]]
+// SIMD-ONLY0:       if.end3316:
+// SIMD-ONLY0-NEXT:    [[TMP1621:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1622:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3317:%.*]] = icmp slt i64 [[TMP1621]], [[TMP1622]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3317]], label [[IF_THEN3319:%.*]], label [[IF_END3320:%.*]]
+// SIMD-ONLY0:       if.then3319:
+// SIMD-ONLY0-NEXT:    [[TMP1623:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1623]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3320]]
+// SIMD-ONLY0:       if.end3320:
+// SIMD-ONLY0-NEXT:    [[TMP1624:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1625:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3321:%.*]] = icmp eq i64 [[TMP1624]], [[TMP1625]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3321]], label [[COND_TRUE3323:%.*]], label [[COND_FALSE3324:%.*]]
+// SIMD-ONLY0:       cond.true3323:
+// SIMD-ONLY0-NEXT:    [[TMP1626:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3325:%.*]]
+// SIMD-ONLY0:       cond.false3324:
+// SIMD-ONLY0-NEXT:    [[TMP1627:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3325]]
+// SIMD-ONLY0:       cond.end3325:
+// SIMD-ONLY0-NEXT:    [[COND3326:%.*]] = phi i64 [ [[TMP1626]], [[COND_TRUE3323]] ], [ [[TMP1627]], [[COND_FALSE3324]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3326]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1628:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1629:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3327:%.*]] = icmp eq i64 [[TMP1628]], [[TMP1629]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3327]], label [[COND_TRUE3329:%.*]], label [[COND_FALSE3330:%.*]]
+// SIMD-ONLY0:       cond.true3329:
+// SIMD-ONLY0-NEXT:    [[TMP1630:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3331:%.*]]
+// SIMD-ONLY0:       cond.false3330:
+// SIMD-ONLY0-NEXT:    [[TMP1631:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3331]]
+// SIMD-ONLY0:       cond.end3331:
+// SIMD-ONLY0-NEXT:    [[COND3332:%.*]] = phi i64 [ [[TMP1630]], [[COND_TRUE3329]] ], [ [[TMP1631]], [[COND_FALSE3330]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3332]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1632:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1633:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3333:%.*]] = icmp eq i64 [[TMP1632]], [[TMP1633]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3333]], label [[IF_THEN3335:%.*]], label [[IF_END3336:%.*]]
+// SIMD-ONLY0:       if.then3335:
+// SIMD-ONLY0-NEXT:    [[TMP1634:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1634]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3336]]
+// SIMD-ONLY0:       if.end3336:
+// SIMD-ONLY0-NEXT:    [[TMP1635:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1636:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3337:%.*]] = icmp eq i64 [[TMP1635]], [[TMP1636]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3337]], label [[IF_THEN3339:%.*]], label [[IF_END3340:%.*]]
+// SIMD-ONLY0:       if.then3339:
+// SIMD-ONLY0-NEXT:    [[TMP1637:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1637]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3340]]
+// SIMD-ONLY0:       if.end3340:
+// SIMD-ONLY0-NEXT:    [[TMP1638:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1639:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3341:%.*]] = icmp ugt i64 [[TMP1638]], [[TMP1639]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3341]], label [[COND_TRUE3343:%.*]], label [[COND_FALSE3344:%.*]]
+// SIMD-ONLY0:       cond.true3343:
+// SIMD-ONLY0-NEXT:    [[TMP1640:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3345:%.*]]
+// SIMD-ONLY0:       cond.false3344:
+// SIMD-ONLY0-NEXT:    [[TMP1641:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3345]]
+// SIMD-ONLY0:       cond.end3345:
+// SIMD-ONLY0-NEXT:    [[COND3346:%.*]] = phi i64 [ [[TMP1640]], [[COND_TRUE3343]] ], [ [[TMP1641]], [[COND_FALSE3344]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3346]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1642:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1643:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3347:%.*]] = icmp ult i64 [[TMP1642]], [[TMP1643]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3347]], label [[COND_TRUE3349:%.*]], label [[COND_FALSE3350:%.*]]
+// SIMD-ONLY0:       cond.true3349:
+// SIMD-ONLY0-NEXT:    [[TMP1644:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3351:%.*]]
+// SIMD-ONLY0:       cond.false3350:
+// SIMD-ONLY0-NEXT:    [[TMP1645:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3351]]
+// SIMD-ONLY0:       cond.end3351:
+// SIMD-ONLY0-NEXT:    [[COND3352:%.*]] = phi i64 [ [[TMP1644]], [[COND_TRUE3349]] ], [ [[TMP1645]], [[COND_FALSE3350]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3352]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1646:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1647:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3353:%.*]] = icmp ugt i64 [[TMP1646]], [[TMP1647]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3353]], label [[COND_TRUE3355:%.*]], label [[COND_FALSE3356:%.*]]
+// SIMD-ONLY0:       cond.true3355:
+// SIMD-ONLY0-NEXT:    [[TMP1648:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3357:%.*]]
+// SIMD-ONLY0:       cond.false3356:
+// SIMD-ONLY0-NEXT:    [[TMP1649:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3357]]
+// SIMD-ONLY0:       cond.end3357:
+// SIMD-ONLY0-NEXT:    [[COND3358:%.*]] = phi i64 [ [[TMP1648]], [[COND_TRUE3355]] ], [ [[TMP1649]], [[COND_FALSE3356]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3358]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1650:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1651:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3359:%.*]] = icmp ult i64 [[TMP1650]], [[TMP1651]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3359]], label [[COND_TRUE3361:%.*]], label [[COND_FALSE3362:%.*]]
+// SIMD-ONLY0:       cond.true3361:
+// SIMD-ONLY0-NEXT:    [[TMP1652:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3363:%.*]]
+// SIMD-ONLY0:       cond.false3362:
+// SIMD-ONLY0-NEXT:    [[TMP1653:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3363]]
+// SIMD-ONLY0:       cond.end3363:
+// SIMD-ONLY0-NEXT:    [[COND3364:%.*]] = phi i64 [ [[TMP1652]], [[COND_TRUE3361]] ], [ [[TMP1653]], [[COND_FALSE3362]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3364]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1654:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1655:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3365:%.*]] = icmp ugt i64 [[TMP1654]], [[TMP1655]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3365]], label [[IF_THEN3367:%.*]], label [[IF_END3368:%.*]]
+// SIMD-ONLY0:       if.then3367:
+// SIMD-ONLY0-NEXT:    [[TMP1656:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1656]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3368]]
+// SIMD-ONLY0:       if.end3368:
+// SIMD-ONLY0-NEXT:    [[TMP1657:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1658:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3369:%.*]] = icmp ult i64 [[TMP1657]], [[TMP1658]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3369]], label [[IF_THEN3371:%.*]], label [[IF_END3372:%.*]]
+// SIMD-ONLY0:       if.then3371:
+// SIMD-ONLY0-NEXT:    [[TMP1659:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1659]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3372]]
+// SIMD-ONLY0:       if.end3372:
+// SIMD-ONLY0-NEXT:    [[TMP1660:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1661:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3373:%.*]] = icmp ugt i64 [[TMP1660]], [[TMP1661]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3373]], label [[IF_THEN3375:%.*]], label [[IF_END3376:%.*]]
+// SIMD-ONLY0:       if.then3375:
+// SIMD-ONLY0-NEXT:    [[TMP1662:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1662]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3376]]
+// SIMD-ONLY0:       if.end3376:
+// SIMD-ONLY0-NEXT:    [[TMP1663:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1664:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3377:%.*]] = icmp ult i64 [[TMP1663]], [[TMP1664]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3377]], label [[IF_THEN3379:%.*]], label [[IF_END3380:%.*]]
+// SIMD-ONLY0:       if.then3379:
+// SIMD-ONLY0-NEXT:    [[TMP1665:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1665]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3380]]
+// SIMD-ONLY0:       if.end3380:
+// SIMD-ONLY0-NEXT:    [[TMP1666:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1667:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3381:%.*]] = icmp eq i64 [[TMP1666]], [[TMP1667]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3381]], label [[COND_TRUE3383:%.*]], label [[COND_FALSE3384:%.*]]
+// SIMD-ONLY0:       cond.true3383:
+// SIMD-ONLY0-NEXT:    [[TMP1668:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3385:%.*]]
+// SIMD-ONLY0:       cond.false3384:
+// SIMD-ONLY0-NEXT:    [[TMP1669:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3385]]
+// SIMD-ONLY0:       cond.end3385:
+// SIMD-ONLY0-NEXT:    [[COND3386:%.*]] = phi i64 [ [[TMP1668]], [[COND_TRUE3383]] ], [ [[TMP1669]], [[COND_FALSE3384]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3386]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1670:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1671:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3387:%.*]] = icmp eq i64 [[TMP1670]], [[TMP1671]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3387]], label [[COND_TRUE3389:%.*]], label [[COND_FALSE3390:%.*]]
+// SIMD-ONLY0:       cond.true3389:
+// SIMD-ONLY0-NEXT:    [[TMP1672:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3391:%.*]]
+// SIMD-ONLY0:       cond.false3390:
+// SIMD-ONLY0-NEXT:    [[TMP1673:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3391]]
+// SIMD-ONLY0:       cond.end3391:
+// SIMD-ONLY0-NEXT:    [[COND3392:%.*]] = phi i64 [ [[TMP1672]], [[COND_TRUE3389]] ], [ [[TMP1673]], [[COND_FALSE3390]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3392]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1674:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1675:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3393:%.*]] = icmp eq i64 [[TMP1674]], [[TMP1675]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3393]], label [[IF_THEN3395:%.*]], label [[IF_END3396:%.*]]
+// SIMD-ONLY0:       if.then3395:
+// SIMD-ONLY0-NEXT:    [[TMP1676:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1676]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3396]]
+// SIMD-ONLY0:       if.end3396:
+// SIMD-ONLY0-NEXT:    [[TMP1677:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1678:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3397:%.*]] = icmp eq i64 [[TMP1677]], [[TMP1678]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3397]], label [[IF_THEN3399:%.*]], label [[IF_END3400:%.*]]
+// SIMD-ONLY0:       if.then3399:
+// SIMD-ONLY0-NEXT:    [[TMP1679:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1679]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3400]]
+// SIMD-ONLY0:       if.end3400:
+// SIMD-ONLY0-NEXT:    [[TMP1680:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1681:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3401:%.*]] = icmp sgt i64 [[TMP1680]], [[TMP1681]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3401]], label [[COND_TRUE3403:%.*]], label [[COND_FALSE3404:%.*]]
+// SIMD-ONLY0:       cond.true3403:
+// SIMD-ONLY0-NEXT:    [[TMP1682:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3405:%.*]]
+// SIMD-ONLY0:       cond.false3404:
+// SIMD-ONLY0-NEXT:    [[TMP1683:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3405]]
+// SIMD-ONLY0:       cond.end3405:
+// SIMD-ONLY0-NEXT:    [[COND3406:%.*]] = phi i64 [ [[TMP1682]], [[COND_TRUE3403]] ], [ [[TMP1683]], [[COND_FALSE3404]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3406]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1684:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1685:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3407:%.*]] = icmp slt i64 [[TMP1684]], [[TMP1685]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3407]], label [[COND_TRUE3409:%.*]], label [[COND_FALSE3410:%.*]]
+// SIMD-ONLY0:       cond.true3409:
+// SIMD-ONLY0-NEXT:    [[TMP1686:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3411:%.*]]
+// SIMD-ONLY0:       cond.false3410:
+// SIMD-ONLY0-NEXT:    [[TMP1687:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3411]]
+// SIMD-ONLY0:       cond.end3411:
+// SIMD-ONLY0-NEXT:    [[COND3412:%.*]] = phi i64 [ [[TMP1686]], [[COND_TRUE3409]] ], [ [[TMP1687]], [[COND_FALSE3410]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3412]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1688:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1689:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3413:%.*]] = icmp sgt i64 [[TMP1688]], [[TMP1689]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3413]], label [[COND_TRUE3415:%.*]], label [[COND_FALSE3416:%.*]]
+// SIMD-ONLY0:       cond.true3415:
+// SIMD-ONLY0-NEXT:    [[TMP1690:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3417:%.*]]
+// SIMD-ONLY0:       cond.false3416:
+// SIMD-ONLY0-NEXT:    [[TMP1691:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3417]]
+// SIMD-ONLY0:       cond.end3417:
+// SIMD-ONLY0-NEXT:    [[COND3418:%.*]] = phi i64 [ [[TMP1690]], [[COND_TRUE3415]] ], [ [[TMP1691]], [[COND_FALSE3416]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3418]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1692:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1693:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3419:%.*]] = icmp slt i64 [[TMP1692]], [[TMP1693]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3419]], label [[COND_TRUE3421:%.*]], label [[COND_FALSE3422:%.*]]
+// SIMD-ONLY0:       cond.true3421:
+// SIMD-ONLY0-NEXT:    [[TMP1694:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3423:%.*]]
+// SIMD-ONLY0:       cond.false3422:
+// SIMD-ONLY0-NEXT:    [[TMP1695:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3423]]
+// SIMD-ONLY0:       cond.end3423:
+// SIMD-ONLY0-NEXT:    [[COND3424:%.*]] = phi i64 [ [[TMP1694]], [[COND_TRUE3421]] ], [ [[TMP1695]], [[COND_FALSE3422]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3424]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1696:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1697:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3425:%.*]] = icmp sgt i64 [[TMP1696]], [[TMP1697]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3425]], label [[IF_THEN3427:%.*]], label [[IF_END3428:%.*]]
+// SIMD-ONLY0:       if.then3427:
+// SIMD-ONLY0-NEXT:    [[TMP1698:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1698]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3428]]
+// SIMD-ONLY0:       if.end3428:
+// SIMD-ONLY0-NEXT:    [[TMP1699:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1700:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3429:%.*]] = icmp slt i64 [[TMP1699]], [[TMP1700]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3429]], label [[IF_THEN3431:%.*]], label [[IF_END3432:%.*]]
+// SIMD-ONLY0:       if.then3431:
+// SIMD-ONLY0-NEXT:    [[TMP1701:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1701]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3432]]
+// SIMD-ONLY0:       if.end3432:
+// SIMD-ONLY0-NEXT:    [[TMP1702:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1703:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3433:%.*]] = icmp sgt i64 [[TMP1702]], [[TMP1703]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3433]], label [[IF_THEN3435:%.*]], label [[IF_END3436:%.*]]
+// SIMD-ONLY0:       if.then3435:
+// SIMD-ONLY0-NEXT:    [[TMP1704:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1704]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3436]]
+// SIMD-ONLY0:       if.end3436:
+// SIMD-ONLY0-NEXT:    [[TMP1705:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1706:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3437:%.*]] = icmp slt i64 [[TMP1705]], [[TMP1706]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3437]], label [[IF_THEN3439:%.*]], label [[IF_END3440:%.*]]
+// SIMD-ONLY0:       if.then3439:
+// SIMD-ONLY0-NEXT:    [[TMP1707:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1707]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3440]]
+// SIMD-ONLY0:       if.end3440:
+// SIMD-ONLY0-NEXT:    [[TMP1708:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1709:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3441:%.*]] = icmp eq i64 [[TMP1708]], [[TMP1709]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3441]], label [[COND_TRUE3443:%.*]], label [[COND_FALSE3444:%.*]]
+// SIMD-ONLY0:       cond.true3443:
+// SIMD-ONLY0-NEXT:    [[TMP1710:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3445:%.*]]
+// SIMD-ONLY0:       cond.false3444:
+// SIMD-ONLY0-NEXT:    [[TMP1711:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3445]]
+// SIMD-ONLY0:       cond.end3445:
+// SIMD-ONLY0-NEXT:    [[COND3446:%.*]] = phi i64 [ [[TMP1710]], [[COND_TRUE3443]] ], [ [[TMP1711]], [[COND_FALSE3444]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3446]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1712:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1713:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3447:%.*]] = icmp eq i64 [[TMP1712]], [[TMP1713]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3447]], label [[COND_TRUE3449:%.*]], label [[COND_FALSE3450:%.*]]
+// SIMD-ONLY0:       cond.true3449:
+// SIMD-ONLY0-NEXT:    [[TMP1714:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3451:%.*]]
+// SIMD-ONLY0:       cond.false3450:
+// SIMD-ONLY0-NEXT:    [[TMP1715:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3451]]
+// SIMD-ONLY0:       cond.end3451:
+// SIMD-ONLY0-NEXT:    [[COND3452:%.*]] = phi i64 [ [[TMP1714]], [[COND_TRUE3449]] ], [ [[TMP1715]], [[COND_FALSE3450]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3452]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1716:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1717:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3453:%.*]] = icmp eq i64 [[TMP1716]], [[TMP1717]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3453]], label [[IF_THEN3455:%.*]], label [[IF_END3456:%.*]]
+// SIMD-ONLY0:       if.then3455:
+// SIMD-ONLY0-NEXT:    [[TMP1718:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1718]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3456]]
+// SIMD-ONLY0:       if.end3456:
+// SIMD-ONLY0-NEXT:    [[TMP1719:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1720:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3457:%.*]] = icmp eq i64 [[TMP1719]], [[TMP1720]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3457]], label [[IF_THEN3459:%.*]], label [[IF_END3460:%.*]]
+// SIMD-ONLY0:       if.then3459:
+// SIMD-ONLY0-NEXT:    [[TMP1721:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1721]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3460]]
+// SIMD-ONLY0:       if.end3460:
+// SIMD-ONLY0-NEXT:    [[TMP1722:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1723:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3461:%.*]] = icmp ugt i64 [[TMP1722]], [[TMP1723]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3461]], label [[COND_TRUE3463:%.*]], label [[COND_FALSE3464:%.*]]
+// SIMD-ONLY0:       cond.true3463:
+// SIMD-ONLY0-NEXT:    [[TMP1724:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3465:%.*]]
+// SIMD-ONLY0:       cond.false3464:
+// SIMD-ONLY0-NEXT:    [[TMP1725:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3465]]
+// SIMD-ONLY0:       cond.end3465:
+// SIMD-ONLY0-NEXT:    [[COND3466:%.*]] = phi i64 [ [[TMP1724]], [[COND_TRUE3463]] ], [ [[TMP1725]], [[COND_FALSE3464]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3466]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1726:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1727:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3467:%.*]] = icmp ult i64 [[TMP1726]], [[TMP1727]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3467]], label [[COND_TRUE3469:%.*]], label [[COND_FALSE3470:%.*]]
+// SIMD-ONLY0:       cond.true3469:
+// SIMD-ONLY0-NEXT:    [[TMP1728:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3471:%.*]]
+// SIMD-ONLY0:       cond.false3470:
+// SIMD-ONLY0-NEXT:    [[TMP1729:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3471]]
+// SIMD-ONLY0:       cond.end3471:
+// SIMD-ONLY0-NEXT:    [[COND3472:%.*]] = phi i64 [ [[TMP1728]], [[COND_TRUE3469]] ], [ [[TMP1729]], [[COND_FALSE3470]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3472]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1730:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1731:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3473:%.*]] = icmp ugt i64 [[TMP1730]], [[TMP1731]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3473]], label [[COND_TRUE3475:%.*]], label [[COND_FALSE3476:%.*]]
+// SIMD-ONLY0:       cond.true3475:
+// SIMD-ONLY0-NEXT:    [[TMP1732:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3477:%.*]]
+// SIMD-ONLY0:       cond.false3476:
+// SIMD-ONLY0-NEXT:    [[TMP1733:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3477]]
+// SIMD-ONLY0:       cond.end3477:
+// SIMD-ONLY0-NEXT:    [[COND3478:%.*]] = phi i64 [ [[TMP1732]], [[COND_TRUE3475]] ], [ [[TMP1733]], [[COND_FALSE3476]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3478]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1734:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1735:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3479:%.*]] = icmp ult i64 [[TMP1734]], [[TMP1735]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3479]], label [[COND_TRUE3481:%.*]], label [[COND_FALSE3482:%.*]]
+// SIMD-ONLY0:       cond.true3481:
+// SIMD-ONLY0-NEXT:    [[TMP1736:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3483:%.*]]
+// SIMD-ONLY0:       cond.false3482:
+// SIMD-ONLY0-NEXT:    [[TMP1737:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3483]]
+// SIMD-ONLY0:       cond.end3483:
+// SIMD-ONLY0-NEXT:    [[COND3484:%.*]] = phi i64 [ [[TMP1736]], [[COND_TRUE3481]] ], [ [[TMP1737]], [[COND_FALSE3482]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3484]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1738:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1739:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3485:%.*]] = icmp ugt i64 [[TMP1738]], [[TMP1739]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3485]], label [[IF_THEN3487:%.*]], label [[IF_END3488:%.*]]
+// SIMD-ONLY0:       if.then3487:
+// SIMD-ONLY0-NEXT:    [[TMP1740:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1740]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3488]]
+// SIMD-ONLY0:       if.end3488:
+// SIMD-ONLY0-NEXT:    [[TMP1741:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1742:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3489:%.*]] = icmp ult i64 [[TMP1741]], [[TMP1742]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3489]], label [[IF_THEN3491:%.*]], label [[IF_END3492:%.*]]
+// SIMD-ONLY0:       if.then3491:
+// SIMD-ONLY0-NEXT:    [[TMP1743:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1743]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3492]]
+// SIMD-ONLY0:       if.end3492:
+// SIMD-ONLY0-NEXT:    [[TMP1744:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1745:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3493:%.*]] = icmp ugt i64 [[TMP1744]], [[TMP1745]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3493]], label [[IF_THEN3495:%.*]], label [[IF_END3496:%.*]]
+// SIMD-ONLY0:       if.then3495:
+// SIMD-ONLY0-NEXT:    [[TMP1746:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1746]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3496]]
+// SIMD-ONLY0:       if.end3496:
+// SIMD-ONLY0-NEXT:    [[TMP1747:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1748:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3497:%.*]] = icmp ult i64 [[TMP1747]], [[TMP1748]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3497]], label [[IF_THEN3499:%.*]], label [[IF_END3500:%.*]]
+// SIMD-ONLY0:       if.then3499:
+// SIMD-ONLY0-NEXT:    [[TMP1749:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1749]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3500]]
+// SIMD-ONLY0:       if.end3500:
+// SIMD-ONLY0-NEXT:    [[TMP1750:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1751:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3501:%.*]] = icmp eq i64 [[TMP1750]], [[TMP1751]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3501]], label [[COND_TRUE3503:%.*]], label [[COND_FALSE3504:%.*]]
+// SIMD-ONLY0:       cond.true3503:
+// SIMD-ONLY0-NEXT:    [[TMP1752:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3505:%.*]]
+// SIMD-ONLY0:       cond.false3504:
+// SIMD-ONLY0-NEXT:    [[TMP1753:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3505]]
+// SIMD-ONLY0:       cond.end3505:
+// SIMD-ONLY0-NEXT:    [[COND3506:%.*]] = phi i64 [ [[TMP1752]], [[COND_TRUE3503]] ], [ [[TMP1753]], [[COND_FALSE3504]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3506]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1754:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1755:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3507:%.*]] = icmp eq i64 [[TMP1754]], [[TMP1755]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3507]], label [[COND_TRUE3509:%.*]], label [[COND_FALSE3510:%.*]]
+// SIMD-ONLY0:       cond.true3509:
+// SIMD-ONLY0-NEXT:    [[TMP1756:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3511:%.*]]
+// SIMD-ONLY0:       cond.false3510:
+// SIMD-ONLY0-NEXT:    [[TMP1757:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3511]]
+// SIMD-ONLY0:       cond.end3511:
+// SIMD-ONLY0-NEXT:    [[COND3512:%.*]] = phi i64 [ [[TMP1756]], [[COND_TRUE3509]] ], [ [[TMP1757]], [[COND_FALSE3510]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3512]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1758:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1759:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3513:%.*]] = icmp eq i64 [[TMP1758]], [[TMP1759]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3513]], label [[IF_THEN3515:%.*]], label [[IF_END3516:%.*]]
+// SIMD-ONLY0:       if.then3515:
+// SIMD-ONLY0-NEXT:    [[TMP1760:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1760]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3516]]
+// SIMD-ONLY0:       if.end3516:
+// SIMD-ONLY0-NEXT:    [[TMP1761:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1762:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3517:%.*]] = icmp eq i64 [[TMP1761]], [[TMP1762]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3517]], label [[IF_THEN3519:%.*]], label [[IF_END3520:%.*]]
+// SIMD-ONLY0:       if.then3519:
+// SIMD-ONLY0-NEXT:    [[TMP1763:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1763]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3520]]
+// SIMD-ONLY0:       if.end3520:
+// SIMD-ONLY0-NEXT:    [[TMP1764:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1765:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3521:%.*]] = icmp sgt i64 [[TMP1764]], [[TMP1765]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3521]], label [[COND_TRUE3523:%.*]], label [[COND_FALSE3524:%.*]]
+// SIMD-ONLY0:       cond.true3523:
+// SIMD-ONLY0-NEXT:    [[TMP1766:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3525:%.*]]
+// SIMD-ONLY0:       cond.false3524:
+// SIMD-ONLY0-NEXT:    [[TMP1767:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3525]]
+// SIMD-ONLY0:       cond.end3525:
+// SIMD-ONLY0-NEXT:    [[COND3526:%.*]] = phi i64 [ [[TMP1766]], [[COND_TRUE3523]] ], [ [[TMP1767]], [[COND_FALSE3524]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3526]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1768:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1769:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3527:%.*]] = icmp slt i64 [[TMP1768]], [[TMP1769]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3527]], label [[COND_TRUE3529:%.*]], label [[COND_FALSE3530:%.*]]
+// SIMD-ONLY0:       cond.true3529:
+// SIMD-ONLY0-NEXT:    [[TMP1770:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3531:%.*]]
+// SIMD-ONLY0:       cond.false3530:
+// SIMD-ONLY0-NEXT:    [[TMP1771:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3531]]
+// SIMD-ONLY0:       cond.end3531:
+// SIMD-ONLY0-NEXT:    [[COND3532:%.*]] = phi i64 [ [[TMP1770]], [[COND_TRUE3529]] ], [ [[TMP1771]], [[COND_FALSE3530]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3532]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1772:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1773:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3533:%.*]] = icmp sgt i64 [[TMP1772]], [[TMP1773]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3533]], label [[COND_TRUE3535:%.*]], label [[COND_FALSE3536:%.*]]
+// SIMD-ONLY0:       cond.true3535:
+// SIMD-ONLY0-NEXT:    [[TMP1774:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3537:%.*]]
+// SIMD-ONLY0:       cond.false3536:
+// SIMD-ONLY0-NEXT:    [[TMP1775:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3537]]
+// SIMD-ONLY0:       cond.end3537:
+// SIMD-ONLY0-NEXT:    [[COND3538:%.*]] = phi i64 [ [[TMP1774]], [[COND_TRUE3535]] ], [ [[TMP1775]], [[COND_FALSE3536]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3538]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1776:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1777:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3539:%.*]] = icmp slt i64 [[TMP1776]], [[TMP1777]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3539]], label [[COND_TRUE3541:%.*]], label [[COND_FALSE3542:%.*]]
+// SIMD-ONLY0:       cond.true3541:
+// SIMD-ONLY0-NEXT:    [[TMP1778:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3543:%.*]]
+// SIMD-ONLY0:       cond.false3542:
+// SIMD-ONLY0-NEXT:    [[TMP1779:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3543]]
+// SIMD-ONLY0:       cond.end3543:
+// SIMD-ONLY0-NEXT:    [[COND3544:%.*]] = phi i64 [ [[TMP1778]], [[COND_TRUE3541]] ], [ [[TMP1779]], [[COND_FALSE3542]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3544]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1780:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1781:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3545:%.*]] = icmp sgt i64 [[TMP1780]], [[TMP1781]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3545]], label [[IF_THEN3547:%.*]], label [[IF_END3548:%.*]]
+// SIMD-ONLY0:       if.then3547:
+// SIMD-ONLY0-NEXT:    [[TMP1782:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1782]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3548]]
+// SIMD-ONLY0:       if.end3548:
+// SIMD-ONLY0-NEXT:    [[TMP1783:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1784:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3549:%.*]] = icmp slt i64 [[TMP1783]], [[TMP1784]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3549]], label [[IF_THEN3551:%.*]], label [[IF_END3552:%.*]]
+// SIMD-ONLY0:       if.then3551:
+// SIMD-ONLY0-NEXT:    [[TMP1785:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1785]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3552]]
+// SIMD-ONLY0:       if.end3552:
+// SIMD-ONLY0-NEXT:    [[TMP1786:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1787:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3553:%.*]] = icmp sgt i64 [[TMP1786]], [[TMP1787]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3553]], label [[IF_THEN3555:%.*]], label [[IF_END3556:%.*]]
+// SIMD-ONLY0:       if.then3555:
+// SIMD-ONLY0-NEXT:    [[TMP1788:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1788]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3556]]
+// SIMD-ONLY0:       if.end3556:
+// SIMD-ONLY0-NEXT:    [[TMP1789:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1790:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3557:%.*]] = icmp slt i64 [[TMP1789]], [[TMP1790]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3557]], label [[IF_THEN3559:%.*]], label [[IF_END3560:%.*]]
+// SIMD-ONLY0:       if.then3559:
+// SIMD-ONLY0-NEXT:    [[TMP1791:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1791]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3560]]
+// SIMD-ONLY0:       if.end3560:
+// SIMD-ONLY0-NEXT:    [[TMP1792:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1793:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3561:%.*]] = icmp eq i64 [[TMP1792]], [[TMP1793]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3561]], label [[COND_TRUE3563:%.*]], label [[COND_FALSE3564:%.*]]
+// SIMD-ONLY0:       cond.true3563:
+// SIMD-ONLY0-NEXT:    [[TMP1794:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3565:%.*]]
+// SIMD-ONLY0:       cond.false3564:
+// SIMD-ONLY0-NEXT:    [[TMP1795:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3565]]
+// SIMD-ONLY0:       cond.end3565:
+// SIMD-ONLY0-NEXT:    [[COND3566:%.*]] = phi i64 [ [[TMP1794]], [[COND_TRUE3563]] ], [ [[TMP1795]], [[COND_FALSE3564]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3566]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1796:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1797:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3567:%.*]] = icmp eq i64 [[TMP1796]], [[TMP1797]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3567]], label [[COND_TRUE3569:%.*]], label [[COND_FALSE3570:%.*]]
+// SIMD-ONLY0:       cond.true3569:
+// SIMD-ONLY0-NEXT:    [[TMP1798:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3571:%.*]]
+// SIMD-ONLY0:       cond.false3570:
+// SIMD-ONLY0-NEXT:    [[TMP1799:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3571]]
+// SIMD-ONLY0:       cond.end3571:
+// SIMD-ONLY0-NEXT:    [[COND3572:%.*]] = phi i64 [ [[TMP1798]], [[COND_TRUE3569]] ], [ [[TMP1799]], [[COND_FALSE3570]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3572]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1800:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1801:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3573:%.*]] = icmp eq i64 [[TMP1800]], [[TMP1801]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3573]], label [[IF_THEN3575:%.*]], label [[IF_END3576:%.*]]
+// SIMD-ONLY0:       if.then3575:
+// SIMD-ONLY0-NEXT:    [[TMP1802:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1802]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3576]]
+// SIMD-ONLY0:       if.end3576:
+// SIMD-ONLY0-NEXT:    [[TMP1803:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1804:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3577:%.*]] = icmp eq i64 [[TMP1803]], [[TMP1804]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3577]], label [[IF_THEN3579:%.*]], label [[IF_END3580:%.*]]
+// SIMD-ONLY0:       if.then3579:
+// SIMD-ONLY0-NEXT:    [[TMP1805:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1805]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3580]]
+// SIMD-ONLY0:       if.end3580:
+// SIMD-ONLY0-NEXT:    [[TMP1806:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1807:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3581:%.*]] = icmp ugt i64 [[TMP1806]], [[TMP1807]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3581]], label [[COND_TRUE3583:%.*]], label [[COND_FALSE3584:%.*]]
+// SIMD-ONLY0:       cond.true3583:
+// SIMD-ONLY0-NEXT:    [[TMP1808:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3585:%.*]]
+// SIMD-ONLY0:       cond.false3584:
+// SIMD-ONLY0-NEXT:    [[TMP1809:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3585]]
+// SIMD-ONLY0:       cond.end3585:
+// SIMD-ONLY0-NEXT:    [[COND3586:%.*]] = phi i64 [ [[TMP1808]], [[COND_TRUE3583]] ], [ [[TMP1809]], [[COND_FALSE3584]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3586]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1810:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1811:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3587:%.*]] = icmp ult i64 [[TMP1810]], [[TMP1811]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3587]], label [[COND_TRUE3589:%.*]], label [[COND_FALSE3590:%.*]]
+// SIMD-ONLY0:       cond.true3589:
+// SIMD-ONLY0-NEXT:    [[TMP1812:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3591:%.*]]
+// SIMD-ONLY0:       cond.false3590:
+// SIMD-ONLY0-NEXT:    [[TMP1813:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3591]]
+// SIMD-ONLY0:       cond.end3591:
+// SIMD-ONLY0-NEXT:    [[COND3592:%.*]] = phi i64 [ [[TMP1812]], [[COND_TRUE3589]] ], [ [[TMP1813]], [[COND_FALSE3590]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3592]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1814:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1815:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3593:%.*]] = icmp ugt i64 [[TMP1814]], [[TMP1815]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3593]], label [[COND_TRUE3595:%.*]], label [[COND_FALSE3596:%.*]]
+// SIMD-ONLY0:       cond.true3595:
+// SIMD-ONLY0-NEXT:    [[TMP1816:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3597:%.*]]
+// SIMD-ONLY0:       cond.false3596:
+// SIMD-ONLY0-NEXT:    [[TMP1817:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3597]]
+// SIMD-ONLY0:       cond.end3597:
+// SIMD-ONLY0-NEXT:    [[COND3598:%.*]] = phi i64 [ [[TMP1816]], [[COND_TRUE3595]] ], [ [[TMP1817]], [[COND_FALSE3596]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3598]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1818:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1819:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3599:%.*]] = icmp ult i64 [[TMP1818]], [[TMP1819]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3599]], label [[COND_TRUE3601:%.*]], label [[COND_FALSE3602:%.*]]
+// SIMD-ONLY0:       cond.true3601:
+// SIMD-ONLY0-NEXT:    [[TMP1820:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3603:%.*]]
+// SIMD-ONLY0:       cond.false3602:
+// SIMD-ONLY0-NEXT:    [[TMP1821:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3603]]
+// SIMD-ONLY0:       cond.end3603:
+// SIMD-ONLY0-NEXT:    [[COND3604:%.*]] = phi i64 [ [[TMP1820]], [[COND_TRUE3601]] ], [ [[TMP1821]], [[COND_FALSE3602]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3604]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1822:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1823:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3605:%.*]] = icmp ugt i64 [[TMP1822]], [[TMP1823]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3605]], label [[IF_THEN3607:%.*]], label [[IF_END3608:%.*]]
+// SIMD-ONLY0:       if.then3607:
+// SIMD-ONLY0-NEXT:    [[TMP1824:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1824]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3608]]
+// SIMD-ONLY0:       if.end3608:
+// SIMD-ONLY0-NEXT:    [[TMP1825:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1826:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3609:%.*]] = icmp ult i64 [[TMP1825]], [[TMP1826]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3609]], label [[IF_THEN3611:%.*]], label [[IF_END3612:%.*]]
+// SIMD-ONLY0:       if.then3611:
+// SIMD-ONLY0-NEXT:    [[TMP1827:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1827]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3612]]
+// SIMD-ONLY0:       if.end3612:
+// SIMD-ONLY0-NEXT:    [[TMP1828:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1829:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3613:%.*]] = icmp ugt i64 [[TMP1828]], [[TMP1829]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3613]], label [[IF_THEN3615:%.*]], label [[IF_END3616:%.*]]
+// SIMD-ONLY0:       if.then3615:
+// SIMD-ONLY0-NEXT:    [[TMP1830:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1830]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3616]]
+// SIMD-ONLY0:       if.end3616:
+// SIMD-ONLY0-NEXT:    [[TMP1831:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1832:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3617:%.*]] = icmp ult i64 [[TMP1831]], [[TMP1832]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3617]], label [[IF_THEN3619:%.*]], label [[IF_END3620:%.*]]
+// SIMD-ONLY0:       if.then3619:
+// SIMD-ONLY0-NEXT:    [[TMP1833:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1833]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3620]]
+// SIMD-ONLY0:       if.end3620:
+// SIMD-ONLY0-NEXT:    [[TMP1834:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1835:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3621:%.*]] = icmp eq i64 [[TMP1834]], [[TMP1835]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3621]], label [[COND_TRUE3623:%.*]], label [[COND_FALSE3624:%.*]]
+// SIMD-ONLY0:       cond.true3623:
+// SIMD-ONLY0-NEXT:    [[TMP1836:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3625:%.*]]
+// SIMD-ONLY0:       cond.false3624:
+// SIMD-ONLY0-NEXT:    [[TMP1837:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3625]]
+// SIMD-ONLY0:       cond.end3625:
+// SIMD-ONLY0-NEXT:    [[COND3626:%.*]] = phi i64 [ [[TMP1836]], [[COND_TRUE3623]] ], [ [[TMP1837]], [[COND_FALSE3624]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3626]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1838:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1839:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3627:%.*]] = icmp eq i64 [[TMP1838]], [[TMP1839]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3627]], label [[COND_TRUE3629:%.*]], label [[COND_FALSE3630:%.*]]
+// SIMD-ONLY0:       cond.true3629:
+// SIMD-ONLY0-NEXT:    [[TMP1840:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3631:%.*]]
+// SIMD-ONLY0:       cond.false3630:
+// SIMD-ONLY0-NEXT:    [[TMP1841:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3631]]
+// SIMD-ONLY0:       cond.end3631:
+// SIMD-ONLY0-NEXT:    [[COND3632:%.*]] = phi i64 [ [[TMP1840]], [[COND_TRUE3629]] ], [ [[TMP1841]], [[COND_FALSE3630]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3632]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1842:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1843:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3633:%.*]] = icmp eq i64 [[TMP1842]], [[TMP1843]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3633]], label [[IF_THEN3635:%.*]], label [[IF_END3636:%.*]]
+// SIMD-ONLY0:       if.then3635:
+// SIMD-ONLY0-NEXT:    [[TMP1844:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1844]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3636]]
+// SIMD-ONLY0:       if.end3636:
+// SIMD-ONLY0-NEXT:    [[TMP1845:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1846:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3637:%.*]] = icmp eq i64 [[TMP1845]], [[TMP1846]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3637]], label [[IF_THEN3639:%.*]], label [[IF_END3640:%.*]]
+// SIMD-ONLY0:       if.then3639:
+// SIMD-ONLY0-NEXT:    [[TMP1847:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1847]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3640]]
+// SIMD-ONLY0:       if.end3640:
+// SIMD-ONLY0-NEXT:    [[TMP1848:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1849:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3641:%.*]] = icmp sgt i64 [[TMP1848]], [[TMP1849]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3641]], label [[COND_TRUE3643:%.*]], label [[COND_FALSE3644:%.*]]
+// SIMD-ONLY0:       cond.true3643:
+// SIMD-ONLY0-NEXT:    [[TMP1850:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3645:%.*]]
+// SIMD-ONLY0:       cond.false3644:
+// SIMD-ONLY0-NEXT:    [[TMP1851:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3645]]
+// SIMD-ONLY0:       cond.end3645:
+// SIMD-ONLY0-NEXT:    [[COND3646:%.*]] = phi i64 [ [[TMP1850]], [[COND_TRUE3643]] ], [ [[TMP1851]], [[COND_FALSE3644]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3646]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1852:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1853:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3647:%.*]] = icmp slt i64 [[TMP1852]], [[TMP1853]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3647]], label [[COND_TRUE3649:%.*]], label [[COND_FALSE3650:%.*]]
+// SIMD-ONLY0:       cond.true3649:
+// SIMD-ONLY0-NEXT:    [[TMP1854:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3651:%.*]]
+// SIMD-ONLY0:       cond.false3650:
+// SIMD-ONLY0-NEXT:    [[TMP1855:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3651]]
+// SIMD-ONLY0:       cond.end3651:
+// SIMD-ONLY0-NEXT:    [[COND3652:%.*]] = phi i64 [ [[TMP1854]], [[COND_TRUE3649]] ], [ [[TMP1855]], [[COND_FALSE3650]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3652]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1856:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1857:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3653:%.*]] = icmp sgt i64 [[TMP1856]], [[TMP1857]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3653]], label [[COND_TRUE3655:%.*]], label [[COND_FALSE3656:%.*]]
+// SIMD-ONLY0:       cond.true3655:
+// SIMD-ONLY0-NEXT:    [[TMP1858:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3657:%.*]]
+// SIMD-ONLY0:       cond.false3656:
+// SIMD-ONLY0-NEXT:    [[TMP1859:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3657]]
+// SIMD-ONLY0:       cond.end3657:
+// SIMD-ONLY0-NEXT:    [[COND3658:%.*]] = phi i64 [ [[TMP1858]], [[COND_TRUE3655]] ], [ [[TMP1859]], [[COND_FALSE3656]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3658]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1860:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1861:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3659:%.*]] = icmp slt i64 [[TMP1860]], [[TMP1861]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3659]], label [[COND_TRUE3661:%.*]], label [[COND_FALSE3662:%.*]]
+// SIMD-ONLY0:       cond.true3661:
+// SIMD-ONLY0-NEXT:    [[TMP1862:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3663:%.*]]
+// SIMD-ONLY0:       cond.false3662:
+// SIMD-ONLY0-NEXT:    [[TMP1863:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3663]]
+// SIMD-ONLY0:       cond.end3663:
+// SIMD-ONLY0-NEXT:    [[COND3664:%.*]] = phi i64 [ [[TMP1862]], [[COND_TRUE3661]] ], [ [[TMP1863]], [[COND_FALSE3662]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3664]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1864:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1865:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3665:%.*]] = icmp sgt i64 [[TMP1864]], [[TMP1865]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3665]], label [[IF_THEN3667:%.*]], label [[IF_END3668:%.*]]
+// SIMD-ONLY0:       if.then3667:
+// SIMD-ONLY0-NEXT:    [[TMP1866:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1866]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3668]]
+// SIMD-ONLY0:       if.end3668:
+// SIMD-ONLY0-NEXT:    [[TMP1867:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1868:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3669:%.*]] = icmp slt i64 [[TMP1867]], [[TMP1868]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3669]], label [[IF_THEN3671:%.*]], label [[IF_END3672:%.*]]
+// SIMD-ONLY0:       if.then3671:
+// SIMD-ONLY0-NEXT:    [[TMP1869:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1869]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3672]]
+// SIMD-ONLY0:       if.end3672:
+// SIMD-ONLY0-NEXT:    [[TMP1870:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1871:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3673:%.*]] = icmp sgt i64 [[TMP1870]], [[TMP1871]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3673]], label [[IF_THEN3675:%.*]], label [[IF_END3676:%.*]]
+// SIMD-ONLY0:       if.then3675:
+// SIMD-ONLY0-NEXT:    [[TMP1872:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1872]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3676]]
+// SIMD-ONLY0:       if.end3676:
+// SIMD-ONLY0-NEXT:    [[TMP1873:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1874:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3677:%.*]] = icmp slt i64 [[TMP1873]], [[TMP1874]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3677]], label [[IF_THEN3679:%.*]], label [[IF_END3680:%.*]]
+// SIMD-ONLY0:       if.then3679:
+// SIMD-ONLY0-NEXT:    [[TMP1875:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1875]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3680]]
+// SIMD-ONLY0:       if.end3680:
+// SIMD-ONLY0-NEXT:    [[TMP1876:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1877:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3681:%.*]] = icmp eq i64 [[TMP1876]], [[TMP1877]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3681]], label [[COND_TRUE3683:%.*]], label [[COND_FALSE3684:%.*]]
+// SIMD-ONLY0:       cond.true3683:
+// SIMD-ONLY0-NEXT:    [[TMP1878:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3685:%.*]]
+// SIMD-ONLY0:       cond.false3684:
+// SIMD-ONLY0-NEXT:    [[TMP1879:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3685]]
+// SIMD-ONLY0:       cond.end3685:
+// SIMD-ONLY0-NEXT:    [[COND3686:%.*]] = phi i64 [ [[TMP1878]], [[COND_TRUE3683]] ], [ [[TMP1879]], [[COND_FALSE3684]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3686]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1880:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1881:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3687:%.*]] = icmp eq i64 [[TMP1880]], [[TMP1881]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3687]], label [[COND_TRUE3689:%.*]], label [[COND_FALSE3690:%.*]]
+// SIMD-ONLY0:       cond.true3689:
+// SIMD-ONLY0-NEXT:    [[TMP1882:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3691:%.*]]
+// SIMD-ONLY0:       cond.false3690:
+// SIMD-ONLY0-NEXT:    [[TMP1883:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3691]]
+// SIMD-ONLY0:       cond.end3691:
+// SIMD-ONLY0-NEXT:    [[COND3692:%.*]] = phi i64 [ [[TMP1882]], [[COND_TRUE3689]] ], [ [[TMP1883]], [[COND_FALSE3690]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3692]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1884:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1885:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3693:%.*]] = icmp eq i64 [[TMP1884]], [[TMP1885]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3693]], label [[IF_THEN3695:%.*]], label [[IF_END3696:%.*]]
+// SIMD-ONLY0:       if.then3695:
+// SIMD-ONLY0-NEXT:    [[TMP1886:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1886]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3696]]
+// SIMD-ONLY0:       if.end3696:
+// SIMD-ONLY0-NEXT:    [[TMP1887:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1888:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3697:%.*]] = icmp eq i64 [[TMP1887]], [[TMP1888]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3697]], label [[IF_THEN3699:%.*]], label [[IF_END3700:%.*]]
+// SIMD-ONLY0:       if.then3699:
+// SIMD-ONLY0-NEXT:    [[TMP1889:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1889]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3700]]
+// SIMD-ONLY0:       if.end3700:
+// SIMD-ONLY0-NEXT:    [[TMP1890:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1891:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3701:%.*]] = icmp ugt i64 [[TMP1890]], [[TMP1891]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3701]], label [[COND_TRUE3703:%.*]], label [[COND_FALSE3704:%.*]]
+// SIMD-ONLY0:       cond.true3703:
+// SIMD-ONLY0-NEXT:    [[TMP1892:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3705:%.*]]
+// SIMD-ONLY0:       cond.false3704:
+// SIMD-ONLY0-NEXT:    [[TMP1893:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3705]]
+// SIMD-ONLY0:       cond.end3705:
+// SIMD-ONLY0-NEXT:    [[COND3706:%.*]] = phi i64 [ [[TMP1892]], [[COND_TRUE3703]] ], [ [[TMP1893]], [[COND_FALSE3704]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3706]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1894:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1895:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3707:%.*]] = icmp ult i64 [[TMP1894]], [[TMP1895]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3707]], label [[COND_TRUE3709:%.*]], label [[COND_FALSE3710:%.*]]
+// SIMD-ONLY0:       cond.true3709:
+// SIMD-ONLY0-NEXT:    [[TMP1896:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3711:%.*]]
+// SIMD-ONLY0:       cond.false3710:
+// SIMD-ONLY0-NEXT:    [[TMP1897:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3711]]
+// SIMD-ONLY0:       cond.end3711:
+// SIMD-ONLY0-NEXT:    [[COND3712:%.*]] = phi i64 [ [[TMP1896]], [[COND_TRUE3709]] ], [ [[TMP1897]], [[COND_FALSE3710]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3712]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1898:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1899:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3713:%.*]] = icmp ugt i64 [[TMP1898]], [[TMP1899]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3713]], label [[COND_TRUE3715:%.*]], label [[COND_FALSE3716:%.*]]
+// SIMD-ONLY0:       cond.true3715:
+// SIMD-ONLY0-NEXT:    [[TMP1900:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3717:%.*]]
+// SIMD-ONLY0:       cond.false3716:
+// SIMD-ONLY0-NEXT:    [[TMP1901:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3717]]
+// SIMD-ONLY0:       cond.end3717:
+// SIMD-ONLY0-NEXT:    [[COND3718:%.*]] = phi i64 [ [[TMP1900]], [[COND_TRUE3715]] ], [ [[TMP1901]], [[COND_FALSE3716]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3718]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1902:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1903:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3719:%.*]] = icmp ult i64 [[TMP1902]], [[TMP1903]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3719]], label [[COND_TRUE3721:%.*]], label [[COND_FALSE3722:%.*]]
+// SIMD-ONLY0:       cond.true3721:
+// SIMD-ONLY0-NEXT:    [[TMP1904:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3723:%.*]]
+// SIMD-ONLY0:       cond.false3722:
+// SIMD-ONLY0-NEXT:    [[TMP1905:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3723]]
+// SIMD-ONLY0:       cond.end3723:
+// SIMD-ONLY0-NEXT:    [[COND3724:%.*]] = phi i64 [ [[TMP1904]], [[COND_TRUE3721]] ], [ [[TMP1905]], [[COND_FALSE3722]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3724]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1906:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1907:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3725:%.*]] = icmp ugt i64 [[TMP1906]], [[TMP1907]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3725]], label [[IF_THEN3727:%.*]], label [[IF_END3728:%.*]]
+// SIMD-ONLY0:       if.then3727:
+// SIMD-ONLY0-NEXT:    [[TMP1908:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1908]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3728]]
+// SIMD-ONLY0:       if.end3728:
+// SIMD-ONLY0-NEXT:    [[TMP1909:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1910:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3729:%.*]] = icmp ult i64 [[TMP1909]], [[TMP1910]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3729]], label [[IF_THEN3731:%.*]], label [[IF_END3732:%.*]]
+// SIMD-ONLY0:       if.then3731:
+// SIMD-ONLY0-NEXT:    [[TMP1911:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1911]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3732]]
+// SIMD-ONLY0:       if.end3732:
+// SIMD-ONLY0-NEXT:    [[TMP1912:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1913:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3733:%.*]] = icmp ugt i64 [[TMP1912]], [[TMP1913]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3733]], label [[IF_THEN3735:%.*]], label [[IF_END3736:%.*]]
+// SIMD-ONLY0:       if.then3735:
+// SIMD-ONLY0-NEXT:    [[TMP1914:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1914]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3736]]
+// SIMD-ONLY0:       if.end3736:
+// SIMD-ONLY0-NEXT:    [[TMP1915:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1916:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3737:%.*]] = icmp ult i64 [[TMP1915]], [[TMP1916]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3737]], label [[IF_THEN3739:%.*]], label [[IF_END3740:%.*]]
+// SIMD-ONLY0:       if.then3739:
+// SIMD-ONLY0-NEXT:    [[TMP1917:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1917]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3740]]
+// SIMD-ONLY0:       if.end3740:
+// SIMD-ONLY0-NEXT:    [[TMP1918:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1919:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3741:%.*]] = icmp eq i64 [[TMP1918]], [[TMP1919]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3741]], label [[COND_TRUE3743:%.*]], label [[COND_FALSE3744:%.*]]
+// SIMD-ONLY0:       cond.true3743:
+// SIMD-ONLY0-NEXT:    [[TMP1920:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3745:%.*]]
+// SIMD-ONLY0:       cond.false3744:
+// SIMD-ONLY0-NEXT:    [[TMP1921:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3745]]
+// SIMD-ONLY0:       cond.end3745:
+// SIMD-ONLY0-NEXT:    [[COND3746:%.*]] = phi i64 [ [[TMP1920]], [[COND_TRUE3743]] ], [ [[TMP1921]], [[COND_FALSE3744]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3746]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1922:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1923:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3747:%.*]] = icmp eq i64 [[TMP1922]], [[TMP1923]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3747]], label [[COND_TRUE3749:%.*]], label [[COND_FALSE3750:%.*]]
+// SIMD-ONLY0:       cond.true3749:
+// SIMD-ONLY0-NEXT:    [[TMP1924:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3751:%.*]]
+// SIMD-ONLY0:       cond.false3750:
+// SIMD-ONLY0-NEXT:    [[TMP1925:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3751]]
+// SIMD-ONLY0:       cond.end3751:
+// SIMD-ONLY0-NEXT:    [[COND3752:%.*]] = phi i64 [ [[TMP1924]], [[COND_TRUE3749]] ], [ [[TMP1925]], [[COND_FALSE3750]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3752]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1926:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1927:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3753:%.*]] = icmp eq i64 [[TMP1926]], [[TMP1927]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3753]], label [[IF_THEN3755:%.*]], label [[IF_END3756:%.*]]
+// SIMD-ONLY0:       if.then3755:
+// SIMD-ONLY0-NEXT:    [[TMP1928:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1928]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3756]]
+// SIMD-ONLY0:       if.end3756:
+// SIMD-ONLY0-NEXT:    [[TMP1929:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1930:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3757:%.*]] = icmp eq i64 [[TMP1929]], [[TMP1930]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3757]], label [[IF_THEN3759:%.*]], label [[IF_END3760:%.*]]
+// SIMD-ONLY0:       if.then3759:
+// SIMD-ONLY0-NEXT:    [[TMP1931:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1931]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3760]]
+// SIMD-ONLY0:       if.end3760:
+// SIMD-ONLY0-NEXT:    [[TMP1932:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1933:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3761:%.*]] = icmp sgt i64 [[TMP1932]], [[TMP1933]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3761]], label [[COND_TRUE3763:%.*]], label [[COND_FALSE3764:%.*]]
+// SIMD-ONLY0:       cond.true3763:
+// SIMD-ONLY0-NEXT:    [[TMP1934:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3765:%.*]]
+// SIMD-ONLY0:       cond.false3764:
+// SIMD-ONLY0-NEXT:    [[TMP1935:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3765]]
+// SIMD-ONLY0:       cond.end3765:
+// SIMD-ONLY0-NEXT:    [[COND3766:%.*]] = phi i64 [ [[TMP1934]], [[COND_TRUE3763]] ], [ [[TMP1935]], [[COND_FALSE3764]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3766]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1936:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1937:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3767:%.*]] = icmp slt i64 [[TMP1936]], [[TMP1937]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3767]], label [[COND_TRUE3769:%.*]], label [[COND_FALSE3770:%.*]]
+// SIMD-ONLY0:       cond.true3769:
+// SIMD-ONLY0-NEXT:    [[TMP1938:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3771:%.*]]
+// SIMD-ONLY0:       cond.false3770:
+// SIMD-ONLY0-NEXT:    [[TMP1939:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3771]]
+// SIMD-ONLY0:       cond.end3771:
+// SIMD-ONLY0-NEXT:    [[COND3772:%.*]] = phi i64 [ [[TMP1938]], [[COND_TRUE3769]] ], [ [[TMP1939]], [[COND_FALSE3770]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3772]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1940:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1941:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3773:%.*]] = icmp sgt i64 [[TMP1940]], [[TMP1941]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3773]], label [[COND_TRUE3775:%.*]], label [[COND_FALSE3776:%.*]]
+// SIMD-ONLY0:       cond.true3775:
+// SIMD-ONLY0-NEXT:    [[TMP1942:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3777:%.*]]
+// SIMD-ONLY0:       cond.false3776:
+// SIMD-ONLY0-NEXT:    [[TMP1943:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3777]]
+// SIMD-ONLY0:       cond.end3777:
+// SIMD-ONLY0-NEXT:    [[COND3778:%.*]] = phi i64 [ [[TMP1942]], [[COND_TRUE3775]] ], [ [[TMP1943]], [[COND_FALSE3776]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3778]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1944:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1945:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3779:%.*]] = icmp slt i64 [[TMP1944]], [[TMP1945]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3779]], label [[COND_TRUE3781:%.*]], label [[COND_FALSE3782:%.*]]
+// SIMD-ONLY0:       cond.true3781:
+// SIMD-ONLY0-NEXT:    [[TMP1946:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3783:%.*]]
+// SIMD-ONLY0:       cond.false3782:
+// SIMD-ONLY0-NEXT:    [[TMP1947:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3783]]
+// SIMD-ONLY0:       cond.end3783:
+// SIMD-ONLY0-NEXT:    [[COND3784:%.*]] = phi i64 [ [[TMP1946]], [[COND_TRUE3781]] ], [ [[TMP1947]], [[COND_FALSE3782]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3784]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1948:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1949:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3785:%.*]] = icmp sgt i64 [[TMP1948]], [[TMP1949]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3785]], label [[IF_THEN3787:%.*]], label [[IF_END3788:%.*]]
+// SIMD-ONLY0:       if.then3787:
+// SIMD-ONLY0-NEXT:    [[TMP1950:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1950]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3788]]
+// SIMD-ONLY0:       if.end3788:
+// SIMD-ONLY0-NEXT:    [[TMP1951:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1952:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3789:%.*]] = icmp slt i64 [[TMP1951]], [[TMP1952]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3789]], label [[IF_THEN3791:%.*]], label [[IF_END3792:%.*]]
+// SIMD-ONLY0:       if.then3791:
+// SIMD-ONLY0-NEXT:    [[TMP1953:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1953]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3792]]
+// SIMD-ONLY0:       if.end3792:
+// SIMD-ONLY0-NEXT:    [[TMP1954:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1955:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3793:%.*]] = icmp sgt i64 [[TMP1954]], [[TMP1955]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3793]], label [[IF_THEN3795:%.*]], label [[IF_END3796:%.*]]
+// SIMD-ONLY0:       if.then3795:
+// SIMD-ONLY0-NEXT:    [[TMP1956:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1956]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3796]]
+// SIMD-ONLY0:       if.end3796:
+// SIMD-ONLY0-NEXT:    [[TMP1957:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1958:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3797:%.*]] = icmp slt i64 [[TMP1957]], [[TMP1958]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3797]], label [[IF_THEN3799:%.*]], label [[IF_END3800:%.*]]
+// SIMD-ONLY0:       if.then3799:
+// SIMD-ONLY0-NEXT:    [[TMP1959:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1959]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3800]]
+// SIMD-ONLY0:       if.end3800:
+// SIMD-ONLY0-NEXT:    [[TMP1960:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1961:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3801:%.*]] = icmp eq i64 [[TMP1960]], [[TMP1961]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3801]], label [[COND_TRUE3803:%.*]], label [[COND_FALSE3804:%.*]]
+// SIMD-ONLY0:       cond.true3803:
+// SIMD-ONLY0-NEXT:    [[TMP1962:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3805:%.*]]
+// SIMD-ONLY0:       cond.false3804:
+// SIMD-ONLY0-NEXT:    [[TMP1963:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3805]]
+// SIMD-ONLY0:       cond.end3805:
+// SIMD-ONLY0-NEXT:    [[COND3806:%.*]] = phi i64 [ [[TMP1962]], [[COND_TRUE3803]] ], [ [[TMP1963]], [[COND_FALSE3804]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3806]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1964:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1965:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3807:%.*]] = icmp eq i64 [[TMP1964]], [[TMP1965]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3807]], label [[COND_TRUE3809:%.*]], label [[COND_FALSE3810:%.*]]
+// SIMD-ONLY0:       cond.true3809:
+// SIMD-ONLY0-NEXT:    [[TMP1966:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3811:%.*]]
+// SIMD-ONLY0:       cond.false3810:
+// SIMD-ONLY0-NEXT:    [[TMP1967:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3811]]
+// SIMD-ONLY0:       cond.end3811:
+// SIMD-ONLY0-NEXT:    [[COND3812:%.*]] = phi i64 [ [[TMP1966]], [[COND_TRUE3809]] ], [ [[TMP1967]], [[COND_FALSE3810]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3812]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1968:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1969:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3813:%.*]] = icmp eq i64 [[TMP1968]], [[TMP1969]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3813]], label [[IF_THEN3815:%.*]], label [[IF_END3816:%.*]]
+// SIMD-ONLY0:       if.then3815:
+// SIMD-ONLY0-NEXT:    [[TMP1970:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1970]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3816]]
+// SIMD-ONLY0:       if.end3816:
+// SIMD-ONLY0-NEXT:    [[TMP1971:%.*]] = load i64, i64* [[LE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1972:%.*]] = load i64, i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3817:%.*]] = icmp eq i64 [[TMP1971]], [[TMP1972]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3817]], label [[IF_THEN3819:%.*]], label [[IF_END3820:%.*]]
+// SIMD-ONLY0:       if.then3819:
+// SIMD-ONLY0-NEXT:    [[TMP1973:%.*]] = load i64, i64* [[LD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1973]], i64* [[LX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3820]]
+// SIMD-ONLY0:       if.end3820:
+// SIMD-ONLY0-NEXT:    [[TMP1974:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1975:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3821:%.*]] = icmp ugt i64 [[TMP1974]], [[TMP1975]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3821]], label [[COND_TRUE3823:%.*]], label [[COND_FALSE3824:%.*]]
+// SIMD-ONLY0:       cond.true3823:
+// SIMD-ONLY0-NEXT:    [[TMP1976:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3825:%.*]]
+// SIMD-ONLY0:       cond.false3824:
+// SIMD-ONLY0-NEXT:    [[TMP1977:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3825]]
+// SIMD-ONLY0:       cond.end3825:
+// SIMD-ONLY0-NEXT:    [[COND3826:%.*]] = phi i64 [ [[TMP1976]], [[COND_TRUE3823]] ], [ [[TMP1977]], [[COND_FALSE3824]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3826]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1978:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1979:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3827:%.*]] = icmp ult i64 [[TMP1978]], [[TMP1979]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3827]], label [[COND_TRUE3829:%.*]], label [[COND_FALSE3830:%.*]]
+// SIMD-ONLY0:       cond.true3829:
+// SIMD-ONLY0-NEXT:    [[TMP1980:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3831:%.*]]
+// SIMD-ONLY0:       cond.false3830:
+// SIMD-ONLY0-NEXT:    [[TMP1981:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3831]]
+// SIMD-ONLY0:       cond.end3831:
+// SIMD-ONLY0-NEXT:    [[COND3832:%.*]] = phi i64 [ [[TMP1980]], [[COND_TRUE3829]] ], [ [[TMP1981]], [[COND_FALSE3830]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3832]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1982:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1983:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3833:%.*]] = icmp ugt i64 [[TMP1982]], [[TMP1983]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3833]], label [[COND_TRUE3835:%.*]], label [[COND_FALSE3836:%.*]]
+// SIMD-ONLY0:       cond.true3835:
+// SIMD-ONLY0-NEXT:    [[TMP1984:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3837:%.*]]
+// SIMD-ONLY0:       cond.false3836:
+// SIMD-ONLY0-NEXT:    [[TMP1985:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3837]]
+// SIMD-ONLY0:       cond.end3837:
+// SIMD-ONLY0-NEXT:    [[COND3838:%.*]] = phi i64 [ [[TMP1984]], [[COND_TRUE3835]] ], [ [[TMP1985]], [[COND_FALSE3836]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3838]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1986:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1987:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3839:%.*]] = icmp ult i64 [[TMP1986]], [[TMP1987]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3839]], label [[COND_TRUE3841:%.*]], label [[COND_FALSE3842:%.*]]
+// SIMD-ONLY0:       cond.true3841:
+// SIMD-ONLY0-NEXT:    [[TMP1988:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3843:%.*]]
+// SIMD-ONLY0:       cond.false3842:
+// SIMD-ONLY0-NEXT:    [[TMP1989:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3843]]
+// SIMD-ONLY0:       cond.end3843:
+// SIMD-ONLY0-NEXT:    [[COND3844:%.*]] = phi i64 [ [[TMP1988]], [[COND_TRUE3841]] ], [ [[TMP1989]], [[COND_FALSE3842]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3844]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1990:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1991:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3845:%.*]] = icmp ugt i64 [[TMP1990]], [[TMP1991]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3845]], label [[IF_THEN3847:%.*]], label [[IF_END3848:%.*]]
+// SIMD-ONLY0:       if.then3847:
+// SIMD-ONLY0-NEXT:    [[TMP1992:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1992]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3848]]
+// SIMD-ONLY0:       if.end3848:
+// SIMD-ONLY0-NEXT:    [[TMP1993:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1994:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3849:%.*]] = icmp ult i64 [[TMP1993]], [[TMP1994]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3849]], label [[IF_THEN3851:%.*]], label [[IF_END3852:%.*]]
+// SIMD-ONLY0:       if.then3851:
+// SIMD-ONLY0-NEXT:    [[TMP1995:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1995]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3852]]
+// SIMD-ONLY0:       if.end3852:
+// SIMD-ONLY0-NEXT:    [[TMP1996:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP1997:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3853:%.*]] = icmp ugt i64 [[TMP1996]], [[TMP1997]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3853]], label [[IF_THEN3855:%.*]], label [[IF_END3856:%.*]]
+// SIMD-ONLY0:       if.then3855:
+// SIMD-ONLY0-NEXT:    [[TMP1998:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP1998]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3856]]
+// SIMD-ONLY0:       if.end3856:
+// SIMD-ONLY0-NEXT:    [[TMP1999:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2000:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3857:%.*]] = icmp ult i64 [[TMP1999]], [[TMP2000]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3857]], label [[IF_THEN3859:%.*]], label [[IF_END3860:%.*]]
+// SIMD-ONLY0:       if.then3859:
+// SIMD-ONLY0-NEXT:    [[TMP2001:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2001]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3860]]
+// SIMD-ONLY0:       if.end3860:
+// SIMD-ONLY0-NEXT:    [[TMP2002:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2003:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3861:%.*]] = icmp eq i64 [[TMP2002]], [[TMP2003]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3861]], label [[COND_TRUE3863:%.*]], label [[COND_FALSE3864:%.*]]
+// SIMD-ONLY0:       cond.true3863:
+// SIMD-ONLY0-NEXT:    [[TMP2004:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3865:%.*]]
+// SIMD-ONLY0:       cond.false3864:
+// SIMD-ONLY0-NEXT:    [[TMP2005:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3865]]
+// SIMD-ONLY0:       cond.end3865:
+// SIMD-ONLY0-NEXT:    [[COND3866:%.*]] = phi i64 [ [[TMP2004]], [[COND_TRUE3863]] ], [ [[TMP2005]], [[COND_FALSE3864]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3866]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2006:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2007:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3867:%.*]] = icmp eq i64 [[TMP2006]], [[TMP2007]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3867]], label [[COND_TRUE3869:%.*]], label [[COND_FALSE3870:%.*]]
+// SIMD-ONLY0:       cond.true3869:
+// SIMD-ONLY0-NEXT:    [[TMP2008:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3871:%.*]]
+// SIMD-ONLY0:       cond.false3870:
+// SIMD-ONLY0-NEXT:    [[TMP2009:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3871]]
+// SIMD-ONLY0:       cond.end3871:
+// SIMD-ONLY0-NEXT:    [[COND3872:%.*]] = phi i64 [ [[TMP2008]], [[COND_TRUE3869]] ], [ [[TMP2009]], [[COND_FALSE3870]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3872]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2010:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2011:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3873:%.*]] = icmp eq i64 [[TMP2010]], [[TMP2011]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3873]], label [[IF_THEN3875:%.*]], label [[IF_END3876:%.*]]
+// SIMD-ONLY0:       if.then3875:
+// SIMD-ONLY0-NEXT:    [[TMP2012:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2012]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3876]]
+// SIMD-ONLY0:       if.end3876:
+// SIMD-ONLY0-NEXT:    [[TMP2013:%.*]] = load i64, i64* [[ULE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2014:%.*]] = load i64, i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3877:%.*]] = icmp eq i64 [[TMP2013]], [[TMP2014]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3877]], label [[IF_THEN3879:%.*]], label [[IF_END3880:%.*]]
+// SIMD-ONLY0:       if.then3879:
+// SIMD-ONLY0-NEXT:    [[TMP2015:%.*]] = load i64, i64* [[ULD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2015]], i64* [[ULX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3880]]
+// SIMD-ONLY0:       if.end3880:
+// SIMD-ONLY0-NEXT:    [[TMP2016:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2017:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3881:%.*]] = icmp sgt i64 [[TMP2016]], [[TMP2017]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3881]], label [[COND_TRUE3883:%.*]], label [[COND_FALSE3884:%.*]]
+// SIMD-ONLY0:       cond.true3883:
+// SIMD-ONLY0-NEXT:    [[TMP2018:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3885:%.*]]
+// SIMD-ONLY0:       cond.false3884:
+// SIMD-ONLY0-NEXT:    [[TMP2019:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3885]]
+// SIMD-ONLY0:       cond.end3885:
+// SIMD-ONLY0-NEXT:    [[COND3886:%.*]] = phi i64 [ [[TMP2018]], [[COND_TRUE3883]] ], [ [[TMP2019]], [[COND_FALSE3884]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3886]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2020:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2021:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3887:%.*]] = icmp slt i64 [[TMP2020]], [[TMP2021]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3887]], label [[COND_TRUE3889:%.*]], label [[COND_FALSE3890:%.*]]
+// SIMD-ONLY0:       cond.true3889:
+// SIMD-ONLY0-NEXT:    [[TMP2022:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3891:%.*]]
+// SIMD-ONLY0:       cond.false3890:
+// SIMD-ONLY0-NEXT:    [[TMP2023:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3891]]
+// SIMD-ONLY0:       cond.end3891:
+// SIMD-ONLY0-NEXT:    [[COND3892:%.*]] = phi i64 [ [[TMP2022]], [[COND_TRUE3889]] ], [ [[TMP2023]], [[COND_FALSE3890]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3892]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2024:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2025:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3893:%.*]] = icmp sgt i64 [[TMP2024]], [[TMP2025]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3893]], label [[COND_TRUE3895:%.*]], label [[COND_FALSE3896:%.*]]
+// SIMD-ONLY0:       cond.true3895:
+// SIMD-ONLY0-NEXT:    [[TMP2026:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3897:%.*]]
+// SIMD-ONLY0:       cond.false3896:
+// SIMD-ONLY0-NEXT:    [[TMP2027:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3897]]
+// SIMD-ONLY0:       cond.end3897:
+// SIMD-ONLY0-NEXT:    [[COND3898:%.*]] = phi i64 [ [[TMP2026]], [[COND_TRUE3895]] ], [ [[TMP2027]], [[COND_FALSE3896]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3898]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2028:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2029:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3899:%.*]] = icmp slt i64 [[TMP2028]], [[TMP2029]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3899]], label [[COND_TRUE3901:%.*]], label [[COND_FALSE3902:%.*]]
+// SIMD-ONLY0:       cond.true3901:
+// SIMD-ONLY0-NEXT:    [[TMP2030:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3903:%.*]]
+// SIMD-ONLY0:       cond.false3902:
+// SIMD-ONLY0-NEXT:    [[TMP2031:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3903]]
+// SIMD-ONLY0:       cond.end3903:
+// SIMD-ONLY0-NEXT:    [[COND3904:%.*]] = phi i64 [ [[TMP2030]], [[COND_TRUE3901]] ], [ [[TMP2031]], [[COND_FALSE3902]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3904]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2032:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2033:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3905:%.*]] = icmp sgt i64 [[TMP2032]], [[TMP2033]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3905]], label [[IF_THEN3907:%.*]], label [[IF_END3908:%.*]]
+// SIMD-ONLY0:       if.then3907:
+// SIMD-ONLY0-NEXT:    [[TMP2034:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2034]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3908]]
+// SIMD-ONLY0:       if.end3908:
+// SIMD-ONLY0-NEXT:    [[TMP2035:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2036:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3909:%.*]] = icmp slt i64 [[TMP2035]], [[TMP2036]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3909]], label [[IF_THEN3911:%.*]], label [[IF_END3912:%.*]]
+// SIMD-ONLY0:       if.then3911:
+// SIMD-ONLY0-NEXT:    [[TMP2037:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2037]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3912]]
+// SIMD-ONLY0:       if.end3912:
+// SIMD-ONLY0-NEXT:    [[TMP2038:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2039:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3913:%.*]] = icmp sgt i64 [[TMP2038]], [[TMP2039]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3913]], label [[IF_THEN3915:%.*]], label [[IF_END3916:%.*]]
+// SIMD-ONLY0:       if.then3915:
+// SIMD-ONLY0-NEXT:    [[TMP2040:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2040]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3916]]
+// SIMD-ONLY0:       if.end3916:
+// SIMD-ONLY0-NEXT:    [[TMP2041:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2042:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3917:%.*]] = icmp slt i64 [[TMP2041]], [[TMP2042]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3917]], label [[IF_THEN3919:%.*]], label [[IF_END3920:%.*]]
+// SIMD-ONLY0:       if.then3919:
+// SIMD-ONLY0-NEXT:    [[TMP2043:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2043]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3920]]
+// SIMD-ONLY0:       if.end3920:
+// SIMD-ONLY0-NEXT:    [[TMP2044:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2045:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3921:%.*]] = icmp eq i64 [[TMP2044]], [[TMP2045]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3921]], label [[COND_TRUE3923:%.*]], label [[COND_FALSE3924:%.*]]
+// SIMD-ONLY0:       cond.true3923:
+// SIMD-ONLY0-NEXT:    [[TMP2046:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3925:%.*]]
+// SIMD-ONLY0:       cond.false3924:
+// SIMD-ONLY0-NEXT:    [[TMP2047:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3925]]
+// SIMD-ONLY0:       cond.end3925:
+// SIMD-ONLY0-NEXT:    [[COND3926:%.*]] = phi i64 [ [[TMP2046]], [[COND_TRUE3923]] ], [ [[TMP2047]], [[COND_FALSE3924]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3926]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2048:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2049:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3927:%.*]] = icmp eq i64 [[TMP2048]], [[TMP2049]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3927]], label [[COND_TRUE3929:%.*]], label [[COND_FALSE3930:%.*]]
+// SIMD-ONLY0:       cond.true3929:
+// SIMD-ONLY0-NEXT:    [[TMP2050:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3931:%.*]]
+// SIMD-ONLY0:       cond.false3930:
+// SIMD-ONLY0-NEXT:    [[TMP2051:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3931]]
+// SIMD-ONLY0:       cond.end3931:
+// SIMD-ONLY0-NEXT:    [[COND3932:%.*]] = phi i64 [ [[TMP2050]], [[COND_TRUE3929]] ], [ [[TMP2051]], [[COND_FALSE3930]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3932]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2052:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2053:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3933:%.*]] = icmp eq i64 [[TMP2052]], [[TMP2053]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3933]], label [[IF_THEN3935:%.*]], label [[IF_END3936:%.*]]
+// SIMD-ONLY0:       if.then3935:
+// SIMD-ONLY0-NEXT:    [[TMP2054:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2054]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3936]]
+// SIMD-ONLY0:       if.end3936:
+// SIMD-ONLY0-NEXT:    [[TMP2055:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2056:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3937:%.*]] = icmp eq i64 [[TMP2055]], [[TMP2056]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3937]], label [[IF_THEN3939:%.*]], label [[IF_END3940:%.*]]
+// SIMD-ONLY0:       if.then3939:
+// SIMD-ONLY0-NEXT:    [[TMP2057:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2057]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3940]]
+// SIMD-ONLY0:       if.end3940:
+// SIMD-ONLY0-NEXT:    [[TMP2058:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2059:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3941:%.*]] = icmp ugt i64 [[TMP2058]], [[TMP2059]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3941]], label [[COND_TRUE3943:%.*]], label [[COND_FALSE3944:%.*]]
+// SIMD-ONLY0:       cond.true3943:
+// SIMD-ONLY0-NEXT:    [[TMP2060:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3945:%.*]]
+// SIMD-ONLY0:       cond.false3944:
+// SIMD-ONLY0-NEXT:    [[TMP2061:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3945]]
+// SIMD-ONLY0:       cond.end3945:
+// SIMD-ONLY0-NEXT:    [[COND3946:%.*]] = phi i64 [ [[TMP2060]], [[COND_TRUE3943]] ], [ [[TMP2061]], [[COND_FALSE3944]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3946]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2062:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2063:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3947:%.*]] = icmp ult i64 [[TMP2062]], [[TMP2063]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3947]], label [[COND_TRUE3949:%.*]], label [[COND_FALSE3950:%.*]]
+// SIMD-ONLY0:       cond.true3949:
+// SIMD-ONLY0-NEXT:    [[TMP2064:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3951:%.*]]
+// SIMD-ONLY0:       cond.false3950:
+// SIMD-ONLY0-NEXT:    [[TMP2065:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3951]]
+// SIMD-ONLY0:       cond.end3951:
+// SIMD-ONLY0-NEXT:    [[COND3952:%.*]] = phi i64 [ [[TMP2064]], [[COND_TRUE3949]] ], [ [[TMP2065]], [[COND_FALSE3950]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3952]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2066:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2067:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3953:%.*]] = icmp ugt i64 [[TMP2066]], [[TMP2067]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3953]], label [[COND_TRUE3955:%.*]], label [[COND_FALSE3956:%.*]]
+// SIMD-ONLY0:       cond.true3955:
+// SIMD-ONLY0-NEXT:    [[TMP2068:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3957:%.*]]
+// SIMD-ONLY0:       cond.false3956:
+// SIMD-ONLY0-NEXT:    [[TMP2069:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3957]]
+// SIMD-ONLY0:       cond.end3957:
+// SIMD-ONLY0-NEXT:    [[COND3958:%.*]] = phi i64 [ [[TMP2068]], [[COND_TRUE3955]] ], [ [[TMP2069]], [[COND_FALSE3956]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3958]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2070:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2071:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3959:%.*]] = icmp ult i64 [[TMP2070]], [[TMP2071]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3959]], label [[COND_TRUE3961:%.*]], label [[COND_FALSE3962:%.*]]
+// SIMD-ONLY0:       cond.true3961:
+// SIMD-ONLY0-NEXT:    [[TMP2072:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3963:%.*]]
+// SIMD-ONLY0:       cond.false3962:
+// SIMD-ONLY0-NEXT:    [[TMP2073:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3963]]
+// SIMD-ONLY0:       cond.end3963:
+// SIMD-ONLY0-NEXT:    [[COND3964:%.*]] = phi i64 [ [[TMP2072]], [[COND_TRUE3961]] ], [ [[TMP2073]], [[COND_FALSE3962]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3964]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2074:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2075:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3965:%.*]] = icmp ugt i64 [[TMP2074]], [[TMP2075]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3965]], label [[IF_THEN3967:%.*]], label [[IF_END3968:%.*]]
+// SIMD-ONLY0:       if.then3967:
+// SIMD-ONLY0-NEXT:    [[TMP2076:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2076]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3968]]
+// SIMD-ONLY0:       if.end3968:
+// SIMD-ONLY0-NEXT:    [[TMP2077:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2078:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3969:%.*]] = icmp ult i64 [[TMP2077]], [[TMP2078]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3969]], label [[IF_THEN3971:%.*]], label [[IF_END3972:%.*]]
+// SIMD-ONLY0:       if.then3971:
+// SIMD-ONLY0-NEXT:    [[TMP2079:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2079]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3972]]
+// SIMD-ONLY0:       if.end3972:
+// SIMD-ONLY0-NEXT:    [[TMP2080:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2081:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3973:%.*]] = icmp ugt i64 [[TMP2080]], [[TMP2081]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3973]], label [[IF_THEN3975:%.*]], label [[IF_END3976:%.*]]
+// SIMD-ONLY0:       if.then3975:
+// SIMD-ONLY0-NEXT:    [[TMP2082:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2082]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3976]]
+// SIMD-ONLY0:       if.end3976:
+// SIMD-ONLY0-NEXT:    [[TMP2083:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2084:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3977:%.*]] = icmp ult i64 [[TMP2083]], [[TMP2084]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3977]], label [[IF_THEN3979:%.*]], label [[IF_END3980:%.*]]
+// SIMD-ONLY0:       if.then3979:
+// SIMD-ONLY0-NEXT:    [[TMP2085:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2085]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3980]]
+// SIMD-ONLY0:       if.end3980:
+// SIMD-ONLY0-NEXT:    [[TMP2086:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2087:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3981:%.*]] = icmp eq i64 [[TMP2086]], [[TMP2087]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3981]], label [[COND_TRUE3983:%.*]], label [[COND_FALSE3984:%.*]]
+// SIMD-ONLY0:       cond.true3983:
+// SIMD-ONLY0-NEXT:    [[TMP2088:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3985:%.*]]
+// SIMD-ONLY0:       cond.false3984:
+// SIMD-ONLY0-NEXT:    [[TMP2089:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3985]]
+// SIMD-ONLY0:       cond.end3985:
+// SIMD-ONLY0-NEXT:    [[COND3986:%.*]] = phi i64 [ [[TMP2088]], [[COND_TRUE3983]] ], [ [[TMP2089]], [[COND_FALSE3984]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3986]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2090:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2091:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3987:%.*]] = icmp eq i64 [[TMP2090]], [[TMP2091]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3987]], label [[COND_TRUE3989:%.*]], label [[COND_FALSE3990:%.*]]
+// SIMD-ONLY0:       cond.true3989:
+// SIMD-ONLY0-NEXT:    [[TMP2092:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3991:%.*]]
+// SIMD-ONLY0:       cond.false3990:
+// SIMD-ONLY0-NEXT:    [[TMP2093:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END3991]]
+// SIMD-ONLY0:       cond.end3991:
+// SIMD-ONLY0-NEXT:    [[COND3992:%.*]] = phi i64 [ [[TMP2092]], [[COND_TRUE3989]] ], [ [[TMP2093]], [[COND_FALSE3990]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND3992]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2094:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2095:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3993:%.*]] = icmp eq i64 [[TMP2094]], [[TMP2095]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3993]], label [[IF_THEN3995:%.*]], label [[IF_END3996:%.*]]
+// SIMD-ONLY0:       if.then3995:
+// SIMD-ONLY0-NEXT:    [[TMP2096:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2096]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END3996]]
+// SIMD-ONLY0:       if.end3996:
+// SIMD-ONLY0-NEXT:    [[TMP2097:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2098:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP3997:%.*]] = icmp eq i64 [[TMP2097]], [[TMP2098]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP3997]], label [[IF_THEN3999:%.*]], label [[IF_END4000:%.*]]
+// SIMD-ONLY0:       if.then3999:
+// SIMD-ONLY0-NEXT:    [[TMP2099:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2099]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4000]]
+// SIMD-ONLY0:       if.end4000:
+// SIMD-ONLY0-NEXT:    [[TMP2100:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2101:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4001:%.*]] = icmp sgt i64 [[TMP2100]], [[TMP2101]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4001]], label [[COND_TRUE4003:%.*]], label [[COND_FALSE4004:%.*]]
+// SIMD-ONLY0:       cond.true4003:
+// SIMD-ONLY0-NEXT:    [[TMP2102:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4005:%.*]]
+// SIMD-ONLY0:       cond.false4004:
+// SIMD-ONLY0-NEXT:    [[TMP2103:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4005]]
+// SIMD-ONLY0:       cond.end4005:
+// SIMD-ONLY0-NEXT:    [[COND4006:%.*]] = phi i64 [ [[TMP2102]], [[COND_TRUE4003]] ], [ [[TMP2103]], [[COND_FALSE4004]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4006]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2104:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2105:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4007:%.*]] = icmp slt i64 [[TMP2104]], [[TMP2105]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4007]], label [[COND_TRUE4009:%.*]], label [[COND_FALSE4010:%.*]]
+// SIMD-ONLY0:       cond.true4009:
+// SIMD-ONLY0-NEXT:    [[TMP2106:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4011:%.*]]
+// SIMD-ONLY0:       cond.false4010:
+// SIMD-ONLY0-NEXT:    [[TMP2107:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4011]]
+// SIMD-ONLY0:       cond.end4011:
+// SIMD-ONLY0-NEXT:    [[COND4012:%.*]] = phi i64 [ [[TMP2106]], [[COND_TRUE4009]] ], [ [[TMP2107]], [[COND_FALSE4010]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4012]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2108:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2109:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4013:%.*]] = icmp sgt i64 [[TMP2108]], [[TMP2109]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4013]], label [[COND_TRUE4015:%.*]], label [[COND_FALSE4016:%.*]]
+// SIMD-ONLY0:       cond.true4015:
+// SIMD-ONLY0-NEXT:    [[TMP2110:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4017:%.*]]
+// SIMD-ONLY0:       cond.false4016:
+// SIMD-ONLY0-NEXT:    [[TMP2111:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4017]]
+// SIMD-ONLY0:       cond.end4017:
+// SIMD-ONLY0-NEXT:    [[COND4018:%.*]] = phi i64 [ [[TMP2110]], [[COND_TRUE4015]] ], [ [[TMP2111]], [[COND_FALSE4016]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4018]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2112:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2113:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4019:%.*]] = icmp slt i64 [[TMP2112]], [[TMP2113]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4019]], label [[COND_TRUE4021:%.*]], label [[COND_FALSE4022:%.*]]
+// SIMD-ONLY0:       cond.true4021:
+// SIMD-ONLY0-NEXT:    [[TMP2114:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4023:%.*]]
+// SIMD-ONLY0:       cond.false4022:
+// SIMD-ONLY0-NEXT:    [[TMP2115:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4023]]
+// SIMD-ONLY0:       cond.end4023:
+// SIMD-ONLY0-NEXT:    [[COND4024:%.*]] = phi i64 [ [[TMP2114]], [[COND_TRUE4021]] ], [ [[TMP2115]], [[COND_FALSE4022]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4024]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2116:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2117:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4025:%.*]] = icmp sgt i64 [[TMP2116]], [[TMP2117]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4025]], label [[IF_THEN4027:%.*]], label [[IF_END4028:%.*]]
+// SIMD-ONLY0:       if.then4027:
+// SIMD-ONLY0-NEXT:    [[TMP2118:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2118]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4028]]
+// SIMD-ONLY0:       if.end4028:
+// SIMD-ONLY0-NEXT:    [[TMP2119:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2120:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4029:%.*]] = icmp slt i64 [[TMP2119]], [[TMP2120]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4029]], label [[IF_THEN4031:%.*]], label [[IF_END4032:%.*]]
+// SIMD-ONLY0:       if.then4031:
+// SIMD-ONLY0-NEXT:    [[TMP2121:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2121]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4032]]
+// SIMD-ONLY0:       if.end4032:
+// SIMD-ONLY0-NEXT:    [[TMP2122:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2123:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4033:%.*]] = icmp sgt i64 [[TMP2122]], [[TMP2123]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4033]], label [[IF_THEN4035:%.*]], label [[IF_END4036:%.*]]
+// SIMD-ONLY0:       if.then4035:
+// SIMD-ONLY0-NEXT:    [[TMP2124:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2124]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4036]]
+// SIMD-ONLY0:       if.end4036:
+// SIMD-ONLY0-NEXT:    [[TMP2125:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2126:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4037:%.*]] = icmp slt i64 [[TMP2125]], [[TMP2126]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4037]], label [[IF_THEN4039:%.*]], label [[IF_END4040:%.*]]
+// SIMD-ONLY0:       if.then4039:
+// SIMD-ONLY0-NEXT:    [[TMP2127:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2127]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4040]]
+// SIMD-ONLY0:       if.end4040:
+// SIMD-ONLY0-NEXT:    [[TMP2128:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2129:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4041:%.*]] = icmp eq i64 [[TMP2128]], [[TMP2129]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4041]], label [[COND_TRUE4043:%.*]], label [[COND_FALSE4044:%.*]]
+// SIMD-ONLY0:       cond.true4043:
+// SIMD-ONLY0-NEXT:    [[TMP2130:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4045:%.*]]
+// SIMD-ONLY0:       cond.false4044:
+// SIMD-ONLY0-NEXT:    [[TMP2131:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4045]]
+// SIMD-ONLY0:       cond.end4045:
+// SIMD-ONLY0-NEXT:    [[COND4046:%.*]] = phi i64 [ [[TMP2130]], [[COND_TRUE4043]] ], [ [[TMP2131]], [[COND_FALSE4044]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4046]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2132:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2133:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4047:%.*]] = icmp eq i64 [[TMP2132]], [[TMP2133]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4047]], label [[COND_TRUE4049:%.*]], label [[COND_FALSE4050:%.*]]
+// SIMD-ONLY0:       cond.true4049:
+// SIMD-ONLY0-NEXT:    [[TMP2134:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4051:%.*]]
+// SIMD-ONLY0:       cond.false4050:
+// SIMD-ONLY0-NEXT:    [[TMP2135:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4051]]
+// SIMD-ONLY0:       cond.end4051:
+// SIMD-ONLY0-NEXT:    [[COND4052:%.*]] = phi i64 [ [[TMP2134]], [[COND_TRUE4049]] ], [ [[TMP2135]], [[COND_FALSE4050]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4052]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2136:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2137:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4053:%.*]] = icmp eq i64 [[TMP2136]], [[TMP2137]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4053]], label [[IF_THEN4055:%.*]], label [[IF_END4056:%.*]]
+// SIMD-ONLY0:       if.then4055:
+// SIMD-ONLY0-NEXT:    [[TMP2138:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2138]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4056]]
+// SIMD-ONLY0:       if.end4056:
+// SIMD-ONLY0-NEXT:    [[TMP2139:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2140:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4057:%.*]] = icmp eq i64 [[TMP2139]], [[TMP2140]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4057]], label [[IF_THEN4059:%.*]], label [[IF_END4060:%.*]]
+// SIMD-ONLY0:       if.then4059:
+// SIMD-ONLY0-NEXT:    [[TMP2141:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2141]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4060]]
+// SIMD-ONLY0:       if.end4060:
+// SIMD-ONLY0-NEXT:    [[TMP2142:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2143:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4061:%.*]] = icmp ugt i64 [[TMP2142]], [[TMP2143]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4061]], label [[COND_TRUE4063:%.*]], label [[COND_FALSE4064:%.*]]
+// SIMD-ONLY0:       cond.true4063:
+// SIMD-ONLY0-NEXT:    [[TMP2144:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4065:%.*]]
+// SIMD-ONLY0:       cond.false4064:
+// SIMD-ONLY0-NEXT:    [[TMP2145:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4065]]
+// SIMD-ONLY0:       cond.end4065:
+// SIMD-ONLY0-NEXT:    [[COND4066:%.*]] = phi i64 [ [[TMP2144]], [[COND_TRUE4063]] ], [ [[TMP2145]], [[COND_FALSE4064]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4066]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2146:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2147:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4067:%.*]] = icmp ult i64 [[TMP2146]], [[TMP2147]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4067]], label [[COND_TRUE4069:%.*]], label [[COND_FALSE4070:%.*]]
+// SIMD-ONLY0:       cond.true4069:
+// SIMD-ONLY0-NEXT:    [[TMP2148:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4071:%.*]]
+// SIMD-ONLY0:       cond.false4070:
+// SIMD-ONLY0-NEXT:    [[TMP2149:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4071]]
+// SIMD-ONLY0:       cond.end4071:
+// SIMD-ONLY0-NEXT:    [[COND4072:%.*]] = phi i64 [ [[TMP2148]], [[COND_TRUE4069]] ], [ [[TMP2149]], [[COND_FALSE4070]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4072]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2150:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2151:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4073:%.*]] = icmp ugt i64 [[TMP2150]], [[TMP2151]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4073]], label [[COND_TRUE4075:%.*]], label [[COND_FALSE4076:%.*]]
+// SIMD-ONLY0:       cond.true4075:
+// SIMD-ONLY0-NEXT:    [[TMP2152:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4077:%.*]]
+// SIMD-ONLY0:       cond.false4076:
+// SIMD-ONLY0-NEXT:    [[TMP2153:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4077]]
+// SIMD-ONLY0:       cond.end4077:
+// SIMD-ONLY0-NEXT:    [[COND4078:%.*]] = phi i64 [ [[TMP2152]], [[COND_TRUE4075]] ], [ [[TMP2153]], [[COND_FALSE4076]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4078]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2154:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2155:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4079:%.*]] = icmp ult i64 [[TMP2154]], [[TMP2155]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4079]], label [[COND_TRUE4081:%.*]], label [[COND_FALSE4082:%.*]]
+// SIMD-ONLY0:       cond.true4081:
+// SIMD-ONLY0-NEXT:    [[TMP2156:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4083:%.*]]
+// SIMD-ONLY0:       cond.false4082:
+// SIMD-ONLY0-NEXT:    [[TMP2157:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4083]]
+// SIMD-ONLY0:       cond.end4083:
+// SIMD-ONLY0-NEXT:    [[COND4084:%.*]] = phi i64 [ [[TMP2156]], [[COND_TRUE4081]] ], [ [[TMP2157]], [[COND_FALSE4082]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4084]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2158:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2159:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4085:%.*]] = icmp ugt i64 [[TMP2158]], [[TMP2159]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4085]], label [[IF_THEN4087:%.*]], label [[IF_END4088:%.*]]
+// SIMD-ONLY0:       if.then4087:
+// SIMD-ONLY0-NEXT:    [[TMP2160:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2160]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4088]]
+// SIMD-ONLY0:       if.end4088:
+// SIMD-ONLY0-NEXT:    [[TMP2161:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2162:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4089:%.*]] = icmp ult i64 [[TMP2161]], [[TMP2162]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4089]], label [[IF_THEN4091:%.*]], label [[IF_END4092:%.*]]
+// SIMD-ONLY0:       if.then4091:
+// SIMD-ONLY0-NEXT:    [[TMP2163:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2163]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4092]]
+// SIMD-ONLY0:       if.end4092:
+// SIMD-ONLY0-NEXT:    [[TMP2164:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2165:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4093:%.*]] = icmp ugt i64 [[TMP2164]], [[TMP2165]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4093]], label [[IF_THEN4095:%.*]], label [[IF_END4096:%.*]]
+// SIMD-ONLY0:       if.then4095:
+// SIMD-ONLY0-NEXT:    [[TMP2166:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2166]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4096]]
+// SIMD-ONLY0:       if.end4096:
+// SIMD-ONLY0-NEXT:    [[TMP2167:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2168:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4097:%.*]] = icmp ult i64 [[TMP2167]], [[TMP2168]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4097]], label [[IF_THEN4099:%.*]], label [[IF_END4100:%.*]]
+// SIMD-ONLY0:       if.then4099:
+// SIMD-ONLY0-NEXT:    [[TMP2169:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2169]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4100]]
+// SIMD-ONLY0:       if.end4100:
+// SIMD-ONLY0-NEXT:    [[TMP2170:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2171:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4101:%.*]] = icmp eq i64 [[TMP2170]], [[TMP2171]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4101]], label [[COND_TRUE4103:%.*]], label [[COND_FALSE4104:%.*]]
+// SIMD-ONLY0:       cond.true4103:
+// SIMD-ONLY0-NEXT:    [[TMP2172:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4105:%.*]]
+// SIMD-ONLY0:       cond.false4104:
+// SIMD-ONLY0-NEXT:    [[TMP2173:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4105]]
+// SIMD-ONLY0:       cond.end4105:
+// SIMD-ONLY0-NEXT:    [[COND4106:%.*]] = phi i64 [ [[TMP2172]], [[COND_TRUE4103]] ], [ [[TMP2173]], [[COND_FALSE4104]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4106]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2174:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2175:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4107:%.*]] = icmp eq i64 [[TMP2174]], [[TMP2175]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4107]], label [[COND_TRUE4109:%.*]], label [[COND_FALSE4110:%.*]]
+// SIMD-ONLY0:       cond.true4109:
+// SIMD-ONLY0-NEXT:    [[TMP2176:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4111:%.*]]
+// SIMD-ONLY0:       cond.false4110:
+// SIMD-ONLY0-NEXT:    [[TMP2177:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4111]]
+// SIMD-ONLY0:       cond.end4111:
+// SIMD-ONLY0-NEXT:    [[COND4112:%.*]] = phi i64 [ [[TMP2176]], [[COND_TRUE4109]] ], [ [[TMP2177]], [[COND_FALSE4110]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4112]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2178:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2179:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4113:%.*]] = icmp eq i64 [[TMP2178]], [[TMP2179]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4113]], label [[IF_THEN4115:%.*]], label [[IF_END4116:%.*]]
+// SIMD-ONLY0:       if.then4115:
+// SIMD-ONLY0-NEXT:    [[TMP2180:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2180]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4116]]
+// SIMD-ONLY0:       if.end4116:
+// SIMD-ONLY0-NEXT:    [[TMP2181:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2182:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4117:%.*]] = icmp eq i64 [[TMP2181]], [[TMP2182]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4117]], label [[IF_THEN4119:%.*]], label [[IF_END4120:%.*]]
+// SIMD-ONLY0:       if.then4119:
+// SIMD-ONLY0-NEXT:    [[TMP2183:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2183]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4120]]
+// SIMD-ONLY0:       if.end4120:
+// SIMD-ONLY0-NEXT:    [[TMP2184:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2185:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4121:%.*]] = icmp sgt i64 [[TMP2184]], [[TMP2185]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4121]], label [[COND_TRUE4123:%.*]], label [[COND_FALSE4124:%.*]]
+// SIMD-ONLY0:       cond.true4123:
+// SIMD-ONLY0-NEXT:    [[TMP2186:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4125:%.*]]
+// SIMD-ONLY0:       cond.false4124:
+// SIMD-ONLY0-NEXT:    [[TMP2187:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4125]]
+// SIMD-ONLY0:       cond.end4125:
+// SIMD-ONLY0-NEXT:    [[COND4126:%.*]] = phi i64 [ [[TMP2186]], [[COND_TRUE4123]] ], [ [[TMP2187]], [[COND_FALSE4124]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4126]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2188:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2189:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4127:%.*]] = icmp slt i64 [[TMP2188]], [[TMP2189]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4127]], label [[COND_TRUE4129:%.*]], label [[COND_FALSE4130:%.*]]
+// SIMD-ONLY0:       cond.true4129:
+// SIMD-ONLY0-NEXT:    [[TMP2190:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4131:%.*]]
+// SIMD-ONLY0:       cond.false4130:
+// SIMD-ONLY0-NEXT:    [[TMP2191:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4131]]
+// SIMD-ONLY0:       cond.end4131:
+// SIMD-ONLY0-NEXT:    [[COND4132:%.*]] = phi i64 [ [[TMP2190]], [[COND_TRUE4129]] ], [ [[TMP2191]], [[COND_FALSE4130]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4132]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2192:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2193:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4133:%.*]] = icmp sgt i64 [[TMP2192]], [[TMP2193]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4133]], label [[COND_TRUE4135:%.*]], label [[COND_FALSE4136:%.*]]
+// SIMD-ONLY0:       cond.true4135:
+// SIMD-ONLY0-NEXT:    [[TMP2194:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4137:%.*]]
+// SIMD-ONLY0:       cond.false4136:
+// SIMD-ONLY0-NEXT:    [[TMP2195:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4137]]
+// SIMD-ONLY0:       cond.end4137:
+// SIMD-ONLY0-NEXT:    [[COND4138:%.*]] = phi i64 [ [[TMP2194]], [[COND_TRUE4135]] ], [ [[TMP2195]], [[COND_FALSE4136]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4138]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2196:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2197:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4139:%.*]] = icmp slt i64 [[TMP2196]], [[TMP2197]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4139]], label [[COND_TRUE4141:%.*]], label [[COND_FALSE4142:%.*]]
+// SIMD-ONLY0:       cond.true4141:
+// SIMD-ONLY0-NEXT:    [[TMP2198:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4143:%.*]]
+// SIMD-ONLY0:       cond.false4142:
+// SIMD-ONLY0-NEXT:    [[TMP2199:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4143]]
+// SIMD-ONLY0:       cond.end4143:
+// SIMD-ONLY0-NEXT:    [[COND4144:%.*]] = phi i64 [ [[TMP2198]], [[COND_TRUE4141]] ], [ [[TMP2199]], [[COND_FALSE4142]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4144]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2200:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2201:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4145:%.*]] = icmp sgt i64 [[TMP2200]], [[TMP2201]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4145]], label [[IF_THEN4147:%.*]], label [[IF_END4148:%.*]]
+// SIMD-ONLY0:       if.then4147:
+// SIMD-ONLY0-NEXT:    [[TMP2202:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2202]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4148]]
+// SIMD-ONLY0:       if.end4148:
+// SIMD-ONLY0-NEXT:    [[TMP2203:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2204:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4149:%.*]] = icmp slt i64 [[TMP2203]], [[TMP2204]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4149]], label [[IF_THEN4151:%.*]], label [[IF_END4152:%.*]]
+// SIMD-ONLY0:       if.then4151:
+// SIMD-ONLY0-NEXT:    [[TMP2205:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2205]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4152]]
+// SIMD-ONLY0:       if.end4152:
+// SIMD-ONLY0-NEXT:    [[TMP2206:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2207:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4153:%.*]] = icmp sgt i64 [[TMP2206]], [[TMP2207]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4153]], label [[IF_THEN4155:%.*]], label [[IF_END4156:%.*]]
+// SIMD-ONLY0:       if.then4155:
+// SIMD-ONLY0-NEXT:    [[TMP2208:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2208]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4156]]
+// SIMD-ONLY0:       if.end4156:
+// SIMD-ONLY0-NEXT:    [[TMP2209:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2210:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4157:%.*]] = icmp slt i64 [[TMP2209]], [[TMP2210]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4157]], label [[IF_THEN4159:%.*]], label [[IF_END4160:%.*]]
+// SIMD-ONLY0:       if.then4159:
+// SIMD-ONLY0-NEXT:    [[TMP2211:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2211]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4160]]
+// SIMD-ONLY0:       if.end4160:
+// SIMD-ONLY0-NEXT:    [[TMP2212:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2213:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4161:%.*]] = icmp eq i64 [[TMP2212]], [[TMP2213]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4161]], label [[COND_TRUE4163:%.*]], label [[COND_FALSE4164:%.*]]
+// SIMD-ONLY0:       cond.true4163:
+// SIMD-ONLY0-NEXT:    [[TMP2214:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4165:%.*]]
+// SIMD-ONLY0:       cond.false4164:
+// SIMD-ONLY0-NEXT:    [[TMP2215:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4165]]
+// SIMD-ONLY0:       cond.end4165:
+// SIMD-ONLY0-NEXT:    [[COND4166:%.*]] = phi i64 [ [[TMP2214]], [[COND_TRUE4163]] ], [ [[TMP2215]], [[COND_FALSE4164]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4166]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2216:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2217:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4167:%.*]] = icmp eq i64 [[TMP2216]], [[TMP2217]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4167]], label [[COND_TRUE4169:%.*]], label [[COND_FALSE4170:%.*]]
+// SIMD-ONLY0:       cond.true4169:
+// SIMD-ONLY0-NEXT:    [[TMP2218:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4171:%.*]]
+// SIMD-ONLY0:       cond.false4170:
+// SIMD-ONLY0-NEXT:    [[TMP2219:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4171]]
+// SIMD-ONLY0:       cond.end4171:
+// SIMD-ONLY0-NEXT:    [[COND4172:%.*]] = phi i64 [ [[TMP2218]], [[COND_TRUE4169]] ], [ [[TMP2219]], [[COND_FALSE4170]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4172]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2220:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2221:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4173:%.*]] = icmp eq i64 [[TMP2220]], [[TMP2221]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4173]], label [[IF_THEN4175:%.*]], label [[IF_END4176:%.*]]
+// SIMD-ONLY0:       if.then4175:
+// SIMD-ONLY0-NEXT:    [[TMP2222:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2222]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4176]]
+// SIMD-ONLY0:       if.end4176:
+// SIMD-ONLY0-NEXT:    [[TMP2223:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2224:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4177:%.*]] = icmp eq i64 [[TMP2223]], [[TMP2224]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4177]], label [[IF_THEN4179:%.*]], label [[IF_END4180:%.*]]
+// SIMD-ONLY0:       if.then4179:
+// SIMD-ONLY0-NEXT:    [[TMP2225:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2225]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4180]]
+// SIMD-ONLY0:       if.end4180:
+// SIMD-ONLY0-NEXT:    [[TMP2226:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2227:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4181:%.*]] = icmp ugt i64 [[TMP2226]], [[TMP2227]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4181]], label [[COND_TRUE4183:%.*]], label [[COND_FALSE4184:%.*]]
+// SIMD-ONLY0:       cond.true4183:
+// SIMD-ONLY0-NEXT:    [[TMP2228:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4185:%.*]]
+// SIMD-ONLY0:       cond.false4184:
+// SIMD-ONLY0-NEXT:    [[TMP2229:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4185]]
+// SIMD-ONLY0:       cond.end4185:
+// SIMD-ONLY0-NEXT:    [[COND4186:%.*]] = phi i64 [ [[TMP2228]], [[COND_TRUE4183]] ], [ [[TMP2229]], [[COND_FALSE4184]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4186]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2230:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2231:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4187:%.*]] = icmp ult i64 [[TMP2230]], [[TMP2231]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4187]], label [[COND_TRUE4189:%.*]], label [[COND_FALSE4190:%.*]]
+// SIMD-ONLY0:       cond.true4189:
+// SIMD-ONLY0-NEXT:    [[TMP2232:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4191:%.*]]
+// SIMD-ONLY0:       cond.false4190:
+// SIMD-ONLY0-NEXT:    [[TMP2233:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4191]]
+// SIMD-ONLY0:       cond.end4191:
+// SIMD-ONLY0-NEXT:    [[COND4192:%.*]] = phi i64 [ [[TMP2232]], [[COND_TRUE4189]] ], [ [[TMP2233]], [[COND_FALSE4190]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4192]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2234:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2235:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4193:%.*]] = icmp ugt i64 [[TMP2234]], [[TMP2235]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4193]], label [[COND_TRUE4195:%.*]], label [[COND_FALSE4196:%.*]]
+// SIMD-ONLY0:       cond.true4195:
+// SIMD-ONLY0-NEXT:    [[TMP2236:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4197:%.*]]
+// SIMD-ONLY0:       cond.false4196:
+// SIMD-ONLY0-NEXT:    [[TMP2237:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4197]]
+// SIMD-ONLY0:       cond.end4197:
+// SIMD-ONLY0-NEXT:    [[COND4198:%.*]] = phi i64 [ [[TMP2236]], [[COND_TRUE4195]] ], [ [[TMP2237]], [[COND_FALSE4196]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4198]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2238:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2239:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4199:%.*]] = icmp ult i64 [[TMP2238]], [[TMP2239]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4199]], label [[COND_TRUE4201:%.*]], label [[COND_FALSE4202:%.*]]
+// SIMD-ONLY0:       cond.true4201:
+// SIMD-ONLY0-NEXT:    [[TMP2240:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4203:%.*]]
+// SIMD-ONLY0:       cond.false4202:
+// SIMD-ONLY0-NEXT:    [[TMP2241:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4203]]
+// SIMD-ONLY0:       cond.end4203:
+// SIMD-ONLY0-NEXT:    [[COND4204:%.*]] = phi i64 [ [[TMP2240]], [[COND_TRUE4201]] ], [ [[TMP2241]], [[COND_FALSE4202]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4204]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2242:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2243:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4205:%.*]] = icmp ugt i64 [[TMP2242]], [[TMP2243]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4205]], label [[IF_THEN4207:%.*]], label [[IF_END4208:%.*]]
+// SIMD-ONLY0:       if.then4207:
+// SIMD-ONLY0-NEXT:    [[TMP2244:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2244]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4208]]
+// SIMD-ONLY0:       if.end4208:
+// SIMD-ONLY0-NEXT:    [[TMP2245:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2246:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4209:%.*]] = icmp ult i64 [[TMP2245]], [[TMP2246]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4209]], label [[IF_THEN4211:%.*]], label [[IF_END4212:%.*]]
+// SIMD-ONLY0:       if.then4211:
+// SIMD-ONLY0-NEXT:    [[TMP2247:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2247]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4212]]
+// SIMD-ONLY0:       if.end4212:
+// SIMD-ONLY0-NEXT:    [[TMP2248:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2249:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4213:%.*]] = icmp ugt i64 [[TMP2248]], [[TMP2249]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4213]], label [[IF_THEN4215:%.*]], label [[IF_END4216:%.*]]
+// SIMD-ONLY0:       if.then4215:
+// SIMD-ONLY0-NEXT:    [[TMP2250:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2250]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4216]]
+// SIMD-ONLY0:       if.end4216:
+// SIMD-ONLY0-NEXT:    [[TMP2251:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2252:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4217:%.*]] = icmp ult i64 [[TMP2251]], [[TMP2252]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4217]], label [[IF_THEN4219:%.*]], label [[IF_END4220:%.*]]
+// SIMD-ONLY0:       if.then4219:
+// SIMD-ONLY0-NEXT:    [[TMP2253:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2253]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4220]]
+// SIMD-ONLY0:       if.end4220:
+// SIMD-ONLY0-NEXT:    [[TMP2254:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2255:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4221:%.*]] = icmp eq i64 [[TMP2254]], [[TMP2255]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4221]], label [[COND_TRUE4223:%.*]], label [[COND_FALSE4224:%.*]]
+// SIMD-ONLY0:       cond.true4223:
+// SIMD-ONLY0-NEXT:    [[TMP2256:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4225:%.*]]
+// SIMD-ONLY0:       cond.false4224:
+// SIMD-ONLY0-NEXT:    [[TMP2257:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4225]]
+// SIMD-ONLY0:       cond.end4225:
+// SIMD-ONLY0-NEXT:    [[COND4226:%.*]] = phi i64 [ [[TMP2256]], [[COND_TRUE4223]] ], [ [[TMP2257]], [[COND_FALSE4224]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4226]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2258:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2259:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4227:%.*]] = icmp eq i64 [[TMP2258]], [[TMP2259]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4227]], label [[COND_TRUE4229:%.*]], label [[COND_FALSE4230:%.*]]
+// SIMD-ONLY0:       cond.true4229:
+// SIMD-ONLY0-NEXT:    [[TMP2260:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4231:%.*]]
+// SIMD-ONLY0:       cond.false4230:
+// SIMD-ONLY0-NEXT:    [[TMP2261:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4231]]
+// SIMD-ONLY0:       cond.end4231:
+// SIMD-ONLY0-NEXT:    [[COND4232:%.*]] = phi i64 [ [[TMP2260]], [[COND_TRUE4229]] ], [ [[TMP2261]], [[COND_FALSE4230]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4232]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2262:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2263:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4233:%.*]] = icmp eq i64 [[TMP2262]], [[TMP2263]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4233]], label [[IF_THEN4235:%.*]], label [[IF_END4236:%.*]]
+// SIMD-ONLY0:       if.then4235:
+// SIMD-ONLY0-NEXT:    [[TMP2264:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2264]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4236]]
+// SIMD-ONLY0:       if.end4236:
+// SIMD-ONLY0-NEXT:    [[TMP2265:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2266:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4237:%.*]] = icmp eq i64 [[TMP2265]], [[TMP2266]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4237]], label [[IF_THEN4239:%.*]], label [[IF_END4240:%.*]]
+// SIMD-ONLY0:       if.then4239:
+// SIMD-ONLY0-NEXT:    [[TMP2267:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2267]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4240]]
+// SIMD-ONLY0:       if.end4240:
+// SIMD-ONLY0-NEXT:    [[TMP2268:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2269:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4241:%.*]] = icmp sgt i64 [[TMP2268]], [[TMP2269]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4241]], label [[COND_TRUE4243:%.*]], label [[COND_FALSE4244:%.*]]
+// SIMD-ONLY0:       cond.true4243:
+// SIMD-ONLY0-NEXT:    [[TMP2270:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4245:%.*]]
+// SIMD-ONLY0:       cond.false4244:
+// SIMD-ONLY0-NEXT:    [[TMP2271:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4245]]
+// SIMD-ONLY0:       cond.end4245:
+// SIMD-ONLY0-NEXT:    [[COND4246:%.*]] = phi i64 [ [[TMP2270]], [[COND_TRUE4243]] ], [ [[TMP2271]], [[COND_FALSE4244]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4246]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2272:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2273:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4247:%.*]] = icmp slt i64 [[TMP2272]], [[TMP2273]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4247]], label [[COND_TRUE4249:%.*]], label [[COND_FALSE4250:%.*]]
+// SIMD-ONLY0:       cond.true4249:
+// SIMD-ONLY0-NEXT:    [[TMP2274:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4251:%.*]]
+// SIMD-ONLY0:       cond.false4250:
+// SIMD-ONLY0-NEXT:    [[TMP2275:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4251]]
+// SIMD-ONLY0:       cond.end4251:
+// SIMD-ONLY0-NEXT:    [[COND4252:%.*]] = phi i64 [ [[TMP2274]], [[COND_TRUE4249]] ], [ [[TMP2275]], [[COND_FALSE4250]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4252]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2276:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2277:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4253:%.*]] = icmp sgt i64 [[TMP2276]], [[TMP2277]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4253]], label [[COND_TRUE4255:%.*]], label [[COND_FALSE4256:%.*]]
+// SIMD-ONLY0:       cond.true4255:
+// SIMD-ONLY0-NEXT:    [[TMP2278:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4257:%.*]]
+// SIMD-ONLY0:       cond.false4256:
+// SIMD-ONLY0-NEXT:    [[TMP2279:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4257]]
+// SIMD-ONLY0:       cond.end4257:
+// SIMD-ONLY0-NEXT:    [[COND4258:%.*]] = phi i64 [ [[TMP2278]], [[COND_TRUE4255]] ], [ [[TMP2279]], [[COND_FALSE4256]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4258]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2280:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2281:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4259:%.*]] = icmp slt i64 [[TMP2280]], [[TMP2281]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4259]], label [[COND_TRUE4261:%.*]], label [[COND_FALSE4262:%.*]]
+// SIMD-ONLY0:       cond.true4261:
+// SIMD-ONLY0-NEXT:    [[TMP2282:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4263:%.*]]
+// SIMD-ONLY0:       cond.false4262:
+// SIMD-ONLY0-NEXT:    [[TMP2283:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4263]]
+// SIMD-ONLY0:       cond.end4263:
+// SIMD-ONLY0-NEXT:    [[COND4264:%.*]] = phi i64 [ [[TMP2282]], [[COND_TRUE4261]] ], [ [[TMP2283]], [[COND_FALSE4262]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4264]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2284:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2285:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4265:%.*]] = icmp sgt i64 [[TMP2284]], [[TMP2285]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4265]], label [[IF_THEN4267:%.*]], label [[IF_END4268:%.*]]
+// SIMD-ONLY0:       if.then4267:
+// SIMD-ONLY0-NEXT:    [[TMP2286:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2286]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4268]]
+// SIMD-ONLY0:       if.end4268:
+// SIMD-ONLY0-NEXT:    [[TMP2287:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2288:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4269:%.*]] = icmp slt i64 [[TMP2287]], [[TMP2288]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4269]], label [[IF_THEN4271:%.*]], label [[IF_END4272:%.*]]
+// SIMD-ONLY0:       if.then4271:
+// SIMD-ONLY0-NEXT:    [[TMP2289:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2289]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4272]]
+// SIMD-ONLY0:       if.end4272:
+// SIMD-ONLY0-NEXT:    [[TMP2290:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2291:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4273:%.*]] = icmp sgt i64 [[TMP2290]], [[TMP2291]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4273]], label [[IF_THEN4275:%.*]], label [[IF_END4276:%.*]]
+// SIMD-ONLY0:       if.then4275:
+// SIMD-ONLY0-NEXT:    [[TMP2292:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2292]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4276]]
+// SIMD-ONLY0:       if.end4276:
+// SIMD-ONLY0-NEXT:    [[TMP2293:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2294:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4277:%.*]] = icmp slt i64 [[TMP2293]], [[TMP2294]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4277]], label [[IF_THEN4279:%.*]], label [[IF_END4280:%.*]]
+// SIMD-ONLY0:       if.then4279:
+// SIMD-ONLY0-NEXT:    [[TMP2295:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2295]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4280]]
+// SIMD-ONLY0:       if.end4280:
+// SIMD-ONLY0-NEXT:    [[TMP2296:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2297:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4281:%.*]] = icmp eq i64 [[TMP2296]], [[TMP2297]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4281]], label [[COND_TRUE4283:%.*]], label [[COND_FALSE4284:%.*]]
+// SIMD-ONLY0:       cond.true4283:
+// SIMD-ONLY0-NEXT:    [[TMP2298:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4285:%.*]]
+// SIMD-ONLY0:       cond.false4284:
+// SIMD-ONLY0-NEXT:    [[TMP2299:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4285]]
+// SIMD-ONLY0:       cond.end4285:
+// SIMD-ONLY0-NEXT:    [[COND4286:%.*]] = phi i64 [ [[TMP2298]], [[COND_TRUE4283]] ], [ [[TMP2299]], [[COND_FALSE4284]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4286]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2300:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2301:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4287:%.*]] = icmp eq i64 [[TMP2300]], [[TMP2301]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4287]], label [[COND_TRUE4289:%.*]], label [[COND_FALSE4290:%.*]]
+// SIMD-ONLY0:       cond.true4289:
+// SIMD-ONLY0-NEXT:    [[TMP2302:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4291:%.*]]
+// SIMD-ONLY0:       cond.false4290:
+// SIMD-ONLY0-NEXT:    [[TMP2303:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4291]]
+// SIMD-ONLY0:       cond.end4291:
+// SIMD-ONLY0-NEXT:    [[COND4292:%.*]] = phi i64 [ [[TMP2302]], [[COND_TRUE4289]] ], [ [[TMP2303]], [[COND_FALSE4290]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4292]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2304:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2305:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4293:%.*]] = icmp eq i64 [[TMP2304]], [[TMP2305]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4293]], label [[IF_THEN4295:%.*]], label [[IF_END4296:%.*]]
+// SIMD-ONLY0:       if.then4295:
+// SIMD-ONLY0-NEXT:    [[TMP2306:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2306]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4296]]
+// SIMD-ONLY0:       if.end4296:
+// SIMD-ONLY0-NEXT:    [[TMP2307:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2308:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4297:%.*]] = icmp eq i64 [[TMP2307]], [[TMP2308]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4297]], label [[IF_THEN4299:%.*]], label [[IF_END4300:%.*]]
+// SIMD-ONLY0:       if.then4299:
+// SIMD-ONLY0-NEXT:    [[TMP2309:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2309]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4300]]
+// SIMD-ONLY0:       if.end4300:
+// SIMD-ONLY0-NEXT:    [[TMP2310:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2311:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4301:%.*]] = icmp ugt i64 [[TMP2310]], [[TMP2311]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4301]], label [[COND_TRUE4303:%.*]], label [[COND_FALSE4304:%.*]]
+// SIMD-ONLY0:       cond.true4303:
+// SIMD-ONLY0-NEXT:    [[TMP2312:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4305:%.*]]
+// SIMD-ONLY0:       cond.false4304:
+// SIMD-ONLY0-NEXT:    [[TMP2313:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4305]]
+// SIMD-ONLY0:       cond.end4305:
+// SIMD-ONLY0-NEXT:    [[COND4306:%.*]] = phi i64 [ [[TMP2312]], [[COND_TRUE4303]] ], [ [[TMP2313]], [[COND_FALSE4304]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4306]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2314:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2315:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4307:%.*]] = icmp ult i64 [[TMP2314]], [[TMP2315]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4307]], label [[COND_TRUE4309:%.*]], label [[COND_FALSE4310:%.*]]
+// SIMD-ONLY0:       cond.true4309:
+// SIMD-ONLY0-NEXT:    [[TMP2316:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4311:%.*]]
+// SIMD-ONLY0:       cond.false4310:
+// SIMD-ONLY0-NEXT:    [[TMP2317:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4311]]
+// SIMD-ONLY0:       cond.end4311:
+// SIMD-ONLY0-NEXT:    [[COND4312:%.*]] = phi i64 [ [[TMP2316]], [[COND_TRUE4309]] ], [ [[TMP2317]], [[COND_FALSE4310]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4312]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2318:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2319:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4313:%.*]] = icmp ugt i64 [[TMP2318]], [[TMP2319]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4313]], label [[COND_TRUE4315:%.*]], label [[COND_FALSE4316:%.*]]
+// SIMD-ONLY0:       cond.true4315:
+// SIMD-ONLY0-NEXT:    [[TMP2320:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4317:%.*]]
+// SIMD-ONLY0:       cond.false4316:
+// SIMD-ONLY0-NEXT:    [[TMP2321:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4317]]
+// SIMD-ONLY0:       cond.end4317:
+// SIMD-ONLY0-NEXT:    [[COND4318:%.*]] = phi i64 [ [[TMP2320]], [[COND_TRUE4315]] ], [ [[TMP2321]], [[COND_FALSE4316]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4318]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2322:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2323:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4319:%.*]] = icmp ult i64 [[TMP2322]], [[TMP2323]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4319]], label [[COND_TRUE4321:%.*]], label [[COND_FALSE4322:%.*]]
+// SIMD-ONLY0:       cond.true4321:
+// SIMD-ONLY0-NEXT:    [[TMP2324:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4323:%.*]]
+// SIMD-ONLY0:       cond.false4322:
+// SIMD-ONLY0-NEXT:    [[TMP2325:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4323]]
+// SIMD-ONLY0:       cond.end4323:
+// SIMD-ONLY0-NEXT:    [[COND4324:%.*]] = phi i64 [ [[TMP2324]], [[COND_TRUE4321]] ], [ [[TMP2325]], [[COND_FALSE4322]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4324]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2326:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2327:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4325:%.*]] = icmp ugt i64 [[TMP2326]], [[TMP2327]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4325]], label [[IF_THEN4327:%.*]], label [[IF_END4328:%.*]]
+// SIMD-ONLY0:       if.then4327:
+// SIMD-ONLY0-NEXT:    [[TMP2328:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2328]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4328]]
+// SIMD-ONLY0:       if.end4328:
+// SIMD-ONLY0-NEXT:    [[TMP2329:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2330:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4329:%.*]] = icmp ult i64 [[TMP2329]], [[TMP2330]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4329]], label [[IF_THEN4331:%.*]], label [[IF_END4332:%.*]]
+// SIMD-ONLY0:       if.then4331:
+// SIMD-ONLY0-NEXT:    [[TMP2331:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2331]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4332]]
+// SIMD-ONLY0:       if.end4332:
+// SIMD-ONLY0-NEXT:    [[TMP2332:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2333:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4333:%.*]] = icmp ugt i64 [[TMP2332]], [[TMP2333]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4333]], label [[IF_THEN4335:%.*]], label [[IF_END4336:%.*]]
+// SIMD-ONLY0:       if.then4335:
+// SIMD-ONLY0-NEXT:    [[TMP2334:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2334]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4336]]
+// SIMD-ONLY0:       if.end4336:
+// SIMD-ONLY0-NEXT:    [[TMP2335:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2336:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4337:%.*]] = icmp ult i64 [[TMP2335]], [[TMP2336]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4337]], label [[IF_THEN4339:%.*]], label [[IF_END4340:%.*]]
+// SIMD-ONLY0:       if.then4339:
+// SIMD-ONLY0-NEXT:    [[TMP2337:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2337]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4340]]
+// SIMD-ONLY0:       if.end4340:
+// SIMD-ONLY0-NEXT:    [[TMP2338:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2339:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4341:%.*]] = icmp eq i64 [[TMP2338]], [[TMP2339]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4341]], label [[COND_TRUE4343:%.*]], label [[COND_FALSE4344:%.*]]
+// SIMD-ONLY0:       cond.true4343:
+// SIMD-ONLY0-NEXT:    [[TMP2340:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4345:%.*]]
+// SIMD-ONLY0:       cond.false4344:
+// SIMD-ONLY0-NEXT:    [[TMP2341:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4345]]
+// SIMD-ONLY0:       cond.end4345:
+// SIMD-ONLY0-NEXT:    [[COND4346:%.*]] = phi i64 [ [[TMP2340]], [[COND_TRUE4343]] ], [ [[TMP2341]], [[COND_FALSE4344]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4346]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2342:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2343:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4347:%.*]] = icmp eq i64 [[TMP2342]], [[TMP2343]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4347]], label [[COND_TRUE4349:%.*]], label [[COND_FALSE4350:%.*]]
+// SIMD-ONLY0:       cond.true4349:
+// SIMD-ONLY0-NEXT:    [[TMP2344:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4351:%.*]]
+// SIMD-ONLY0:       cond.false4350:
+// SIMD-ONLY0-NEXT:    [[TMP2345:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4351]]
+// SIMD-ONLY0:       cond.end4351:
+// SIMD-ONLY0-NEXT:    [[COND4352:%.*]] = phi i64 [ [[TMP2344]], [[COND_TRUE4349]] ], [ [[TMP2345]], [[COND_FALSE4350]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4352]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2346:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2347:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4353:%.*]] = icmp eq i64 [[TMP2346]], [[TMP2347]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4353]], label [[IF_THEN4355:%.*]], label [[IF_END4356:%.*]]
+// SIMD-ONLY0:       if.then4355:
+// SIMD-ONLY0-NEXT:    [[TMP2348:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2348]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4356]]
+// SIMD-ONLY0:       if.end4356:
+// SIMD-ONLY0-NEXT:    [[TMP2349:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2350:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4357:%.*]] = icmp eq i64 [[TMP2349]], [[TMP2350]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4357]], label [[IF_THEN4359:%.*]], label [[IF_END4360:%.*]]
+// SIMD-ONLY0:       if.then4359:
+// SIMD-ONLY0-NEXT:    [[TMP2351:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2351]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4360]]
+// SIMD-ONLY0:       if.end4360:
+// SIMD-ONLY0-NEXT:    [[TMP2352:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2353:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4361:%.*]] = icmp sgt i64 [[TMP2352]], [[TMP2353]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4361]], label [[COND_TRUE4363:%.*]], label [[COND_FALSE4364:%.*]]
+// SIMD-ONLY0:       cond.true4363:
+// SIMD-ONLY0-NEXT:    [[TMP2354:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4365:%.*]]
+// SIMD-ONLY0:       cond.false4364:
+// SIMD-ONLY0-NEXT:    [[TMP2355:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4365]]
+// SIMD-ONLY0:       cond.end4365:
+// SIMD-ONLY0-NEXT:    [[COND4366:%.*]] = phi i64 [ [[TMP2354]], [[COND_TRUE4363]] ], [ [[TMP2355]], [[COND_FALSE4364]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4366]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2356:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2357:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4367:%.*]] = icmp slt i64 [[TMP2356]], [[TMP2357]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4367]], label [[COND_TRUE4369:%.*]], label [[COND_FALSE4370:%.*]]
+// SIMD-ONLY0:       cond.true4369:
+// SIMD-ONLY0-NEXT:    [[TMP2358:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4371:%.*]]
+// SIMD-ONLY0:       cond.false4370:
+// SIMD-ONLY0-NEXT:    [[TMP2359:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4371]]
+// SIMD-ONLY0:       cond.end4371:
+// SIMD-ONLY0-NEXT:    [[COND4372:%.*]] = phi i64 [ [[TMP2358]], [[COND_TRUE4369]] ], [ [[TMP2359]], [[COND_FALSE4370]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4372]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2360:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2361:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4373:%.*]] = icmp sgt i64 [[TMP2360]], [[TMP2361]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4373]], label [[COND_TRUE4375:%.*]], label [[COND_FALSE4376:%.*]]
+// SIMD-ONLY0:       cond.true4375:
+// SIMD-ONLY0-NEXT:    [[TMP2362:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4377:%.*]]
+// SIMD-ONLY0:       cond.false4376:
+// SIMD-ONLY0-NEXT:    [[TMP2363:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4377]]
+// SIMD-ONLY0:       cond.end4377:
+// SIMD-ONLY0-NEXT:    [[COND4378:%.*]] = phi i64 [ [[TMP2362]], [[COND_TRUE4375]] ], [ [[TMP2363]], [[COND_FALSE4376]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4378]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2364:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2365:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4379:%.*]] = icmp slt i64 [[TMP2364]], [[TMP2365]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4379]], label [[COND_TRUE4381:%.*]], label [[COND_FALSE4382:%.*]]
+// SIMD-ONLY0:       cond.true4381:
+// SIMD-ONLY0-NEXT:    [[TMP2366:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4383:%.*]]
+// SIMD-ONLY0:       cond.false4382:
+// SIMD-ONLY0-NEXT:    [[TMP2367:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4383]]
+// SIMD-ONLY0:       cond.end4383:
+// SIMD-ONLY0-NEXT:    [[COND4384:%.*]] = phi i64 [ [[TMP2366]], [[COND_TRUE4381]] ], [ [[TMP2367]], [[COND_FALSE4382]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4384]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2368:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2369:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4385:%.*]] = icmp sgt i64 [[TMP2368]], [[TMP2369]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4385]], label [[IF_THEN4387:%.*]], label [[IF_END4388:%.*]]
+// SIMD-ONLY0:       if.then4387:
+// SIMD-ONLY0-NEXT:    [[TMP2370:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2370]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4388]]
+// SIMD-ONLY0:       if.end4388:
+// SIMD-ONLY0-NEXT:    [[TMP2371:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2372:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4389:%.*]] = icmp slt i64 [[TMP2371]], [[TMP2372]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4389]], label [[IF_THEN4391:%.*]], label [[IF_END4392:%.*]]
+// SIMD-ONLY0:       if.then4391:
+// SIMD-ONLY0-NEXT:    [[TMP2373:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2373]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4392]]
+// SIMD-ONLY0:       if.end4392:
+// SIMD-ONLY0-NEXT:    [[TMP2374:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2375:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4393:%.*]] = icmp sgt i64 [[TMP2374]], [[TMP2375]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4393]], label [[IF_THEN4395:%.*]], label [[IF_END4396:%.*]]
+// SIMD-ONLY0:       if.then4395:
+// SIMD-ONLY0-NEXT:    [[TMP2376:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2376]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4396]]
+// SIMD-ONLY0:       if.end4396:
+// SIMD-ONLY0-NEXT:    [[TMP2377:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2378:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4397:%.*]] = icmp slt i64 [[TMP2377]], [[TMP2378]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4397]], label [[IF_THEN4399:%.*]], label [[IF_END4400:%.*]]
+// SIMD-ONLY0:       if.then4399:
+// SIMD-ONLY0-NEXT:    [[TMP2379:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2379]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4400]]
+// SIMD-ONLY0:       if.end4400:
+// SIMD-ONLY0-NEXT:    [[TMP2380:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2381:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4401:%.*]] = icmp eq i64 [[TMP2380]], [[TMP2381]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4401]], label [[COND_TRUE4403:%.*]], label [[COND_FALSE4404:%.*]]
+// SIMD-ONLY0:       cond.true4403:
+// SIMD-ONLY0-NEXT:    [[TMP2382:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4405:%.*]]
+// SIMD-ONLY0:       cond.false4404:
+// SIMD-ONLY0-NEXT:    [[TMP2383:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4405]]
+// SIMD-ONLY0:       cond.end4405:
+// SIMD-ONLY0-NEXT:    [[COND4406:%.*]] = phi i64 [ [[TMP2382]], [[COND_TRUE4403]] ], [ [[TMP2383]], [[COND_FALSE4404]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4406]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2384:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2385:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4407:%.*]] = icmp eq i64 [[TMP2384]], [[TMP2385]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4407]], label [[COND_TRUE4409:%.*]], label [[COND_FALSE4410:%.*]]
+// SIMD-ONLY0:       cond.true4409:
+// SIMD-ONLY0-NEXT:    [[TMP2386:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4411:%.*]]
+// SIMD-ONLY0:       cond.false4410:
+// SIMD-ONLY0-NEXT:    [[TMP2387:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4411]]
+// SIMD-ONLY0:       cond.end4411:
+// SIMD-ONLY0-NEXT:    [[COND4412:%.*]] = phi i64 [ [[TMP2386]], [[COND_TRUE4409]] ], [ [[TMP2387]], [[COND_FALSE4410]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4412]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2388:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2389:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4413:%.*]] = icmp eq i64 [[TMP2388]], [[TMP2389]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4413]], label [[IF_THEN4415:%.*]], label [[IF_END4416:%.*]]
+// SIMD-ONLY0:       if.then4415:
+// SIMD-ONLY0-NEXT:    [[TMP2390:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2390]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4416]]
+// SIMD-ONLY0:       if.end4416:
+// SIMD-ONLY0-NEXT:    [[TMP2391:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2392:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4417:%.*]] = icmp eq i64 [[TMP2391]], [[TMP2392]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4417]], label [[IF_THEN4419:%.*]], label [[IF_END4420:%.*]]
+// SIMD-ONLY0:       if.then4419:
+// SIMD-ONLY0-NEXT:    [[TMP2393:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2393]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4420]]
+// SIMD-ONLY0:       if.end4420:
+// SIMD-ONLY0-NEXT:    [[TMP2394:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2395:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4421:%.*]] = icmp ugt i64 [[TMP2394]], [[TMP2395]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4421]], label [[COND_TRUE4423:%.*]], label [[COND_FALSE4424:%.*]]
+// SIMD-ONLY0:       cond.true4423:
+// SIMD-ONLY0-NEXT:    [[TMP2396:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4425:%.*]]
+// SIMD-ONLY0:       cond.false4424:
+// SIMD-ONLY0-NEXT:    [[TMP2397:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4425]]
+// SIMD-ONLY0:       cond.end4425:
+// SIMD-ONLY0-NEXT:    [[COND4426:%.*]] = phi i64 [ [[TMP2396]], [[COND_TRUE4423]] ], [ [[TMP2397]], [[COND_FALSE4424]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4426]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2398:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2399:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4427:%.*]] = icmp ult i64 [[TMP2398]], [[TMP2399]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4427]], label [[COND_TRUE4429:%.*]], label [[COND_FALSE4430:%.*]]
+// SIMD-ONLY0:       cond.true4429:
+// SIMD-ONLY0-NEXT:    [[TMP2400:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4431:%.*]]
+// SIMD-ONLY0:       cond.false4430:
+// SIMD-ONLY0-NEXT:    [[TMP2401:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4431]]
+// SIMD-ONLY0:       cond.end4431:
+// SIMD-ONLY0-NEXT:    [[COND4432:%.*]] = phi i64 [ [[TMP2400]], [[COND_TRUE4429]] ], [ [[TMP2401]], [[COND_FALSE4430]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4432]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2402:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2403:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4433:%.*]] = icmp ugt i64 [[TMP2402]], [[TMP2403]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4433]], label [[COND_TRUE4435:%.*]], label [[COND_FALSE4436:%.*]]
+// SIMD-ONLY0:       cond.true4435:
+// SIMD-ONLY0-NEXT:    [[TMP2404:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4437:%.*]]
+// SIMD-ONLY0:       cond.false4436:
+// SIMD-ONLY0-NEXT:    [[TMP2405:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4437]]
+// SIMD-ONLY0:       cond.end4437:
+// SIMD-ONLY0-NEXT:    [[COND4438:%.*]] = phi i64 [ [[TMP2404]], [[COND_TRUE4435]] ], [ [[TMP2405]], [[COND_FALSE4436]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4438]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2406:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2407:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4439:%.*]] = icmp ult i64 [[TMP2406]], [[TMP2407]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4439]], label [[COND_TRUE4441:%.*]], label [[COND_FALSE4442:%.*]]
+// SIMD-ONLY0:       cond.true4441:
+// SIMD-ONLY0-NEXT:    [[TMP2408:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4443:%.*]]
+// SIMD-ONLY0:       cond.false4442:
+// SIMD-ONLY0-NEXT:    [[TMP2409:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4443]]
+// SIMD-ONLY0:       cond.end4443:
+// SIMD-ONLY0-NEXT:    [[COND4444:%.*]] = phi i64 [ [[TMP2408]], [[COND_TRUE4441]] ], [ [[TMP2409]], [[COND_FALSE4442]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4444]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2410:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2411:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4445:%.*]] = icmp ugt i64 [[TMP2410]], [[TMP2411]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4445]], label [[IF_THEN4447:%.*]], label [[IF_END4448:%.*]]
+// SIMD-ONLY0:       if.then4447:
+// SIMD-ONLY0-NEXT:    [[TMP2412:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2412]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4448]]
+// SIMD-ONLY0:       if.end4448:
+// SIMD-ONLY0-NEXT:    [[TMP2413:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2414:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4449:%.*]] = icmp ult i64 [[TMP2413]], [[TMP2414]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4449]], label [[IF_THEN4451:%.*]], label [[IF_END4452:%.*]]
+// SIMD-ONLY0:       if.then4451:
+// SIMD-ONLY0-NEXT:    [[TMP2415:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2415]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4452]]
+// SIMD-ONLY0:       if.end4452:
+// SIMD-ONLY0-NEXT:    [[TMP2416:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2417:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4453:%.*]] = icmp ugt i64 [[TMP2416]], [[TMP2417]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4453]], label [[IF_THEN4455:%.*]], label [[IF_END4456:%.*]]
+// SIMD-ONLY0:       if.then4455:
+// SIMD-ONLY0-NEXT:    [[TMP2418:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2418]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4456]]
+// SIMD-ONLY0:       if.end4456:
+// SIMD-ONLY0-NEXT:    [[TMP2419:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2420:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4457:%.*]] = icmp ult i64 [[TMP2419]], [[TMP2420]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4457]], label [[IF_THEN4459:%.*]], label [[IF_END4460:%.*]]
+// SIMD-ONLY0:       if.then4459:
+// SIMD-ONLY0-NEXT:    [[TMP2421:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2421]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4460]]
+// SIMD-ONLY0:       if.end4460:
+// SIMD-ONLY0-NEXT:    [[TMP2422:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2423:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4461:%.*]] = icmp eq i64 [[TMP2422]], [[TMP2423]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4461]], label [[COND_TRUE4463:%.*]], label [[COND_FALSE4464:%.*]]
+// SIMD-ONLY0:       cond.true4463:
+// SIMD-ONLY0-NEXT:    [[TMP2424:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4465:%.*]]
+// SIMD-ONLY0:       cond.false4464:
+// SIMD-ONLY0-NEXT:    [[TMP2425:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4465]]
+// SIMD-ONLY0:       cond.end4465:
+// SIMD-ONLY0-NEXT:    [[COND4466:%.*]] = phi i64 [ [[TMP2424]], [[COND_TRUE4463]] ], [ [[TMP2425]], [[COND_FALSE4464]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4466]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2426:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2427:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4467:%.*]] = icmp eq i64 [[TMP2426]], [[TMP2427]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4467]], label [[COND_TRUE4469:%.*]], label [[COND_FALSE4470:%.*]]
+// SIMD-ONLY0:       cond.true4469:
+// SIMD-ONLY0-NEXT:    [[TMP2428:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4471:%.*]]
+// SIMD-ONLY0:       cond.false4470:
+// SIMD-ONLY0-NEXT:    [[TMP2429:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4471]]
+// SIMD-ONLY0:       cond.end4471:
+// SIMD-ONLY0-NEXT:    [[COND4472:%.*]] = phi i64 [ [[TMP2428]], [[COND_TRUE4469]] ], [ [[TMP2429]], [[COND_FALSE4470]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4472]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2430:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2431:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4473:%.*]] = icmp eq i64 [[TMP2430]], [[TMP2431]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4473]], label [[IF_THEN4475:%.*]], label [[IF_END4476:%.*]]
+// SIMD-ONLY0:       if.then4475:
+// SIMD-ONLY0-NEXT:    [[TMP2432:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2432]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4476]]
+// SIMD-ONLY0:       if.end4476:
+// SIMD-ONLY0-NEXT:    [[TMP2433:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2434:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4477:%.*]] = icmp eq i64 [[TMP2433]], [[TMP2434]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4477]], label [[IF_THEN4479:%.*]], label [[IF_END4480:%.*]]
+// SIMD-ONLY0:       if.then4479:
+// SIMD-ONLY0-NEXT:    [[TMP2435:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2435]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4480]]
+// SIMD-ONLY0:       if.end4480:
+// SIMD-ONLY0-NEXT:    [[TMP2436:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2437:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4481:%.*]] = icmp sgt i64 [[TMP2436]], [[TMP2437]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4481]], label [[COND_TRUE4483:%.*]], label [[COND_FALSE4484:%.*]]
+// SIMD-ONLY0:       cond.true4483:
+// SIMD-ONLY0-NEXT:    [[TMP2438:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4485:%.*]]
+// SIMD-ONLY0:       cond.false4484:
+// SIMD-ONLY0-NEXT:    [[TMP2439:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4485]]
+// SIMD-ONLY0:       cond.end4485:
+// SIMD-ONLY0-NEXT:    [[COND4486:%.*]] = phi i64 [ [[TMP2438]], [[COND_TRUE4483]] ], [ [[TMP2439]], [[COND_FALSE4484]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4486]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2440:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2441:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4487:%.*]] = icmp slt i64 [[TMP2440]], [[TMP2441]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4487]], label [[COND_TRUE4489:%.*]], label [[COND_FALSE4490:%.*]]
+// SIMD-ONLY0:       cond.true4489:
+// SIMD-ONLY0-NEXT:    [[TMP2442:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4491:%.*]]
+// SIMD-ONLY0:       cond.false4490:
+// SIMD-ONLY0-NEXT:    [[TMP2443:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4491]]
+// SIMD-ONLY0:       cond.end4491:
+// SIMD-ONLY0-NEXT:    [[COND4492:%.*]] = phi i64 [ [[TMP2442]], [[COND_TRUE4489]] ], [ [[TMP2443]], [[COND_FALSE4490]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4492]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2444:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2445:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4493:%.*]] = icmp sgt i64 [[TMP2444]], [[TMP2445]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4493]], label [[COND_TRUE4495:%.*]], label [[COND_FALSE4496:%.*]]
+// SIMD-ONLY0:       cond.true4495:
+// SIMD-ONLY0-NEXT:    [[TMP2446:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4497:%.*]]
+// SIMD-ONLY0:       cond.false4496:
+// SIMD-ONLY0-NEXT:    [[TMP2447:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4497]]
+// SIMD-ONLY0:       cond.end4497:
+// SIMD-ONLY0-NEXT:    [[COND4498:%.*]] = phi i64 [ [[TMP2446]], [[COND_TRUE4495]] ], [ [[TMP2447]], [[COND_FALSE4496]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4498]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2448:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2449:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4499:%.*]] = icmp slt i64 [[TMP2448]], [[TMP2449]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4499]], label [[COND_TRUE4501:%.*]], label [[COND_FALSE4502:%.*]]
+// SIMD-ONLY0:       cond.true4501:
+// SIMD-ONLY0-NEXT:    [[TMP2450:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4503:%.*]]
+// SIMD-ONLY0:       cond.false4502:
+// SIMD-ONLY0-NEXT:    [[TMP2451:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4503]]
+// SIMD-ONLY0:       cond.end4503:
+// SIMD-ONLY0-NEXT:    [[COND4504:%.*]] = phi i64 [ [[TMP2450]], [[COND_TRUE4501]] ], [ [[TMP2451]], [[COND_FALSE4502]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4504]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2452:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2453:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4505:%.*]] = icmp sgt i64 [[TMP2452]], [[TMP2453]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4505]], label [[IF_THEN4507:%.*]], label [[IF_END4508:%.*]]
+// SIMD-ONLY0:       if.then4507:
+// SIMD-ONLY0-NEXT:    [[TMP2454:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2454]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4508]]
+// SIMD-ONLY0:       if.end4508:
+// SIMD-ONLY0-NEXT:    [[TMP2455:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2456:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4509:%.*]] = icmp slt i64 [[TMP2455]], [[TMP2456]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4509]], label [[IF_THEN4511:%.*]], label [[IF_END4512:%.*]]
+// SIMD-ONLY0:       if.then4511:
+// SIMD-ONLY0-NEXT:    [[TMP2457:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2457]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4512]]
+// SIMD-ONLY0:       if.end4512:
+// SIMD-ONLY0-NEXT:    [[TMP2458:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2459:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4513:%.*]] = icmp sgt i64 [[TMP2458]], [[TMP2459]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4513]], label [[IF_THEN4515:%.*]], label [[IF_END4516:%.*]]
+// SIMD-ONLY0:       if.then4515:
+// SIMD-ONLY0-NEXT:    [[TMP2460:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2460]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4516]]
+// SIMD-ONLY0:       if.end4516:
+// SIMD-ONLY0-NEXT:    [[TMP2461:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2462:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4517:%.*]] = icmp slt i64 [[TMP2461]], [[TMP2462]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4517]], label [[IF_THEN4519:%.*]], label [[IF_END4520:%.*]]
+// SIMD-ONLY0:       if.then4519:
+// SIMD-ONLY0-NEXT:    [[TMP2463:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2463]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4520]]
+// SIMD-ONLY0:       if.end4520:
+// SIMD-ONLY0-NEXT:    [[TMP2464:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2465:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4521:%.*]] = icmp eq i64 [[TMP2464]], [[TMP2465]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4521]], label [[COND_TRUE4523:%.*]], label [[COND_FALSE4524:%.*]]
+// SIMD-ONLY0:       cond.true4523:
+// SIMD-ONLY0-NEXT:    [[TMP2466:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4525:%.*]]
+// SIMD-ONLY0:       cond.false4524:
+// SIMD-ONLY0-NEXT:    [[TMP2467:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4525]]
+// SIMD-ONLY0:       cond.end4525:
+// SIMD-ONLY0-NEXT:    [[COND4526:%.*]] = phi i64 [ [[TMP2466]], [[COND_TRUE4523]] ], [ [[TMP2467]], [[COND_FALSE4524]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4526]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2468:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2469:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4527:%.*]] = icmp eq i64 [[TMP2468]], [[TMP2469]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4527]], label [[COND_TRUE4529:%.*]], label [[COND_FALSE4530:%.*]]
+// SIMD-ONLY0:       cond.true4529:
+// SIMD-ONLY0-NEXT:    [[TMP2470:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4531:%.*]]
+// SIMD-ONLY0:       cond.false4530:
+// SIMD-ONLY0-NEXT:    [[TMP2471:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4531]]
+// SIMD-ONLY0:       cond.end4531:
+// SIMD-ONLY0-NEXT:    [[COND4532:%.*]] = phi i64 [ [[TMP2470]], [[COND_TRUE4529]] ], [ [[TMP2471]], [[COND_FALSE4530]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4532]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2472:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2473:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4533:%.*]] = icmp eq i64 [[TMP2472]], [[TMP2473]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4533]], label [[IF_THEN4535:%.*]], label [[IF_END4536:%.*]]
+// SIMD-ONLY0:       if.then4535:
+// SIMD-ONLY0-NEXT:    [[TMP2474:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2474]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4536]]
+// SIMD-ONLY0:       if.end4536:
+// SIMD-ONLY0-NEXT:    [[TMP2475:%.*]] = load i64, i64* [[LLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2476:%.*]] = load i64, i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4537:%.*]] = icmp eq i64 [[TMP2475]], [[TMP2476]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4537]], label [[IF_THEN4539:%.*]], label [[IF_END4540:%.*]]
+// SIMD-ONLY0:       if.then4539:
+// SIMD-ONLY0-NEXT:    [[TMP2477:%.*]] = load i64, i64* [[LLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2477]], i64* [[LLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4540]]
+// SIMD-ONLY0:       if.end4540:
+// SIMD-ONLY0-NEXT:    [[TMP2478:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2479:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4541:%.*]] = icmp ugt i64 [[TMP2478]], [[TMP2479]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4541]], label [[COND_TRUE4543:%.*]], label [[COND_FALSE4544:%.*]]
+// SIMD-ONLY0:       cond.true4543:
+// SIMD-ONLY0-NEXT:    [[TMP2480:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4545:%.*]]
+// SIMD-ONLY0:       cond.false4544:
+// SIMD-ONLY0-NEXT:    [[TMP2481:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4545]]
+// SIMD-ONLY0:       cond.end4545:
+// SIMD-ONLY0-NEXT:    [[COND4546:%.*]] = phi i64 [ [[TMP2480]], [[COND_TRUE4543]] ], [ [[TMP2481]], [[COND_FALSE4544]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4546]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2482:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2483:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4547:%.*]] = icmp ult i64 [[TMP2482]], [[TMP2483]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4547]], label [[COND_TRUE4549:%.*]], label [[COND_FALSE4550:%.*]]
+// SIMD-ONLY0:       cond.true4549:
+// SIMD-ONLY0-NEXT:    [[TMP2484:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4551:%.*]]
+// SIMD-ONLY0:       cond.false4550:
+// SIMD-ONLY0-NEXT:    [[TMP2485:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4551]]
+// SIMD-ONLY0:       cond.end4551:
+// SIMD-ONLY0-NEXT:    [[COND4552:%.*]] = phi i64 [ [[TMP2484]], [[COND_TRUE4549]] ], [ [[TMP2485]], [[COND_FALSE4550]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4552]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2486:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2487:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4553:%.*]] = icmp ugt i64 [[TMP2486]], [[TMP2487]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4553]], label [[COND_TRUE4555:%.*]], label [[COND_FALSE4556:%.*]]
+// SIMD-ONLY0:       cond.true4555:
+// SIMD-ONLY0-NEXT:    [[TMP2488:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4557:%.*]]
+// SIMD-ONLY0:       cond.false4556:
+// SIMD-ONLY0-NEXT:    [[TMP2489:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4557]]
+// SIMD-ONLY0:       cond.end4557:
+// SIMD-ONLY0-NEXT:    [[COND4558:%.*]] = phi i64 [ [[TMP2488]], [[COND_TRUE4555]] ], [ [[TMP2489]], [[COND_FALSE4556]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4558]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2490:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2491:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4559:%.*]] = icmp ult i64 [[TMP2490]], [[TMP2491]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4559]], label [[COND_TRUE4561:%.*]], label [[COND_FALSE4562:%.*]]
+// SIMD-ONLY0:       cond.true4561:
+// SIMD-ONLY0-NEXT:    [[TMP2492:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4563:%.*]]
+// SIMD-ONLY0:       cond.false4562:
+// SIMD-ONLY0-NEXT:    [[TMP2493:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4563]]
+// SIMD-ONLY0:       cond.end4563:
+// SIMD-ONLY0-NEXT:    [[COND4564:%.*]] = phi i64 [ [[TMP2492]], [[COND_TRUE4561]] ], [ [[TMP2493]], [[COND_FALSE4562]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4564]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2494:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2495:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4565:%.*]] = icmp ugt i64 [[TMP2494]], [[TMP2495]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4565]], label [[IF_THEN4567:%.*]], label [[IF_END4568:%.*]]
+// SIMD-ONLY0:       if.then4567:
+// SIMD-ONLY0-NEXT:    [[TMP2496:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2496]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4568]]
+// SIMD-ONLY0:       if.end4568:
+// SIMD-ONLY0-NEXT:    [[TMP2497:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2498:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4569:%.*]] = icmp ult i64 [[TMP2497]], [[TMP2498]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4569]], label [[IF_THEN4571:%.*]], label [[IF_END4572:%.*]]
+// SIMD-ONLY0:       if.then4571:
+// SIMD-ONLY0-NEXT:    [[TMP2499:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2499]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4572]]
+// SIMD-ONLY0:       if.end4572:
+// SIMD-ONLY0-NEXT:    [[TMP2500:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2501:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4573:%.*]] = icmp ugt i64 [[TMP2500]], [[TMP2501]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4573]], label [[IF_THEN4575:%.*]], label [[IF_END4576:%.*]]
+// SIMD-ONLY0:       if.then4575:
+// SIMD-ONLY0-NEXT:    [[TMP2502:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2502]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4576]]
+// SIMD-ONLY0:       if.end4576:
+// SIMD-ONLY0-NEXT:    [[TMP2503:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2504:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4577:%.*]] = icmp ult i64 [[TMP2503]], [[TMP2504]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4577]], label [[IF_THEN4579:%.*]], label [[IF_END4580:%.*]]
+// SIMD-ONLY0:       if.then4579:
+// SIMD-ONLY0-NEXT:    [[TMP2505:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2505]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4580]]
+// SIMD-ONLY0:       if.end4580:
+// SIMD-ONLY0-NEXT:    [[TMP2506:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2507:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4581:%.*]] = icmp eq i64 [[TMP2506]], [[TMP2507]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4581]], label [[COND_TRUE4583:%.*]], label [[COND_FALSE4584:%.*]]
+// SIMD-ONLY0:       cond.true4583:
+// SIMD-ONLY0-NEXT:    [[TMP2508:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4585:%.*]]
+// SIMD-ONLY0:       cond.false4584:
+// SIMD-ONLY0-NEXT:    [[TMP2509:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4585]]
+// SIMD-ONLY0:       cond.end4585:
+// SIMD-ONLY0-NEXT:    [[COND4586:%.*]] = phi i64 [ [[TMP2508]], [[COND_TRUE4583]] ], [ [[TMP2509]], [[COND_FALSE4584]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4586]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2510:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2511:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4587:%.*]] = icmp eq i64 [[TMP2510]], [[TMP2511]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4587]], label [[COND_TRUE4589:%.*]], label [[COND_FALSE4590:%.*]]
+// SIMD-ONLY0:       cond.true4589:
+// SIMD-ONLY0-NEXT:    [[TMP2512:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4591:%.*]]
+// SIMD-ONLY0:       cond.false4590:
+// SIMD-ONLY0-NEXT:    [[TMP2513:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[COND_END4591]]
+// SIMD-ONLY0:       cond.end4591:
+// SIMD-ONLY0-NEXT:    [[COND4592:%.*]] = phi i64 [ [[TMP2512]], [[COND_TRUE4589]] ], [ [[TMP2513]], [[COND_FALSE4590]] ]
+// SIMD-ONLY0-NEXT:    store i64 [[COND4592]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2514:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2515:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4593:%.*]] = icmp eq i64 [[TMP2514]], [[TMP2515]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4593]], label [[IF_THEN4595:%.*]], label [[IF_END4596:%.*]]
+// SIMD-ONLY0:       if.then4595:
+// SIMD-ONLY0-NEXT:    [[TMP2516:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2516]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4596]]
+// SIMD-ONLY0:       if.end4596:
+// SIMD-ONLY0-NEXT:    [[TMP2517:%.*]] = load i64, i64* [[ULLE]], align 8
+// SIMD-ONLY0-NEXT:    [[TMP2518:%.*]] = load i64, i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    [[CMP4597:%.*]] = icmp eq i64 [[TMP2517]], [[TMP2518]]
+// SIMD-ONLY0-NEXT:    br i1 [[CMP4597]], label [[IF_THEN4599:%.*]], label [[IF_END4600:%.*]]
+// SIMD-ONLY0:       if.then4599:
+// SIMD-ONLY0-NEXT:    [[TMP2519:%.*]] = load i64, i64* [[ULLD]], align 8
+// SIMD-ONLY0-NEXT:    store i64 [[TMP2519]], i64* [[ULLX]], align 8
+// SIMD-ONLY0-NEXT:    br label [[IF_END4600]]
+// SIMD-ONLY0:       if.end4600:
+// SIMD-ONLY0-NEXT:    ret void
+//

llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp

OpenMPIRBuilder::InsertPointTy OpenMPIRBuilder::createAtomicCompare(
   if (Op == OMPAtomicCompareOp::EQ) {
     unsigned Addrspace = cast<PointerType>(X.Var->getType())->getAddressSpace();
     IntegerType *IntCastTy =
         IntegerType::get(M.getContext(), X.ElemTy->getScalarSizeInBits());
     Value *XAddr =
         X.ElemTy->isIntegerTy()
             ? X.Var
             : Builder.CreateBitCast(X.Var, IntCastTy->getPointerTo(Addrspace));
+    Value *NewE = E->getType()->isFloatingPointTy()
+                      ? Builder.CreateFPToSI(E, IntCastTy)
+                      : E;
+    Value *NewD = D->getType()->isFloatingPointTy()
+                      ? Builder.CreateFPToSI(D, IntCastTy)
+                      : D;
     AtomicOrdering Failure = AtomicCmpXchgInst::getStrongestFailureOrdering(AO);
     // We don't need the result for now.
-    (void)Builder.CreateAtomicCmpXchg(XAddr, E, D, MaybeAlign(), AO, Failure);
+    (void)Builder.CreateAtomicCmpXchg(XAddr, NewE, NewD, MaybeAlign(), AO,
+                                      Failure);
   } else {
     assert((Op == OMPAtomicCompareOp::MAX || Op == OMPAtomicCompareOp::MIN) &&
            "Op should be either max or min at this point");
     assert(X.ElemTy->isIntegerTy() &&
            "max and min operators only support integer type");
 
     // Reverse the ordop as the OpenMP forms are different from LLVM forms.
     // Let's take max as example.