[ARM] Make getInstSizeInBytes() use instruction size from InstrInfo.td

[tyb0807]

Summary

Currently, ARMBaseInstrInfo::getInstSizeInBytes() uses hard-coded
instruction size for some pseudo-instructions, while this
information should ideally be found in ARMInstrInfo.td,
ARMInstrThumb(2).td files (which can be accessed via MCInstrDesc). Hence,
the .td files should be updated and no hard-coded instruction sizes
should be used by getInstSizeInBytes() anymore.

[tyb0807]

Fix typo in commit message

[nickdesaulniers]

Please appease the linter for the newly added tests.

Other reviewers should be careful with review here. My major concern that I have not yet verified is whether these pseudo's always expand to the same number of instructions or not, which would affect their corresponding size.

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

759

so the Aarch64 version of this patch does the opposite. It checks the getSize() first, then returns early before the switch.
https://reviews.llvm.org/D117970
Is there a reason we can't or shouldn't be consistent between the two targets?

llvm/unittests/Target/ARM/CMakeLists.txt

13

should this be a separate change?

llvm/utils/gn/secondary/llvm/unittests/Target/ARM/BUILD.gn

5

different change?

[tyb0807]

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

759

So in the AArch64 version, the default size of an expanded pseudo-instruction is 4 bytes, while for ARM, it is more complicated to define such a default size: Thumb1 instructions are 2 bytes, Thumb2 instructions are 2-4 bytes, and ARM instructions are 4 bytes. As a result, we return 0 for pseudo-instructions that we don't have any information about the size.

I'll move the AArch64 code into the default case as well, to make the comparison easier, and add a comment explaining this

llvm/unittests/Target/ARM/CMakeLists.txt

13

Do you mean the test should be in a separate change? Any reason for doing this?

llvm/utils/gn/secondary/llvm/unittests/Target/ARM/BUILD.gn

5

See reply above

[tyb0807]

clang-format, update comment to clarify the intention of the code, and add new
comments specifying fixed constant sizes of pseudo-instructions

[tyb0807]

Indeed, the pseudo's that are updated in the .td files always expand to the same instruction sequence, hence their size in bytes are fixed. Or maybe you mean you are not sure if the expansion would change in the future (i.e. the pseudo's will be expanded to a different instruction sequence)?

[lenary]

In D118009#3267198, @nickdesaulniers wrote:

Other reviewers should be careful with review here. My major concern that I have not yet verified is whether these pseudo's always expand to the same number of instructions or not, which would affect their corresponding size.

If these sizes are wrong, then this patch doesn't make that worse (but this is a good opportunity to verify that the sizes are correct). This override tends to only be required for pseudos that are expanded very late (usually in the Asm Printer), and problems with it tend to affect branch relaxation, iirc.

llvm/unittests/Target/ARM/CMakeLists.txt

13

Adding tests with these changes seems like the right thing to do, and these tests need a MIR parser, so this change is required.

llvm/unittests/Target/ARM/InstSizes.cpp

88

Can you add tests for the instructions remaining in the switch block, each of which has more complex logic for calculating its size? Right now you're only testing the things you moved out of the switch block.

[tyb0807]

Update new tests for variable-sized pseudo-instructions

[AaronLiu]

Looks like linking the following test caused many(57 for now) LoP-LE build failures (first build failure: https://lab.llvm.org/buildbot/#/builders/57/builds/14559):

186.515 [21/53/841] Linking CXX executable unittests/Target/ARM/ARMTests
FAILED: unittests/Target/ARM/ARMTests 
: && /home/buildbots/clang.11.0.0/bin/clang++ --gcc-toolchain=/opt/rh/devtoolset-7/root/usr  -fPIC -fvisibility-inlines-hidden -Werror -Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion -Wmisleading-indentation -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG  -Wl,--gc-sections unittests/Target/ARM/CMakeFiles/ARMTests.dir/MachineInstrTest.cpp.o unittests/Target/ARM/CMakeFiles/ARMTests.dir/InstSizes.cpp.o  -o unittests/Target/ARM/ARMTests  -Wl,-rpath,/home/buildbots/docker-RHEL-buildbot/SetupBot/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/build/lib  lib/libLLVMARMCodeGen.so.14git  lib/libLLVMARMDesc.so.14git  lib/libLLVMARMInfo.so.14git  lib/libLLVMGlobalISel.so.14git  lib/libLLVMMIRParser.so.14git  lib/libLLVMSelectionDAG.so.14git  -lpthread  lib/libgtest_main.so.14git  lib/libgtest.so.14git  -lpthread  lib/libLLVMCodeGen.so.14git  lib/libLLVMTarget.so.14git  lib/libLLVMMC.so.14git  lib/libLLVMSupport.so.14git  -Wl,-rpath-link,/home/buildbots/docker-RHEL-buildbot/SetupBot/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/build/lib && :
/opt/rh/devtoolset-7/root/usr/lib/gcc/ppc64le-redhat-linux/7/../../../../bin/ld: unittests/Target/ARM/CMakeFiles/ARMTests.dir/InstSizes.cpp.o: undefined reference to symbol '_ZN4llvm10DataLayout5clearEv'
/home/buildbots/docker-RHEL-buildbot/SetupBot/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/build/lib/libLLVMCore.so.14git: error adding symbols: DSO missing from command line
clang++: error: linker command failed with exit code 1 (use -v to see invocation)
289.769 [21/2/892] Building CXX object tools/clang/unittests/Tooling/CMakeFiles/ToolingTests.dir/SourceCodeTest.cpp.o
ninja: build stopped: subcommand failed.
program finished with exit code 1
elapsedTime=424.974897

[tyb0807]

Sorry for the linking issue, this has been fixed in commit ec00c9cdeb5ee9fc7846cb3d2a4d53eba2c35a43

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 /// GetInstSize - Return the size of the specified MachineInstr.
 ///
 unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   const MachineBasicBlock &MBB = *MI.getParent();
   const MachineFunction *MF = MBB.getParent();
   const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
 
   const MCInstrDesc &MCID = MI.getDesc();
-  if (MCID.getSize())
-    return MCID.getSize();
 
   switch (MI.getOpcode()) {
   default:
     // pseudo-instruction sizes are zero.
-    return 0;
+    return MCID.getSize();
   case TargetOpcode::BUNDLE:
     return getInstBundleLength(MI);
-  case ARM::MOVi16_ga_pcrel:
-  case ARM::MOVTi16_ga_pcrel:
-  case ARM::t2MOVi16_ga_pcrel:
-  case ARM::t2MOVTi16_ga_pcrel:
-    return 4;
-  case ARM::MOVi32imm:
-  case ARM::t2MOVi32imm:
-    return 8;
   case ARM::CONSTPOOL_ENTRY:
   case ARM::JUMPTABLE_INSTS:
   case ARM::JUMPTABLE_ADDRS:
   case ARM::JUMPTABLE_TBB:
   case ARM::JUMPTABLE_TBH:
     // If this machine instr is a constant pool entry, its size is recorded as
     // operand #2.
     return MI.getOperand(2).getImm();
-  case ARM::Int_eh_sjlj_longjmp:
-    return 16;
-  case ARM::tInt_eh_sjlj_longjmp:
-    return 10;
-  case ARM::tInt_WIN_eh_sjlj_longjmp:
-    return 12;
-  case ARM::Int_eh_sjlj_setjmp:
-  case ARM::Int_eh_sjlj_setjmp_nofp:
-    return 20;
-  case ARM::tInt_eh_sjlj_setjmp:
-  case ARM::t2Int_eh_sjlj_setjmp:
-  case ARM::t2Int_eh_sjlj_setjmp_nofp:
-    return 12;
   case ARM::SPACE:
     return MI.getOperand(1).getImm();
   case ARM::INLINEASM:
   case ARM::INLINEASM_BR: {
     // If this machine instr is an inline asm, measure it.
     unsigned Size = getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
     if (!MF->getInfo<ARMFunctionInfo>()->isThumbFunction())
       Size = alignTo(Size, 4);
     return Size;
   }
-  case ARM::SpeculationBarrierISBDSBEndBB:
-  case ARM::t2SpeculationBarrierISBDSBEndBB:
-    // This gets lowered to 2 4-byte instructions.
-    return 8;
-  case ARM::SpeculationBarrierSBEndBB:
-  case ARM::t2SpeculationBarrierSBEndBB:
-    // This gets lowered to 1 4-byte instructions.
-    return 4;
   }
 }
 
 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {
   unsigned Size = 0;
   MachineBasicBlock::const_instr_iterator I = MI.getIterator();
   MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
   while (++I != E && I->isInsideBundle()) {

llvm/lib/Target/ARM/ARMInstrInfo.td

def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
   let Inst{25} = 1;
   let DecoderMethod = "DecodeArmMOVTWInstruction";
 }
 
 def : InstAlias<"mov${p} $Rd, $imm",
                 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>,
         Requires<[IsARM, HasV6T2]>;
 
+let Size = 4 in
 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
                                 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
                       Sched<[WriteALU]>;
 
 let Constraints = "$src = $Rd" in {
 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
                   (ins GPR:$src, imm0_65535_expr:$imm),
                   DPFrm, IIC_iMOVi,
                   "movt", "\t$Rd, $imm",
                   [(set GPRnopc:$Rd,
                         (or (and GPR:$src, 0xffff),
                             lo16AllZero:$imm))]>, UnaryDP,
                   Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
   bits<4> Rd;
   bits<16> imm;
   let Inst{15-12} = Rd;
   let Inst{11-0}  = imm{11-0};
   let Inst{19-16} = imm{15-12};
   let Inst{20} = 0;
   let Inst{25} = 1;
   let DecoderMethod = "DecodeArmMOVTWInstruction";
 }
 
+let Size = 4 in
 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
                       (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
                       Sched<[WriteALU]>;
 
 } // Constraints
 
 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
       Requires<[IsARM, HasV6T2]>;

 //   all of the callee-saved registers, which is exactly what we want.
 //   A constant value is passed in $val, and we use the location as a scratch.
 //
 // These are pseudo-instructions and are lowered to individual MC-insts, so
 // no encoding information is necessary.
 let Defs =
   [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR,
     Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
-  hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
+  hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1, Size = 20 in {
   def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
                                NoItinerary,
                          [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
                            Requires<[IsARM, HasVFP2]>;
 }
 
 let Defs =
   [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR ],
-  hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
+  hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1, Size = 20 in {
   def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
                                    NoItinerary,
                          [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
                                 Requires<[IsARM, NoVFP]>;
 }
 
 // FIXME: Non-IOS version(s)
-let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
+let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, Size = 16,
     Defs = [ R7, LR, SP ] in {
 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
                              NoItinerary,
                          [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
                                 Requires<[IsARM]>;
 }
 
 let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in
def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst),
                   Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
 
 // Large immediate handling.
 
 // 32-bit immediate using two piece mod_imms or movw + movt.
 // This is a single pseudo instruction, the benefit is that it can be remat'd
 // as a single unit instead of having to handle reg inputs.
 // FIXME: Remove this when we can do generalized remat.
-let isReMaterializable = 1, isMoveImm = 1 in
+let isReMaterializable = 1, isMoveImm = 1, Size = 8 in
 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
                            [(set GPR:$dst, (arm_i32imm:$src))]>,
                            Requires<[IsARM]>;
 
 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
                                [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
                     Requires<[IsARM, DontUseMovt]>;
 

 let mayLoad = 1, mayStore =1, hasSideEffects = 1, hasNoSchedulingInfo = 1 in
 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
                        NoItinerary,
                        [(set GPR:$Rd, (int_arm_space timm:$size, GPR:$Rn))]>;
 
 // SpeculationBarrierEndBB must only be used after an unconditional control
 // flow, i.e. after a terminator for which isBarrier is True.
 let hasSideEffects = 1, isCodeGenOnly = 1, isTerminator = 1, isBarrier = 1 in {
+  let Size = 8 in
   def SpeculationBarrierISBDSBEndBB
       : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
+  let Size = 4 in
   def SpeculationBarrierSBEndBB
       : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
 }
 
 //===----------------------------------
 // Atomic cmpxchg for -O0
 //===----------------------------------
 

llvm/lib/Target/ARM/ARMInstrThumb.td

 // containing function to save/restore registers, we can't keep anything live in
 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
 // tromped upon when we get here from a longjmp(). We force everything out of
 // registers except for our own input by listing the relevant registers in
 // Defs. By doing so, we also cause the prologue/epilogue code to actively
 // preserve all of the callee-saved registers, which is exactly what we want.
 // $val is a scratch register for our use.
 let Defs = [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7, R12, CPSR ],
-    hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
+    hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, Size = 12,
     usesCustomInserter = 1 in
 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
                                   AddrModeNone, 0, NoItinerary, "","",
                           [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
 
 // FIXME: Non-IOS version(s)
 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
-    Defs = [ R7, LR, SP ] in
+    Size = 10, Defs = [ R7, LR, SP ] in
 def tInt_eh_sjlj_longjmp : XI<(outs), (ins tGPR:$src, tGPR:$scratch),
                               AddrModeNone, 0, IndexModeNone,
                               Pseudo, NoItinerary, "", "",
                               [(ARMeh_sjlj_longjmp tGPR:$src, tGPR:$scratch)]>,
                              Requires<[IsThumb,IsNotWindows]>;
 
 // (Windows is Thumb2-only)
 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
-    Defs = [ R11, LR, SP ] in
+    Size = 12, Defs = [ R11, LR, SP ] in
 def tInt_WIN_eh_sjlj_longjmp
   : XI<(outs), (ins GPR:$src, GPR:$scratch), AddrModeNone, 0, IndexModeNone,
        Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
     Requires<[IsThumb,IsWindows]>;
 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //

llvm/lib/Target/ARM/ARMInstrThumb2.td

def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
   let Inst{7-0}   = imm{7-0};
   let DecoderMethod = "DecodeT2MOVTWInstruction";
 }
 
 def : InstAlias<"mov${p} $Rd, $imm",
                 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p), 0>,
                 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteALU]>;
 
+let Size = 4 in
 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
                                 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
                         Sched<[WriteALU]>;
 
 let Constraints = "$src = $Rd" in {
 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
                     (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
                     "movt", "\t$Rd, $imm",
def t2MOVTi16 : T2I<(outs rGPR:$Rd),
   let Inst{11-8}  = Rd;
   let Inst{19-16} = imm{15-12};
   let Inst{26}    = imm{11};
   let Inst{14-12} = imm{10-8};
   let Inst{7-0}   = imm{7-0};
   let DecoderMethod = "DecodeT2MOVTWInstruction";
 }
 
+let Size = 4 in
 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
                      (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
                      Sched<[WriteALU]>, Requires<[IsThumb, HasV8MBaseline]>;
 } // Constraints
 
 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
 
 //===----------------------------------------------------------------------===//

 //   when we get here from a longjmp(). We force everything out of registers
 //   except for our own input by listing the relevant registers in Defs. By
 //   doing so, we also cause the prologue/epilogue code to actively preserve
 //   all of the callee-saved registers, which is exactly what we want.
 //   $val is a scratch register for our use.
 let Defs =
   [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR,
     Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
-  hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
+  hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, Size = 12,
   usesCustomInserter = 1 in {
   def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
                                AddrModeNone, 0, NoItinerary, "", "",
                           [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
                              Requires<[IsThumb2, HasVFP2]>;
 }
 
 let Defs =
   [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR ],
-  hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
+  hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, Size = 12,
   usesCustomInserter = 1 in {
   def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
                                AddrModeNone, 0, NoItinerary, "", "",
                           [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
                                   Requires<[IsThumb2, NoVFP]>;
 }
 
 

 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //
 
 // 32-bit immediate using movw + movt.
 // This is a single pseudo instruction to make it re-materializable.
 // FIXME: Remove this when we can do generalized remat.
-let isReMaterializable = 1, isMoveImm = 1 in
+let isReMaterializable = 1, isMoveImm = 1, Size = 8 in
 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
                             [(set rGPR:$dst, (i32 imm:$src))]>,
                             Requires<[IsThumb, UseMovt]>;
 
 // Pseudo instruction that combines movw + movt + add pc (if pic).
 // It also makes it possible to rematerialize the instructions.
 // FIXME: Remove this when we can do generalized remat and when machine licm
 // can properly the instructions.

 def : InstAlias<"pssbb", (t2DSB 0x4, 14, 0), 1>, Requires<[HasDB, IsThumb2]>;
 
 // Armv8-R 'Data Full Barrier'
 def : InstAlias<"dfb${p}", (t2DSB 0xc, pred:$p), 1>, Requires<[HasDFB]>;
 
 // SpeculationBarrierEndBB must only be used after an unconditional control
 // flow, i.e. after a terminator for which isBarrier is True.
 let hasSideEffects = 1, isCodeGenOnly = 1, isTerminator = 1, isBarrier = 1 in {
+  let Size = 8 in
   def t2SpeculationBarrierISBDSBEndBB
       : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
+  let Size = 4 in
   def t2SpeculationBarrierSBEndBB
       : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
 }
 
 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
 // width specifier.
 def : t2InstAlias<"ldr${p} $Rt, $addr",
                   (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;

llvm/unittests/Target/ARM/CMakeLists.txt

 include_directories(
   ${LLVM_MAIN_SRC_DIR}/lib/Target/ARM
   ${LLVM_BINARY_DIR}/lib/Target/ARM
   )
 
 set(LLVM_LINK_COMPONENTS
   ARMCodeGen
   ARMDesc
   ARMInfo
   CodeGen
   GlobalISel
   MC
+  MIRParser
   SelectionDAG
   Support
   Target
 )
 
 add_llvm_target_unittest(ARMTests
   MachineInstrTest.cpp
+  InstSizes.cpp
   )

llvm/unittests/Target/ARM/InstSizes.cpp

+#include "ARMInstrInfo.h"
+#include "ARMSubtarget.h"
+#include "ARMTargetMachine.h"
+#include "llvm/CodeGen/MIRParser/MIRParser.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/TargetSelect.h"
+
+#include "gtest/gtest.h"
+
+using namespace llvm;
+
+namespace {
+/// The \p InputIRSnippet is only needed for things that can't be expressed in
+/// the \p InputMIRSnippet (global variables etc)
+/// TODO: Some of this might be useful for other architectures as well - extract
+///       the platform-independent parts somewhere they can be reused.
+void runChecks(
+    LLVMTargetMachine *TM, const ARMBaseInstrInfo *II, const StringRef InputIRSnippet,
+    const StringRef InputMIRSnippet, unsigned Expected,
+    std::function<void(const ARMBaseInstrInfo &, MachineFunction &, unsigned &)> Checks) {
+  LLVMContext Context;
+
+  auto MIRString =
+    "--- |\n"
+    "  declare void @sizes()\n"
+    + InputIRSnippet.str() +
+    "...\n"
+    "---\n"
+    "name: sizes\n"
+    "body: |\n"
+    "  bb.0:\n"
+    + InputMIRSnippet.str();
+
+  std::unique_ptr<MemoryBuffer> MBuffer = MemoryBuffer::getMemBuffer(MIRString);
+  std::unique_ptr<MIRParser> MParser =
+      createMIRParser(std::move(MBuffer), Context);
+  ASSERT_TRUE(MParser);
+
+  std::unique_ptr<Module> M = MParser->parseIRModule();
+  ASSERT_TRUE(M);
+
+  M->setTargetTriple(TM->getTargetTriple().getTriple());
+  M->setDataLayout(TM->createDataLayout());
+
+  MachineModuleInfo MMI(TM);
+  bool Res = MParser->parseMachineFunctions(*M, MMI);
+  ASSERT_FALSE(Res);
+
+  auto F = M->getFunction("sizes");
+  ASSERT_TRUE(F != nullptr);
+  auto &MF = MMI.getOrCreateMachineFunction(*F);
+
+  Checks(*II, MF, Expected);
+}
+
+} // anonymous namespace
+
+TEST(InstSizes, PseudoInst) {
+  LLVMInitializeARMTargetInfo();
+  LLVMInitializeARMTarget();
+  LLVMInitializeARMTargetMC();
+
+  auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi"));
+  std::string Error;
+  const Target *T = TargetRegistry::lookupTarget(TT, Error);
+  if (!T) {
+    dbgs() << Error;
+    return;
+  }
+
+  TargetOptions Options;
+  auto TM = std::unique_ptr<LLVMTargetMachine>(
+    static_cast<LLVMTargetMachine*>(
+      T->createTargetMachine(TT, "generic", "", Options, None, None,
+                             CodeGenOpt::Default)));
+  ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
+                  std::string(TM->getTargetFeatureString()),
+                  *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
+  const ARMBaseInstrInfo *II = ST.getInstrInfo();
+
+  auto cmpInstSize = [](const ARMBaseInstrInfo &II, MachineFunction &MF, unsigned &Expected) {
+    auto I = MF.begin()->begin();
+    EXPECT_EQ(Expected, II.getInstSizeInBytes(*I));
+  };
+
+  runChecks(TM.get(), II, "",
+            "    $r0 = MOVi16_ga_pcrel"
+            " target-flags(arm-lo16, arm-nonlazy) @sizes, 0\n",
+            4u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    $r0 = MOVTi16_ga_pcrel $r0,"
+            " target-flags(arm-hi16, arm-nonlazy) @sizes, 0\n",
+            4u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    $r0 = t2MOVi16_ga_pcrel"
+            " target-flags(arm-lo16, arm-nonlazy) @sizes, 0\n",
+            4u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    $r0 = t2MOVTi16_ga_pcrel $r0,"
+            " target-flags(arm-hi16, arm-nonlazy) @sizes, 0\n",
+            4u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    $r0 = MOVi32imm 2\n",
+            8u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    $r0 = t2MOVi32imm 2\n",
+            8u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    SpeculationBarrierISBDSBEndBB\n"
+            "    tBX_RET 14, $noreg, implicit $r0\n",
+            8u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    t2SpeculationBarrierISBDSBEndBB\n"
+            "    tBX_RET 14, $noreg, implicit $r0\n",
+            8u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    SpeculationBarrierSBEndBB\n"
+            "    tBX_RET 14, $noreg, implicit $r0\n",
+            4u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    t2SpeculationBarrierSBEndBB\n"
+            "    tBX_RET 14, $noreg, implicit $r0\n",
+            4u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    Int_eh_sjlj_longjmp $r0, $r1, implicit-def $r7,"
+            " implicit-def $lr, implicit-def $sp\n",
+            16u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    tInt_eh_sjlj_longjmp $r0, $r1, implicit-def $r7,"
+            " implicit-def $lr, implicit-def $sp\n",
+            10u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    tInt_WIN_eh_sjlj_longjmp $r0, $r1, implicit-def $r11,"
+            " implicit-def $lr, implicit-def $sp\n",
+            12u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    Int_eh_sjlj_setjmp $r0, $r1, implicit-def $r0,"
+            " implicit-def $r1, implicit-def $r2, implicit-def $r3,"
+            " implicit-def $r4, implicit-def $r5, implicit-def $r6,"
+            " implicit-def $r7, implicit-def $r8, implicit-def $r9,"
+            " implicit-def $r10, implicit-def $r11, implicit-def $r12,"
+            " implicit-def $lr, implicit-def $cpsr, implicit-def $q0,"
+            " implicit-def $q1, implicit-def $q2, implicit-def $q3,"
+            " implicit-def $q4, implicit-def $q5, implicit-def $q6,"
+            " implicit-def $q7, implicit-def $q8, implicit-def $q9,"
+            " implicit-def $q10, implicit-def $q11, implicit-def $q12,"
+            " implicit-def $q13, implicit-def $q14, implicit-def $q15\n"
+            "    tBX_RET 14, $noreg, implicit $r0\n",
+            20u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    Int_eh_sjlj_setjmp_nofp $r0, $r1, implicit-def $r0,"
+            " implicit-def $r1, implicit-def $r2, implicit-def $r3,"
+            " implicit-def $r4, implicit-def $r5, implicit-def $r6,"
+            " implicit-def $r7, implicit-def $r8, implicit-def $r9,"
+            " implicit-def $r10, implicit-def $r11, implicit-def $r12,"
+            " implicit-def $lr, implicit-def $cpsr\n"
+            "    tBX_RET 14, $noreg, implicit $r0\n",
+            20u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    tInt_eh_sjlj_setjmp $r0, $r1, implicit-def $r0,"
+            " implicit-def $r1, implicit-def $r2, implicit-def $r3,"
+            " implicit-def $r4, implicit-def $r5, implicit-def $r6,"
+            " implicit-def $r7, implicit-def $r12, implicit-def $cpsr\n"
+            "    tBX_RET 14, $noreg, implicit $r0\n",
+            12u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    t2Int_eh_sjlj_setjmp $r0, $r1, implicit-def $r0,"
+            " implicit-def $r1, implicit-def $r2, implicit-def $r3,"
+            " implicit-def $r4, implicit-def $r5, implicit-def $r6,"
+            " implicit-def $r7, implicit-def $r8, implicit-def $r9,"
+            " implicit-def $r10, implicit-def $r11, implicit-def $r12,"
+            " implicit-def $lr, implicit-def $cpsr, implicit-def $q0,"
+            " implicit-def $q1, implicit-def $q2, implicit-def $q3,"
+            " implicit-def $q8, implicit-def $q9, implicit-def $q10,"
+            " implicit-def $q11, implicit-def $q12, implicit-def $q13,"
+            " implicit-def $q14, implicit-def $q15\n"
+            "    tBX_RET 14, $noreg, implicit $r0\n",
+            12u, cmpInstSize);
+
+  runChecks(TM.get(), II, "",
+            "    t2Int_eh_sjlj_setjmp_nofp $r0, $r1, implicit-def $r0,"
+            " implicit-def $r1, implicit-def $r2, implicit-def $r3,"
+            " implicit-def $r4, implicit-def $r5, implicit-def $r6,"
+            " implicit-def $r7, implicit-def $r8, implicit-def $r9,"
+            " implicit-def $r10, implicit-def $r11, implicit-def $r12,"
+            " implicit-def $lr, implicit-def $cpsr\n"
+            "    tBX_RET 14, $noreg, implicit $r0\n",
+            12u, cmpInstSize);
+}
+

llvm/utils/gn/secondary/llvm/unittests/Target/ARM/BUILD.gn

 import("//llvm/utils/unittest/unittest.gni")
 
 unittest("ARMTests") {
   deps = [
+    "//llvm/lib/CodeGen/MIRParser",
     "//llvm/lib/MC",
     "//llvm/lib/Support",
     "//llvm/lib/Target",
     "//llvm/lib/Target/ARM:LLVMARMCodeGen",
     "//llvm/lib/Target/ARM/MCTargetDesc",
     "//llvm/lib/Target/ARM/TargetInfo",
     "//llvm/lib/Target/ARM/Utils",
   ]
   include_dirs = [ "//llvm/lib/Target/ARM" ]
-  sources = [ "MachineInstrTest.cpp" ]
+  sources = [ "MachineInstrTest.cpp", "InstSizes.cpp" ]
 }