[RISCV] Add patterns for vector widening floating-point fused multiply-add instructions

[jacquesguan]

Summary

Add patterns for vector widening floating-point fused multiply-add instructions.

[jacquesguan]

ping.

[craig.topper]

Should we be testing half->float?

[jacquesguan]

Add half->float test cases.

[jacquesguan]

In D117546#3268393, @craig.topper wrote:

Should we be testing half->float?

Done.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

431

This isn't crucial but I wonder if these patterns could be made easier to read if vti.Wti.Vector and vti.Vti.Vector were defvard into variables. They're really eating up the columns.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

431

We also don’t need vti..Wti.Vector on every fma operand. Once it’s said for any operand or the result, tablegen can infer it for the other operands.

[jacquesguan]

Simplify tablegen class definations.

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

431

Done

[jacquesguan]

ping.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

multiclass VPatWidenBinaryFPSDNode_WV_WF<SDNode op, string instruction_name> {
   }
 }
 
 multiclass VPatWidenBinaryFPSDNode_VV_VF_WV_WF<SDNode op, string instruction_name> {
   defm : VPatWidenBinaryFPSDNode_VV_VF<op, instruction_name>;
   defm : VPatWidenBinaryFPSDNode_WV_WF<op, instruction_name>;
 }
 
+multiclass VPatWidenFPMulAccSDNode_VV_VF<string instruction_name> {
+  foreach vti = AllWidenableFloatVectors in {
+    def : Pat<(fma (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs1))),
+                   (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs2))),
+                   (vti.Wti.Vector vti.Wti.RegClass:$rd)),
+              (!cast<Instruction>(instruction_name#"_VV_"#vti.Vti.LMul.MX)
+                 vti.Wti.RegClass:$rd, vti.Vti.RegClass:$rs1, vti.Vti.RegClass:$rs2,
+                 vti.Vti.AVL, vti.Vti.Log2SEW, TAIL_AGNOSTIC)>;
+    def : Pat<(fma (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector (splat_vector vti.Vti.ScalarRegClass:$rs1)))),
+                   (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs2))),
+                   (vti.Wti.Vector vti.Wti.RegClass:$rd)),
+              (!cast<Instruction>(instruction_name#"_V"#vti.Vti.ScalarSuffix#"_"#vti.Vti.LMul.MX)
+                 vti.Wti.RegClass:$rd, vti.Vti.ScalarRegClass:$rs1, vti.Vti.RegClass:$rs2,
+                 vti.Vti.AVL, vti.Vti.Log2SEW, TAIL_AGNOSTIC)>;
+  }
+}
+
+multiclass VPatWidenFPNegMulAccSDNode_VV_VF<string instruction_name> {
+  foreach vtiToWti = AllWidenableFloatVectors in {
+    defvar vti = vtiToWti.Vti;
+    defvar wti = vtiToWti.Wti;
+    def : Pat<(fma (fneg (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1)))),
+                   (fpext_oneuse (vti.Vector vti.RegClass:$rs2)),
+                   (fneg wti.RegClass:$rd)),
+              (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
+                 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
+                 vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
+    def : Pat<(fma (fpext_oneuse (vti.Vector (splat_vector vti.ScalarRegClass:$rs1))),
+                   (fneg (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2)))),
+                   (fneg wti.RegClass:$rd)),
+              (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
+                 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
+                 vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
+    def : Pat<(fma (fneg (wti.Vector (fpext_oneuse (vti.Vector (splat_vector vti.ScalarRegClass:$rs1))))),
+                   (fpext_oneuse (vti.Vector vti.RegClass:$rs2)),
+                   (fneg wti.RegClass:$rd)),
+              (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
+                 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
+                 vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
+  }
+}
+
+multiclass VPatWidenFPMulSacSDNode_VV_VF<string instruction_name> {
+  foreach vtiToWti = AllWidenableFloatVectors in {
+    defvar vti = vtiToWti.Vti;
+    defvar wti = vtiToWti.Wti;
+    def : Pat<(fma (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1))),
+                   (fpext_oneuse (vti.Vector vti.RegClass:$rs2)),
+                   (fneg wti.RegClass:$rd)),
+              (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
+                 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
+                 vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
+    def : Pat<(fma (wti.Vector (fpext_oneuse (vti.Vector (splat_vector vti.ScalarRegClass:$rs1)))),
+                   (fpext_oneuse (vti.Vector vti.RegClass:$rs2)),
+                   (fneg wti.RegClass:$rd)),
+              (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
+                 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
+                 vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
+  }
+}
+
+multiclass VPatWidenFPNegMulSacSDNode_VV_VF<string instruction_name> {
+  foreach vtiToWti = AllWidenableFloatVectors in {
+    defvar vti = vtiToWti.Vti;
+    defvar wti = vtiToWti.Wti;
+    def : Pat<(fma (fneg (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1)))),
+                   (fpext_oneuse (vti.Vector vti.RegClass:$rs2)),
+                   wti.RegClass:$rd),
+              (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
+                 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
+                 vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
+    def : Pat<(fma (wti.Vector (fpext_oneuse (vti.Vector (splat_vector vti.ScalarRegClass:$rs1)))),
+                   (fneg (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2)))),
+                   wti.RegClass:$rd),
+              (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
+                 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
+                 vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
+    def : Pat<(fma (fneg (wti.Vector (fpext_oneuse (vti.Vector (splat_vector vti.ScalarRegClass:$rs1))))),
+                   (fpext_oneuse (vti.Vector vti.RegClass:$rs2)),
+                   wti.RegClass:$rd),
+              (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
+                 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
+                 vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Patterns.
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasVInstructions] in {
 
 // 7.4. Vector Unit-Stride Instructions
 foreach vti = !listconcat(FractionalGroupIntegerVectors,
def : Pat<(fvti.Vector (fma (fneg (splat_vector fvti.ScalarRegClass:$rs1)),
                  fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
   def : Pat<(fvti.Vector (fma (fneg (splat_vector fvti.ScalarRegClass:$rs1)),
                               fvti.RegClass:$rd, fvti.RegClass:$rs2)),
             (!cast<Instruction>("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix)
                  fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
                  fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
 }
 
+// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
+defm : VPatWidenFPMulAccSDNode_VV_VF<"PseudoVFWMACC">;
+defm : VPatWidenFPNegMulAccSDNode_VV_VF<"PseudoVFWNMACC">;
+defm : VPatWidenFPMulSacSDNode_VV_VF<"PseudoVFWMSAC">;
+defm : VPatWidenFPNegMulSacSDNode_VV_VF<"PseudoVFWNMSAC">;
+
 foreach vti = AllFloatVectors in {
   // 14.8. Vector Floating-Point Square-Root Instruction
   def : Pat<(fsqrt (vti.Vector vti.RegClass:$rs2)),
             (!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX)
                  vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>;
 
   // 14.12. Vector Floating-Point Sign-Injection Instructions
   def : Pat<(fabs (vti.Vector vti.RegClass:$rs)),

llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+v -target-abi=ilp32d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+v -target-abi=lp64d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+declare <vscale x 1 x float> @llvm.fma.v1f32(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>)
+
+define <vscale x 1 x float> @vfwmacc_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x half> %vb, <vscale x 1 x half> %vc) {
+; CHECK-LABEL: vfwmacc_vv_nxv1f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vfwmacc.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 1 x half> %vb to <vscale x 1 x float>
+  %ve = fpext <vscale x 1 x half> %vc to <vscale x 1 x float>
+  %vf = call <vscale x 1 x float> @llvm.fma.v1f32(<vscale x 1 x float> %vd, <vscale x 1 x float> %ve, <vscale x 1 x float> %va)
+  ret <vscale x 1 x float> %vf
+}
+
+define <vscale x 1 x float> @vfwmacc_vf_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmacc_vf_nxv1f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vfwmacc.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
+  %vd = fpext <vscale x 1 x half> %vb to <vscale x 1 x float>
+  %ve = fpext <vscale x 1 x half> %splat to <vscale x 1 x float>
+  %vf = call <vscale x 1 x float> @llvm.fma.v1f32(<vscale x 1 x float> %vd, <vscale x 1 x float> %ve, <vscale x 1 x float> %va)
+  ret <vscale x 1 x float> %vf
+}
+
+define <vscale x 1 x float> @vfwnmacc_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x half> %vb, <vscale x 1 x half> %vc) {
+; CHECK-LABEL: vfwnmacc_vv_nxv1f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vfwnmacc.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 1 x half> %vb to <vscale x 1 x float>
+  %ve = fpext <vscale x 1 x half> %vc to <vscale x 1 x float>
+  %vf = fneg <vscale x 1 x float> %va
+  %vg = fneg <vscale x 1 x float> %vd
+  %vh = call <vscale x 1 x float> @llvm.fma.v1f32(<vscale x 1 x float> %vg, <vscale x 1 x float> %ve, <vscale x 1 x float> %vf)
+  ret <vscale x 1 x float> %vh
+}
+
+define <vscale x 1 x float> @vfwnmacc_vf_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_vf_nxv1f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
+  %vd = fpext <vscale x 1 x half> %vb to <vscale x 1 x float>
+  %ve = fpext <vscale x 1 x half> %splat to <vscale x 1 x float>
+  %vf = fneg <vscale x 1 x float> %va
+  %vg = fneg <vscale x 1 x float> %vd
+  %vh = call <vscale x 1 x float> @llvm.fma.v1f32(<vscale x 1 x float> %vg, <vscale x 1 x float> %ve, <vscale x 1 x float> %vf)
+  ret <vscale x 1 x float> %vh
+}
+
+define <vscale x 1 x float> @vfwnmacc_fv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_fv_nxv1f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
+  %vd = fpext <vscale x 1 x half> %vb to <vscale x 1 x float>
+  %ve = fpext <vscale x 1 x half> %splat to <vscale x 1 x float>
+  %vf = fneg <vscale x 1 x float> %va
+  %vg = fneg <vscale x 1 x float> %ve
+  %vh = call <vscale x 1 x float> @llvm.fma.v1f32(<vscale x 1 x float> %vd, <vscale x 1 x float> %vg, <vscale x 1 x float> %vf)
+  ret <vscale x 1 x float> %vh
+}
+
+define <vscale x 1 x float> @vfwmsac_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x half> %vb, <vscale x 1 x half> %vc) {
+; CHECK-LABEL: vfwmsac_vv_nxv1f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vfwmsac.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 1 x half> %vb to <vscale x 1 x float>
+  %ve = fpext <vscale x 1 x half> %vc to <vscale x 1 x float>
+  %vf = fneg <vscale x 1 x float> %va
+  %vg = call <vscale x 1 x float> @llvm.fma.v1f32(<vscale x 1 x float> %vd, <vscale x 1 x float> %ve, <vscale x 1 x float> %vf)
+  ret <vscale x 1 x float> %vg
+}
+
+define <vscale x 1 x float> @vfwmsac_vf_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmsac_vf_nxv1f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vfwmsac.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
+  %vd = fpext <vscale x 1 x half> %vb to <vscale x 1 x float>
+  %ve = fpext <vscale x 1 x half> %splat to <vscale x 1 x float>
+  %vf = fneg <vscale x 1 x float> %va
+  %vg = call <vscale x 1 x float> @llvm.fma.v1f32(<vscale x 1 x float> %vd, <vscale x 1 x float> %ve, <vscale x 1 x float> %vf)
+  ret <vscale x 1 x float> %vg
+}
+
+define <vscale x 1 x float> @vfwnmsac_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x half> %vb, <vscale x 1 x half> %vc) {
+; CHECK-LABEL: vfwnmsac_vv_nxv1f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vfwnmsac.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 1 x half> %vb to <vscale x 1 x float>
+  %ve = fpext <vscale x 1 x half> %vc to <vscale x 1 x float>
+  %vf = fneg <vscale x 1 x float> %vd
+  %vg = call <vscale x 1 x float> @llvm.fma.v1f32(<vscale x 1 x float> %vf, <vscale x 1 x float> %ve, <vscale x 1 x float> %va)
+  ret <vscale x 1 x float> %vg
+}
+
+define <vscale x 1 x float> @vfwnmsac_vf_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_vf_nxv1f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
+  %vd = fpext <vscale x 1 x half> %vb to <vscale x 1 x float>
+  %ve = fpext <vscale x 1 x half> %splat to <vscale x 1 x float>
+  %vf = fneg <vscale x 1 x float> %vd
+  %vg = call <vscale x 1 x float> @llvm.fma.v1f32(<vscale x 1 x float> %vf, <vscale x 1 x float> %ve, <vscale x 1 x float> %va)
+  ret <vscale x 1 x float> %vg
+}
+
+define <vscale x 1 x float> @vfwnmsac_fv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_fv_nxv1f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
+  %vd = fpext <vscale x 1 x half> %vb to <vscale x 1 x float>
+  %ve = fpext <vscale x 1 x half> %splat to <vscale x 1 x float>
+  %vf = fneg <vscale x 1 x float> %ve
+  %vg = call <vscale x 1 x float> @llvm.fma.v1f32(<vscale x 1 x float> %vd, <vscale x 1 x float> %vf, <vscale x 1 x float> %va)
+  ret <vscale x 1 x float> %vg
+}
+
+declare <vscale x 2 x float> @llvm.fma.v2f32(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>)
+
+define <vscale x 2 x float> @vfwmacc_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x half> %vb, <vscale x 2 x half> %vc) {
+; CHECK-LABEL: vfwmacc_vv_nxv2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vfwmacc.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 2 x half> %vb to <vscale x 2 x float>
+  %ve = fpext <vscale x 2 x half> %vc to <vscale x 2 x float>
+  %vf = call <vscale x 2 x float> @llvm.fma.v2f32(<vscale x 2 x float> %vd, <vscale x 2 x float> %ve, <vscale x 2 x float> %va)
+  ret <vscale x 2 x float> %vf
+}
+
+define <vscale x 2 x float> @vfwmacc_vf_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmacc_vf_nxv2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vfwmacc.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
+  %vd = fpext <vscale x 2 x half> %vb to <vscale x 2 x float>
+  %ve = fpext <vscale x 2 x half> %splat to <vscale x 2 x float>
+  %vf = call <vscale x 2 x float> @llvm.fma.v2f32(<vscale x 2 x float> %vd, <vscale x 2 x float> %ve, <vscale x 2 x float> %va)
+  ret <vscale x 2 x float> %vf
+}
+
+define <vscale x 2 x float> @vfwnmacc_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x half> %vb, <vscale x 2 x half> %vc) {
+; CHECK-LABEL: vfwnmacc_vv_nxv2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vfwnmacc.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 2 x half> %vb to <vscale x 2 x float>
+  %ve = fpext <vscale x 2 x half> %vc to <vscale x 2 x float>
+  %vf = fneg <vscale x 2 x float> %va
+  %vg = fneg <vscale x 2 x float> %vd
+  %vh = call <vscale x 2 x float> @llvm.fma.v2f32(<vscale x 2 x float> %vg, <vscale x 2 x float> %ve, <vscale x 2 x float> %vf)
+  ret <vscale x 2 x float> %vh
+}
+
+define <vscale x 2 x float> @vfwnmacc_vf_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_vf_nxv2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
+  %vd = fpext <vscale x 2 x half> %vb to <vscale x 2 x float>
+  %ve = fpext <vscale x 2 x half> %splat to <vscale x 2 x float>
+  %vf = fneg <vscale x 2 x float> %va
+  %vg = fneg <vscale x 2 x float> %vd
+  %vh = call <vscale x 2 x float> @llvm.fma.v2f32(<vscale x 2 x float> %vg, <vscale x 2 x float> %ve, <vscale x 2 x float> %vf)
+  ret <vscale x 2 x float> %vh
+}
+
+define <vscale x 2 x float> @vfwnmacc_fv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_fv_nxv2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
+  %vd = fpext <vscale x 2 x half> %vb to <vscale x 2 x float>
+  %ve = fpext <vscale x 2 x half> %splat to <vscale x 2 x float>
+  %vf = fneg <vscale x 2 x float> %va
+  %vg = fneg <vscale x 2 x float> %ve
+  %vh = call <vscale x 2 x float> @llvm.fma.v2f32(<vscale x 2 x float> %vd, <vscale x 2 x float> %vg, <vscale x 2 x float> %vf)
+  ret <vscale x 2 x float> %vh
+}
+
+define <vscale x 2 x float> @vfwmsac_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x half> %vb, <vscale x 2 x half> %vc) {
+; CHECK-LABEL: vfwmsac_vv_nxv2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vfwmsac.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 2 x half> %vb to <vscale x 2 x float>
+  %ve = fpext <vscale x 2 x half> %vc to <vscale x 2 x float>
+  %vf = fneg <vscale x 2 x float> %va
+  %vg = call <vscale x 2 x float> @llvm.fma.v2f32(<vscale x 2 x float> %vd, <vscale x 2 x float> %ve, <vscale x 2 x float> %vf)
+  ret <vscale x 2 x float> %vg
+}
+
+define <vscale x 2 x float> @vfwmsac_vf_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmsac_vf_nxv2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vfwmsac.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
+  %vd = fpext <vscale x 2 x half> %vb to <vscale x 2 x float>
+  %ve = fpext <vscale x 2 x half> %splat to <vscale x 2 x float>
+  %vf = fneg <vscale x 2 x float> %va
+  %vg = call <vscale x 2 x float> @llvm.fma.v2f32(<vscale x 2 x float> %vd, <vscale x 2 x float> %ve, <vscale x 2 x float> %vf)
+  ret <vscale x 2 x float> %vg
+}
+
+define <vscale x 2 x float> @vfwnmsac_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x half> %vb, <vscale x 2 x half> %vc) {
+; CHECK-LABEL: vfwnmsac_vv_nxv2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vfwnmsac.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 2 x half> %vb to <vscale x 2 x float>
+  %ve = fpext <vscale x 2 x half> %vc to <vscale x 2 x float>
+  %vf = fneg <vscale x 2 x float> %vd
+  %vg = call <vscale x 2 x float> @llvm.fma.v2f32(<vscale x 2 x float> %vf, <vscale x 2 x float> %ve, <vscale x 2 x float> %va)
+  ret <vscale x 2 x float> %vg
+}
+
+define <vscale x 2 x float> @vfwnmsac_vf_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_vf_nxv2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
+  %vd = fpext <vscale x 2 x half> %vb to <vscale x 2 x float>
+  %ve = fpext <vscale x 2 x half> %splat to <vscale x 2 x float>
+  %vf = fneg <vscale x 2 x float> %vd
+  %vg = call <vscale x 2 x float> @llvm.fma.v2f32(<vscale x 2 x float> %vf, <vscale x 2 x float> %ve, <vscale x 2 x float> %va)
+  ret <vscale x 2 x float> %vg
+}
+
+define <vscale x 2 x float> @vfwnmsac_fv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_fv_nxv2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
+  %vd = fpext <vscale x 2 x half> %vb to <vscale x 2 x float>
+  %ve = fpext <vscale x 2 x half> %splat to <vscale x 2 x float>
+  %vf = fneg <vscale x 2 x float> %ve
+  %vg = call <vscale x 2 x float> @llvm.fma.v2f32(<vscale x 2 x float> %vd, <vscale x 2 x float> %vf, <vscale x 2 x float> %va)
+  ret <vscale x 2 x float> %vg
+}
+
+
+declare <vscale x 4 x float> @llvm.fma.v4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
+
+define <vscale x 4 x float> @vfwmacc_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x half> %vb, <vscale x 4 x half> %vc) {
+; CHECK-LABEL: vfwmacc_vv_nxv4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vfwmacc.vv v8, v10, v11
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 4 x half> %vb to <vscale x 4 x float>
+  %ve = fpext <vscale x 4 x half> %vc to <vscale x 4 x float>
+  %vf = call <vscale x 4 x float> @llvm.fma.v4f32(<vscale x 4 x float> %vd, <vscale x 4 x float> %ve, <vscale x 4 x float> %va)
+  ret <vscale x 4 x float> %vf
+}
+
+define <vscale x 4 x float> @vfwmacc_vf_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmacc_vf_nxv4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vfwmacc.vf v8, fa0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
+  %vd = fpext <vscale x 4 x half> %vb to <vscale x 4 x float>
+  %ve = fpext <vscale x 4 x half> %splat to <vscale x 4 x float>
+  %vf = call <vscale x 4 x float> @llvm.fma.v4f32(<vscale x 4 x float> %vd, <vscale x 4 x float> %ve, <vscale x 4 x float> %va)
+  ret <vscale x 4 x float> %vf
+}
+
+define <vscale x 4 x float> @vfwnmacc_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x half> %vb, <vscale x 4 x half> %vc) {
+; CHECK-LABEL: vfwnmacc_vv_nxv4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vfwnmacc.vv v8, v10, v11
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 4 x half> %vb to <vscale x 4 x float>
+  %ve = fpext <vscale x 4 x half> %vc to <vscale x 4 x float>
+  %vf = fneg <vscale x 4 x float> %va
+  %vg = fneg <vscale x 4 x float> %vd
+  %vh = call <vscale x 4 x float> @llvm.fma.v4f32(<vscale x 4 x float> %vg, <vscale x 4 x float> %ve, <vscale x 4 x float> %vf)
+  ret <vscale x 4 x float> %vh
+}
+
+define <vscale x 4 x float> @vfwnmacc_vf_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_vf_nxv4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
+  %vd = fpext <vscale x 4 x half> %vb to <vscale x 4 x float>
+  %ve = fpext <vscale x 4 x half> %splat to <vscale x 4 x float>
+  %vf = fneg <vscale x 4 x float> %va
+  %vg = fneg <vscale x 4 x float> %vd
+  %vh = call <vscale x 4 x float> @llvm.fma.v4f32(<vscale x 4 x float> %vg, <vscale x 4 x float> %ve, <vscale x 4 x float> %vf)
+  ret <vscale x 4 x float> %vh
+}
+
+define <vscale x 4 x float> @vfwnmacc_fv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_fv_nxv4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
+  %vd = fpext <vscale x 4 x half> %vb to <vscale x 4 x float>
+  %ve = fpext <vscale x 4 x half> %splat to <vscale x 4 x float>
+  %vf = fneg <vscale x 4 x float> %va
+  %vg = fneg <vscale x 4 x float> %ve
+  %vh = call <vscale x 4 x float> @llvm.fma.v4f32(<vscale x 4 x float> %vd, <vscale x 4 x float> %vg, <vscale x 4 x float> %vf)
+  ret <vscale x 4 x float> %vh
+}
+
+define <vscale x 4 x float> @vfwmsac_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x half> %vb, <vscale x 4 x half> %vc) {
+; CHECK-LABEL: vfwmsac_vv_nxv4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vfwmsac.vv v8, v10, v11
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 4 x half> %vb to <vscale x 4 x float>
+  %ve = fpext <vscale x 4 x half> %vc to <vscale x 4 x float>
+  %vf = fneg <vscale x 4 x float> %va
+  %vg = call <vscale x 4 x float> @llvm.fma.v4f32(<vscale x 4 x float> %vd, <vscale x 4 x float> %ve, <vscale x 4 x float> %vf)
+  ret <vscale x 4 x float> %vg
+}
+
+define <vscale x 4 x float> @vfwmsac_vf_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmsac_vf_nxv4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vfwmsac.vf v8, fa0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
+  %vd = fpext <vscale x 4 x half> %vb to <vscale x 4 x float>
+  %ve = fpext <vscale x 4 x half> %splat to <vscale x 4 x float>
+  %vf = fneg <vscale x 4 x float> %va
+  %vg = call <vscale x 4 x float> @llvm.fma.v4f32(<vscale x 4 x float> %vd, <vscale x 4 x float> %ve, <vscale x 4 x float> %vf)
+  ret <vscale x 4 x float> %vg
+}
+
+define <vscale x 4 x float> @vfwnmsac_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x half> %vb, <vscale x 4 x half> %vc) {
+; CHECK-LABEL: vfwnmsac_vv_nxv4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vfwnmsac.vv v8, v10, v11
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 4 x half> %vb to <vscale x 4 x float>
+  %ve = fpext <vscale x 4 x half> %vc to <vscale x 4 x float>
+  %vf = fneg <vscale x 4 x float> %vd
+  %vg = call <vscale x 4 x float> @llvm.fma.v4f32(<vscale x 4 x float> %vf, <vscale x 4 x float> %ve, <vscale x 4 x float> %va)
+  ret <vscale x 4 x float> %vg
+}
+
+define <vscale x 4 x float> @vfwnmsac_vf_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_vf_nxv4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
+  %vd = fpext <vscale x 4 x half> %vb to <vscale x 4 x float>
+  %ve = fpext <vscale x 4 x half> %splat to <vscale x 4 x float>
+  %vf = fneg <vscale x 4 x float> %vd
+  %vg = call <vscale x 4 x float> @llvm.fma.v4f32(<vscale x 4 x float> %vf, <vscale x 4 x float> %ve, <vscale x 4 x float> %va)
+  ret <vscale x 4 x float> %vg
+}
+
+define <vscale x 4 x float> @vfwnmsac_fv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_fv_nxv4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
+  %vd = fpext <vscale x 4 x half> %vb to <vscale x 4 x float>
+  %ve = fpext <vscale x 4 x half> %splat to <vscale x 4 x float>
+  %vf = fneg <vscale x 4 x float> %ve
+  %vg = call <vscale x 4 x float> @llvm.fma.v4f32(<vscale x 4 x float> %vd, <vscale x 4 x float> %vf, <vscale x 4 x float> %va)
+  ret <vscale x 4 x float> %vg
+}
+
+declare <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>)
+
+define <vscale x 8 x float> @vfwmacc_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x half> %vb, <vscale x 8 x half> %vc) {
+; CHECK-LABEL: vfwmacc_vv_nxv8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vfwmacc.vv v8, v12, v14
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 8 x half> %vb to <vscale x 8 x float>
+  %ve = fpext <vscale x 8 x half> %vc to <vscale x 8 x float>
+  %vf = call <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float> %vd, <vscale x 8 x float> %ve, <vscale x 8 x float> %va)
+  ret <vscale x 8 x float> %vf
+}
+
+define <vscale x 8 x float> @vfwmacc_vf_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmacc_vf_nxv8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vfwmacc.vf v8, fa0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %vd = fpext <vscale x 8 x half> %vb to <vscale x 8 x float>
+  %ve = fpext <vscale x 8 x half> %splat to <vscale x 8 x float>
+  %vf = call <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float> %vd, <vscale x 8 x float> %ve, <vscale x 8 x float> %va)
+  ret <vscale x 8 x float> %vf
+}
+
+define <vscale x 8 x float> @vfwnmacc_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x half> %vb, <vscale x 8 x half> %vc) {
+; CHECK-LABEL: vfwnmacc_vv_nxv8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vfwnmacc.vv v8, v12, v14
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 8 x half> %vb to <vscale x 8 x float>
+  %ve = fpext <vscale x 8 x half> %vc to <vscale x 8 x float>
+  %vf = fneg <vscale x 8 x float> %va
+  %vg = fneg <vscale x 8 x float> %vd
+  %vh = call <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float> %vg, <vscale x 8 x float> %ve, <vscale x 8 x float> %vf)
+  ret <vscale x 8 x float> %vh
+}
+
+define <vscale x 8 x float> @vfwnmacc_vf_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_vf_nxv8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %vd = fpext <vscale x 8 x half> %vb to <vscale x 8 x float>
+  %ve = fpext <vscale x 8 x half> %splat to <vscale x 8 x float>
+  %vf = fneg <vscale x 8 x float> %va
+  %vg = fneg <vscale x 8 x float> %vd
+  %vh = call <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float> %vg, <vscale x 8 x float> %ve, <vscale x 8 x float> %vf)
+  ret <vscale x 8 x float> %vh
+}
+
+define <vscale x 8 x float> @vfwnmacc_fv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_fv_nxv8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %vd = fpext <vscale x 8 x half> %vb to <vscale x 8 x float>
+  %ve = fpext <vscale x 8 x half> %splat to <vscale x 8 x float>
+  %vf = fneg <vscale x 8 x float> %va
+  %vg = fneg <vscale x 8 x float> %ve
+  %vh = call <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float> %vd, <vscale x 8 x float> %vg, <vscale x 8 x float> %vf)
+  ret <vscale x 8 x float> %vh
+}
+
+define <vscale x 8 x float> @vfwmsac_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x half> %vb, <vscale x 8 x half> %vc) {
+; CHECK-LABEL: vfwmsac_vv_nxv8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vfwmsac.vv v8, v12, v14
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 8 x half> %vb to <vscale x 8 x float>
+  %ve = fpext <vscale x 8 x half> %vc to <vscale x 8 x float>
+  %vf = fneg <vscale x 8 x float> %va
+  %vg = call <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float> %vd, <vscale x 8 x float> %ve, <vscale x 8 x float> %vf)
+  ret <vscale x 8 x float> %vg
+}
+
+define <vscale x 8 x float> @vfwmsac_vf_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmsac_vf_nxv8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vfwmsac.vf v8, fa0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %vd = fpext <vscale x 8 x half> %vb to <vscale x 8 x float>
+  %ve = fpext <vscale x 8 x half> %splat to <vscale x 8 x float>
+  %vf = fneg <vscale x 8 x float> %va
+  %vg = call <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float> %vd, <vscale x 8 x float> %ve, <vscale x 8 x float> %vf)
+  ret <vscale x 8 x float> %vg
+}
+
+define <vscale x 8 x float> @vfwnmsac_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x half> %vb, <vscale x 8 x half> %vc) {
+; CHECK-LABEL: vfwnmsac_vv_nxv8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vfwnmsac.vv v8, v12, v14
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 8 x half> %vb to <vscale x 8 x float>
+  %ve = fpext <vscale x 8 x half> %vc to <vscale x 8 x float>
+  %vf = fneg <vscale x 8 x float> %vd
+  %vg = call <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float> %vf, <vscale x 8 x float> %ve, <vscale x 8 x float> %va)
+  ret <vscale x 8 x float> %vg
+}
+
+define <vscale x 8 x float> @vfwnmsac_vf_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_vf_nxv8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %vd = fpext <vscale x 8 x half> %vb to <vscale x 8 x float>
+  %ve = fpext <vscale x 8 x half> %splat to <vscale x 8 x float>
+  %vf = fneg <vscale x 8 x float> %vd
+  %vg = call <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float> %vf, <vscale x 8 x float> %ve, <vscale x 8 x float> %va)
+  ret <vscale x 8 x float> %vg
+}
+
+define <vscale x 8 x float> @vfwnmsac_fv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_fv_nxv8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %vd = fpext <vscale x 8 x half> %vb to <vscale x 8 x float>
+  %ve = fpext <vscale x 8 x half> %splat to <vscale x 8 x float>
+  %vf = fneg <vscale x 8 x float> %ve
+  %vg = call <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float> %vd, <vscale x 8 x float> %vf, <vscale x 8 x float> %va)
+  ret <vscale x 8 x float> %vg
+}
+
+declare <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>)
+
+define <vscale x 16 x float> @vfwmacc_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x half> %vb, <vscale x 16 x half> %vc) {
+; CHECK-LABEL: vfwmacc_vv_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vfwmacc.vv v8, v16, v20
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 16 x half> %vb to <vscale x 16 x float>
+  %ve = fpext <vscale x 16 x half> %vc to <vscale x 16 x float>
+  %vf = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vd, <vscale x 16 x float> %ve, <vscale x 16 x float> %va)
+  ret <vscale x 16 x float> %vf
+}
+
+define <vscale x 16 x float> @vfwmacc_vf_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmacc_vf_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vfwmacc.vf v8, fa0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
+  %vd = fpext <vscale x 16 x half> %vb to <vscale x 16 x float>
+  %ve = fpext <vscale x 16 x half> %splat to <vscale x 16 x float>
+  %vf = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vd, <vscale x 16 x float> %ve, <vscale x 16 x float> %va)
+  ret <vscale x 16 x float> %vf
+}
+
+define <vscale x 16 x float> @vfwnmacc_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x half> %vb, <vscale x 16 x half> %vc) {
+; CHECK-LABEL: vfwnmacc_vv_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vfwnmacc.vv v8, v16, v20
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 16 x half> %vb to <vscale x 16 x float>
+  %ve = fpext <vscale x 16 x half> %vc to <vscale x 16 x float>
+  %vf = fneg <vscale x 16 x float> %va
+  %vg = fneg <vscale x 16 x float> %vd
+  %vh = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vg, <vscale x 16 x float> %ve, <vscale x 16 x float> %vf)
+  ret <vscale x 16 x float> %vh
+}
+
+define <vscale x 16 x float> @vfwnmacc_vf_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_vf_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
+  %vd = fpext <vscale x 16 x half> %vb to <vscale x 16 x float>
+  %ve = fpext <vscale x 16 x half> %splat to <vscale x 16 x float>
+  %vf = fneg <vscale x 16 x float> %va
+  %vg = fneg <vscale x 16 x float> %vd
+  %vh = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vg, <vscale x 16 x float> %ve, <vscale x 16 x float> %vf)
+  ret <vscale x 16 x float> %vh
+}
+
+define <vscale x 16 x float> @vfwnmacc_fv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_fv_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
+  %vd = fpext <vscale x 16 x half> %vb to <vscale x 16 x float>
+  %ve = fpext <vscale x 16 x half> %splat to <vscale x 16 x float>
+  %vf = fneg <vscale x 16 x float> %va
+  %vg = fneg <vscale x 16 x float> %ve
+  %vh = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vd, <vscale x 16 x float> %vg, <vscale x 16 x float> %vf)
+  ret <vscale x 16 x float> %vh
+}
+
+define <vscale x 16 x float> @vfwmsac_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x half> %vb, <vscale x 16 x half> %vc) {
+; CHECK-LABEL: vfwmsac_vv_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vfwmsac.vv v8, v16, v20
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 16 x half> %vb to <vscale x 16 x float>
+  %ve = fpext <vscale x 16 x half> %vc to <vscale x 16 x float>
+  %vf = fneg <vscale x 16 x float> %va
+  %vg = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vd, <vscale x 16 x float> %ve, <vscale x 16 x float> %vf)
+  ret <vscale x 16 x float> %vg
+}
+
+define <vscale x 16 x float> @vfwmsac_vf_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmsac_vf_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vfwmsac.vf v8, fa0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
+  %vd = fpext <vscale x 16 x half> %vb to <vscale x 16 x float>
+  %ve = fpext <vscale x 16 x half> %splat to <vscale x 16 x float>
+  %vf = fneg <vscale x 16 x float> %va
+  %vg = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vd, <vscale x 16 x float> %ve, <vscale x 16 x float> %vf)
+  ret <vscale x 16 x float> %vg
+}
+
+define <vscale x 16 x float> @vfwnmsac_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x half> %vb, <vscale x 16 x half> %vc) {
+; CHECK-LABEL: vfwnmsac_vv_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vfwnmsac.vv v8, v16, v20
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 16 x half> %vb to <vscale x 16 x float>
+  %ve = fpext <vscale x 16 x half> %vc to <vscale x 16 x float>
+  %vf = fneg <vscale x 16 x float> %vd
+  %vg = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vf, <vscale x 16 x float> %ve, <vscale x 16 x float> %va)
+  ret <vscale x 16 x float> %vg
+}
+
+define <vscale x 16 x float> @vfwnmsac_vf_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_vf_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
+  %vd = fpext <vscale x 16 x half> %vb to <vscale x 16 x float>
+  %ve = fpext <vscale x 16 x half> %splat to <vscale x 16 x float>
+  %vf = fneg <vscale x 16 x float> %vd
+  %vg = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vf, <vscale x 16 x float> %ve, <vscale x 16 x float> %va)
+  ret <vscale x 16 x float> %vg
+}
+
+define <vscale x 16 x float> @vfwnmsac_fv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_fv_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x half> undef, half %c, i32 0
+  %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
+  %vd = fpext <vscale x 16 x half> %vb to <vscale x 16 x float>
+  %ve = fpext <vscale x 16 x half> %splat to <vscale x 16 x float>
+  %vf = fneg <vscale x 16 x float> %ve
+  %vg = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vd, <vscale x 16 x float> %vf, <vscale x 16 x float> %va)
+  ret <vscale x 16 x float> %vg
+}
+
+declare <vscale x 1 x double> @llvm.fma.v1f64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>)
+
+define <vscale x 1 x double> @vfwmacc_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x float> %vb, <vscale x 1 x float> %vc) {
+; CHECK-LABEL: vfwmacc_vv_nxv1f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwmacc.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
+  %ve = fpext <vscale x 1 x float> %vc to <vscale x 1 x double>
+  %vf = call <vscale x 1 x double> @llvm.fma.v1f64(<vscale x 1 x double> %vd, <vscale x 1 x double> %ve, <vscale x 1 x double> %va)
+  ret <vscale x 1 x double> %vf
+}
+
+define <vscale x 1 x double> @vfwmacc_vf_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x float> %vb, float %c) {
+; CHECK-LABEL: vfwmacc_vf_nxv1f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwmacc.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
+  %vd = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
+  %ve = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
+  %vf = call <vscale x 1 x double> @llvm.fma.v1f64(<vscale x 1 x double> %vd, <vscale x 1 x double> %ve, <vscale x 1 x double> %va)
+  ret <vscale x 1 x double> %vf
+}
+
+define <vscale x 1 x double> @vfwnmacc_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x float> %vb, <vscale x 1 x float> %vc) {
+; CHECK-LABEL: vfwnmacc_vv_nxv1f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwnmacc.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
+  %ve = fpext <vscale x 1 x float> %vc to <vscale x 1 x double>
+  %vf = fneg <vscale x 1 x double> %va
+  %vg = fneg <vscale x 1 x double> %vd
+  %vh = call <vscale x 1 x double> @llvm.fma.v1f64(<vscale x 1 x double> %vg, <vscale x 1 x double> %ve, <vscale x 1 x double> %vf)
+  ret <vscale x 1 x double> %vh
+}
+
+define <vscale x 1 x double> @vfwnmacc_vf_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x float> %vb, float %c) {
+; CHECK-LABEL: vfwnmacc_vf_nxv1f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
+  %vd = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
+  %ve = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
+  %vf = fneg <vscale x 1 x double> %va
+  %vg = fneg <vscale x 1 x double> %vd
+  %vh = call <vscale x 1 x double> @llvm.fma.v1f64(<vscale x 1 x double> %vg, <vscale x 1 x double> %ve, <vscale x 1 x double> %vf)
+  ret <vscale x 1 x double> %vh
+}
+
+define <vscale x 1 x double> @vfwnmacc_fv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x float> %vb, float %c) {
+; CHECK-LABEL: vfwnmacc_fv_nxv1f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
+  %vd = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
+  %ve = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
+  %vf = fneg <vscale x 1 x double> %va
+  %vg = fneg <vscale x 1 x double> %ve
+  %vh = call <vscale x 1 x double> @llvm.fma.v1f64(<vscale x 1 x double> %vd, <vscale x 1 x double> %vg, <vscale x 1 x double> %vf)
+  ret <vscale x 1 x double> %vh
+}
+
+define <vscale x 1 x double> @vfwmsac_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x float> %vb, <vscale x 1 x float> %vc) {
+; CHECK-LABEL: vfwmsac_vv_nxv1f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwmsac.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
+  %ve = fpext <vscale x 1 x float> %vc to <vscale x 1 x double>
+  %vf = fneg <vscale x 1 x double> %va
+  %vg = call <vscale x 1 x double> @llvm.fma.v1f64(<vscale x 1 x double> %vd, <vscale x 1 x double> %ve, <vscale x 1 x double> %vf)
+  ret <vscale x 1 x double> %vg
+}
+
+define <vscale x 1 x double> @vfwmsac_vf_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x float> %vb, float %c) {
+; CHECK-LABEL: vfwmsac_vf_nxv1f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwmsac.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
+  %vd = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
+  %ve = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
+  %vf = fneg <vscale x 1 x double> %va
+  %vg = call <vscale x 1 x double> @llvm.fma.v1f64(<vscale x 1 x double> %vd, <vscale x 1 x double> %ve, <vscale x 1 x double> %vf)
+  ret <vscale x 1 x double> %vg
+}
+
+define <vscale x 1 x double> @vfwnmsac_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x float> %vb, <vscale x 1 x float> %vc) {
+; CHECK-LABEL: vfwnmsac_vv_nxv1f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwnmsac.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
+  %ve = fpext <vscale x 1 x float> %vc to <vscale x 1 x double>
+  %vf = fneg <vscale x 1 x double> %vd
+  %vg = call <vscale x 1 x double> @llvm.fma.v1f64(<vscale x 1 x double> %vf, <vscale x 1 x double> %ve, <vscale x 1 x double> %va)
+  ret <vscale x 1 x double> %vg
+}
+
+define <vscale x 1 x double> @vfwnmsac_vf_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x float> %vb, float %c) {
+; CHECK-LABEL: vfwnmsac_vf_nxv1f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
+  %vd = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
+  %ve = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
+  %vf = fneg <vscale x 1 x double> %vd
+  %vg = call <vscale x 1 x double> @llvm.fma.v1f64(<vscale x 1 x double> %vf, <vscale x 1 x double> %ve, <vscale x 1 x double> %va)
+  ret <vscale x 1 x double> %vg
+}
+
+define <vscale x 1 x double> @vfwnmsac_fv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x float> %vb, float %c) {
+; CHECK-LABEL: vfwnmsac_fv_nxv1f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v9
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
+  %vd = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
+  %ve = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
+  %vf = fneg <vscale x 1 x double> %ve
+  %vg = call <vscale x 1 x double> @llvm.fma.v1f64(<vscale x 1 x double> %vd, <vscale x 1 x double> %vf, <vscale x 1 x double> %va)
+  ret <vscale x 1 x double> %vg
+}
+
+declare <vscale x 2 x double> @llvm.fma.v2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)
+
+define <vscale x 2 x double> @vfwmacc_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x float> %vb, <vscale x 2 x float> %vc) {
+; CHECK-LABEL: vfwmacc_vv_nxv2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfwmacc.vv v8, v10, v11
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
+  %ve = fpext <vscale x 2 x float> %vc to <vscale x 2 x double>
+  %vf = call <vscale x 2 x double> @llvm.fma.v2f64(<vscale x 2 x double> %vd, <vscale x 2 x double> %ve, <vscale x 2 x double> %va)
+  ret <vscale x 2 x double> %vf
+}
+
+define <vscale x 2 x double> @vfwmacc_vf_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x float> %vb, float %c) {
+; CHECK-LABEL: vfwmacc_vf_nxv2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfwmacc.vf v8, fa0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
+  %vd = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
+  %ve = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
+  %vf = call <vscale x 2 x double> @llvm.fma.v2f64(<vscale x 2 x double> %vd, <vscale x 2 x double> %ve, <vscale x 2 x double> %va)
+  ret <vscale x 2 x double> %vf
+}
+
+define <vscale x 2 x double> @vfwnmacc_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x float> %vb, <vscale x 2 x float> %vc) {
+; CHECK-LABEL: vfwnmacc_vv_nxv2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfwnmacc.vv v8, v10, v11
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
+  %ve = fpext <vscale x 2 x float> %vc to <vscale x 2 x double>
+  %vf = fneg <vscale x 2 x double> %va
+  %vg = fneg <vscale x 2 x double> %vd
+  %vh = call <vscale x 2 x double> @llvm.fma.v2f64(<vscale x 2 x double> %vg, <vscale x 2 x double> %ve, <vscale x 2 x double> %vf)
+  ret <vscale x 2 x double> %vh
+}
+
+define <vscale x 2 x double> @vfwnmacc_vf_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x float> %vb, float %c) {
+; CHECK-LABEL: vfwnmacc_vf_nxv2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
+  %vd = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
+  %ve = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
+  %vf = fneg <vscale x 2 x double> %va
+  %vg = fneg <vscale x 2 x double> %vd
+  %vh = call <vscale x 2 x double> @llvm.fma.v2f64(<vscale x 2 x double> %vg, <vscale x 2 x double> %ve, <vscale x 2 x double> %vf)
+  ret <vscale x 2 x double> %vh
+}
+
+define <vscale x 2 x double> @vfwnmacc_fv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x float> %vb, float %c) {
+; CHECK-LABEL: vfwnmacc_fv_nxv2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
+  %vd = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
+  %ve = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
+  %vf = fneg <vscale x 2 x double> %va
+  %vg = fneg <vscale x 2 x double> %ve
+  %vh = call <vscale x 2 x double> @llvm.fma.v2f64(<vscale x 2 x double> %vd, <vscale x 2 x double> %vg, <vscale x 2 x double> %vf)
+  ret <vscale x 2 x double> %vh
+}
+
+define <vscale x 2 x double> @vfwmsac_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x float> %vb, <vscale x 2 x float> %vc) {
+; CHECK-LABEL: vfwmsac_vv_nxv2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfwmsac.vv v8, v10, v11
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
+  %ve = fpext <vscale x 2 x float> %vc to <vscale x 2 x double>
+  %vf = fneg <vscale x 2 x double> %va
+  %vg = call <vscale x 2 x double> @llvm.fma.v2f64(<vscale x 2 x double> %vd, <vscale x 2 x double> %ve, <vscale x 2 x double> %vf)
+  ret <vscale x 2 x double> %vg
+}
+
+define <vscale x 2 x double> @vfwmsac_vf_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x float> %vb, float %c) {
+; CHECK-LABEL: vfwmsac_vf_nxv2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfwmsac.vf v8, fa0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
+  %vd = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
+  %ve = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
+  %vf = fneg <vscale x 2 x double> %va
+  %vg = call <vscale x 2 x double> @llvm.fma.v2f64(<vscale x 2 x double> %vd, <vscale x 2 x double> %ve, <vscale x 2 x double> %vf)
+  ret <vscale x 2 x double> %vg
+}
+
+define <vscale x 2 x double> @vfwnmsac_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x float> %vb, <vscale x 2 x float> %vc) {
+; CHECK-LABEL: vfwnmsac_vv_nxv2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfwnmsac.vv v8, v10, v11
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
+  %ve = fpext <vscale x 2 x float> %vc to <vscale x 2 x double>
+  %vf = fneg <vscale x 2 x double> %vd
+  %vg = call <vscale x 2 x double> @llvm.fma.v2f64(<vscale x 2 x double> %vf, <vscale x 2 x double> %ve, <vscale x 2 x double> %va)
+  ret <vscale x 2 x double> %vg
+}
+
+define <vscale x 2 x double> @vfwnmsac_vf_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x float> %vb, float %c) {
+; CHECK-LABEL: vfwnmsac_vf_nxv2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
+  %vd = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
+  %ve = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
+  %vf = fneg <vscale x 2 x double> %vd
+  %vg = call <vscale x 2 x double> @llvm.fma.v2f64(<vscale x 2 x double> %vf, <vscale x 2 x double> %ve, <vscale x 2 x double> %va)
+  ret <vscale x 2 x double> %vg
+}
+
+define <vscale x 2 x double> @vfwnmsac_fv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x float> %vb, float %c) {
+; CHECK-LABEL: vfwnmsac_fv_nxv2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
+  %vd = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
+  %ve = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
+  %vf = fneg <vscale x 2 x double> %ve
+  %vg = call <vscale x 2 x double> @llvm.fma.v2f64(<vscale x 2 x double> %vd, <vscale x 2 x double> %vf, <vscale x 2 x double> %va)
+  ret <vscale x 2 x double> %vg
+}
+
+
+declare <vscale x 4 x double> @llvm.fma.v4f64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x double>)
+
+define <vscale x 4 x double> @vfwmacc_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x float> %vb, <vscale x 4 x float> %vc) {
+; CHECK-LABEL: vfwmacc_vv_nxv4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vfwmacc.vv v8, v12, v14
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
+  %ve = fpext <vscale x 4 x float> %vc to <vscale x 4 x double>
+  %vf = call <vscale x 4 x double> @llvm.fma.v4f64(<vscale x 4 x double> %vd, <vscale x 4 x double> %ve, <vscale x 4 x double> %va)
+  ret <vscale x 4 x double> %vf
+}
+
+define <vscale x 4 x double> @vfwmacc_vf_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x float> %vb, float %c) {
+; CHECK-LABEL: vfwmacc_vf_nxv4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vfwmacc.vf v8, fa0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %vd = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
+  %ve = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
+  %vf = call <vscale x 4 x double> @llvm.fma.v4f64(<vscale x 4 x double> %vd, <vscale x 4 x double> %ve, <vscale x 4 x double> %va)
+  ret <vscale x 4 x double> %vf
+}
+
+define <vscale x 4 x double> @vfwnmacc_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x float> %vb, <vscale x 4 x float> %vc) {
+; CHECK-LABEL: vfwnmacc_vv_nxv4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vfwnmacc.vv v8, v12, v14
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
+  %ve = fpext <vscale x 4 x float> %vc to <vscale x 4 x double>
+  %vf = fneg <vscale x 4 x double> %va
+  %vg = fneg <vscale x 4 x double> %vd
+  %vh = call <vscale x 4 x double> @llvm.fma.v4f64(<vscale x 4 x double> %vg, <vscale x 4 x double> %ve, <vscale x 4 x double> %vf)
+  ret <vscale x 4 x double> %vh
+}
+
+define <vscale x 4 x double> @vfwnmacc_vf_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x float> %vb, float %c) {
+; CHECK-LABEL: vfwnmacc_vf_nxv4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %vd = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
+  %ve = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
+  %vf = fneg <vscale x 4 x double> %va
+  %vg = fneg <vscale x 4 x double> %vd
+  %vh = call <vscale x 4 x double> @llvm.fma.v4f64(<vscale x 4 x double> %vg, <vscale x 4 x double> %ve, <vscale x 4 x double> %vf)
+  ret <vscale x 4 x double> %vh
+}
+
+define <vscale x 4 x double> @vfwnmacc_fv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x float> %vb, float %c) {
+; CHECK-LABEL: vfwnmacc_fv_nxv4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %vd = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
+  %ve = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
+  %vf = fneg <vscale x 4 x double> %va
+  %vg = fneg <vscale x 4 x double> %ve
+  %vh = call <vscale x 4 x double> @llvm.fma.v4f64(<vscale x 4 x double> %vd, <vscale x 4 x double> %vg, <vscale x 4 x double> %vf)
+  ret <vscale x 4 x double> %vh
+}
+
+define <vscale x 4 x double> @vfwmsac_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x float> %vb, <vscale x 4 x float> %vc) {
+; CHECK-LABEL: vfwmsac_vv_nxv4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vfwmsac.vv v8, v12, v14
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
+  %ve = fpext <vscale x 4 x float> %vc to <vscale x 4 x double>
+  %vf = fneg <vscale x 4 x double> %va
+  %vg = call <vscale x 4 x double> @llvm.fma.v4f64(<vscale x 4 x double> %vd, <vscale x 4 x double> %ve, <vscale x 4 x double> %vf)
+  ret <vscale x 4 x double> %vg
+}
+
+define <vscale x 4 x double> @vfwmsac_vf_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x float> %vb, float %c) {
+; CHECK-LABEL: vfwmsac_vf_nxv4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vfwmsac.vf v8, fa0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %vd = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
+  %ve = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
+  %vf = fneg <vscale x 4 x double> %va
+  %vg = call <vscale x 4 x double> @llvm.fma.v4f64(<vscale x 4 x double> %vd, <vscale x 4 x double> %ve, <vscale x 4 x double> %vf)
+  ret <vscale x 4 x double> %vg
+}
+
+define <vscale x 4 x double> @vfwnmsac_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x float> %vb, <vscale x 4 x float> %vc) {
+; CHECK-LABEL: vfwnmsac_vv_nxv4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vfwnmsac.vv v8, v12, v14
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
+  %ve = fpext <vscale x 4 x float> %vc to <vscale x 4 x double>
+  %vf = fneg <vscale x 4 x double> %vd
+  %vg = call <vscale x 4 x double> @llvm.fma.v4f64(<vscale x 4 x double> %vf, <vscale x 4 x double> %ve, <vscale x 4 x double> %va)
+  ret <vscale x 4 x double> %vg
+}
+
+define <vscale x 4 x double> @vfwnmsac_vf_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x float> %vb, float %c) {
+; CHECK-LABEL: vfwnmsac_vf_nxv4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %vd = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
+  %ve = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
+  %vf = fneg <vscale x 4 x double> %vd
+  %vg = call <vscale x 4 x double> @llvm.fma.v4f64(<vscale x 4 x double> %vf, <vscale x 4 x double> %ve, <vscale x 4 x double> %va)
+  ret <vscale x 4 x double> %vg
+}
+
+define <vscale x 4 x double> @vfwnmsac_fv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x float> %vb, float %c) {
+; CHECK-LABEL: vfwnmsac_fv_nxv4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %vd = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
+  %ve = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
+  %vf = fneg <vscale x 4 x double> %ve
+  %vg = call <vscale x 4 x double> @llvm.fma.v4f64(<vscale x 4 x double> %vd, <vscale x 4 x double> %vf, <vscale x 4 x double> %va)
+  ret <vscale x 4 x double> %vg
+}
+
+declare <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x double>)
+
+define <vscale x 8 x double> @vfwmacc_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x float> %vb, <vscale x 8 x float> %vc) {
+; CHECK-LABEL: vfwmacc_vv_nxv8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfwmacc.vv v8, v16, v20
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
+  %ve = fpext <vscale x 8 x float> %vc to <vscale x 8 x double>
+  %vf = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vd, <vscale x 8 x double> %ve, <vscale x 8 x double> %va)
+  ret <vscale x 8 x double> %vf
+}
+
+define <vscale x 8 x double> @vfwmacc_vf_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x float> %vb, float %c) {
+; CHECK-LABEL: vfwmacc_vf_nxv8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfwmacc.vf v8, fa0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
+  %vd = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
+  %ve = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
+  %vf = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vd, <vscale x 8 x double> %ve, <vscale x 8 x double> %va)
+  ret <vscale x 8 x double> %vf
+}
+
+define <vscale x 8 x double> @vfwnmacc_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x float> %vb, <vscale x 8 x float> %vc) {
+; CHECK-LABEL: vfwnmacc_vv_nxv8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfwnmacc.vv v8, v16, v20
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
+  %ve = fpext <vscale x 8 x float> %vc to <vscale x 8 x double>
+  %vf = fneg <vscale x 8 x double> %va
+  %vg = fneg <vscale x 8 x double> %vd
+  %vh = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vg, <vscale x 8 x double> %ve, <vscale x 8 x double> %vf)
+  ret <vscale x 8 x double> %vh
+}
+
+define <vscale x 8 x double> @vfwnmacc_vf_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x float> %vb, float %c) {
+; CHECK-LABEL: vfwnmacc_vf_nxv8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
+  %vd = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
+  %ve = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
+  %vf = fneg <vscale x 8 x double> %va
+  %vg = fneg <vscale x 8 x double> %vd
+  %vh = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vg, <vscale x 8 x double> %ve, <vscale x 8 x double> %vf)
+  ret <vscale x 8 x double> %vh
+}
+
+define <vscale x 8 x double> @vfwnmacc_fv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x float> %vb, float %c) {
+; CHECK-LABEL: vfwnmacc_fv_nxv8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
+  %vd = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
+  %ve = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
+  %vf = fneg <vscale x 8 x double> %va
+  %vg = fneg <vscale x 8 x double> %ve
+  %vh = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vd, <vscale x 8 x double> %vg, <vscale x 8 x double> %vf)
+  ret <vscale x 8 x double> %vh
+}
+
+define <vscale x 8 x double> @vfwmsac_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x float> %vb, <vscale x 8 x float> %vc) {
+; CHECK-LABEL: vfwmsac_vv_nxv8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfwmsac.vv v8, v16, v20
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
+  %ve = fpext <vscale x 8 x float> %vc to <vscale x 8 x double>
+  %vf = fneg <vscale x 8 x double> %va
+  %vg = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vd, <vscale x 8 x double> %ve, <vscale x 8 x double> %vf)
+  ret <vscale x 8 x double> %vg
+}
+
+define <vscale x 8 x double> @vfwmsac_vf_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x float> %vb, float %c) {
+; CHECK-LABEL: vfwmsac_vf_nxv8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfwmsac.vf v8, fa0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
+  %vd = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
+  %ve = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
+  %vf = fneg <vscale x 8 x double> %va
+  %vg = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vd, <vscale x 8 x double> %ve, <vscale x 8 x double> %vf)
+  ret <vscale x 8 x double> %vg
+}
+
+define <vscale x 8 x double> @vfwnmsac_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x float> %vb, <vscale x 8 x float> %vc) {
+; CHECK-LABEL: vfwnmsac_vv_nxv8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfwnmsac.vv v8, v16, v20
+; CHECK-NEXT:    ret
+  %vd = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
+  %ve = fpext <vscale x 8 x float> %vc to <vscale x 8 x double>
+  %vf = fneg <vscale x 8 x double> %vd
+  %vg = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vf, <vscale x 8 x double> %ve, <vscale x 8 x double> %va)
+  ret <vscale x 8 x double> %vg
+}
+
+define <vscale x 8 x double> @vfwnmsac_vf_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x float> %vb, float %c) {
+; CHECK-LABEL: vfwnmsac_vf_nxv8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
+  %vd = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
+  %ve = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
+  %vf = fneg <vscale x 8 x double> %vd
+  %vg = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vf, <vscale x 8 x double> %ve, <vscale x 8 x double> %va)
+  ret <vscale x 8 x double> %vg
+}
+
+define <vscale x 8 x double> @vfwnmsac_fv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x float> %vb, float %c) {
+; CHECK-LABEL: vfwnmsac_fv_nxv8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x float> undef, float %c, i32 0
+  %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
+  %vd = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
+  %ve = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
+  %vf = fneg <vscale x 8 x double> %ve
+  %vg = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vd, <vscale x 8 x double> %vf, <vscale x 8 x double> %va)
+  ret <vscale x 8 x double> %vg
+}