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Differential D117298

[CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.
ClosedPublic

Authored by foad on Jan 14 2022, 3:05 AM.

Details

Reviewers
jholewinski
nigelp-xmos
tstellar
t.p.northover
arsenm
Commits
rGf510045d820b: [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.
Summary

Take advantage of D117117 to simplify all {{\[}} to [ and {{\]}} to ].

Diff Detail

Event Timeline

foad created this revision.Jan 14 2022, 3:05 AM
Herald added subscribers: asavonic, wenlei, kerbowa and 7 others. · View Herald TranscriptJan 14 2022, 3:05 AM
foad requested review of this revision.Jan 14 2022, 3:05 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 14 2022, 3:05 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
foad added reviewers: jholewinski, nigelp-xmos, tstellar, t.p.northover, arsenm.Jan 14 2022, 3:07 AM
Herald added a subscriber: wdng. · View Herald TranscriptJan 14 2022, 3:07 AM
foad added a comment.Jan 14 2022, 3:10 AM

In case anyone needs to make equivalent changes downstream, this patch was created with: sed -i 's/{{\\\[}}/[/g;s/{{\\\]}}/]/g' $(grep -lr '{{\\[][]}}' test)

Harbormaster completed remote builds in B143354: Diff 399944.Jan 14 2022, 3:38 AM
nigelp-xmos added a comment.Jan 17 2022, 6:35 AM

XCore files LGTM. Nice improvement.

foad added a comment.Feb 18 2022, 7:59 AM

Ping!

arsenm accepted this revision.Feb 18 2022, 8:01 AM
This revision is now accepted and ready to land.Feb 18 2022, 8:01 AM
Closed by commit rGf510045d820b: [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. (authored by foad). · Explain WhyFeb 18 2022, 8:11 AM
This revision was automatically updated to reflect the committed changes.
foad added a commit: rGf510045d820b: [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC..
foad mentioned this in rG21843d96e055: [AMDGPU] Remove unneeded regex escaping in FileCheck patterns.May 23 2022, 4:10 AM
nigelp-xmos mentioned this in D132606: Fix CSR update check.Aug 24 2022, 2:55 PM

Revision Contents

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Diff 399944

llvm/test/CodeGen/AArch64/GlobalISel/swiftself.ll

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; We cannot pretend that 'x0' is alive across the thisreturn_attribute call as ; We cannot pretend that 'x0' is alive across the thisreturn_attribute call as
; we normally would. We marked the first parameter with swiftself which means it ; we normally would. We marked the first parameter with swiftself which means it
; will no longer be passed in x0. ; will no longer be passed in x0.
declare swiftcc i8* @thisreturn_attribute(i8* returned swiftself) declare swiftcc i8* @thisreturn_attribute(i8* returned swiftself)
; CHECK-LABEL: swiftself_nothisreturn: ; CHECK-LABEL: swiftself_nothisreturn:
; CHECK-DAG: ldr x20, [x20] ; CHECK-DAG: ldr x20, [x20]
; CHECK-DAG: mov [[CSREG:x[1-9].*]], x8 ; CHECK-DAG: mov [[CSREG:x[1-9].*]], x8
; CHECK: bl {{_?}}thisreturn_attribute ; CHECK: bl {{_?}}thisreturn_attribute
; CHECK: str x0, {{\[}}[[CSREG]] ; CHECK: str x0, [[[CSREG]]
; CHECK: ret ; CHECK: ret
define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture sret(i8*), i8** noalias nocapture readonly swiftself) { define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture sret(i8*), i8** noalias nocapture readonly swiftself) {
entry: entry:
%2 = load i8*, i8** %1, align 8 %2 = load i8*, i8** %1, align 8
%3 = tail call swiftcc i8* @thisreturn_attribute(i8* swiftself %2) %3 = tail call swiftcc i8* @thisreturn_attribute(i8* swiftself %2)
store i8* %3, i8** %0, align 8 store i8* %3, i8** %0, align 8
ret void ret void
} }
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llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll

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; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15> ; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
; CHECK: ret void ; CHECK: ret void
; AS-LABEL: aarch64_ilc_idx ; AS-LABEL: aarch64_ilc_idx
; AS-DAG: lsl [[LSL:x[0-9]+]], x1, #2 ; AS-DAG: lsl [[LSL:x[0-9]+]], x1, #2
; AS-DAG: add [[ADD:x[0-9]+]], [[LSL]], #64 ; AS-DAG: add [[ADD:x[0-9]+]], [[LSL]], #64
; AS-DAG: and [[AND:x[0-9]+]], [[ADD]], #0xfffffffffffffff0 ; AS-DAG: and [[AND:x[0-9]+]], [[ADD]], #0xfffffffffffffff0
; AS-DAG: add [[ADR:x[0-9]+]], x0, [[AND]] ; AS-DAG: add [[ADR:x[0-9]+]], x0, [[AND]]
; AS-DAG: ld4 { v[[V0:[0-9]+]].4s, v[[V1:[0-9]+]].4s, v[[V2:[0-9]+]].4s, v[[V3:[0-9]+]].4s }, {{\[}}[[ADR]]{{\]}} ; AS-DAG: ld4 { v[[V0:[0-9]+]].4s, v[[V1:[0-9]+]].4s, v[[V2:[0-9]+]].4s, v[[V3:[0-9]+]].4s }, [[[ADR]]]
; AS-DAG: str q[[V0]] ; AS-DAG: str q[[V0]]
; AS-DAG: str q[[V1]] ; AS-DAG: str q[[V1]]
; AS-DAG: str q[[V2]] ; AS-DAG: str q[[V2]]
; AS-DAG: str q[[V3]] ; AS-DAG: str q[[V3]]
; AS: ret ; AS: ret
%a2 = add i64 %idx, 20 %a2 = add i64 %idx, 20
%idx2 = lshr i64 %a2, 2 %idx2 = lshr i64 %a2, 2
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; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15> ; CHECK-DAG: %{{.* }}= shufflevector <16 x float> [[LOAD]], <16 x float> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
; CHECK: ret void ; CHECK: ret void
; AS-LABEL: aarch64_ilc_struct ; AS-LABEL: aarch64_ilc_struct
; AS-DAG: lsl [[LSL:x[0-9]+]], x1, #2 ; AS-DAG: lsl [[LSL:x[0-9]+]], x1, #2
; AS-DAG: add [[ADD:x[0-9]+]], x0, #4 ; AS-DAG: add [[ADD:x[0-9]+]], x0, #4
; AS-DAG: and [[AND:x[0-9]+]], [[LSL]], #0xfffffffffffffff0 ; AS-DAG: and [[AND:x[0-9]+]], [[LSL]], #0xfffffffffffffff0
; AS-DAG: add [[ADR:x[0-9]+]], [[ADD]], [[AND]] ; AS-DAG: add [[ADR:x[0-9]+]], [[ADD]], [[AND]]
; AS-DAG: ld4 { v[[V0:[0-9]+]].4s, v[[V1:[0-9]+]].4s, v[[V2:[0-9]+]].4s, v[[V3:[0-9]+]].4s }, {{\[}}[[ADR]]{{\]}} ; AS-DAG: ld4 { v[[V0:[0-9]+]].4s, v[[V1:[0-9]+]].4s, v[[V2:[0-9]+]].4s, v[[V3:[0-9]+]].4s }, [[[ADR]]]
; AS-DAG: str q[[V0]] ; AS-DAG: str q[[V0]]
; AS-DAG: str q[[V1]] ; AS-DAG: str q[[V1]]
; AS-DAG: str q[[V2]] ; AS-DAG: str q[[V2]]
; AS-DAG: str q[[V3]] ; AS-DAG: str q[[V3]]
; AS: ret ; AS: ret
%a1 = add i64 %idx, 4 %a1 = add i64 %idx, 4
%idx2 = lshr i64 %a1, 2 %idx2 = lshr i64 %a1, 2
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llvm/test/CodeGen/AArch64/arm64-abi_align.ll

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; "i64 %0" should be in register x7. ; "i64 %0" should be in register x7.
; "i32 8" should be on stack at [sp]. ; "i32 8" should be on stack at [sp].
; CHECK: ldr x7, [{{x[0-9]+}}] ; CHECK: ldr x7, [{{x[0-9]+}}]
; CHECK: str {{w[0-9]+}}, [sp] ; CHECK: str {{w[0-9]+}}, [sp]
; FAST-LABEL: i64_split ; FAST-LABEL: i64_split
; FAST: ldr x7, [{{x[0-9]+}}] ; FAST: ldr x7, [{{x[0-9]+}}]
; FAST: mov x[[R0:[0-9]+]], sp ; FAST: mov x[[R0:[0-9]+]], sp
; FAST: mov w[[R1:[0-9]+]], #8 ; FAST: mov w[[R1:[0-9]+]], #8
; FAST: str w[[R1]], {{\[}}x[[R0]]{{\]}} ; FAST: str w[[R1]], [x[[R0]]]
%0 = load i64, i64* bitcast (%struct.s41* @g41 to i64*), align 16 %0 = load i64, i64* bitcast (%struct.s41* @g41 to i64*), align 16
%call = tail call i32 @callee_i64(i32 1, i32 2, i32 3, i32 4, i32 5, %call = tail call i32 @callee_i64(i32 1, i32 2, i32 3, i32 4, i32 5,
i32 6, i32 7, i64 %0, i32 8) #5 i32 6, i32 7, i64 %0, i32 8) #5
ret i32 %call ret i32 %call
} }
attributes #0 = { noinline nounwind readnone "fp-contract-model"="standard" "relocation-model"="pic" "ssp-buffers-size"="8" } attributes #0 = { noinline nounwind readnone "fp-contract-model"="standard" "relocation-model"="pic" "ssp-buffers-size"="8" }
attributes #1 = { nounwind readonly "fp-contract-model"="standard" "relocation-model"="pic" "ssp-buffers-size"="8" } attributes #1 = { nounwind readonly "fp-contract-model"="standard" "relocation-model"="pic" "ssp-buffers-size"="8" }
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llvm/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll

; RUN: llc < %s -mtriple=arm64-apple-darwin -enable-misched=false -enable-post-misched=false | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-darwin -enable-misched=false -enable-post-misched=false | FileCheck %s
; rdar://12713765 ; rdar://12713765
; Make sure we are not creating stack objects that are assumed to be 64-byte ; Make sure we are not creating stack objects that are assumed to be 64-byte
; aligned. ; aligned.
@T3_retval = common global <16 x float> zeroinitializer, align 16 @T3_retval = common global <16 x float> zeroinitializer, align 16
define void @test(<16 x float>* noalias sret(<16 x float>) %agg.result) nounwind ssp { define void @test(<16 x float>* noalias sret(<16 x float>) %agg.result) nounwind ssp {
entry: entry:
; CHECK: test ; CHECK: test
; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [sp, #32] ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [sp, #32]
; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [sp] ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [sp]
; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], {{\[}}[[BASE:x[0-9]+]], #32] ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [[[BASE:x[0-9]+]], #32]
; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], {{\[}}[[BASE]]] ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [[[BASE]]]
%retval = alloca <16 x float>, align 16 %retval = alloca <16 x float>, align 16
%0 = load <16 x float>, <16 x float>* @T3_retval, align 16 %0 = load <16 x float>, <16 x float>* @T3_retval, align 16
store <16 x float> %0, <16 x float>* %retval store <16 x float> %0, <16 x float>* %retval
%1 = load <16 x float>, <16 x float>* %retval %1 = load <16 x float>, <16 x float>* %retval
store <16 x float> %1, <16 x float>* %agg.result, align 16 store <16 x float> %1, <16 x float>* %agg.result, align 16
ret void ret void
} }

llvm/test/CodeGen/AArch64/arm64-code-model-large-darwin.ll

; Check that AArch64 is honoring code-model=large at -O0 and -O2. ; Check that AArch64 is honoring code-model=large at -O0 and -O2.
; ;
; RUN: llc -mtriple=arm64-apple-darwin19 -code-model=large -O0 -o - %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-darwin19 -code-model=large -O0 -o - %s | FileCheck %s
; RUN: llc -mtriple=arm64-apple-darwin19 -code-model=large -O2 -o - %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-darwin19 -code-model=large -O2 -o - %s | FileCheck %s
; CHECK: adrp [[REG1:x[0-9]+]], _bar@GOTPAGE ; CHECK: adrp [[REG1:x[0-9]+]], _bar@GOTPAGE
; CHECK: ldr [[REG1]], {{\[}}[[REG1]], _bar@GOTPAGEOFF] ; CHECK: ldr [[REG1]], [[[REG1]], _bar@GOTPAGEOFF]
; CHECK: blr [[REG1]] ; CHECK: blr [[REG1]]
declare void @bar() declare void @bar()
define void @foo() { define void @foo() {
call void @bar() call void @bar()
ret void ret void
} }

llvm/test/CodeGen/AArch64/arm64-collect-loh.ll

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@C = common global i32 0, align 4 @C = common global i32 0, align 4
; Check that we catch AdrpLdrGotLdr case when we have a simple chain: ; Check that we catch AdrpLdrGotLdr case when we have a simple chain:
; adrp -> ldrgot -> ldr. ; adrp -> ldrgot -> ldr.
; CHECK-LABEL: _getC ; CHECK-LABEL: _getC
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _C@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _C@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _C@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _C@GOTPAGEOFF]
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr w0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: ldr w0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]]
define i32 @getC() { define i32 @getC() {
%res = load i32, i32* @C, align 4 %res = load i32, i32* @C, align 4
ret i32 %res ret i32 %res
} }
; LDRSW supports loading from a literal. ; LDRSW supports loading from a literal.
; Make sure we emit AdrpLdrGotLdr for those. ; Make sure we emit AdrpLdrGotLdr for those.
; CHECK-LABEL: _getSExtC ; CHECK-LABEL: _getSExtC
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _C@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _C@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _C@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _C@GOTPAGEOFF]
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldrsw x0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: ldrsw x0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]]
define i64 @getSExtC() { define i64 @getSExtC() {
%res = load i32, i32* @C, align 4 %res = load i32, i32* @C, align 4
%sextres = sext i32 %res to i64 %sextres = sext i32 %res to i64
ret i64 %sextres ret i64 %sextres
} }
; It may not be safe to fold the literal in the load if the address is ; It may not be safe to fold the literal in the load if the address is
; used several times. ; used several times.
; Make sure we emit AdrpLdrGot for those. ; Make sure we emit AdrpLdrGot for those.
; CHECK-LABEL: _getSeveralC ; CHECK-LABEL: _getSeveralC
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _C@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _C@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _C@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _C@GOTPAGEOFF]
; CHECK-NEXT: ldr [[LOAD:w[0-9]+]], [x[[LDRGOT_REG]]] ; CHECK-NEXT: ldr [[LOAD:w[0-9]+]], [x[[LDRGOT_REG]]]
; CHECK-NEXT: add [[ADD:w[0-9]+]], [[LOAD]], w0 ; CHECK-NEXT: add [[ADD:w[0-9]+]], [[LOAD]], w0
; CHECK-NEXT: str [[ADD]], [x[[LDRGOT_REG]]] ; CHECK-NEXT: str [[ADD]], [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGot [[ADRP_LABEL]], [[LDRGOT_LABEL]] ; CHECK: .loh AdrpLdrGot [[ADRP_LABEL]], [[LDRGOT_LABEL]]
define void @getSeveralC(i32 %t) { define void @getSeveralC(i32 %t) {
entry: entry:
%tmp = load i32, i32* @C, align 4 %tmp = load i32, i32* @C, align 4
%add = add nsw i32 %tmp, %t %add = add nsw i32 %tmp, %t
store i32 %add, i32* @C, align 4 store i32 %add, i32* @C, align 4
ret void ret void
} }
; Make sure we catch that: ; Make sure we catch that:
; adrp -> ldrgot -> str. ; adrp -> ldrgot -> str.
; CHECK-LABEL: _setC ; CHECK-LABEL: _setC
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _C@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _C@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _C@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _C@GOTPAGEOFF]
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: str w0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: str w0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]]
define void @setC(i32 %t) { define void @setC(i32 %t) {
entry: entry:
store i32 %t, i32* @C, align 4 store i32 %t, i32* @C, align 4
ret void ret void
} }
; Perform the same tests for internal global and a displacement ; Perform the same tests for internal global and a displacement
; in the addressing mode. ; in the addressing mode.
; Indeed we will get an ADD for those instead of LOADGot. ; Indeed we will get an ADD for those instead of LOADGot.
@InternalC = internal global i32 0, align 4 @InternalC = internal global i32 0, align 4
; Check that we catch AdrpAddLdr case when we have a simple chain: ; Check that we catch AdrpAddLdr case when we have a simple chain:
; adrp -> add -> ldr. ; adrp -> add -> ldr.
; CHECK-LABEL: _getInternalCPlus4 ; CHECK-LABEL: _getInternalCPlus4
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _InternalC@PAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _InternalC@PAGE
; CHECK-NEXT: [[ADDGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[ADDGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: add [[ADDGOT_REG:x[0-9]+]], [[ADRP_REG]], _InternalC@PAGEOFF ; CHECK-NEXT: add [[ADDGOT_REG:x[0-9]+]], [[ADRP_REG]], _InternalC@PAGEOFF
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr w0, {{\[}}[[ADDGOT_REG]], #16] ; CHECK-NEXT: ldr w0, [[[ADDGOT_REG]], #16]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpAddLdr [[ADRP_LABEL]], [[ADDGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpAddLdr [[ADRP_LABEL]], [[ADDGOT_LABEL]], [[LDR_LABEL]]
define i32 @getInternalCPlus4() { define i32 @getInternalCPlus4() {
%addr = getelementptr inbounds i32, i32* @InternalC, i32 4 %addr = getelementptr inbounds i32, i32* @InternalC, i32 4
%res = load i32, i32* %addr, align 4 %res = load i32, i32* %addr, align 4
ret i32 %res ret i32 %res
} }
; LDRSW supports loading from a literal. ; LDRSW supports loading from a literal.
; Make sure we emit AdrpLdrGotLdr for those. ; Make sure we emit AdrpLdrGotLdr for those.
; CHECK-LABEL: _getSExtInternalCPlus4 ; CHECK-LABEL: _getSExtInternalCPlus4
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _InternalC@PAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _InternalC@PAGE
; CHECK-NEXT: [[ADDGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[ADDGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: add [[ADDGOT_REG:x[0-9]+]], [[ADRP_REG]], _InternalC@PAGEOFF ; CHECK-NEXT: add [[ADDGOT_REG:x[0-9]+]], [[ADRP_REG]], _InternalC@PAGEOFF
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldrsw x0, {{\[}}[[ADDGOT_REG]], #16] ; CHECK-NEXT: ldrsw x0, [[[ADDGOT_REG]], #16]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpAddLdr [[ADRP_LABEL]], [[ADDGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpAddLdr [[ADRP_LABEL]], [[ADDGOT_LABEL]], [[LDR_LABEL]]
define i64 @getSExtInternalCPlus4() { define i64 @getSExtInternalCPlus4() {
%addr = getelementptr inbounds i32, i32* @InternalC, i32 4 %addr = getelementptr inbounds i32, i32* @InternalC, i32 4
%res = load i32, i32* %addr, align 4 %res = load i32, i32* %addr, align 4
%sextres = sext i32 %res to i64 %sextres = sext i32 %res to i64
ret i64 %sextres ret i64 %sextres
} }
; It may not be safe to fold the literal in the load if the address is ; It may not be safe to fold the literal in the load if the address is
; used several times. ; used several times.
; Make sure we emit AdrpAdd for those. ; Make sure we emit AdrpAdd for those.
; CHECK-LABEL: _getSeveralInternalCPlus4 ; CHECK-LABEL: _getSeveralInternalCPlus4
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _InternalC@PAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _InternalC@PAGE
; CHECK-NEXT: [[ADDGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[ADDGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: add [[ADDGOT_REG:x[0-9]+]], [[ADRP_REG]], _InternalC@PAGEOFF ; CHECK-NEXT: add [[ADDGOT_REG:x[0-9]+]], [[ADRP_REG]], _InternalC@PAGEOFF
; CHECK-NEXT: ldr [[LOAD:w[0-9]+]], {{\[}}[[ADDGOT_REG]], #16] ; CHECK-NEXT: ldr [[LOAD:w[0-9]+]], [[[ADDGOT_REG]], #16]
; CHECK-NEXT: add [[ADD:w[0-9]+]], [[LOAD]], w0 ; CHECK-NEXT: add [[ADD:w[0-9]+]], [[LOAD]], w0
; CHECK-NEXT: str [[ADD]], {{\[}}[[ADDGOT_REG]], #16] ; CHECK-NEXT: str [[ADD]], [[[ADDGOT_REG]], #16]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpAdd [[ADRP_LABEL]], [[ADDGOT_LABEL]] ; CHECK: .loh AdrpAdd [[ADRP_LABEL]], [[ADDGOT_LABEL]]
define void @getSeveralInternalCPlus4(i32 %t) { define void @getSeveralInternalCPlus4(i32 %t) {
entry: entry:
%addr = getelementptr inbounds i32, i32* @InternalC, i32 4 %addr = getelementptr inbounds i32, i32* @InternalC, i32 4
%tmp = load i32, i32* %addr, align 4 %tmp = load i32, i32* %addr, align 4
%add = add nsw i32 %tmp, %t %add = add nsw i32 %tmp, %t
store i32 %add, i32* %addr, align 4 store i32 %add, i32* %addr, align 4
ret void ret void
} }
; Make sure we catch that: ; Make sure we catch that:
; adrp -> add -> str. ; adrp -> add -> str.
; CHECK-LABEL: _setInternalCPlus4 ; CHECK-LABEL: _setInternalCPlus4
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _InternalC@PAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _InternalC@PAGE
; CHECK-NEXT: [[ADDGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[ADDGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: add [[ADDGOT_REG:x[0-9]+]], [[ADRP_REG]], _InternalC@PAGEOFF ; CHECK-NEXT: add [[ADDGOT_REG:x[0-9]+]], [[ADRP_REG]], _InternalC@PAGEOFF
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: str w0, {{\[}}[[ADDGOT_REG]], #16] ; CHECK-NEXT: str w0, [[[ADDGOT_REG]], #16]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpAddStr [[ADRP_LABEL]], [[ADDGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpAddStr [[ADRP_LABEL]], [[ADDGOT_LABEL]], [[LDR_LABEL]]
define void @setInternalCPlus4(i32 %t) { define void @setInternalCPlus4(i32 %t) {
entry: entry:
%addr = getelementptr inbounds i32, i32* @InternalC, i32 4 %addr = getelementptr inbounds i32, i32* @InternalC, i32 4
store i32 %t, i32* %addr, align 4 store i32 %t, i32* %addr, align 4
ret void ret void
} }
; Check that we catch AdrpAddLdr case when we have a simple chain: ; Check that we catch AdrpAddLdr case when we have a simple chain:
; adrp -> ldr. ; adrp -> ldr.
; CHECK-LABEL: _getInternalC ; CHECK-LABEL: _getInternalC
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _InternalC@PAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _InternalC@PAGE
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr w0, {{\[}}[[ADRP_REG]], _InternalC@PAGEOFF] ; CHECK-NEXT: ldr w0, [[[ADRP_REG]], _InternalC@PAGEOFF]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdr [[ADRP_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpLdr [[ADRP_LABEL]], [[LDR_LABEL]]
define i32 @getInternalC() { define i32 @getInternalC() {
%res = load i32, i32* @InternalC, align 4 %res = load i32, i32* @InternalC, align 4
ret i32 %res ret i32 %res
} }
; LDRSW supports loading from a literal. ; LDRSW supports loading from a literal.
; Make sure we emit AdrpLdrGotLdr for those. ; Make sure we emit AdrpLdrGotLdr for those.
; CHECK-LABEL: _getSExtInternalC ; CHECK-LABEL: _getSExtInternalC
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _InternalC@PAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _InternalC@PAGE
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldrsw x0, {{\[}}[[ADRP_REG]], _InternalC@PAGEOFF] ; CHECK-NEXT: ldrsw x0, [[[ADRP_REG]], _InternalC@PAGEOFF]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdr [[ADRP_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpLdr [[ADRP_LABEL]], [[LDR_LABEL]]
define i64 @getSExtInternalC() { define i64 @getSExtInternalC() {
%res = load i32, i32* @InternalC, align 4 %res = load i32, i32* @InternalC, align 4
%sextres = sext i32 %res to i64 %sextres = sext i32 %res to i64
ret i64 %sextres ret i64 %sextres
} }
; It may not be safe to fold the literal in the load if the address is ; It may not be safe to fold the literal in the load if the address is
; used several times. ; used several times.
; Make sure we do not catch anything here. We have a adrp alone, ; Make sure we do not catch anything here. We have a adrp alone,
; there is not much we can do about it. ; there is not much we can do about it.
; CHECK-LABEL: _getSeveralInternalC ; CHECK-LABEL: _getSeveralInternalC
; CHECK: adrp [[ADRP_REG:x[0-9]+]], _InternalC@PAGE ; CHECK: adrp [[ADRP_REG:x[0-9]+]], _InternalC@PAGE
; CHECK-NEXT: ldr [[LOAD:w[0-9]+]], {{\[}}[[ADRP_REG]], _InternalC@PAGEOFF] ; CHECK-NEXT: ldr [[LOAD:w[0-9]+]], [[[ADRP_REG]], _InternalC@PAGEOFF]
; CHECK-NEXT: add [[ADD:w[0-9]+]], [[LOAD]], w0 ; CHECK-NEXT: add [[ADD:w[0-9]+]], [[LOAD]], w0
; CHECK-NEXT: str [[ADD]], {{\[}}[[ADRP_REG]], _InternalC@PAGEOFF] ; CHECK-NEXT: str [[ADD]], [[[ADRP_REG]], _InternalC@PAGEOFF]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @getSeveralInternalC(i32 %t) { define void @getSeveralInternalC(i32 %t) {
entry: entry:
%tmp = load i32, i32* @InternalC, align 4 %tmp = load i32, i32* @InternalC, align 4
%add = add nsw i32 %tmp, %t %add = add nsw i32 %tmp, %t
store i32 %add, i32* @InternalC, align 4 store i32 %add, i32* @InternalC, align 4
ret void ret void
} }
; Make sure we do not catch anything when: ; Make sure we do not catch anything when:
; adrp -> str. ; adrp -> str.
; We cannot fold anything in the str at this point. ; We cannot fold anything in the str at this point.
; Indeed, strs do not support litterals. ; Indeed, strs do not support litterals.
; CHECK-LABEL: _setInternalC ; CHECK-LABEL: _setInternalC
; CHECK: adrp [[ADRP_REG:x[0-9]+]], _InternalC@PAGE ; CHECK: adrp [[ADRP_REG:x[0-9]+]], _InternalC@PAGE
; CHECK-NEXT: str w0, {{\[}}[[ADRP_REG]], _InternalC@PAGEOFF] ; CHECK-NEXT: str w0, [[[ADRP_REG]], _InternalC@PAGEOFF]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @setInternalC(i32 %t) { define void @setInternalC(i32 %t) {
entry: entry:
store i32 %t, i32* @InternalC, align 4 store i32 %t, i32* @InternalC, align 4
ret void ret void
} }
; Now check other variant of loads/stores. ; Now check other variant of loads/stores.
@D = common global i8 0, align 4 @D = common global i8 0, align 4
; LDRB does not support loading from a literal. ; LDRB does not support loading from a literal.
; Make sure we emit AdrpLdrGot and not AdrpLdrGotLdr for those. ; Make sure we emit AdrpLdrGot and not AdrpLdrGotLdr for those.
; CHECK-LABEL: _getD ; CHECK-LABEL: _getD
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _D@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _D@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _D@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _D@GOTPAGEOFF]
; CHECK-NEXT: ldrb w0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: ldrb w0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGot [[ADRP_LABEL]], [[LDRGOT_LABEL]] ; CHECK: .loh AdrpLdrGot [[ADRP_LABEL]], [[LDRGOT_LABEL]]
define i8 @getD() { define i8 @getD() {
%res = load i8, i8* @D, align 4 %res = load i8, i8* @D, align 4
ret i8 %res ret i8 %res
} }
; CHECK-LABEL: _setD ; CHECK-LABEL: _setD
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _D@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _D@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _D@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _D@GOTPAGEOFF]
; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: strb w0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: strb w0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]] ; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]]
define void @setD(i8 %t) { define void @setD(i8 %t) {
store i8 %t, i8* @D, align 4 store i8 %t, i8* @D, align 4
ret void ret void
} }
; LDRSB supports loading from a literal. ; LDRSB supports loading from a literal.
; Make sure we emit AdrpLdrGotLdr for those. ; Make sure we emit AdrpLdrGotLdr for those.
; CHECK-LABEL: _getSExtD ; CHECK-LABEL: _getSExtD
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _D@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _D@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _D@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _D@GOTPAGEOFF]
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldrsb w0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: ldrsb w0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]]
define i32 @getSExtD() { define i32 @getSExtD() {
%res = load i8, i8* @D, align 4 %res = load i8, i8* @D, align 4
%sextres = sext i8 %res to i32 %sextres = sext i8 %res to i32
ret i32 %sextres ret i32 %sextres
} }
; LDRSB supports loading from a literal. ; LDRSB supports loading from a literal.
; Make sure we emit AdrpLdrGotLdr for those. ; Make sure we emit AdrpLdrGotLdr for those.
; CHECK-LABEL: _getSExt64D ; CHECK-LABEL: _getSExt64D
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _D@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _D@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _D@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _D@GOTPAGEOFF]
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldrsb x0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: ldrsb x0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]]
define i64 @getSExt64D() { define i64 @getSExt64D() {
%res = load i8, i8* @D, align 4 %res = load i8, i8* @D, align 4
%sextres = sext i8 %res to i64 %sextres = sext i8 %res to i64
ret i64 %sextres ret i64 %sextres
} }
@E = common global i16 0, align 4 @E = common global i16 0, align 4
; LDRH does not support loading from a literal. ; LDRH does not support loading from a literal.
; Make sure we emit AdrpLdrGot and not AdrpLdrGotLdr for those. ; Make sure we emit AdrpLdrGot and not AdrpLdrGotLdr for those.
; CHECK-LABEL: _getE ; CHECK-LABEL: _getE
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _E@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _E@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _E@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _E@GOTPAGEOFF]
; CHECK-NEXT: ldrh w0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: ldrh w0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGot [[ADRP_LABEL]], [[LDRGOT_LABEL]] ; CHECK: .loh AdrpLdrGot [[ADRP_LABEL]], [[LDRGOT_LABEL]]
define i16 @getE() { define i16 @getE() {
%res = load i16, i16* @E, align 4 %res = load i16, i16* @E, align 4
ret i16 %res ret i16 %res
} }
; LDRSH supports loading from a literal. ; LDRSH supports loading from a literal.
; Make sure we emit AdrpLdrGotLdr for those. ; Make sure we emit AdrpLdrGotLdr for those.
; CHECK-LABEL: _getSExtE ; CHECK-LABEL: _getSExtE
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _E@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _E@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _E@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _E@GOTPAGEOFF]
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldrsh w0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: ldrsh w0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]]
define i32 @getSExtE() { define i32 @getSExtE() {
%res = load i16, i16* @E, align 4 %res = load i16, i16* @E, align 4
%sextres = sext i16 %res to i32 %sextres = sext i16 %res to i32
ret i32 %sextres ret i32 %sextres
} }
; CHECK-LABEL: _setE ; CHECK-LABEL: _setE
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _E@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _E@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _E@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _E@GOTPAGEOFF]
; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: strh w0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: strh w0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]] ; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]]
define void @setE(i16 %t) { define void @setE(i16 %t) {
store i16 %t, i16* @E, align 4 store i16 %t, i16* @E, align 4
ret void ret void
} }
; LDRSH supports loading from a literal. ; LDRSH supports loading from a literal.
; Make sure we emit AdrpLdrGotLdr for those. ; Make sure we emit AdrpLdrGotLdr for those.
; CHECK-LABEL: _getSExt64E ; CHECK-LABEL: _getSExt64E
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _E@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _E@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _E@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _E@GOTPAGEOFF]
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldrsh x0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: ldrsh x0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]]
define i64 @getSExt64E() { define i64 @getSExt64E() {
%res = load i16, i16* @E, align 4 %res = load i16, i16* @E, align 4
%sextres = sext i16 %res to i64 %sextres = sext i16 %res to i64
ret i64 %sextres ret i64 %sextres
} }
@F = common global i64 0, align 4 @F = common global i64 0, align 4
; LDR supports loading from a literal. ; LDR supports loading from a literal.
; Make sure we emit AdrpLdrGotLdr for those. ; Make sure we emit AdrpLdrGotLdr for those.
; CHECK-LABEL: _getF ; CHECK-LABEL: _getF
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _F@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _F@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _F@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _F@GOTPAGEOFF]
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr x0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: ldr x0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]]
define i64 @getF() { define i64 @getF() {
%res = load i64, i64* @F, align 4 %res = load i64, i64* @F, align 4
ret i64 %res ret i64 %res
} }
; CHECK-LABEL: _setF ; CHECK-LABEL: _setF
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _F@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _F@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _F@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _F@GOTPAGEOFF]
; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: str x0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: str x0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]] ; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]]
define void @setF(i64 %t) { define void @setF(i64 %t) {
store i64 %t, i64* @F, align 4 store i64 %t, i64* @F, align 4
ret void ret void
} }
@G = common global float 0.0, align 4 @G = common global float 0.0, align 4
; LDR float supports loading from a literal. ; LDR float supports loading from a literal.
; Make sure we emit AdrpLdrGotLdr for those. ; Make sure we emit AdrpLdrGotLdr for those.
; CHECK-LABEL: _getG ; CHECK-LABEL: _getG
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _G@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _G@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _G@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _G@GOTPAGEOFF]
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr s0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: ldr s0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]]
define float @getG() { define float @getG() {
%res = load float, float* @G, align 4 %res = load float, float* @G, align 4
ret float %res ret float %res
} }
; CHECK-LABEL: _setG ; CHECK-LABEL: _setG
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _G@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _G@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _G@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _G@GOTPAGEOFF]
; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: str s0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: str s0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]] ; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]]
define void @setG(float %t) { define void @setG(float %t) {
store float %t, float* @G, align 4 store float %t, float* @G, align 4
ret void ret void
} }
@H = common global half 0.0, align 4 @H = common global half 0.0, align 4
; LDR half supports loading from a literal. ; LDR half supports loading from a literal.
; Make sure we emit AdrpLdrGotLdr for those. ; Make sure we emit AdrpLdrGotLdr for those.
; CHECK-LABEL: _getH ; CHECK-LABEL: _getH
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _H@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _H@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _H@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _H@GOTPAGEOFF]
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr h0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: ldr h0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]]
define half @getH() { define half @getH() {
%res = load half, half* @H, align 4 %res = load half, half* @H, align 4
ret half %res ret half %res
} }
; CHECK-LABEL: _setH ; CHECK-LABEL: _setH
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _H@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _H@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _H@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _H@GOTPAGEOFF]
; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: str h0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: str h0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]] ; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]]
define void @setH(half %t) { define void @setH(half %t) {
store half %t, half* @H, align 4 store half %t, half* @H, align 4
ret void ret void
} }
@I = common global double 0.0, align 4 @I = common global double 0.0, align 4
; LDR double supports loading from a literal. ; LDR double supports loading from a literal.
; Make sure we emit AdrpLdrGotLdr for those. ; Make sure we emit AdrpLdrGotLdr for those.
; CHECK-LABEL: _getI ; CHECK-LABEL: _getI
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _I@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _I@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _I@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _I@GOTPAGEOFF]
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr d0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: ldr d0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]]
define double @getI() { define double @getI() {
%res = load double, double* @I, align 4 %res = load double, double* @I, align 4
ret double %res ret double %res
} }
; CHECK-LABEL: _setI ; CHECK-LABEL: _setI
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _I@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _I@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _I@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _I@GOTPAGEOFF]
; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: str d0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: str d0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]] ; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]]
define void @setI(double %t) { define void @setI(double %t) {
store double %t, double* @I, align 4 store double %t, double* @I, align 4
ret void ret void
} }
@J = common global <2 x i32> <i32 0, i32 0>, align 4 @J = common global <2 x i32> <i32 0, i32 0>, align 4
; LDR 64-bit vector supports loading from a literal. ; LDR 64-bit vector supports loading from a literal.
; Make sure we emit AdrpLdrGotLdr for those. ; Make sure we emit AdrpLdrGotLdr for those.
; CHECK-LABEL: _getJ ; CHECK-LABEL: _getJ
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _J@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _J@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _J@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _J@GOTPAGEOFF]
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr d0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: ldr d0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]]
define <2 x i32> @getJ() { define <2 x i32> @getJ() {
%res = load <2 x i32>, <2 x i32>* @J, align 4 %res = load <2 x i32>, <2 x i32>* @J, align 4
ret <2 x i32> %res ret <2 x i32> %res
} }
; CHECK-LABEL: _setJ ; CHECK-LABEL: _setJ
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _J@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _J@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _J@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _J@GOTPAGEOFF]
; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: str d0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: str d0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]] ; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]]
define void @setJ(<2 x i32> %t) { define void @setJ(<2 x i32> %t) {
store <2 x i32> %t, <2 x i32>* @J, align 4 store <2 x i32> %t, <2 x i32>* @J, align 4
ret void ret void
} }
@K = common global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 4 @K = common global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 4
; LDR 128-bit vector supports loading from a literal. ; LDR 128-bit vector supports loading from a literal.
; Make sure we emit AdrpLdrGotLdr for those. ; Make sure we emit AdrpLdrGotLdr for those.
; CHECK-LABEL: _getK ; CHECK-LABEL: _getK
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _K@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _K@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _K@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _K@GOTPAGEOFF]
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr q0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: ldr q0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]]
define <4 x i32> @getK() { define <4 x i32> @getK() {
%res = load <4 x i32>, <4 x i32>* @K, align 4 %res = load <4 x i32>, <4 x i32>* @K, align 4
ret <4 x i32> %res ret <4 x i32> %res
} }
; CHECK-LABEL: _setK ; CHECK-LABEL: _setK
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _K@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _K@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _K@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _K@GOTPAGEOFF]
; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[STR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: str q0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: str q0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]] ; CHECK: .loh AdrpLdrGotStr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[STR_LABEL]]
define void @setK(<4 x i32> %t) { define void @setK(<4 x i32> %t) {
store <4 x i32> %t, <4 x i32>* @K, align 4 store <4 x i32> %t, <4 x i32>* @K, align 4
ret void ret void
} }
@L = common global <1 x i8> <i8 0>, align 4 @L = common global <1 x i8> <i8 0>, align 4
; LDR 8-bit vector supports loading from a literal. ; LDR 8-bit vector supports loading from a literal.
; Make sure we emit AdrpLdrGotLdr for those. ; Make sure we emit AdrpLdrGotLdr for those.
; CHECK-LABEL: _getL ; CHECK-LABEL: _getL
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _L@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _L@GOTPAGE
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _L@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _L@GOTPAGEOFF]
; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDR_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr b0, [x[[LDRGOT_REG]]] ; CHECK-NEXT: ldr b0, [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]] ; CHECK: .loh AdrpLdrGotLdr [[ADRP_LABEL]], [[LDRGOT_LABEL]], [[LDR_LABEL]]
define <1 x i8> @getL() { define <1 x i8> @getL() {
%res = load <1 x i8>, <1 x i8>* @L, align 4 %res = load <1 x i8>, <1 x i8>* @L, align 4
ret <1 x i8> %res ret <1 x i8> %res
} }
; CHECK-LABEL: _setL ; CHECK-LABEL: _setL
; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]: ; CHECK: [[ADRP_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _L@GOTPAGE ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _L@GOTPAGE
; CHECK-NEXT: ; kill ; CHECK-NEXT: ; kill
; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]:
; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], {{\[}}[[ADRP_REG]], _L@GOTPAGEOFF] ; CHECK-NEXT: ldr {{[xw]}}[[LDRGOT_REG:[0-9]+]], [[[ADRP_REG]], _L@GOTPAGEOFF]
; Ultimately we should generate str b0, but right now, we match the vector ; Ultimately we should generate str b0, but right now, we match the vector
; variant which does not allow to fold the immediate into the store. ; variant which does not allow to fold the immediate into the store.
; CHECK-NEXT: st1.b { v0 }[0], [x[[LDRGOT_REG]]] ; CHECK-NEXT: st1.b { v0 }[0], [x[[LDRGOT_REG]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK: .loh AdrpLdrGot [[ADRP_LABEL]], [[LDRGOT_LABEL]] ; CHECK: .loh AdrpLdrGot [[ADRP_LABEL]], [[LDRGOT_LABEL]]
define void @setL(<1 x i8> %t) { define void @setL(<1 x i8> %t) {
store <1 x i8> %t, <1 x i8>* @L, align 4 store <1 x i8> %t, <1 x i8>* @L, align 4
ret void ret void
} }
; Make sure we do not assert when we do not track ; Make sure we do not assert when we do not track
; all the aliases of a tuple register. ; all the aliases of a tuple register.
; Indeed the tuple register can be tracked because of ; Indeed the tuple register can be tracked because of
; one of its element, but the other elements of the tuple ; one of its element, but the other elements of the tuple
; do not need to be tracked and we used to assert on that. ; do not need to be tracked and we used to assert on that.
; Note: The test case is fragile in the sense that we need ; Note: The test case is fragile in the sense that we need
; a tuple register to appear in the lowering. Thus, the target ; a tuple register to appear in the lowering. Thus, the target
; cpu is required to have the problem reproduced. ; cpu is required to have the problem reproduced.
; CHECK-LABEL: _uninterestingSub ; CHECK-LABEL: _uninterestingSub
; CHECK: [[LOH_LABEL0:Lloh[0-9]+]]: ; CHECK: [[LOH_LABEL0:Lloh[0-9]+]]:
; CHECK: adrp [[ADRP_REG:x[0-9]+]], [[CONSTPOOL:lCPI[0-9]+_[0-9]+]]@PAGE ; CHECK: adrp [[ADRP_REG:x[0-9]+]], [[CONSTPOOL:lCPI[0-9]+_[0-9]+]]@PAGE
; CHECK: [[LOH_LABEL1:Lloh[0-9]+]]: ; CHECK: [[LOH_LABEL1:Lloh[0-9]+]]:
; CHECK: ldr q[[IDX:[0-9]+]], {{\[}}[[ADRP_REG]], [[CONSTPOOL]]@PAGEOFF] ; CHECK: ldr q[[IDX:[0-9]+]], [[[ADRP_REG]], [[CONSTPOOL]]@PAGEOFF]
; The tuple comes from the next instruction. ; The tuple comes from the next instruction.
; CHECK: ext.16b v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, #1 ; CHECK: ext.16b v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, #1
; CHECK: ret ; CHECK: ret
; CHECK: .loh AdrpLdr [[LOH_LABEL0]], [[LOH_LABEL1]] ; CHECK: .loh AdrpLdr [[LOH_LABEL0]], [[LOH_LABEL1]]
define void @uninterestingSub(i8* nocapture %row) #0 { define void @uninterestingSub(i8* nocapture %row) #0 {
%tmp = bitcast i8* %row to <16 x i8>* %tmp = bitcast i8* %row to <16 x i8>*
%tmp1 = load <16 x i8>, <16 x i8>* %tmp, align 16 %tmp1 = load <16 x i8>, <16 x i8>* %tmp, align 16
%vext43 = shufflevector <16 x i8> <i8 undef, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2>, <16 x i8> %tmp1, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16> %vext43 = shufflevector <16 x i8> <i8 undef, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2>, <16 x i8> %tmp1, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
Show All 35 Lines

llvm/test/CodeGen/AArch64/arm64-dagcombiner-load-slicing.ll

; RUN: llc -mtriple arm64-apple-ios -O3 -o - < %s | FileCheck %s ; RUN: llc -mtriple arm64-apple-ios -O3 -o - < %s | FileCheck %s
; <rdar://problem/14477220> ; <rdar://problem/14477220>
%class.Complex = type { float, float } %class.Complex = type { float, float }
%class.Complex_int = type { i32, i32 } %class.Complex_int = type { i32, i32 }
%class.Complex_long = type { i64, i64 } %class.Complex_long = type { i64, i64 }
; CHECK-LABEL: @test ; CHECK-LABEL: @test
; CHECK: add [[BASE:x[0-9]+]], x0, x1, lsl #3 ; CHECK: add [[BASE:x[0-9]+]], x0, x1, lsl #3
; CHECK: ldp [[CPLX1_I:s[0-9]+]], [[CPLX1_R:s[0-9]+]], {{\[}}[[BASE]]] ; CHECK: ldp [[CPLX1_I:s[0-9]+]], [[CPLX1_R:s[0-9]+]], [[[BASE]]]
; CHECK: ldp [[CPLX2_I:s[0-9]+]], [[CPLX2_R:s[0-9]+]], {{\[}}[[BASE]], #64] ; CHECK: ldp [[CPLX2_I:s[0-9]+]], [[CPLX2_R:s[0-9]+]], [[[BASE]], #64]
; CHECK: fadd {{s[0-9]+}}, [[CPLX2_I]], [[CPLX1_I]] ; CHECK: fadd {{s[0-9]+}}, [[CPLX2_I]], [[CPLX1_I]]
; CHECK: fadd {{s[0-9]+}}, [[CPLX2_R]], [[CPLX1_R]] ; CHECK: fadd {{s[0-9]+}}, [[CPLX2_R]], [[CPLX1_R]]
; CHECK: ret ; CHECK: ret
define void @test(%class.Complex* nocapture %out, i64 %out_start) { define void @test(%class.Complex* nocapture %out, i64 %out_start) {
entry: entry:
%arrayidx = getelementptr inbounds %class.Complex, %class.Complex* %out, i64 %out_start %arrayidx = getelementptr inbounds %class.Complex, %class.Complex* %out, i64 %out_start
%0 = bitcast %class.Complex* %arrayidx to i64* %0 = bitcast %class.Complex* %arrayidx to i64*
%1 = load i64, i64* %0, align 4 %1 = load i64, i64* %0, align 4
Show All 14 Linesentry:
%retval.sroa.0.4.vec.insert.i = insertelement <2 x float> %retval.sroa.0.0.vec.insert.i, float %add5.i, i32 1 %retval.sroa.0.4.vec.insert.i = insertelement <2 x float> %retval.sroa.0.0.vec.insert.i, float %add5.i, i32 1
%ref.tmp.sroa.0.0.cast = bitcast %class.Complex* %arrayidx to <2 x float>* %ref.tmp.sroa.0.0.cast = bitcast %class.Complex* %arrayidx to <2 x float>*
store <2 x float> %retval.sroa.0.4.vec.insert.i, <2 x float>* %ref.tmp.sroa.0.0.cast, align 4 store <2 x float> %retval.sroa.0.4.vec.insert.i, <2 x float>* %ref.tmp.sroa.0.0.cast, align 4
ret void ret void
} }
; CHECK-LABEL: @test_int ; CHECK-LABEL: @test_int
; CHECK: add [[BASE:x[0-9]+]], x0, x1, lsl #3 ; CHECK: add [[BASE:x[0-9]+]], x0, x1, lsl #3
; CHECK: ldp [[CPLX1_I:w[0-9]+]], [[CPLX1_R:w[0-9]+]], {{\[}}[[BASE]]] ; CHECK: ldp [[CPLX1_I:w[0-9]+]], [[CPLX1_R:w[0-9]+]], [[[BASE]]]
; CHECK: ldp [[CPLX2_I:w[0-9]+]], [[CPLX2_R:w[0-9]+]], {{\[}}[[BASE]], #64] ; CHECK: ldp [[CPLX2_I:w[0-9]+]], [[CPLX2_R:w[0-9]+]], [[[BASE]], #64]
; CHECK: add {{w[0-9]+}}, [[CPLX2_I]], [[CPLX1_I]] ; CHECK: add {{w[0-9]+}}, [[CPLX2_I]], [[CPLX1_I]]
; CHECK: add {{w[0-9]+}}, [[CPLX2_R]], [[CPLX1_R]] ; CHECK: add {{w[0-9]+}}, [[CPLX2_R]], [[CPLX1_R]]
; CHECK: ret ; CHECK: ret
define void @test_int(%class.Complex_int* nocapture %out, i64 %out_start) { define void @test_int(%class.Complex_int* nocapture %out, i64 %out_start) {
entry: entry:
%arrayidx = getelementptr inbounds %class.Complex_int, %class.Complex_int* %out, i64 %out_start %arrayidx = getelementptr inbounds %class.Complex_int, %class.Complex_int* %out, i64 %out_start
%0 = bitcast %class.Complex_int* %arrayidx to i64* %0 = bitcast %class.Complex_int* %arrayidx to i64*
%1 = load i64, i64* %0, align 4 %1 = load i64, i64* %0, align 4
Show All 14 Linesentry:
%retval.sroa.0.4.vec.insert.i = insertelement <2 x i32> %retval.sroa.0.0.vec.insert.i, i32 %add5.i, i32 1 %retval.sroa.0.4.vec.insert.i = insertelement <2 x i32> %retval.sroa.0.0.vec.insert.i, i32 %add5.i, i32 1
%ref.tmp.sroa.0.0.cast = bitcast %class.Complex_int* %arrayidx to <2 x i32>* %ref.tmp.sroa.0.0.cast = bitcast %class.Complex_int* %arrayidx to <2 x i32>*
store <2 x i32> %retval.sroa.0.4.vec.insert.i, <2 x i32>* %ref.tmp.sroa.0.0.cast, align 4 store <2 x i32> %retval.sroa.0.4.vec.insert.i, <2 x i32>* %ref.tmp.sroa.0.0.cast, align 4
ret void ret void
} }
; CHECK-LABEL: @test_long ; CHECK-LABEL: @test_long
; CHECK: add [[BASE:x[0-9]+]], x0, x1, lsl #4 ; CHECK: add [[BASE:x[0-9]+]], x0, x1, lsl #4
; CHECK: ldp [[CPLX1_I:x[0-9]+]], [[CPLX1_R:x[0-9]+]], {{\[}}[[BASE]]] ; CHECK: ldp [[CPLX1_I:x[0-9]+]], [[CPLX1_R:x[0-9]+]], [[[BASE]]]
; CHECK: ldp [[CPLX2_I:x[0-9]+]], [[CPLX2_R:x[0-9]+]], {{\[}}[[BASE]], #128] ; CHECK: ldp [[CPLX2_I:x[0-9]+]], [[CPLX2_R:x[0-9]+]], [[[BASE]], #128]
; CHECK: add {{x[0-9]+}}, [[CPLX2_I]], [[CPLX1_I]] ; CHECK: add {{x[0-9]+}}, [[CPLX2_I]], [[CPLX1_I]]
; CHECK: add {{x[0-9]+}}, [[CPLX2_R]], [[CPLX1_R]] ; CHECK: add {{x[0-9]+}}, [[CPLX2_R]], [[CPLX1_R]]
; CHECK: ret ; CHECK: ret
define void @test_long(%class.Complex_long* nocapture %out, i64 %out_start) { define void @test_long(%class.Complex_long* nocapture %out, i64 %out_start) {
entry: entry:
%arrayidx = getelementptr inbounds %class.Complex_long, %class.Complex_long* %out, i64 %out_start %arrayidx = getelementptr inbounds %class.Complex_long, %class.Complex_long* %out, i64 %out_start
%0 = bitcast %class.Complex_long* %arrayidx to i128* %0 = bitcast %class.Complex_long* %arrayidx to i128*
%1 = load i128, i128* %0, align 4 %1 = load i128, i128* %0, align 4
Show All 19 Lines

llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll

; RUN: llc -O0 -fast-isel -fast-isel-abort=2 -code-model=small -verify-machineinstrs -frame-pointer=all -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -O0 -fast-isel -fast-isel-abort=2 -code-model=small -verify-machineinstrs -frame-pointer=all -mtriple=arm64-apple-darwin < %s | FileCheck %s
; RUN: llc -O0 -fast-isel -fast-isel-abort=2 -code-model=large -verify-machineinstrs -frame-pointer=all -mtriple=arm64-apple-darwin < %s | FileCheck %s --check-prefix=LARGE ; RUN: llc -O0 -fast-isel -fast-isel-abort=2 -code-model=large -verify-machineinstrs -frame-pointer=all -mtriple=arm64-apple-darwin < %s | FileCheck %s --check-prefix=LARGE
; RUN: llc -O0 -fast-isel -fast-isel-abort=2 -code-model=small -verify-machineinstrs -frame-pointer=all -mtriple=aarch64_be-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-BE ; RUN: llc -O0 -fast-isel -fast-isel-abort=2 -code-model=small -verify-machineinstrs -frame-pointer=all -mtriple=aarch64_be-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-BE
define void @call0() nounwind { define void @call0() nounwind {
entry: entry:
ret void ret void
} }
define void @foo0() nounwind { define void @foo0() nounwind {
entry: entry:
; CHECK-LABEL: foo0 ; CHECK-LABEL: foo0
; CHECK: bl _call0 ; CHECK: bl _call0
; LARGE-LABEL: foo0 ; LARGE-LABEL: foo0
; LARGE: adrp [[REG0:x[0-9]+]], _call0@GOTPAGE ; LARGE: adrp [[REG0:x[0-9]+]], _call0@GOTPAGE
; LARGE: ldr [[REG1:x[0-9]+]], {{\[}}[[REG0]], _call0@GOTPAGEOFF{{\]}} ; LARGE: ldr [[REG1:x[0-9]+]], [[[REG0]], _call0@GOTPAGEOFF]
; LARGE-NEXT: blr [[REG1]] ; LARGE-NEXT: blr [[REG1]]
call void @call0() call void @call0()
ret void ret void
} }
define i32 @call1(i32 %a) nounwind { define i32 @call1(i32 %a) nounwind {
entry: entry:
%a.addr = alloca i32, align 4 %a.addr = alloca i32, align 4
▲ Show 20 Lines • Show All 245 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll

; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
; Test load/store of global value from global offset table. ; Test load/store of global value from global offset table.
@seed = common global i64 0, align 8 @seed = common global i64 0, align 8
define void @Initrand() nounwind { define void @Initrand() nounwind {
entry: entry:
; CHECK: @Initrand ; CHECK: @Initrand
; CHECK: adrp [[REG:x[0-9]+]], _seed@GOTPAGE ; CHECK: adrp [[REG:x[0-9]+]], _seed@GOTPAGE
; CHECK: ldr [[REG2:x[0-9]+]], {{\[}}[[REG]], _seed@GOTPAGEOFF{{\]}} ; CHECK: ldr [[REG2:x[0-9]+]], [[[REG]], _seed@GOTPAGEOFF]
; CHECK: str {{x[0-9]+}}, {{\[}}[[REG2]]{{\]}} ; CHECK: str {{x[0-9]+}}, [[[REG2]]]
store i64 74755, i64* @seed, align 8 store i64 74755, i64* @seed, align 8
ret void ret void
} }
define i32 @Rand() nounwind { define i32 @Rand() nounwind {
entry: entry:
; CHECK: @Rand ; CHECK: @Rand
; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE ; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE
; CHECK: ldr [[REG2:x[0-9]+]], {{\[}}[[REG1]], _seed@GOTPAGEOFF{{\]}} ; CHECK: ldr [[REG2:x[0-9]+]], [[[REG1]], _seed@GOTPAGEOFF]
; CHECK: ldr [[REG5:x[0-9]+]], {{\[}}[[REG2]]{{\]}} ; CHECK: ldr [[REG5:x[0-9]+]], [[[REG2]]]
; CHECK: mov [[REG4:x[0-9]+]], #1309 ; CHECK: mov [[REG4:x[0-9]+]], #1309
; CHECK: mul [[REG6:x[0-9]+]], [[REG5]], [[REG4]] ; CHECK: mul [[REG6:x[0-9]+]], [[REG5]], [[REG4]]
; CHECK: mov [[REG3:x[0-9]+]], #13849 ; CHECK: mov [[REG3:x[0-9]+]], #13849
; CHECK: add [[REG7:x[0-9]+]], [[REG6]], [[REG3]] ; CHECK: add [[REG7:x[0-9]+]], [[REG6]], [[REG3]]
; CHECK: and [[REG8:x[0-9]+]], [[REG7]], #0xffff ; CHECK: and [[REG8:x[0-9]+]], [[REG7]], #0xffff
; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE ; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE
; CHECK: ldr [[REG1]], {{\[}}[[REG1]], _seed@GOTPAGEOFF{{\]}} ; CHECK: ldr [[REG1]], [[[REG1]], _seed@GOTPAGEOFF]
; CHECK: str [[REG8]], {{\[}}[[REG1]]{{\]}} ; CHECK: str [[REG8]], [[[REG1]]]
; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE ; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE
; CHECK: ldr [[REG1]], {{\[}}[[REG1]], _seed@GOTPAGEOFF{{\]}} ; CHECK: ldr [[REG1]], [[[REG1]], _seed@GOTPAGEOFF]
; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG1]]{{\]}} ; CHECK: ldr {{x[0-9]+}}, [[[REG1]]]
%0 = load i64, i64* @seed, align 8 %0 = load i64, i64* @seed, align 8
%mul = mul nsw i64 %0, 1309 %mul = mul nsw i64 %0, 1309
%add = add nsw i64 %mul, 13849 %add = add nsw i64 %mul, 13849
%and = and i64 %add, 65535 %and = and i64 %add, 65535
store i64 %and, i64* @seed, align 8 store i64 %and, i64* @seed, align 8
%1 = load i64, i64* @seed, align 8 %1 = load i64, i64* @seed, align 8
%conv = trunc i64 %1 to i32 %conv = trunc i64 %1 to i32
ret i32 %conv ret i32 %conv
} }

llvm/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1)
define void @t4() { define void @t4() {
; ARM64-LABEL: t4 ; ARM64-LABEL: t4
; ARM64: adrp x8, _temp@GOTPAGE ; ARM64: adrp x8, _temp@GOTPAGE
; ARM64: ldr [[REG0:x[0-9]+]], [x8, _temp@GOTPAGEOFF] ; ARM64: ldr [[REG0:x[0-9]+]], [x8, _temp@GOTPAGEOFF]
; ARM64: adrp [[REG1:x[0-9]+]], _message@PAGE ; ARM64: adrp [[REG1:x[0-9]+]], _message@PAGE
; ARM64: add [[REG2:x[0-9]+]], [[REG1]], _message@PAGEOFF ; ARM64: add [[REG2:x[0-9]+]], [[REG1]], _message@PAGEOFF
; ARM64: ldr x10, {{\[}}[[REG2]]{{\]}} ; ARM64: ldr x10, [[[REG2]]]
; ARM64: str x10, {{\[}}[[REG0]]{{\]}} ; ARM64: str x10, [[[REG0]]]
; ARM64: ldr x10, {{\[}}[[REG2]], #8] ; ARM64: ldr x10, [[[REG2]], #8]
; ARM64: str x10, {{\[}}[[REG0]], #8] ; ARM64: str x10, [[[REG0]], #8]
; ARM64: ldrb [[REG3:w[0-9]+]], {{\[}}[[REG2]], #16] ; ARM64: ldrb [[REG3:w[0-9]+]], [[[REG2]], #16]
; ARM64: strb [[REG3]], {{\[}}[[REG0]], #16] ; ARM64: strb [[REG3]], [[[REG0]], #16]
; ARM64: ret ; ARM64: ret
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* align 16 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 17, i1 false) call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* align 16 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 17, i1 false)
ret void ret void
} }
define void @t5() { define void @t5() {
; ARM64-LABEL: t5 ; ARM64-LABEL: t5
; ARM64: adrp x8, _temp@GOTPAGE ; ARM64: adrp x8, _temp@GOTPAGE
; ARM64: ldr [[REG0:x[0-9]+]], [x8, _temp@GOTPAGEOFF] ; ARM64: ldr [[REG0:x[0-9]+]], [x8, _temp@GOTPAGEOFF]
; ARM64: adrp [[REG3:x[0-9]+]], _message@PAGE ; ARM64: adrp [[REG3:x[0-9]+]], _message@PAGE
; ARM64: add [[REG1:x[0-9]+]], [[REG3]], _message@PAGEOFF ; ARM64: add [[REG1:x[0-9]+]], [[REG3]], _message@PAGEOFF
; ARM64: ldr x10, {{\[}}[[REG1]]] ; ARM64: ldr x10, [[[REG1]]]
; ARM64: str x10, {{\[}}[[REG0]]] ; ARM64: str x10, [[[REG0]]]
; ARM64: ldr x10, {{\[}}[[REG1]], #8] ; ARM64: ldr x10, [[[REG1]], #8]
; ARM64: str x10, {{\[}}[[REG0]], #8] ; ARM64: str x10, [[[REG0]], #8]
; ARM64: ldrb [[REG4:w[0-9]+]], {{\[}}[[REG1]], #16] ; ARM64: ldrb [[REG4:w[0-9]+]], [[[REG1]], #16]
; ARM64: strb [[REG4]], {{\[}}[[REG0]], #16] ; ARM64: strb [[REG4]], [[[REG0]], #16]
; ARM64: ret ; ARM64: ret
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* align 8 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 17, i1 false) call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* align 8 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 17, i1 false)
ret void ret void
} }
define void @t6() { define void @t6() {
; ARM64-LABEL: t6 ; ARM64-LABEL: t6
; ARM64: adrp x8, _temp@GOTPAGE ; ARM64: adrp x8, _temp@GOTPAGE
; ARM64: ldr [[REG0:x[0-9]+]], [x8, _temp@GOTPAGEOFF] ; ARM64: ldr [[REG0:x[0-9]+]], [x8, _temp@GOTPAGEOFF]
; ARM64: adrp [[REG1:x[0-9]+]], _message@PAGE ; ARM64: adrp [[REG1:x[0-9]+]], _message@PAGE
; ARM64: add [[REG2:x[0-9]+]], [[REG1]], _message@PAGEOFF ; ARM64: add [[REG2:x[0-9]+]], [[REG1]], _message@PAGEOFF
; ARM64: ldr w10, {{\[}}[[REG2]]] ; ARM64: ldr w10, [[[REG2]]]
; ARM64: str w10, {{\[}}[[REG0]]] ; ARM64: str w10, [[[REG0]]]
; ARM64: ldr w10, {{\[}}[[REG2]], #4] ; ARM64: ldr w10, [[[REG2]], #4]
; ARM64: str w10, {{\[}}[[REG0]], #4] ; ARM64: str w10, [[[REG0]], #4]
; ARM64: ldrb [[REG3:w[0-9]+]], {{\[}}[[REG2]], #8] ; ARM64: ldrb [[REG3:w[0-9]+]], [[[REG2]], #8]
; ARM64: strb [[REG3]], {{\[}}[[REG0]], #8] ; ARM64: strb [[REG3]], [[[REG0]], #8]
; ARM64: ret ; ARM64: ret
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* align 4 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 9, i1 false) call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* align 4 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 9, i1 false)
ret void ret void
} }
define void @t7() { define void @t7() {
; ARM64-LABEL: t7 ; ARM64-LABEL: t7
; ARM64: adrp x8, _temp@GOTPAGE ; ARM64: adrp x8, _temp@GOTPAGE
; ARM64: ldr [[REG0:x[0-9]+]], [x8, _temp@GOTPAGEOFF] ; ARM64: ldr [[REG0:x[0-9]+]], [x8, _temp@GOTPAGEOFF]
; ARM64: adrp [[REG1:x[0-9]+]], _message@PAGE ; ARM64: adrp [[REG1:x[0-9]+]], _message@PAGE
; ARM64: add [[REG2:x[0-9]+]], [[REG1]], _message@PAGEOFF ; ARM64: add [[REG2:x[0-9]+]], [[REG1]], _message@PAGEOFF
; ARM64: ldrh w10, {{\[}}[[REG2]]] ; ARM64: ldrh w10, [[[REG2]]]
; ARM64: strh w10, {{\[}}[[REG0]]] ; ARM64: strh w10, [[[REG0]]]
; ARM64: ldrh w10, {{\[}}[[REG2]], #2] ; ARM64: ldrh w10, [[[REG2]], #2]
; ARM64: strh w10, {{\[}}[[REG0]], #2] ; ARM64: strh w10, [[[REG0]], #2]
; ARM64: ldrh w10, {{\[}}[[REG2]], #4] ; ARM64: ldrh w10, [[[REG2]], #4]
; ARM64: strh w10, {{\[}}[[REG0]], #4] ; ARM64: strh w10, [[[REG0]], #4]
; ARM64: ldrb [[REG3:w[0-9]+]], {{\[}}[[REG2]], #6] ; ARM64: ldrb [[REG3:w[0-9]+]], [[[REG2]], #6]
; ARM64: strb [[REG3]], {{\[}}[[REG0]], #6] ; ARM64: strb [[REG3]], [[[REG0]], #6]
; ARM64: ret ; ARM64: ret
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* align 2 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 7, i1 false) call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* align 2 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 7, i1 false)
ret void ret void
} }
define void @t8() { define void @t8() {
; ARM64-LABEL: t8 ; ARM64-LABEL: t8
; ARM64: adrp x8, _temp@GOTPAGE ; ARM64: adrp x8, _temp@GOTPAGE
; ARM64: ldr [[REG0:x[0-9]+]], [x8, _temp@GOTPAGEOFF] ; ARM64: ldr [[REG0:x[0-9]+]], [x8, _temp@GOTPAGEOFF]
; ARM64: adrp [[REG1:x[0-9]+]], _message@PAGE ; ARM64: adrp [[REG1:x[0-9]+]], _message@PAGE
; ARM64: add [[REG2:x[0-9]+]], [[REG1:x[0-9]+]], _message@PAGEOFF ; ARM64: add [[REG2:x[0-9]+]], [[REG1:x[0-9]+]], _message@PAGEOFF
; ARM64: ldrb w10, {{\[}}[[REG2]]] ; ARM64: ldrb w10, [[[REG2]]]
; ARM64: strb w10, {{\[}}[[REG0]]] ; ARM64: strb w10, [[[REG0]]]
; ARM64: ldrb w10, {{\[}}[[REG2]], #1] ; ARM64: ldrb w10, [[[REG2]], #1]
; ARM64: strb w10, {{\[}}[[REG0]], #1] ; ARM64: strb w10, [[[REG0]], #1]
; ARM64: ldrb w10, {{\[}}[[REG2]], #2] ; ARM64: ldrb w10, [[[REG2]], #2]
; ARM64: strb w10, {{\[}}[[REG0]], #2] ; ARM64: strb w10, [[[REG0]], #2]
; ARM64: ldrb [[REG3:w[0-9]+]], {{\[}}[[REG2]], #3] ; ARM64: ldrb [[REG3:w[0-9]+]], [[[REG2]], #3]
; ARM64: strb [[REG3]], {{\[}}[[REG0]], #3] ; ARM64: strb [[REG3]], [[[REG0]], #3]
; ARM64: ret ; ARM64: ret
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 1 getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* align 1 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 4, i1 false) call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 1 getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* align 1 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 4, i1 false)
ret void ret void
} }
define void @test_distant_memcpy(i8* %dst) { define void @test_distant_memcpy(i8* %dst) {
; ARM64-LABEL: test_distant_memcpy: ; ARM64-LABEL: test_distant_memcpy:
; ARM64: mov [[ARRAY:x[0-9]+]], sp ; ARM64: mov [[ARRAY:x[0-9]+]], sp
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llvm/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll

Show All 33 Lines
; GISEL: movi d0, #0000000000000000 ; GISEL: movi d0, #0000000000000000
ret double 0.0e+00 ret double 0.0e+00
} }
; Materialize from constant pool ; Materialize from constant pool
define float @cp_float() { define float @cp_float() {
; CHECK-LABEL: cp_float ; CHECK-LABEL: cp_float
; CHECK: adrp [[REG:x[0-9]+]], {{lCPI[0-9]+_0}}@PAGE ; CHECK: adrp [[REG:x[0-9]+]], {{lCPI[0-9]+_0}}@PAGE
; CHECK-NEXT: ldr s0, {{\[}}[[REG]], {{lCPI[0-9]+_0}}@PAGEOFF{{\]}} ; CHECK-NEXT: ldr s0, [[[REG]], {{lCPI[0-9]+_0}}@PAGEOFF]
ret float 0x400921FB60000000 ret float 0x400921FB60000000
} }
define double @cp_double() { define double @cp_double() {
; CHECK-LABEL: cp_double ; CHECK-LABEL: cp_double
; CHECK: adrp [[REG:x[0-9]+]], {{lCPI[0-9]+_0}}@PAGE ; CHECK: adrp [[REG:x[0-9]+]], {{lCPI[0-9]+_0}}@PAGE
; CHECK-NEXT: ldr d0, {{\[}}[[REG]], {{lCPI[0-9]+_0}}@PAGEOFF{{\]}} ; CHECK-NEXT: ldr d0, [[[REG]], {{lCPI[0-9]+_0}}@PAGEOFF]
ret double 0x400921FB54442D18 ret double 0x400921FB54442D18
} }

llvm/test/CodeGen/AArch64/arm64-promote-const.ll

; Disable machine cse to stress the different path of the algorithm. ; Disable machine cse to stress the different path of the algorithm.
; Otherwise, we always fall in the simple case, i.e., only one definition. ; Otherwise, we always fall in the simple case, i.e., only one definition.
; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-machine-cse -aarch64-stress-promote-const -mcpu=cyclone -verify-machineinstrs | FileCheck -check-prefix=PROMOTED %s ; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-machine-cse -aarch64-stress-promote-const -mcpu=cyclone -verify-machineinstrs | FileCheck -check-prefix=PROMOTED %s
; The REGULAR run just checks that the inputs passed to promote const expose ; The REGULAR run just checks that the inputs passed to promote const expose
; the appropriate patterns. ; the appropriate patterns.
; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-machine-cse -aarch64-enable-promote-const=false -mcpu=cyclone -verify-machineinstrs | FileCheck -check-prefix=REGULAR %s ; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-machine-cse -aarch64-enable-promote-const=false -mcpu=cyclone -verify-machineinstrs | FileCheck -check-prefix=REGULAR %s
%struct.uint8x16x4_t = type { [4 x <16 x i8>] } %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
; Constant is a structure ; Constant is a structure
define %struct.uint8x16x4_t @test1() { define %struct.uint8x16x4_t @test1() {
; PROMOTED-LABEL: test1: ; PROMOTED-LABEL: test1:
; Promote constant has created a big constant for the whole structure ; Promote constant has created a big constant for the whole structure
; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], __PromotedConst@PAGE ; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], __PromotedConst@PAGE
; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], __PromotedConst@PAGEOFF ; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], __PromotedConst@PAGEOFF
; Destination registers are defined by the ABI ; Destination registers are defined by the ABI
; PROMOTED-NEXT: ldp q0, q1, {{\[}}[[BASEADDR]]] ; PROMOTED-NEXT: ldp q0, q1, [[[BASEADDR]]]
; PROMOTED-NEXT: ldp q2, q3, {{\[}}[[BASEADDR]], #32] ; PROMOTED-NEXT: ldp q2, q3, [[[BASEADDR]], #32]
; PROMOTED-NEXT: ret ; PROMOTED-NEXT: ret
; REGULAR-LABEL: test1: ; REGULAR-LABEL: test1:
; Regular access is quite bad, it performs 4 loads, one for each chunk of ; Regular access is quite bad, it performs 4 loads, one for each chunk of
; the structure ; the structure
; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE ; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
; Destination registers are defined by the ABI ; Destination registers are defined by the ABI
; REGULAR: ldr q0, {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF] ; REGULAR: ldr q0, [[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE ; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
; REGULAR: ldr q1, {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF] ; REGULAR: ldr q1, [[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
; REGULAR: adrp [[PAGEADDR2:x[0-9]+]], [[CSTLABEL2:lCP.*]]@PAGE ; REGULAR: adrp [[PAGEADDR2:x[0-9]+]], [[CSTLABEL2:lCP.*]]@PAGE
; REGULAR: ldr q2, {{\[}}[[PAGEADDR2]], [[CSTLABEL2]]@PAGEOFF] ; REGULAR: ldr q2, [[[PAGEADDR2]], [[CSTLABEL2]]@PAGEOFF]
; REGULAR: adrp [[PAGEADDR3:x[0-9]+]], [[CSTLABEL3:lCP.*]]@PAGE ; REGULAR: adrp [[PAGEADDR3:x[0-9]+]], [[CSTLABEL3:lCP.*]]@PAGE
; REGULAR: ldr q3, {{\[}}[[PAGEADDR3]], [[CSTLABEL3]]@PAGEOFF] ; REGULAR: ldr q3, [[[PAGEADDR3]], [[CSTLABEL3]]@PAGEOFF]
; REGULAR-NEXT: ret ; REGULAR-NEXT: ret
entry: entry:
ret %struct.uint8x16x4_t { [4 x <16 x i8>] [<16 x i8> <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>, <16 x i8> <i8 32, i8 124, i8 121, i8 120, i8 8, i8 117, i8 -56, i8 113, i8 -76, i8 110, i8 -53, i8 107, i8 7, i8 105, i8 103, i8 102>, <16 x i8> <i8 -24, i8 99, i8 -121, i8 97, i8 66, i8 95, i8 24, i8 93, i8 6, i8 91, i8 12, i8 89, i8 39, i8 87, i8 86, i8 85>, <16 x i8> <i8 -104, i8 83, i8 -20, i8 81, i8 81, i8 80, i8 -59, i8 78, i8 73, i8 77, i8 -37, i8 75, i8 122, i8 74, i8 37, i8 73>] } ret %struct.uint8x16x4_t { [4 x <16 x i8>] [<16 x i8> <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>, <16 x i8> <i8 32, i8 124, i8 121, i8 120, i8 8, i8 117, i8 -56, i8 113, i8 -76, i8 110, i8 -53, i8 107, i8 7, i8 105, i8 103, i8 102>, <16 x i8> <i8 -24, i8 99, i8 -121, i8 97, i8 66, i8 95, i8 24, i8 93, i8 6, i8 91, i8 12, i8 89, i8 39, i8 87, i8 86, i8 85>, <16 x i8> <i8 -104, i8 83, i8 -20, i8 81, i8 81, i8 80, i8 -59, i8 78, i8 73, i8 77, i8 -37, i8 75, i8 122, i8 74, i8 37, i8 73>] }
} }
; Two different uses of the same constant in the same basic block ; Two different uses of the same constant in the same basic block
define <16 x i8> @test2(<16 x i8> %arg) { define <16 x i8> @test2(<16 x i8> %arg) {
entry: entry:
; PROMOTED-LABEL: test2: ; PROMOTED-LABEL: test2:
; In stress mode, constant vector are promoted ; In stress mode, constant vector are promoted
; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1:__PromotedConst.[0-9]+]]@PAGE ; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1:__PromotedConst.[0-9]+]]@PAGE
; PROMOTED: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF] ; PROMOTED: ldr q[[REGNUM:[0-9]+]], [[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
; Destination register is defined by ABI ; Destination register is defined by ABI
; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]] ; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
; PROMOTED-NEXT: mla.16b v0, v0, v[[REGNUM]] ; PROMOTED-NEXT: mla.16b v0, v0, v[[REGNUM]]
; PROMOTED-NEXT: ret ; PROMOTED-NEXT: ret
; REGULAR-LABEL: test2: ; REGULAR-LABEL: test2:
; Regular access is strickly the same as promoted access. ; Regular access is strickly the same as promoted access.
; The difference is that the address (and thus the space in memory) is not ; The difference is that the address (and thus the space in memory) is not
; shared between constants ; shared between constants
; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE ; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
; REGULAR: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF] ; REGULAR: ldr q[[REGNUM:[0-9]+]], [[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
; Destination register is defined by ABI ; Destination register is defined by ABI
; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]] ; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]]
; REGULAR-NEXT: mla.16b v0, v0, v[[REGNUM]] ; REGULAR-NEXT: mla.16b v0, v0, v[[REGNUM]]
; REGULAR-NEXT: ret ; REGULAR-NEXT: ret
%add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
%mul.i = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128> %mul.i = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
%add.i9 = add <16 x i8> %add.i, %mul.i %add.i9 = add <16 x i8> %add.i, %mul.i
ret <16 x i8> %add.i9 ret <16 x i8> %add.i9
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llvm/test/CodeGen/AArch64/arm64-swizzle-tbl-i16-layout.ll

Show All 21 Lines
; CHECK: .byte 9 ; 0x9 ; CHECK: .byte 9 ; 0x9
; CHECK: .byte 8 ; 0x8 ; CHECK: .byte 8 ; 0x8
; CHECK: .byte 9 ; 0x9 ; CHECK: .byte 9 ; 0x9
; CHECK: .section __TEXT,__text,regular,pure_instructions ; CHECK: .section __TEXT,__text,regular,pure_instructions
; CHECK: .globl _foo ; CHECK: .globl _foo
; CHECK: .p2align 2 ; CHECK: .p2align 2
; CHECK:_foo: ; @foo ; CHECK:_foo: ; @foo
; CHECK: adrp [[BASE:x[0-9]+]], lCPI0_0@PAGE ; CHECK: adrp [[BASE:x[0-9]+]], lCPI0_0@PAGE
; CHECK: ldr q[[REG:[0-9]+]], {{\[}}[[BASE]], lCPI0_0@PAGEOFF] ; CHECK: ldr q[[REG:[0-9]+]], [[[BASE]], lCPI0_0@PAGEOFF]
; CHECK: tbl.16b v0, { v0 }, v[[REG]] ; CHECK: tbl.16b v0, { v0 }, v[[REG]]
; CHECK: ret ; CHECK: ret
%val = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4> %val = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4>
ret <8 x i16> %val ret <8 x i16> %val
} }

llvm/test/CodeGen/AArch64/arm64-vector-ldst.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
@floatglobalArray32x2 = common global <2 x float>* null, align 8 @floatglobalArray32x2 = common global <2 x float>* null, align 8
define void @fct1_64x2(<2 x i64>* nocapture %array, i64 %offset) nounwind ssp { define void @fct1_64x2(<2 x i64>* nocapture %array, i64 %offset) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct1_64x2: ; CHECK-LABEL: fct1_64x2:
; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #4 ; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #4
; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]] ; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]
; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]] ; CHECK: str [[DEST]], [[[BASE]], [[SHIFTEDOFFSET]]]
%arrayidx = getelementptr inbounds <2 x i64>, <2 x i64>* %array, i64 %offset %arrayidx = getelementptr inbounds <2 x i64>, <2 x i64>* %array, i64 %offset
%tmp = load <2 x i64>, <2 x i64>* %arrayidx, align 16 %tmp = load <2 x i64>, <2 x i64>* %arrayidx, align 16
%tmp1 = load <2 x i64>*, <2 x i64>** @globalArray64x2, align 8 %tmp1 = load <2 x i64>*, <2 x i64>** @globalArray64x2, align 8
%arrayidx1 = getelementptr inbounds <2 x i64>, <2 x i64>* %tmp1, i64 %offset %arrayidx1 = getelementptr inbounds <2 x i64>, <2 x i64>* %tmp1, i64 %offset
store <2 x i64> %tmp, <2 x i64>* %arrayidx1, align 16 store <2 x i64> %tmp, <2 x i64>* %arrayidx1, align 16
ret void ret void
} }
define void @fct2_64x2(<2 x i64>* nocapture %array) nounwind ssp { define void @fct2_64x2(<2 x i64>* nocapture %array) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct2_64x2: ; CHECK-LABEL: fct2_64x2:
; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48] ; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48]
; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], {{\[}}[[BASE]], #80] ; CHECK: str [[DEST]], [[[BASE]], #80]
%arrayidx = getelementptr inbounds <2 x i64>, <2 x i64>* %array, i64 3 %arrayidx = getelementptr inbounds <2 x i64>, <2 x i64>* %array, i64 3
%tmp = load <2 x i64>, <2 x i64>* %arrayidx, align 16 %tmp = load <2 x i64>, <2 x i64>* %arrayidx, align 16
%tmp1 = load <2 x i64>*, <2 x i64>** @globalArray64x2, align 8 %tmp1 = load <2 x i64>*, <2 x i64>** @globalArray64x2, align 8
%arrayidx1 = getelementptr inbounds <2 x i64>, <2 x i64>* %tmp1, i64 5 %arrayidx1 = getelementptr inbounds <2 x i64>, <2 x i64>* %tmp1, i64 5
store <2 x i64> %tmp, <2 x i64>* %arrayidx1, align 16 store <2 x i64> %tmp, <2 x i64>* %arrayidx1, align 16
ret void ret void
} }
define void @fct1_32x4(<4 x i32>* nocapture %array, i64 %offset) nounwind ssp { define void @fct1_32x4(<4 x i32>* nocapture %array, i64 %offset) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct1_32x4: ; CHECK-LABEL: fct1_32x4:
; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #4 ; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #4
; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]] ; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]] ; CHECK: str [[DEST]], [[[BASE]], [[SHIFTEDOFFSET]]]
%arrayidx = getelementptr inbounds <4 x i32>, <4 x i32>* %array, i64 %offset %arrayidx = getelementptr inbounds <4 x i32>, <4 x i32>* %array, i64 %offset
%tmp = load <4 x i32>, <4 x i32>* %arrayidx, align 16 %tmp = load <4 x i32>, <4 x i32>* %arrayidx, align 16
%tmp1 = load <4 x i32>*, <4 x i32>** @globalArray32x4, align 8 %tmp1 = load <4 x i32>*, <4 x i32>** @globalArray32x4, align 8
%arrayidx1 = getelementptr inbounds <4 x i32>, <4 x i32>* %tmp1, i64 %offset %arrayidx1 = getelementptr inbounds <4 x i32>, <4 x i32>* %tmp1, i64 %offset
store <4 x i32> %tmp, <4 x i32>* %arrayidx1, align 16 store <4 x i32> %tmp, <4 x i32>* %arrayidx1, align 16
ret void ret void
} }
define void @fct2_32x4(<4 x i32>* nocapture %array) nounwind ssp { define void @fct2_32x4(<4 x i32>* nocapture %array) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct2_32x4: ; CHECK-LABEL: fct2_32x4:
; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48] ; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48]
; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], {{\[}}[[BASE]], #80] ; CHECK: str [[DEST]], [[[BASE]], #80]
%arrayidx = getelementptr inbounds <4 x i32>, <4 x i32>* %array, i64 3 %arrayidx = getelementptr inbounds <4 x i32>, <4 x i32>* %array, i64 3
%tmp = load <4 x i32>, <4 x i32>* %arrayidx, align 16 %tmp = load <4 x i32>, <4 x i32>* %arrayidx, align 16
%tmp1 = load <4 x i32>*, <4 x i32>** @globalArray32x4, align 8 %tmp1 = load <4 x i32>*, <4 x i32>** @globalArray32x4, align 8
%arrayidx1 = getelementptr inbounds <4 x i32>, <4 x i32>* %tmp1, i64 5 %arrayidx1 = getelementptr inbounds <4 x i32>, <4 x i32>* %tmp1, i64 5
store <4 x i32> %tmp, <4 x i32>* %arrayidx1, align 16 store <4 x i32> %tmp, <4 x i32>* %arrayidx1, align 16
ret void ret void
} }
define void @fct1_16x8(<8 x i16>* nocapture %array, i64 %offset) nounwind ssp { define void @fct1_16x8(<8 x i16>* nocapture %array, i64 %offset) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct1_16x8: ; CHECK-LABEL: fct1_16x8:
; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #4 ; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #4
; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]] ; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]] ; CHECK: str [[DEST]], [[[BASE]], [[SHIFTEDOFFSET]]]
%arrayidx = getelementptr inbounds <8 x i16>, <8 x i16>* %array, i64 %offset %arrayidx = getelementptr inbounds <8 x i16>, <8 x i16>* %array, i64 %offset
%tmp = load <8 x i16>, <8 x i16>* %arrayidx, align 16 %tmp = load <8 x i16>, <8 x i16>* %arrayidx, align 16
%tmp1 = load <8 x i16>*, <8 x i16>** @globalArray16x8, align 8 %tmp1 = load <8 x i16>*, <8 x i16>** @globalArray16x8, align 8
%arrayidx1 = getelementptr inbounds <8 x i16>, <8 x i16>* %tmp1, i64 %offset %arrayidx1 = getelementptr inbounds <8 x i16>, <8 x i16>* %tmp1, i64 %offset
store <8 x i16> %tmp, <8 x i16>* %arrayidx1, align 16 store <8 x i16> %tmp, <8 x i16>* %arrayidx1, align 16
ret void ret void
} }
define void @fct2_16x8(<8 x i16>* nocapture %array) nounwind ssp { define void @fct2_16x8(<8 x i16>* nocapture %array) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct2_16x8: ; CHECK-LABEL: fct2_16x8:
; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48] ; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48]
; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], {{\[}}[[BASE]], #80] ; CHECK: str [[DEST]], [[[BASE]], #80]
%arrayidx = getelementptr inbounds <8 x i16>, <8 x i16>* %array, i64 3 %arrayidx = getelementptr inbounds <8 x i16>, <8 x i16>* %array, i64 3
%tmp = load <8 x i16>, <8 x i16>* %arrayidx, align 16 %tmp = load <8 x i16>, <8 x i16>* %arrayidx, align 16
%tmp1 = load <8 x i16>*, <8 x i16>** @globalArray16x8, align 8 %tmp1 = load <8 x i16>*, <8 x i16>** @globalArray16x8, align 8
%arrayidx1 = getelementptr inbounds <8 x i16>, <8 x i16>* %tmp1, i64 5 %arrayidx1 = getelementptr inbounds <8 x i16>, <8 x i16>* %tmp1, i64 5
store <8 x i16> %tmp, <8 x i16>* %arrayidx1, align 16 store <8 x i16> %tmp, <8 x i16>* %arrayidx1, align 16
ret void ret void
} }
define void @fct1_8x16(<16 x i8>* nocapture %array, i64 %offset) nounwind ssp { define void @fct1_8x16(<16 x i8>* nocapture %array, i64 %offset) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct1_8x16: ; CHECK-LABEL: fct1_8x16:
; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #4 ; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #4
; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]] ; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]] ; CHECK: str [[DEST]], [[[BASE]], [[SHIFTEDOFFSET]]]
%arrayidx = getelementptr inbounds <16 x i8>, <16 x i8>* %array, i64 %offset %arrayidx = getelementptr inbounds <16 x i8>, <16 x i8>* %array, i64 %offset
%tmp = load <16 x i8>, <16 x i8>* %arrayidx, align 16 %tmp = load <16 x i8>, <16 x i8>* %arrayidx, align 16
%tmp1 = load <16 x i8>*, <16 x i8>** @globalArray8x16, align 8 %tmp1 = load <16 x i8>*, <16 x i8>** @globalArray8x16, align 8
%arrayidx1 = getelementptr inbounds <16 x i8>, <16 x i8>* %tmp1, i64 %offset %arrayidx1 = getelementptr inbounds <16 x i8>, <16 x i8>* %tmp1, i64 %offset
store <16 x i8> %tmp, <16 x i8>* %arrayidx1, align 16 store <16 x i8> %tmp, <16 x i8>* %arrayidx1, align 16
ret void ret void
} }
define void @fct2_8x16(<16 x i8>* nocapture %array) nounwind ssp { define void @fct2_8x16(<16 x i8>* nocapture %array) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct2_8x16: ; CHECK-LABEL: fct2_8x16:
; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48] ; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48]
; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], {{\[}}[[BASE]], #80] ; CHECK: str [[DEST]], [[[BASE]], #80]
%arrayidx = getelementptr inbounds <16 x i8>, <16 x i8>* %array, i64 3 %arrayidx = getelementptr inbounds <16 x i8>, <16 x i8>* %array, i64 3
%tmp = load <16 x i8>, <16 x i8>* %arrayidx, align 16 %tmp = load <16 x i8>, <16 x i8>* %arrayidx, align 16
%tmp1 = load <16 x i8>*, <16 x i8>** @globalArray8x16, align 8 %tmp1 = load <16 x i8>*, <16 x i8>** @globalArray8x16, align 8
%arrayidx1 = getelementptr inbounds <16 x i8>, <16 x i8>* %tmp1, i64 5 %arrayidx1 = getelementptr inbounds <16 x i8>, <16 x i8>* %tmp1, i64 5
store <16 x i8> %tmp, <16 x i8>* %arrayidx1, align 16 store <16 x i8> %tmp, <16 x i8>* %arrayidx1, align 16
ret void ret void
} }
define void @fct1_64x1(<1 x i64>* nocapture %array, i64 %offset) nounwind ssp { define void @fct1_64x1(<1 x i64>* nocapture %array, i64 %offset) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct1_64x1: ; CHECK-LABEL: fct1_64x1:
; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #3 ; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #3
; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]] ; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]] ; CHECK: str [[DEST]], [[[BASE]], [[SHIFTEDOFFSET]]]
%arrayidx = getelementptr inbounds <1 x i64>, <1 x i64>* %array, i64 %offset %arrayidx = getelementptr inbounds <1 x i64>, <1 x i64>* %array, i64 %offset
%tmp = load <1 x i64>, <1 x i64>* %arrayidx, align 8 %tmp = load <1 x i64>, <1 x i64>* %arrayidx, align 8
%tmp1 = load <1 x i64>*, <1 x i64>** @globalArray64x1, align 8 %tmp1 = load <1 x i64>*, <1 x i64>** @globalArray64x1, align 8
%arrayidx1 = getelementptr inbounds <1 x i64>, <1 x i64>* %tmp1, i64 %offset %arrayidx1 = getelementptr inbounds <1 x i64>, <1 x i64>* %tmp1, i64 %offset
store <1 x i64> %tmp, <1 x i64>* %arrayidx1, align 8 store <1 x i64> %tmp, <1 x i64>* %arrayidx1, align 8
ret void ret void
} }
define void @fct2_64x1(<1 x i64>* nocapture %array) nounwind ssp { define void @fct2_64x1(<1 x i64>* nocapture %array) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct2_64x1: ; CHECK-LABEL: fct2_64x1:
; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24] ; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24]
; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], {{\[}}[[BASE]], #40] ; CHECK: str [[DEST]], [[[BASE]], #40]
%arrayidx = getelementptr inbounds <1 x i64>, <1 x i64>* %array, i64 3 %arrayidx = getelementptr inbounds <1 x i64>, <1 x i64>* %array, i64 3
%tmp = load <1 x i64>, <1 x i64>* %arrayidx, align 8 %tmp = load <1 x i64>, <1 x i64>* %arrayidx, align 8
%tmp1 = load <1 x i64>*, <1 x i64>** @globalArray64x1, align 8 %tmp1 = load <1 x i64>*, <1 x i64>** @globalArray64x1, align 8
%arrayidx1 = getelementptr inbounds <1 x i64>, <1 x i64>* %tmp1, i64 5 %arrayidx1 = getelementptr inbounds <1 x i64>, <1 x i64>* %tmp1, i64 5
store <1 x i64> %tmp, <1 x i64>* %arrayidx1, align 8 store <1 x i64> %tmp, <1 x i64>* %arrayidx1, align 8
ret void ret void
} }
define void @fct1_32x2(<2 x i32>* nocapture %array, i64 %offset) nounwind ssp { define void @fct1_32x2(<2 x i32>* nocapture %array, i64 %offset) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct1_32x2: ; CHECK-LABEL: fct1_32x2:
; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #3 ; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #3
; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]] ; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]] ; CHECK: str [[DEST]], [[[BASE]], [[SHIFTEDOFFSET]]]
%arrayidx = getelementptr inbounds <2 x i32>, <2 x i32>* %array, i64 %offset %arrayidx = getelementptr inbounds <2 x i32>, <2 x i32>* %array, i64 %offset
%tmp = load <2 x i32>, <2 x i32>* %arrayidx, align 8 %tmp = load <2 x i32>, <2 x i32>* %arrayidx, align 8
%tmp1 = load <2 x i32>*, <2 x i32>** @globalArray32x2, align 8 %tmp1 = load <2 x i32>*, <2 x i32>** @globalArray32x2, align 8
%arrayidx1 = getelementptr inbounds <2 x i32>, <2 x i32>* %tmp1, i64 %offset %arrayidx1 = getelementptr inbounds <2 x i32>, <2 x i32>* %tmp1, i64 %offset
store <2 x i32> %tmp, <2 x i32>* %arrayidx1, align 8 store <2 x i32> %tmp, <2 x i32>* %arrayidx1, align 8
ret void ret void
} }
define void @fct2_32x2(<2 x i32>* nocapture %array) nounwind ssp { define void @fct2_32x2(<2 x i32>* nocapture %array) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct2_32x2: ; CHECK-LABEL: fct2_32x2:
; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24] ; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24]
; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], {{\[}}[[BASE]], #40] ; CHECK: str [[DEST]], [[[BASE]], #40]
%arrayidx = getelementptr inbounds <2 x i32>, <2 x i32>* %array, i64 3 %arrayidx = getelementptr inbounds <2 x i32>, <2 x i32>* %array, i64 3
%tmp = load <2 x i32>, <2 x i32>* %arrayidx, align 8 %tmp = load <2 x i32>, <2 x i32>* %arrayidx, align 8
%tmp1 = load <2 x i32>*, <2 x i32>** @globalArray32x2, align 8 %tmp1 = load <2 x i32>*, <2 x i32>** @globalArray32x2, align 8
%arrayidx1 = getelementptr inbounds <2 x i32>, <2 x i32>* %tmp1, i64 5 %arrayidx1 = getelementptr inbounds <2 x i32>, <2 x i32>* %tmp1, i64 5
store <2 x i32> %tmp, <2 x i32>* %arrayidx1, align 8 store <2 x i32> %tmp, <2 x i32>* %arrayidx1, align 8
ret void ret void
} }
define void @fct1_16x4(<4 x i16>* nocapture %array, i64 %offset) nounwind ssp { define void @fct1_16x4(<4 x i16>* nocapture %array, i64 %offset) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct1_16x4: ; CHECK-LABEL: fct1_16x4:
; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #3 ; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #3
; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]] ; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]] ; CHECK: str [[DEST]], [[[BASE]], [[SHIFTEDOFFSET]]]
%arrayidx = getelementptr inbounds <4 x i16>, <4 x i16>* %array, i64 %offset %arrayidx = getelementptr inbounds <4 x i16>, <4 x i16>* %array, i64 %offset
%tmp = load <4 x i16>, <4 x i16>* %arrayidx, align 8 %tmp = load <4 x i16>, <4 x i16>* %arrayidx, align 8
%tmp1 = load <4 x i16>*, <4 x i16>** @globalArray16x4, align 8 %tmp1 = load <4 x i16>*, <4 x i16>** @globalArray16x4, align 8
%arrayidx1 = getelementptr inbounds <4 x i16>, <4 x i16>* %tmp1, i64 %offset %arrayidx1 = getelementptr inbounds <4 x i16>, <4 x i16>* %tmp1, i64 %offset
store <4 x i16> %tmp, <4 x i16>* %arrayidx1, align 8 store <4 x i16> %tmp, <4 x i16>* %arrayidx1, align 8
ret void ret void
} }
define void @fct2_16x4(<4 x i16>* nocapture %array) nounwind ssp { define void @fct2_16x4(<4 x i16>* nocapture %array) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct2_16x4: ; CHECK-LABEL: fct2_16x4:
; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24] ; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24]
; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], {{\[}}[[BASE]], #40] ; CHECK: str [[DEST]], [[[BASE]], #40]
%arrayidx = getelementptr inbounds <4 x i16>, <4 x i16>* %array, i64 3 %arrayidx = getelementptr inbounds <4 x i16>, <4 x i16>* %array, i64 3
%tmp = load <4 x i16>, <4 x i16>* %arrayidx, align 8 %tmp = load <4 x i16>, <4 x i16>* %arrayidx, align 8
%tmp1 = load <4 x i16>*, <4 x i16>** @globalArray16x4, align 8 %tmp1 = load <4 x i16>*, <4 x i16>** @globalArray16x4, align 8
%arrayidx1 = getelementptr inbounds <4 x i16>, <4 x i16>* %tmp1, i64 5 %arrayidx1 = getelementptr inbounds <4 x i16>, <4 x i16>* %tmp1, i64 5
store <4 x i16> %tmp, <4 x i16>* %arrayidx1, align 8 store <4 x i16> %tmp, <4 x i16>* %arrayidx1, align 8
ret void ret void
} }
define void @fct1_8x8(<8 x i8>* nocapture %array, i64 %offset) nounwind ssp { define void @fct1_8x8(<8 x i8>* nocapture %array, i64 %offset) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct1_8x8: ; CHECK-LABEL: fct1_8x8:
; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #3 ; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #3
; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]] ; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]] ; CHECK: str [[DEST]], [[[BASE]], [[SHIFTEDOFFSET]]]
%arrayidx = getelementptr inbounds <8 x i8>, <8 x i8>* %array, i64 %offset %arrayidx = getelementptr inbounds <8 x i8>, <8 x i8>* %array, i64 %offset
%tmp = load <8 x i8>, <8 x i8>* %arrayidx, align 8 %tmp = load <8 x i8>, <8 x i8>* %arrayidx, align 8
%tmp1 = load <8 x i8>*, <8 x i8>** @globalArray8x8, align 8 %tmp1 = load <8 x i8>*, <8 x i8>** @globalArray8x8, align 8
%arrayidx1 = getelementptr inbounds <8 x i8>, <8 x i8>* %tmp1, i64 %offset %arrayidx1 = getelementptr inbounds <8 x i8>, <8 x i8>* %tmp1, i64 %offset
store <8 x i8> %tmp, <8 x i8>* %arrayidx1, align 8 store <8 x i8> %tmp, <8 x i8>* %arrayidx1, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
%q = bitcast i8* %p to <16 x i8>* %q = bitcast i8* %p to <16 x i8>*
%0 = load <16 x i8>, <16 x i8>* %q, align 16 %0 = load <16 x i8>, <16 x i8>* %q, align 16
ret <16 x i8> %0 ret <16 x i8> %0
} }
define void @fct8(i8* %str) nounwind ssp { define void @fct8(i8* %str) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct8: ; CHECK-LABEL: fct8:
; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3] ; CHECK: ldur [[DESTREG:d[0-9]+]], [[[BASEREG:x[0-9]+]], #3]
; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4] ; CHECK: stur [[DESTREG]], [[[BASEREG]], #4]
%p = getelementptr inbounds i8, i8* %str, i64 3 %p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <1 x i64>* %q = bitcast i8* %p to <1 x i64>*
%0 = load <1 x i64>, <1 x i64>* %q, align 8 %0 = load <1 x i64>, <1 x i64>* %q, align 8
%p2 = getelementptr inbounds i8, i8* %str, i64 4 %p2 = getelementptr inbounds i8, i8* %str, i64 4
%q2 = bitcast i8* %p2 to <1 x i64>* %q2 = bitcast i8* %p2 to <1 x i64>*
store <1 x i64> %0, <1 x i64>* %q2, align 8 store <1 x i64> %0, <1 x i64>* %q2, align 8
ret void ret void
} }
define void @fct9(i8* %str) nounwind ssp { define void @fct9(i8* %str) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct9: ; CHECK-LABEL: fct9:
; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3] ; CHECK: ldur [[DESTREG:d[0-9]+]], [[[BASEREG:x[0-9]+]], #3]
; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4] ; CHECK: stur [[DESTREG]], [[[BASEREG]], #4]
%p = getelementptr inbounds i8, i8* %str, i64 3 %p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <2 x i32>* %q = bitcast i8* %p to <2 x i32>*
%0 = load <2 x i32>, <2 x i32>* %q, align 8 %0 = load <2 x i32>, <2 x i32>* %q, align 8
%p2 = getelementptr inbounds i8, i8* %str, i64 4 %p2 = getelementptr inbounds i8, i8* %str, i64 4
%q2 = bitcast i8* %p2 to <2 x i32>* %q2 = bitcast i8* %p2 to <2 x i32>*
store <2 x i32> %0, <2 x i32>* %q2, align 8 store <2 x i32> %0, <2 x i32>* %q2, align 8
ret void ret void
} }
define void @fct10(i8* %str) nounwind ssp { define void @fct10(i8* %str) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct10: ; CHECK-LABEL: fct10:
; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3] ; CHECK: ldur [[DESTREG:d[0-9]+]], [[[BASEREG:x[0-9]+]], #3]
; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4] ; CHECK: stur [[DESTREG]], [[[BASEREG]], #4]
%p = getelementptr inbounds i8, i8* %str, i64 3 %p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <4 x i16>* %q = bitcast i8* %p to <4 x i16>*
%0 = load <4 x i16>, <4 x i16>* %q, align 8 %0 = load <4 x i16>, <4 x i16>* %q, align 8
%p2 = getelementptr inbounds i8, i8* %str, i64 4 %p2 = getelementptr inbounds i8, i8* %str, i64 4
%q2 = bitcast i8* %p2 to <4 x i16>* %q2 = bitcast i8* %p2 to <4 x i16>*
store <4 x i16> %0, <4 x i16>* %q2, align 8 store <4 x i16> %0, <4 x i16>* %q2, align 8
ret void ret void
} }
define void @fct11(i8* %str) nounwind ssp { define void @fct11(i8* %str) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct11: ; CHECK-LABEL: fct11:
; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3] ; CHECK: ldur [[DESTREG:d[0-9]+]], [[[BASEREG:x[0-9]+]], #3]
; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4] ; CHECK: stur [[DESTREG]], [[[BASEREG]], #4]
%p = getelementptr inbounds i8, i8* %str, i64 3 %p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <8 x i8>* %q = bitcast i8* %p to <8 x i8>*
%0 = load <8 x i8>, <8 x i8>* %q, align 8 %0 = load <8 x i8>, <8 x i8>* %q, align 8
%p2 = getelementptr inbounds i8, i8* %str, i64 4 %p2 = getelementptr inbounds i8, i8* %str, i64 4
%q2 = bitcast i8* %p2 to <8 x i8>* %q2 = bitcast i8* %p2 to <8 x i8>*
store <8 x i8> %0, <8 x i8>* %q2, align 8 store <8 x i8> %0, <8 x i8>* %q2, align 8
ret void ret void
} }
define void @fct12(i8* %str) nounwind ssp { define void @fct12(i8* %str) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct12: ; CHECK-LABEL: fct12:
; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3] ; CHECK: ldur [[DESTREG:q[0-9]+]], [[[BASEREG:x[0-9]+]], #3]
; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4] ; CHECK: stur [[DESTREG]], [[[BASEREG]], #4]
%p = getelementptr inbounds i8, i8* %str, i64 3 %p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <2 x i64>* %q = bitcast i8* %p to <2 x i64>*
%0 = load <2 x i64>, <2 x i64>* %q, align 16 %0 = load <2 x i64>, <2 x i64>* %q, align 16
%p2 = getelementptr inbounds i8, i8* %str, i64 4 %p2 = getelementptr inbounds i8, i8* %str, i64 4
%q2 = bitcast i8* %p2 to <2 x i64>* %q2 = bitcast i8* %p2 to <2 x i64>*
store <2 x i64> %0, <2 x i64>* %q2, align 16 store <2 x i64> %0, <2 x i64>* %q2, align 16
ret void ret void
} }
define void @fct13(i8* %str) nounwind ssp { define void @fct13(i8* %str) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct13: ; CHECK-LABEL: fct13:
; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3] ; CHECK: ldur [[DESTREG:q[0-9]+]], [[[BASEREG:x[0-9]+]], #3]
; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4] ; CHECK: stur [[DESTREG]], [[[BASEREG]], #4]
%p = getelementptr inbounds i8, i8* %str, i64 3 %p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <4 x i32>* %q = bitcast i8* %p to <4 x i32>*
%0 = load <4 x i32>, <4 x i32>* %q, align 16 %0 = load <4 x i32>, <4 x i32>* %q, align 16
%p2 = getelementptr inbounds i8, i8* %str, i64 4 %p2 = getelementptr inbounds i8, i8* %str, i64 4
%q2 = bitcast i8* %p2 to <4 x i32>* %q2 = bitcast i8* %p2 to <4 x i32>*
store <4 x i32> %0, <4 x i32>* %q2, align 16 store <4 x i32> %0, <4 x i32>* %q2, align 16
ret void ret void
} }
define void @fct14(i8* %str) nounwind ssp { define void @fct14(i8* %str) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct14: ; CHECK-LABEL: fct14:
; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3] ; CHECK: ldur [[DESTREG:q[0-9]+]], [[[BASEREG:x[0-9]+]], #3]
; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4] ; CHECK: stur [[DESTREG]], [[[BASEREG]], #4]
%p = getelementptr inbounds i8, i8* %str, i64 3 %p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <8 x i16>* %q = bitcast i8* %p to <8 x i16>*
%0 = load <8 x i16>, <8 x i16>* %q, align 16 %0 = load <8 x i16>, <8 x i16>* %q, align 16
%p2 = getelementptr inbounds i8, i8* %str, i64 4 %p2 = getelementptr inbounds i8, i8* %str, i64 4
%q2 = bitcast i8* %p2 to <8 x i16>* %q2 = bitcast i8* %p2 to <8 x i16>*
store <8 x i16> %0, <8 x i16>* %q2, align 16 store <8 x i16> %0, <8 x i16>* %q2, align 16
ret void ret void
} }
define void @fct15(i8* %str) nounwind ssp { define void @fct15(i8* %str) nounwind ssp {
entry: entry:
; CHECK-LABEL: fct15: ; CHECK-LABEL: fct15:
; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3] ; CHECK: ldur [[DESTREG:q[0-9]+]], [[[BASEREG:x[0-9]+]], #3]
; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4] ; CHECK: stur [[DESTREG]], [[[BASEREG]], #4]
%p = getelementptr inbounds i8, i8* %str, i64 3 %p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <16 x i8>* %q = bitcast i8* %p to <16 x i8>*
%0 = load <16 x i8>, <16 x i8>* %q, align 16 %0 = load <16 x i8>, <16 x i8>* %q, align 16
%p2 = getelementptr inbounds i8, i8* %str, i64 4 %p2 = getelementptr inbounds i8, i8* %str, i64 4
%q2 = bitcast i8* %p2 to <16 x i8>* %q2 = bitcast i8* %p2 to <16 x i8>*
store <16 x i8> %0, <16 x i8>* %q2, align 16 store <16 x i8> %0, <16 x i8>* %q2, align 16
ret void ret void
} }
▲ Show 20 Lines • Show All 190 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/arm64-virtual_base.ll

Show All 29 Lines
%struct.istk_entry = type { double, [3 x double], [3 x double], %struct.Object_Struct*, i32, i32, double, double, i8* } %struct.istk_entry = type { double, [3 x double], [3 x double], %struct.Object_Struct*, i32, i32, double, double, i8* }
%struct.Transform_Struct = type { [4 x [4 x double]], [4 x [4 x double]] } %struct.Transform_Struct = type { [4 x [4 x double]], [4 x [4 x double]] }
%struct.Bezier_Node_Struct = type { i32, [3 x double], double, i32, i8* } %struct.Bezier_Node_Struct = type { i32, [3 x double], double, i32, i8* }
define void @Precompute_Patch_Values(%struct.Bicubic_Patch_Struct* %Shape) { define void @Precompute_Patch_Values(%struct.Bicubic_Patch_Struct* %Shape) {
; CHECK: Precompute_Patch_Values ; CHECK: Precompute_Patch_Values
; CHECK: ldr [[VAL2:q[0-9]+]], [x0, #272] ; CHECK: ldr [[VAL2:q[0-9]+]], [x0, #272]
; CHECK-NEXT: ldr [[VAL:x[0-9]+]], [x0, #288] ; CHECK-NEXT: ldr [[VAL:x[0-9]+]], [x0, #288]
; CHECK-NEXT: stur [[VAL2]], {{\[}}sp, #216] ; CHECK-NEXT: stur [[VAL2]], [sp, #216]
; CHECK-NEXT: str [[VAL]], [sp, #232] ; CHECK-NEXT: str [[VAL]], [sp, #232]
entry: entry:
%Control_Points = alloca [16 x [3 x double]], align 8 %Control_Points = alloca [16 x [3 x double]], align 8
%arraydecay5.3.1 = getelementptr inbounds [16 x [3 x double]], [16 x [3 x double]]* %Control_Points, i64 0, i64 9, i64 0 %arraydecay5.3.1 = getelementptr inbounds [16 x [3 x double]], [16 x [3 x double]]* %Control_Points, i64 0, i64 9, i64 0
%tmp14 = bitcast double* %arraydecay5.3.1 to i8* %tmp14 = bitcast double* %arraydecay5.3.1 to i8*
%arraydecay11.3.1 = getelementptr inbounds %struct.Bicubic_Patch_Struct, %struct.Bicubic_Patch_Struct* %Shape, i64 0, i32 12, i64 1, i64 3, i64 0 %arraydecay11.3.1 = getelementptr inbounds %struct.Bicubic_Patch_Struct, %struct.Bicubic_Patch_Struct* %Shape, i64 0, i32 12, i64 1, i64 3, i64 0
%tmp15 = bitcast double* %arraydecay11.3.1 to i8* %tmp15 = bitcast double* %arraydecay11.3.1 to i8*
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 24, i1 false) call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 24, i1 false)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1)

llvm/test/CodeGen/AArch64/cmpxchg-O0.ll

; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -O0 -fast-isel=0 -global-isel=false %s -o - | FileCheck -enable-var-scope %s ; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -O0 -fast-isel=0 -global-isel=false %s -o - | FileCheck -enable-var-scope %s
; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -O0 -fast-isel=0 -global-isel=false -mattr=+outline-atomics %s -o - | FileCheck -enable-var-scope %s --check-prefix=OUTLINE-ATOMICS ; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -O0 -fast-isel=0 -global-isel=false -mattr=+outline-atomics %s -o - | FileCheck -enable-var-scope %s --check-prefix=OUTLINE-ATOMICS
define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind { define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind {
; OUTLINE-ATOMICS: bl __aarch64_cas1_acq_rel ; OUTLINE-ATOMICS: bl __aarch64_cas1_acq_rel
; CHECK-LABEL: test_cmpxchg_8: ; CHECK-LABEL: test_cmpxchg_8:
; CHECK: mov [[ADDR:x[0-9]+]], x0 ; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxrb [[OLD:w[0-9]+]], {{\[}}[[ADDR]]{{\]}} ; CHECK: ldaxrb [[OLD:w[0-9]+]], [[[ADDR]]]
; CHECK: cmp [[OLD]], w1, uxtb ; CHECK: cmp [[OLD]], w1, uxtb
; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] ; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: stlxrb [[STATUS:w[0-9]+]], w2, {{\[}}[[ADDR]]{{\]}} ; CHECK: stlxrb [[STATUS:w[0-9]+]], w2, [[[ADDR]]]
; CHECK: cbnz [[STATUS]], [[RETRY]] ; CHECK: cbnz [[STATUS]], [[RETRY]]
; CHECK: [[DONE]]: ; CHECK: [[DONE]]:
; CHECK: subs {{w[0-9]+}}, [[OLD]], w1, uxtb ; CHECK: subs {{w[0-9]+}}, [[OLD]], w1, uxtb
; CHECK: cset {{w[0-9]+}}, eq ; CHECK: cset {{w[0-9]+}}, eq
%res = cmpxchg i8* %addr, i8 %desired, i8 %new seq_cst monotonic %res = cmpxchg i8* %addr, i8 %desired, i8 %new seq_cst monotonic
ret { i8, i1 } %res ret { i8, i1 } %res
} }
define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind { define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind {
; OUTLINE-ATOMICS: bl __aarch64_cas2_acq_rel ; OUTLINE-ATOMICS: bl __aarch64_cas2_acq_rel
; CHECK-LABEL: test_cmpxchg_16: ; CHECK-LABEL: test_cmpxchg_16:
; CHECK: mov [[ADDR:x[0-9]+]], x0 ; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxrh [[OLD:w[0-9]+]], {{\[}}[[ADDR]]{{\]}} ; CHECK: ldaxrh [[OLD:w[0-9]+]], [[[ADDR]]]
; CHECK: cmp [[OLD]], w1, uxth ; CHECK: cmp [[OLD]], w1, uxth
; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] ; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: stlxrh [[STATUS:w[3-9]]], w2, {{\[}}[[ADDR]]{{\]}} ; CHECK: stlxrh [[STATUS:w[3-9]]], w2, [[[ADDR]]]
; CHECK: cbnz [[STATUS]], [[RETRY]] ; CHECK: cbnz [[STATUS]], [[RETRY]]
; CHECK: [[DONE]]: ; CHECK: [[DONE]]:
; CHECK: subs {{w[0-9]+}}, [[OLD]], w1 ; CHECK: subs {{w[0-9]+}}, [[OLD]], w1
; CHECK: cset {{w[0-9]+}}, eq ; CHECK: cset {{w[0-9]+}}, eq
%res = cmpxchg i16* %addr, i16 %desired, i16 %new seq_cst monotonic %res = cmpxchg i16* %addr, i16 %desired, i16 %new seq_cst monotonic
ret { i16, i1 } %res ret { i16, i1 } %res
} }
define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind { define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind {
; OUTLINE-ATOMICS: bl __aarch64_cas4_acq_rel ; OUTLINE-ATOMICS: bl __aarch64_cas4_acq_rel
; CHECK-LABEL: test_cmpxchg_32: ; CHECK-LABEL: test_cmpxchg_32:
; CHECK: mov [[ADDR:x[0-9]+]], x0 ; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxr [[OLD:w[0-9]+]], {{\[}}[[ADDR]]{{\]}} ; CHECK: ldaxr [[OLD:w[0-9]+]], [[[ADDR]]]
; CHECK: cmp [[OLD]], w1 ; CHECK: cmp [[OLD]], w1
; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] ; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: stlxr [[STATUS:w[0-9]+]], w2, {{\[}}[[ADDR]]{{\]}} ; CHECK: stlxr [[STATUS:w[0-9]+]], w2, [[[ADDR]]]
; CHECK: cbnz [[STATUS]], [[RETRY]] ; CHECK: cbnz [[STATUS]], [[RETRY]]
; CHECK: [[DONE]]: ; CHECK: [[DONE]]:
; CHECK: subs {{w[0-9]+}}, [[OLD]], w1 ; CHECK: subs {{w[0-9]+}}, [[OLD]], w1
; CHECK: cset {{w[0-9]+}}, eq ; CHECK: cset {{w[0-9]+}}, eq
%res = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic %res = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
ret { i32, i1 } %res ret { i32, i1 } %res
} }
define { i64, i1 } @test_cmpxchg_64(i64* %addr, i64 %desired, i64 %new) nounwind { define { i64, i1 } @test_cmpxchg_64(i64* %addr, i64 %desired, i64 %new) nounwind {
; OUTLINE-ATOMICS: bl __aarch64_cas8_acq_rel ; OUTLINE-ATOMICS: bl __aarch64_cas8_acq_rel
; CHECK-LABEL: test_cmpxchg_64: ; CHECK-LABEL: test_cmpxchg_64:
; CHECK: mov [[ADDR:x[0-9]+]], x0 ; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxr [[OLD:x[0-9]+]], {{\[}}[[ADDR]]{{\]}} ; CHECK: ldaxr [[OLD:x[0-9]+]], [[[ADDR]]]
; CHECK: cmp [[OLD]], x1 ; CHECK: cmp [[OLD]], x1
; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] ; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: stlxr [[STATUS:w[0-9]+]], x2, {{\[}}[[ADDR]]{{\]}} ; CHECK: stlxr [[STATUS:w[0-9]+]], x2, [[[ADDR]]]
; CHECK: cbnz [[STATUS]], [[RETRY]] ; CHECK: cbnz [[STATUS]], [[RETRY]]
; CHECK: [[DONE]]: ; CHECK: [[DONE]]:
; CHECK: subs {{x[0-9]+}}, [[OLD]], x1 ; CHECK: subs {{x[0-9]+}}, [[OLD]], x1
; CHECK: cset {{w[0-9]+}}, eq ; CHECK: cset {{w[0-9]+}}, eq
%res = cmpxchg i64* %addr, i64 %desired, i64 %new seq_cst monotonic %res = cmpxchg i64* %addr, i64 %desired, i64 %new seq_cst monotonic
ret { i64, i1 } %res ret { i64, i1 } %res
} }
define { i128, i1 } @test_cmpxchg_128(i128* %addr, i128 %desired, i128 %new) nounwind { define { i128, i1 } @test_cmpxchg_128(i128* %addr, i128 %desired, i128 %new) nounwind {
; OUTLINE-ATOMICS: bl __aarch64_cas16_acq_rel ; OUTLINE-ATOMICS: bl __aarch64_cas16_acq_rel
; CHECK-LABEL: test_cmpxchg_128: ; CHECK-LABEL: test_cmpxchg_128:
; CHECK: mov [[ADDR:x[0-9]+]], x0 ; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxp [[OLD_LO:x[0-9]+]], [[OLD_HI:x[0-9]+]], {{\[}}[[ADDR]]{{\]}} ; CHECK: ldaxp [[OLD_LO:x[0-9]+]], [[OLD_HI:x[0-9]+]], [[[ADDR]]]
; CHECK: cmp [[OLD_LO]], x2 ; CHECK: cmp [[OLD_LO]], x2
; CHECK: cset [[CMP_TMP:w[0-9]+]], ne ; CHECK: cset [[CMP_TMP:w[0-9]+]], ne
; CHECK: cmp [[OLD_HI]], x3 ; CHECK: cmp [[OLD_HI]], x3
; CHECK: cinc [[CMP:w[0-9]+]], [[CMP_TMP]], ne ; CHECK: cinc [[CMP:w[0-9]+]], [[CMP_TMP]], ne
; CHECK: cbnz [[CMP]], [[DONE:.LBB[0-9]+_[0-9]+]] ; CHECK: cbnz [[CMP]], [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: stlxp [[STATUS:w[0-9]+]], x4, x5, {{\[}}[[ADDR]]{{\]}} ; CHECK: stlxp [[STATUS:w[0-9]+]], x4, x5, [[[ADDR]]]
; CHECK: cbnz [[STATUS]], [[RETRY]] ; CHECK: cbnz [[STATUS]], [[RETRY]]
; CHECK: [[DONE]]: ; CHECK: [[DONE]]:
%res = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst monotonic %res = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst monotonic
ret { i128, i1 } %res ret { i128, i1 } %res
} }
; Original implementation assumed the desired & new arguments had already been ; Original implementation assumed the desired & new arguments had already been
; type-legalized into some kind of BUILD_PAIR operation and crashed when this ; type-legalized into some kind of BUILD_PAIR operation and crashed when this
; was false. ; was false.
@var128 = dso_local global i128 0 @var128 = dso_local global i128 0
define {i128, i1} @test_cmpxchg_128_unsplit(i128* %addr) { define {i128, i1} @test_cmpxchg_128_unsplit(i128* %addr) {
; OUTLINE-ATOMICS: bl __aarch64_cas16_acq_rel ; OUTLINE-ATOMICS: bl __aarch64_cas16_acq_rel
; CHECK-LABEL: test_cmpxchg_128_unsplit: ; CHECK-LABEL: test_cmpxchg_128_unsplit:
; CHECK: mov [[ADDR:x[0-9]+]], x0 ; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128 ; CHECK: add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128
; CHECK: ldp [[DESIRED_LO:x[0-9]+]], [[DESIRED_HI:x[0-9]+]], [x[[VAR128]]] ; CHECK: ldp [[DESIRED_LO:x[0-9]+]], [[DESIRED_HI:x[0-9]+]], [x[[VAR128]]]
; CHECK: ldp [[NEW_LO:x[0-9]+]], [[NEW_HI:x[0-9]+]], [x[[VAR128]]] ; CHECK: ldp [[NEW_LO:x[0-9]+]], [[NEW_HI:x[0-9]+]], [x[[VAR128]]]
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxp [[OLD_LO:x[0-9]+]], [[OLD_HI:x[0-9]+]], {{\[}}[[ADDR]]{{\]}} ; CHECK: ldaxp [[OLD_LO:x[0-9]+]], [[OLD_HI:x[0-9]+]], [[[ADDR]]]
; CHECK: cmp [[OLD_LO]], [[DESIRED_LO]] ; CHECK: cmp [[OLD_LO]], [[DESIRED_LO]]
; CHECK: cset [[CMP_TMP:w[0-9]+]], ne ; CHECK: cset [[CMP_TMP:w[0-9]+]], ne
; CHECK: cmp [[OLD_HI]], [[DESIRED_HI]] ; CHECK: cmp [[OLD_HI]], [[DESIRED_HI]]
; CHECK: cinc [[CMP:w[0-9]+]], [[CMP_TMP]], ne ; CHECK: cinc [[CMP:w[0-9]+]], [[CMP_TMP]], ne
; CHECK: cbnz [[CMP]], [[DONE:.LBB[0-9]+_[0-9]+]] ; CHECK: cbnz [[CMP]], [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: stlxp [[STATUS:w[0-9]+]], [[NEW_LO]], [[NEW_HI]], {{\[}}[[ADDR]]{{\]}} ; CHECK: stlxp [[STATUS:w[0-9]+]], [[NEW_LO]], [[NEW_HI]], [[[ADDR]]]
; CHECK: cbnz [[STATUS]], [[RETRY]] ; CHECK: cbnz [[STATUS]], [[RETRY]]
; CHECK: [[DONE]]: ; CHECK: [[DONE]]:
%desired = load volatile i128, i128* @var128 %desired = load volatile i128, i128* @var128
%new = load volatile i128, i128* @var128 %new = load volatile i128, i128* @var128
%val = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst %val = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
ret { i128, i1 } %val ret { i128, i1 } %val
} }

llvm/test/CodeGen/AArch64/dllimport.ll

Show All 31 Lines
; CHECK: ret ; CHECK: ret
define i32* @get_var_pointer() { define i32* @get_var_pointer() {
ret i32* @var ret i32* @var
} }
; CHECK-LABEL: get_var_pointer ; CHECK-LABEL: get_var_pointer
; CHECK: adrp [[REG1:x[0-9]+]], __imp_var ; CHECK: adrp [[REG1:x[0-9]+]], __imp_var
; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG1]], :lo12:__imp_var] ; CHECK: ldr {{x[0-9]+}}, [[[REG1]], :lo12:__imp_var]
; CHECK: ret ; CHECK: ret
define i32 @call_external() { define i32 @call_external() {
%call = tail call i32 @external() %call = tail call i32 @external()
ret i32 %call ret i32 %call
} }
; CHECK-LABEL: call_external ; CHECK-LABEL: call_external
Show All 13 Lines

llvm/test/CodeGen/AArch64/fast-isel-atomic.ll

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
define void @atomic_store_release_8(i8* %p, i8 %val) #0 { define void @atomic_store_release_8(i8* %p, i8 %val) #0 {
store atomic i8 %val, i8* %p release, align 1 store atomic i8 %val, i8* %p release, align 1
ret void ret void
} }
; CHECK-LABEL: atomic_store_release_8_off: ; CHECK-LABEL: atomic_store_release_8_off:
; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #1 ; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #1
; CHECK-NEXT: stlrb w1, {{\[}}[[REG0]]] ; CHECK-NEXT: stlrb w1, [[[REG0]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @atomic_store_release_8_off(i8* %p, i8 %val) #0 { define void @atomic_store_release_8_off(i8* %p, i8 %val) #0 {
%tmp0 = getelementptr i8, i8* %p, i32 1 %tmp0 = getelementptr i8, i8* %p, i32 1
store atomic i8 %val, i8* %tmp0 release, align 1 store atomic i8 %val, i8* %tmp0 release, align 1
ret void ret void
} }
; CHECK-LABEL: atomic_store_release_16: ; CHECK-LABEL: atomic_store_release_16:
; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlrh w1, [x0] ; CHECK-NEXT: stlrh w1, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @atomic_store_release_16(i16* %p, i16 %val) #0 { define void @atomic_store_release_16(i16* %p, i16 %val) #0 {
store atomic i16 %val, i16* %p release, align 2 store atomic i16 %val, i16* %p release, align 2
ret void ret void
} }
; CHECK-LABEL: atomic_store_release_16_off: ; CHECK-LABEL: atomic_store_release_16_off:
; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #2 ; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #2
; CHECK-NEXT: stlrh w1, {{\[}}[[REG0]]] ; CHECK-NEXT: stlrh w1, [[[REG0]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @atomic_store_release_16_off(i16* %p, i16 %val) #0 { define void @atomic_store_release_16_off(i16* %p, i16 %val) #0 {
%tmp0 = getelementptr i16, i16* %p, i32 1 %tmp0 = getelementptr i16, i16* %p, i32 1
store atomic i16 %val, i16* %tmp0 release, align 2 store atomic i16 %val, i16* %tmp0 release, align 2
ret void ret void
} }
; CHECK-LABEL: atomic_store_release_32: ; CHECK-LABEL: atomic_store_release_32:
; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlr w1, [x0] ; CHECK-NEXT: stlr w1, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @atomic_store_release_32(i32* %p, i32 %val) #0 { define void @atomic_store_release_32(i32* %p, i32 %val) #0 {
store atomic i32 %val, i32* %p release, align 4 store atomic i32 %val, i32* %p release, align 4
ret void ret void
} }
; CHECK-LABEL: atomic_store_release_32_off: ; CHECK-LABEL: atomic_store_release_32_off:
; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #4 ; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #4
; CHECK-NEXT: stlr w1, {{\[}}[[REG0]]] ; CHECK-NEXT: stlr w1, [[[REG0]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @atomic_store_release_32_off(i32* %p, i32 %val) #0 { define void @atomic_store_release_32_off(i32* %p, i32 %val) #0 {
%tmp0 = getelementptr i32, i32* %p, i32 1 %tmp0 = getelementptr i32, i32* %p, i32 1
store atomic i32 %val, i32* %tmp0 release, align 4 store atomic i32 %val, i32* %tmp0 release, align 4
ret void ret void
} }
; CHECK-LABEL: atomic_store_release_64: ; CHECK-LABEL: atomic_store_release_64:
; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlr x1, [x0] ; CHECK-NEXT: stlr x1, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @atomic_store_release_64(i64* %p, i64 %val) #0 { define void @atomic_store_release_64(i64* %p, i64 %val) #0 {
store atomic i64 %val, i64* %p release, align 8 store atomic i64 %val, i64* %p release, align 8
ret void ret void
} }
; CHECK-LABEL: atomic_store_release_64_off: ; CHECK-LABEL: atomic_store_release_64_off:
; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #8 ; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #8
; CHECK-NEXT: stlr x1, {{\[}}[[REG0]]] ; CHECK-NEXT: stlr x1, [[[REG0]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @atomic_store_release_64_off(i64* %p, i64 %val) #0 { define void @atomic_store_release_64_off(i64* %p, i64 %val) #0 {
%tmp0 = getelementptr i64, i64* %p, i32 1 %tmp0 = getelementptr i64, i64* %p, i32 1
store atomic i64 %val, i64* %tmp0 release, align 8 store atomic i64 %val, i64* %tmp0 release, align 8
ret void ret void
} }
; CHECK-LABEL: atomic_store_seq_cst_8: ; CHECK-LABEL: atomic_store_seq_cst_8:
; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlrb w1, [x0] ; CHECK-NEXT: stlrb w1, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @atomic_store_seq_cst_8(i8* %p, i8 %val) #0 { define void @atomic_store_seq_cst_8(i8* %p, i8 %val) #0 {
store atomic i8 %val, i8* %p seq_cst, align 1 store atomic i8 %val, i8* %p seq_cst, align 1
ret void ret void
} }
; CHECK-LABEL: atomic_store_seq_cst_8_off: ; CHECK-LABEL: atomic_store_seq_cst_8_off:
; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #1 ; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #1
; CHECK-NEXT: stlrb w1, {{\[}}[[REG0]]] ; CHECK-NEXT: stlrb w1, [[[REG0]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @atomic_store_seq_cst_8_off(i8* %p, i8 %val) #0 { define void @atomic_store_seq_cst_8_off(i8* %p, i8 %val) #0 {
%tmp0 = getelementptr i8, i8* %p, i32 1 %tmp0 = getelementptr i8, i8* %p, i32 1
store atomic i8 %val, i8* %tmp0 seq_cst, align 1 store atomic i8 %val, i8* %tmp0 seq_cst, align 1
ret void ret void
} }
; CHECK-LABEL: atomic_store_seq_cst_16: ; CHECK-LABEL: atomic_store_seq_cst_16:
; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlrh w1, [x0] ; CHECK-NEXT: stlrh w1, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @atomic_store_seq_cst_16(i16* %p, i16 %val) #0 { define void @atomic_store_seq_cst_16(i16* %p, i16 %val) #0 {
store atomic i16 %val, i16* %p seq_cst, align 2 store atomic i16 %val, i16* %p seq_cst, align 2
ret void ret void
} }
; CHECK-LABEL: atomic_store_seq_cst_16_off: ; CHECK-LABEL: atomic_store_seq_cst_16_off:
; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #2 ; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #2
; CHECK-NEXT: stlrh w1, {{\[}}[[REG0]]] ; CHECK-NEXT: stlrh w1, [[[REG0]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @atomic_store_seq_cst_16_off(i16* %p, i16 %val) #0 { define void @atomic_store_seq_cst_16_off(i16* %p, i16 %val) #0 {
%tmp0 = getelementptr i16, i16* %p, i32 1 %tmp0 = getelementptr i16, i16* %p, i32 1
store atomic i16 %val, i16* %tmp0 seq_cst, align 2 store atomic i16 %val, i16* %tmp0 seq_cst, align 2
ret void ret void
} }
; CHECK-LABEL: atomic_store_seq_cst_32: ; CHECK-LABEL: atomic_store_seq_cst_32:
; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlr w1, [x0] ; CHECK-NEXT: stlr w1, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @atomic_store_seq_cst_32(i32* %p, i32 %val) #0 { define void @atomic_store_seq_cst_32(i32* %p, i32 %val) #0 {
store atomic i32 %val, i32* %p seq_cst, align 4 store atomic i32 %val, i32* %p seq_cst, align 4
ret void ret void
} }
; CHECK-LABEL: atomic_store_seq_cst_32_off: ; CHECK-LABEL: atomic_store_seq_cst_32_off:
; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #4 ; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #4
; CHECK-NEXT: stlr w1, {{\[}}[[REG0]]] ; CHECK-NEXT: stlr w1, [[[REG0]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @atomic_store_seq_cst_32_off(i32* %p, i32 %val) #0 { define void @atomic_store_seq_cst_32_off(i32* %p, i32 %val) #0 {
%tmp0 = getelementptr i32, i32* %p, i32 1 %tmp0 = getelementptr i32, i32* %p, i32 1
store atomic i32 %val, i32* %tmp0 seq_cst, align 4 store atomic i32 %val, i32* %tmp0 seq_cst, align 4
ret void ret void
} }
; CHECK-LABEL: atomic_store_seq_cst_64: ; CHECK-LABEL: atomic_store_seq_cst_64:
; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlr x1, [x0] ; CHECK-NEXT: stlr x1, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @atomic_store_seq_cst_64(i64* %p, i64 %val) #0 { define void @atomic_store_seq_cst_64(i64* %p, i64 %val) #0 {
store atomic i64 %val, i64* %p seq_cst, align 8 store atomic i64 %val, i64* %p seq_cst, align 8
ret void ret void
} }
; CHECK-LABEL: atomic_store_seq_cst_64_off: ; CHECK-LABEL: atomic_store_seq_cst_64_off:
; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #8 ; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #8
; CHECK-NEXT: stlr x1, {{\[}}[[REG0]]] ; CHECK-NEXT: stlr x1, [[[REG0]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @atomic_store_seq_cst_64_off(i64* %p, i64 %val) #0 { define void @atomic_store_seq_cst_64_off(i64* %p, i64 %val) #0 {
%tmp0 = getelementptr i64, i64* %p, i32 1 %tmp0 = getelementptr i64, i64* %p, i32 1
store atomic i64 %val, i64* %tmp0 seq_cst, align 8 store atomic i64 %val, i64* %tmp0 seq_cst, align 8
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/AArch64/fast-isel-branch-cond-mask.ll

; RUN: llc -mtriple=aarch64-apple-darwin -O0 -fast-isel -fast-isel-abort=0 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -O0 -fast-isel -fast-isel-abort=0 -verify-machineinstrs < %s | FileCheck %s
define void @test(i64 %a, i64 %b, i2* %c) { define void @test(i64 %a, i64 %b, i2* %c) {
; CHECK-LABEL: test ; CHECK-LABEL: test
; CHECK: and [[REG1:w[0-9]+]], {{w[0-9]+}}, #0x3 ; CHECK: and [[REG1:w[0-9]+]], {{w[0-9]+}}, #0x3
; CHECK-NEXT: strb [[REG1]], {{\[}}x2{{\]}} ; CHECK-NEXT: strb [[REG1]], [x2]
; CHECK-NEXT: tbz {{w[0-9]+}}, #0, ; CHECK-NEXT: tbz {{w[0-9]+}}, #0,
%1 = trunc i64 %a to i2 %1 = trunc i64 %a to i2
%2 = trunc i64 %b to i1 %2 = trunc i64 %b to i1
; Force fast-isel to fall back to SDAG. ; Force fast-isel to fall back to SDAG.
store i2 %1, i2* %c, align 8 store i2 %1, i2* %c, align 8
br i1 %2, label %bb1, label %bb2 br i1 %2, label %bb1, label %bb2
bb1: bb1:
ret void ret void
bb2: bb2:
ret void ret void
} }

llvm/test/CodeGen/AArch64/fast-isel-cmpxchg.ll

; RUN: llc -mtriple=aarch64-- -O0 -fast-isel -fast-isel-abort=4 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-- -O0 -fast-isel -fast-isel-abort=4 -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: cmpxchg_monotonic_32: ; CHECK-LABEL: cmpxchg_monotonic_32:
; CHECK: mov [[ADDR:x[0-9]+]], x0 ; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: [[RETRY:.LBB[0-9_]+]]: ; CHECK: [[RETRY:.LBB[0-9_]+]]:
; CHECK-NEXT: ldaxr w0, {{\[}}[[ADDR]]{{\]}} ; CHECK-NEXT: ldaxr w0, [[[ADDR]]]
; CHECK-NEXT: cmp w0, w1 ; CHECK-NEXT: cmp w0, w1
; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]] ; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]]
; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: // %bb.2:
; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], w2, {{\[}}[[ADDR]]{{\]}} ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], w2, [[[ADDR]]]
; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]] ; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]]
; CHECK-NEXT: [[DONE]]: ; CHECK-NEXT: [[DONE]]:
; CHECK-NEXT: cmp w0, w1 ; CHECK-NEXT: cmp w0, w1
; CHECK-NEXT: cset [[STATUS]], eq ; CHECK-NEXT: cset [[STATUS]], eq
; CHECK-NEXT: and [[STATUS32:w[0-9]+]], [[STATUS]], #0x1 ; CHECK-NEXT: and [[STATUS32:w[0-9]+]], [[STATUS]], #0x1
; CHECK-NEXT: str [[STATUS32]], [x3] ; CHECK-NEXT: str [[STATUS32]], [x3]
define i32 @cmpxchg_monotonic_32(i32* %p, i32 %cmp, i32 %new, i32* %ps) #0 { define i32 @cmpxchg_monotonic_32(i32* %p, i32 %cmp, i32 %new, i32* %ps) #0 {
%tmp0 = cmpxchg i32* %p, i32 %cmp, i32 %new monotonic monotonic %tmp0 = cmpxchg i32* %p, i32 %cmp, i32 %new monotonic monotonic
%tmp1 = extractvalue { i32, i1 } %tmp0, 0 %tmp1 = extractvalue { i32, i1 } %tmp0, 0
%tmp2 = extractvalue { i32, i1 } %tmp0, 1 %tmp2 = extractvalue { i32, i1 } %tmp0, 1
%tmp3 = zext i1 %tmp2 to i32 %tmp3 = zext i1 %tmp2 to i32
store i32 %tmp3, i32* %ps store i32 %tmp3, i32* %ps
ret i32 %tmp1 ret i32 %tmp1
} }
; CHECK-LABEL: cmpxchg_acq_rel_32_load: ; CHECK-LABEL: cmpxchg_acq_rel_32_load:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK: mov [[ADDR:x[0-9]+]], x0 ; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: ldr [[NEW:w[0-9]+]], [x2] ; CHECK: ldr [[NEW:w[0-9]+]], [x2]
; CHECK-NEXT: [[RETRY:.LBB[0-9_]+]]: ; CHECK-NEXT: [[RETRY:.LBB[0-9_]+]]:
; CHECK-NEXT: ldaxr w0, {{\[}}[[ADDR]]{{\]}} ; CHECK-NEXT: ldaxr w0, [[[ADDR]]]
; CHECK-NEXT: cmp w0, w1 ; CHECK-NEXT: cmp w0, w1
; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]] ; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]]
; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: // %bb.2:
; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], {{\[}}[[ADDR]]{{\]}} ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [[[ADDR]]]
; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]] ; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]]
; CHECK-NEXT: [[DONE]]: ; CHECK-NEXT: [[DONE]]:
; CHECK-NEXT: cmp w0, w1 ; CHECK-NEXT: cmp w0, w1
; CHECK-NEXT: cset [[STATUS]], eq ; CHECK-NEXT: cset [[STATUS]], eq
; CHECK-NEXT: and [[STATUS32:w[0-9]+]], [[STATUS]], #0x1 ; CHECK-NEXT: and [[STATUS32:w[0-9]+]], [[STATUS]], #0x1
; CHECK-NEXT: str [[STATUS32]], [x3] ; CHECK-NEXT: str [[STATUS32]], [x3]
define i32 @cmpxchg_acq_rel_32_load(i32* %p, i32 %cmp, i32* %pnew, i32* %ps) #0 { define i32 @cmpxchg_acq_rel_32_load(i32* %p, i32 %cmp, i32* %pnew, i32* %ps) #0 {
%new = load i32, i32* %pnew %new = load i32, i32* %pnew
%tmp0 = cmpxchg i32* %p, i32 %cmp, i32 %new acq_rel acquire %tmp0 = cmpxchg i32* %p, i32 %cmp, i32 %new acq_rel acquire
%tmp1 = extractvalue { i32, i1 } %tmp0, 0 %tmp1 = extractvalue { i32, i1 } %tmp0, 0
%tmp2 = extractvalue { i32, i1 } %tmp0, 1 %tmp2 = extractvalue { i32, i1 } %tmp0, 1
%tmp3 = zext i1 %tmp2 to i32 %tmp3 = zext i1 %tmp2 to i32
store i32 %tmp3, i32* %ps store i32 %tmp3, i32* %ps
ret i32 %tmp1 ret i32 %tmp1
} }
; CHECK-LABEL: cmpxchg_seq_cst_64: ; CHECK-LABEL: cmpxchg_seq_cst_64:
; CHECK: mov [[ADDR:x[0-9]+]], x0 ; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: [[RETRY:.LBB[0-9_]+]]: ; CHECK: [[RETRY:.LBB[0-9_]+]]:
; CHECK-NEXT: ldaxr x0, {{\[}}[[ADDR]]{{\]}} ; CHECK-NEXT: ldaxr x0, [[[ADDR]]]
; CHECK-NEXT: cmp x0, x1 ; CHECK-NEXT: cmp x0, x1
; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]] ; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]]
; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: // %bb.2:
; CHECK-NEXT: stlxr [[STATUS]], x2, {{\[}}[[ADDR]]{{\]}} ; CHECK-NEXT: stlxr [[STATUS]], x2, [[[ADDR]]]
; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]] ; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]]
; CHECK-NEXT: [[DONE]]: ; CHECK-NEXT: [[DONE]]:
; CHECK-NEXT: cmp x0, x1 ; CHECK-NEXT: cmp x0, x1
; CHECK-NEXT: cset [[STATUS:w[0-9]+]], eq ; CHECK-NEXT: cset [[STATUS:w[0-9]+]], eq
; CHECK-NEXT: and [[STATUS32:w[0-9]+]], [[STATUS]], #0x1 ; CHECK-NEXT: and [[STATUS32:w[0-9]+]], [[STATUS]], #0x1
; CHECK-NEXT: str [[STATUS32]], [x3] ; CHECK-NEXT: str [[STATUS32]], [x3]
define i64 @cmpxchg_seq_cst_64(i64* %p, i64 %cmp, i64 %new, i32* %ps) #0 { define i64 @cmpxchg_seq_cst_64(i64* %p, i64 %cmp, i64 %new, i32* %ps) #0 {
%tmp0 = cmpxchg i64* %p, i64 %cmp, i64 %new seq_cst seq_cst %tmp0 = cmpxchg i64* %p, i64 %cmp, i64 %new seq_cst seq_cst
%tmp1 = extractvalue { i64, i1 } %tmp0, 0 %tmp1 = extractvalue { i64, i1 } %tmp0, 0
%tmp2 = extractvalue { i64, i1 } %tmp0, 1 %tmp2 = extractvalue { i64, i1 } %tmp0, 1
%tmp3 = zext i1 %tmp2 to i32 %tmp3 = zext i1 %tmp2 to i32
store i32 %tmp3, i32* %ps store i32 %tmp3, i32* %ps
ret i64 %tmp1 ret i64 %tmp1
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/AArch64/fast-isel-runtime-libcall.ll

; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -code-model=small -verify-machineinstrs < %s | FileCheck %s --check-prefix=SMALL ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -code-model=small -verify-machineinstrs < %s | FileCheck %s --check-prefix=SMALL
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -code-model=large -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -code-model=large -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE
define float @frem_f32(float %a, float %b) { define float @frem_f32(float %a, float %b) {
; SMALL-LABEL: frem_f32 ; SMALL-LABEL: frem_f32
; SMALL: bl _fmodf ; SMALL: bl _fmodf
; LARGE-LABEL: frem_f32 ; LARGE-LABEL: frem_f32
; LARGE: adrp [[REG:x[0-9]+]], _fmodf@GOTPAGE ; LARGE: adrp [[REG:x[0-9]+]], _fmodf@GOTPAGE
; LARGE: ldr [[REG]], {{\[}}[[REG]], _fmodf@GOTPAGEOFF{{\]}} ; LARGE: ldr [[REG]], [[[REG]], _fmodf@GOTPAGEOFF]
; LARGE-NEXT: blr [[REG]] ; LARGE-NEXT: blr [[REG]]
%1 = frem float %a, %b %1 = frem float %a, %b
ret float %1 ret float %1
} }
define double @frem_f64(double %a, double %b) { define double @frem_f64(double %a, double %b) {
; SMALL-LABEL: frem_f64 ; SMALL-LABEL: frem_f64
; SMALL: bl _fmod ; SMALL: bl _fmod
; LARGE-LABEL: frem_f64 ; LARGE-LABEL: frem_f64
; LARGE: adrp [[REG:x[0-9]+]], _fmod@GOTPAGE ; LARGE: adrp [[REG:x[0-9]+]], _fmod@GOTPAGE
; LARGE: ldr [[REG]], {{\[}}[[REG]], _fmod@GOTPAGEOFF{{\]}} ; LARGE: ldr [[REG]], [[[REG]], _fmod@GOTPAGEOFF]
; LARGE-NEXT: blr [[REG]] ; LARGE-NEXT: blr [[REG]]
%1 = frem double %a, %b %1 = frem double %a, %b
ret double %1 ret double %1
} }
define float @sin_f32(float %a) { define float @sin_f32(float %a) {
; SMALL-LABEL: sin_f32 ; SMALL-LABEL: sin_f32
; SMALL: bl _sinf ; SMALL: bl _sinf
; LARGE-LABEL: sin_f32 ; LARGE-LABEL: sin_f32
; LARGE: adrp [[REG:x[0-9]+]], _sinf@GOTPAGE ; LARGE: adrp [[REG:x[0-9]+]], _sinf@GOTPAGE
; LARGE: ldr [[REG]], {{\[}}[[REG]], _sinf@GOTPAGEOFF{{\]}} ; LARGE: ldr [[REG]], [[[REG]], _sinf@GOTPAGEOFF]
; LARGE-NEXT: blr [[REG]] ; LARGE-NEXT: blr [[REG]]
%1 = call float @llvm.sin.f32(float %a) %1 = call float @llvm.sin.f32(float %a)
ret float %1 ret float %1
} }
define double @sin_f64(double %a) { define double @sin_f64(double %a) {
; SMALL-LABEL: sin_f64 ; SMALL-LABEL: sin_f64
; SMALL: bl _sin ; SMALL: bl _sin
; LARGE-LABEL: sin_f64 ; LARGE-LABEL: sin_f64
; LARGE: adrp [[REG:x[0-9]+]], _sin@GOTPAGE ; LARGE: adrp [[REG:x[0-9]+]], _sin@GOTPAGE
; LARGE: ldr [[REG]], {{\[}}[[REG]], _sin@GOTPAGEOFF{{\]}} ; LARGE: ldr [[REG]], [[[REG]], _sin@GOTPAGEOFF]
; LARGE-NEXT: blr [[REG]] ; LARGE-NEXT: blr [[REG]]
%1 = call double @llvm.sin.f64(double %a) %1 = call double @llvm.sin.f64(double %a)
ret double %1 ret double %1
} }
define float @cos_f32(float %a) { define float @cos_f32(float %a) {
; SMALL-LABEL: cos_f32 ; SMALL-LABEL: cos_f32
; SMALL: bl _cosf ; SMALL: bl _cosf
; LARGE-LABEL: cos_f32 ; LARGE-LABEL: cos_f32
; LARGE: adrp [[REG:x[0-9]+]], _cosf@GOTPAGE ; LARGE: adrp [[REG:x[0-9]+]], _cosf@GOTPAGE
; LARGE: ldr [[REG]], {{\[}}[[REG]], _cosf@GOTPAGEOFF{{\]}} ; LARGE: ldr [[REG]], [[[REG]], _cosf@GOTPAGEOFF]
; LARGE-NEXT: blr [[REG]] ; LARGE-NEXT: blr [[REG]]
%1 = call float @llvm.cos.f32(float %a) %1 = call float @llvm.cos.f32(float %a)
ret float %1 ret float %1
} }
define double @cos_f64(double %a) { define double @cos_f64(double %a) {
; SMALL-LABEL: cos_f64 ; SMALL-LABEL: cos_f64
; SMALL: bl _cos ; SMALL: bl _cos
; LARGE-LABEL: cos_f64 ; LARGE-LABEL: cos_f64
; LARGE: adrp [[REG:x[0-9]+]], _cos@GOTPAGE ; LARGE: adrp [[REG:x[0-9]+]], _cos@GOTPAGE
; LARGE: ldr [[REG]], {{\[}}[[REG]], _cos@GOTPAGEOFF{{\]}} ; LARGE: ldr [[REG]], [[[REG]], _cos@GOTPAGEOFF]
; LARGE-NEXT: blr [[REG]] ; LARGE-NEXT: blr [[REG]]
%1 = call double @llvm.cos.f64(double %a) %1 = call double @llvm.cos.f64(double %a)
ret double %1 ret double %1
} }
define float @pow_f32(float %a, float %b) { define float @pow_f32(float %a, float %b) {
; SMALL-LABEL: pow_f32 ; SMALL-LABEL: pow_f32
; SMALL: bl _powf ; SMALL: bl _powf
; LARGE-LABEL: pow_f32 ; LARGE-LABEL: pow_f32
; LARGE: adrp [[REG:x[0-9]+]], _powf@GOTPAGE ; LARGE: adrp [[REG:x[0-9]+]], _powf@GOTPAGE
; LARGE: ldr [[REG]], {{\[}}[[REG]], _powf@GOTPAGEOFF{{\]}} ; LARGE: ldr [[REG]], [[[REG]], _powf@GOTPAGEOFF]
; LARGE-NEXT: blr [[REG]] ; LARGE-NEXT: blr [[REG]]
%1 = call float @llvm.pow.f32(float %a, float %b) %1 = call float @llvm.pow.f32(float %a, float %b)
ret float %1 ret float %1
} }
define double @pow_f64(double %a, double %b) { define double @pow_f64(double %a, double %b) {
; SMALL-LABEL: pow_f64 ; SMALL-LABEL: pow_f64
; SMALL: bl _pow ; SMALL: bl _pow
; LARGE-LABEL: pow_f64 ; LARGE-LABEL: pow_f64
; LARGE: adrp [[REG:x[0-9]+]], _pow@GOTPAGE ; LARGE: adrp [[REG:x[0-9]+]], _pow@GOTPAGE
; LARGE: ldr [[REG]], {{\[}}[[REG]], _pow@GOTPAGEOFF{{\]}} ; LARGE: ldr [[REG]], [[[REG]], _pow@GOTPAGEOFF]
; LARGE-NEXT: blr [[REG]] ; LARGE-NEXT: blr [[REG]]
%1 = call double @llvm.pow.f64(double %a, double %b) %1 = call double @llvm.pow.f64(double %a, double %b)
ret double %1 ret double %1
} }
declare float @llvm.sin.f32(float) declare float @llvm.sin.f32(float)
declare double @llvm.sin.f64(double) declare double @llvm.sin.f64(double)
declare float @llvm.cos.f32(float) declare float @llvm.cos.f32(float)
declare double @llvm.cos.f64(double) declare double @llvm.cos.f64(double)
declare float @llvm.pow.f32(float, float) declare float @llvm.pow.f32(float, float)
declare double @llvm.pow.f64(double, double) declare double @llvm.pow.f64(double, double)

llvm/test/CodeGen/AArch64/misched-fusion-addr-tune.ll

Show All 9 Linesdefine dso_local void @ldst_double() {
%vald = load volatile double, double* @var_double %vald = load volatile double, double* @var_double
%vald1 = insertelement <2 x double> undef, double %vald, i32 0 %vald1 = insertelement <2 x double> undef, double %vald, i32 0
%vald2 = insertelement <2 x double> %vald1, double %vale, i32 1 %vald2 = insertelement <2 x double> %vald1, double %vale, i32 1
store volatile <2 x double> %vald2, <2 x double>* @var_double2 store volatile <2 x double> %vald2, <2 x double>* @var_double2
ret void ret void
; CHECK-LABEL: ldst_double: ; CHECK-LABEL: ldst_double:
; CHECK: adrp [[RD:x[0-9]+]], var_double ; CHECK: adrp [[RD:x[0-9]+]], var_double
; CHECK-NEXT: ldr {{d[0-9]+}}, {{\[}}[[RD]], {{#?}}:lo12:var_double{{\]}} ; CHECK-NEXT: ldr {{d[0-9]+}}, [[[RD]], {{#?}}:lo12:var_double]
; CHECK: adrp [[RQ:x[0-9]+]], var_double2 ; CHECK: adrp [[RQ:x[0-9]+]], var_double2
; CHECK-NEXT: str {{q[0-9]+}}, {{\[}}[[RQ]], {{#?}}:lo12:var_double2{{\]}} ; CHECK-NEXT: str {{q[0-9]+}}, [[[RQ]], {{#?}}:lo12:var_double2]
} }
define dso_local void @ldst_double_tune_a53() #0 { define dso_local void @ldst_double_tune_a53() #0 {
%valf = load volatile float, float* @var_float %valf = load volatile float, float* @var_float
%vale = fpext float %valf to double %vale = fpext float %valf to double
%vald = load volatile double, double* @var_double %vald = load volatile double, double* @var_double
%vald1 = insertelement <2 x double> undef, double %vald, i32 0 %vald1 = insertelement <2 x double> undef, double %vald, i32 0
%vald2 = insertelement <2 x double> %vald1, double %vale, i32 1 %vald2 = insertelement <2 x double> %vald1, double %vale, i32 1
store volatile <2 x double> %vald2, <2 x double>* @var_double2 store volatile <2 x double> %vald2, <2 x double>* @var_double2
ret void ret void
; CHECK-LABEL: ldst_double_tune_a53: ; CHECK-LABEL: ldst_double_tune_a53:
; CHECK: adrp [[RD:x[0-9]+]], var_double ; CHECK: adrp [[RD:x[0-9]+]], var_double
; CHECK-NEXT: ldr {{d[0-9]+}}, {{\[}}[[RD]], {{#?}}:lo12:var_double{{\]}} ; CHECK-NEXT: ldr {{d[0-9]+}}, [[[RD]], {{#?}}:lo12:var_double]
; CHECK-NEXT: adrp [[RQ:x[0-9]+]], var_double2 ; CHECK-NEXT: adrp [[RQ:x[0-9]+]], var_double2
; CHECK: fcvt ; CHECK: fcvt
; CHECK: str {{q[0-9]+}}, {{\[}}[[RQ]], {{#?}}:lo12:var_double2{{\]}} ; CHECK: str {{q[0-9]+}}, [[[RQ]], {{#?}}:lo12:var_double2]
} }
attributes #0 = { "tune-cpu"="cortex-a53" } attributes #0 = { "tune-cpu"="cortex-a53" }

llvm/test/CodeGen/AArch64/misched-fusion-addr.ll

Show All 20 Linesdefine dso_local void @ldst_8bit() {
%ext = zext i8 %val8 to i64 %ext = zext i8 %val8 to i64
%add = add i64 %ext, 1 %add = add i64 %ext, 1
%val16 = trunc i64 %add to i16 %val16 = trunc i64 %add to i16
store volatile i16 %val16, i16* @var_16bit store volatile i16 %val16, i16* @var_16bit
ret void ret void
; CHECK-LABEL: ldst_8bit: ; CHECK-LABEL: ldst_8bit:
; CHECK: adrp [[RB:x[0-9]+]], var_8bit ; CHECK: adrp [[RB:x[0-9]+]], var_8bit
; CHECK-NEXT: ldrb {{w[0-9]+}}, {{\[}}[[RB]], {{#?}}:lo12:var_8bit{{\]}} ; CHECK-NEXT: ldrb {{w[0-9]+}}, [[[RB]], {{#?}}:lo12:var_8bit]
; CHECK: adrp [[RH:x[0-9]+]], var_16bit ; CHECK: adrp [[RH:x[0-9]+]], var_16bit
; CHECK-NEXT: strh {{w[0-9]+}}, {{\[}}[[RH]], {{#?}}:lo12:var_16bit{{\]}} ; CHECK-NEXT: strh {{w[0-9]+}}, [[[RH]], {{#?}}:lo12:var_16bit]
} }
define dso_local void @ldst_16bit() { define dso_local void @ldst_16bit() {
%val16 = load volatile i16, i16* @var_16bit %val16 = load volatile i16, i16* @var_16bit
%ext = zext i16 %val16 to i64 %ext = zext i16 %val16 to i64
%add = add i64 %ext, 1 %add = add i64 %ext, 1
%val32 = trunc i64 %add to i32 %val32 = trunc i64 %add to i32
store volatile i32 %val32, i32* @var_32bit store volatile i32 %val32, i32* @var_32bit
ret void ret void
; CHECK-LABEL: ldst_16bit: ; CHECK-LABEL: ldst_16bit:
; CHECK: adrp [[RH:x[0-9]+]], var_16bit ; CHECK: adrp [[RH:x[0-9]+]], var_16bit
; CHECK-NEXT: ldrh {{w[0-9]+}}, {{\[}}[[RH]], {{#?}}:lo12:var_16bit{{\]}} ; CHECK-NEXT: ldrh {{w[0-9]+}}, [[[RH]], {{#?}}:lo12:var_16bit]
; CHECK: adrp [[RW:x[0-9]+]], var_32bit ; CHECK: adrp [[RW:x[0-9]+]], var_32bit
; CHECK-NEXT: str {{w[0-9]+}}, {{\[}}[[RW]], {{#?}}:lo12:var_32bit{{\]}} ; CHECK-NEXT: str {{w[0-9]+}}, [[[RW]], {{#?}}:lo12:var_32bit]
} }
define dso_local void @ldst_32bit() { define dso_local void @ldst_32bit() {
%val32 = load volatile i32, i32* @var_32bit %val32 = load volatile i32, i32* @var_32bit
%ext = zext i32 %val32 to i64 %ext = zext i32 %val32 to i64
%val64 = add i64 %ext, 1 %val64 = add i64 %ext, 1
store volatile i64 %val64, i64* @var_64bit store volatile i64 %val64, i64* @var_64bit
ret void ret void
; CHECK-LABEL: ldst_32bit: ; CHECK-LABEL: ldst_32bit:
; CHECK: adrp [[RW:x[0-9]+]], var_32bit ; CHECK: adrp [[RW:x[0-9]+]], var_32bit
; CHECK-NEXT: ldr {{w[0-9]+}}, {{\[}}[[RW]], {{#?}}:lo12:var_32bit{{\]}} ; CHECK-NEXT: ldr {{w[0-9]+}}, [[[RW]], {{#?}}:lo12:var_32bit]
; CHECK: adrp [[RL:x[0-9]+]], var_64bit ; CHECK: adrp [[RL:x[0-9]+]], var_64bit
; CHECK-NEXT: str {{x[0-9]+}}, {{\[}}[[RL]], {{#?}}:lo12:var_64bit{{\]}} ; CHECK-NEXT: str {{x[0-9]+}}, [[[RL]], {{#?}}:lo12:var_64bit]
} }
define dso_local void @ldst_64bit() { define dso_local void @ldst_64bit() {
%val64 = load volatile i64, i64* @var_64bit %val64 = load volatile i64, i64* @var_64bit
%ext = zext i64 %val64 to i128 %ext = zext i64 %val64 to i128
%val128 = add i128 %ext, 1 %val128 = add i128 %ext, 1
store volatile i128 %val128, i128* @var_128bit store volatile i128 %val128, i128* @var_128bit
ret void ret void
; CHECK-LABEL: ldst_64bit: ; CHECK-LABEL: ldst_64bit:
; CHECK: adrp [[RL:x[0-9]+]], var_64bit ; CHECK: adrp [[RL:x[0-9]+]], var_64bit
; CHECK-NEXT: ldr {{x[0-9]+}}, {{\[}}[[RL]], {{#?}}:lo12:var_64bit{{\]}} ; CHECK-NEXT: ldr {{x[0-9]+}}, [[[RL]], {{#?}}:lo12:var_64bit]
; CHECK: adrp [[RQ:x[0-9]+]], var_128bit ; CHECK: adrp [[RQ:x[0-9]+]], var_128bit
; CHECK-NEXT: add {{x[0-9]+}}, [[RQ]], {{#?}}:lo12:var_128bit ; CHECK-NEXT: add {{x[0-9]+}}, [[RQ]], {{#?}}:lo12:var_128bit
} }
define dso_local void @ldst_half() { define dso_local void @ldst_half() {
%valh = load volatile half, half* @var_half %valh = load volatile half, half* @var_half
%valf = fpext half %valh to float %valf = fpext half %valh to float
store volatile float %valf, float* @var_float store volatile float %valf, float* @var_float
ret void ret void
; CHECK-LABEL: ldst_half: ; CHECK-LABEL: ldst_half:
; CHECK: adrp [[RH:x[0-9]+]], var_half ; CHECK: adrp [[RH:x[0-9]+]], var_half
; CHECK-NEXT: ldr {{h[0-9]+}}, {{\[}}[[RH]], {{#?}}:lo12:var_half{{\]}} ; CHECK-NEXT: ldr {{h[0-9]+}}, [[[RH]], {{#?}}:lo12:var_half]
; CHECK: adrp [[RF:x[0-9]+]], var_float ; CHECK: adrp [[RF:x[0-9]+]], var_float
; CHECK-NEXT: str {{s[0-9]+}}, {{\[}}[[RF]], {{#?}}:lo12:var_float{{\]}} ; CHECK-NEXT: str {{s[0-9]+}}, [[[RF]], {{#?}}:lo12:var_float]
} }
define dso_local void @ldst_float() { define dso_local void @ldst_float() {
%valf = load volatile float, float* @var_float %valf = load volatile float, float* @var_float
%vald = fpext float %valf to double %vald = fpext float %valf to double
store volatile double %vald, double* @var_double store volatile double %vald, double* @var_double
ret void ret void
; CHECK-LABEL: ldst_float: ; CHECK-LABEL: ldst_float:
; CHECK: adrp [[RF:x[0-9]+]], var_float ; CHECK: adrp [[RF:x[0-9]+]], var_float
; CHECK-NEXT: ldr {{s[0-9]+}}, {{\[}}[[RF]], {{#?}}:lo12:var_float{{\]}} ; CHECK-NEXT: ldr {{s[0-9]+}}, [[[RF]], {{#?}}:lo12:var_float]
; CHECK: adrp [[RD:x[0-9]+]], var_double ; CHECK: adrp [[RD:x[0-9]+]], var_double
; CHECK-NEXT: str {{d[0-9]+}}, {{\[}}[[RD]], {{#?}}:lo12:var_double{{\]}} ; CHECK-NEXT: str {{d[0-9]+}}, [[[RD]], {{#?}}:lo12:var_double]
} }
define dso_local void @ldst_double() { define dso_local void @ldst_double() {
%valf = load volatile float, float* @var_float %valf = load volatile float, float* @var_float
%vale = fpext float %valf to double %vale = fpext float %valf to double
%vald = load volatile double, double* @var_double %vald = load volatile double, double* @var_double
%vald1 = insertelement <2 x double> undef, double %vald, i32 0 %vald1 = insertelement <2 x double> undef, double %vald, i32 0
%vald2 = insertelement <2 x double> %vald1, double %vale, i32 1 %vald2 = insertelement <2 x double> %vald1, double %vale, i32 1
store volatile <2 x double> %vald2, <2 x double>* @var_double2 store volatile <2 x double> %vald2, <2 x double>* @var_double2
ret void ret void
; CHECK-LABEL: ldst_double: ; CHECK-LABEL: ldst_double:
; CHECK: adrp [[RD:x[0-9]+]], var_double ; CHECK: adrp [[RD:x[0-9]+]], var_double
; CHECK-NEXT: ldr {{d[0-9]+}}, {{\[}}[[RD]], {{#?}}:lo12:var_double{{\]}} ; CHECK-NEXT: ldr {{d[0-9]+}}, [[[RD]], {{#?}}:lo12:var_double]
; CHECK: adrp [[RQ:x[0-9]+]], var_double2 ; CHECK: adrp [[RQ:x[0-9]+]], var_double2
; CHECK-NEXT: str {{q[0-9]+}}, {{\[}}[[RQ]], {{#?}}:lo12:var_double2{{\]}} ; CHECK-NEXT: str {{q[0-9]+}}, [[[RQ]], {{#?}}:lo12:var_double2]
} }

llvm/test/CodeGen/AArch64/stack-guard-reassign.ll

; RUN: llc -O0 --frame-pointer=all -mtriple=aarch64-- -o - %S/../Inputs/stack-guard-reassign.ll | FileCheck %s ; RUN: llc -O0 --frame-pointer=all -mtriple=aarch64-- -o - %S/../Inputs/stack-guard-reassign.ll | FileCheck %s
; Verify that the offset assigned to the stack protector is at the top of the ; Verify that the offset assigned to the stack protector is at the top of the
; frame, covering the locals. ; frame, covering the locals.
; CHECK-LABEL: fn: ; CHECK-LABEL: fn:
; CHECK: adrp [[REG:x[0-9]+]], __stack_chk_guard ; CHECK: adrp [[REG:x[0-9]+]], __stack_chk_guard
; CHECK-NEXT: ldr [[REG]], {{\[}}[[REG]], :lo12:__stack_chk_guard] ; CHECK-NEXT: ldr [[REG]], [[[REG]], :lo12:__stack_chk_guard]
; CHECK-NEXT: stur [[REG]], [x29, #-8] ; CHECK-NEXT: stur [[REG]], [x29, #-8]

llvm/test/CodeGen/AArch64/stack-guard-sve.ll

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; CHECK-LABEL: call_ptr_strong: ; CHECK-LABEL: call_ptr_strong:
; CHECK: mov x29, sp ; CHECK: mov x29, sp
; CHECK: addvl sp, sp, #-2 ; CHECK: addvl sp, sp, #-2
; CHECK-DAG: addvl [[ADDR:x[0-9]+]], x29, #-1 ; CHECK-DAG: addvl [[ADDR:x[0-9]+]], x29, #-1
; CHECK-DAG: ldr [[VAL:x[0-9]+]], [{{x[0-9]+}}, :lo12:__stack_chk_guard] ; CHECK-DAG: ldr [[VAL:x[0-9]+]], [{{x[0-9]+}}, :lo12:__stack_chk_guard]
; CHECK-DAG: str [[VAL]], {{\[}}[[ADDR]]] ; CHECK-DAG: str [[VAL]], [[[ADDR]]]
; CHECK-DAG: addvl x0, x29, #-2 ; CHECK-DAG: addvl x0, x29, #-2
; CHECK: bl ptr_fn ; CHECK: bl ptr_fn
define void @call_ptr_strong() #1 { define void @call_ptr_strong() #1 {
entry: entry:
%x = alloca <vscale x 4 x float>, align 16 %x = alloca <vscale x 4 x float>, align 16
call void @ptr_fn(<vscale x 4 x float>* %x) call void @ptr_fn(<vscale x 4 x float>* %x)
ret void ret void
} }
Show All 19 Linesentry:
ret void ret void
} }
; CHECK-LABEL: call_both_strong: ; CHECK-LABEL: call_both_strong:
; CHECK: mov x29, sp ; CHECK: mov x29, sp
; CHECK: addvl sp, sp, #-3 ; CHECK: addvl sp, sp, #-3
; CHECK-DAG: addvl [[ADDR:x[0-9]+]], x29, #-1 ; CHECK-DAG: addvl [[ADDR:x[0-9]+]], x29, #-1
; CHECK-DAG: ldr [[VAL:x[0-9]+]], [{{x[0-9]+}}, :lo12:__stack_chk_guard] ; CHECK-DAG: ldr [[VAL:x[0-9]+]], [{{x[0-9]+}}, :lo12:__stack_chk_guard]
; CHECK-DAG: str [[VAL]], {{\[}}[[ADDR]]] ; CHECK-DAG: str [[VAL]], [[[ADDR]]]
; CHECK-DAG: st1w { {{z[0-9]+.s}} }, {{p[0-9]+}}, [x29, #-2, mul vl] ; CHECK-DAG: st1w { {{z[0-9]+.s}} }, {{p[0-9]+}}, [x29, #-2, mul vl]
; CHECK: bl val_fn ; CHECK: bl val_fn
; CHECK: addvl x0, x29, #-3 ; CHECK: addvl x0, x29, #-3
; CHECK: bl ptr_fn ; CHECK: bl ptr_fn
define void @call_both_strong() #1 { define void @call_both_strong() #1 {
entry: entry:
%x = alloca <vscale x 4 x float>, align 16 %x = alloca <vscale x 4 x float>, align 16
%y = alloca <vscale x 4 x float>, align 16 %y = alloca <vscale x 4 x float>, align 16
Show All 9 Lines
; CHECK-LABEL: callee_save: ; CHECK-LABEL: callee_save:
; CHECK: mov x29, sp ; CHECK: mov x29, sp
; CHECK: addvl sp, sp, #-18 ; CHECK: addvl sp, sp, #-18
; CHECK: str {{z[0-9]+}}, [sp, #{{[0-9]+}}, mul vl] ; CHECK: str {{z[0-9]+}}, [sp, #{{[0-9]+}}, mul vl]
; CHECK-NOT: mov x29, sp ; CHECK-NOT: mov x29, sp
; CHECK: addvl sp, sp, #-1 ; CHECK: addvl sp, sp, #-1
; CHECK-NOT: __stack_chk_guard ; CHECK-NOT: __stack_chk_guard
; CHECK: addvl [[REG:x[0-9]+]], x29, #-11 ; CHECK: addvl [[REG:x[0-9]+]], x29, #-11
; CHECK: st1w { {{z[0-9]+.s}} }, {{p[0-9]+}}, {{\[}}[[REG]], #-8, mul vl] ; CHECK: st1w { {{z[0-9]+.s}} }, {{p[0-9]+}}, [[[REG]], #-8, mul vl]
define void @callee_save(<vscale x 4 x float> %x) #0 { define void @callee_save(<vscale x 4 x float> %x) #0 {
entry: entry:
%x.addr = alloca <vscale x 4 x float>, align 16 %x.addr = alloca <vscale x 4 x float>, align 16
store <vscale x 4 x float> %x, <vscale x 4 x float>* %x.addr, align 16 store <vscale x 4 x float> %x, <vscale x 4 x float>* %x.addr, align 16
call void @ptr_fn(<vscale x 4 x float>* %x.addr) call void @ptr_fn(<vscale x 4 x float>* %x.addr)
ret void ret void
} }
; CHECK-LABEL: callee_save_strong: ; CHECK-LABEL: callee_save_strong:
; CHECK: mov x29, sp ; CHECK: mov x29, sp
; CHECK: addvl sp, sp, #-18 ; CHECK: addvl sp, sp, #-18
; CHECK: str {{z[0-9]+}}, [sp, #{{[0-9]+}}, mul vl] ; CHECK: str {{z[0-9]+}}, [sp, #{{[0-9]+}}, mul vl]
; CHECK: addvl sp, sp, #-2 ; CHECK: addvl sp, sp, #-2
; CHECK-DAG: addvl [[ADDR:x[0-9]+]], x29, #-19 ; CHECK-DAG: addvl [[ADDR:x[0-9]+]], x29, #-19
; CHECK-DAG: ldr [[VAL:x[0-9]+]], [{{x[0-9]+}}, :lo12:__stack_chk_guard] ; CHECK-DAG: ldr [[VAL:x[0-9]+]], [{{x[0-9]+}}, :lo12:__stack_chk_guard]
; CHECK-DAG: str [[VAL]], {{\[}}[[ADDR]]] ; CHECK-DAG: str [[VAL]], [[[ADDR]]]
; CHECK-DAG: addvl [[ADDR2:x[0-9]+]], x29, #-12 ; CHECK-DAG: addvl [[ADDR2:x[0-9]+]], x29, #-12
; CHECK-DAG: st1w { z0.s }, p0, {{\[}}[[ADDR2]], #-8, mul vl] ; CHECK-DAG: st1w { z0.s }, p0, [[[ADDR2]], #-8, mul vl]
define void @callee_save_strong(<vscale x 4 x float> %x) #1 { define void @callee_save_strong(<vscale x 4 x float> %x) #1 {
entry: entry:
%x.addr = alloca <vscale x 4 x float>, align 16 %x.addr = alloca <vscale x 4 x float>, align 16
store <vscale x 4 x float> %x, <vscale x 4 x float>* %x.addr, align 16 store <vscale x 4 x float> %x, <vscale x 4 x float>* %x.addr, align 16
call void @ptr_fn(<vscale x 4 x float>* %x.addr) call void @ptr_fn(<vscale x 4 x float>* %x.addr)
ret void ret void
} }
; Check that local stack allocation works correctly both when we have a stack ; Check that local stack allocation works correctly both when we have a stack
; guard but no vulnerable SVE objects, and when we do have such objects. ; guard but no vulnerable SVE objects, and when we do have such objects.
; CHECK-LABEL: local_stack_alloc: ; CHECK-LABEL: local_stack_alloc:
; CHECK: mov x29, sp ; CHECK: mov x29, sp
; CHECK: addvl sp, sp, #-2 ; CHECK: addvl sp, sp, #-2
; CHECK: sub sp, sp, #16, lsl #12 ; CHECK: sub sp, sp, #16, lsl #12
; CHECK: sub sp, sp, #16 ; CHECK: sub sp, sp, #16
; Stack guard is placed below the SVE stack area ; Stack guard is placed below the SVE stack area
; CHECK-DAG: ldr [[STACK_GUARD:x[0-9]+]], [{{x[0-9]+}}, :lo12:__stack_chk_guard] ; CHECK-DAG: ldr [[STACK_GUARD:x[0-9]+]], [{{x[0-9]+}}, :lo12:__stack_chk_guard]
; CHECK-DAG: addvl [[STACK_GUARD_POS:x[0-9]+]], x29, #-2 ; CHECK-DAG: addvl [[STACK_GUARD_POS:x[0-9]+]], x29, #-2
; CHECK-DAG: stur [[STACK_GUARD]], {{\[}}[[STACK_GUARD_POS]], #-8] ; CHECK-DAG: stur [[STACK_GUARD]], [[[STACK_GUARD_POS]], #-8]
; char_arr is below the stack guard ; char_arr is below the stack guard
; CHECK-DAG: sub [[CHAR_ARR_1:x[0-9]+]], x29, #16 ; CHECK-DAG: sub [[CHAR_ARR_1:x[0-9]+]], x29, #16
; CHECK-DAG: addvl [[CHAR_ARR_2:x[0-9]+]], [[CHAR_ARR_1]], #-2 ; CHECK-DAG: addvl [[CHAR_ARR_2:x[0-9]+]], [[CHAR_ARR_1]], #-2
; CHECK-DAG: strb wzr, {{\[}}[[CHAR_ARR_2]]] ; CHECK-DAG: strb wzr, [[[CHAR_ARR_2]]]
; large1 is accessed via a virtual base register ; large1 is accessed via a virtual base register
; CHECK-DAG: add [[LARGE1:x[0-9]+]], sp, #8, lsl #12 ; CHECK-DAG: add [[LARGE1:x[0-9]+]], sp, #8, lsl #12
; CHECK-DAG: stp x0, x0, {{\[}}[[LARGE1]]] ; CHECK-DAG: stp x0, x0, [[[LARGE1]]]
; large2 is at the bottom of the stack ; large2 is at the bottom of the stack
; CHECK-DAG: stp x0, x0, [sp] ; CHECK-DAG: stp x0, x0, [sp]
; vec1 and vec2 are in the SVE stack immediately below fp ; vec1 and vec2 are in the SVE stack immediately below fp
; CHECK-DAG: addvl x0, x29, #-1 ; CHECK-DAG: addvl x0, x29, #-1
; CHECK-DAG: bl ptr_fn ; CHECK-DAG: bl ptr_fn
; CHECK-DAG: addvl x0, x29, #-2 ; CHECK-DAG: addvl x0, x29, #-2
Show All 24 Lines
; CHECK: mov x29, sp ; CHECK: mov x29, sp
; CHECK: addvl sp, sp, #-3 ; CHECK: addvl sp, sp, #-3
; CHECK: sub sp, sp, #16, lsl #12 ; CHECK: sub sp, sp, #16, lsl #12
; CHECK: sub sp, sp, #16 ; CHECK: sub sp, sp, #16
; Stack guard is placed at the top of the SVE stack area ; Stack guard is placed at the top of the SVE stack area
; CHECK-DAG: ldr [[STACK_GUARD:x[0-9]+]], [{{x[0-9]+}}, :lo12:__stack_chk_guard] ; CHECK-DAG: ldr [[STACK_GUARD:x[0-9]+]], [{{x[0-9]+}}, :lo12:__stack_chk_guard]
; CHECK-DAG: addvl [[STACK_GUARD_POS:x[0-9]+]], x29, #-1 ; CHECK-DAG: addvl [[STACK_GUARD_POS:x[0-9]+]], x29, #-1
; CHECK-DAG: str [[STACK_GUARD]], {{\[}}[[STACK_GUARD_POS]]] ; CHECK-DAG: str [[STACK_GUARD]], [[[STACK_GUARD_POS]]]
; char_arr is below the SVE stack area ; char_arr is below the SVE stack area
; CHECK-DAG: addvl [[CHAR_ARR:x[0-9]+]], x29, #-3 ; CHECK-DAG: addvl [[CHAR_ARR:x[0-9]+]], x29, #-3
; CHECK-DAG: sturb wzr, {{\[}}[[CHAR_ARR]], #-8] ; CHECK-DAG: sturb wzr, [[[CHAR_ARR]], #-8]
; large1 is accessed via a virtual base register ; large1 is accessed via a virtual base register
; CHECK-DAG: add [[LARGE1:x[0-9]+]], sp, #8, lsl #12 ; CHECK-DAG: add [[LARGE1:x[0-9]+]], sp, #8, lsl #12
; CHECK-DAG: stp x0, x0, {{\[}}[[LARGE1]], #8] ; CHECK-DAG: stp x0, x0, [[[LARGE1]], #8]
; large2 is at the bottom of the stack ; large2 is at the bottom of the stack
; CHECK-DAG: stp x0, x0, [sp, #8] ; CHECK-DAG: stp x0, x0, [sp, #8]
; vec1 and vec2 are in the SVE stack area below the stack guard ; vec1 and vec2 are in the SVE stack area below the stack guard
; CHECK-DAG: addvl x0, x29, #-2 ; CHECK-DAG: addvl x0, x29, #-2
; CHECK-DAG: bl ptr_fn ; CHECK-DAG: bl ptr_fn
; CHECK-DAG: addvl x0, x29, #-3 ; CHECK-DAG: addvl x0, x29, #-3
▲ Show 20 Lines • Show All 114 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/stack-protector-target.ll

Show All 9 Linesentry:
%0 = bitcast i32* %x to i8* %0 = bitcast i32* %x to i8*
call void @_Z7CapturePi(i32* nonnull %x) call void @_Z7CapturePi(i32* nonnull %x)
ret void ret void
} }
declare void @_Z7CapturePi(i32*) declare void @_Z7CapturePi(i32*)
; ANDROID-AARCH64: mrs [[A:.*]], TPIDR_EL0 ; ANDROID-AARCH64: mrs [[A:.*]], TPIDR_EL0
; ANDROID-AARCH64: ldr [[B:.*]], {{\[}}[[A]], #40] ; ANDROID-AARCH64: ldr [[B:.*]], [[[A]], #40]
; ANDROID-AARCH64: str [[B]], [sp, ; ANDROID-AARCH64: str [[B]], [sp,
; ANDROID-AARCH64: ldr [[C:.*]], {{\[}}[[A]], #40] ; ANDROID-AARCH64: ldr [[C:.*]], [[[A]], #40]
; ANDROID-AARCH64: ldr [[D:.*]], [sp, ; ANDROID-AARCH64: ldr [[D:.*]], [sp,
; ANDROID-AARCH64: cmp [[C]], [[D]] ; ANDROID-AARCH64: cmp [[C]], [[D]]
; FUCHSIA-AARCH64-USER: mrs [[A:.*]], TPIDR_EL0 ; FUCHSIA-AARCH64-USER: mrs [[A:.*]], TPIDR_EL0
; FUCHSIA-AARCH64-KERNEL: mrs [[A:.*]], TPIDR_EL1 ; FUCHSIA-AARCH64-KERNEL: mrs [[A:.*]], TPIDR_EL1
; FUCHSIA-AARCH64-COMMON: ldur [[B:.*]], {{\[}}[[A]], #-16] ; FUCHSIA-AARCH64-COMMON: ldur [[B:.*]], [[[A]], #-16]
; FUCHSIA-AARCH64-COMMON: str [[B]], [sp, ; FUCHSIA-AARCH64-COMMON: str [[B]], [sp,
; FUCHSIA-AARCH64-COMMON: ldur [[C:.*]], {{\[}}[[A]], #-16] ; FUCHSIA-AARCH64-COMMON: ldur [[C:.*]], [[[A]], #-16]
; FUCHSIA-AARCH64-COMMON: ldr [[D:.*]], [sp, ; FUCHSIA-AARCH64-COMMON: ldr [[D:.*]], [sp,
; FUCHSIA-AARCH64-COMMON: cmp [[C]], [[D]] ; FUCHSIA-AARCH64-COMMON: cmp [[C]], [[D]]
; WINDOWS-AARCH64: adrp x8, __security_cookie ; WINDOWS-AARCH64: adrp x8, __security_cookie
; WINDOWS-AARCH64: ldr x8, [x8, :lo12:__security_cookie] ; WINDOWS-AARCH64: ldr x8, [x8, :lo12:__security_cookie]
; WINDOWS-AARCH64: str x8, [sp, #8] ; WINDOWS-AARCH64: str x8, [sp, #8]
; WINDOWS-AARCH64: bl _Z7CapturePi ; WINDOWS-AARCH64: bl _Z7CapturePi
; WINDOWS-AARCH64: ldr x0, [sp, #8] ; WINDOWS-AARCH64: ldr x0, [sp, #8]
; WINDOWS-AARCH64: bl __security_check_cookie ; WINDOWS-AARCH64: bl __security_check_cookie

llvm/test/CodeGen/AArch64/stack-tagging-unchecked-ld-st.ll

Show First 20 Lines • Show All 206 Lines • ▼ Show 20 Lines
; NEVER: ldrb [[A:w.*]], [x{{.*}}] ; NEVER: ldrb [[A:w.*]], [x{{.*}}]
; NEVER: ldrb [[B:w.*]], [x{{.*}}] ; NEVER: ldrb [[B:w.*]], [x{{.*}}]
; DEFAULT: ldrb [[A:w.*]], [x{{.*}}] ; DEFAULT: ldrb [[A:w.*]], [x{{.*}}]
; DEFAULT: ldrb [[B:w.*]], [x{{.*}}] ; DEFAULT: ldrb [[B:w.*]], [x{{.*}}]
; ALWAYS-DAG: ldg [[PA:x.*]], [x{{.*}}] ; ALWAYS-DAG: ldg [[PA:x.*]], [x{{.*}}]
; ALWAYS-DAG: ldrb [[B:w.*]], [sp] ; ALWAYS-DAG: ldrb [[B:w.*]], [sp]
; ALWAYS-DAG: ldrb [[A:w.*]], {{\[}}[[PA]]{{\]}} ; ALWAYS-DAG: ldrb [[A:w.*]], [[[PA]]]
; COMMON: ret ; COMMON: ret
; One of these allocas is closer to FP than to SP, and within 256 bytes ; One of these allocas is closer to FP than to SP, and within 256 bytes
; of the former (see hardcoded limit in resolveFrameOffsetReference). ; of the former (see hardcoded limit in resolveFrameOffsetReference).
; It could be lowered to an FP-relative load, but not when doing an ; It could be lowered to an FP-relative load, but not when doing an
; unchecked access to tagged memory! ; unchecked access to tagged memory!
define i8 @FPOffset() "frame-pointer"="all" sanitize_memtag { define i8 @FPOffset() "frame-pointer"="all" sanitize_memtag {
Show All 36 Lines

llvm/test/CodeGen/AArch64/stack_guard_remat.ll

; RUN: llc < %s -mtriple=arm64-apple-ios -relocation-model=pic -no-integrated-as | FileCheck %s -check-prefix=DARWIN ; RUN: llc < %s -mtriple=arm64-apple-ios -relocation-model=pic -no-integrated-as | FileCheck %s -check-prefix=DARWIN
; RUN: llc < %s -mtriple=arm64-apple-ios -relocation-model=static -no-integrated-as | FileCheck %s -check-prefix=DARWIN ; RUN: llc < %s -mtriple=arm64-apple-ios -relocation-model=static -no-integrated-as | FileCheck %s -check-prefix=DARWIN
; RUN: llc < %s -mtriple=aarch64-linux-gnu -relocation-model=pic -no-integrated-as | FileCheck %s -check-prefix=PIC-LINUX ; RUN: llc < %s -mtriple=aarch64-linux-gnu -relocation-model=pic -no-integrated-as | FileCheck %s -check-prefix=PIC-LINUX
; RUN: llc < %s -mtriple=aarch64-linux-gnu -relocation-model=static -code-model=large -no-integrated-as | FileCheck %s -check-prefix=STATIC-LARGE ; RUN: llc < %s -mtriple=aarch64-linux-gnu -relocation-model=static -code-model=large -no-integrated-as | FileCheck %s -check-prefix=STATIC-LARGE
; RUN: llc < %s -mtriple=aarch64-linux-gnu -relocation-model=static -code-model=small -no-integrated-as | FileCheck %s -check-prefix=STATIC-SMALL ; RUN: llc < %s -mtriple=aarch64-linux-gnu -relocation-model=static -code-model=small -no-integrated-as | FileCheck %s -check-prefix=STATIC-SMALL
; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=arm64-apple-ios -relocation-model=pic -no-integrated-as 2>&1 | FileCheck %s -check-prefixes=DARWIN,FALLBACK ; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=arm64-apple-ios -relocation-model=pic -no-integrated-as 2>&1 | FileCheck %s -check-prefixes=DARWIN,FALLBACK
; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=arm64-apple-ios -relocation-model=static -no-integrated-as 2>&1 | FileCheck %s -check-prefixes=DARWIN,FALLBACK ; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=arm64-apple-ios -relocation-model=static -no-integrated-as 2>&1 | FileCheck %s -check-prefixes=DARWIN,FALLBACK
; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=aarch64-linux-gnu -relocation-model=pic -no-integrated-as 2>&1 | FileCheck %s -check-prefixes=PIC-LINUX,FALLBACK ; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=aarch64-linux-gnu -relocation-model=pic -no-integrated-as 2>&1 | FileCheck %s -check-prefixes=PIC-LINUX,FALLBACK
; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=aarch64-linux-gnu -relocation-model=static -code-model=large -no-integrated-as 2>&1 | FileCheck %s -check-prefixes=STATIC-LARGE,FALLBACK ; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=aarch64-linux-gnu -relocation-model=static -code-model=large -no-integrated-as 2>&1 | FileCheck %s -check-prefixes=STATIC-LARGE,FALLBACK
; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=aarch64-linux-gnu -relocation-model=static -code-model=small -no-integrated-as 2>&1 | FileCheck %s -check-prefixes=STATIC-SMALL,FALLBACK ; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=aarch64-linux-gnu -relocation-model=static -code-model=small -no-integrated-as 2>&1 | FileCheck %s -check-prefixes=STATIC-SMALL,FALLBACK
; DARWIN: foo2 ; DARWIN: foo2
; DARWIN: adrp [[R0:x[0-9]+]], ___stack_chk_guard@GOTPAGE ; DARWIN: adrp [[R0:x[0-9]+]], ___stack_chk_guard@GOTPAGE
; DARWIN: ldr [[R1:x[0-9]+]], {{\[}}[[R0]], ___stack_chk_guard@GOTPAGEOFF{{\]}} ; DARWIN: ldr [[R1:x[0-9]+]], [[[R0]], ___stack_chk_guard@GOTPAGEOFF]
; DARWIN: ldr {{x[0-9]+}}, {{\[}}[[R1]]{{\]}} ; DARWIN: ldr {{x[0-9]+}}, [[[R1]]]
; PIC-LINUX: foo2 ; PIC-LINUX: foo2
; PIC-LINUX: adrp [[R0:x[0-9]+]], :got:__stack_chk_guard ; PIC-LINUX: adrp [[R0:x[0-9]+]], :got:__stack_chk_guard
; PIC-LINUX: ldr [[R1:x[0-9]+]], {{\[}}[[R0]], :got_lo12:__stack_chk_guard{{\]}} ; PIC-LINUX: ldr [[R1:x[0-9]+]], [[[R0]], :got_lo12:__stack_chk_guard]
; PIC-LINUX: ldr {{x[0-9]+}}, {{\[}}[[R1]]{{\]}} ; PIC-LINUX: ldr {{x[0-9]+}}, [[[R1]]]
; STATIC-LARGE: foo2 ; STATIC-LARGE: foo2
; STATIC-LARGE: movz [[R0:x[0-9]+]], #:abs_g0_nc:__stack_chk_guard ; STATIC-LARGE: movz [[R0:x[0-9]+]], #:abs_g0_nc:__stack_chk_guard
; STATIC-LARGE: movk [[R0]], #:abs_g1_nc:__stack_chk_guard ; STATIC-LARGE: movk [[R0]], #:abs_g1_nc:__stack_chk_guard
; STATIC-LARGE: movk [[R0]], #:abs_g2_nc:__stack_chk_guard ; STATIC-LARGE: movk [[R0]], #:abs_g2_nc:__stack_chk_guard
; STATIC-LARGE: movk [[R0]], #:abs_g3:__stack_chk_guard ; STATIC-LARGE: movk [[R0]], #:abs_g3:__stack_chk_guard
; STATIC-LARGE: ldr {{x[0-9]+}}, {{\[}}[[R0]]{{\]}} ; STATIC-LARGE: ldr {{x[0-9]+}}, [[[R0]]]
; STATIC-SMALL: foo2 ; STATIC-SMALL: foo2
; STATIC-SMALL: adrp [[R0:x[0-9]+]], __stack_chk_guard ; STATIC-SMALL: adrp [[R0:x[0-9]+]], __stack_chk_guard
; STATIC-SMALL: ldr {{x[0-9]+}}, {{\[}}[[R0]], :lo12:__stack_chk_guard{{\]}} ; STATIC-SMALL: ldr {{x[0-9]+}}, [[[R0]], :lo12:__stack_chk_guard]
; FALLBACK-NOT: remark:{{.*}}llvm.lifetime.end ; FALLBACK-NOT: remark:{{.*}}llvm.lifetime.end
; FALLBACK-NOT: remark:{{.*}}llvm.lifetime.start ; FALLBACK-NOT: remark:{{.*}}llvm.lifetime.start
define i32 @test_stack_guard_remat() #0 { define i32 @test_stack_guard_remat() #0 {
entry: entry:
%a1 = alloca [256 x i32], align 4 %a1 = alloca [256 x i32], align 4
%0 = bitcast [256 x i32]* %a1 to i8* %0 = bitcast [256 x i32]* %a1 to i8*
call void @llvm.lifetime.start.p0i8(i64 1024, i8* %0) call void @llvm.lifetime.start.p0i8(i64 1024, i8* %0)
Show All 16 Lines

llvm/test/CodeGen/AArch64/stgp.ll

; RUN: llc < %s -mtriple=aarch64 -mattr=+mte | FileCheck %s ; RUN: llc < %s -mtriple=aarch64 -mattr=+mte | FileCheck %s
define void @stgp0(i64 %a, i64 %b, i8* %p) { define void @stgp0(i64 %a, i64 %b, i8* %p) {
entry: entry:
; CHECK-LABEL: stgp0: ; CHECK-LABEL: stgp0:
; CHECK: stgp x0, x1, [x2] ; CHECK: stgp x0, x1, [x2]
; CHECK: ret ; CHECK: ret
call void @llvm.aarch64.stgp(i8* %p, i64 %a, i64 %b) call void @llvm.aarch64.stgp(i8* %p, i64 %a, i64 %b)
ret void ret void
} }
define void @stgp1004(i64 %a, i64 %b, i8* %p) { define void @stgp1004(i64 %a, i64 %b, i8* %p) {
entry: entry:
; CHECK-LABEL: stgp1004: ; CHECK-LABEL: stgp1004:
; CHECK: add [[R:x[0-9]+]], x2, #1004 ; CHECK: add [[R:x[0-9]+]], x2, #1004
; CHECK: stgp x0, x1, {{\[}}[[R]]{{\]}} ; CHECK: stgp x0, x1, [[[R]]]
; CHECK: ret ; CHECK: ret
%q = getelementptr i8, i8* %p, i32 1004 %q = getelementptr i8, i8* %p, i32 1004
call void @llvm.aarch64.stgp(i8* %q, i64 %a, i64 %b) call void @llvm.aarch64.stgp(i8* %q, i64 %a, i64 %b)
ret void ret void
} }
define void @stgp1008(i64 %a, i64 %b, i8* %p) { define void @stgp1008(i64 %a, i64 %b, i8* %p) {
entry: entry:
; CHECK-LABEL: stgp1008: ; CHECK-LABEL: stgp1008:
; CHECK: stgp x0, x1, [x2, #1008] ; CHECK: stgp x0, x1, [x2, #1008]
; CHECK: ret ; CHECK: ret
%q = getelementptr i8, i8* %p, i32 1008 %q = getelementptr i8, i8* %p, i32 1008
call void @llvm.aarch64.stgp(i8* %q, i64 %a, i64 %b) call void @llvm.aarch64.stgp(i8* %q, i64 %a, i64 %b)
ret void ret void
} }
define void @stgp1024(i64 %a, i64 %b, i8* %p) { define void @stgp1024(i64 %a, i64 %b, i8* %p) {
entry: entry:
; CHECK-LABEL: stgp1024: ; CHECK-LABEL: stgp1024:
; CHECK: add [[R:x[0-9]+]], x2, #1024 ; CHECK: add [[R:x[0-9]+]], x2, #1024
; CHECK: stgp x0, x1, {{\[}}[[R]]{{\]}} ; CHECK: stgp x0, x1, [[[R]]]
; CHECK: ret ; CHECK: ret
%q = getelementptr i8, i8* %p, i32 1024 %q = getelementptr i8, i8* %p, i32 1024
call void @llvm.aarch64.stgp(i8* %q, i64 %a, i64 %b) call void @llvm.aarch64.stgp(i8* %q, i64 %a, i64 %b)
ret void ret void
} }
define void @stgp_1024(i64 %a, i64 %b, i8* %p) { define void @stgp_1024(i64 %a, i64 %b, i8* %p) {
entry: entry:
Show All 33 Lines

llvm/test/CodeGen/AArch64/swiftself.ll

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
; We cannot pretend that 'x0' is alive across the thisreturn_attribute call as ; We cannot pretend that 'x0' is alive across the thisreturn_attribute call as
; we normally would. We marked the first parameter with swiftself which means it ; we normally would. We marked the first parameter with swiftself which means it
; will no longer be passed in x0. ; will no longer be passed in x0.
declare swiftcc i8* @thisreturn_attribute(i8* returned swiftself) declare swiftcc i8* @thisreturn_attribute(i8* returned swiftself)
; OPTAARCH64-LABEL: swiftself_nothisreturn: ; OPTAARCH64-LABEL: swiftself_nothisreturn:
; OPTAARCH64-DAG: ldr x20, [x20] ; OPTAARCH64-DAG: ldr x20, [x20]
; OPTAARCH64-DAG: mov [[CSREG:x[1-9].*]], x8 ; OPTAARCH64-DAG: mov [[CSREG:x[1-9].*]], x8
; OPTAARCH64: bl {{_?}}thisreturn_attribute ; OPTAARCH64: bl {{_?}}thisreturn_attribute
; OPTAARCH64: str x0, {{\[}}[[CSREG]] ; OPTAARCH64: str x0, [[[CSREG]]
; OPTAARCH64: ret ; OPTAARCH64: ret
; OPTARM64_32-LABEL: swiftself_nothisreturn: ; OPTARM64_32-LABEL: swiftself_nothisreturn:
; OPTARM64_32-DAG: ldr w20, [x20] ; OPTARM64_32-DAG: ldr w20, [x20]
; OPTARM64_32-DAG: mov [[CSREG:x[1-9].*]], x8 ; OPTARM64_32-DAG: mov [[CSREG:x[1-9].*]], x8
; OPTARM64_32: bl {{_?}}thisreturn_attribute ; OPTARM64_32: bl {{_?}}thisreturn_attribute
; OPTARM64_32: str w0, {{\[}}[[CSREG]] ; OPTARM64_32: str w0, [[[CSREG]]
; OPTARM64_32: ret ; OPTARM64_32: ret
define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture sret(i8*), i8** noalias nocapture readonly swiftself) { define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture sret(i8*), i8** noalias nocapture readonly swiftself) {
entry: entry:
%2 = load i8*, i8** %1, align 8 %2 = load i8*, i8** %1, align 8
%3 = tail call swiftcc i8* @thisreturn_attribute(i8* swiftself %2) %3 = tail call swiftcc i8* @thisreturn_attribute(i8* swiftself %2)
store i8* %3, i8** %0, align 8 store i8* %3, i8** %0, align 8
ret void ret void
} }

llvm/test/CodeGen/AArch64/tagged-globals-pic.ll

Show All 18 Lines
target triple = "aarch64-unknown-linux-android" target triple = "aarch64-unknown-linux-android"
@global = external global i32 @global = external global i32
declare void @func() declare void @func()
define i32* @global_addr() #0 { define i32* @global_addr() #0 {
; CHECK-PIC: global_addr: ; CHECK-PIC: global_addr:
; CHECK-PIC: adrp [[REG:x[0-9]+]], :got:global ; CHECK-PIC: adrp [[REG:x[0-9]+]], :got:global
; CHECK-PIC: ldr x0, {{\[}}[[REG]], :got_lo12:global] ; CHECK-PIC: ldr x0, [[[REG]], :got_lo12:global]
; CHECK-PIC: ret ; CHECK-PIC: ret
ret i32* @global ret i32* @global
} }
define i32 @global_load() #0 { define i32 @global_load() #0 {
; CHECK-SELECTIONDAGISEL: global_load: ; CHECK-SELECTIONDAGISEL: global_load:
; CHECK-SELECTIONDAGISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global ; CHECK-SELECTIONDAGISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global
; CHECK-SELECTIONDAGISEL: ldr w0, {{\[}}[[REG]], :lo12:global{{\]}} ; CHECK-SELECTIONDAGISEL: ldr w0, [[[REG]], :lo12:global]
; CHECK-SELECTIONDAGISEL: ret ; CHECK-SELECTIONDAGISEL: ret
; CHECK-GLOBALISEL: global_load: ; CHECK-GLOBALISEL: global_load:
; CHECK-GLOBALISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global ; CHECK-GLOBALISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global
; CHECK-GLOBALISEL: movk [[REG]], #:prel_g3:global+4294967296 ; CHECK-GLOBALISEL: movk [[REG]], #:prel_g3:global+4294967296
; CHECK-GLOBALISEL: add [[REG]], [[REG]], :lo12:global ; CHECK-GLOBALISEL: add [[REG]], [[REG]], :lo12:global
; CHECK-GLOBALISEL: ldr w0, {{\[}}[[REG]]{{\]}} ; CHECK-GLOBALISEL: ldr w0, [[[REG]]]
; CHECK-GLOBALISEL: ret ; CHECK-GLOBALISEL: ret
; CHECK-PIC: global_load: ; CHECK-PIC: global_load:
; CHECK-PIC: adrp [[REG:x[0-9]+]], :got:global ; CHECK-PIC: adrp [[REG:x[0-9]+]], :got:global
; CHECK-PIC: ldr [[REG]], {{\[}}[[REG]], :got_lo12:global] ; CHECK-PIC: ldr [[REG]], [[[REG]], :got_lo12:global]
; CHECK-PIC: ldr w0, {{\[}}[[REG]]{{\]}} ; CHECK-PIC: ldr w0, [[[REG]]]
; CHECK-PIC: ret ; CHECK-PIC: ret
%load = load i32, i32* @global %load = load i32, i32* @global
ret i32 %load ret i32 %load
} }
define void @global_store() #0 { define void @global_store() #0 {
; CHECK-SELECTIONDAGISEL: global_store: ; CHECK-SELECTIONDAGISEL: global_store:
; CHECK-SELECTIONDAGISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global ; CHECK-SELECTIONDAGISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global
; CHECK-SELECTIONDAGISEL: str wzr, {{\[}}[[REG]], :lo12:global{{\]}} ; CHECK-SELECTIONDAGISEL: str wzr, [[[REG]], :lo12:global]
; CHECK-SELECTIONDAGISEL: ret ; CHECK-SELECTIONDAGISEL: ret
; CHECK-GLOBALISEL: global_store: ; CHECK-GLOBALISEL: global_store:
; CHECK-GLOBALISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global ; CHECK-GLOBALISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global
; CHECK-GLOBALISEL: movk [[REG]], #:prel_g3:global+4294967296 ; CHECK-GLOBALISEL: movk [[REG]], #:prel_g3:global+4294967296
; CHECK-GLOBALISEL: add [[REG]], [[REG]], :lo12:global ; CHECK-GLOBALISEL: add [[REG]], [[REG]], :lo12:global
; CHECK-GLOBALISEL: str wzr, {{\[}}[[REG]]{{\]}} ; CHECK-GLOBALISEL: str wzr, [[[REG]]]
; CHECK-GLOBALISEL: ret ; CHECK-GLOBALISEL: ret
; CHECK-PIC: global_store: ; CHECK-PIC: global_store:
; CHECK-PIC: adrp [[REG:x[0-9]+]], :got:global ; CHECK-PIC: adrp [[REG:x[0-9]+]], :got:global
; CHECK-PIC: ldr [[REG]], {{\[}}[[REG]], :got_lo12:global] ; CHECK-PIC: ldr [[REG]], [[[REG]], :got_lo12:global]
; CHECK-PIC: str wzr, {{\[}}[[REG]]{{\]}} ; CHECK-PIC: str wzr, [[[REG]]]
; CHECK-PIC: ret ; CHECK-PIC: ret
store i32 0, i32* @global store i32 0, i32* @global
ret void ret void
} }
define void ()* @func_addr() #0 { define void ()* @func_addr() #0 {
; CHECK-PIC: func_addr: ; CHECK-PIC: func_addr:
; CHECK-PIC: adrp [[REG:x[0-9]+]], :got:func ; CHECK-PIC: adrp [[REG:x[0-9]+]], :got:func
; CHECK-PIC: ldr x0, {{\[}}[[REG]], :got_lo12:func] ; CHECK-PIC: ldr x0, [[[REG]], :got_lo12:func]
; CHECK-PIC: ret ; CHECK-PIC: ret
ret void ()* @func ret void ()* @func
} }
attributes #0 = { "target-features"="+tagged-globals" } attributes #0 = { "target-features"="+tagged-globals" }

llvm/test/CodeGen/AArch64/tagged-globals-static.ll

Show All 20 Linesdefine i32* @global_addr() #0 {
; CHECK-STATIC: ret ; CHECK-STATIC: ret
ret i32* @global ret i32* @global
} }
define i32 @global_load() #0 { define i32 @global_load() #0 {
; CHECK-SELECTIONDAGISEL: global_load: ; CHECK-SELECTIONDAGISEL: global_load:
; CHECK-SELECTIONDAGISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global ; CHECK-SELECTIONDAGISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global
; CHECK-SELECTIONDAGISEL: ldr w0, {{\[}}[[REG]], :lo12:global{{\]}} ; CHECK-SELECTIONDAGISEL: ldr w0, [[[REG]], :lo12:global]
; CHECK-SELECTIONDAGISEL: ret ; CHECK-SELECTIONDAGISEL: ret
; CHECK-GLOBALISEL: global_load: ; CHECK-GLOBALISEL: global_load:
; CHECK-GLOBALISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global ; CHECK-GLOBALISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global
; CHECK-GLOBALISEL: movk [[REG]], #:prel_g3:global+4294967296 ; CHECK-GLOBALISEL: movk [[REG]], #:prel_g3:global+4294967296
; CHECK-GLOBALISEL: add [[REG]], [[REG]], :lo12:global ; CHECK-GLOBALISEL: add [[REG]], [[REG]], :lo12:global
; CHECK-GLOBALISEL: ldr w0, {{\[}}[[REG]]{{\]}} ; CHECK-GLOBALISEL: ldr w0, [[[REG]]]
; CHECK-GLOBALISEL: ret ; CHECK-GLOBALISEL: ret
%load = load i32, i32* @global %load = load i32, i32* @global
ret i32 %load ret i32 %load
} }
define void @global_store() #0 { define void @global_store() #0 {
; CHECK-SELECTIONDAGISEL: global_store: ; CHECK-SELECTIONDAGISEL: global_store:
; CHECK-SELECTIONDAGISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global ; CHECK-SELECTIONDAGISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global
; CHECK-SELECTIONDAGISEL: str wzr, {{\[}}[[REG]], :lo12:global{{\]}} ; CHECK-SELECTIONDAGISEL: str wzr, [[[REG]], :lo12:global]
; CHECK-SELECTIONDAGISEL: ret ; CHECK-SELECTIONDAGISEL: ret
; CHECK-GLOBALISEL: global_store: ; CHECK-GLOBALISEL: global_store:
; CHECK-GLOBALISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global ; CHECK-GLOBALISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global
; CHECK-GLOBALISEL: movk [[REG]], #:prel_g3:global+4294967296 ; CHECK-GLOBALISEL: movk [[REG]], #:prel_g3:global+4294967296
; CHECK-GLOBALISEL: add [[REG]], [[REG]], :lo12:global ; CHECK-GLOBALISEL: add [[REG]], [[REG]], :lo12:global
; CHECK-GLOBALISEL: str wzr, {{\[}}[[REG]]{{\]}} ; CHECK-GLOBALISEL: str wzr, [[[REG]]]
; CHECK-GLOBALISEL: ret ; CHECK-GLOBALISEL: ret
store i32 0, i32* @global store i32 0, i32* @global
ret void ret void
} }
define void ()* @func_addr() #0 { define void ()* @func_addr() #0 {
; CHECK-STATIC: func_addr: ; CHECK-STATIC: func_addr:
; CHECK-STATIC: adrp [[REG:x[0-9]+]], func ; CHECK-STATIC: adrp [[REG:x[0-9]+]], func
; CHECK-STATIC: add x0, [[REG]], :lo12:func ; CHECK-STATIC: add x0, [[REG]], :lo12:func
; CHECK-STATIC: ret ; CHECK-STATIC: ret
ret void ()* @func ret void ()* @func
} }
attributes #0 = { "target-features"="+tagged-globals" } attributes #0 = { "target-features"="+tagged-globals" }

llvm/test/CodeGen/AArch64/win-tls.ll

Show All 25 Lines
define i64 @getVar64() { define i64 @getVar64() {
%1 = load i64, i64* @tlsVar64 %1 = load i64, i64* @tlsVar64
ret i64 %1 ret i64 %1
} }
; CHECK-LABEL: getVar ; CHECK-LABEL: getVar
; CHECK: adrp [[TLS_INDEX_ADDR:x[0-9]+]], _tls_index ; CHECK: adrp [[TLS_INDEX_ADDR:x[0-9]+]], _tls_index
; CHECK: ldr [[TLS_POINTER:x[0-9]+]], [x18, #88] ; CHECK: ldr [[TLS_POINTER:x[0-9]+]], [x18, #88]
; CHECK: ldr w[[TLS_INDEX:[0-9]+]], {{\[}}[[TLS_INDEX_ADDR]], :lo12:_tls_index] ; CHECK: ldr w[[TLS_INDEX:[0-9]+]], [[[TLS_INDEX_ADDR]], :lo12:_tls_index]
; CHECK: ldr [[TLS:x[0-9]+]], {{\[}}[[TLS_POINTER]], x[[TLS_INDEX]], lsl #3] ; CHECK: ldr [[TLS:x[0-9]+]], [[[TLS_POINTER]], x[[TLS_INDEX]], lsl #3]
; CHECK: add [[TLS]], [[TLS]], :secrel_hi12:tlsVar ; CHECK: add [[TLS]], [[TLS]], :secrel_hi12:tlsVar
; CHECK: ldr w0, {{\[}}[[TLS]], :secrel_lo12:tlsVar{{\]}} ; CHECK: ldr w0, [[[TLS]], :secrel_lo12:tlsVar]
; CHECK-LABEL: getPtr ; CHECK-LABEL: getPtr
; CHECK: adrp [[TLS_INDEX_ADDR:x[0-9]+]], _tls_index ; CHECK: adrp [[TLS_INDEX_ADDR:x[0-9]+]], _tls_index
; CHECK: ldr [[TLS_POINTER:x[0-9]+]], [x18, #88] ; CHECK: ldr [[TLS_POINTER:x[0-9]+]], [x18, #88]
; CHECK: ldr w[[TLS_INDEX:[0-9]+]], {{\[}}[[TLS_INDEX_ADDR]], :lo12:_tls_index] ; CHECK: ldr w[[TLS_INDEX:[0-9]+]], [[[TLS_INDEX_ADDR]], :lo12:_tls_index]
; CHECK: ldr [[TLS:x[0-9]+]], {{\[}}[[TLS_POINTER]], x[[TLS_INDEX]], lsl #3] ; CHECK: ldr [[TLS:x[0-9]+]], [[[TLS_POINTER]], x[[TLS_INDEX]], lsl #3]
; CHECK: add [[TLS]], [[TLS]], :secrel_hi12:tlsVar ; CHECK: add [[TLS]], [[TLS]], :secrel_hi12:tlsVar
; CHECK: add x0, [[TLS]], :secrel_lo12:tlsVar ; CHECK: add x0, [[TLS]], :secrel_lo12:tlsVar
; CHECK-LABEL: setVar ; CHECK-LABEL: setVar
; CHECK: adrp [[TLS_INDEX_ADDR:x[0-9]+]], _tls_index ; CHECK: adrp [[TLS_INDEX_ADDR:x[0-9]+]], _tls_index
; CHECK: ldr [[TLS_POINTER:x[0-9]+]], [x18, #88] ; CHECK: ldr [[TLS_POINTER:x[0-9]+]], [x18, #88]
; CHECK: ldr w[[TLS_INDEX:[0-9]+]], {{\[}}[[TLS_INDEX_ADDR]], :lo12:_tls_index] ; CHECK: ldr w[[TLS_INDEX:[0-9]+]], [[[TLS_INDEX_ADDR]], :lo12:_tls_index]
; CHECK: ldr [[TLS:x[0-9]+]], {{\[}}[[TLS_POINTER]], x[[TLS_INDEX]], lsl #3] ; CHECK: ldr [[TLS:x[0-9]+]], [[[TLS_POINTER]], x[[TLS_INDEX]], lsl #3]
; CHECK: add [[TLS]], [[TLS]], :secrel_hi12:tlsVar ; CHECK: add [[TLS]], [[TLS]], :secrel_hi12:tlsVar
; CHECK: str w0, {{\[}}[[TLS]], :secrel_lo12:tlsVar{{\]}} ; CHECK: str w0, [[[TLS]], :secrel_lo12:tlsVar]
; CHECK-LABEL: getVar8 ; CHECK-LABEL: getVar8
; CHECK: add [[TLS:x[0-9]+]], [[TLS]], :secrel_hi12:tlsVar8 ; CHECK: add [[TLS:x[0-9]+]], [[TLS]], :secrel_hi12:tlsVar8
; CHECK: ldrb w0, {{\[}}[[TLS]], :secrel_lo12:tlsVar8{{\]}} ; CHECK: ldrb w0, [[[TLS]], :secrel_lo12:tlsVar8]
; CHECK-LABEL: getVar64 ; CHECK-LABEL: getVar64
; CHECK: add [[TLS:x[0-9]+]], [[TLS]], :secrel_hi12:tlsVar64 ; CHECK: add [[TLS:x[0-9]+]], [[TLS]], :secrel_hi12:tlsVar64
; CHECK: ldr x0, {{\[}}[[TLS]], :secrel_lo12:tlsVar64{{\]}} ; CHECK: ldr x0, [[[TLS]], :secrel_lo12:tlsVar64]

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.id.ll

; RUN: llc -global-isel -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -global-isel -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i64 @llvm.amdgcn.dispatch.id() #1 declare i64 @llvm.amdgcn.dispatch.id() #1
; GCN-LABEL: {{^}}dispatch_id: ; GCN-LABEL: {{^}}dispatch_id:
; GCN: .amd_kernel_code_t ; GCN: .amd_kernel_code_t
; GCN: enable_sgpr_dispatch_id = 1 ; GCN: enable_sgpr_dispatch_id = 1
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s6 ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s6
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s7 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s7
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @dispatch_id(i64 addrspace(1)* %out) #0 { define amdgpu_kernel void @dispatch_id(i64 addrspace(1)* %out) #0 {
%tmp0 = call i64 @llvm.amdgcn.dispatch.id() %tmp0 = call i64 @llvm.amdgcn.dispatch.id()
store i64 %tmp0, i64 addrspace(1)* %out store i64 %tmp0, i64 addrspace(1)* %out
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

llvm/test/CodeGen/AMDGPU/acc-ldst.ll

Show All 20 Linesbb:
%mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.0, float 2.0, <32 x float> %in.1, i32 1, i32 2, i32 3) %mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.0, float 2.0, <32 x float> %in.1, i32 1, i32 2, i32 3)
store <32 x float> %mai.1, <32 x float> addrspace(1)* %gep store <32 x float> %mai.1, <32 x float> addrspace(1)* %gep
ret void ret void
} }
; GCN-LABEL: {{^}}test_load1_mfma_store1: ; GCN-LABEL: {{^}}test_load1_mfma_store1:
; GCN: global_load_dword a{{[0-9]+}}, v{{[0-9:]+}}, s[{{[0-9:]+}}] ; GCN: global_load_dword a{{[0-9]+}}, v{{[0-9:]+}}, s[{{[0-9:]+}}]
; GCN-NOT: v_accvgpr_read ; GCN-NOT: v_accvgpr_read
; GCN: v_mfma_f32_32x32x1f32 a{{\[}}[[N:[0-9]+]]: ; GCN: v_mfma_f32_32x32x1f32 a[[[N:[0-9]+]]:
; GCN-NEXT: s_nop 7 ; GCN-NEXT: s_nop 7
; GCN-NEXT: s_nop 7 ; GCN-NEXT: s_nop 7
; GCN-NEXT: s_nop 2 ; GCN-NEXT: s_nop 2
; GCN-NOT: v_accvgpr_read ; GCN-NOT: v_accvgpr_read
; GCN-NEXT: global_store_dword v{{[0-9:]+}}, a[[N]], s[{{[0-9:]+}}] ; GCN-NEXT: global_store_dword v{{[0-9:]+}}, a[[N]], s[{{[0-9:]+}}]
define amdgpu_kernel void @test_load1_mfma_store1(float addrspace(1)* %arg) { define amdgpu_kernel void @test_load1_mfma_store1(float addrspace(1)* %arg) {
bb: bb:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
; NB: for atomics both vdata and vdst shall be either VGPR or AGPR ; NB: for atomics both vdata and vdst shall be either VGPR or AGPR
; GCN-LABEL: {{^}}test_atomic_mfma_4xi32_atomic_store: ; GCN-LABEL: {{^}}test_atomic_mfma_4xi32_atomic_store:
; GCN: global_atomic_sub [[IN:v[0-9]+]], v{{[0-9:]+}}, v{{[0-9]+}}, s[{{[0-9:]+}}] glc ; GCN: global_atomic_sub [[IN:v[0-9]+]], v{{[0-9:]+}}, v{{[0-9]+}}, s[{{[0-9:]+}}] glc
; GCN-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, [[IN]] ; GCN-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, [[IN]]
; GCN-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} ; GCN-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
; GCN-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} ; GCN-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
; GCN-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} ; GCN-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
; GCN: v_mfma_i32_4x4x4i8 a{{\[}}[[N:[0-9]+]]: ; GCN: v_mfma_i32_4x4x4i8 a[[[N:[0-9]+]]:
; GCN: v_accvgpr_read_b32 [[V:v[0-9]+]], a[[N]]{{$}} ; GCN: v_accvgpr_read_b32 [[V:v[0-9]+]], a[[N]]{{$}}
; GCN: global_atomic_add v{{[0-9]+}}, v{{[0-9:]+}}, [[V]], s[{{[0-9:]+}}] glc ; GCN: global_atomic_add v{{[0-9]+}}, v{{[0-9:]+}}, [[V]], s[{{[0-9:]+}}] glc
; GCN: global_store_dword v{{[0-9]+}}, v{{[0-9]+}}, ; GCN: global_store_dword v{{[0-9]+}}, v{{[0-9]+}},
define amdgpu_kernel void @test_atomic_mfma_4xi32_atomic_store(i32 addrspace(1)* %arg) { define amdgpu_kernel void @test_atomic_mfma_4xi32_atomic_store(i32 addrspace(1)* %arg) {
bb: bb:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tid %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tid
%in.1 = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 1 seq_cst %in.1 = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 1 seq_cst
%tmp0 = insertelement <4 x i32> undef, i32 %in.1, i32 0 %tmp0 = insertelement <4 x i32> undef, i32 %in.1, i32 0
%tmp1 = insertelement <4 x i32> %tmp0, i32 0, i32 1 %tmp1 = insertelement <4 x i32> %tmp0, i32 0, i32 1
%tmp2 = insertelement <4 x i32> %tmp1, i32 0, i32 2 %tmp2 = insertelement <4 x i32> %tmp1, i32 0, i32 2
%tmp3 = insertelement <4 x i32> %tmp2, i32 0, i32 3 %tmp3 = insertelement <4 x i32> %tmp2, i32 0, i32 3
%mai.1 = tail call <4 x i32> @llvm.amdgcn.mfma.i32.4x4x4i8(i32 1, i32 2, <4 x i32> %tmp3, i32 0, i32 0, i32 0) %mai.1 = tail call <4 x i32> @llvm.amdgcn.mfma.i32.4x4x4i8(i32 1, i32 2, <4 x i32> %tmp3, i32 0, i32 0, i32 0)
%elt = extractelement <4 x i32> %mai.1, i32 0 %elt = extractelement <4 x i32> %mai.1, i32 0
%val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %elt seq_cst %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %elt seq_cst
store i32 %val, i32 addrspace(1)* %arg store i32 %val, i32 addrspace(1)* %arg
ret void ret void
} }
; GCN-LABEL: {{^}}test_atomic_mfma_4xi32_atomic64_store: ; GCN-LABEL: {{^}}test_atomic_mfma_4xi32_atomic64_store:
; GCN: global_atomic_sub_x2 v[{{[0-9:]+}}], v{{[0-9:]+}}, v[{{[0-9:]+}}], s[{{[0-9:]+}}] glc ; GCN: global_atomic_sub_x2 v[{{[0-9:]+}}], v{{[0-9:]+}}, v[{{[0-9:]+}}], s[{{[0-9:]+}}] glc
; GCN-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} ; GCN-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
; GCN: v_mfma_i32_4x4x4i8 a{{\[}}[[N:[0-9]+]]: ; GCN: v_mfma_i32_4x4x4i8 a[[[N:[0-9]+]]:
; GCN: v_accvgpr_read_b32 v{{[0-9]+}}, a{{[0-9]+}} ; GCN: v_accvgpr_read_b32 v{{[0-9]+}}, a{{[0-9]+}}
; GCN: v_accvgpr_read_b32 v{{[0-9]+}}, a{{[0-9]+}} ; GCN: v_accvgpr_read_b32 v{{[0-9]+}}, a{{[0-9]+}}
; GCN: global_atomic_add_x2 v[{{[0-9:]+}}], v{{[0-9:]+}}, v[{{[0-9:]+}}], s[{{[0-9:]+}}] glc ; GCN: global_atomic_add_x2 v[{{[0-9:]+}}], v{{[0-9:]+}}, v[{{[0-9:]+}}], s[{{[0-9:]+}}] glc
define amdgpu_kernel void @test_atomic_mfma_4xi32_atomic64_store(i64 addrspace(1)* %arg) { define amdgpu_kernel void @test_atomic_mfma_4xi32_atomic64_store(i64 addrspace(1)* %arg) {
bb: bb:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tid %gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tid
%in.1 = atomicrmw volatile sub i64 addrspace(1)* %gep, i64 1 seq_cst %in.1 = atomicrmw volatile sub i64 addrspace(1)* %gep, i64 1 seq_cst
Show All 10 Linesbb:
store i64 %val, i64 addrspace(1)* %arg store i64 %val, i64 addrspace(1)* %arg
ret void ret void
} }
; NB: both data operands should be VGPR or AGPR ; NB: both data operands should be VGPR or AGPR
; GCN-LABEL: {{^}}test_load_mfma_ds2_store: ; GCN-LABEL: {{^}}test_load_mfma_ds2_store:
; GCN-DAG: ds_read_b128 [[IN:a\[[0-9:]+\]]], v{{[0-9:]+}} ; GCN-DAG: ds_read_b128 [[IN:a\[[0-9:]+\]]], v{{[0-9:]+}}
; GCN-NOT: v_accvgpr_write ; GCN-NOT: v_accvgpr_write
; GCN-DAG: v_mfma_i32_4x4x4i8 a{{\[}}[[N:[0-9]+]]:{{[0-9]+}}], v{{[0-9:]+}}, v{{[0-9:]+}}, [[IN]] ; GCN-DAG: v_mfma_i32_4x4x4i8 a[[[N:[0-9]+]]:{{[0-9]+}}], v{{[0-9:]+}}, v{{[0-9:]+}}, [[IN]]
; GCN-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} ; GCN-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}
; GCN-NOT: v_accvgpr_read ; GCN-NOT: v_accvgpr_read
; GCN: ds_write_b32 v{{[0-9]+}}, a[[N]] offset:128 ; GCN: ds_write_b32 v{{[0-9]+}}, a[[N]] offset:128
define amdgpu_kernel void @test_load_mfma_ds2_store(<4 x i32> addrspace(3)* %arg) { define amdgpu_kernel void @test_load_mfma_ds2_store(<4 x i32> addrspace(3)* %arg) {
bb: bb:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.1 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(3)* %arg, i32 %tid %gep.1 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(3)* %arg, i32 %tid
%in.1 = load <4 x i32>, <4 x i32> addrspace(3)* %gep.1 %in.1 = load <4 x i32>, <4 x i32> addrspace(3)* %gep.1
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/add.i16.ll

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_test_add_i16_zext_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
ret void ret void
} }
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
; GCN-LABEL: {{^}}v_test_add_i16_zext_to_i64: ; GCN-LABEL: {{^}}v_test_add_i16_zext_to_i64:
; VI: flat_load_ushort [[A:v[0-9]+]] ; VI: flat_load_ushort [[A:v[0-9]+]]
; VI: flat_load_ushort [[B:v[0-9]+]] ; VI: flat_load_ushort [[B:v[0-9]+]]
; VI-DAG: v_add_u16_e32 v[[ADD:[0-9]+]], [[A]], [[B]] ; VI-DAG: v_add_u16_e32 v[[ADD:[0-9]+]], [[A]], [[B]]
; VI: buffer_store_dwordx2 v{{\[}}[[ADD]]:{{[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0{{$}} ; VI: buffer_store_dwordx2 v[[[ADD]]:{{[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
define amdgpu_kernel void @v_test_add_i16_zext_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 { define amdgpu_kernel void @v_test_add_i16_zext_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds i64, i64 addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds i64, i64 addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
%gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid %gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid
%a = load volatile i16, i16 addrspace(1)* %gep.in0 %a = load volatile i16, i16 addrspace(1)* %gep.in0
%b = load volatile i16, i16 addrspace(1)* %gep.in1 %b = load volatile i16, i16 addrspace(1)* %gep.in1
%add = add i16 %a, %b %add = add i16 %a, %b
Show All 24 Lines
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
; GCN-LABEL: {{^}}v_test_add_i16_sext_to_i64: ; GCN-LABEL: {{^}}v_test_add_i16_sext_to_i64:
; VI: flat_load_ushort [[A:v[0-9]+]] ; VI: flat_load_ushort [[A:v[0-9]+]]
; VI: flat_load_ushort [[B:v[0-9]+]] ; VI: flat_load_ushort [[B:v[0-9]+]]
; VI: v_add_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]] ; VI: v_add_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
; VI-NEXT: v_bfe_i32 v[[LO:[0-9]+]], [[ADD]], 0, 16 ; VI-NEXT: v_bfe_i32 v[[LO:[0-9]+]], [[ADD]], 0, 16
; VI-NEXT: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; VI-NEXT: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; VI-NEXT: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; VI-NEXT: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
define amdgpu_kernel void @v_test_add_i16_sext_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 { define amdgpu_kernel void @v_test_add_i16_sext_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds i64, i64 addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds i64, i64 addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
%gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid %gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid
%a = load i16, i16 addrspace(1)* %gep.in0 %a = load i16, i16 addrspace(1)* %gep.in0
%b = load i16, i16 addrspace(1)* %gep.in1 %b = load i16, i16 addrspace(1)* %gep.in1
%add = add i16 %a, %b %add = add i16 %a, %b
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llvm/test/CodeGen/AMDGPU/add.v2i16.ll

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; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
; GCN-LABEL: {{^}}v_test_add_v2i16_zext_to_v2i32: ; GCN-LABEL: {{^}}v_test_add_v2i16_zext_to_v2i32:
; GFX9PLUS: global_load_dword [[A:v[0-9]+]] ; GFX9PLUS: global_load_dword [[A:v[0-9]+]]
; GFX9PLUS: global_load_dword [[B:v[0-9]+]] ; GFX9PLUS: global_load_dword [[B:v[0-9]+]]
; GFX9PLUS: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]] ; GFX9PLUS: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]]
; GFX9PLUS-DAG: v_and_b32_e32 v[[ELT0:[0-9]+]], 0xffff, [[ADD]] ; GFX9PLUS-DAG: v_and_b32_e32 v[[ELT0:[0-9]+]], 0xffff, [[ADD]]
; GFX9PLUS-DAG: v_lshrrev_b32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]] ; GFX9PLUS-DAG: v_lshrrev_b32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]]
; GFX9PLUS: buffer_store_dwordx2 v{{\[}}[[ELT0]]:[[ELT1]]{{\]}} ; GFX9PLUS: buffer_store_dwordx2 v[[[ELT0]]:[[ELT1]]]
; VI: flat_load_dword v[[A:[0-9]+]] ; VI: flat_load_dword v[[A:[0-9]+]]
; VI: flat_load_dword v[[B:[0-9]+]] ; VI: flat_load_dword v[[B:[0-9]+]]
; VI-NOT: and ; VI-NOT: and
; VI-NOT: shl ; VI-NOT: shl
; VI: v_add_u16_e32 v[[ADD_LO:[0-9]+]], v[[A]], v[[B]] ; VI: v_add_u16_e32 v[[ADD_LO:[0-9]+]], v[[A]], v[[B]]
; VI: v_add_u16_sdwa v[[ADD_HI:[0-9]+]], v[[A]], v[[B]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI: v_add_u16_sdwa v[[ADD_HI:[0-9]+]], v[[A]], v[[B]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NOT: and ; VI-NOT: and
; VI-NOT: shl ; VI-NOT: shl
; VI: buffer_store_dwordx2 v{{\[}}[[ADD_LO]]:[[ADD_HI]]{{\]}} ; VI: buffer_store_dwordx2 v[[[ADD_LO]]:[[ADD_HI]]]
define amdgpu_kernel void @v_test_add_v2i16_zext_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 { define amdgpu_kernel void @v_test_add_v2i16_zext_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid %gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1 %b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1
%add = add <2 x i16> %a, %b %add = add <2 x i16> %a, %b
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; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
; GCN-LABEL: {{^}}v_test_add_v2i16_sext_to_v2i32: ; GCN-LABEL: {{^}}v_test_add_v2i16_sext_to_v2i32:
; GFX9PLUS: global_load_dword [[A:v[0-9]+]] ; GFX9PLUS: global_load_dword [[A:v[0-9]+]]
; GFX9PLUS: global_load_dword [[B:v[0-9]+]] ; GFX9PLUS: global_load_dword [[B:v[0-9]+]]
; GFX9PLUS: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]] ; GFX9PLUS: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]]
; GFX9PLUS-DAG: v_bfe_i32 v[[ELT0:[0-9]+]], [[ADD]], 0, 16 ; GFX9PLUS-DAG: v_bfe_i32 v[[ELT0:[0-9]+]], [[ADD]], 0, 16
; GFX9PLUS-DAG: v_ashrrev_i32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]] ; GFX9PLUS-DAG: v_ashrrev_i32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]]
; GFX9PLUS: buffer_store_dwordx2 v{{\[}}[[ELT0]]:[[ELT1]]{{\]}} ; GFX9PLUS: buffer_store_dwordx2 v[[[ELT0]]:[[ELT1]]]
; VI: v_add_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI: v_add_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI: v_add_u16_e32 ; VI: v_add_u16_e32
; VI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16 ; VI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16
; VI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16 ; VI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16
; VI: buffer_store_dwordx2 ; VI: buffer_store_dwordx2
define amdgpu_kernel void @v_test_add_v2i16_sext_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 { define amdgpu_kernel void @v_test_add_v2i16_sext_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 {
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llvm/test/CodeGen/AMDGPU/add_i128.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_i128_vreg: ; GCN-LABEL: {{^}}test_i128_vreg:
; GCN: v_add_i32_e32 v[[LO:[0-9]+]], vcc, ; GCN: v_add_i32_e32 v[[LO:[0-9]+]], vcc,
; GCN-NEXT: v_addc_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, vcc ; GCN-NEXT: v_addc_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, vcc
; GCN-NEXT: v_addc_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, vcc ; GCN-NEXT: v_addc_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, vcc
; GCN-NEXT: v_addc_u32_e32 v[[HI:[0-9]+]], vcc, v{{[0-9]+}}, v{{[0-9]+}}, vcc ; GCN-NEXT: v_addc_u32_e32 v[[HI:[0-9]+]], vcc, v{{[0-9]+}}, v{{[0-9]+}}, vcc
; GCN: buffer_store_dwordx4 v{{\[}}[[LO]]:[[HI]]], ; GCN: buffer_store_dwordx4 v[[[LO]]:[[HI]]],
define amdgpu_kernel void @test_i128_vreg(i128 addrspace(1)* noalias %out, i128 addrspace(1)* noalias %inA, i128 addrspace(1)* noalias %inB) { define amdgpu_kernel void @test_i128_vreg(i128 addrspace(1)* noalias %out, i128 addrspace(1)* noalias %inA, i128 addrspace(1)* noalias %inB) {
%tid = call i32 @llvm.amdgcn.workitem.id.x() readnone %tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
%a_ptr = getelementptr i128, i128 addrspace(1)* %inA, i32 %tid %a_ptr = getelementptr i128, i128 addrspace(1)* %inA, i32 %tid
%b_ptr = getelementptr i128, i128 addrspace(1)* %inB, i32 %tid %b_ptr = getelementptr i128, i128 addrspace(1)* %inB, i32 %tid
%a = load i128, i128 addrspace(1)* %a_ptr %a = load i128, i128 addrspace(1)* %a_ptr
%b = load i128, i128 addrspace(1)* %b_ptr %b = load i128, i128 addrspace(1)* %b_ptr
%result = add i128 %a, %b %result = add i128 %a, %b
store i128 %result, i128 addrspace(1)* %out store i128 %result, i128 addrspace(1)* %out
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llvm/test/CodeGen/AMDGPU/addrspacecast.ll

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; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_shared_base ; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_shared_base
; GFX9: s_cmp_lg_u32 [[PTR]], -1 ; GFX9: s_cmp_lg_u32 [[PTR]], -1
; GFX9: s_cselect_b64 vcc, -1, 0 ; GFX9: s_cselect_b64 vcc, -1, 0
; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc ; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
; GFX9-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] ; GFX9-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] ; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] ; HSA: flat_store_dword v[[[LO]]:[[HI]]], [[K]]
; At most 2 digits. Make sure src_shared_base is not counted as a high ; At most 2 digits. Make sure src_shared_base is not counted as a high
; number SGPR. ; number SGPR.
; CI: NumSgprs: {{[0-9][0-9]+}} ; CI: NumSgprs: {{[0-9][0-9]+}}
; GFX9: NumSgprs: {{[0-9]+}} ; GFX9: NumSgprs: {{[0-9]+}}
define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #0 { define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #0 {
%stof = addrspacecast i32 addrspace(3)* %ptr to i32* %stof = addrspacecast i32 addrspace(3)* %ptr to i32*
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; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 ; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16
; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_SHARED_BASE]] ; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_SHARED_BASE]]
; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_shared_base ; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_shared_base
; GFX9-DAG: v_cmp_ne_u32_e32 vcc, -1, v0 ; GFX9-DAG: v_cmp_ne_u32_e32 vcc, -1, v0
; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, v0, vcc ; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, v0, vcc
; GFX9-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc ; GFX9-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] ; HSA: flat_store_dword v[[[LO]]:[[HI]]], [[K]]
define void @use_group_to_flat_addrspacecast_func(i32 addrspace(3)* %ptr) #0 { define void @use_group_to_flat_addrspacecast_func(i32 addrspace(3)* %ptr) #0 {
%stof = addrspacecast i32 addrspace(3)* %ptr to i32* %stof = addrspacecast i32 addrspace(3)* %ptr to i32*
store volatile i32 7, i32* %stof store volatile i32 7, i32* %stof
ret void ret void
} }
; HSA-LABEL: {{^}}use_private_to_flat_addrspacecast: ; HSA-LABEL: {{^}}use_private_to_flat_addrspacecast:
; HSA: enable_sgpr_private_segment_buffer = 1 ; HSA: enable_sgpr_private_segment_buffer = 1
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; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 ; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
; GFX9: s_cmp_lg_u32 [[PTR]], -1 ; GFX9: s_cmp_lg_u32 [[PTR]], -1
; GFX9: s_cselect_b64 vcc, -1, 0 ; GFX9: s_cselect_b64 vcc, -1, 0
; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc ; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
; GFX9: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] ; GFX9: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] ; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] ; HSA: flat_store_dword v[[[LO]]:[[HI]]], [[K]]
; CI: NumSgprs: {{[0-9][0-9]+}} ; CI: NumSgprs: {{[0-9][0-9]+}}
; GFX9: NumSgprs: {{[0-9]+}} ; GFX9: NumSgprs: {{[0-9]+}}
define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32 addrspace(5)* %ptr) #0 { define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32 addrspace(5)* %ptr) #0 {
%stof = addrspacecast i32 addrspace(5)* %ptr to i32* %stof = addrspacecast i32 addrspace(5)* %ptr to i32*
store volatile i32 7, i32* %stof store volatile i32 7, i32* %stof
ret void ret void
} }
; no-op ; no-op
; HSA-LABEL: {{^}}use_global_to_flat_addrspacecast: ; HSA-LABEL: {{^}}use_global_to_flat_addrspacecast:
; HSA: enable_sgpr_queue_ptr = 0 ; HSA: enable_sgpr_queue_ptr = 0
; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} ; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
; HSA: flat_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]] ; HSA: flat_store_dword v[[[VPTRLO]]:[[VPTRHI]]], [[K]]
define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #0 {
%stof = addrspacecast i32 addrspace(1)* %ptr to i32* %stof = addrspacecast i32 addrspace(1)* %ptr to i32*
store volatile i32 7, i32* %stof store volatile i32 7, i32* %stof
ret void ret void
} }
; no-op ; no-op
; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast: ; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast:
; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} ; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
; HSA: flat_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}} ; HSA: flat_load_dword v{{[0-9]+}}, v[[[VPTRLO]]:[[VPTRHI]]]
define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(4)* %ptr) #0 {
%stof = addrspacecast i32 addrspace(4)* %ptr to i32* %stof = addrspacecast i32 addrspace(4)* %ptr to i32*
%ld = load volatile i32, i32* %stof %ld = load volatile i32, i32* %stof
ret void ret void
} }
; HSA-LABEl: {{^}}use_constant_to_global_addrspacecast: ; HSA-LABEl: {{^}}use_constant_to_global_addrspacecast:
; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} ; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
; CI-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] ; CI-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
; CI-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] ; CI-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
; CI: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}} ; CI: {{flat|global}}_load_dword v{{[0-9]+}}, v[[[VPTRLO]]:[[VPTRHI]]]
; GFX9: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}} ; GFX9: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
; GFX9: global_load_dword v{{[0-9]+}}, [[ZERO:v[0-9]+]], s{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}} ; GFX9: global_load_dword v{{[0-9]+}}, [[ZERO:v[0-9]+]], s[[[PTRLO]]:[[PTRHI]]]
define amdgpu_kernel void @use_constant_to_global_addrspacecast(i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @use_constant_to_global_addrspacecast(i32 addrspace(4)* %ptr) #0 {
%stof = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(1)* %stof = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(1)*
%ld = load volatile i32, i32 addrspace(1)* %stof %ld = load volatile i32, i32 addrspace(1)* %stof
ret void ret void
} }
; HSA-LABEL: {{^}}use_flat_to_group_addrspacecast: ; HSA-LABEL: {{^}}use_flat_to_group_addrspacecast:
; HSA: enable_sgpr_private_segment_buffer = 1 ; HSA: enable_sgpr_private_segment_buffer = 1
; HSA: enable_sgpr_dispatch_ptr = 0 ; HSA: enable_sgpr_dispatch_ptr = 0
; HSA: enable_sgpr_queue_ptr = 0 ; HSA: enable_sgpr_queue_ptr = 0
; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}} ; HSA: s_load_dwordx2 s[[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]]
; CI-DAG: v_cmp_ne_u64_e64 vcc, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}} ; CI-DAG: v_cmp_ne_u64_e64 vcc, s[[[PTR_LO]]:[[PTR_HI]]], 0{{$}}
; CI-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]] ; CI-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]]
; CI-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]] ; CI-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]]
; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}} ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}}
; GFX9-DAG: s_cmp_lg_u64 s{{\[}}[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]{{\]}}, 0 ; GFX9-DAG: s_cmp_lg_u64 s[[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]], 0
; GFX9-DAG: s_cselect_b32 s[[PTR_LO]], s[[PTR_LO]], -1 ; GFX9-DAG: s_cselect_b32 s[[PTR_LO]], s[[PTR_LO]], -1
; GFX9-DAG: v_mov_b32_e32 [[CASTPTR:v[0-9]+]], s[[PTR_LO]] ; GFX9-DAG: v_mov_b32_e32 [[CASTPTR:v[0-9]+]], s[[PTR_LO]]
; HSA: ds_write_b32 [[CASTPTR]], v[[K]] ; HSA: ds_write_b32 [[CASTPTR]], v[[K]]
define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32* %ptr) #0 { define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32* %ptr) #0 {
%ftos = addrspacecast i32* %ptr to i32 addrspace(3)* %ftos = addrspacecast i32* %ptr to i32 addrspace(3)*
store volatile i32 0, i32 addrspace(3)* %ftos store volatile i32 0, i32 addrspace(3)* %ftos
ret void ret void
} }
; HSA-LABEL: {{^}}use_flat_to_private_addrspacecast: ; HSA-LABEL: {{^}}use_flat_to_private_addrspacecast:
; HSA: enable_sgpr_private_segment_buffer = 1 ; HSA: enable_sgpr_private_segment_buffer = 1
; HSA: enable_sgpr_dispatch_ptr = 0 ; HSA: enable_sgpr_dispatch_ptr = 0
; HSA: enable_sgpr_queue_ptr = 0 ; HSA: enable_sgpr_queue_ptr = 0
; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}} ; HSA: s_load_dwordx2 s[[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]]
; CI-DAG: v_cmp_ne_u64_e64 vcc, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}} ; CI-DAG: v_cmp_ne_u64_e64 vcc, s[[[PTR_LO]]:[[PTR_HI]]], 0{{$}}
; CI-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]] ; CI-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]]
; CI-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]] ; CI-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]]
; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}} ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}}
; GFX9-DAG: s_cmp_lg_u64 s{{\[}}[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]{{\]}}, 0 ; GFX9-DAG: s_cmp_lg_u64 s[[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]], 0
; GFX9-DAG: s_cselect_b32 s[[PTR_LO]], s[[PTR_LO]], -1 ; GFX9-DAG: s_cselect_b32 s[[PTR_LO]], s[[PTR_LO]], -1
; GFX9-DAG: v_mov_b32_e32 [[CASTPTR:v[0-9]+]], s[[PTR_LO]] ; GFX9-DAG: v_mov_b32_e32 [[CASTPTR:v[0-9]+]], s[[PTR_LO]]
; HSA: buffer_store_dword v[[K]], [[CASTPTR]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}} ; HSA: buffer_store_dword v[[K]], [[CASTPTR]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32* %ptr) #0 { define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32* %ptr) #0 {
%ftos = addrspacecast i32* %ptr to i32 addrspace(5)* %ftos = addrspacecast i32* %ptr to i32 addrspace(5)*
store volatile i32 0, i32 addrspace(5)* %ftos store volatile i32 0, i32 addrspace(5)* %ftos
ret void ret void
} }
; HSA-LABEL: {{^}}use_flat_to_global_addrspacecast: ; HSA-LABEL: {{^}}use_flat_to_global_addrspacecast:
; HSA: enable_sgpr_queue_ptr = 0 ; HSA: enable_sgpr_queue_ptr = 0
; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0 ; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]], s[4:5], 0x0
; CI-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] ; CI-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
; CI-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] ; CI-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
; CI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0 ; CI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0
; CI: flat_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]] ; CI: flat_store_dword v[[[VPTRLO]]:[[VPTRHI]]], [[K]]
; GFX9: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0 ; GFX9: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
; GFX9: global_store_dword [[ZERO]], [[ZERO]], s{{\[}}[[PTRLO]]:[[PTRHI]]{{\]$}} ; GFX9: global_store_dword [[ZERO]], [[ZERO]], s[[[PTRLO]]:[[PTRHI]]{{\]$}}
define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #0 { define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #0 {
%ftos = addrspacecast i32* %ptr to i32 addrspace(1)* %ftos = addrspacecast i32* %ptr to i32 addrspace(1)*
store volatile i32 0, i32 addrspace(1)* %ftos store volatile i32 0, i32 addrspace(1)* %ftos
ret void ret void
} }
; HSA-LABEL: {{^}}use_flat_to_constant_addrspacecast: ; HSA-LABEL: {{^}}use_flat_to_constant_addrspacecast:
; HSA: enable_sgpr_queue_ptr = 0 ; HSA: enable_sgpr_queue_ptr = 0
; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0 ; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]], s[4:5], 0x0
; HSA: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, 0x0 ; HSA: s_load_dword s{{[0-9]+}}, s[[[PTRLO]]:[[PTRHI]]], 0x0
define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #0 { define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #0 {
%ftos = addrspacecast i32* %ptr to i32 addrspace(4)* %ftos = addrspacecast i32* %ptr to i32 addrspace(4)*
load volatile i32, i32 addrspace(4)* %ftos load volatile i32, i32 addrspace(4)* %ftos
ret void ret void
} }
; HSA-LABEL: {{^}}cast_0_group_to_flat_addrspacecast: ; HSA-LABEL: {{^}}cast_0_group_to_flat_addrspacecast:
; CI: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10 ; CI: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10
; CI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]] ; CI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]]
; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) ; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16)
; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 ; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16
; GFX9-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SSRC_SHARED_BASE]] ; GFX9-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SSRC_SHARED_BASE]]
; GFX9-XXX: v_mov_b32_e32 v[[HI:[0-9]+]], src_shared_base ; GFX9-XXX: v_mov_b32_e32 v[[HI:[0-9]+]], src_shared_base
; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] ; HSA: {{flat|global}}_store_dword v[[[LO]]:[[HI]]], v[[K]]
define amdgpu_kernel void @cast_0_group_to_flat_addrspacecast() #0 { define amdgpu_kernel void @cast_0_group_to_flat_addrspacecast() #0 {
%cast = addrspacecast i32 addrspace(3)* null to i32* %cast = addrspacecast i32 addrspace(3)* null to i32*
store volatile i32 7, i32* %cast store volatile i32 7, i32* %cast
ret void ret void
} }
; HSA-LABEL: {{^}}cast_0_flat_to_group_addrspacecast: ; HSA-LABEL: {{^}}cast_0_flat_to_group_addrspacecast:
; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} ; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}}
; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
; HSA: ds_write_b32 [[PTR]], [[K]] ; HSA: ds_write_b32 [[PTR]], [[K]]
define amdgpu_kernel void @cast_0_flat_to_group_addrspacecast() #0 { define amdgpu_kernel void @cast_0_flat_to_group_addrspacecast() #0 {
%cast = addrspacecast i32* null to i32 addrspace(3)* %cast = addrspacecast i32* null to i32 addrspace(3)*
store volatile i32 7, i32 addrspace(3)* %cast store volatile i32 7, i32 addrspace(3)* %cast
ret void ret void
} }
; HSA-LABEL: {{^}}cast_neg1_group_to_flat_addrspacecast: ; HSA-LABEL: {{^}}cast_neg1_group_to_flat_addrspacecast:
; HSA: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; HSA: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
; HSA-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; HSA-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] ; HSA: {{flat|global}}_store_dword v[[[LO]]:[[HI]]], v[[K]]
define amdgpu_kernel void @cast_neg1_group_to_flat_addrspacecast() #0 { define amdgpu_kernel void @cast_neg1_group_to_flat_addrspacecast() #0 {
%cast = addrspacecast i32 addrspace(3)* inttoptr (i32 -1 to i32 addrspace(3)*) to i32* %cast = addrspacecast i32 addrspace(3)* inttoptr (i32 -1 to i32 addrspace(3)*) to i32*
store volatile i32 7, i32* %cast store volatile i32 7, i32* %cast
ret void ret void
} }
; HSA-LABEL: {{^}}cast_neg1_flat_to_group_addrspacecast: ; HSA-LABEL: {{^}}cast_neg1_flat_to_group_addrspacecast:
; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} ; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}}
Show All 12 Lines
; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16) ; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16)
; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 ; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16
; GFX9-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SSRC_SHARED_BASE]] ; GFX9-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SSRC_SHARED_BASE]]
; GFX9-XXX: v_mov_b32_e32 v[[HI:[0-9]+]], src_shared_base ; GFX9-XXX: v_mov_b32_e32 v[[HI:[0-9]+]], src_shared_base
; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] ; HSA: {{flat|global}}_store_dword v[[[LO]]:[[HI]]], v[[K]]
define amdgpu_kernel void @cast_0_private_to_flat_addrspacecast() #0 { define amdgpu_kernel void @cast_0_private_to_flat_addrspacecast() #0 {
%cast = addrspacecast i32 addrspace(5)* null to i32* %cast = addrspacecast i32 addrspace(5)* null to i32*
store volatile i32 7, i32* %cast store volatile i32 7, i32* %cast
ret void ret void
} }
; HSA-LABEL: {{^}}cast_0_flat_to_private_addrspacecast: ; HSA-LABEL: {{^}}cast_0_flat_to_private_addrspacecast:
; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} ; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}}
; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
; HSA: buffer_store_dword [[K]], [[PTR]], s{{\[[0-9]+:[0-9]+\]}}, 0 ; HSA: buffer_store_dword [[K]], [[PTR]], s{{\[[0-9]+:[0-9]+\]}}, 0
define amdgpu_kernel void @cast_0_flat_to_private_addrspacecast() #0 { define amdgpu_kernel void @cast_0_flat_to_private_addrspacecast() #0 {
%cast = addrspacecast i32* null to i32 addrspace(5)* %cast = addrspacecast i32* null to i32 addrspace(5)*
store volatile i32 7, i32 addrspace(5)* %cast store volatile i32 7, i32 addrspace(5)* %cast
ret void ret void
} }
; HSA-LABEL: {{^}}cast_neg1_private_to_flat_addrspacecast: ; HSA-LABEL: {{^}}cast_neg1_private_to_flat_addrspacecast:
; CI: enable_sgpr_queue_ptr = 1 ; CI: enable_sgpr_queue_ptr = 1
; GFX9: enable_sgpr_queue_ptr = 0 ; GFX9: enable_sgpr_queue_ptr = 0
; HSA: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; HSA: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
; HSA-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; HSA-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] ; HSA: {{flat|global}}_store_dword v[[[LO]]:[[HI]]], v[[K]]
define amdgpu_kernel void @cast_neg1_private_to_flat_addrspacecast() #0 { define amdgpu_kernel void @cast_neg1_private_to_flat_addrspacecast() #0 {
%cast = addrspacecast i32 addrspace(5)* inttoptr (i32 -1 to i32 addrspace(5)*) to i32* %cast = addrspacecast i32 addrspace(5)* inttoptr (i32 -1 to i32 addrspace(5)*) to i32*
store volatile i32 7, i32* %cast store volatile i32 7, i32* %cast
ret void ret void
} }
; HSA-LABEL: {{^}}cast_neg1_flat_to_private_addrspacecast: ; HSA-LABEL: {{^}}cast_neg1_flat_to_private_addrspacecast:
; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} ; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}}
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 {
%reload = load volatile i32, i32* %fptr, align 4 %reload = load volatile i32, i32* %fptr, align 4
store volatile i32 %reload, i32 addrspace(1)* %out, align 4 store volatile i32 %reload, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; HSA-LABEL: {{^}}use_constant_to_constant32_addrspacecast ; HSA-LABEL: {{^}}use_constant_to_constant32_addrspacecast
; GFX9: s_load_dwordx2 [[PTRPTR:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0{{$}} ; GFX9: s_load_dwordx2 [[PTRPTR:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0{{$}}
; GFX9: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0x8{{$}} ; GFX9: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0x8{{$}}
; GFX9: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}, [[PTRPTR]], 0x0{{$}} ; GFX9: s_load_dwordx2 s[[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]], [[PTRPTR]], 0x0{{$}}
; GFX9: s_mov_b32 s[[PTR_HI]], 0{{$}} ; GFX9: s_mov_b32 s[[PTR_HI]], 0{{$}}
; GFX9: s_add_i32 s[[PTR_LO]], s[[PTR_LO]], [[OFFSET]] ; GFX9: s_add_i32 s[[PTR_LO]], s[[PTR_LO]], [[OFFSET]]
; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x0{{$}} ; GFX9: s_load_dword s{{[0-9]+}}, s[[[PTR_LO]]:[[PTR_HI]]], 0x0{{$}}
define amdgpu_kernel void @use_constant_to_constant32_addrspacecast(i8 addrspace(4)* addrspace(4)* %ptr.ptr, i32 %offset) #0 { define amdgpu_kernel void @use_constant_to_constant32_addrspacecast(i8 addrspace(4)* addrspace(4)* %ptr.ptr, i32 %offset) #0 {
%ptr = load volatile i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %ptr.ptr %ptr = load volatile i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %ptr.ptr
%addrspacecast = addrspacecast i8 addrspace(4)* %ptr to i8 addrspace(6)* %addrspacecast = addrspacecast i8 addrspace(4)* %ptr to i8 addrspace(6)*
%gep = getelementptr i8, i8 addrspace(6)* %addrspacecast, i32 %offset %gep = getelementptr i8, i8 addrspace(6)* %addrspacecast, i32 %offset
%ptr.cast = bitcast i8 addrspace(6)* %gep to i32 addrspace(6)* %ptr.cast = bitcast i8 addrspace(6)* %gep to i32 addrspace(6)*
%load = load volatile i32, i32 addrspace(6)* %ptr.cast, align 4 %load = load volatile i32, i32 addrspace(6)* %ptr.cast, align 4
ret void ret void
} }
; HSA-LABEL: {{^}}use_global_to_constant32_addrspacecast ; HSA-LABEL: {{^}}use_global_to_constant32_addrspacecast
; GFX9: s_load_dwordx2 [[PTRPTR:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0{{$}} ; GFX9: s_load_dwordx2 [[PTRPTR:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0{{$}}
; GFX9: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0x8{{$}} ; GFX9: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0x8{{$}}
; GFX9: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}, [[PTRPTR]], 0x0{{$}} ; GFX9: s_load_dwordx2 s[[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]], [[PTRPTR]], 0x0{{$}}
; GFX9: s_mov_b32 s[[PTR_HI]], 0{{$}} ; GFX9: s_mov_b32 s[[PTR_HI]], 0{{$}}
; GFX9: s_add_i32 s[[PTR_LO]], s[[PTR_LO]], [[OFFSET]] ; GFX9: s_add_i32 s[[PTR_LO]], s[[PTR_LO]], [[OFFSET]]
; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x0{{$}} ; GFX9: s_load_dword s{{[0-9]+}}, s[[[PTR_LO]]:[[PTR_HI]]], 0x0{{$}}
define amdgpu_kernel void @use_global_to_constant32_addrspacecast(i8 addrspace(1)* addrspace(4)* %ptr.ptr, i32 %offset) #0 { define amdgpu_kernel void @use_global_to_constant32_addrspacecast(i8 addrspace(1)* addrspace(4)* %ptr.ptr, i32 %offset) #0 {
%ptr = load volatile i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* %ptr.ptr %ptr = load volatile i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* %ptr.ptr
%addrspacecast = addrspacecast i8 addrspace(1)* %ptr to i8 addrspace(6)* %addrspacecast = addrspacecast i8 addrspace(1)* %ptr to i8 addrspace(6)*
%gep = getelementptr i8, i8 addrspace(6)* %addrspacecast, i32 %offset %gep = getelementptr i8, i8 addrspace(6)* %addrspacecast, i32 %offset
%ptr.cast = bitcast i8 addrspace(6)* %gep to i32 addrspace(6)* %ptr.cast = bitcast i8 addrspace(6)* %gep to i32 addrspace(6)*
%load = load volatile i32, i32 addrspace(6)* %ptr.cast, align 4 %load = load volatile i32, i32 addrspace(6)* %ptr.cast, align 4
ret void ret void
} }
declare void @llvm.amdgcn.s.barrier() #1 declare void @llvm.amdgcn.s.barrier() #1
declare i32 @llvm.amdgcn.workitem.id.x() #2 declare i32 @llvm.amdgcn.workitem.id.x() #2
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind convergent } attributes #1 = { nounwind convergent }
attributes #2 = { nounwind readnone } attributes #2 = { nounwind readnone }

llvm/test/CodeGen/AMDGPU/alignbit-pat.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}alignbit_shr_pat: ; GCN-LABEL: {{^}}alignbit_shr_pat:
; GCN-DAG: s_load_dword s[[SHR:[0-9]+]] ; GCN-DAG: s_load_dword s[[SHR:[0-9]+]]
; GCN-DAG: load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} ; GCN-DAG: load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], s[[SHR]] ; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], s[[SHR]]
define amdgpu_kernel void @alignbit_shr_pat(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) { define amdgpu_kernel void @alignbit_shr_pat(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
bb: bb:
%tmp = load i64, i64 addrspace(1)* %arg, align 8 %tmp = load i64, i64 addrspace(1)* %arg, align 8
%tmp3 = and i32 %arg2, 31 %tmp3 = and i32 %arg2, 31
%tmp4 = zext i32 %tmp3 to i64 %tmp4 = zext i32 %tmp3 to i64
%tmp5 = lshr i64 %tmp, %tmp4 %tmp5 = lshr i64 %tmp, %tmp4
%tmp6 = trunc i64 %tmp5 to i32 %tmp6 = trunc i64 %tmp5 to i32
store i32 %tmp6, i32 addrspace(1)* %arg1, align 4 store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}alignbit_shr_pat_v: ; GCN-LABEL: {{^}}alignbit_shr_pat_v:
; GCN-DAG: load_dword v[[SHR:[0-9]+]], ; GCN-DAG: load_dword v[[SHR:[0-9]+]],
; GCN-DAG: load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} ; GCN-DAG: load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], v[[SHR]] ; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], v[[SHR]]
define amdgpu_kernel void @alignbit_shr_pat_v(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1) { define amdgpu_kernel void @alignbit_shr_pat_v(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1) {
bb: bb:
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tid %gep1 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tid
%tmp = load i64, i64 addrspace(1)* %gep1, align 8 %tmp = load i64, i64 addrspace(1)* %gep1, align 8
%gep2 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i32 %tid %gep2 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i32 %tid
Show All 34 Linesbb:
%tmp4 = zext i32 %tmp3 to i64 %tmp4 = zext i32 %tmp3 to i64
%tmp5 = lshr i64 %tmp, %tmp4 %tmp5 = lshr i64 %tmp, %tmp4
%tmp6 = trunc i64 %tmp5 to i32 %tmp6 = trunc i64 %tmp5 to i32
store i32 %tmp6, i32 addrspace(1)* %arg1, align 4 store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}alignbit_shr_pat_const30: ; GCN-LABEL: {{^}}alignbit_shr_pat_const30:
; GCN: load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} ; GCN: load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], 30 ; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], 30
define amdgpu_kernel void @alignbit_shr_pat_const30(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1) { define amdgpu_kernel void @alignbit_shr_pat_const30(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1) {
bb: bb:
%tmp = load i64, i64 addrspace(1)* %arg, align 8 %tmp = load i64, i64 addrspace(1)* %arg, align 8
%tmp5 = lshr i64 %tmp, 30 %tmp5 = lshr i64 %tmp, 30
%tmp6 = trunc i64 %tmp5 to i32 %tmp6 = trunc i64 %tmp5 to i32
store i32 %tmp6, i32 addrspace(1)* %arg1, align 4 store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
Show All 20 Lines

llvm/test/CodeGen/AMDGPU/always-uniform.ll

; RUN: llc -mtriple amdgcn-amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple amdgcn-amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()
declare i32 @llvm.amdgcn.readfirstlane(i32) declare i32 @llvm.amdgcn.readfirstlane(i32)
; GCN-LABEL: readfirstlane_uniform ; GCN-LABEL: readfirstlane_uniform
; GCN: s_load_dwordx2 s{{\[}}[[IN_ADDR:[0-9]+]]:1{{\]}}, s[4:5], 0x0 ; GCN: s_load_dwordx2 s[[[IN_ADDR:[0-9]+]]:1], s[4:5], 0x0
; GCN: v_readfirstlane_b32 s[[SCALAR:[0-9]+]], v0 ; GCN: v_readfirstlane_b32 s[[SCALAR:[0-9]+]], v0
; GCN: s_add_u32 s[[LOAD_ADDR:[0-9]+]], s[[IN_ADDR]], s[[SCALAR]] ; GCN: s_add_u32 s[[LOAD_ADDR:[0-9]+]], s[[IN_ADDR]], s[[SCALAR]]
; GCN: s_load_dword s{{[0-9]+}}, s{{\[}}[[LOAD_ADDR]] ; GCN: s_load_dword s{{[0-9]+}}, s[[[LOAD_ADDR]]
define amdgpu_kernel void @readfirstlane_uniform(float addrspace(1)* noalias nocapture readonly, float addrspace(1)* noalias nocapture readonly) { define amdgpu_kernel void @readfirstlane_uniform(float addrspace(1)* noalias nocapture readonly, float addrspace(1)* noalias nocapture readonly) {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
%scalar = tail call i32 @llvm.amdgcn.readfirstlane(i32 %tid) %scalar = tail call i32 @llvm.amdgcn.readfirstlane(i32 %tid)
%idx = zext i32 %scalar to i64 %idx = zext i32 %scalar to i64
%gep0 = getelementptr inbounds float, float addrspace(1)* %0, i64 %idx %gep0 = getelementptr inbounds float, float addrspace(1)* %0, i64 %idx
%val = load float, float addrspace(1)* %gep0, align 4 %val = load float, float addrspace(1)* %gep0, align 4
%gep1 = getelementptr inbounds float, float addrspace(1)* %1, i64 10 %gep1 = getelementptr inbounds float, float addrspace(1)* %1, i64 10
store float %val, float addrspace(1)* %gep1, align 4 store float %val, float addrspace(1)* %gep1, align 4
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/amdpal.ll

; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tahiti | FileCheck --check-prefixes=PAL,CI --enable-var-scope %s ; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tahiti | FileCheck --check-prefixes=PAL,CI --enable-var-scope %s
; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tonga | FileCheck --check-prefixes=PAL,VI --enable-var-scope %s ; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tonga | FileCheck --check-prefixes=PAL,VI --enable-var-scope %s
; PAL-NOT: .AMDGPU.config ; PAL-NOT: .AMDGPU.config
; PAL-LABEL: {{^}}simple: ; PAL-LABEL: {{^}}simple:
define amdgpu_kernel void @simple(i32 addrspace(1)* %out) { define amdgpu_kernel void @simple(i32 addrspace(1)* %out) {
entry: entry:
store i32 0, i32 addrspace(1)* %out store i32 0, i32 addrspace(1)* %out
ret void ret void
} }
; Check code sequence for amdpal use of scratch for alloca. This is the case ; Check code sequence for amdpal use of scratch for alloca. This is the case
; where the high half of the address comes from s_getpc. ; where the high half of the address comes from s_getpc.
; PAL-LABEL: {{^}}scratch: ; PAL-LABEL: {{^}}scratch:
; PAL: s_getpc_b64 s{{\[}}[[GITPTR:[0-9]+]]: ; PAL: s_getpc_b64 s[[[GITPTR:[0-9]+]]:
; PAL: s_mov_b32 s[[GITPTR]], s0 ; PAL: s_mov_b32 s[[GITPTR]], s0
; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]: ; PAL: s_load_dwordx4 s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s[[[GITPTR]]:
; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]: ; PAL: buffer_store{{.*}}, s[[[SCRATCHDESC]]:
define amdgpu_kernel void @scratch(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) { define amdgpu_kernel void @scratch(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) {
entry: entry:
%v = alloca [2 x i32], addrspace(5) %v = alloca [2 x i32], addrspace(5)
%vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)* %vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)*
store <2 x i32> %in, <2 x i32> addrspace(5)* %vv store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
%e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx
%x = load i32, i32 addrspace(5)* %e %x = load i32, i32 addrspace(5)* %e
store i32 %x, i32 addrspace(5)* %out store i32 %x, i32 addrspace(5)* %out
ret void ret void
} }
; Check code sequence for amdpal use of scratch for alloca. This is the case ; Check code sequence for amdpal use of scratch for alloca. This is the case
; where the amdgpu-git-ptr-high function attribute gives the high half of the ; where the amdgpu-git-ptr-high function attribute gives the high half of the
; address to use. ; address to use.
; Looks like you can't do arithmetic on a filecheck variable, so we can't test ; Looks like you can't do arithmetic on a filecheck variable, so we can't test
; that the s_movk_i32 is into a reg that is one more than the following ; that the s_movk_i32 is into a reg that is one more than the following
; s_mov_b32. ; s_mov_b32.
; PAL-LABEL: {{^}}scratch2: ; PAL-LABEL: {{^}}scratch2:
; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234 ; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234
; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0 ; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0
; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]: ; PAL: s_load_dwordx4 s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s[[[GITPTR]]:
; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]: ; PAL: buffer_store{{.*}}, s[[[SCRATCHDESC]]:
define amdgpu_kernel void @scratch2(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) #0 { define amdgpu_kernel void @scratch2(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) #0 {
entry: entry:
%v = alloca [2 x i32], addrspace(5) %v = alloca [2 x i32], addrspace(5)
%vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)* %vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)*
store <2 x i32> %in, <2 x i32> addrspace(5)* %vv store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
%e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx
%x = load i32, i32 addrspace(5)* %e %x = load i32, i32 addrspace(5)* %e
store i32 %x, i32 addrspace(5)* %out store i32 %x, i32 addrspace(5)* %out
ret void ret void
} }
; Check code sequence for amdpal use of scratch for alloca in a compute shader. ; Check code sequence for amdpal use of scratch for alloca in a compute shader.
; The scratch descriptor is loaded from offset 0x10 of the GIT, rather than offset ; The scratch descriptor is loaded from offset 0x10 of the GIT, rather than offset
; 0 in a graphics shader. ; 0 in a graphics shader.
; Prior to GCN3 s_load_dword offsets are dwords, so the offset will be 0x4. ; Prior to GCN3 s_load_dword offsets are dwords, so the offset will be 0x4.
; PAL-LABEL: {{^}}scratch2_cs: ; PAL-LABEL: {{^}}scratch2_cs:
; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234 ; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234
; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0 ; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0
; CI: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:{{[0-9]+\]}}, 0x4 ; CI: s_load_dwordx4 s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s[[[GITPTR]]:{{[0-9]+\]}}, 0x4
; VI: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:{{[0-9]+\]}}, 0x10 ; VI: s_load_dwordx4 s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s[[[GITPTR]]:{{[0-9]+\]}}, 0x10
; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]: ; PAL: buffer_store{{.*}}, s[[[SCRATCHDESC]]:
define amdgpu_cs void @scratch2_cs(i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <3 x i32> %coord, <2 x i32> %in, i32 %extra, i32 %idx) #0 { define amdgpu_cs void @scratch2_cs(i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <3 x i32> %coord, <2 x i32> %in, i32 %extra, i32 %idx) #0 {
entry: entry:
%v = alloca [3 x i32], addrspace(5) %v = alloca [3 x i32], addrspace(5)
%v0 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 0 %v0 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 0
%v1 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 1 %v1 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 1
store i32 %extra, i32 addrspace(5)* %v0 store i32 %extra, i32 addrspace(5)* %v0
%v1a = bitcast i32 addrspace(5)* %v1 to [2 x i32] addrspace(5)* %v1a = bitcast i32 addrspace(5)* %v1 to [2 x i32] addrspace(5)*
Show All 23 Lines

llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll

; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
; On gfx9 and later, a HS is a merged shader, in which s0-s7 are reserved by the ; On gfx9 and later, a HS is a merged shader, in which s0-s7 are reserved by the
; hardware, so the PAL puts the GIT (global information table) in s8 rather ; hardware, so the PAL puts the GIT (global information table) in s8 rather
; than s0. ; than s0.
; GCN-LABEL: {{^}}_amdgpu_hs_main: ; GCN-LABEL: {{^}}_amdgpu_hs_main:
; GCN: s_getpc_b64 s{{\[}}[[GITPTR:[0-9]+]]: ; GCN: s_getpc_b64 s[[[GITPTR:[0-9]+]]:
; PREGFX9: s_mov_b32 s[[GITPTR]], s0 ; PREGFX9: s_mov_b32 s[[GITPTR]], s0
; GFX9: s_mov_b32 s[[GITPTR]], s8 ; GFX9: s_mov_b32 s[[GITPTR]], s8
define amdgpu_hs void @_amdgpu_hs_main(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3, i32 inreg %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 inreg %arg7, <6 x i32> inreg %arg8) { define amdgpu_hs void @_amdgpu_hs_main(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3, i32 inreg %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 inreg %arg7, <6 x i32> inreg %arg8) {
.entry: .entry:
%__llpc_global_proxy_7.i = alloca [3 x <4 x float>], align 16, addrspace(5) %__llpc_global_proxy_7.i = alloca [3 x <4 x float>], align 16, addrspace(5)
%tmp = icmp ult i32 undef, undef %tmp = icmp ult i32 undef, undef
br i1 %tmp, label %.beginls, label %.endls br i1 %tmp, label %.beginls, label %.endls
Show All 18 Lines

llvm/test/CodeGen/AMDGPU/and.ll

Show First 20 Lines • Show All 196 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) {
%and = and i64 %a, 549756338176 %and = and i64 %a, 549756338176
store i64 %and, i64 addrspace(1)* %out, align 8 store i64 %and, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}s_and_multi_use_constant_i64: ; FUNC-LABEL: {{^}}s_and_multi_use_constant_i64:
; XSI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0x80000{{$}} ; XSI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0x80000{{$}}
; XSI-DAG: s_mov_b32 s[[KHI:[0-9]+]], 0x80{{$}} ; XSI-DAG: s_mov_b32 s[[KHI:[0-9]+]], 0x80{{$}}
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}} ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s[[[KLO]]:[[KHI]]]
define amdgpu_kernel void @s_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { define amdgpu_kernel void @s_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
%and0 = and i64 %a, 549756338176 %and0 = and i64 %a, 549756338176
%and1 = and i64 %b, 549756338176 %and1 = and i64 %b, 549756338176
store volatile i64 %and0, i64 addrspace(1)* %out store volatile i64 %and0, i64 addrspace(1)* %out
store volatile i64 %and1, i64 addrspace(1)* %out store volatile i64 %and1, i64 addrspace(1)* %out
ret void ret void
} }
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid %gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
%a = load i64, i64 addrspace(1)* %gep.a, align 8 %a = load i64, i64 addrspace(1)* %gep.a, align 8
%and = and i64 %a, 1231231234567 %and = and i64 %a, 1231231234567
store i64 %and, i64 addrspace(1)* %out, align 8 store i64 %and, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}v_and_multi_use_constant_i64: ; FUNC-LABEL: {{^}}v_and_multi_use_constant_i64:
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO0:[0-9]+]]:[[HI0:[0-9]+]]{{\]}} ; SI-DAG: buffer_load_dwordx2 v[[[LO0:[0-9]+]]:[[HI0:[0-9]+]]]
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO1:[0-9]+]]:[[HI1:[0-9]+]]{{\]}} ; SI-DAG: buffer_load_dwordx2 v[[[LO1:[0-9]+]]:[[HI1:[0-9]+]]]
; SI-DAG: s_movk_i32 [[KHI:s[0-9]+]], 0x11e{{$}} ; SI-DAG: s_movk_i32 [[KHI:s[0-9]+]], 0x11e{{$}}
; SI-DAG: s_mov_b32 [[KLO:s[0-9]+]], 0xab19b207{{$}} ; SI-DAG: s_mov_b32 [[KLO:s[0-9]+]], 0xab19b207{{$}}
; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO0]] ; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO0]]
; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI0]] ; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI0]]
; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO1]] ; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO1]]
; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI1]] ; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI1]]
; SI: buffer_store_dwordx2 ; SI: buffer_store_dwordx2
; SI: buffer_store_dwordx2 ; SI: buffer_store_dwordx2
define amdgpu_kernel void @v_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { define amdgpu_kernel void @v_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
%a = load volatile i64, i64 addrspace(1)* %aptr %a = load volatile i64, i64 addrspace(1)* %aptr
%b = load volatile i64, i64 addrspace(1)* %aptr %b = load volatile i64, i64 addrspace(1)* %aptr
%and0 = and i64 %a, 1231231234567 %and0 = and i64 %a, 1231231234567
%and1 = and i64 %b, 1231231234567 %and1 = and i64 %b, 1231231234567
store volatile i64 %and0, i64 addrspace(1)* %out store volatile i64 %and0, i64 addrspace(1)* %out
store volatile i64 %and1, i64 addrspace(1)* %out store volatile i64 %and1, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}v_and_multi_use_inline_imm_i64: ; FUNC-LABEL: {{^}}v_and_multi_use_inline_imm_i64:
; SI: buffer_load_dwordx2 v{{\[}}[[LO0:[0-9]+]]:[[HI0:[0-9]+]]{{\]}} ; SI: buffer_load_dwordx2 v[[[LO0:[0-9]+]]:[[HI0:[0-9]+]]]
; SI-NOT: and ; SI-NOT: and
; SI: buffer_load_dwordx2 v{{\[}}[[LO1:[0-9]+]]:[[HI1:[0-9]+]]{{\]}} ; SI: buffer_load_dwordx2 v[[[LO1:[0-9]+]]:[[HI1:[0-9]+]]]
; SI-NOT: and ; SI-NOT: and
; SI: v_and_b32_e32 v[[RESLO0:[0-9]+]], 63, v[[LO0]] ; SI: v_and_b32_e32 v[[RESLO0:[0-9]+]], 63, v[[LO0]]
; SI: v_and_b32_e32 v[[RESLO1:[0-9]+]], 63, v[[LO1]] ; SI: v_and_b32_e32 v[[RESLO1:[0-9]+]], 63, v[[LO1]]
; SI-NOT: and ; SI-NOT: and
; SI: buffer_store_dwordx2 v{{\[}}[[RESLO0]] ; SI: buffer_store_dwordx2 v[[[RESLO0]]
; SI: buffer_store_dwordx2 v{{\[}}[[RESLO1]] ; SI: buffer_store_dwordx2 v[[[RESLO1]]
define amdgpu_kernel void @v_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { define amdgpu_kernel void @v_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
%a = load volatile i64, i64 addrspace(1)* %aptr %a = load volatile i64, i64 addrspace(1)* %aptr
%b = load volatile i64, i64 addrspace(1)* %aptr %b = load volatile i64, i64 addrspace(1)* %aptr
%and0 = and i64 %a, 63 %and0 = and i64 %a, 63
%and1 = and i64 %b, 63 %and1 = and i64 %b, 63
store volatile i64 %and0, i64 addrspace(1)* %out store volatile i64 %and0, i64 addrspace(1)* %out
store volatile i64 %and1, i64 addrspace(1)* %out store volatile i64 %and1, i64 addrspace(1)* %out
ret void ret void
Show All 26 Linesdefine amdgpu_kernel void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
%a = load i64, i64 addrspace(1)* %gep.a, align 8 %a = load i64, i64 addrspace(1)* %gep.a, align 8
%and = and i64 %a, 64 %and = and i64 %a, 64
store i64 %and, i64 addrspace(1)* %out, align 8 store i64 %and, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; FIXME: Should be able to reduce load width ; FIXME: Should be able to reduce load width
; FUNC-LABEL: {{^}}v_and_inline_neg_imm_i64: ; FUNC-LABEL: {{^}}v_and_inline_neg_imm_i64:
; SI: {{buffer|flat}}_load_dwordx2 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} ; SI: {{buffer|flat}}_load_dwordx2 v[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]]
; SI-NOT: and ; SI-NOT: and
; SI: v_and_b32_e32 v[[VAL_LO]], -8, v[[VAL_LO]] ; SI: v_and_b32_e32 v[[VAL_LO]], -8, v[[VAL_LO]]
; SI-NOT: and ; SI-NOT: and
; SI: buffer_store_dwordx2 v{{\[}}[[VAL_LO]]:[[VAL_HI]]{{\]}} ; SI: buffer_store_dwordx2 v[[[VAL_LO]]:[[VAL_HI]]]
define amdgpu_kernel void @v_and_inline_neg_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { define amdgpu_kernel void @v_and_inline_neg_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid %gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
%a = load i64, i64 addrspace(1)* %gep.a, align 8 %a = load i64, i64 addrspace(1)* %gep.a, align 8
%and = and i64 %a, -8 %and = and i64 %a, -8
store i64 %and, i64 addrspace(1)* %out, align 8 store i64 %and, i64 addrspace(1)* %out, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 213 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll

Show All 23 Linesdefine amdgpu_kernel void @lds_atomic_cmpxchg_ret_i32_offset(i32 addrspace(1)* %out, [8 x i32], i32 addrspace(3)* %ptr, [8 x i32], i32 %swap) nounwind {
ret void ret void
} }
; GCN-LABEL: {{^}}lds_atomic_cmpxchg_ret_i64_offset: ; GCN-LABEL: {{^}}lds_atomic_cmpxchg_ret_i64_offset:
; GFX9-NOT: m0 ; GFX9-NOT: m0
; SICIVI-DAG: s_mov_b32 m0 ; SICIVI-DAG: s_mov_b32 m0
; SICI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SICI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
; SICI-DAG: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd ; SICI-DAG: s_load_dwordx2 s[[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c ; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
; GFX89-DAG: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34 ; GFX89-DAG: s_load_dwordx2 s[[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x34
; GCN-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7 ; GCN-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7
; GCN-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0 ; GCN-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0
; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]] ; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]] ; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
; GCN: ds_cmpst_rtn_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32 ; GCN: ds_cmpst_rtn_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v[[[LOVCMP]]:[[HIVCMP]]], v[[[LOSWAPV]]:[[HISWAPV]]] offset:32
; GCN: [[RESULT]] ; GCN: [[RESULT]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @lds_atomic_cmpxchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr, i64 %swap) nounwind { define amdgpu_kernel void @lds_atomic_cmpxchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr, i64 %swap) nounwind {
%gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4 %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
%pair = cmpxchg i64 addrspace(3)* %gep, i64 7, i64 %swap seq_cst monotonic %pair = cmpxchg i64 addrspace(3)* %gep, i64 7, i64 %swap seq_cst monotonic
%result = extractvalue { i64, i1 } %pair, 0 %result = extractvalue { i64, i1 } %pair, 0
store i64 %result, i64 addrspace(1)* %out, align 8 store i64 %result, i64 addrspace(1)* %out, align 8
ret void ret void
Show All 36 Linesdefine amdgpu_kernel void @lds_atomic_cmpxchg_noret_i32_offset(i32 addrspace(3)* %ptr, [8 x i32], i32 %swap) nounwind {
ret void ret void
} }
; GCN-LABEL: {{^}}lds_atomic_cmpxchg_noret_i64_offset: ; GCN-LABEL: {{^}}lds_atomic_cmpxchg_noret_i64_offset:
; GFX9-NOT: m0 ; GFX9-NOT: m0
; SICIVI-DAG: s_mov_b32 m0 ; SICIVI-DAG: s_mov_b32 m0
; SICI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9 ; SICI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
; SICI-DAG: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SICI-DAG: s_load_dwordx2 s[[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24 ; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24
; GFX89-DAG: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c ; GFX89-DAG: s_load_dwordx2 s[[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
; GCN-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7 ; GCN-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7
; GCN-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0 ; GCN-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0
; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]] ; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]] ; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
; GCN: ds_cmpst_b64 [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32 ; GCN: ds_cmpst_b64 [[VPTR]], v[[[LOVCMP]]:[[HIVCMP]]], v[[[LOSWAPV]]:[[HISWAPV]]] offset:32
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @lds_atomic_cmpxchg_noret_i64_offset(i64 addrspace(3)* %ptr, i64 %swap) nounwind { define amdgpu_kernel void @lds_atomic_cmpxchg_noret_i64_offset(i64 addrspace(3)* %ptr, i64 %swap) nounwind {
%gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4 %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
%pair = cmpxchg i64 addrspace(3)* %gep, i64 7, i64 %swap seq_cst monotonic %pair = cmpxchg i64 addrspace(3)* %gep, i64 7, i64 %swap seq_cst monotonic
%result = extractvalue { i64, i1 } %pair, 0 %result = extractvalue { i64, i1 } %pair, 0
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll

; RUN: llc -march=amdgcn -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX7LESS %s ; RUN: llc -march=amdgcn -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX7LESS %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX89 %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX89 %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX89 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX89 %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX10 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX10 %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN32,GFX8MORE,GFX8MORE32,GFX10 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN32,GFX8MORE,GFX8MORE32,GFX10 %s
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()
declare i32 @llvm.amdgcn.raw.buffer.atomic.add(i32, <4 x i32>, i32, i32, i32 immarg) declare i32 @llvm.amdgcn.raw.buffer.atomic.add(i32, <4 x i32>, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.struct.buffer.atomic.add(i32, <4 x i32>, i32, i32, i32, i32 immarg) declare i32 @llvm.amdgcn.struct.buffer.atomic.add(i32, <4 x i32>, i32, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.raw.buffer.atomic.sub(i32, <4 x i32>, i32, i32, i32 immarg) declare i32 @llvm.amdgcn.raw.buffer.atomic.sub(i32, <4 x i32>, i32, i32, i32 immarg)
; Show what the atomic optimization pass will do for raw buffers. ; Show what the atomic optimization pass will do for raw buffers.
; GCN-LABEL: add_i32_constant: ; GCN-LABEL: add_i32_constant:
; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec ; GCN64: s_mov_b64 s[[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]], exec
; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] ; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]]
; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc ; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc
; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s[[[exec_lo]]:[[exec_hi]]]
; GCN: s_mul_i32 s[[value:[0-9]+]], s[[popcount]], 5 ; GCN: s_mul_i32 s[[value:[0-9]+]], s[[popcount]], 5
; GCN: v_mov_b32_e32 v[[data:[0-9]+]], s[[value]] ; GCN: v_mov_b32_e32 v[[data:[0-9]+]], s[[value]]
; GCN: buffer_atomic_add v[[data]] ; GCN: buffer_atomic_add v[[data]]
define amdgpu_kernel void @add_i32_constant(i32 addrspace(1)* %out, <4 x i32> %inout) { define amdgpu_kernel void @add_i32_constant(i32 addrspace(1)* %out, <4 x i32> %inout) {
entry: entry:
%old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0) %old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0)
store i32 %old, i32 addrspace(1)* %out store i32 %old, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: add_i32_uniform: ; GCN-LABEL: add_i32_uniform:
; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec ; GCN64: s_mov_b64 s[[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]], exec
; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] ; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]]
; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc ; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc
; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s[[[exec_lo]]:[[exec_hi]]]
; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]] ; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
; GCN: buffer_atomic_add v[[value]] ; GCN: buffer_atomic_add v[[value]]
define amdgpu_kernel void @add_i32_uniform(i32 addrspace(1)* %out, <4 x i32> %inout, i32 %additive) { define amdgpu_kernel void @add_i32_uniform(i32 addrspace(1)* %out, <4 x i32> %inout, i32 %additive) {
entry: entry:
%old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 %additive, <4 x i32> %inout, i32 0, i32 0, i32 0) %old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 %additive, <4 x i32> %inout, i32 0, i32 0, i32 0)
store i32 %old, i32 addrspace(1)* %out store i32 %old, i32 addrspace(1)* %out
ret void ret void
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Linesentry:
%lane = call i32 @llvm.amdgcn.workitem.id.x() %lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 1, <4 x i32> %inout, i32 %lane, i32 0, i32 0) %old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 1, <4 x i32> %inout, i32 %lane, i32 0, i32 0)
store i32 %old, i32 addrspace(1)* %out store i32 %old, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: sub_i32_constant: ; GCN-LABEL: sub_i32_constant:
; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec ; GCN64: s_mov_b64 s[[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]], exec
; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] ; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]]
; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc ; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc
; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s[[[exec_lo]]:[[exec_hi]]]
; GCN: s_mul_i32 s[[value:[0-9]+]], s[[popcount]], 5 ; GCN: s_mul_i32 s[[value:[0-9]+]], s[[popcount]], 5
; GCN: v_mov_b32_e32 v[[data:[0-9]+]], s[[value]] ; GCN: v_mov_b32_e32 v[[data:[0-9]+]], s[[value]]
; GCN: buffer_atomic_sub v[[data]] ; GCN: buffer_atomic_sub v[[data]]
define amdgpu_kernel void @sub_i32_constant(i32 addrspace(1)* %out, <4 x i32> %inout) { define amdgpu_kernel void @sub_i32_constant(i32 addrspace(1)* %out, <4 x i32> %inout) {
entry: entry:
%old = call i32 @llvm.amdgcn.raw.buffer.atomic.sub(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0) %old = call i32 @llvm.amdgcn.raw.buffer.atomic.sub(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0)
store i32 %old, i32 addrspace(1)* %out store i32 %old, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: sub_i32_uniform: ; GCN-LABEL: sub_i32_uniform:
; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec ; GCN64: s_mov_b64 s[[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]], exec
; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] ; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]]
; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc ; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc
; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s[[[exec_lo]]:[[exec_hi]]]
; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]] ; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
; GCN: buffer_atomic_sub v[[value]] ; GCN: buffer_atomic_sub v[[value]]
define amdgpu_kernel void @sub_i32_uniform(i32 addrspace(1)* %out, <4 x i32> %inout, i32 %subitive) { define amdgpu_kernel void @sub_i32_uniform(i32 addrspace(1)* %out, <4 x i32> %inout, i32 %subitive) {
entry: entry:
%old = call i32 @llvm.amdgcn.raw.buffer.atomic.sub(i32 %subitive, <4 x i32> %inout, i32 0, i32 0, i32 0) %old = call i32 @llvm.amdgcn.raw.buffer.atomic.sub(i32 %subitive, <4 x i32> %inout, i32 0, i32 0, i32 0)
store i32 %old, i32 addrspace(1)* %out store i32 %old, i32 addrspace(1)* %out
ret void ret void
Show All 40 Lines

llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll

; RUN: llc -march=amdgcn -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX7LESS %s ; RUN: llc -march=amdgcn -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX7LESS %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX89,DPPCOMB %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX89,DPPCOMB %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX89,DPPCOMB %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX89,DPPCOMB %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX10 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX10 %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN32,GFX8MORE,GFX8MORE32,GFX10 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN32,GFX8MORE,GFX8MORE32,GFX10 %s
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()
declare i32 @llvm.amdgcn.raw.buffer.atomic.add(i32, <4 x i32>, i32, i32, i32) declare i32 @llvm.amdgcn.raw.buffer.atomic.add(i32, <4 x i32>, i32, i32, i32)
declare i32 @llvm.amdgcn.raw.buffer.atomic.sub(i32, <4 x i32>, i32, i32, i32) declare i32 @llvm.amdgcn.raw.buffer.atomic.sub(i32, <4 x i32>, i32, i32, i32)
; Show what the atomic optimization pass will do for raw buffers. ; Show what the atomic optimization pass will do for raw buffers.
; GCN-LABEL: add_i32_constant: ; GCN-LABEL: add_i32_constant:
; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec ; GCN64: s_mov_b64 s[[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]], exec
; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] ; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]]
; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc ; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc
; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s[[[exec_lo]]:[[exec_hi]]]
; GCN: s_mul_i32 s[[popcount]], s[[popcount]], 5 ; GCN: s_mul_i32 s[[popcount]], s[[popcount]], 5
; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[popcount]] ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[popcount]]
; GCN: buffer_atomic_add v[[value]] ; GCN: buffer_atomic_add v[[value]]
define amdgpu_kernel void @add_i32_constant(i32 addrspace(1)* %out, <4 x i32> %inout) { define amdgpu_kernel void @add_i32_constant(i32 addrspace(1)* %out, <4 x i32> %inout) {
entry: entry:
%old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0) %old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0)
store i32 %old, i32 addrspace(1)* %out store i32 %old, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: add_i32_uniform: ; GCN-LABEL: add_i32_uniform:
; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec ; GCN64: s_mov_b64 s[[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]], exec
; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] ; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]]
; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc ; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc
; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s[[[exec_lo]]:[[exec_hi]]]
; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]] ; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
; GCN: buffer_atomic_add v[[value]] ; GCN: buffer_atomic_add v[[value]]
define amdgpu_kernel void @add_i32_uniform(i32 addrspace(1)* %out, <4 x i32> %inout, i32 %additive) { define amdgpu_kernel void @add_i32_uniform(i32 addrspace(1)* %out, <4 x i32> %inout, i32 %additive) {
entry: entry:
%old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 %additive, <4 x i32> %inout, i32 0, i32 0, i32 0) %old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 %additive, <4 x i32> %inout, i32 0, i32 0, i32 0)
store i32 %old, i32 addrspace(1)* %out store i32 %old, i32 addrspace(1)* %out
ret void ret void
Show All 30 Linesentry:
%lane = call i32 @llvm.amdgcn.workitem.id.x() %lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 1, <4 x i32> %inout, i32 %lane, i32 0, i32 0) %old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 1, <4 x i32> %inout, i32 %lane, i32 0, i32 0)
store i32 %old, i32 addrspace(1)* %out store i32 %old, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: sub_i32_constant: ; GCN-LABEL: sub_i32_constant:
; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec ; GCN64: s_mov_b64 s[[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]], exec
; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] ; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]]
; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc ; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc
; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s[[[exec_lo]]:[[exec_hi]]]
; GCN: s_mul_i32 s[[popcount]], s[[popcount]], 5 ; GCN: s_mul_i32 s[[popcount]], s[[popcount]], 5
; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[popcount]] ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[popcount]]
; GCN: buffer_atomic_sub v[[value]] ; GCN: buffer_atomic_sub v[[value]]
define amdgpu_kernel void @sub_i32_constant(i32 addrspace(1)* %out, <4 x i32> %inout) { define amdgpu_kernel void @sub_i32_constant(i32 addrspace(1)* %out, <4 x i32> %inout) {
entry: entry:
%old = call i32 @llvm.amdgcn.raw.buffer.atomic.sub(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0) %old = call i32 @llvm.amdgcn.raw.buffer.atomic.sub(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0)
store i32 %old, i32 addrspace(1)* %out store i32 %old, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: sub_i32_uniform: ; GCN-LABEL: sub_i32_uniform:
; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec ; GCN64: s_mov_b64 s[[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]], exec
; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] ; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]]
; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc ; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc
; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s[[[exec_lo]]:[[exec_hi]]]
; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]] ; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
; GCN: buffer_atomic_sub v[[value]] ; GCN: buffer_atomic_sub v[[value]]
define amdgpu_kernel void @sub_i32_uniform(i32 addrspace(1)* %out, <4 x i32> %inout, i32 %subitive) { define amdgpu_kernel void @sub_i32_uniform(i32 addrspace(1)* %out, <4 x i32> %inout, i32 %subitive) {
entry: entry:
%old = call i32 @llvm.amdgcn.raw.buffer.atomic.sub(i32 %subitive, <4 x i32> %inout, i32 0, i32 0, i32 0) %old = call i32 @llvm.amdgcn.raw.buffer.atomic.sub(i32 %subitive, <4 x i32> %inout, i32 0, i32 0, i32 0)
store i32 %old, i32 addrspace(1)* %out store i32 %old, i32 addrspace(1)* %out
ret void ret void
Show All 35 Lines

llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll

; RUN: llc -march=amdgcn -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX7LESS %s ; RUN: llc -march=amdgcn -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX7LESS %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX89,DPPCOMB %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX89,DPPCOMB %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX89,DPPCOMB %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX89,DPPCOMB %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX10 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX10 %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN32,GFX8MORE,GFX8MORE32,GFX10 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN32,GFX8MORE,GFX8MORE32,GFX10 %s
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()
declare i32 @llvm.amdgcn.struct.buffer.atomic.add(i32, <4 x i32>, i32, i32, i32, i32) declare i32 @llvm.amdgcn.struct.buffer.atomic.add(i32, <4 x i32>, i32, i32, i32, i32)
declare i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32, <4 x i32>, i32, i32, i32, i32) declare i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32, <4 x i32>, i32, i32, i32, i32)
; Show what the atomic optimization pass will do for struct buffers. ; Show what the atomic optimization pass will do for struct buffers.
; GCN-LABEL: add_i32_constant: ; GCN-LABEL: add_i32_constant:
; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec ; GCN64: s_mov_b64 s[[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]], exec
; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] ; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]]
; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc ; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc
; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s[[[exec_lo]]:[[exec_hi]]]
; GCN: s_mul_i32 s[[popcount]], s[[popcount]], 5 ; GCN: s_mul_i32 s[[popcount]], s[[popcount]], 5
; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[popcount]] ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[popcount]]
; GCN: buffer_atomic_add v[[value]] ; GCN: buffer_atomic_add v[[value]]
define amdgpu_kernel void @add_i32_constant(i32 addrspace(1)* %out, <4 x i32> %inout) { define amdgpu_kernel void @add_i32_constant(i32 addrspace(1)* %out, <4 x i32> %inout) {
entry: entry:
%old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0) %old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0)
store i32 %old, i32 addrspace(1)* %out store i32 %old, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: add_i32_uniform: ; GCN-LABEL: add_i32_uniform:
; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec ; GCN64: s_mov_b64 s[[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]], exec
; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] ; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]]
; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc ; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc
; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s[[[exec_lo]]:[[exec_hi]]]
; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]] ; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
; GCN: buffer_atomic_add v[[value]] ; GCN: buffer_atomic_add v[[value]]
define amdgpu_kernel void @add_i32_uniform(i32 addrspace(1)* %out, <4 x i32> %inout, i32 %additive) { define amdgpu_kernel void @add_i32_uniform(i32 addrspace(1)* %out, <4 x i32> %inout, i32 %additive) {
entry: entry:
%old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 %additive, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0) %old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 %additive, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0)
store i32 %old, i32 addrspace(1)* %out store i32 %old, i32 addrspace(1)* %out
ret void ret void
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesentry:
%lane = call i32 @llvm.amdgcn.workitem.id.x() %lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 1, <4 x i32> %inout, i32 0, i32 %lane, i32 0, i32 0) %old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 1, <4 x i32> %inout, i32 0, i32 %lane, i32 0, i32 0)
store i32 %old, i32 addrspace(1)* %out store i32 %old, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: sub_i32_constant: ; GCN-LABEL: sub_i32_constant:
; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec ; GCN64: s_mov_b64 s[[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]], exec
; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] ; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]]
; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc ; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc
; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s[[[exec_lo]]:[[exec_hi]]]
; GCN: s_mul_i32 s[[popcount]], s[[popcount]], 5 ; GCN: s_mul_i32 s[[popcount]], s[[popcount]], 5
; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[popcount]] ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[popcount]]
; GCN: buffer_atomic_sub v[[value]] ; GCN: buffer_atomic_sub v[[value]]
define amdgpu_kernel void @sub_i32_constant(i32 addrspace(1)* %out, <4 x i32> %inout) { define amdgpu_kernel void @sub_i32_constant(i32 addrspace(1)* %out, <4 x i32> %inout) {
entry: entry:
%old = call i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0) %old = call i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0)
store i32 %old, i32 addrspace(1)* %out store i32 %old, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: sub_i32_uniform: ; GCN-LABEL: sub_i32_uniform:
; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo ; GCN32: s_mov_b32 s[[exec_lo:[0-9]+]], exec_lo
; GCN64: s_mov_b64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, exec ; GCN64: s_mov_b64 s[[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]], exec
; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 ; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] ; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]]
; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] ; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]]
; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc ; GCN: s_and_saveexec_b{{32|64}} s[[exec:\[?[0-9:]+\]?]], vcc
; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] ; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]]
; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} ; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s[[[exec_lo]]:[[exec_hi]]]
; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]] ; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]]
; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
; GCN: buffer_atomic_sub v[[value]] ; GCN: buffer_atomic_sub v[[value]]
define amdgpu_kernel void @sub_i32_uniform(i32 addrspace(1)* %out, <4 x i32> %inout, i32 %subitive) { define amdgpu_kernel void @sub_i32_uniform(i32 addrspace(1)* %out, <4 x i32> %inout, i32 %subitive) {
entry: entry:
%old = call i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32 %subitive, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0) %old = call i32 @llvm.amdgcn.struct.buffer.atomic.sub(i32 %subitive, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 0)
store i32 %old, i32 addrspace(1)* %out store i32 %old, i32 addrspace(1)* %out
ret void ret void
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/bfe-combine.ll

; RUN: llc -march=amdgcn -mcpu=fiji -amdgpu-sdwa-peephole=0 < %s | FileCheck --check-prefix=GCN --check-prefix=VI %s ; RUN: llc -march=amdgcn -mcpu=fiji -amdgpu-sdwa-peephole=0 < %s | FileCheck --check-prefix=GCN --check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck --check-prefix=GCN --check-prefix=VI-SDWA %s ; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck --check-prefix=GCN --check-prefix=VI-SDWA %s
; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck --check-prefix=GCN --check-prefix=CI %s ; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck --check-prefix=GCN --check-prefix=CI %s
; GCN-LABEL: {{^}}bfe_combine8: ; GCN-LABEL: {{^}}bfe_combine8:
; VI: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 8, 8 ; VI: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 8, 8
; VI: v_lshlrev_b32_e32 v[[ADDRBASE:[0-9]+]], 2, v[[BFE]] ; VI: v_lshlrev_b32_e32 v[[ADDRBASE:[0-9]+]], 2, v[[BFE]]
; VI-SDWA: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 2 ; VI-SDWA: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 2
; VI-SDWA: v_lshlrev_b32_sdwa v[[ADDRBASE:[0-9]+]], v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 ; VI-SDWA: v_lshlrev_b32_sdwa v[[ADDRBASE:[0-9]+]], v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; CI: v_lshrrev_b32_e32 v[[SHR:[0-9]+]], 6, v{{[0-9]+}} ; CI: v_lshrrev_b32_e32 v[[SHR:[0-9]+]], 6, v{{[0-9]+}}
; CI: v_and_b32_e32 v[[ADDRLO:[0-9]+]], 0x3fc, v[[SHR]] ; CI: v_and_b32_e32 v[[ADDRLO:[0-9]+]], 0x3fc, v[[SHR]]
; VI: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]] ; VI: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]]
; VI-SDWA: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]] ; VI-SDWA: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]]
; GCN: load_dword v{{[0-9]+}}, v{{\[}}[[ADDRLO]]: ; GCN: load_dword v{{[0-9]+}}, v[[[ADDRLO]]:
define amdgpu_kernel void @bfe_combine8(i32 addrspace(1)* nocapture %arg, i32 %x) { define amdgpu_kernel void @bfe_combine8(i32 addrspace(1)* nocapture %arg, i32 %x) {
%id = tail call i32 @llvm.amdgcn.workitem.id.x() #2 %id = tail call i32 @llvm.amdgcn.workitem.id.x() #2
%idx = add i32 %x, %id %idx = add i32 %x, %id
%srl = lshr i32 %idx, 8 %srl = lshr i32 %idx, 8
%and = and i32 %srl, 255 %and = and i32 %srl, 255
%ptr = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %and %ptr = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %and
%val = load i32, i32 addrspace(1)* %ptr, align 4 %val = load i32, i32 addrspace(1)* %ptr, align 4
store i32 %val, i32 addrspace(1)* %arg, align 4 store i32 %val, i32 addrspace(1)* %arg, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}bfe_combine16: ; GCN-LABEL: {{^}}bfe_combine16:
; VI: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 16, 16 ; VI: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 16, 16
; VI: v_lshlrev_b32_e32 v[[ADDRBASE:[0-9]+]], {{[^,]+}}, v[[BFE]] ; VI: v_lshlrev_b32_e32 v[[ADDRBASE:[0-9]+]], {{[^,]+}}, v[[BFE]]
; VI-SDWA: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 15 ; VI-SDWA: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 15
; VI-SDWA: v_lshlrev_b32_sdwa v[[ADDRBASE1:[0-9]+]], v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-SDWA: v_lshlrev_b32_sdwa v[[ADDRBASE1:[0-9]+]], v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-SDWA: v_lshlrev_b64 v{{\[}}[[ADDRBASE:[0-9]+]]:{{[^\]+}}], 2, v{{\[}}[[ADDRBASE1]]:{{[^\]+}}] ; VI-SDWA: v_lshlrev_b64 v[[[ADDRBASE:[0-9]+]]:{{[^\]+}}], 2, v[[[ADDRBASE1]]:{{[^\]+}}]
; VI-SDWA: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]] ; VI-SDWA: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]]
; CI: v_lshrrev_b32_e32 v[[SHR:[0-9]+]], 1, v{{[0-9]+}} ; CI: v_lshrrev_b32_e32 v[[SHR:[0-9]+]], 1, v{{[0-9]+}}
; CI: v_and_b32_e32 v[[AND:[0-9]+]], 0x7fff8000, v[[SHR]] ; CI: v_and_b32_e32 v[[AND:[0-9]+]], 0x7fff8000, v[[SHR]]
; CI: v_lshl_b64 v{{\[}}[[ADDRLO:[0-9]+]]:{{[^\]+}}], v{{\[}}[[AND]]:{{[^\]+}}], 2 ; CI: v_lshl_b64 v[[[ADDRLO:[0-9]+]]:{{[^\]+}}], v[[[AND]]:{{[^\]+}}], 2
; VI: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]] ; VI: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]]
; GCN: load_dword v{{[0-9]+}}, v{{\[}}[[ADDRLO]]: ; GCN: load_dword v{{[0-9]+}}, v[[[ADDRLO]]:
define amdgpu_kernel void @bfe_combine16(i32 addrspace(1)* nocapture %arg, i32 %x) { define amdgpu_kernel void @bfe_combine16(i32 addrspace(1)* nocapture %arg, i32 %x) {
%id = tail call i32 @llvm.amdgcn.workitem.id.x() #2 %id = tail call i32 @llvm.amdgcn.workitem.id.x() #2
%idx = add i32 %x, %id %idx = add i32 %x, %id
%srl = lshr i32 %idx, 1 %srl = lshr i32 %idx, 1
%and = and i32 %srl, 2147450880 %and = and i32 %srl, 2147450880
%ptr = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %and %ptr = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %and
%val = load i32, i32 addrspace(1)* %ptr, align 4 %val = load i32, i32 addrspace(1)* %ptr, align 4
store i32 %val, i32 addrspace(1)* %arg, align 4 store i32 %val, i32 addrspace(1)* %arg, align 4
ret void ret void
} }
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1

llvm/test/CodeGen/AMDGPU/bfe-patterns.ll

Show All 39 Linesdefine amdgpu_kernel void @v_ubfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #1 {
%shl = shl i32 %src, %sub %shl = shl i32 %src, %sub
%bfe = lshr i32 %shl, %sub %bfe = lshr i32 %shl, %sub
store i32 %bfe, i32 addrspace(1)* %out.gep store i32 %bfe, i32 addrspace(1)* %out.gep
store volatile i32 %shl, i32 addrspace(1)* undef store volatile i32 %shl, i32 addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}s_ubfe_sub_i32: ; GCN-LABEL: {{^}}s_ubfe_sub_i32:
; GCN: s_load_dwordx2 s{{\[}}[[SRC:[0-9]+]]:[[WIDTH:[0-9]+]]{{\]}}, s[0:1], {{0xb|0x2c}} ; GCN: s_load_dwordx2 s[[[SRC:[0-9]+]]:[[WIDTH:[0-9]+]]], s[0:1], {{0xb|0x2c}}
; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]] ; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]]
; GCN: s_lshl_b32 [[TMP:s[0-9]+]], s[[SRC]], [[SUB]] ; GCN: s_lshl_b32 [[TMP:s[0-9]+]], s[[SRC]], [[SUB]]
; GCN: s_lshr_b32 s{{[0-9]+}}, [[TMP]], [[SUB]] ; GCN: s_lshr_b32 s{{[0-9]+}}, [[TMP]], [[SUB]]
define amdgpu_kernel void @s_ubfe_sub_i32(i32 addrspace(1)* %out, i32 %src, i32 %width) #1 { define amdgpu_kernel void @s_ubfe_sub_i32(i32 addrspace(1)* %out, i32 %src, i32 %width) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
%sub = sub i32 32, %width %sub = sub i32 32, %width
%shl = shl i32 %src, %sub %shl = shl i32 %src, %sub
%bfe = lshr i32 %shl, %sub %bfe = lshr i32 %shl, %sub
store i32 %bfe, i32 addrspace(1)* %out.gep store i32 %bfe, i32 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}s_ubfe_sub_multi_use_shl_i32: ; GCN-LABEL: {{^}}s_ubfe_sub_multi_use_shl_i32:
; GCN: s_load_dwordx2 s{{\[}}[[SRC:[0-9]+]]:[[WIDTH:[0-9]+]]{{\]}}, s[0:1], {{0xb|0x2c}} ; GCN: s_load_dwordx2 s[[[SRC:[0-9]+]]:[[WIDTH:[0-9]+]]], s[0:1], {{0xb|0x2c}}
; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]] ; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]]
; GCN: s_lshl_b32 [[SHL:s[0-9]+]], s[[SRC]], [[SUB]] ; GCN: s_lshl_b32 [[SHL:s[0-9]+]], s[[SRC]], [[SUB]]
; GCN: s_lshr_b32 s{{[0-9]+}}, [[SHL]], [[SUB]] ; GCN: s_lshr_b32 s{{[0-9]+}}, [[SHL]], [[SUB]]
define amdgpu_kernel void @s_ubfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 %src, i32 %width) #1 { define amdgpu_kernel void @s_ubfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 %src, i32 %width) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
%sub = sub i32 32, %width %sub = sub i32 32, %width
%shl = shl i32 %src, %sub %shl = shl i32 %src, %sub
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_sbfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #1 {
%shl = shl i32 %src, %sub %shl = shl i32 %src, %sub
%bfe = ashr i32 %shl, %sub %bfe = ashr i32 %shl, %sub
store i32 %bfe, i32 addrspace(1)* %out.gep store i32 %bfe, i32 addrspace(1)* %out.gep
store volatile i32 %shl, i32 addrspace(1)* undef store volatile i32 %shl, i32 addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}s_sbfe_sub_i32: ; GCN-LABEL: {{^}}s_sbfe_sub_i32:
; GCN: s_load_dwordx2 s{{\[}}[[SRC:[0-9]+]]:[[WIDTH:[0-9]+]]{{\]}}, s[0:1], {{0xb|0x2c}} ; GCN: s_load_dwordx2 s[[[SRC:[0-9]+]]:[[WIDTH:[0-9]+]]], s[0:1], {{0xb|0x2c}}
; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]] ; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]]
; GCN: s_lshl_b32 [[TMP:s[0-9]+]], s[[SRC]], [[SUB]] ; GCN: s_lshl_b32 [[TMP:s[0-9]+]], s[[SRC]], [[SUB]]
; GCN: s_ashr_i32 s{{[0-9]+}}, [[TMP]], [[SUB]] ; GCN: s_ashr_i32 s{{[0-9]+}}, [[TMP]], [[SUB]]
define amdgpu_kernel void @s_sbfe_sub_i32(i32 addrspace(1)* %out, i32 %src, i32 %width) #1 { define amdgpu_kernel void @s_sbfe_sub_i32(i32 addrspace(1)* %out, i32 %src, i32 %width) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
%sub = sub i32 32, %width %sub = sub i32 32, %width
%shl = shl i32 %src, %sub %shl = shl i32 %src, %sub
%bfe = ashr i32 %shl, %sub %bfe = ashr i32 %shl, %sub
store i32 %bfe, i32 addrspace(1)* %out.gep store i32 %bfe, i32 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}s_sbfe_sub_multi_use_shl_i32: ; GCN-LABEL: {{^}}s_sbfe_sub_multi_use_shl_i32:
; GCN: s_load_dwordx2 s{{\[}}[[SRC:[0-9]+]]:[[WIDTH:[0-9]+]]{{\]}}, s[0:1], {{0xb|0x2c}} ; GCN: s_load_dwordx2 s[[[SRC:[0-9]+]]:[[WIDTH:[0-9]+]]], s[0:1], {{0xb|0x2c}}
; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]] ; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]]
; GCN: s_lshl_b32 [[SHL:s[0-9]+]], s[[SRC]], [[SUB]] ; GCN: s_lshl_b32 [[SHL:s[0-9]+]], s[[SRC]], [[SUB]]
; GCN: s_ashr_i32 s{{[0-9]+}}, [[SHL]], [[SUB]] ; GCN: s_ashr_i32 s{{[0-9]+}}, [[SHL]], [[SUB]]
define amdgpu_kernel void @s_sbfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 %src, i32 %width) #1 { define amdgpu_kernel void @s_sbfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 %src, i32 %width) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
%sub = sub i32 32, %width %sub = sub i32 32, %width
%shl = shl i32 %src, %sub %shl = shl i32 %src, %sub
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llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll

Show All 9 Lines
define amdgpu_kernel void @materialize_0_i32(i32 addrspace(1)* %out) { define amdgpu_kernel void @materialize_0_i32(i32 addrspace(1)* %out) {
store i32 0, i32 addrspace(1)* %out store i32 0, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_0_i64: ; GCN-LABEL: {{^}}materialize_0_i64:
; GCN: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}}
; GCN: v_mov_b32_e32 v[[HIK:[0-9]+]], v[[LOK]]{{$}} ; GCN: v_mov_b32_e32 v[[HIK:[0-9]+]], v[[LOK]]{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LOK]]:[[HIK]]]
define amdgpu_kernel void @materialize_0_i64(i64 addrspace(1)* %out) { define amdgpu_kernel void @materialize_0_i64(i64 addrspace(1)* %out) {
store i64 0, i64 addrspace(1)* %out store i64 0, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_neg1_i32: ; GCN-LABEL: {{^}}materialize_neg1_i32:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], -1{{$}} ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], -1{{$}}
; GCN: buffer_store_dword [[K]] ; GCN: buffer_store_dword [[K]]
define amdgpu_kernel void @materialize_neg1_i32(i32 addrspace(1)* %out) { define amdgpu_kernel void @materialize_neg1_i32(i32 addrspace(1)* %out) {
store i32 -1, i32 addrspace(1)* %out store i32 -1, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_neg1_i64: ; GCN-LABEL: {{^}}materialize_neg1_i64:
; GCN: v_mov_b32_e32 v[[LOK:[0-9]+]], -1{{$}} ; GCN: v_mov_b32_e32 v[[LOK:[0-9]+]], -1{{$}}
; GCN: v_mov_b32_e32 v[[HIK:[0-9]+]], v[[LOK]]{{$}} ; GCN: v_mov_b32_e32 v[[HIK:[0-9]+]], v[[LOK]]{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LOK]]:[[HIK]]]
define amdgpu_kernel void @materialize_neg1_i64(i64 addrspace(1)* %out) { define amdgpu_kernel void @materialize_neg1_i64(i64 addrspace(1)* %out) {
store i64 -1, i64 addrspace(1)* %out store i64 -1, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_signbit_i32: ; GCN-LABEL: {{^}}materialize_signbit_i32:
; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}} ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
; GCN: buffer_store_dword [[K]] ; GCN: buffer_store_dword [[K]]
define amdgpu_kernel void @materialize_signbit_i32(i32 addrspace(1)* %out) { define amdgpu_kernel void @materialize_signbit_i32(i32 addrspace(1)* %out) {
store i32 -2147483648, i32 addrspace(1)* %out store i32 -2147483648, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_signbit_i64: ; GCN-LABEL: {{^}}materialize_signbit_i64:
; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}}
; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}} ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LOK]]:[[HIK]]]
define amdgpu_kernel void @materialize_signbit_i64(i64 addrspace(1)* %out) { define amdgpu_kernel void @materialize_signbit_i64(i64 addrspace(1)* %out) {
store i64 -9223372036854775808, i64 addrspace(1)* %out store i64 -9223372036854775808, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_rev_neg16_i32: ; GCN-LABEL: {{^}}materialize_rev_neg16_i32:
; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}} ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
; GCN: buffer_store_dword [[K]] ; GCN: buffer_store_dword [[K]]
define amdgpu_kernel void @materialize_rev_neg16_i32(i32 addrspace(1)* %out) { define amdgpu_kernel void @materialize_rev_neg16_i32(i32 addrspace(1)* %out) {
store i32 268435455, i32 addrspace(1)* %out store i32 268435455, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_rev_neg16_i64: ; GCN-LABEL: {{^}}materialize_rev_neg16_i64:
; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], -1{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], -1{{$}}
; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}} ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LOK]]:[[HIK]]]
define amdgpu_kernel void @materialize_rev_neg16_i64(i64 addrspace(1)* %out) { define amdgpu_kernel void @materialize_rev_neg16_i64(i64 addrspace(1)* %out) {
store i64 1152921504606846975, i64 addrspace(1)* %out store i64 1152921504606846975, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_rev_neg17_i32: ; GCN-LABEL: {{^}}materialize_rev_neg17_i32:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0xf7ffffff{{$}} ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0xf7ffffff{{$}}
; GCN: buffer_store_dword [[K]] ; GCN: buffer_store_dword [[K]]
define amdgpu_kernel void @materialize_rev_neg17_i32(i32 addrspace(1)* %out) { define amdgpu_kernel void @materialize_rev_neg17_i32(i32 addrspace(1)* %out) {
store i32 -134217729, i32 addrspace(1)* %out store i32 -134217729, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_rev_neg17_i64: ; GCN-LABEL: {{^}}materialize_rev_neg17_i64:
; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], -1{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], -1{{$}}
; GCN-DAG: v_mov_b32_e32 v[[HIK:[0-9]+]], 0xf7ffffff{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HIK:[0-9]+]], 0xf7ffffff{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LOK]]:[[HIK]]]
define amdgpu_kernel void @materialize_rev_neg17_i64(i64 addrspace(1)* %out) { define amdgpu_kernel void @materialize_rev_neg17_i64(i64 addrspace(1)* %out) {
store i64 -576460752303423489, i64 addrspace(1)* %out store i64 -576460752303423489, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_rev_64_i32: ; GCN-LABEL: {{^}}materialize_rev_64_i32:
; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}} ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
; GCN: buffer_store_dword [[K]] ; GCN: buffer_store_dword [[K]]
define amdgpu_kernel void @materialize_rev_64_i32(i32 addrspace(1)* %out) { define amdgpu_kernel void @materialize_rev_64_i32(i32 addrspace(1)* %out) {
store i32 33554432, i32 addrspace(1)* %out store i32 33554432, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_rev_64_i64: ; GCN-LABEL: {{^}}materialize_rev_64_i64:
; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}}
; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}} ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LOK]]:[[HIK]]]
define amdgpu_kernel void @materialize_rev_64_i64(i64 addrspace(1)* %out) { define amdgpu_kernel void @materialize_rev_64_i64(i64 addrspace(1)* %out) {
store i64 144115188075855872, i64 addrspace(1)* %out store i64 144115188075855872, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_rev_65_i32: ; GCN-LABEL: {{^}}materialize_rev_65_i32:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x82000000{{$}} ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x82000000{{$}}
; GCN: buffer_store_dword [[K]] ; GCN: buffer_store_dword [[K]]
define amdgpu_kernel void @materialize_rev_65_i32(i32 addrspace(1)* %out) { define amdgpu_kernel void @materialize_rev_65_i32(i32 addrspace(1)* %out) {
store i32 -2113929216, i32 addrspace(1)* %out store i32 -2113929216, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_rev_65_i64: ; GCN-LABEL: {{^}}materialize_rev_65_i64:
; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}}
; GCN-DAG: v_mov_b32_e32 v[[HIK:[0-9]+]], 0x82000000{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HIK:[0-9]+]], 0x82000000{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LOK]]:[[HIK]]]
define amdgpu_kernel void @materialize_rev_65_i64(i64 addrspace(1)* %out) { define amdgpu_kernel void @materialize_rev_65_i64(i64 addrspace(1)* %out) {
store i64 -9079256848778919936, i64 addrspace(1)* %out store i64 -9079256848778919936, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_rev_3_i32: ; GCN-LABEL: {{^}}materialize_rev_3_i32:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], -2.0{{$}} ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], -2.0{{$}}
; GCN: buffer_store_dword [[K]] ; GCN: buffer_store_dword [[K]]
define amdgpu_kernel void @materialize_rev_3_i32(i32 addrspace(1)* %out) { define amdgpu_kernel void @materialize_rev_3_i32(i32 addrspace(1)* %out) {
store i32 -1073741824, i32 addrspace(1)* %out store i32 -1073741824, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_rev_3_i64: ; GCN-LABEL: {{^}}materialize_rev_3_i64:
; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}}
; GCN-DAG: v_mov_b32_e32 v[[HIK:[0-9]+]], -2.0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HIK:[0-9]+]], -2.0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LOK]]:[[HIK]]]
define amdgpu_kernel void @materialize_rev_3_i64(i64 addrspace(1)* %out) { define amdgpu_kernel void @materialize_rev_3_i64(i64 addrspace(1)* %out) {
store i64 -4611686018427387904, i64 addrspace(1)* %out store i64 -4611686018427387904, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_rev_1.0_i32: ; GCN-LABEL: {{^}}materialize_rev_1.0_i32:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x1fc{{$}} ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x1fc{{$}}
; GCN: buffer_store_dword [[K]] ; GCN: buffer_store_dword [[K]]
define amdgpu_kernel void @materialize_rev_1.0_i32(i32 addrspace(1)* %out) { define amdgpu_kernel void @materialize_rev_1.0_i32(i32 addrspace(1)* %out) {
store i32 508, i32 addrspace(1)* %out store i32 508, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}materialize_rev_1.0_i64: ; GCN-LABEL: {{^}}materialize_rev_1.0_i64:
; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0x1fc{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0x1fc{{$}}
; GCN-DAG: v_mov_b32_e32 v[[HIK:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HIK:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LOK]]:[[HIK]]]
define amdgpu_kernel void @materialize_rev_1.0_i64(i64 addrspace(1)* %out) { define amdgpu_kernel void @materialize_rev_1.0_i64(i64 addrspace(1)* %out) {
store i64 508, i64 addrspace(1)* %out store i64 508, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}s_materialize_0_i32: ; GCN-LABEL: {{^}}s_materialize_0_i32:
; GCN: s_mov_b32 s{{[0-9]+}}, 0{{$}} ; GCN: s_mov_b32 s{{[0-9]+}}, 0{{$}}
define amdgpu_kernel void @s_materialize_0_i32() { define amdgpu_kernel void @s_materialize_0_i32() {
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llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir

# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-before=branch-relaxation -amdgpu-s-branch-bits=4 -o - %s | FileCheck -check-prefix=GCN %s # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-before=branch-relaxation -amdgpu-s-branch-bits=4 -o - %s | FileCheck -check-prefix=GCN %s
# Make sure there's no assert if the DBG_VALUE ends up in the same # Make sure there's no assert if the DBG_VALUE ends up in the same
# block as the branch expansion. # block as the branch expansion.
# GCN-LABEL: long_branch_dbg_value: # GCN-LABEL: long_branch_dbg_value:
# GCN: .LBB0_5: ; %bb # GCN: .LBB0_5: ; %bb
# GCN-NEXT: ;DEBUG_VALUE: test_debug_value:globalptr_arg <- [DW_OP_plus_uconst 12, DW_OP_stack_value] # GCN-NEXT: ;DEBUG_VALUE: test_debug_value:globalptr_arg <- [DW_OP_plus_uconst 12, DW_OP_stack_value]
# GCN-NEXT: .loc 1 0 42 is_stmt 0 ; /tmp/test_debug_value.cl:0:42 # GCN-NEXT: .loc 1 0 42 is_stmt 0 ; /tmp/test_debug_value.cl:0:42
# GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} # GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
# GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} # GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
# GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], (.LBB0_4-[[POST_GETPC]])&4294967295 # GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], (.LBB0_4-[[POST_GETPC]])&4294967295
# GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], (.LBB0_4-[[POST_GETPC]])>>32 # GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], (.LBB0_4-[[POST_GETPC]])>>32
# GCN-NEXT: s_setpc_b64 # GCN-NEXT: s_setpc_b64
--- | --- |
define amdgpu_kernel void @long_branch_dbg_value(float addrspace(1)* nocapture %arg, float %arg1) #1 !dbg !5 { define amdgpu_kernel void @long_branch_dbg_value(float addrspace(1)* nocapture %arg, float %arg1) #1 !dbg !5 {
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llvm/test/CodeGen/AMDGPU/branch-relaxation.ll

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} }
; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_branch: ; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_branch:
; GCN: s_load_dword [[CND:s[0-9]+]] ; GCN: s_load_dword [[CND:s[0-9]+]]
; GCN: s_cmp_eq_u32 [[CND]], 0 ; GCN: s_cmp_eq_u32 [[CND]], 0
; GCN-NEXT: s_cbranch_scc0 [[LONGBB:.LBB[0-9]+_[0-9]+]] ; GCN-NEXT: s_cbranch_scc0 [[LONGBB:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %bb0 ; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %bb0
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[ENDBB:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[ENDBB:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[ENDBB]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[ENDBB]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: [[LONGBB]]: ; GCN-NEXT: [[LONGBB]]:
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
Show All 24 Lines
; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_vcnd_branch: ; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_vcnd_branch:
; GCN: s_load_dword [[CND:s[0-9]+]] ; GCN: s_load_dword [[CND:s[0-9]+]]
; GCN-DAG: v_cmp_eq_f32_e64 [[UNMASKED:s\[[0-9]+:[0-9]+\]]], [[CND]], 0 ; GCN-DAG: v_cmp_eq_f32_e64 [[UNMASKED:s\[[0-9]+:[0-9]+\]]], [[CND]], 0
; GCN-DAG: s_and_b64 vcc, exec, [[UNMASKED]] ; GCN-DAG: s_and_b64 vcc, exec, [[UNMASKED]]
; GCN: s_cbranch_vccz [[LONGBB:.LBB[0-9]+_[0-9]+]] ; GCN: s_cbranch_vccz [[LONGBB:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %bb0 ; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %bb0
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[ENDBB:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[ENDBB:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[ENDBB]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[ENDBB]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: [[LONGBB]]: ; GCN-NEXT: [[LONGBB]]:
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: [[ENDBB]]: ; GCN: [[ENDBB]]:
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: s_cbranch_scc0 [[ENDBB:.LBB[0-9]+_[0-9]+]] ; GCN-NEXT: s_cbranch_scc0 [[ENDBB:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %bb2 ; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %bb2
; GCN-NEXT: ; in Loop: Header=[[LOOPBB]] Depth=1 ; GCN-NEXT: ; in Loop: Header=[[LOOPBB]] Depth=1
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], (.L[[LOOPBB]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], (.L[[LOOPBB]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], (.L[[LOOPBB]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], (.L[[LOOPBB]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: [[ENDBB]]: ; GCN-NEXT: [[ENDBB]]:
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @long_backward_sbranch(i32 addrspace(1)* %arg) #0 { define amdgpu_kernel void @long_backward_sbranch(i32 addrspace(1)* %arg) #0 {
bb: bb:
br label %bb2 br label %bb2
bb2: bb2:
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; Requires expansion of unconditional branch from %bb2 to %bb4 (and ; Requires expansion of unconditional branch from %bb2 to %bb4 (and
; expansion of conditional branch from %bb to %bb3. ; expansion of conditional branch from %bb to %bb3.
; GCN-LABEL: {{^}}uniform_unconditional_min_long_forward_branch: ; GCN-LABEL: {{^}}uniform_unconditional_min_long_forward_branch:
; GCN: s_cmp_eq_u32 ; GCN: s_cmp_eq_u32
; GCN: s_cbranch_scc{{[0-1]}} [[BB2:.LBB[0-9]+_[0-9]+]] ; GCN: s_cbranch_scc{{[0-1]}} [[BB2:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %bb0 ; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %bb0
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s[[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]]
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC0_LO]], s[[PC0_LO]], ([[BB3:.LBB[0-9]_[0-9]+]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC0_LO]], s[[PC0_LO]], ([[BB3:.LBB[0-9]_[0-9]+]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC0_HI]], s[[PC0_HI]], ([[BB3:.LBB[0-9]_[0-9]+]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC0_HI]], s[[PC0_HI]], ([[BB3:.LBB[0-9]_[0-9]+]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC0_LO]]:[[PC0_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s[[[PC0_LO]]:[[PC0_HI]]]
; GCN: [[BB2]]: ; %bb3 ; GCN: [[BB2]]: ; %bb3
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: ;;#ASMEND ; GCN: ;;#ASMEND
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; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %loop ; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %loop
; GCN-NEXT: ; in Loop: Header=[[LOOP]] Depth=1 ; GCN-NEXT: ; in Loop: Header=[[LOOP]] Depth=1
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], (.L[[LOOP]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], (.L[[LOOP]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], (.L[[LOOP]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], (.L[[LOOP]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: .Lfunc_end{{[0-9]+}}: ; GCN-NEXT: .Lfunc_end{{[0-9]+}}:
define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(i32 addrspace(1)* %arg, i32 %arg1) { define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(i32 addrspace(1)* %arg, i32 %arg1) {
entry: entry:
br label %loop br label %loop
loop: loop:
; 32 byte asm ; 32 byte asm
call void asm sideeffect call void asm sideeffect
Show All 15 Lines
; GCN: s_load_dword ; GCN: s_load_dword
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lg_u32 ; GCN-NEXT: s_cmp_lg_u32
; GCN-NEXT: s_cselect_b64 ; GCN-NEXT: s_cselect_b64
; GCN: s_cbranch_vccz [[BB2:.LBB[0-9]_[0-9]+]] ; GCN: s_cbranch_vccz [[BB2:.LBB[0-9]_[0-9]+]]
; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}:
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s[[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]]
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC1_LO]], s[[PC1_LO]], ([[BB3:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC1_LO]], s[[PC1_LO]], ([[BB3:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC1_HI]], s[[PC1_HI]], ([[BB3:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC1_HI]], s[[PC1_HI]], ([[BB3:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC1_LO]]:[[PC1_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s[[[PC1_LO]]:[[PC1_HI]]]
; GCN-NEXT: [[BB2]]: ; %bb2 ; GCN-NEXT: [[BB2]]: ; %bb2
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
Show All 38 Lines
; Requires expanding of required skip branch. ; Requires expanding of required skip branch.
; GCN-LABEL: {{^}}uniform_inside_divergent: ; GCN-LABEL: {{^}}uniform_inside_divergent:
; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}} ; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
; GCN-NEXT: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc ; GCN-NEXT: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
; GCN-NEXT: s_cbranch_execnz [[IF:.LBB[0-9]+_[0-9]+]] ; GCN-NEXT: s_cbranch_execnz [[IF:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %entry ; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %entry
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[BB2:.LBB[0-9]_[0-9]+]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[BB2:.LBB[0-9]_[0-9]+]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[BB2:.LBB[0-9]_[0-9]+]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[BB2:.LBB[0-9]_[0-9]+]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: [[IF]]: ; %if ; GCN-NEXT: [[IF]]: ; %if
; GCN: s_cmp_lg_u32 ; GCN: s_cmp_lg_u32
; GCN: s_cbranch_scc1 [[ENDIF:.LBB[0-9]+_[0-9]+]] ; GCN: s_cbranch_scc1 [[ENDIF:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: ; %bb.2: ; %if_uniform ; GCN-NEXT: ; %bb.2: ; %if_uniform
; GCN: buffer_store_dword ; GCN: buffer_store_dword
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; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: v_nop_e64 ; GCN: v_nop_e64
; GCN: ;;#ASMEND ; GCN: ;;#ASMEND
; GCN: s_cbranch_{{vccz|vccnz}} [[RET:.LBB[0-9]+_[0-9]+]] ; GCN: s_cbranch_{{vccz|vccnz}} [[RET:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %loop ; GCN-NEXT: {{.LBB[0-9]+_[0-9]+}}: ; %loop
; GCN-NEXT: ; in Loop: Header=[[LOOP_BODY]] Depth=1 ; GCN-NEXT: ; in Loop: Header=[[LOOP_BODY]] Depth=1
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], (.L[[LOOP_BODY]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], (.L[[LOOP_BODY]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], (.L[[LOOP_BODY]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], (.L[[LOOP_BODY]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: [[RET]]: ; %UnifiedReturnBlock ; GCN-NEXT: [[RET]]: ; %UnifiedReturnBlock
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @analyze_mask_branch() #0 { define amdgpu_kernel void @analyze_mask_branch() #0 {
entry: entry:
%reg = call float asm sideeffect "v_mov_b32_e64 $0, 0", "=v"() %reg = call float asm sideeffect "v_mov_b32_e64 $0, 0", "=v"()
%cmp0 = fcmp ogt float %reg, 0.000000e+00 %cmp0 = fcmp ogt float %reg, 0.000000e+00
br i1 %cmp0, label %loop, label %ret br i1 %cmp0, label %loop, label %ret
Show All 19 Linesret:
ret void ret void
} }
; GCN-LABEL: {{^}}long_branch_hang: ; GCN-LABEL: {{^}}long_branch_hang:
; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 6 ; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 6
; GCN: s_cbranch_scc{{[0-1]}} [[LONG_BR_0:.LBB[0-9]+_[0-9]+]] ; GCN: s_cbranch_scc{{[0-1]}} [[LONG_BR_0:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: BB{{[0-9]+_[0-9]+}}: ; GCN-NEXT: BB{{[0-9]+_[0-9]+}}:
; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[LONG_BR_DEST0:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[LONG_BR_DEST0:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[LONG_BR_DEST0]]-[[POST_GETPC]])>>32 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[LONG_BR_DEST0]]-[[POST_GETPC]])>>32
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: [[LONG_BR_0]]: ; GCN-NEXT: [[LONG_BR_0]]:
; GCN: [[LONG_BR_DEST0]]: ; GCN: [[LONG_BR_DEST0]]:
; GCN-DAG: s_cmp_lt_i32 ; GCN-DAG: s_cmp_lt_i32
; GCN-DAG: s_cmp_ge_i32 ; GCN-DAG: s_cmp_ge_i32
; GCN: s_cbranch_vccz ; GCN: s_cbranch_vccz
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llvm/test/CodeGen/AMDGPU/build_vector.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefixes=R600,ALL ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefixes=R600,ALL
; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefixes=SI,GFX6,GFX678,ALL ; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefixes=SI,GFX6,GFX678,ALL
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=SI,GFX8,GFX678,ALL ; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=SI,GFX8,GFX678,ALL
; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX10,SI,ALL ; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX10,SI,ALL
; ALL-LABEL: {{^}}build_vector2: ; ALL-LABEL: {{^}}build_vector2:
; R600: MOV ; R600: MOV
; R600: MOV ; R600: MOV
; R600-NOT: MOV ; R600-NOT: MOV
; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5 ; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6 ; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
; GFX678: buffer_store_dwordx2 v{{\[}}[[X]]:[[Y]]{{\]}} ; GFX678: buffer_store_dwordx2 v[[[X]]:[[Y]]]
; GFX10: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10: global_store_dwordx2 v2, v[0:1], s[0:1]
define amdgpu_kernel void @build_vector2 (<2 x i32> addrspace(1)* %out) { define amdgpu_kernel void @build_vector2 (<2 x i32> addrspace(1)* %out) {
entry: entry:
store <2 x i32> <i32 5, i32 6>, <2 x i32> addrspace(1)* %out store <2 x i32> <i32 5, i32 6>, <2 x i32> addrspace(1)* %out
ret void ret void
} }
; ALL-LABEL: {{^}}build_vector4: ; ALL-LABEL: {{^}}build_vector4:
; R600: MOV ; R600: MOV
; R600: MOV ; R600: MOV
; R600: MOV ; R600: MOV
; R600: MOV ; R600: MOV
; R600-NOT: MOV ; R600-NOT: MOV
; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5 ; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6 ; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
; SI-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7 ; SI-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
; SI-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8 ; SI-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
; GFX678: buffer_store_dwordx4 v{{\[}}[[X]]:[[W]]{{\]}} ; GFX678: buffer_store_dwordx4 v[[[X]]:[[W]]]
; GFX10: global_store_dwordx4 v4, v[0:3], s[0:1] ; GFX10: global_store_dwordx4 v4, v[0:3], s[0:1]
define amdgpu_kernel void @build_vector4 (<4 x i32> addrspace(1)* %out) { define amdgpu_kernel void @build_vector4 (<4 x i32> addrspace(1)* %out) {
entry: entry:
store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> addrspace(1)* %out store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> addrspace(1)* %out
ret void ret void
} }
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/call-argument-types.ll

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; FIXME: Should be passing -1 ; FIXME: Should be passing -1
; GCN-LABEL: {{^}}test_call_external_void_func_i1_imm: ; GCN-LABEL: {{^}}test_call_external_void_func_i1_imm:
; MESA: s_mov_b32 s36, SCRATCH_RSRC_DWORD ; MESA: s_mov_b32 s36, SCRATCH_RSRC_DWORD
; MESA-DAG: s_mov_b64 s[0:1], s[36:37] ; MESA-DAG: s_mov_b64 s[0:1], s[36:37]
; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-DAG: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1@rel32@lo+4 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1@rel32@lo+4
; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1@rel32@hi+12 ; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1@rel32@hi+12
; GCN-DAG: v_mov_b32_e32 v0, 1{{$}} ; GCN-DAG: v_mov_b32_e32 v0, 1{{$}}
; MESA-DAG: s_mov_b64 s[2:3], s[38:39] ; MESA-DAG: s_mov_b64 s[2:3], s[38:39]
; GCN: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN: s_swappc_b64 s[30:31], s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 { define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
call void @external_void_func_i1(i1 true) call void @external_void_func_i1(i1 true)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_i1_signext: ; GCN-LABEL: {{^}}test_call_external_void_func_i1_signext:
; HSA: buffer_load_ubyte [[VAR:v[0-9]+]] ; HSA: buffer_load_ubyte [[VAR:v[0-9]+]]
; HSA: s_mov_b32 s32, 0 ; HSA: s_mov_b32 s32, 0
; MESA-DAG: buffer_load_ubyte [[VAR:v[0-9]+]] ; MESA-DAG: buffer_load_ubyte [[VAR:v[0-9]+]]
; MESA-DAG: s_mov_b32 s32, 0{{$}} ; MESA-DAG: s_mov_b32 s32, 0{{$}}
; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_signext@rel32@lo+4 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_signext@rel32@lo+4
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1_signext@rel32@hi+12 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1_signext@rel32@hi+12
; GCN-NEXT: v_bfe_i32 v0, [[VAR]], 0, 1 ; GCN-NEXT: v_bfe_i32 v0, [[VAR]], 0, 1
; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_swappc_b64 s[30:31], s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
%var = load volatile i1, i1 addrspace(1)* undef %var = load volatile i1, i1 addrspace(1)* undef
call void @external_void_func_i1_signext(i1 signext %var) call void @external_void_func_i1_signext(i1 signext %var)
ret void ret void
} }
; FIXME: load should be scheduled before getpc ; FIXME: load should be scheduled before getpc
; GCN-LABEL: {{^}}test_call_external_void_func_i1_zeroext: ; GCN-LABEL: {{^}}test_call_external_void_func_i1_zeroext:
; HSA: buffer_load_ubyte [[VAL:v[0-9]+]] ; HSA: buffer_load_ubyte [[VAL:v[0-9]+]]
; HSA-DAG: s_mov_b32 s32, 0{{$}} ; HSA-DAG: s_mov_b32 s32, 0{{$}}
; MESA: buffer_load_ubyte [[VAL:v[0-9]+]] ; MESA: buffer_load_ubyte [[VAL:v[0-9]+]]
; MESA-DAG: s_mov_b32 s32, 0{{$}} ; MESA-DAG: s_mov_b32 s32, 0{{$}}
; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_zeroext@rel32@lo+4 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_zeroext@rel32@lo+4
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1_zeroext@rel32@hi+12 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1_zeroext@rel32@hi+12
; GCN-NEXT: v_and_b32_e32 v0, 1, [[VAL]] ; GCN-NEXT: v_and_b32_e32 v0, 1, [[VAL]]
; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_swappc_b64 s[30:31], s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {
%var = load volatile i1, i1 addrspace(1)* undef %var = load volatile i1, i1 addrspace(1)* undef
call void @external_void_func_i1_zeroext(i1 zeroext %var) call void @external_void_func_i1_zeroext(i1 zeroext %var)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_i8_imm: ; GCN-LABEL: {{^}}test_call_external_void_func_i8_imm:
; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-DAG: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8@rel32@lo+4 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8@rel32@lo+4
; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8@rel32@hi+12 ; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8@rel32@hi+12
; GCN-DAG: v_mov_b32_e32 v0, 0x7b ; GCN-DAG: v_mov_b32_e32 v0, 0x7b
; GCN-DAG: s_mov_b32 s32, 0{{$}} ; GCN-DAG: s_mov_b32 s32, 0{{$}}
; GCN: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN: s_swappc_b64 s[30:31], s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
call void @external_void_func_i8(i8 123) call void @external_void_func_i8(i8 123)
ret void ret void
} }
; FIXME: don't wait before call ; FIXME: don't wait before call
; GCN-LABEL: {{^}}test_call_external_void_func_i8_signext: ; GCN-LABEL: {{^}}test_call_external_void_func_i8_signext:
; GCN-DAG: buffer_load_sbyte [[VAL:v[0-9]+]] ; GCN-DAG: buffer_load_sbyte [[VAL:v[0-9]+]]
; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-DAG: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_signext@rel32@lo+4 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_signext@rel32@lo+4
; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8_signext@rel32@hi+12 ; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8_signext@rel32@hi+12
; GCN-DAG: s_mov_b32 s32, 0 ; GCN-DAG: s_mov_b32 s32, 0
; GCN-NOT: s_waitcnt ; GCN-NOT: s_waitcnt
; GCN: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN: s_swappc_b64 s[30:31], s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {
%var = load volatile i8, i8 addrspace(1)* undef %var = load volatile i8, i8 addrspace(1)* undef
call void @external_void_func_i8_signext(i8 signext %var) call void @external_void_func_i8_signext(i8 signext %var)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_i8_zeroext: ; GCN-LABEL: {{^}}test_call_external_void_func_i8_zeroext:
; GCN-DAG: buffer_load_ubyte [[VAL:v[0-9]+]] ; GCN-DAG: buffer_load_ubyte [[VAL:v[0-9]+]]
; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-DAG: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_zeroext@rel32@lo+4 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_zeroext@rel32@lo+4
; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8_zeroext@rel32@hi+12 ; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8_zeroext@rel32@hi+12
; GCN-DAG: s_mov_b32 s32, 0 ; GCN-DAG: s_mov_b32 s32, 0
; GCN-NOT: s_waitcnt ; GCN-NOT: s_waitcnt
; GCN: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN: s_swappc_b64 s[30:31], s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 {
%var = load volatile i8, i8 addrspace(1)* undef %var = load volatile i8, i8 addrspace(1)* undef
call void @external_void_func_i8_zeroext(i8 zeroext %var) call void @external_void_func_i8_zeroext(i8 zeroext %var)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_i16_imm: ; GCN-LABEL: {{^}}test_call_external_void_func_i16_imm:
; GCN-DAG: v_mov_b32_e32 v0, 0x7b{{$}} ; GCN-DAG: v_mov_b32_e32 v0, 0x7b{{$}}
; GCN-DAG: s_mov_b32 s32, 0 ; GCN-DAG: s_mov_b32 s32, 0
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 { define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {
call void @external_void_func_i16(i16 123) call void @external_void_func_i16(i16 123)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_i16_signext: ; GCN-LABEL: {{^}}test_call_external_void_func_i16_signext:
; GCN-DAG: buffer_load_sshort [[VAL:v[0-9]+]] ; GCN-DAG: buffer_load_sshort [[VAL:v[0-9]+]]
; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-DAG: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_signext@rel32@lo+4 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_signext@rel32@lo+4
; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i16_signext@rel32@hi+12 ; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i16_signext@rel32@hi+12
; GCN-DAG: s_mov_b32 s32, 0 ; GCN-DAG: s_mov_b32 s32, 0
; GCN-NOT: s_waitcnt ; GCN-NOT: s_waitcnt
; GCN: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN: s_swappc_b64 s[30:31], s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {
%var = load volatile i16, i16 addrspace(1)* undef %var = load volatile i16, i16 addrspace(1)* undef
call void @external_void_func_i16_signext(i16 signext %var) call void @external_void_func_i16_signext(i16 signext %var)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_i16_zeroext: ; GCN-LABEL: {{^}}test_call_external_void_func_i16_zeroext:
; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-DAG: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_zeroext@rel32@lo+4 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_zeroext@rel32@lo+4
; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i16_zeroext@rel32@hi+12 ; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i16_zeroext@rel32@hi+12
; GCN-DAG: s_mov_b32 s32, 0 ; GCN-DAG: s_mov_b32 s32, 0
; GCN-NOT: s_waitcnt ; GCN-NOT: s_waitcnt
; GCN: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN: s_swappc_b64 s[30:31], s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 {
%var = load volatile i16, i16 addrspace(1)* undef %var = load volatile i16, i16 addrspace(1)* undef
call void @external_void_func_i16_zeroext(i16 zeroext %var) call void @external_void_func_i16_zeroext(i16 zeroext %var)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_i32_imm: ; GCN-LABEL: {{^}}test_call_external_void_func_i32_imm:
; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-DAG: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i32@rel32@lo+4 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i32@rel32@lo+4
; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i32@rel32@hi+12 ; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i32@rel32@hi+12
; GCN-DAG: v_mov_b32_e32 v0, 42 ; GCN-DAG: v_mov_b32_e32 v0, 42
; GCN-DAG: s_mov_b32 s32, 0 ; GCN-DAG: s_mov_b32 s32, 0
; GCN: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN: s_swappc_b64 s[30:31], s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i32_imm(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i32_imm(i32) #0 {
call void @external_void_func_i32(i32 42) call void @external_void_func_i32(i32 42)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_i64_imm: ; GCN-LABEL: {{^}}test_call_external_void_func_i64_imm:
; GCN-DAG: v_mov_b32_e32 v0, 0x7b{{$}} ; GCN-DAG: v_mov_b32_e32 v0, 0x7b{{$}}
; GCN-DAG: v_mov_b32_e32 v1, 0{{$}} ; GCN-DAG: v_mov_b32_e32 v1, 0{{$}}
; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-DAG: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i64@rel32@lo+4 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i64@rel32@lo+4
; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i64@rel32@hi+12 ; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i64@rel32@hi+12
; GCN: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN: s_swappc_b64 s[30:31], s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i64_imm() #0 { define amdgpu_kernel void @test_call_external_void_func_i64_imm() #0 {
call void @external_void_func_i64(i64 123) call void @external_void_func_i64(i64 123)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_v2i64: ; GCN-LABEL: {{^}}test_call_external_void_func_v2i64:
; GCN: buffer_load_dwordx4 v[0:3] ; GCN: buffer_load_dwordx4 v[0:3]
▲ Show 20 Lines • Show All 672 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll

Show All 36 Linesdefine amdgpu_kernel void @kern_indirect_use_queue_ptr(i32) #1 {
ret void ret void
} }
; GCN-LABEL: {{^}}use_queue_ptr_addrspacecast: ; GCN-LABEL: {{^}}use_queue_ptr_addrspacecast:
; CIVI: s_load_dword [[APERTURE_LOAD:s[0-9]+]], s[6:7], 0x10 ; CIVI: s_load_dword [[APERTURE_LOAD:s[0-9]+]], s[6:7], 0x10
; GFX9: s_getreg_b32 [[APERTURE_LOAD:s[0-9]+]] ; GFX9: s_getreg_b32 [[APERTURE_LOAD:s[0-9]+]]
; CIVI: v_mov_b32_e32 v[[LO:[0-9]+]], 16 ; CIVI: v_mov_b32_e32 v[[LO:[0-9]+]], 16
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE_LOAD]] ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE_LOAD]]
; GFX9: {{flat|global}}_store_dword v{{\[[0-9]+}}:[[HI]]{{\]}} ; GFX9: {{flat|global}}_store_dword v{{\[[0-9]+}}:[[HI]]]
; CIVI: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}} ; CIVI: {{flat|global}}_store_dword v[[[LO]]:[[HI]]]
define hidden void @use_queue_ptr_addrspacecast() #1 { define hidden void @use_queue_ptr_addrspacecast() #1 {
%asc = addrspacecast i32 addrspace(3)* inttoptr (i32 16 to i32 addrspace(3)*) to i32* %asc = addrspacecast i32 addrspace(3)* inttoptr (i32 16 to i32 addrspace(3)*) to i32*
store volatile i32 0, i32* %asc store volatile i32 0, i32* %asc
ret void ret void
} }
; GCN-LABEL: {{^}}kern_indirect_use_queue_ptr_addrspacecast: ; GCN-LABEL: {{^}}kern_indirect_use_queue_ptr_addrspacecast:
; CIVI: s_mov_b64 s[6:7], s[4:5] ; CIVI: s_mov_b64 s[6:7], s[4:5]
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llvm/test/CodeGen/AMDGPU/captured-frame-index.ll

Show First 20 Lines • Show All 175 Lines • ▼ Show 20 Lines
} }
@g1 = external addrspace(1) global i32 addrspace(5)* @g1 = external addrspace(1) global i32 addrspace(5)*
; This was leaving a dead node around resulting in failing to select ; This was leaving a dead node around resulting in failing to select
; on the leftover AssertZext's ValueType operand. ; on the leftover AssertZext's ValueType operand.
; GCN-LABEL: {{^}}cannot_select_assertzext_valuetype: ; GCN-LABEL: {{^}}cannot_select_assertzext_valuetype:
; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; GCN: s_add_u32 s{{[0-9]+}}, s[[PC_LO]], g1@gotpcrel32@lo+4 ; GCN: s_add_u32 s{{[0-9]+}}, s[[PC_LO]], g1@gotpcrel32@lo+4
; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC_HI]], g1@gotpcrel32@hi+12 ; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC_HI]], g1@gotpcrel32@hi+12
; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}} ; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}}
; GCN: buffer_store_dword [[FI]] ; GCN: buffer_store_dword [[FI]]
define amdgpu_kernel void @cannot_select_assertzext_valuetype(i32 addrspace(1)* %out, i32 %idx) #0 { define amdgpu_kernel void @cannot_select_assertzext_valuetype(i32 addrspace(1)* %out, i32 %idx) #0 {
entry: entry:
%b = alloca i32, align 4, addrspace(5) %b = alloca i32, align 4, addrspace(5)
%tmp1 = load volatile i32 addrspace(5)*, i32 addrspace(5)* addrspace(1)* @g1, align 4 %tmp1 = load volatile i32 addrspace(5)*, i32 addrspace(5)* addrspace(1)* @g1, align 4
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llvm/test/CodeGen/AMDGPU/clamp-modifier.ll

Show First 20 Lines • Show All 133 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_clamp_add_src_f16_no_denormals(half addrspace(1)* %out, half addrspace(1)* %aptr) #3 {
%add = fadd half %a, 1.0 %add = fadd half %a, 1.0
%max = call half @llvm.maxnum.f16(half %add, half 0.0) %max = call half @llvm.maxnum.f16(half %add, half 0.0)
%clamp = call half @llvm.minnum.f16(half %max, half 1.0) %clamp = call half @llvm.minnum.f16(half %max, half 1.0)
store half %clamp, half addrspace(1)* %out.gep store half %clamp, half addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_clamp_add_src_v2f32: ; GCN-LABEL: {{^}}v_clamp_add_src_v2f32:
; GCN: {{buffer|flat|global}}_load_dwordx2 v{{\[}}[[A:[0-9]+]]:[[B:[0-9]+]]{{\]}} ; GCN: {{buffer|flat|global}}_load_dwordx2 v[[[A:[0-9]+]]:[[B:[0-9]+]]]
; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, v[[A]], 1.0 clamp{{$}} ; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, v[[A]], 1.0 clamp{{$}}
; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, v[[B]], 1.0 clamp{{$}} ; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, v[[B]], 1.0 clamp{{$}}
define amdgpu_kernel void @v_clamp_add_src_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %aptr) #0 { define amdgpu_kernel void @v_clamp_add_src_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %aptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep0 = getelementptr <2 x float>, <2 x float> addrspace(1)* %aptr, i32 %tid %gep0 = getelementptr <2 x float>, <2 x float> addrspace(1)* %aptr, i32 %tid
%out.gep = getelementptr <2 x float>, <2 x float> addrspace(1)* %out, i32 %tid %out.gep = getelementptr <2 x float>, <2 x float> addrspace(1)* %out, i32 %tid
%a = load <2 x float>, <2 x float> addrspace(1)* %gep0 %a = load <2 x float>, <2 x float> addrspace(1)* %gep0
%add = fadd <2 x float> %a, <float 1.0, float 1.0> %add = fadd <2 x float> %a, <float 1.0, float 1.0>
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llvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; Check that register coalescer does not create an odd subreg when register tuples ; Check that register coalescer does not create an odd subreg when register tuples
; must be aligned. ; must be aligned.
; GCN-LABEL: {{^}}test_odd_int4: ; GCN-LABEL: {{^}}test_odd_int4:
; GCN: global_load_dwordx4 v[{{[0-9]*[02468]:[0-9]*[13579]}}], v{{[0-9]+}}, s[{{[0-9:]+}}] ; GCN: global_load_dwordx4 v[{{[0-9]*[02468]:[0-9]*[13579]}}], v{{[0-9]+}}, s[{{[0-9:]+}}]
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: v_mov_b32_e32 v{{[0-9]*}}[[LO:[02468]]], v{{[0-9]+}} ; GCN-NEXT: v_mov_b32_e32 v{{[0-9]*}}[[LO:[02468]]], v{{[0-9]+}}
; GCN-NEXT: global_store_dwordx2 v{{[0-9]+}}, v{{\[}}[[LO]]:{{[0-9]+\]}}, s[{{[0-9:]+}}] ; GCN-NEXT: global_store_dwordx2 v{{[0-9]+}}, v[[[LO]]:{{[0-9]+\]}}, s[{{[0-9:]+}}]
define amdgpu_kernel void @test_odd_int4(<4 x i32> addrspace(1)* %arg, <2 x i32> addrspace(1)* %arg1) { define amdgpu_kernel void @test_odd_int4(<4 x i32> addrspace(1)* %arg, <2 x i32> addrspace(1)* %arg1) {
bb: bb:
%lid = tail call i32 @llvm.amdgcn.workitem.id.x() %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i32 %lid %gep1 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i32 %lid
%load = load <4 x i32>, <4 x i32> addrspace(1)* %gep1, align 16 %load = load <4 x i32>, <4 x i32> addrspace(1)* %gep1, align 16
%shuffle = shufflevector <4 x i32> %load, <4 x i32> undef, <2 x i32> <i32 1, i32 3> %shuffle = shufflevector <4 x i32> %load, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
%gep2 = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %arg1, i32 %lid %gep2 = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %arg1, i32 %lid
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llvm/test/CodeGen/AMDGPU/combine-ftrunc.ll

Show All 18 Linesdefine amdgpu_kernel void @combine_ftrunc_frint_f32(float addrspace(1)* %p) {
%round = tail call float @llvm.rint.f32(float %v) %round = tail call float @llvm.rint.f32(float %v)
%trunc = tail call float @llvm.trunc.f32(float %round) %trunc = tail call float @llvm.trunc.f32(float %round)
store float %trunc, float addrspace(1)* %p, align 4 store float %trunc, float addrspace(1)* %p, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}combine_ftrunc_frint_v2f32: ; GCN-LABEL: {{^}}combine_ftrunc_frint_v2f32:
; GCN: s_load_dwordx2 ; GCN: s_load_dwordx2
; GCN: s_load_dwordx2 s{{\[}}[[SRC1:[0-9]+]]:[[SRC2:[0-9]+]]{{\]}} ; GCN: s_load_dwordx2 s[[[SRC1:[0-9]+]]:[[SRC2:[0-9]+]]]
; GCN-DAG: v_rndne_f32_e32 v[[RND1:[0-9]+]], s[[SRC1]] ; GCN-DAG: v_rndne_f32_e32 v[[RND1:[0-9]+]], s[[SRC1]]
; GCN-DAG: v_rndne_f32_e32 v[[RND2:[0-9]+]], s[[SRC2]] ; GCN-DAG: v_rndne_f32_e32 v[[RND2:[0-9]+]], s[[SRC2]]
; GCN: flat_store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[RND1]]:[[RND2]]{{\]}} ; GCN: flat_store_dwordx2 v[{{[0-9:]+}}], v[[[RND1]]:[[RND2]]]
define amdgpu_kernel void @combine_ftrunc_frint_v2f32(<2 x float> addrspace(1)* %p) { define amdgpu_kernel void @combine_ftrunc_frint_v2f32(<2 x float> addrspace(1)* %p) {
%v = load <2 x float>, <2 x float> addrspace(1)* %p, align 8 %v = load <2 x float>, <2 x float> addrspace(1)* %p, align 8
%round = tail call <2 x float> @llvm.rint.v2f32(<2 x float> %v) %round = tail call <2 x float> @llvm.rint.v2f32(<2 x float> %v)
%trunc = tail call <2 x float> @llvm.trunc.v2f32(<2 x float> %round) %trunc = tail call <2 x float> @llvm.trunc.v2f32(<2 x float> %round)
store <2 x float> %trunc, <2 x float> addrspace(1)* %p, align 8 store <2 x float> %trunc, <2 x float> addrspace(1)* %p, align 8
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/commute-compares.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @commute_ule_63_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
store i32 %ext, i32 addrspace(1)* %gep.out store i32 %ext, i32 addrspace(1)* %gep.out
ret void ret void
} }
; FIXME: Undo canonicalization to gt (x + 1) since it doesn't use the inline imm ; FIXME: Undo canonicalization to gt (x + 1) since it doesn't use the inline imm
; GCN-LABEL: {{^}}commute_ule_64_i64: ; GCN-LABEL: {{^}}commute_ule_64_i64:
; GCN-DAG: s_movk_i32 s[[KLO:[0-9]+]], 0x41{{$}} ; GCN-DAG: s_movk_i32 s[[KLO:[0-9]+]], 0x41{{$}}
; GCN: v_cmp_gt_u64_e32 vcc, s{{\[}}[[KLO]]:{{[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} ; GCN: v_cmp_gt_u64_e32 vcc, s[[[KLO]]:{{[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @commute_ule_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @commute_ule_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
%gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
%gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
%val = load i64, i64 addrspace(1)* %gep.in %val = load i64, i64 addrspace(1)* %gep.in
%cmp = icmp ule i64 %val, 64 %cmp = icmp ule i64 %val, 64
%ext = sext i1 %cmp to i32 %ext = sext i1 %cmp to i32
store i32 %ext, i32 addrspace(1)* %gep.out store i32 %ext, i32 addrspace(1)* %gep.out
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llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll

Show First 20 Lines • Show All 300 Lines • ▼ Show 20 Linesdefine amdgpu_vs float @load_addr_no_fold(i32 addrspace(6)* inreg noalias %p0) #0 {
%r1 = load i32, i32 addrspace(6)* %gep1 %r1 = load i32, i32 addrspace(6)* %gep1
%r2 = bitcast i32 %r1 to float %r2 = bitcast i32 %r1 to float
ret float %r2 ret float %r2
} }
; CHECK-LABEL: {{^}}vgpr_arg_src: ; CHECK-LABEL: {{^}}vgpr_arg_src:
; CHECK: v_readfirstlane_b32 s[[READLANE:[0-9]+]], v0 ; CHECK: v_readfirstlane_b32 s[[READLANE:[0-9]+]], v0
; CHECK: s_mov_b32 s[[ZERO:[0-9]+]] ; CHECK: s_mov_b32 s[[ZERO:[0-9]+]]
; CHECK: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[READLANE]]:[[ZERO]]{{\]}} ; CHECK: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[[[READLANE]]:[[ZERO]]]
define amdgpu_vs float @vgpr_arg_src(<4 x i32> addrspace(6)* %arg) { define amdgpu_vs float @vgpr_arg_src(<4 x i32> addrspace(6)* %arg) {
main_body: main_body:
%tmp9 = load <4 x i32>, <4 x i32> addrspace(6)* %arg %tmp9 = load <4 x i32>, <4 x i32> addrspace(6)* %arg
%tmp10 = call nsz float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %tmp9, i32 undef, i32 0, i32 0, i32 0) #1 %tmp10 = call nsz float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %tmp9, i32 undef, i32 0, i32 0, i32 0) #1
ret float %tmp10 ret float %tmp10
} }
; Function Attrs: nounwind readnone speculatable ; Function Attrs: nounwind readnone speculatable
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llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @fold_mi_s_not_0(i32 addrspace(1)* %out, i32 %x) #0 {
ret void ret void
} }
; GCN-LABEL: {{^}}fold_mi_v_not_0: ; GCN-LABEL: {{^}}fold_mi_v_not_0:
; GCN: v_bcnt_u32_b32{{(_e64)*}} v[[RESULT_LO:[0-9]+]], v{{[0-9]+}}, 0{{$}} ; GCN: v_bcnt_u32_b32{{(_e64)*}} v[[RESULT_LO:[0-9]+]], v{{[0-9]+}}, 0{{$}}
; GCN: v_bcnt_u32_b32{{(_e32)*(_e64)*}} v[[RESULT_LO:[0-9]+]], v{{[0-9]+}}, v[[RESULT_LO]]{{$}} ; GCN: v_bcnt_u32_b32{{(_e32)*(_e64)*}} v[[RESULT_LO:[0-9]+]], v{{[0-9]+}}, v[[RESULT_LO]]{{$}}
; GCN-NEXT: v_not_b32_e32 v[[RESULT_LO]] ; GCN-NEXT: v_not_b32_e32 v[[RESULT_LO]]
; GCN-NEXT: v_mov_b32_e32 v[[RESULT_HI:[0-9]+]], -1{{$}} ; GCN-NEXT: v_mov_b32_e32 v[[RESULT_HI:[0-9]+]], -1{{$}}
; GCN-NEXT: buffer_store_dwordx2 v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}} ; GCN-NEXT: buffer_store_dwordx2 v[[[RESULT_LO]]:[[RESULT_HI]]]
define amdgpu_kernel void @fold_mi_v_not_0(i64 addrspace(1)* %out) { define amdgpu_kernel void @fold_mi_v_not_0(i64 addrspace(1)* %out) {
%vreg = load volatile i64, i64 addrspace(1)* undef %vreg = load volatile i64, i64 addrspace(1)* undef
%ctpop = call i64 @llvm.ctpop.i64(i64 %vreg) %ctpop = call i64 @llvm.ctpop.i64(i64 %vreg)
%xor = xor i64 %ctpop, -1 %xor = xor i64 %ctpop, -1
store i64 %xor, i64 addrspace(1)* %out store i64 %xor, i64 addrspace(1)* %out
ret void ret void
} }
; The neg1 appears after folding the not 0 ; The neg1 appears after folding the not 0
; GCN-LABEL: {{^}}fold_mi_or_neg1: ; GCN-LABEL: {{^}}fold_mi_or_neg1:
; GCN: buffer_load_dwordx2 ; GCN: buffer_load_dwordx2
; GCN: buffer_load_dwordx2 v{{\[}}[[VREG1_LO:[0-9]+]]:[[VREG1_HI:[0-9]+]]{{\]}} ; GCN: buffer_load_dwordx2 v[[[VREG1_LO:[0-9]+]]:[[VREG1_HI:[0-9]+]]]
; GCN: v_bcnt_u32_b32{{(_e64)*}} v[[RESULT_LO:[0-9]+]], v{{[0-9]+}}, 0{{$}} ; GCN: v_bcnt_u32_b32{{(_e64)*}} v[[RESULT_LO:[0-9]+]], v{{[0-9]+}}, 0{{$}}
; GCN: v_bcnt_u32_b32{{(_e32)*(_e64)*}} v[[RESULT_LO:[0-9]+]], v{{[0-9]+}}, v[[RESULT_LO]]{{$}} ; GCN: v_bcnt_u32_b32{{(_e32)*(_e64)*}} v[[RESULT_LO:[0-9]+]], v{{[0-9]+}}, v[[RESULT_LO]]{{$}}
; GCN-DAG: v_not_b32_e32 v[[RESULT_LO]], v[[RESULT_LO]] ; GCN-DAG: v_not_b32_e32 v[[RESULT_LO]], v[[RESULT_LO]]
; GCN-DAG: v_or_b32_e32 v[[RESULT_LO]], v[[VREG1_LO]], v[[RESULT_LO]] ; GCN-DAG: v_or_b32_e32 v[[RESULT_LO]], v[[VREG1_LO]], v[[RESULT_LO]]
; GCN-DAG: v_mov_b32_e32 v[[RESULT_HI:[0-9]+]], v[[VREG1_HI]] ; GCN-DAG: v_mov_b32_e32 v[[RESULT_HI:[0-9]+]], v[[VREG1_HI]]
; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[RESULT_LO]]:[[RESULT_HI]]]
define amdgpu_kernel void @fold_mi_or_neg1(i64 addrspace(1)* %out) { define amdgpu_kernel void @fold_mi_or_neg1(i64 addrspace(1)* %out) {
%vreg0 = load volatile i64, i64 addrspace(1)* undef %vreg0 = load volatile i64, i64 addrspace(1)* undef
%vreg1 = load volatile i64, i64 addrspace(1)* undef %vreg1 = load volatile i64, i64 addrspace(1)* undef
%ctpop = call i64 @llvm.ctpop.i64(i64 %vreg0) %ctpop = call i64 @llvm.ctpop.i64(i64 %vreg0)
%xor = xor i64 %ctpop, -1 %xor = xor i64 %ctpop, -1
%or = or i64 %xor, %vreg1 %or = or i64 %xor, %vreg1
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
ret void ret void
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llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll

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; GCN: s_mov_b32 m0, -1 ; GCN: s_mov_b32 m0, -1
; GCN: ds_read_b32 [[LOAD0:v[0-9]+]] ; GCN: ds_read_b32 [[LOAD0:v[0-9]+]]
; Spill load ; Spill load
; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], 0 offset:[[LOAD0_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], 0 offset:[[LOAD0_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN: v_cmp_eq_u32_e64 [[CMP0:s\[[0-9]+:[0-9]\]]], v0, s{{[0-9]+}} ; GCN: v_cmp_eq_u32_e64 [[CMP0:s\[[0-9]+:[0-9]\]]], v0, s{{[0-9]+}}
; Spill saved exec ; Spill saved exec
; GCN: s_mov_b64 s{{\[}}[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]{{\]}}, exec ; GCN: s_mov_b64 s[[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]], exec
; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]] ; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]
; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]] ; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]
; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0 ; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0
; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1 ; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1
; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 offset:[[V_EXEC_SPILL_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 offset:[[V_EXEC_SPILL_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN: s_and_b64 s{{\[}}[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]{{\]}}, s{{\[}}[[SAVEEXEC_LO]]:[[SAVEEXEC_HI]]{{\]}}, [[CMP0]] ; GCN: s_and_b64 s[[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]], s[[[SAVEEXEC_LO]]:[[SAVEEXEC_HI]]], [[CMP0]]
; GCN: s_mov_b64 exec, s{{\[}}[[ANDEXEC_LO]]:[[ANDEXEC_HI]]{{\]}} ; GCN: s_mov_b64 exec, s[[[ANDEXEC_LO]]:[[ANDEXEC_HI]]]
; GCN: s_cbranch_execz [[ENDIF:.LBB[0-9]+_[0-9]+]] ; GCN: s_cbranch_execz [[ENDIF:.LBB[0-9]+_[0-9]+]]
; GCN: ; %bb.{{[0-9]+}}: ; %if ; GCN: ; %bb.{{[0-9]+}}: ; %if
; GCN: buffer_load_dword [[RELOAD_LOAD0:v[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload ; GCN: buffer_load_dword [[RELOAD_LOAD0:v[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload
; GCN: s_mov_b32 m0, -1 ; GCN: s_mov_b32 m0, -1
; GCN: ds_read_b32 [[LOAD1:v[0-9]+]] ; GCN: ds_read_b32 [[LOAD1:v[0-9]+]]
; GCN: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN: s_waitcnt vmcnt(0) lgkmcnt(0)
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; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]] ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]] ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
; VMEM: buffer_load_dword v[[V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 offset:[[V_EXEC_SPILL_OFFSET]] ; 4-byte Folded Reload ; VMEM: buffer_load_dword v[[V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 offset:[[V_EXEC_SPILL_OFFSET]] ; 4-byte Folded Reload
; VMEM: s_waitcnt vmcnt(0) ; VMEM: s_waitcnt vmcnt(0)
; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 0 ; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 0
; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 1 ; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 1
; GCN: s_or_b64 exec, exec, s{{\[}}[[S_RELOAD_SAVEEXEC_LO]]:[[S_RELOAD_SAVEEXEC_HI]]{{\]}} ; GCN: s_or_b64 exec, exec, s[[[S_RELOAD_SAVEEXEC_LO]]:[[S_RELOAD_SAVEEXEC_HI]]]
; Restore val ; Restore val
; GCN: buffer_load_dword [[RELOAD_VAL:v[0-9]+]], off, s[0:3], 0 offset:[[VAL_OFFSET]] ; 4-byte Folded Reload ; GCN: buffer_load_dword [[RELOAD_VAL:v[0-9]+]], off, s[0:3], 0 offset:[[VAL_OFFSET]] ; 4-byte Folded Reload
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RELOAD_VAL]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RELOAD_VAL]]
define amdgpu_kernel void @divergent_if_endif(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @divergent_if_endif(i32 addrspace(1)* %out) #0 {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
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; GCN: {{^}}; %bb.0: ; GCN: {{^}}; %bb.0:
; GCN-DAG: s_mov_b32 m0, -1 ; GCN-DAG: s_mov_b32 m0, -1
; GCN-DAG: v_mov_b32_e32 [[PTR0:v[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 [[PTR0:v[0-9]+]], 0{{$}}
; GCN: ds_read_b32 [[LOAD0:v[0-9]+]], [[PTR0]] ; GCN: ds_read_b32 [[LOAD0:v[0-9]+]], [[PTR0]]
; GCN: v_cmp_eq_u32_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], v0, s{{[0-9]+}} ; GCN: v_cmp_eq_u32_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], v0, s{{[0-9]+}}
; Spill load ; Spill load
; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], 0 offset:[[LOAD0_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], 0 offset:[[LOAD0_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN: s_mov_b64 s{{\[}}[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]{{\]}}, exec ; GCN: s_mov_b64 s[[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]], exec
; Spill saved exec ; Spill saved exec
; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]] ; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]
; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]] ; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]
; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0 ; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0
; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1 ; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1
; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 offset:[[V_EXEC_SPILL_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 offset:[[V_EXEC_SPILL_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN: s_and_b64 s{{\[}}[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]{{\]}}, s{{\[}}[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]{{\]}}, [[CMP0]] ; GCN: s_and_b64 s[[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]], s[[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]], [[CMP0]]
; GCN: s_mov_b64 exec, s{{\[}}[[ANDEXEC_LO]]:[[ANDEXEC_HI]]{{\]}} ; GCN: s_mov_b64 exec, s[[[ANDEXEC_LO]]:[[ANDEXEC_HI]]]
; GCN-NEXT: s_cbranch_execz [[END:.LBB[0-9]+_[0-9]+]] ; GCN-NEXT: s_cbranch_execz [[END:.LBB[0-9]+_[0-9]+]]
; GCN: [[LOOP:.LBB[0-9]+_[0-9]+]]: ; GCN: [[LOOP:.LBB[0-9]+_[0-9]+]]:
; GCN: buffer_load_dword v[[VAL_LOOP_RELOAD:[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload ; GCN: buffer_load_dword v[[VAL_LOOP_RELOAD:[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload
; GCN: v_subrev_i32_e32 [[VAL_LOOP:v[0-9]+]], vcc, v{{[0-9]+}}, v[[VAL_LOOP_RELOAD]] ; GCN: v_subrev_i32_e32 [[VAL_LOOP:v[0-9]+]], vcc, v{{[0-9]+}}, v[[VAL_LOOP_RELOAD]]
; GCN: s_cmp_lg_u32 ; GCN: s_cmp_lg_u32
; VMEM: buffer_store_dword ; VMEM: buffer_store_dword
; VMEM: buffer_store_dword ; VMEM: buffer_store_dword
; VMEM: buffer_store_dword ; VMEM: buffer_store_dword
; GCN: buffer_store_dword [[VAL_LOOP]], off, s[0:3], 0 offset:{{[0-9]+}} ; 4-byte Folded Spill ; GCN: buffer_store_dword [[VAL_LOOP]], off, s[0:3], 0 offset:{{[0-9]+}} ; 4-byte Folded Spill
; GCN-NEXT: s_cbranch_scc1 [[LOOP]] ; GCN-NEXT: s_cbranch_scc1 [[LOOP]]
; GCN: buffer_store_dword [[VAL_LOOP]], off, s[0:3], 0 offset:[[VAL_SUB_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; GCN: buffer_store_dword [[VAL_LOOP]], off, s[0:3], 0 offset:[[VAL_SUB_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN: [[END]]: ; GCN: [[END]]:
; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]] ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]] ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
; VMEM: buffer_load_dword v[[V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 offset:[[V_EXEC_SPILL_OFFSET]] ; 4-byte Folded Reload ; VMEM: buffer_load_dword v[[V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 offset:[[V_EXEC_SPILL_OFFSET]] ; 4-byte Folded Reload
; VMEM: s_waitcnt vmcnt(0) ; VMEM: s_waitcnt vmcnt(0)
; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 0 ; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 0
; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 1 ; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 1
; GCN: s_or_b64 exec, exec, s{{\[}}[[S_RELOAD_SAVEEXEC_LO]]:[[S_RELOAD_SAVEEXEC_HI]]{{\]}} ; GCN: s_or_b64 exec, exec, s[[[S_RELOAD_SAVEEXEC_LO]]:[[S_RELOAD_SAVEEXEC_HI]]]
; GCN: buffer_load_dword v[[VAL_END:[0-9]+]], off, s[0:3], 0 offset:[[VAL_SUB_OFFSET]] ; 4-byte Folded Reload ; GCN: buffer_load_dword v[[VAL_END:[0-9]+]], off, s[0:3], 0 offset:[[VAL_SUB_OFFSET]] ; 4-byte Folded Reload
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[VAL_END]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[VAL_END]]
define amdgpu_kernel void @divergent_loop(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @divergent_loop(i32 addrspace(1)* %out) #0 {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%load0 = load volatile i32, i32 addrspace(3)* null %load0 = load volatile i32, i32 addrspace(3)* null
%cmp0 = icmp eq i32 %tid, 0 %cmp0 = icmp eq i32 %tid, 0
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; GCN: ds_read_b32 [[LOAD0:v[0-9]+]], [[PTR0]] ; GCN: ds_read_b32 [[LOAD0:v[0-9]+]], [[PTR0]]
; Spill load ; Spill load
; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], 0 offset:[[LOAD0_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], 0 offset:[[LOAD0_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN: s_mov_b32 [[ZERO:s[0-9]+]], 0 ; GCN: s_mov_b32 [[ZERO:s[0-9]+]], 0
; GCN: v_cmp_ne_u32_e64 [[CMP0:s\[[0-9]+:[0-9]\]]], v0, [[ZERO]] ; GCN: v_cmp_ne_u32_e64 [[CMP0:s\[[0-9]+:[0-9]\]]], v0, [[ZERO]]
; GCN: s_mov_b64 s{{\[}}[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]{{\]}}, exec ; GCN: s_mov_b64 s[[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]], exec
; GCN: s_and_b64 s{{\[}}[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]{{\]}}, s{{\[}}[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]{{\]}}, [[CMP0]] ; GCN: s_and_b64 s[[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]], s[[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]], [[CMP0]]
; GCN: s_xor_b64 s{{\[}}[[SAVEEXEC_LO]]:[[SAVEEXEC_HI]]{{\]}}, s{{\[}}[[ANDEXEC_LO]]:[[ANDEXEC_HI]]{{\]}}, s{{\[}}[[SAVEEXEC_LO]]:[[SAVEEXEC_HI]]{{\]}} ; GCN: s_xor_b64 s[[[SAVEEXEC_LO]]:[[SAVEEXEC_HI]]], s[[[ANDEXEC_LO]]:[[ANDEXEC_HI]]], s[[[SAVEEXEC_LO]]:[[SAVEEXEC_HI]]]
; Spill saved exec ; Spill saved exec
; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]] ; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]
; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]] ; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]
; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0 ; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0
; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1 ; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1
; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 offset:[[SAVEEXEC_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 offset:[[SAVEEXEC_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN: s_mov_b64 exec, [[CMP0]] ; GCN: s_mov_b64 exec, [[CMP0]]
; FIXME: It makes no sense to put this skip here ; FIXME: It makes no sense to put this skip here
; GCN: s_cbranch_execz [[FLOW:.LBB[0-9]+_[0-9]+]] ; GCN: s_cbranch_execz [[FLOW:.LBB[0-9]+_[0-9]+]]
; GCN-NEXT: s_branch [[ELSE:.LBB[0-9]+_[0-9]+]] ; GCN-NEXT: s_branch [[ELSE:.LBB[0-9]+_[0-9]+]]
; GCN: [[FLOW]]: ; %Flow ; GCN: [[FLOW]]: ; %Flow
; VGPR: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]] ; VGPR: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
; VGPR: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]] ; VGPR: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
; VMEM: buffer_load_dword v[[FLOW_V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 offset:[[SAVEEXEC_OFFSET]] ; VMEM: buffer_load_dword v[[FLOW_V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 offset:[[SAVEEXEC_OFFSET]]
; VMEM: s_waitcnt vmcnt(0) ; VMEM: s_waitcnt vmcnt(0)
; VMEM: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[FLOW_V_RELOAD_SAVEEXEC]], 0 ; VMEM: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[FLOW_V_RELOAD_SAVEEXEC]], 0
; VMEM: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[FLOW_V_RELOAD_SAVEEXEC]], 1 ; VMEM: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[FLOW_V_RELOAD_SAVEEXEC]], 1
; GCN: s_or_saveexec_b64 s{{\[}}[[FLOW_S_RELOAD_SAVEEXEC_LO_SAVEEXEC:[0-9]+]]:[[FLOW_S_RELOAD_SAVEEXEC_HI_SAVEEXEC:[0-9]+]]{{\]}}, s{{\[}}[[FLOW_S_RELOAD_SAVEEXEC_LO]]:[[FLOW_S_RELOAD_SAVEEXEC_HI]]{{\]}} ; GCN: s_or_saveexec_b64 s[[[FLOW_S_RELOAD_SAVEEXEC_LO_SAVEEXEC:[0-9]+]]:[[FLOW_S_RELOAD_SAVEEXEC_HI_SAVEEXEC:[0-9]+]]], s[[[FLOW_S_RELOAD_SAVEEXEC_LO]]:[[FLOW_S_RELOAD_SAVEEXEC_HI]]]
; Regular spill value restored after exec modification ; Regular spill value restored after exec modification
; GCN: buffer_load_dword [[FLOW_VAL:v[0-9]+]], off, s[0:3], 0 offset:[[FLOW_VAL_OFFSET:[0-9]+]] ; 4-byte Folded Reload ; GCN: buffer_load_dword [[FLOW_VAL:v[0-9]+]], off, s[0:3], 0 offset:[[FLOW_VAL_OFFSET:[0-9]+]] ; 4-byte Folded Reload
; Followed by spill ; Followed by spill
; GCN: buffer_store_dword [[FLOW_VAL]], off, s[0:3], 0 offset:[[RESULT_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; GCN: buffer_store_dword [[FLOW_VAL]], off, s[0:3], 0 offset:[[RESULT_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN: s_and_b64 s{{\[}}[[FLOW_AND_EXEC_LO:[0-9]+]]:[[FLOW_AND_EXEC_HI:[0-9]+]]{{\]}}, exec, s{{\[}}[[FLOW_S_RELOAD_SAVEEXEC_LO_SAVEEXEC]]:[[FLOW_S_RELOAD_SAVEEXEC_HI_SAVEEXEC]]{{\]}} ; GCN: s_and_b64 s[[[FLOW_AND_EXEC_LO:[0-9]+]]:[[FLOW_AND_EXEC_HI:[0-9]+]]], exec, s[[[FLOW_S_RELOAD_SAVEEXEC_LO_SAVEEXEC]]:[[FLOW_S_RELOAD_SAVEEXEC_HI_SAVEEXEC]]]
; Spill saved exec ; Spill saved exec
; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[FLOW_AND_EXEC_LO]], [[FLOW_SAVEEXEC_LO_LANE:[0-9]+]] ; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[FLOW_AND_EXEC_LO]], [[FLOW_SAVEEXEC_LO_LANE:[0-9]+]]
; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[FLOW_AND_EXEC_HI]], [[FLOW_SAVEEXEC_HI_LANE:[0-9]+]] ; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[FLOW_AND_EXEC_HI]], [[FLOW_SAVEEXEC_HI_LANE:[0-9]+]]
; VMEM: v_writelane_b32 v[[FLOW_V_SAVEEXEC:[0-9]+]], s[[FLOW_AND_EXEC_LO]], 0 ; VMEM: v_writelane_b32 v[[FLOW_V_SAVEEXEC:[0-9]+]], s[[FLOW_AND_EXEC_LO]], 0
; VMEM: v_writelane_b32 v[[FLOW_V_SAVEEXEC]], s[[FLOW_AND_EXEC_HI]], 1 ; VMEM: v_writelane_b32 v[[FLOW_V_SAVEEXEC]], s[[FLOW_AND_EXEC_HI]], 1
; VMEM: buffer_store_dword v[[FLOW_V_SAVEEXEC]], off, s[0:3], 0 offset:[[FLOW_SAVEEXEC_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; VMEM: buffer_store_dword v[[FLOW_V_SAVEEXEC]], off, s[0:3], 0 offset:[[FLOW_SAVEEXEC_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN: s_xor_b64 exec, exec, s{{\[}}[[FLOW_AND_EXEC_LO]]:[[FLOW_AND_EXEC_HI]]{{\]}} ; GCN: s_xor_b64 exec, exec, s[[[FLOW_AND_EXEC_LO]]:[[FLOW_AND_EXEC_HI]]]
; GCN-NEXT: s_cbranch_execz [[ENDIF:.LBB[0-9]+_[0-9]+]] ; GCN-NEXT: s_cbranch_execz [[ENDIF:.LBB[0-9]+_[0-9]+]]
; GCN: ; %bb.{{[0-9]+}}: ; %if ; GCN: ; %bb.{{[0-9]+}}: ; %if
; GCN: buffer_load_dword v[[LOAD0_RELOAD:[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload ; GCN: buffer_load_dword v[[LOAD0_RELOAD:[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload
; GCN: ds_read_b32 ; GCN: ds_read_b32
; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, v{{[0-9]+}}, v[[LOAD0_RELOAD]] ; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, v{{[0-9]+}}, v[[LOAD0_RELOAD]]
; GCN: buffer_store_dword [[ADD]], off, s[0:3], 0 offset:[[RESULT_OFFSET]] ; 4-byte Folded Spill ; GCN: buffer_store_dword [[ADD]], off, s[0:3], 0 offset:[[RESULT_OFFSET]] ; 4-byte Folded Spill
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; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[FLOW_SAVEEXEC_HI_LANE]] ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[FLOW_SAVEEXEC_HI_LANE]]
; VMEM: buffer_load_dword v[[V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 offset:[[FLOW_SAVEEXEC_OFFSET]] ; 4-byte Folded Reload ; VMEM: buffer_load_dword v[[V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 offset:[[FLOW_SAVEEXEC_OFFSET]] ; 4-byte Folded Reload
; VMEM: s_waitcnt vmcnt(0) ; VMEM: s_waitcnt vmcnt(0)
; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 0 ; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 0
; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 1 ; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 1
; GCN: s_or_b64 exec, exec, s{{\[}}[[S_RELOAD_SAVEEXEC_LO]]:[[S_RELOAD_SAVEEXEC_HI]]{{\]}} ; GCN: s_or_b64 exec, exec, s[[[S_RELOAD_SAVEEXEC_LO]]:[[S_RELOAD_SAVEEXEC_HI]]]
; GCN: buffer_load_dword v[[RESULT:[0-9]+]], off, s[0:3], 0 offset:[[RESULT_OFFSET]] ; 4-byte Folded Reload ; GCN: buffer_load_dword v[[RESULT:[0-9]+]], off, s[0:3], 0 offset:[[RESULT_OFFSET]] ; 4-byte Folded Reload
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RESULT]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RESULT]]
define amdgpu_kernel void @divergent_if_else_endif(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @divergent_if_else_endif(i32 addrspace(1)* %out) #0 {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%load0 = load volatile i32, i32 addrspace(3)* null %load0 = load volatile i32, i32 addrspace(3)* null
%cmp0 = icmp eq i32 %tid, 0 %cmp0 = icmp eq i32 %tid, 0
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llvm/test/CodeGen/AMDGPU/ctpop64.ll

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define amdgpu_kernel void @s_ctpop_i64(i32 addrspace(1)* noalias %out, [8 x i32], i64 %val) nounwind { define amdgpu_kernel void @s_ctpop_i64(i32 addrspace(1)* noalias %out, [8 x i32], i64 %val) nounwind {
%ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone %ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
%truncctpop = trunc i64 %ctpop to i32 %truncctpop = trunc i64 %ctpop to i32
store i32 %truncctpop, i32 addrspace(1)* %out, align 4 store i32 %truncctpop, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; FUNC-LABEL: {{^}}v_ctpop_i64: ; FUNC-LABEL: {{^}}v_ctpop_i64:
; GCN: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, ; GCN: {{buffer|flat}}_load_dwordx2 v[[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]],
; GCN: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0 ; GCN: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0
; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]] ; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
; VI-NEXT: v_bcnt_u32_b32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]] ; VI-NEXT: v_bcnt_u32_b32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
; GCN: buffer_store_dword [[RESULT]], ; GCN: buffer_store_dword [[RESULT]],
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @v_ctpop_i64(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { define amdgpu_kernel void @v_ctpop_i64(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
%val = load i64, i64 addrspace(1)* %in.gep, align 8 %val = load i64, i64 addrspace(1)* %in.gep, align 8
%ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone %ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
%truncctpop = trunc i64 %ctpop to i32 %truncctpop = trunc i64 %ctpop to i32
store i32 %truncctpop, i32 addrspace(1)* %out, align 4 store i32 %truncctpop, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; FUNC-LABEL: {{^}}v_ctpop_i64_user: ; FUNC-LABEL: {{^}}v_ctpop_i64_user:
; GCN: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, ; GCN: {{buffer|flat}}_load_dwordx2 v[[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]],
; GCN: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0 ; GCN: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0
; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]] ; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
; VI-NEXT: v_bcnt_u32_b32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]] ; VI-NEXT: v_bcnt_u32_b32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
; GCN-DAG: v_or_b32_e32 v[[RESULT_LO:[0-9]+]], s{{[0-9]+}}, [[RESULT]] ; GCN-DAG: v_or_b32_e32 v[[RESULT_LO:[0-9]+]], s{{[0-9]+}}, [[RESULT]]
; GCN-DAG: v_mov_b32_e32 v[[RESULT_HI:[0-9]+]], s{{[0-9]+}} ; GCN-DAG: v_mov_b32_e32 v[[RESULT_HI:[0-9]+]], s{{[0-9]+}}
; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[RESULT_LO]]:[[RESULT_HI]]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @v_ctpop_i64_user(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %s.val) nounwind { define amdgpu_kernel void @v_ctpop_i64_user(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %s.val) nounwind {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
%val = load i64, i64 addrspace(1)* %in.gep, align 8 %val = load i64, i64 addrspace(1)* %in.gep, align 8
%ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone %ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
%or = or i64 %ctpop, %s.val %or = or i64 %ctpop, %s.val
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> addrspace(1)* noalias %in) nounwind {
%val = load <4 x i64>, <4 x i64> addrspace(1)* %in.gep, align 32 %val = load <4 x i64>, <4 x i64> addrspace(1)* %in.gep, align 32
%ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
%truncctpop = trunc <4 x i64> %ctpop to <4 x i32> %truncctpop = trunc <4 x i64> %ctpop to <4 x i32>
store <4 x i32> %truncctpop, <4 x i32> addrspace(1)* %out, align 16 store <4 x i32> %truncctpop, <4 x i32> addrspace(1)* %out, align 16
ret void ret void
} }
; FUNC-LABEL: {{^}}ctpop_i64_in_br: ; FUNC-LABEL: {{^}}ctpop_i64_in_br:
; SI-DAG: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xd ; SI-DAG: s_load_dwordx2 s[[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]], s[{{[0-9]+:[0-9]+}}], 0xd
; VI-DAG: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x34 ; VI-DAG: s_load_dwordx2 s[[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]], s[{{[0-9]+:[0-9]+}}], 0x34
; GCN-DAG: s_bcnt1_i32_b64 [[RESULT:s[0-9]+]], {{s\[}}[[LOVAL]]:[[HIVAL]]{{\]}} ; GCN-DAG: s_bcnt1_i32_b64 [[RESULT:s[0-9]+]], {{s\[}}[[LOVAL]]:[[HIVAL]]]
; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0 ; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0
; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], [[RESULT]] ; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], [[RESULT]]
; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[ZERO]] ; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[ZERO]]
; GCN: buffer_store_dwordx2 {{v\[}}[[VLO]]:[[VHI]]{{\]}} ; GCN: buffer_store_dwordx2 {{v\[}}[[VLO]]:[[VHI]]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @ctpop_i64_in_br(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %ctpop_arg, i32 %cond) { define amdgpu_kernel void @ctpop_i64_in_br(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %ctpop_arg, i32 %cond) {
entry: entry:
%tmp0 = icmp eq i32 %cond, 0 %tmp0 = icmp eq i32 %cond, 0
br i1 %tmp0, label %if, label %else br i1 %tmp0, label %if, label %else
if: if:
%tmp2 = call i64 @llvm.ctpop.i64(i64 %ctpop_arg) %tmp2 = call i64 @llvm.ctpop.i64(i64 %ctpop_arg)
Show All 33 Linesdefine amdgpu_kernel void @s_ctpop_i65(i32 addrspace(1)* noalias %out, i65 %val) nounwind {
%truncctpop = trunc i65 %ctpop to i32 %truncctpop = trunc i65 %ctpop to i32
store i32 %truncctpop, i32 addrspace(1)* %out, align 4 store i32 %truncctpop, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; FIXME: Should not have extra add ; FIXME: Should not have extra add
; FUNC-LABEL: {{^}}v_ctpop_i128: ; FUNC-LABEL: {{^}}v_ctpop_i128:
; SI: buffer_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 ; SI: buffer_load_dwordx4 v[[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
; VI: flat_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}} ; VI: flat_load_dwordx4 v[[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]], v{{\[[0-9]+:[0-9]+\]}}
; GCN-DAG: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT0:v[0-9]+]], v{{[0-9]+}}, 0 ; GCN-DAG: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT0:v[0-9]+]], v{{[0-9]+}}, 0
; GCN-DAG: v_bcnt_u32_b32{{(_e32)*(_e64)*}} [[MIDRESULT1:v[0-9]+]], v[[VAL3]], [[MIDRESULT0]] ; GCN-DAG: v_bcnt_u32_b32{{(_e32)*(_e64)*}} [[MIDRESULT1:v[0-9]+]], v[[VAL3]], [[MIDRESULT0]]
; GCN-DAG: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT2:v[0-9]+]], v[[VAL0]], 0 ; GCN-DAG: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT2:v[0-9]+]], v[[VAL0]], 0
; GCN-DAG: v_bcnt_u32_b32{{(_e32)*(_e64)*}} [[MIDRESULT3:v[0-9]+]], v{{[0-9]+}}, [[MIDRESULT2]] ; GCN-DAG: v_bcnt_u32_b32{{(_e32)*(_e64)*}} [[MIDRESULT3:v[0-9]+]], v{{[0-9]+}}, [[MIDRESULT2]]
; GCN: v_add_{{[iu]}}32_e32 [[RESULT:v[0-9]+]], vcc, [[MIDRESULT2]], [[MIDRESULT1]] ; GCN: v_add_{{[iu]}}32_e32 [[RESULT:v[0-9]+]], vcc, [[MIDRESULT2]], [[MIDRESULT1]]
Show All 12 Lines

llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll

Show All 30 Linesdefine amdgpu_kernel void @simple_read2_v2f32_superreg(<2 x float> addrspace(1)* %out) #0 {
%arrayidx0 = getelementptr inbounds [512 x <2 x float>], [512 x <2 x float>] addrspace(3)* @lds.v2, i32 0, i32 %x.i %arrayidx0 = getelementptr inbounds [512 x <2 x float>], [512 x <2 x float>] addrspace(3)* @lds.v2, i32 0, i32 %x.i
%val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0 %val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0
%out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i %out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i
store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep
ret void ret void
} }
; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align4: ; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align4:
; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}} ; CI-DAG: ds_read2_b32 v[[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]], v{{[0-9]+}} offset1:1{{$}}
; CI-DAG: ds_read2_b32 v{{\[}}[[REG_Z:[0-9]+]]:[[REG_W:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}} ; CI-DAG: ds_read2_b32 v[[[REG_Z:[0-9]+]]:[[REG_W:[0-9]+]]], v{{[0-9]+}} offset0:2 offset1:3{{$}}
; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_X]], v[[REG_Z]] ; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_X]], v[[REG_Z]]
; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[REG_Y]], v[[REG_W]] ; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[REG_Y]], v[[REG_W]]
; CI: v_add_f32_e32 v[[ADD2:[0-9]+]], v[[ADD0]], v[[ADD1]] ; CI: v_add_f32_e32 v[[ADD2:[0-9]+]], v[[ADD0]], v[[ADD1]]
; CI: buffer_store_dword v[[ADD2]] ; CI: buffer_store_dword v[[ADD2]]
; CI: s_endpgm ; CI: s_endpgm
define amdgpu_kernel void @simple_read2_v4f32_superreg_align4(float addrspace(1)* %out) #0 { define amdgpu_kernel void @simple_read2_v4f32_superreg_align4(float addrspace(1)* %out) #0 {
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i %arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i
%val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0, align 4 %val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0, align 4
%elt0 = extractelement <4 x float> %val0, i32 0 %elt0 = extractelement <4 x float> %val0, i32 0
%elt1 = extractelement <4 x float> %val0, i32 1 %elt1 = extractelement <4 x float> %val0, i32 1
%elt2 = extractelement <4 x float> %val0, i32 2 %elt2 = extractelement <4 x float> %val0, i32 2
%elt3 = extractelement <4 x float> %val0, i32 3 %elt3 = extractelement <4 x float> %val0, i32 3
%add0 = fadd float %elt0, %elt2 %add0 = fadd float %elt0, %elt2
%add1 = fadd float %elt1, %elt3 %add1 = fadd float %elt1, %elt3
%add2 = fadd float %add0, %add1 %add2 = fadd float %add0, %add1
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
store float %add2, float addrspace(1)* %out.gep store float %add2, float addrspace(1)* %out.gep
ret void ret void
} }
; CI-LABEL: {{^}}simple_read2_v3f32_superreg_align4: ; CI-LABEL: {{^}}simple_read2_v3f32_superreg_align4:
; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}} ; CI-DAG: ds_read2_b32 v[[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]], v{{[0-9]+}} offset1:1{{$}}
; CI-DAG: ds_read_b32 v[[REG_Z:[0-9]+]], v{{[0-9]+}} offset:8{{$}} ; CI-DAG: ds_read_b32 v[[REG_Z:[0-9]+]], v{{[0-9]+}} offset:8{{$}}
; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_X]], v[[REG_Z]] ; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_X]], v[[REG_Z]]
; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[ADD0]], v[[REG_Y]] ; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[ADD0]], v[[REG_Y]]
; CI: buffer_store_dword v[[ADD1]] ; CI: buffer_store_dword v[[ADD1]]
; CI: s_endpgm ; CI: s_endpgm
define amdgpu_kernel void @simple_read2_v3f32_superreg_align4(float addrspace(1)* %out) #0 { define amdgpu_kernel void @simple_read2_v3f32_superreg_align4(float addrspace(1)* %out) #0 {
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%arrayidx0 = getelementptr inbounds [512 x <3 x float>], [512 x <3 x float>] addrspace(3)* @lds.v3, i32 0, i32 %x.i %arrayidx0 = getelementptr inbounds [512 x <3 x float>], [512 x <3 x float>] addrspace(3)* @lds.v3, i32 0, i32 %x.i
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @simple_read2_v16f32_superreg(<16 x float> addrspace(1)* %out) #0 {
%val0 = load <16 x float>, <16 x float> addrspace(3)* %arrayidx0 %val0 = load <16 x float>, <16 x float> addrspace(3)* %arrayidx0
%out.gep = getelementptr inbounds <16 x float>, <16 x float> addrspace(1)* %out, i32 %x.i %out.gep = getelementptr inbounds <16 x float>, <16 x float> addrspace(1)* %out, i32 %x.i
store <16 x float> %val0, <16 x float> addrspace(1)* %out.gep store <16 x float> %val0, <16 x float> addrspace(1)* %out.gep
ret void ret void
} }
; Do scalar loads into the super register we need. ; Do scalar loads into the super register we need.
; CI-LABEL: {{^}}simple_read2_v2f32_superreg_scalar_loads_align4: ; CI-LABEL: {{^}}simple_read2_v2f32_superreg_scalar_loads_align4:
; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}} ; CI-DAG: ds_read2_b32 v[[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]], v{{[0-9]+}} offset1:1{{$}}
; CI-NOT: v_mov {{v[0-9]+}}, {{[sv][0-9]+}} ; CI-NOT: v_mov {{v[0-9]+}}, {{[sv][0-9]+}}
; CI: buffer_store_dwordx2 v{{\[}}[[REG_ELT0]]:[[REG_ELT1]]{{\]}} ; CI: buffer_store_dwordx2 v[[[REG_ELT0]]:[[REG_ELT1]]]
; CI: s_endpgm ; CI: s_endpgm
define amdgpu_kernel void @simple_read2_v2f32_superreg_scalar_loads_align4(<2 x float> addrspace(1)* %out) #0 { define amdgpu_kernel void @simple_read2_v2f32_superreg_scalar_loads_align4(<2 x float> addrspace(1)* %out) #0 {
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
%arrayidx1 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 1 %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 1
%val0 = load float, float addrspace(3)* %arrayidx0 %val0 = load float, float addrspace(3)* %arrayidx0
%val1 = load float, float addrspace(3)* %arrayidx1 %val1 = load float, float addrspace(3)* %arrayidx1
%vec.0 = insertelement <2 x float> undef, float %val0, i32 0 %vec.0 = insertelement <2 x float> undef, float %val0, i32 0
%vec.1 = insertelement <2 x float> %vec.0, float %val1, i32 1 %vec.1 = insertelement <2 x float> %vec.0, float %val1, i32 1
%out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i %out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i
store <2 x float> %vec.1, <2 x float> addrspace(1)* %out.gep store <2 x float> %vec.1, <2 x float> addrspace(1)* %out.gep
ret void ret void
} }
; Do scalar loads into the super register we need. ; Do scalar loads into the super register we need.
; CI-LABEL: {{^}}simple_read2_v4f32_superreg_scalar_loads_align4: ; CI-LABEL: {{^}}simple_read2_v4f32_superreg_scalar_loads_align4:
; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}} ; CI-DAG: ds_read2_b32 v[[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]], v{{[0-9]+}} offset1:1{{$}}
; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT2:[0-9]+]]:[[REG_ELT3:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}} ; CI-DAG: ds_read2_b32 v[[[REG_ELT2:[0-9]+]]:[[REG_ELT3:[0-9]+]]], v{{[0-9]+}} offset0:2 offset1:3{{$}}
; CI-NOT: v_mov {{v[0-9]+}}, {{[sv][0-9]+}} ; CI-NOT: v_mov {{v[0-9]+}}, {{[sv][0-9]+}}
; CI: buffer_store_dwordx4 v{{\[}}[[REG_ELT0]]:[[REG_ELT3]]{{\]}} ; CI: buffer_store_dwordx4 v[[[REG_ELT0]]:[[REG_ELT3]]]
; CI: s_endpgm ; CI: s_endpgm
define amdgpu_kernel void @simple_read2_v4f32_superreg_scalar_loads_align4(<4 x float> addrspace(1)* %out) #0 { define amdgpu_kernel void @simple_read2_v4f32_superreg_scalar_loads_align4(<4 x float> addrspace(1)* %out) #0 {
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
%arrayidx1 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 1 %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 1
%arrayidx2 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 2 %arrayidx2 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 2
%arrayidx3 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 3 %arrayidx3 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 3
Show All 24 Lines

llvm/test/CodeGen/AMDGPU/ds_read2st64.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
@lds = addrspace(3) global [512 x float] undef, align 4 @lds = addrspace(3) global [512 x float] undef, align 4
@lds.f64 = addrspace(3) global [512 x double] undef, align 8 @lds.f64 = addrspace(3) global [512 x double] undef, align 8
; GCN-LABEL: @simple_read2st64_f32_0_1 ; GCN-LABEL: @simple_read2st64_f32_0_1
; CI: s_mov_b32 m0 ; CI: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1 ; GCN: ds_read2st64_b32 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]], v{{[0-9]+}} offset1:1
; GCN: s_waitcnt lgkmcnt(0) ; GCN: s_waitcnt lgkmcnt(0)
; GCN: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[LO_VREG]], v[[HI_VREG]] ; GCN: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[LO_VREG]], v[[HI_VREG]]
; CI: buffer_store_dword [[RESULT]] ; CI: buffer_store_dword [[RESULT]]
; GFX9: global_store_dword v{{[0-9]+}}, [[RESULT]], s{{\[[0-9]+:[0-9]+\]}} ; GFX9: global_store_dword v{{[0-9]+}}, [[RESULT]], s{{\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @simple_read2st64_f32_0_1(float addrspace(1)* %out) #0 { define amdgpu_kernel void @simple_read2st64_f32_0_1(float addrspace(1)* %out) #0 {
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
%val0 = load float, float addrspace(3)* %arrayidx0, align 4 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
%add.x = add nsw i32 %x.i, 64 %add.x = add nsw i32 %x.i, 64
%arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
%val1 = load float, float addrspace(3)* %arrayidx1, align 4 %val1 = load float, float addrspace(3)* %arrayidx1, align 4
%sum = fadd float %val0, %val1 %sum = fadd float %val0, %val1
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
store float %sum, float addrspace(1)* %out.gep, align 4 store float %sum, float addrspace(1)* %out.gep, align 4
ret void ret void
} }
; GCN-LABEL: @simple_read2st64_f32_1_2 ; GCN-LABEL: @simple_read2st64_f32_1_2
; CI: s_mov_b32 m0 ; CI: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:2 ; GCN: ds_read2st64_b32 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]], v{{[0-9]+}} offset0:1 offset1:2
; GCN: s_waitcnt lgkmcnt(0) ; GCN: s_waitcnt lgkmcnt(0)
; GCN: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[LO_VREG]], v[[HI_VREG]] ; GCN: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[LO_VREG]], v[[HI_VREG]]
; CI: buffer_store_dword [[RESULT]] ; CI: buffer_store_dword [[RESULT]]
; GFX9: global_store_dword v{{[0-9]+}}, [[RESULT]], s{{\[[0-9]+:[0-9]+\]}} ; GFX9: global_store_dword v{{[0-9]+}}, [[RESULT]], s{{\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @simple_read2st64_f32_1_2(float addrspace(1)* %out, float addrspace(3)* %lds) #0 { define amdgpu_kernel void @simple_read2st64_f32_1_2(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%add.x.0 = add nsw i32 %x.i, 64 %add.x.0 = add nsw i32 %x.i, 64
%arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.0 %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.0
%val0 = load float, float addrspace(3)* %arrayidx0, align 4 %val0 = load float, float addrspace(3)* %arrayidx0, align 4
%add.x.1 = add nsw i32 %x.i, 128 %add.x.1 = add nsw i32 %x.i, 128
%arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.1 %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.1
%val1 = load float, float addrspace(3)* %arrayidx1, align 4 %val1 = load float, float addrspace(3)* %arrayidx1, align 4
%sum = fadd float %val0, %val1 %sum = fadd float %val0, %val1
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
store float %sum, float addrspace(1)* %out.gep, align 4 store float %sum, float addrspace(1)* %out.gep, align 4
ret void ret void
} }
; GCN-LABEL: @simple_read2st64_f32_max_offset ; GCN-LABEL: @simple_read2st64_f32_max_offset
; CI: s_mov_b32 m0 ; CI: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:255 ; GCN: ds_read2st64_b32 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]], v{{[0-9]+}} offset0:1 offset1:255
; GCN: s_waitcnt lgkmcnt(0) ; GCN: s_waitcnt lgkmcnt(0)
; GCN: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[LO_VREG]], v[[HI_VREG]] ; GCN: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[LO_VREG]], v[[HI_VREG]]
; CI: buffer_store_dword [[RESULT]] ; CI: buffer_store_dword [[RESULT]]
; GFX9: global_store_dword v{{[0-9]+}}, [[RESULT]], s{{\[[0-9]+:[0-9]+\]}} ; GFX9: global_store_dword v{{[0-9]+}}, [[RESULT]], s{{\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @simple_read2st64_f32_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 { define amdgpu_kernel void @simple_read2st64_f32_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%add.x.0 = add nsw i32 %x.i, 64 %add.x.0 = add nsw i32 %x.i, 64
%arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.0 %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.0
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @odd_invalid_read2st64_f32_1(float addrspace(1)* %out) #0 {
store float %sum, float addrspace(1)* %out.gep, align 4 store float %sum, float addrspace(1)* %out.gep, align 4
ret void ret void
} }
; GCN-LABEL: @simple_read2st64_f64_0_1 ; GCN-LABEL: @simple_read2st64_f64_0_1
; CI: s_mov_b32 m0 ; CI: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1 ; GCN: ds_read2st64_b64 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]], v{{[0-9]+}} offset1:1
; GCN: s_waitcnt lgkmcnt(0) ; GCN: s_waitcnt lgkmcnt(0)
; GCN: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}} ; GCN: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v[[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]]
; CI: buffer_store_dwordx2 [[RESULT]] ; CI: buffer_store_dwordx2 [[RESULT]]
; GFX9: global_store_dwordx2 v{{[0-9]+}}, [[RESULT]], s{{\[[0-9]+:[0-9]+\]}} ; GFX9: global_store_dwordx2 v{{[0-9]+}}, [[RESULT]], s{{\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @simple_read2st64_f64_0_1(double addrspace(1)* %out) #0 { define amdgpu_kernel void @simple_read2st64_f64_0_1(double addrspace(1)* %out) #0 {
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
%val0 = load double, double addrspace(3)* %arrayidx0, align 8 %val0 = load double, double addrspace(3)* %arrayidx0, align 8
%add.x = add nsw i32 %x.i, 64 %add.x = add nsw i32 %x.i, 64
%arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
%val1 = load double, double addrspace(3)* %arrayidx1, align 8 %val1 = load double, double addrspace(3)* %arrayidx1, align 8
%sum = fadd double %val0, %val1 %sum = fadd double %val0, %val1
%out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
store double %sum, double addrspace(1)* %out.gep, align 8 store double %sum, double addrspace(1)* %out.gep, align 8
ret void ret void
} }
; GCN-LABEL: @simple_read2st64_f64_1_2 ; GCN-LABEL: @simple_read2st64_f64_1_2
; CI: s_mov_b32 m0 ; CI: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:2 ; GCN: ds_read2st64_b64 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]], v{{[0-9]+}} offset0:1 offset1:2
; GCN: s_waitcnt lgkmcnt(0) ; GCN: s_waitcnt lgkmcnt(0)
; GCN: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}} ; GCN: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v[[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]]
; CI: buffer_store_dwordx2 [[RESULT]] ; CI: buffer_store_dwordx2 [[RESULT]]
; GFX9: global_store_dwordx2 v{{[0-9]+}}, [[RESULT]], s{{\[[0-9]+:[0-9]+\]}} ; GFX9: global_store_dwordx2 v{{[0-9]+}}, [[RESULT]], s{{\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @simple_read2st64_f64_1_2(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { define amdgpu_kernel void @simple_read2st64_f64_1_2(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%add.x.0 = add nsw i32 %x.i, 64 %add.x.0 = add nsw i32 %x.i, 64
%arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0
%val0 = load double, double addrspace(3)* %arrayidx0, align 8 %val0 = load double, double addrspace(3)* %arrayidx0, align 8
Show All 28 Linesdefine amdgpu_kernel void @misaligned_read2st64_f64(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
ret void ret void
} }
; The maximum is not the usual 0xff because 0xff * 8 * 64 > 0xffff ; The maximum is not the usual 0xff because 0xff * 8 * 64 > 0xffff
; GCN-LABEL: @simple_read2st64_f64_max_offset ; GCN-LABEL: @simple_read2st64_f64_max_offset
; CI: s_mov_b32 m0 ; CI: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:4 offset1:127 ; GCN: ds_read2st64_b64 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]], v{{[0-9]+}} offset0:4 offset1:127
; GCN: s_waitcnt lgkmcnt(0) ; GCN: s_waitcnt lgkmcnt(0)
; GCN: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}} ; GCN: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v[[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]]
; CI: buffer_store_dwordx2 [[RESULT]] ; CI: buffer_store_dwordx2 [[RESULT]]
; GFX9: global_store_dwordx2 v{{[0-9]+}}, [[RESULT]], s{{\[[0-9]+:[0-9]+\]}} ; GFX9: global_store_dwordx2 v{{[0-9]+}}, [[RESULT]], s{{\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @simple_read2st64_f64_max_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { define amdgpu_kernel void @simple_read2st64_f64_max_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%add.x.0 = add nsw i32 %x.i, 256 %add.x.0 = add nsw i32 %x.i, 256
%arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0
%val0 = load double, double addrspace(3)* %arrayidx0, align 8 %val0 = load double, double addrspace(3)* %arrayidx0, align 8
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llvm/test/CodeGen/AMDGPU/early-if-convert-cost.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -stress-early-ifcvt -amdgpu-early-ifcvt=1 -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -stress-early-ifcvt -amdgpu-early-ifcvt=1 -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -stress-early-ifcvt -amdgpu-early-ifcvt=1 -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCNX3 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -stress-early-ifcvt -amdgpu-early-ifcvt=1 -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCNX3 %s
; FIXME: Most of these cases that don't trigger because of broken cost ; FIXME: Most of these cases that don't trigger because of broken cost
; heuristics. Should not need -stress-early-ifcvt ; heuristics. Should not need -stress-early-ifcvt
; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle64: ; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle64:
; GCN: buffer_load_dwordx2 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} ; GCN: buffer_load_dwordx2 v[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]]
; GCN: v_cmp_neq_f64_e32 vcc, 1.0, v{{\[}}[[VAL_LO]]:[[VAL_HI]]{{\]}} ; GCN: v_cmp_neq_f64_e32 vcc, 1.0, v[[[VAL_LO]]:[[VAL_HI]]]
; GCN: v_add_f64 v{{\[}}[[ADD_LO:[0-9]+]]:[[ADD_HI:[0-9]+]]{{\]}}, v{{\[}}[[VAL_LO]]:[[VAL_HI]]{{\]}}, v{{\[}}[[VAL_LO]]:[[VAL_HI]]{{\]}} ; GCN: v_add_f64 v[[[ADD_LO:[0-9]+]]:[[ADD_HI:[0-9]+]]], v[[[VAL_LO]]:[[VAL_HI]]], v[[[VAL_LO]]:[[VAL_HI]]]
; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_LO:[0-9]+]], v[[ADD_LO]], v[[VAL_LO]], vcc ; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_LO:[0-9]+]], v[[ADD_LO]], v[[VAL_LO]], vcc
; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_HI:[0-9]+]], v[[ADD_HI]], v[[VAL_HI]], vcc ; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_HI:[0-9]+]], v[[ADD_HI]], v[[VAL_HI]], vcc
; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[RESULT_LO]]:[[RESULT_HI]]]
define amdgpu_kernel void @test_vccnz_ifcvt_triangle64(double addrspace(1)* %out, double addrspace(1)* %in) #0 { define amdgpu_kernel void @test_vccnz_ifcvt_triangle64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
entry: entry:
%v = load double, double addrspace(1)* %in %v = load double, double addrspace(1)* %in
%cc = fcmp oeq double %v, 1.000000e+00 %cc = fcmp oeq double %v, 1.000000e+00
br i1 %cc, label %if, label %endif br i1 %cc, label %if, label %endif
if: if:
%u = fadd double %v, %v %u = fadd double %v, %v
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llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; GCN-LABEL: {{^}}half4_extelt: ; GCN-LABEL: {{^}}half4_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x40003c00 ; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x40003c00
; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x44004200 ; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x44004200
; GCN-DAG: s_lshl_b32 [[SEL:s[0-p]+]], s{{[0-9]+}}, 4 ; GCN-DAG: s_lshl_b32 [[SEL:s[0-p]+]], s{{[0-9]+}}, 4
; GCN: s_lshr_b64 s{{\[}}[[RL:[0-9]+]]:{{[0-9]+}}], s{{\[}}[[SL]]:[[SH]]], [[SEL]] ; GCN: s_lshr_b64 s[[[RL:[0-9]+]]:{{[0-9]+}}], s[[[SL]]:[[SH]]], [[SEL]]
; GCN-DAG: v_mov_b32_e32 v[[VRL:[0-9]+]], s[[RL]] ; GCN-DAG: v_mov_b32_e32 v[[VRL:[0-9]+]], s[[RL]]
; GCN: store_short v[{{[0-9:]+}}], v[[VRL]] ; GCN: store_short v[{{[0-9:]+}}], v[[VRL]]
define amdgpu_kernel void @half4_extelt(half addrspace(1)* %out, i32 %sel) { define amdgpu_kernel void @half4_extelt(half addrspace(1)* %out, i32 %sel) {
entry: entry:
%ext = extractelement <4 x half> <half 1.0, half 2.0, half 3.0, half 4.0>, i32 %sel %ext = extractelement <4 x half> <half 1.0, half 2.0, half 3.0, half 4.0>, i32 %sel
store half %ext, half addrspace(1)* %out store half %ext, half addrspace(1)* %out
ret void ret void
} }
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; GCN-LABEL: {{^}}double8_extelt: ; GCN-LABEL: {{^}}double8_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-NOT: s_or_b32 ; GCN-NOT: s_or_b32
; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0{{$}} ; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0{{$}}
; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]] ; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]]
; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]] ; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]]
; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]] ; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]]
; GCN-DAG: v_movrels_b32_e32 v[[RES_HI:[0-9]+]], v[[#BASE+1]] ; GCN-DAG: v_movrels_b32_e32 v[[RES_HI:[0-9]+]], v[[#BASE+1]]
; GCN: store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[RES_LO]]:[[RES_HI]]] ; GCN: store_dwordx2 v[{{[0-9:]+}}], v[[[RES_LO]]:[[RES_HI]]]
define amdgpu_kernel void @double8_extelt(double addrspace(1)* %out, i32 %sel) { define amdgpu_kernel void @double8_extelt(double addrspace(1)* %out, i32 %sel) {
entry: entry:
%ext = extractelement <8 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0>, i32 %sel %ext = extractelement <8 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0>, i32 %sel
store double %ext, double addrspace(1)* %out store double %ext, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}double7_extelt: ; GCN-LABEL: {{^}}double7_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-NOT: s_or_b32 ; GCN-NOT: s_or_b32
; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0{{$}} ; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0{{$}}
; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]] ; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]]
; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]] ; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]]
; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]] ; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]]
; GCN-DAG: v_movrels_b32_e32 v[[RES_HI:[0-9]+]], v[[#BASE+1]] ; GCN-DAG: v_movrels_b32_e32 v[[RES_HI:[0-9]+]], v[[#BASE+1]]
; GCN: store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[RES_LO]]:[[RES_HI]]] ; GCN: store_dwordx2 v[{{[0-9:]+}}], v[[[RES_LO]]:[[RES_HI]]]
define amdgpu_kernel void @double7_extelt(double addrspace(1)* %out, i32 %sel) { define amdgpu_kernel void @double7_extelt(double addrspace(1)* %out, i32 %sel) {
entry: entry:
%ext = extractelement <7 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0>, i32 %sel %ext = extractelement <7 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0>, i32 %sel
store double %ext, double addrspace(1)* %out store double %ext, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}float16_extelt: ; GCN-LABEL: {{^}}float16_extelt:
Show All 27 Lines
; GCN-LABEL: {{^}}double15_extelt: ; GCN-LABEL: {{^}}double15_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-NOT: s_or_b32 ; GCN-NOT: s_or_b32
; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0{{$}} ; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0{{$}}
; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]] ; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]]
; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]] ; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]]
; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]] ; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]]
; GCN-DAG: v_movrels_b32_e32 v[[RES_HI:[0-9]+]], v[[#BASE+1]] ; GCN-DAG: v_movrels_b32_e32 v[[RES_HI:[0-9]+]], v[[#BASE+1]]
; GCN: store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[RES_LO]]:[[RES_HI]]] ; GCN: store_dwordx2 v[{{[0-9:]+}}], v[[[RES_LO]]:[[RES_HI]]]
define amdgpu_kernel void @double15_extelt(double addrspace(1)* %out, i32 %sel) { define amdgpu_kernel void @double15_extelt(double addrspace(1)* %out, i32 %sel) {
entry: entry:
%ext = extractelement <15 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0, double 9.0, double 10.0, double 11.0, double 12.0, double 13.0, double 14.0, double 15.0>, i32 %sel %ext = extractelement <15 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0, double 9.0, double 10.0, double 11.0, double 12.0, double 13.0, double 14.0, double 15.0>, i32 %sel
store double %ext, double addrspace(1)* %out store double %ext, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}double16_extelt: ; GCN-LABEL: {{^}}double16_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-NOT: s_or_b32 ; GCN-NOT: s_or_b32
; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0{{$}} ; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0{{$}}
; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]] ; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]]
; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]] ; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]]
; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]] ; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]]
; GCN-DAG: v_movrels_b32_e32 v[[RES_HI:[0-9]+]], v[[#BASE+1]] ; GCN-DAG: v_movrels_b32_e32 v[[RES_HI:[0-9]+]], v[[#BASE+1]]
; GCN: store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[RES_LO]]:[[RES_HI]]] ; GCN: store_dwordx2 v[{{[0-9:]+}}], v[[[RES_LO]]:[[RES_HI]]]
define amdgpu_kernel void @double16_extelt(double addrspace(1)* %out, i32 %sel) { define amdgpu_kernel void @double16_extelt(double addrspace(1)* %out, i32 %sel) {
entry: entry:
%ext = extractelement <16 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0, double 9.0, double 10.0, double 11.0, double 12.0, double 13.0, double 14.0, double 15.0, double 16.0>, i32 %sel %ext = extractelement <16 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0, double 9.0, double 10.0, double 11.0, double 12.0, double 13.0, double 14.0, double 15.0, double 16.0>, i32 %sel
store double %ext, double addrspace(1)* %out store double %ext, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}float32_extelt: ; GCN-LABEL: {{^}}float32_extelt:
Show All 40 Linesentry:
ret void ret void
} }
; GCN-LABEL: {{^}}byte8_extelt: ; GCN-LABEL: {{^}}byte8_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x4030201 ; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x4030201
; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x8070605 ; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x8070605
; GCN-DAG: s_lshl_b32 [[SEL:s[0-p]+]], s{{[0-9]+}}, 3 ; GCN-DAG: s_lshl_b32 [[SEL:s[0-p]+]], s{{[0-9]+}}, 3
; GCN: s_lshr_b64 s{{\[}}[[RL:[0-9]+]]:{{[0-9]+}}], s{{\[}}[[SL]]:[[SH]]], [[SEL]] ; GCN: s_lshr_b64 s[[[RL:[0-9]+]]:{{[0-9]+}}], s[[[SL]]:[[SH]]], [[SEL]]
; GCN-DAG: v_mov_b32_e32 v[[VRL:[0-9]+]], s[[RL]] ; GCN-DAG: v_mov_b32_e32 v[[VRL:[0-9]+]], s[[RL]]
; GCN: store_byte v[{{[0-9:]+}}], v[[VRL]] ; GCN: store_byte v[{{[0-9:]+}}], v[[VRL]]
define amdgpu_kernel void @byte8_extelt(i8 addrspace(1)* %out, i32 %sel) { define amdgpu_kernel void @byte8_extelt(i8 addrspace(1)* %out, i32 %sel) {
entry: entry:
%ext = extractelement <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i32 %sel %ext = extractelement <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i32 %sel
store i8 %ext, i8 addrspace(1)* %out store i8 %ext, i8 addrspace(1)* %out
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_extractelement_v4f16_2(half addrspace(1)* %out, <4 x half> addrspace(1)* %in) #0 {
%vec = load <4 x half>, <4 x half> addrspace(1)* %in.gep %vec = load <4 x half>, <4 x half> addrspace(1)* %in.gep
%vec.extract = extractelement <4 x half> %vec, i32 2 %vec.extract = extractelement <4 x half> %vec, i32 2
store half %vec.extract, half addrspace(1)* %out.gep store half %vec.extract, half addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_insertelement_v4f16_dynamic_vgpr: ; GCN-LABEL: {{^}}v_insertelement_v4f16_dynamic_vgpr:
; GCN-DAG: {{flat|global|buffer}}_load_dword [[IDX:v[0-9]+]], ; GCN-DAG: {{flat|global|buffer}}_load_dword [[IDX:v[0-9]+]],
; GCN-DAG: {{flat|global|buffer}}_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} ; GCN-DAG: {{flat|global|buffer}}_load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
; GCN-DAG: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 4, [[IDX]] ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 4, [[IDX]]
; GFX89: v_lshrrev_b64 v{{\[}}[[SHIFT_LO:[0-9]+]]:[[SHIFT_HI:[0-9]+]]{{\]}}, [[SCALED_IDX]], v{{\[}}[[LO]]:[[HI]]{{\]}} ; GFX89: v_lshrrev_b64 v[[[SHIFT_LO:[0-9]+]]:[[SHIFT_HI:[0-9]+]]], [[SCALED_IDX]], v[[[LO]]:[[HI]]]
; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[SHIFT_LO]] ; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[SHIFT_LO]]
; SI: v_lshr_b64 v{{\[}}[[SHIFT_LO:[0-9]+]]:[[SHIFT_HI:[0-9]+]]{{\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}}, [[SCALED_IDX]] ; SI: v_lshr_b64 v[[[SHIFT_LO:[0-9]+]]:[[SHIFT_HI:[0-9]+]]], v[[[LO]]:[[HI]]], [[SCALED_IDX]]
; SI: buffer_store_short v[[SHIFT_LO]] ; SI: buffer_store_short v[[SHIFT_LO]]
define amdgpu_kernel void @v_insertelement_v4f16_dynamic_vgpr(half addrspace(1)* %out, <4 x half> addrspace(1)* %in) #0 { define amdgpu_kernel void @v_insertelement_v4f16_dynamic_vgpr(half addrspace(1)* %out, <4 x half> addrspace(1)* %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(1)* %in, i64 %tid.ext
%out.gep = getelementptr inbounds half, half addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds half, half addrspace(1)* %out, i64 %tid.ext
%idx.val = load volatile i32, i32 addrspace(1)* undef %idx.val = load volatile i32, i32 addrspace(1)* undef
%vec = load <4 x half>, <4 x half> addrspace(1)* %in.gep %vec = load <4 x half>, <4 x half> addrspace(1)* %in.gep
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llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @extract_vector_elt_v3i16(i16 addrspace(1)* %out, <3 x i16> %foo) #0 {
ret void ret void
} }
; GCN-LABEL: {{^}}extract_vector_elt_v4i16: ; GCN-LABEL: {{^}}extract_vector_elt_v4i16:
; SI: s_load_dwordx2 ; SI: s_load_dwordx2
; SI: buffer_store_short ; SI: buffer_store_short
; SI: buffer_store_short ; SI: buffer_store_short
; GFX89-DAG: s_load_dwordx2 s{{\[}}[[LOAD0:[0-9]+]]:[[LOAD1:[0-9]+]]{{\]}}, s[0:1], 0x2c ; GFX89-DAG: s_load_dwordx2 s[[[LOAD0:[0-9]+]]:[[LOAD1:[0-9]+]]], s[0:1], 0x2c
; GFX89-DAG: v_mov_b32_e32 [[VLOAD0:v[0-9]+]], s[[LOAD0]] ; GFX89-DAG: v_mov_b32_e32 [[VLOAD0:v[0-9]+]], s[[LOAD0]]
; GFX89-DAG: buffer_store_short [[VLOAD0]], off ; GFX89-DAG: buffer_store_short [[VLOAD0]], off
; GFX89-DAG: v_mov_b32_e32 [[VLOAD1:v[0-9]+]], s[[LOAD1]] ; GFX89-DAG: v_mov_b32_e32 [[VLOAD1:v[0-9]+]], s[[LOAD1]]
; GFX89-DAG: buffer_store_short [[VLOAD1]], off ; GFX89-DAG: buffer_store_short [[VLOAD1]], off
define amdgpu_kernel void @extract_vector_elt_v4i16(i16 addrspace(1)* %out, <4 x i16> %foo) #0 { define amdgpu_kernel void @extract_vector_elt_v4i16(i16 addrspace(1)* %out, <4 x i16> %foo) #0 {
%p0 = extractelement <4 x i16> %foo, i32 0 %p0 = extractelement <4 x i16> %foo, i32 0
%p1 = extractelement <4 x i16> %foo, i32 2 %p1 = extractelement <4 x i16> %foo, i32 2
%out1 = getelementptr i16, i16 addrspace(1)* %out, i32 10 %out1 = getelementptr i16, i16 addrspace(1)* %out, i32 10
store volatile i16 %p1, i16 addrspace(1)* %out, align 2 store volatile i16 %p1, i16 addrspace(1)* %out, align 2
store volatile i16 %p0, i16 addrspace(1)* %out1, align 2 store volatile i16 %p0, i16 addrspace(1)* %out1, align 2
ret void ret void
} }
; GCN-LABEL: {{^}}dynamic_extract_vector_elt_v3i16: ; GCN-LABEL: {{^}}dynamic_extract_vector_elt_v3i16:
; SI: s_load_dword s ; SI: s_load_dword s
; SI: s_load_dwordx2 s ; SI: s_load_dwordx2 s
; SI: s_load_dwordx2 s ; SI: s_load_dwordx2 s
; GFX89-DAG: s_load_dwordx2 s{{\[}}[[LOAD0:[0-9]+]]:[[LOAD1:[0-9]+]]{{\]}}, s[0:1], 0x24 ; GFX89-DAG: s_load_dwordx2 s[[[LOAD0:[0-9]+]]:[[LOAD1:[0-9]+]]], s[0:1], 0x24
; GFX89-DAG: s_load_dwordx2 s{{\[}}[[LOAD0:[0-9]+]]:[[LOAD1:[0-9]+]]{{\]}}, s[0:1], 0x4c ; GFX89-DAG: s_load_dwordx2 s[[[LOAD0:[0-9]+]]:[[LOAD1:[0-9]+]]], s[0:1], 0x4c
; GFX89-DAG: s_load_dword s{{[0-9]+}}, s[0:1], 0x54 ; GFX89-DAG: s_load_dword s{{[0-9]+}}, s[0:1], 0x54
; GCN-NOT: {{buffer|flat|global}} ; GCN-NOT: {{buffer|flat|global}}
; SICI: buffer_store_short ; SICI: buffer_store_short
; SICI: buffer_store_short ; SICI: buffer_store_short
; SICI: buffer_store_short ; SICI: buffer_store_short
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llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll

Show First 20 Lines • Show All 177 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @dynamic_extract_vector_elt_v4i8(i8 addrspace(1)* %out, <4 x i8> addrspace(4)* %vec.ptr, [8 x i32], i32 %idx) #0 {
ret void ret void
} }
; GCN-LABEL: {{^}}dynamic_extract_vector_elt_v8i8: ; GCN-LABEL: {{^}}dynamic_extract_vector_elt_v8i8:
; VI: s_load_dword [[IDX:s[0-9]+]], s[4:5], 0x10 ; VI: s_load_dword [[IDX:s[0-9]+]], s[4:5], 0x10
; VI: s_load_dwordx2 [[VEC8:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 ; VI: s_load_dwordx2 [[VEC8:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x0
; VI: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3 ; VI: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3
; VI: s_lshr_b64 s{{\[}}[[EXTRACT_LO:[0-9]+]]:{{[0-9]+\]}}, [[VEC8]], [[SCALED_IDX]] ; VI: s_lshr_b64 s[[[EXTRACT_LO:[0-9]+]]:{{[0-9]+\]}}, [[VEC8]], [[SCALED_IDX]]
; VI: v_mov_b32_e32 [[V_EXTRACT:v[0-9]+]], s[[EXTRACT_LO]] ; VI: v_mov_b32_e32 [[V_EXTRACT:v[0-9]+]], s[[EXTRACT_LO]]
; VI: buffer_store_byte [[V_EXTRACT]] ; VI: buffer_store_byte [[V_EXTRACT]]
define amdgpu_kernel void @dynamic_extract_vector_elt_v8i8(i8 addrspace(1)* %out, <8 x i8> addrspace(4)* %vec.ptr, i32 %idx) #0 { define amdgpu_kernel void @dynamic_extract_vector_elt_v8i8(i8 addrspace(1)* %out, <8 x i8> addrspace(4)* %vec.ptr, i32 %idx) #0 {
%vec = load <8 x i8>, <8 x i8> addrspace(4)* %vec.ptr %vec = load <8 x i8>, <8 x i8> addrspace(4)* %vec.ptr
%p0 = extractelement <8 x i8> %vec, i32 %idx %p0 = extractelement <8 x i8> %vec, i32 %idx
%out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1 %out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1
store volatile i8 %p0, i8 addrspace(1)* %out store volatile i8 %p0, i8 addrspace(1)* %out
ret void ret void
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llvm/test/CodeGen/AMDGPU/fabs.f16.ll

Show All 33 Lines
; GCN: s_and_b32 s{{[0-9]+}}, [[VAL]], 0x7fff7fff ; GCN: s_and_b32 s{{[0-9]+}}, [[VAL]], 0x7fff7fff
define amdgpu_kernel void @s_fabs_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %in) { define amdgpu_kernel void @s_fabs_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %in) {
%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in) %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)
store <2 x half> %fabs, <2 x half> addrspace(1)* %out store <2 x half> %fabs, <2 x half> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}s_fabs_v4f16: ; GCN-LABEL: {{^}}s_fabs_v4f16:
; CI: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2 ; CI: s_load_dwordx2 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x2
; GFX89: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x8 ; GFX89: s_load_dwordx2 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x8
; GCN: s_mov_b32 [[MASK:s[0-9]+]], 0x7fff7fff ; GCN: s_mov_b32 [[MASK:s[0-9]+]], 0x7fff7fff
; GCN-DAG: s_and_b32 s{{[0-9]+}}, s[[LO]], [[MASK]] ; GCN-DAG: s_and_b32 s{{[0-9]+}}, s[[LO]], [[MASK]]
; GCN-DAG: s_and_b32 s{{[0-9]+}}, s[[HI]], [[MASK]] ; GCN-DAG: s_and_b32 s{{[0-9]+}}, s[[HI]], [[MASK]]
; GCN: {{flat|global}}_store_dwordx2 ; GCN: {{flat|global}}_store_dwordx2
define amdgpu_kernel void @s_fabs_v4f16(<4 x half> addrspace(1)* %out, <4 x half> %in) { define amdgpu_kernel void @s_fabs_v4f16(<4 x half> addrspace(1)* %out, <4 x half> %in) {
%fabs = call <4 x half> @llvm.fabs.v4f16(<4 x half> %in) %fabs = call <4 x half> @llvm.fabs.v4f16(<4 x half> %in)
store <4 x half> %fabs, <4 x half> addrspace(1)* %out store <4 x half> %fabs, <4 x half> addrspace(1)* %out
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llvm/test/CodeGen/AMDGPU/fabs.ll

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; GCN: s_and_b32 ; GCN: s_and_b32
define amdgpu_kernel void @fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { define amdgpu_kernel void @fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
%fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in) %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
store <4 x float> %fabs, <4 x float> addrspace(1)* %out store <4 x float> %fabs, <4 x float> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}fabs_fn_fold: ; GCN-LABEL: {{^}}fabs_fn_fold:
; SI: s_load_dwordx2 s{{\[}}[[ABS_VALUE:[0-9]+]]:[[MUL_VAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xb ; SI: s_load_dwordx2 s[[[ABS_VALUE:[0-9]+]]:[[MUL_VAL:[0-9]+]]], s[{{[0-9]+:[0-9]+}}], 0xb
; VI: s_load_dwordx2 s{{\[}}[[ABS_VALUE:[0-9]+]]:[[MUL_VAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x2c ; VI: s_load_dwordx2 s[[[ABS_VALUE:[0-9]+]]:[[MUL_VAL:[0-9]+]]], s[{{[0-9]+:[0-9]+}}], 0x2c
; GCN-NOT: and ; GCN-NOT: and
; GCN: v_mov_b32_e32 [[V_MUL_VI:v[0-9]+]], s[[MUL_VAL]] ; GCN: v_mov_b32_e32 [[V_MUL_VI:v[0-9]+]], s[[MUL_VAL]]
; GCN: v_mul_f32_e64 v{{[0-9]+}}, |s[[ABS_VALUE]]|, [[V_MUL_VI]] ; GCN: v_mul_f32_e64 v{{[0-9]+}}, |s[[ABS_VALUE]]|, [[V_MUL_VI]]
define amdgpu_kernel void @fabs_fn_fold(float addrspace(1)* %out, float %in0, float %in1) { define amdgpu_kernel void @fabs_fn_fold(float addrspace(1)* %out, float %in0, float %in1) {
%fabs = call float @fabs(float %in0) %fabs = call float @fabs(float %in0)
%fmul = fmul float %fabs, %in1 %fmul = fmul float %fabs, %in1
store float %fmul, float addrspace(1)* %out store float %fmul, float addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}fabs_fold: ; FUNC-LABEL: {{^}}fabs_fold:
; SI: s_load_dwordx2 s{{\[}}[[ABS_VALUE:[0-9]+]]:[[MUL_VAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xb ; SI: s_load_dwordx2 s[[[ABS_VALUE:[0-9]+]]:[[MUL_VAL:[0-9]+]]], s[{{[0-9]+:[0-9]+}}], 0xb
; VI: s_load_dwordx2 s{{\[}}[[ABS_VALUE:[0-9]+]]:[[MUL_VAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x2c ; VI: s_load_dwordx2 s[[[ABS_VALUE:[0-9]+]]:[[MUL_VAL:[0-9]+]]], s[{{[0-9]+:[0-9]+}}], 0x2c
; GCN-NOT: and ; GCN-NOT: and
; GCN: v_mov_b32_e32 [[V_MUL_VI:v[0-9]+]], s[[MUL_VAL]] ; GCN: v_mov_b32_e32 [[V_MUL_VI:v[0-9]+]], s[[MUL_VAL]]
; GCN: v_mul_f32_e64 v{{[0-9]+}}, |s[[ABS_VALUE]]|, [[V_MUL_VI]] ; GCN: v_mul_f32_e64 v{{[0-9]+}}, |s[[ABS_VALUE]]|, [[V_MUL_VI]]
define amdgpu_kernel void @fabs_fold(float addrspace(1)* %out, float %in0, float %in1) { define amdgpu_kernel void @fabs_fold(float addrspace(1)* %out, float %in0, float %in1) {
%fabs = call float @llvm.fabs.f32(float %in0) %fabs = call float @llvm.fabs.f32(float %in0)
%fmul = fmul float %fabs, %in1 %fmul = fmul float %fabs, %in1
store float %fmul, float addrspace(1)* %out store float %fmul, float addrspace(1)* %out
ret void ret void
Show All 18 Lines

llvm/test/CodeGen/AMDGPU/fcanonicalize.ll

Show First 20 Lines • Show All 278 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_test_canonicalize_fneg_var_f64(double addrspace(1)* %out) #1 {
%canonicalized = call double @llvm.canonicalize.f64(double %val.fneg) %canonicalized = call double @llvm.canonicalize.f64(double %val.fneg)
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_fold_canonicalize_p0_f64: ; GCN-LABEL: {{^}}test_fold_canonicalize_p0_f64:
; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], v[[LO]]{{$}} ; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], v[[LO]]{{$}}
; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_fold_canonicalize_p0_f64(double addrspace(1)* %out) #1 { define amdgpu_kernel void @test_fold_canonicalize_p0_f64(double addrspace(1)* %out) #1 {
%canonicalized = call double @llvm.canonicalize.f64(double 0.0) %canonicalized = call double @llvm.canonicalize.f64(double 0.0)
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_fold_canonicalize_n0_f64: ; GCN-LABEL: {{^}}test_fold_canonicalize_n0_f64:
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN-DAG: v_bfrev_b32_e32 v[[HI:[0-9]+]], 1{{$}} ; GCN-DAG: v_bfrev_b32_e32 v[[HI:[0-9]+]], 1{{$}}
; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_fold_canonicalize_n0_f64(double addrspace(1)* %out) #1 { define amdgpu_kernel void @test_fold_canonicalize_n0_f64(double addrspace(1)* %out) #1 {
%canonicalized = call double @llvm.canonicalize.f64(double -0.0) %canonicalized = call double @llvm.canonicalize.f64(double -0.0)
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_fold_canonicalize_p1_f64: ; GCN-LABEL: {{^}}test_fold_canonicalize_p1_f64:
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x3ff00000{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x3ff00000{{$}}
; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_fold_canonicalize_p1_f64(double addrspace(1)* %out) #1 { define amdgpu_kernel void @test_fold_canonicalize_p1_f64(double addrspace(1)* %out) #1 {
%canonicalized = call double @llvm.canonicalize.f64(double 1.0) %canonicalized = call double @llvm.canonicalize.f64(double 1.0)
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_fold_canonicalize_n1_f64: ; GCN-LABEL: {{^}}test_fold_canonicalize_n1_f64:
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0xbff00000{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0xbff00000{{$}}
; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_fold_canonicalize_n1_f64(double addrspace(1)* %out) #1 { define amdgpu_kernel void @test_fold_canonicalize_n1_f64(double addrspace(1)* %out) #1 {
%canonicalized = call double @llvm.canonicalize.f64(double -1.0) %canonicalized = call double @llvm.canonicalize.f64(double -1.0)
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_fold_canonicalize_literal_f64: ; GCN-LABEL: {{^}}test_fold_canonicalize_literal_f64:
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x40300000{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x40300000{{$}}
; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_fold_canonicalize_literal_f64(double addrspace(1)* %out) #1 { define amdgpu_kernel void @test_fold_canonicalize_literal_f64(double addrspace(1)* %out) #1 {
%canonicalized = call double @llvm.canonicalize.f64(double 16.0) %canonicalized = call double @llvm.canonicalize.f64(double 16.0)
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_no_denormals_fold_canonicalize_denormal0_f64: ; GCN-LABEL: {{^}}test_no_denormals_fold_canonicalize_denormal0_f64:
; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], v[[LO]]{{$}} ; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], v[[LO]]{{$}}
; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal0_f64(double addrspace(1)* %out) #2 { define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal0_f64(double addrspace(1)* %out) #2 {
%canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 4503599627370495 to double)) %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 4503599627370495 to double))
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_denormals_fold_canonicalize_denormal0_f64: ; GCN-LABEL: {{^}}test_denormals_fold_canonicalize_denormal0_f64:
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], -1{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], -1{{$}}
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0xfffff{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0xfffff{{$}}
; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal0_f64(double addrspace(1)* %out) #3 { define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal0_f64(double addrspace(1)* %out) #3 {
%canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 4503599627370495 to double)) %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 4503599627370495 to double))
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_no_denormals_fold_canonicalize_denormal1_f64: ; GCN-LABEL: {{^}}test_no_denormals_fold_canonicalize_denormal1_f64:
; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], v[[LO]]{{$}} ; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], v[[LO]]{{$}}
; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal1_f64(double addrspace(1)* %out) #2 { define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal1_f64(double addrspace(1)* %out) #2 {
%canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 9227875636482146303 to double)) %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 9227875636482146303 to double))
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_denormals_fold_canonicalize_denormal1_f64: ; GCN-LABEL: {{^}}test_denormals_fold_canonicalize_denormal1_f64:
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], -1{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], -1{{$}}
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x800fffff{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x800fffff{{$}}
; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal1_f64(double addrspace(1)* %out) #3 { define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal1_f64(double addrspace(1)* %out) #3 {
%canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 9227875636482146303 to double)) %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 9227875636482146303 to double))
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_f64: ; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_f64:
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}}
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_fold_canonicalize_qnan_f64(double addrspace(1)* %out) #1 { define amdgpu_kernel void @test_fold_canonicalize_qnan_f64(double addrspace(1)* %out) #1 {
%canonicalized = call double @llvm.canonicalize.f64(double 0x7FF8000000000000) %canonicalized = call double @llvm.canonicalize.f64(double 0x7FF8000000000000)
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_value_neg1_f64: ; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_value_neg1_f64:
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}}
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg1_f64(double addrspace(1)* %out) #1 { define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg1_f64(double addrspace(1)* %out) #1 {
%canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 -1 to double)) %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 -1 to double))
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_value_neg2_f64: ; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_value_neg2_f64:
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}}
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg2_f64(double addrspace(1)* %out) #1 { define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg2_f64(double addrspace(1)* %out) #1 {
%canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 -2 to double)) %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 -2 to double))
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_fold_canonicalize_snan0_value_f64: ; GCN-LABEL: {{^}}test_fold_canonicalize_snan0_value_f64:
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}}
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_fold_canonicalize_snan0_value_f64(double addrspace(1)* %out) #1 { define amdgpu_kernel void @test_fold_canonicalize_snan0_value_f64(double addrspace(1)* %out) #1 {
%canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 9218868437227405313 to double)) %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 9218868437227405313 to double))
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_fold_canonicalize_snan1_value_f64: ; GCN-LABEL: {{^}}test_fold_canonicalize_snan1_value_f64:
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}}
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_fold_canonicalize_snan1_value_f64(double addrspace(1)* %out) #1 { define amdgpu_kernel void @test_fold_canonicalize_snan1_value_f64(double addrspace(1)* %out) #1 {
%canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 9223372036854775807 to double)) %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 9223372036854775807 to double))
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_fold_canonicalize_snan2_value_f64: ; GCN-LABEL: {{^}}test_fold_canonicalize_snan2_value_f64:
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}}
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_fold_canonicalize_snan2_value_f64(double addrspace(1)* %out) #1 { define amdgpu_kernel void @test_fold_canonicalize_snan2_value_f64(double addrspace(1)* %out) #1 {
%canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 18442240474082181121 to double)) %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 18442240474082181121 to double))
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_fold_canonicalize_snan3_value_f64: ; GCN-LABEL: {{^}}test_fold_canonicalize_snan3_value_f64:
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}}
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_fold_canonicalize_snan3_value_f64(double addrspace(1)* %out) #1 { define amdgpu_kernel void @test_fold_canonicalize_snan3_value_f64(double addrspace(1)* %out) #1 {
%canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 18446744073709551615 to double)) %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 18446744073709551615 to double))
store double %canonicalized, double addrspace(1)* %out store double %canonicalized, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_canonicalize_value_f64_flush: ; GCN-LABEL: {{^}}test_canonicalize_value_f64_flush:
; GFX678: v_mul_f64 v[{{[0-9:]+}}], 1.0, v[{{[0-9:]+}}] ; GFX678: v_mul_f64 v[{{[0-9:]+}}], 1.0, v[{{[0-9:]+}}]
▲ Show 20 Lines • Show All 217 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/fcmp.f16.ll

Show First 20 Lines • Show All 608 Lines • ▼ Show 20 Lines
; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] ; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]] ; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]]
; SI-DAG: v_cmp_nlt_f32_e32 vcc, v[[A_F32_1]], v[[B_F32_1]] ; SI-DAG: v_cmp_nlt_f32_e32 vcc, v[[A_F32_1]], v[[B_F32_1]]
; VI-DAG: v_cmp_nlt_f16_e32 vcc, v[[B_V2_F16]], v[[A_V2_F16]] ; VI-DAG: v_cmp_nlt_f16_e32 vcc, v[[B_V2_F16]], v[[A_V2_F16]]
; GCN: v_cndmask_b32_e64 v[[R_I32_0:[0-9]+]] ; GCN: v_cndmask_b32_e64 v[[R_I32_0:[0-9]+]]
; VI: v_cmp_nlt_f16_e32 vcc, v[[B_F16_1]], v[[A_F16_1]] ; VI: v_cmp_nlt_f16_e32 vcc, v[[B_F16_1]], v[[A_F16_1]]
; GCN: v_cndmask_b32_e64 v[[R_I32_1:[0-9]+]] ; GCN: v_cndmask_b32_e64 v[[R_I32_1:[0-9]+]]
; GCN: buffer_store_dwordx2 v{{\[}}[[R_I32_0]]:[[R_I32_1]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[R_I32_0]]:[[R_I32_1]]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @fcmp_v2f16_nlt( define amdgpu_kernel void @fcmp_v2f16_nlt(
<2 x i32> addrspace(1)* %r, <2 x i32> addrspace(1)* %r,
<2 x half> addrspace(1)* %a, <2 x half> addrspace(1)* %a,
<2 x half> addrspace(1)* %b) { <2 x half> addrspace(1)* %b) {
entry: entry:
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
%b.val = load <2 x half>, <2 x half> addrspace(1)* %b %b.val = load <2 x half>, <2 x half> addrspace(1)* %b
Show All 10 Lines

llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Linesentry:
%sign = load float, float addrspace(1)* %arg_sign_gep %sign = load float, float addrspace(1)* %arg_sign_gep
%out = call float @llvm.copysign.f32(float %mag.ext, float %sign) %out = call float @llvm.copysign.f32(float %mag.ext, float %sign)
store float %out, float addrspace(1)* %arg_out store float %out, float addrspace(1)* %arg_out
ret void ret void
} }
; GCN-LABEL: {{^}}test_copysign_out_f64_mag_f16_sign_f64: ; GCN-LABEL: {{^}}test_copysign_out_f64_mag_f16_sign_f64:
; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]] ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
; GCN-DAG: {{buffer|flat|global}}_load_dwordx2 v{{\[}}[[SIGN_LO:[0-9]+]]:[[SIGN_HI:[0-9]+]]{{\]}} ; GCN-DAG: {{buffer|flat|global}}_load_dwordx2 v[[[SIGN_LO:[0-9]+]]:[[SIGN_HI:[0-9]+]]]
; GCN-DAG: s_brev_b32 s[[CONST:[0-9]+]], -2 ; GCN-DAG: s_brev_b32 s[[CONST:[0-9]+]], -2
; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]] ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
; GCN-DAG: v_cvt_f64_f32_e32 v{{\[}}[[MAG_EXT_LO:[0-9]+]]:[[MAG_EXT_HI:[0-9]+]]{{\]}}, v[[MAG_EXT]] ; GCN-DAG: v_cvt_f64_f32_e32 v[[[MAG_EXT_LO:[0-9]+]]:[[MAG_EXT_HI:[0-9]+]]], v[[MAG_EXT]]
; GCN: v_bfi_b32 v[[OUT_HI:[0-9]+]], s[[CONST]], v[[MAG_EXT_HI]], v[[SIGN_HI]] ; GCN: v_bfi_b32 v[[OUT_HI:[0-9]+]], s[[CONST]], v[[MAG_EXT_HI]], v[[SIGN_HI]]
; GCN: buffer_store_dwordx2 v{{\[}}[[MAG_EXT_LO]]:[[OUT_HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[MAG_EXT_LO]]:[[OUT_HI]]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @test_copysign_out_f64_mag_f16_sign_f64( define amdgpu_kernel void @test_copysign_out_f64_mag_f16_sign_f64(
double addrspace(1)* %arg_out, double addrspace(1)* %arg_out,
half addrspace(1)* %arg_mag, half addrspace(1)* %arg_mag,
double addrspace(1)* %arg_sign) { double addrspace(1)* %arg_sign) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%arg_mag_gep = getelementptr half, half addrspace(1)* %arg_mag, i32 %tid %arg_mag_gep = getelementptr half, half addrspace(1)* %arg_mag, i32 %tid
Show All 28 Linesentry:
%sign = load half, half addrspace(1)* %arg_sign_gep %sign = load half, half addrspace(1)* %arg_sign_gep
%sign.ext = fpext half %sign to float %sign.ext = fpext half %sign to float
%out = call float @llvm.copysign.f32(float %mag, float %sign.ext) %out = call float @llvm.copysign.f32(float %mag, float %sign.ext)
store float %out, float addrspace(1)* %arg_out store float %out, float addrspace(1)* %arg_out
ret void ret void
} }
; GCN-LABEL: {{^}}test_copysign_out_f64_mag_f64_sign_f16: ; GCN-LABEL: {{^}}test_copysign_out_f64_mag_f64_sign_f16:
; GCN-DAG: {{buffer|flat|global}}_load_dwordx2 v{{\[}}[[MAG_LO:[0-9]+]]:[[MAG_HI:[0-9]+]]{{\]}} ; GCN-DAG: {{buffer|flat|global}}_load_dwordx2 v[[[MAG_LO:[0-9]+]]:[[MAG_HI:[0-9]+]]]
; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[SIGN:[0-9]+]] ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[SIGN:[0-9]+]]
; GCN-DAG: s_brev_b32 s[[CONST:[0-9]+]], -2 ; GCN-DAG: s_brev_b32 s[[CONST:[0-9]+]], -2
; SI-DAG: v_cvt_f32_f16_e32 v[[SIGN_F32:[0-9]+]], v[[SIGN]] ; SI-DAG: v_cvt_f32_f16_e32 v[[SIGN_F32:[0-9]+]], v[[SIGN]]
; SI: v_bfi_b32 v[[OUT_HI:[0-9]+]], s[[CONST]], v[[MAG_HI]], v[[SIGN_F32]] ; SI: v_bfi_b32 v[[OUT_HI:[0-9]+]], s[[CONST]], v[[MAG_HI]], v[[SIGN_F32]]
; GFX89-DAG: v_lshlrev_b32_e32 v[[SIGN_SHIFT:[0-9]+]], 16, v[[SIGN]] ; GFX89-DAG: v_lshlrev_b32_e32 v[[SIGN_SHIFT:[0-9]+]], 16, v[[SIGN]]
; GFX89: v_bfi_b32 v[[OUT_HI:[0-9]+]], s[[CONST]], v[[MAG_HI]], v[[SIGN_SHIFT]] ; GFX89: v_bfi_b32 v[[OUT_HI:[0-9]+]], s[[CONST]], v[[MAG_HI]], v[[SIGN_SHIFT]]
; GCN: buffer_store_dwordx2 v{{\[}}[[MAG_LO]]:[[OUT_HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[MAG_LO]]:[[OUT_HI]]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @test_copysign_out_f64_mag_f64_sign_f16( define amdgpu_kernel void @test_copysign_out_f64_mag_f64_sign_f16(
double addrspace(1)* %arg_out, double addrspace(1)* %arg_out,
double addrspace(1)* %arg_mag, double addrspace(1)* %arg_mag,
half addrspace(1)* %arg_sign) { half addrspace(1)* %arg_sign) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%arg_mag_gep = getelementptr double, double addrspace(1)* %arg_mag, i32 %tid %arg_mag_gep = getelementptr double, double addrspace(1)* %arg_mag, i32 %tid
Show All 31 Linesentry:
%sign.trunc = fptrunc float %sign to half %sign.trunc = fptrunc float %sign to half
%out = call half @llvm.copysign.f16(half %mag, half %sign.trunc) %out = call half @llvm.copysign.f16(half %mag, half %sign.trunc)
store half %out, half addrspace(1)* %arg_out store half %out, half addrspace(1)* %arg_out
ret void ret void
} }
; GCN-LABEL: {{^}}test_copysign_out_f16_mag_f16_sign_f64: ; GCN-LABEL: {{^}}test_copysign_out_f16_mag_f16_sign_f64:
; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]] ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
; GCN-DAG: {{buffer|flat|global}}_load_dwordx2 v{{\[}}[[SIGN_LO:[0-9]+]]:[[SIGN_HI:[0-9]+]]{{\]}} ; GCN-DAG: {{buffer|flat|global}}_load_dwordx2 v[[[SIGN_LO:[0-9]+]]:[[SIGN_HI:[0-9]+]]]
; SI-DAG: s_brev_b32 s[[CONST:[0-9]+]], -2 ; SI-DAG: s_brev_b32 s[[CONST:[0-9]+]], -2
; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]] ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
; SI: v_bfi_b32 v[[OUT_F32:[0-9]+]], s[[CONST]], v[[MAG_F32]], v[[SIGN_HI]] ; SI: v_bfi_b32 v[[OUT_F32:[0-9]+]], s[[CONST]], v[[MAG_F32]], v[[SIGN_HI]]
; SI: v_cvt_f16_f32_e32 v[[OUT:[0-9]+]], v[[OUT_F32]] ; SI: v_cvt_f16_f32_e32 v[[OUT:[0-9]+]], v[[OUT_F32]]
; GFX89-DAG: s_movk_i32 s[[CONST:[0-9]+]], 0x7fff ; GFX89-DAG: s_movk_i32 s[[CONST:[0-9]+]], 0x7fff
; GFX89-DAG: v_lshrrev_b32_e32 v[[SIGN_SHIFT:[0-9]+]], 16, v[[SIGN_HI]] ; GFX89-DAG: v_lshrrev_b32_e32 v[[SIGN_SHIFT:[0-9]+]], 16, v[[SIGN_HI]]
; GFX89: v_bfi_b32 v[[OUT:[0-9]+]], s[[CONST]], v[[MAG]], v[[SIGN_SHIFT]] ; GFX89: v_bfi_b32 v[[OUT:[0-9]+]], s[[CONST]], v[[MAG]], v[[SIGN_SHIFT]]
; GCN: buffer_store_short v[[OUT]] ; GCN: buffer_store_short v[[OUT]]
▲ Show 20 Lines • Show All 108 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
declare float @llvm.copysign.f32(float, float) nounwind readnone declare float @llvm.copysign.f32(float, float) nounwind readnone
declare <2 x float> @llvm.copysign.v2f32(<2 x float>, <2 x float>) nounwind readnone declare <2 x float> @llvm.copysign.v2f32(<2 x float>, <2 x float>) nounwind readnone
declare <4 x float> @llvm.copysign.v4f32(<4 x float>, <4 x float>) nounwind readnone declare <4 x float> @llvm.copysign.v4f32(<4 x float>, <4 x float>) nounwind readnone
; Try to identify arg based on higher address. ; Try to identify arg based on higher address.
; FUNC-LABEL: {{^}}test_copysign_f32: ; FUNC-LABEL: {{^}}test_copysign_f32:
; SI: s_load_dwordx2 s{{\[}}[[SMAG:[0-9]+]]:[[SSIGN:[0-9]+]]{{\]}}, {{.*}} 0xb ; SI: s_load_dwordx2 s[[[SMAG:[0-9]+]]:[[SSIGN:[0-9]+]]], {{.*}} 0xb
; VI: s_load_dwordx2 s{{\[}}[[SMAG:[0-9]+]]:[[SSIGN:[0-9]+]]{{\]}}, {{.*}} 0x2c ; VI: s_load_dwordx2 s[[[SMAG:[0-9]+]]:[[SSIGN:[0-9]+]]], {{.*}} 0x2c
; GCN-DAG: v_mov_b32_e32 [[VSIGN:v[0-9]+]], s[[SSIGN]] ; GCN-DAG: v_mov_b32_e32 [[VSIGN:v[0-9]+]], s[[SSIGN]]
; GCN-DAG: v_mov_b32_e32 [[VMAG:v[0-9]+]], s[[SMAG]] ; GCN-DAG: v_mov_b32_e32 [[VMAG:v[0-9]+]], s[[SMAG]]
; GCN-DAG: s_brev_b32 [[SCONST:s[0-9]+]], -2 ; GCN-DAG: s_brev_b32 [[SCONST:s[0-9]+]], -2
; GCN: v_bfi_b32 [[RESULT:v[0-9]+]], [[SCONST]], [[VMAG]], [[VSIGN]] ; GCN: v_bfi_b32 [[RESULT:v[0-9]+]], [[SCONST]], [[VMAG]], [[VSIGN]]
; GCN: buffer_store_dword [[RESULT]], ; GCN: buffer_store_dword [[RESULT]],
; GCN: s_endpgm ; GCN: s_endpgm
Show All 31 Lines

llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
declare double @llvm.copysign.f64(double, double) nounwind readnone declare double @llvm.copysign.f64(double, double) nounwind readnone
declare <2 x double> @llvm.copysign.v2f64(<2 x double>, <2 x double>) nounwind readnone declare <2 x double> @llvm.copysign.v2f64(<2 x double>, <2 x double>) nounwind readnone
declare <4 x double> @llvm.copysign.v4f64(<4 x double>, <4 x double>) nounwind readnone declare <4 x double> @llvm.copysign.v4f64(<4 x double>, <4 x double>) nounwind readnone
; FUNC-LABEL: {{^}}test_copysign_f64: ; FUNC-LABEL: {{^}}test_copysign_f64:
; SI-DAG: s_load_dwordx2 s{{\[}}[[SMAG_LO:[0-9]+]]:[[SMAG_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x13 ; SI-DAG: s_load_dwordx2 s[[[SMAG_LO:[0-9]+]]:[[SMAG_HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
; SI-DAG: s_load_dwordx2 s{{\[}}[[SSIGN_LO:[0-9]+]]:[[SSIGN_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x1d ; SI-DAG: s_load_dwordx2 s[[[SSIGN_LO:[0-9]+]]:[[SSIGN_HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x1d
; VI-DAG: s_load_dwordx2 s{{\[}}[[SMAG_LO:[0-9]+]]:[[SMAG_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x4c ; VI-DAG: s_load_dwordx2 s[[[SMAG_LO:[0-9]+]]:[[SMAG_HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c
; VI-DAG: s_load_dwordx2 s{{\[}}[[SSIGN_LO:[0-9]+]]:[[SSIGN_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x74 ; VI-DAG: s_load_dwordx2 s[[[SSIGN_LO:[0-9]+]]:[[SSIGN_HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x74
; GCN-DAG: v_mov_b32_e32 v[[VSIGN_HI:[0-9]+]], s[[SSIGN_HI]] ; GCN-DAG: v_mov_b32_e32 v[[VSIGN_HI:[0-9]+]], s[[SSIGN_HI]]
; GCN-DAG: v_mov_b32_e32 v[[VMAG_HI:[0-9]+]], s[[SMAG_HI]] ; GCN-DAG: v_mov_b32_e32 v[[VMAG_HI:[0-9]+]], s[[SMAG_HI]]
; GCN-DAG: s_brev_b32 [[SCONST:s[0-9]+]], -2 ; GCN-DAG: s_brev_b32 [[SCONST:s[0-9]+]], -2
; GCN-DAG: v_bfi_b32 v[[VRESULT_HI:[0-9]+]], [[SCONST]], v[[VMAG_HI]], v[[VSIGN_HI]] ; GCN-DAG: v_bfi_b32 v[[VRESULT_HI:[0-9]+]], [[SCONST]], v[[VMAG_HI]], v[[VSIGN_HI]]
; GCN-DAG: v_mov_b32_e32 v[[VMAG_LO:[0-9]+]], s[[SMAG_LO]] ; GCN-DAG: v_mov_b32_e32 v[[VMAG_LO:[0-9]+]], s[[SMAG_LO]]
; GCN: buffer_store_dwordx2 v{{\[}}[[VMAG_LO]]:[[VRESULT_HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[VMAG_LO]]:[[VRESULT_HI]]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @test_copysign_f64(double addrspace(1)* %out, [8 x i32], double %mag, [8 x i32], double %sign) nounwind { define amdgpu_kernel void @test_copysign_f64(double addrspace(1)* %out, [8 x i32], double %mag, [8 x i32], double %sign) nounwind {
%result = call double @llvm.copysign.f64(double %mag, double %sign) %result = call double @llvm.copysign.f64(double %mag, double %sign)
store double %result, double addrspace(1)* %out, align 8 store double %result, double addrspace(1)* %out, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}test_copysign_f64_f32: ; FUNC-LABEL: {{^}}test_copysign_f64_f32:
; SI-DAG: s_load_dwordx2 s{{\[}}[[SMAG_LO:[0-9]+]]:[[SMAG_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x13 ; SI-DAG: s_load_dwordx2 s[[[SMAG_LO:[0-9]+]]:[[SMAG_HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
; VI-DAG: s_load_dwordx2 s{{\[}}[[SMAG_LO:[0-9]+]]:[[SMAG_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x4c ; VI-DAG: s_load_dwordx2 s[[[SMAG_LO:[0-9]+]]:[[SMAG_HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c
; GCN-DAG: s_load_dword s[[SSIGN:[0-9]+]], s{{\[[0-9]+:[0-9]+\]}} ; GCN-DAG: s_load_dword s[[SSIGN:[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}
; GCN-DAG: s_brev_b32 [[SCONST:s[0-9]+]], -2{{$}} ; GCN-DAG: s_brev_b32 [[SCONST:s[0-9]+]], -2{{$}}
; GCN-DAG: v_mov_b32_e32 v[[VMAG_HI:[0-9]+]], s[[SMAG_HI]] ; GCN-DAG: v_mov_b32_e32 v[[VMAG_HI:[0-9]+]], s[[SMAG_HI]]
; GCN-DAG: v_mov_b32_e32 v[[VSIGN:[0-9]+]], s[[SSIGN]] ; GCN-DAG: v_mov_b32_e32 v[[VSIGN:[0-9]+]], s[[SSIGN]]
; GCN-DAG: v_bfi_b32 v[[VRESULT_HI:[0-9]+]], [[SCONST]], v[[VMAG_HI]], v[[VSIGN]] ; GCN-DAG: v_bfi_b32 v[[VRESULT_HI:[0-9]+]], [[SCONST]], v[[VMAG_HI]], v[[VSIGN]]
; GCN-DAG: v_mov_b32_e32 v[[VMAG_LO:[0-9]+]], s[[SMAG_LO]] ; GCN-DAG: v_mov_b32_e32 v[[VMAG_LO:[0-9]+]], s[[SMAG_LO]]
; GCN: buffer_store_dwordx2 v{{\[}}[[VMAG_LO]]:[[VRESULT_HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[VMAG_LO]]:[[VRESULT_HI]]]
define amdgpu_kernel void @test_copysign_f64_f32(double addrspace(1)* %out, [8 x i32], double %mag, float %sign) nounwind { define amdgpu_kernel void @test_copysign_f64_f32(double addrspace(1)* %out, [8 x i32], double %mag, float %sign) nounwind {
%c = fpext float %sign to double %c = fpext float %sign to double
%result = call double @llvm.copysign.f64(double %mag, double %c) %result = call double @llvm.copysign.f64(double %mag, double %c)
store double %result, double addrspace(1)* %out, align 8 store double %result, double addrspace(1)* %out, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}test_copysign_v2f64: ; FUNC-LABEL: {{^}}test_copysign_v2f64:
Show All 14 Lines

llvm/test/CodeGen/AMDGPU/fdiv.f64.ll

Show First 20 Lines • Show All 131 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @div_fast_2_x_pat_f64(double addrspace(1)* %out) #1 {
%rcp = fdiv fast double %x, 2.0 %rcp = fdiv fast double %x, 2.0
store double %rcp, double addrspace(1)* %out, align 4 store double %rcp, double addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}div_fast_k_x_pat_f64: ; GCN-LABEL: {{^}}div_fast_k_x_pat_f64:
; GCN-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0x9999999a ; GCN-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0x9999999a
; GCN-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0x3fb99999 ; GCN-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0x3fb99999
; GCN: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}} ; GCN: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s[[[K_LO]]:[[K_HI]]]
; GCN: buffer_store_dwordx2 [[MUL]] ; GCN: buffer_store_dwordx2 [[MUL]]
define amdgpu_kernel void @div_fast_k_x_pat_f64(double addrspace(1)* %out) #1 { define amdgpu_kernel void @div_fast_k_x_pat_f64(double addrspace(1)* %out) #1 {
%x = load double, double addrspace(1)* undef %x = load double, double addrspace(1)* undef
%rcp = fdiv fast double %x, 10.0 %rcp = fdiv fast double %x, 10.0
store double %rcp, double addrspace(1)* %out, align 4 store double %rcp, double addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}div_fast_neg_k_x_pat_f64: ; GCN-LABEL: {{^}}div_fast_neg_k_x_pat_f64:
; GCN-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0x9999999a ; GCN-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0x9999999a
; GCN-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0xbfb99999 ; GCN-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0xbfb99999
; GCN: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}} ; GCN: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s[[[K_LO]]:[[K_HI]]]
; GCN: buffer_store_dwordx2 [[MUL]] ; GCN: buffer_store_dwordx2 [[MUL]]
define amdgpu_kernel void @div_fast_neg_k_x_pat_f64(double addrspace(1)* %out) #1 { define amdgpu_kernel void @div_fast_neg_k_x_pat_f64(double addrspace(1)* %out) #1 {
%x = load double, double addrspace(1)* undef %x = load double, double addrspace(1)* undef
%rcp = fdiv fast double %x, -10.0 %rcp = fdiv fast double %x, -10.0
store double %rcp, double addrspace(1)* %out, align 4 store double %rcp, double addrspace(1)* %out, align 4
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind "unsafe-fp-math"="true" } attributes #1 = { nounwind "unsafe-fp-math"="true" }

llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @div_minus_1_by_minus_x_25ulp(float addrspace(1)* %arg) {
%load = load float, float addrspace(1)* %arg, align 4 %load = load float, float addrspace(1)* %arg, align 4
%neg = fsub float -0.000000e+00, %load %neg = fsub float -0.000000e+00, %load
%div = fdiv float -1.000000e+00, %neg, !fpmath !0 %div = fdiv float -1.000000e+00, %neg, !fpmath !0
store float %div, float addrspace(1)* %arg, align 4 store float %div, float addrspace(1)* %arg, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}div_v4_1_by_x_25ulp: ; GCN-LABEL: {{^}}div_v4_1_by_x_25ulp:
; GCN-DAG: s_load_dwordx4 s{{\[}}[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]], s[{{[0-9:]+}}], 0x0{{$}} ; GCN-DAG: s_load_dwordx4 s[[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]], s[{{[0-9:]+}}], 0x0{{$}}
; GCN-DENORM-DAG: v_mov_b32_e32 [[L:v[0-9]+]], 0x6f800000 ; GCN-DENORM-DAG: v_mov_b32_e32 [[L:v[0-9]+]], 0x6f800000
; GCN-DENORM-DAG: v_mov_b32_e32 [[S:v[0-9]+]], 0x2f800000 ; GCN-DENORM-DAG: v_mov_b32_e32 [[S:v[0-9]+]], 0x2f800000
; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]] ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]]
; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc
; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]] ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]]
; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc
; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]] ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]]
; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc
Show All 11 Lines
; GCN-DENORM-DAG: v_mul_f32_e32 ; GCN-DENORM-DAG: v_mul_f32_e32
; GCN-DENORM-DAG: v_mul_f32_e32 ; GCN-DENORM-DAG: v_mul_f32_e32
; GCN-DENORM-DAG: v_mul_f32_e32 ; GCN-DENORM-DAG: v_mul_f32_e32
; GCN-FLUSH: v_rcp_f32_e32 v[[OUT0:[0-9]+]], s[[VAL0]] ; GCN-FLUSH: v_rcp_f32_e32 v[[OUT0:[0-9]+]], s[[VAL0]]
; GCN-FLUSH: v_rcp_f32_e32 ; GCN-FLUSH: v_rcp_f32_e32
; GCN-FLUSH: v_rcp_f32_e32 ; GCN-FLUSH: v_rcp_f32_e32
; GCN-FLUSH: v_rcp_f32_e32 v[[OUT3:[0-9]+]], s[[VAL3]] ; GCN-FLUSH: v_rcp_f32_e32 v[[OUT3:[0-9]+]], s[[VAL3]]
; GCN-FLUSH: global_store_dwordx4 v{{[0-9]+}}, v{{\[}}[[OUT0]]:[[OUT3]]], s{{\[[0-9]+:[0-9]+\]}} ; GCN-FLUSH: global_store_dwordx4 v{{[0-9]+}}, v[[[OUT0]]:[[OUT3]]], s{{\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @div_v4_1_by_x_25ulp(<4 x float> addrspace(1)* %arg) { define amdgpu_kernel void @div_v4_1_by_x_25ulp(<4 x float> addrspace(1)* %arg) {
%load = load <4 x float>, <4 x float> addrspace(1)* %arg, align 16 %load = load <4 x float>, <4 x float> addrspace(1)* %arg, align 16
%div = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %load, !fpmath !0 %div = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %load, !fpmath !0
store <4 x float> %div, <4 x float> addrspace(1)* %arg, align 16 store <4 x float> %div, <4 x float> addrspace(1)* %arg, align 16
ret void ret void
} }
; GCN-LABEL: {{^}}div_v4_minus_1_by_x_25ulp: ; GCN-LABEL: {{^}}div_v4_minus_1_by_x_25ulp:
; GCN-DAG: s_load_dwordx4 s{{\[}}[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]], s[{{[0-9:]+}}], 0x0{{$}} ; GCN-DAG: s_load_dwordx4 s[[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]], s[{{[0-9:]+}}], 0x0{{$}}
; GCN-DENORM-DAG: v_mov_b32_e32 [[L:v[0-9]+]], 0x6f800000 ; GCN-DENORM-DAG: v_mov_b32_e32 [[L:v[0-9]+]], 0x6f800000
; GCN-DENORM-DAG: v_mov_b32_e32 [[S:v[0-9]+]], 0x2f800000 ; GCN-DENORM-DAG: v_mov_b32_e32 [[S:v[0-9]+]], 0x2f800000
; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]] ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]]
; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc
; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]] ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]]
; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc
; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]] ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]]
; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc
Show All 19 Lines
define amdgpu_kernel void @div_v4_minus_1_by_x_25ulp(<4 x float> addrspace(1)* %arg) { define amdgpu_kernel void @div_v4_minus_1_by_x_25ulp(<4 x float> addrspace(1)* %arg) {
%load = load <4 x float>, <4 x float> addrspace(1)* %arg, align 16 %load = load <4 x float>, <4 x float> addrspace(1)* %arg, align 16
%div = fdiv <4 x float> <float -1.000000e+00, float -1.000000e+00, float -1.000000e+00, float -1.000000e+00>, %load, !fpmath !0 %div = fdiv <4 x float> <float -1.000000e+00, float -1.000000e+00, float -1.000000e+00, float -1.000000e+00>, %load, !fpmath !0
store <4 x float> %div, <4 x float> addrspace(1)* %arg, align 16 store <4 x float> %div, <4 x float> addrspace(1)* %arg, align 16
ret void ret void
} }
; GCN-LABEL: {{^}}div_v4_1_by_minus_x_25ulp: ; GCN-LABEL: {{^}}div_v4_1_by_minus_x_25ulp:
; GCN-DAG: s_load_dwordx4 s{{\[}}[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]], s[{{[0-9:]+}}], 0x0{{$}} ; GCN-DAG: s_load_dwordx4 s[[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]], s[{{[0-9:]+}}], 0x0{{$}}
; GCN-DENORM-DAG: v_mov_b32_e32 [[L:v[0-9]+]], 0x6f800000 ; GCN-DENORM-DAG: v_mov_b32_e32 [[L:v[0-9]+]], 0x6f800000
; GCN-DENORM-DAG: v_mov_b32_e32 [[S:v[0-9]+]], 0x2f800000 ; GCN-DENORM-DAG: v_mov_b32_e32 [[S:v[0-9]+]], 0x2f800000
; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]] ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]]
; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc
; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]] ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]]
; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc
; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]] ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]]
; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc
Show All 11 Lines
; GCN-DENORM-DAG: v_mul_f32_e32 ; GCN-DENORM-DAG: v_mul_f32_e32
; GCN-DENORM-DAG: v_mul_f32_e32 ; GCN-DENORM-DAG: v_mul_f32_e32
; GCN-DENORM-DAG: v_mul_f32_e32 ; GCN-DENORM-DAG: v_mul_f32_e32
; GCN-FLUSH: v_rcp_f32_e64 v[[OUT0:[0-9]+]], -s[[VAL0]] ; GCN-FLUSH: v_rcp_f32_e64 v[[OUT0:[0-9]+]], -s[[VAL0]]
; GCN-FLUSH: v_rcp_f32_e64 ; GCN-FLUSH: v_rcp_f32_e64
; GCN-FLUSH: v_rcp_f32_e64 ; GCN-FLUSH: v_rcp_f32_e64
; GCN-FLUSH: v_rcp_f32_e64 v[[OUT3:[0-9]+]], -s[[VAL3]] ; GCN-FLUSH: v_rcp_f32_e64 v[[OUT3:[0-9]+]], -s[[VAL3]]
; GCN-FLUSH: global_store_dwordx4 v{{[0-9]+}}, v{{\[}}[[OUT0]]:[[OUT3]]], s{{\[[0-9]+:[0-9]+\]}} ; GCN-FLUSH: global_store_dwordx4 v{{[0-9]+}}, v[[[OUT0]]:[[OUT3]]], s{{\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @div_v4_1_by_minus_x_25ulp(<4 x float> addrspace(1)* %arg) { define amdgpu_kernel void @div_v4_1_by_minus_x_25ulp(<4 x float> addrspace(1)* %arg) {
%load = load <4 x float>, <4 x float> addrspace(1)* %arg, align 16 %load = load <4 x float>, <4 x float> addrspace(1)* %arg, align 16
%neg = fneg <4 x float> %load %neg = fneg <4 x float> %load
%div = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %neg, !fpmath !0 %div = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %neg, !fpmath !0
store <4 x float> %div, <4 x float> addrspace(1)* %arg, align 16 store <4 x float> %div, <4 x float> addrspace(1)* %arg, align 16
ret void ret void
} }
; GCN-LABEL: {{^}}div_v4_minus_1_by_minus_x_25ulp: ; GCN-LABEL: {{^}}div_v4_minus_1_by_minus_x_25ulp:
; GCN-DAG: s_load_dwordx4 s{{\[}}[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]], s[{{[0-9:]+}}], 0x0{{$}} ; GCN-DAG: s_load_dwordx4 s[[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]], s[{{[0-9:]+}}], 0x0{{$}}
; GCN-DENORM-DAG: v_mov_b32_e32 [[L:v[0-9]+]], 0x6f800000 ; GCN-DENORM-DAG: v_mov_b32_e32 [[L:v[0-9]+]], 0x6f800000
; GCN-DENORM-DAG: v_mov_b32_e32 [[S:v[0-9]+]], 0x2f800000 ; GCN-DENORM-DAG: v_mov_b32_e32 [[S:v[0-9]+]], 0x2f800000
; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]] ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]]
; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc
; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]] ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]]
; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc
; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]] ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]]
; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc
Show All 11 Lines
; GCN-DENORM-DAG: v_mul_f32_e32 ; GCN-DENORM-DAG: v_mul_f32_e32
; GCN-DENORM-DAG: v_mul_f32_e32 ; GCN-DENORM-DAG: v_mul_f32_e32
; GCN-DENORM-DAG: v_mul_f32_e32 ; GCN-DENORM-DAG: v_mul_f32_e32
; GCN-FLUSH: v_rcp_f32_e32 v[[OUT0:[0-9]+]], s[[VAL0]] ; GCN-FLUSH: v_rcp_f32_e32 v[[OUT0:[0-9]+]], s[[VAL0]]
; GCN-FLUSH: v_rcp_f32_e32 ; GCN-FLUSH: v_rcp_f32_e32
; GCN-FLUSH: v_rcp_f32_e32 ; GCN-FLUSH: v_rcp_f32_e32
; GCN-FLUSH: v_rcp_f32_e32 v[[OUT3:[0-9]+]], s[[VAL3]] ; GCN-FLUSH: v_rcp_f32_e32 v[[OUT3:[0-9]+]], s[[VAL3]]
; GCN-FLUSH: global_store_dwordx4 v{{[0-9]+}}, v{{\[}}[[OUT0]]:[[OUT3]]], s{{\[[0-9]+:[0-9]+\]}} ; GCN-FLUSH: global_store_dwordx4 v{{[0-9]+}}, v[[[OUT0]]:[[OUT3]]], s{{\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @div_v4_minus_1_by_minus_x_25ulp(<4 x float> addrspace(1)* %arg) { define amdgpu_kernel void @div_v4_minus_1_by_minus_x_25ulp(<4 x float> addrspace(1)* %arg) {
%load = load <4 x float>, <4 x float> addrspace(1)* %arg, align 16 %load = load <4 x float>, <4 x float> addrspace(1)* %arg, align 16
%neg = fneg <4 x float> %load %neg = fneg <4 x float> %load
%div = fdiv <4 x float> <float -1.000000e+00, float -1.000000e+00, float -1.000000e+00, float -1.000000e+00>, %neg, !fpmath !0 %div = fdiv <4 x float> <float -1.000000e+00, float -1.000000e+00, float -1.000000e+00, float -1.000000e+00>, %neg, !fpmath !0
store <4 x float> %div, <4 x float> addrspace(1)* %arg, align 16 store <4 x float> %div, <4 x float> addrspace(1)* %arg, align 16
ret void ret void
} }
▲ Show 20 Lines • Show All 213 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll

Show All 22 Linesbb54:
ret void ret void
work: work:
; GCN: s_not_b64 exec, exec ; GCN: s_not_b64 exec, exec
; GCN: v_mov_b32_e32 v[[tmp1189:[0-9]+]], 1 ; GCN: v_mov_b32_e32 v[[tmp1189:[0-9]+]], 1
; GCN: s_not_b64 exec, exec ; GCN: s_not_b64 exec, exec
%tmp1189 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 4, i32 1) %tmp1189 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 4, i32 1)
; GCN: s_or_saveexec_b64 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, -1 ; GCN: s_or_saveexec_b64 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], -1
; GCN: v_lshlrev_b32_e32 v[[tmp1191:[0-9]+]], 2, v[[tmp1189]] ; GCN: v_lshlrev_b32_e32 v[[tmp1191:[0-9]+]], 2, v[[tmp1189]]
%tmp1191 = mul i32 %tmp1189, 4 %tmp1191 = mul i32 %tmp1189, 4
; GCN: s_mov_b64 exec, s{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: s_mov_b64 exec, s[[[LO]]:[[HI]]]
%tmp1196 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp1191) %tmp1196 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp1191)
%tmp34 = icmp eq i32 %arg, 0 %tmp34 = icmp eq i32 %arg, 0
br i1 %tmp34, label %bb602, label %bb42 br i1 %tmp34, label %bb602, label %bb42
} }
; GCN-LABEL: strict_wwm: ; GCN-LABEL: strict_wwm:
define amdgpu_hs void @strict_wwm(i32 inreg %arg, <4 x i32> inreg %buffer) { define amdgpu_hs void @strict_wwm(i32 inreg %arg, <4 x i32> inreg %buffer) {
Show All 16 Linesbb54:
ret void ret void
work: work:
; GCN: s_not_b64 exec, exec ; GCN: s_not_b64 exec, exec
; GCN: v_mov_b32_e32 v[[tmp1189:[0-9]+]], 1 ; GCN: v_mov_b32_e32 v[[tmp1189:[0-9]+]], 1
; GCN: s_not_b64 exec, exec ; GCN: s_not_b64 exec, exec
%tmp1189 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 4, i32 1) %tmp1189 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 4, i32 1)
; GCN: s_or_saveexec_b64 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, -1 ; GCN: s_or_saveexec_b64 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], -1
; GCN: v_lshlrev_b32_e32 v[[tmp1191:[0-9]+]], 2, v[[tmp1189]] ; GCN: v_lshlrev_b32_e32 v[[tmp1191:[0-9]+]], 2, v[[tmp1189]]
%tmp1191 = mul i32 %tmp1189, 4 %tmp1191 = mul i32 %tmp1189, 4
; GCN: s_mov_b64 exec, s{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: s_mov_b64 exec, s[[[LO]]:[[HI]]]
%tmp1196 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp1191) %tmp1196 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp1191)
%tmp34 = icmp eq i32 %arg, 0 %tmp34 = icmp eq i32 %arg, 0
br i1 %tmp34, label %bb602, label %bb42 br i1 %tmp34, label %bb602, label %bb42
} }
declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #0 declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #0
declare i32 @llvm.amdgcn.wwm.i32(i32) #1 declare i32 @llvm.amdgcn.wwm.i32(i32) #1
declare i32 @llvm.amdgcn.strict.wwm.i32(i32) #1 declare i32 @llvm.amdgcn.strict.wwm.i32(i32) #1
declare void @llvm.amdgcn.raw.tbuffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg, i32 immarg) #2 declare void @llvm.amdgcn.raw.tbuffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg, i32 immarg) #2
attributes #0 = { convergent nounwind readnone willreturn } attributes #0 = { convergent nounwind readnone willreturn }
attributes #1 = { convergent nounwind readnone speculatable willreturn } attributes #1 = { convergent nounwind readnone speculatable willreturn }
attributes #2 = { nounwind willreturn writeonly } attributes #2 = { nounwind willreturn writeonly }

llvm/test/CodeGen/AMDGPU/flat-address-space.ll

; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire < %s | FileCheck -check-prefixes=CHECK,CIVI %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire < %s | FileCheck -check-prefixes=CHECK,CIVI %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,CIVI %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,CIVI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,CIVI,CIVI-HSA %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,CIVI,CIVI-HSA %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,GFX9 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,GFX9 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,GFX10 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,GFX10 %s
; CHECK-LABEL: {{^}}store_flat_i32: ; CHECK-LABEL: {{^}}store_flat_i32:
; CHECK-DAG: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:[[HI_SREG:[0-9]+]]], ; CHECK-DAG: s_load_dwordx2 s[[[LO_SREG:[0-9]+]]:[[HI_SREG:[0-9]+]]],
; CHECK-DAG: s_load_dword s[[SDATA:[0-9]+]], ; CHECK-DAG: s_load_dword s[[SDATA:[0-9]+]],
; CHECK: s_waitcnt lgkmcnt(0) ; CHECK: s_waitcnt lgkmcnt(0)
; CHECK-DAG: v_mov_b32_e32 v[[DATA:[0-9]+]], s[[SDATA]] ; CHECK-DAG: v_mov_b32_e32 v[[DATA:[0-9]+]], s[[SDATA]]
; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]] ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]]
; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]] ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]]
; CHECK: flat_store_dword v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}, v[[DATA]] ; CHECK: flat_store_dword v[[[LO_VREG]]:[[HI_VREG]]], v[[DATA]]
define amdgpu_kernel void @store_flat_i32(i32 addrspace(1)* %gptr, i32 %x) #0 { define amdgpu_kernel void @store_flat_i32(i32 addrspace(1)* %gptr, i32 %x) #0 {
%fptr = addrspacecast i32 addrspace(1)* %gptr to i32* %fptr = addrspacecast i32 addrspace(1)* %gptr to i32*
store volatile i32 %x, i32* %fptr, align 4 store volatile i32 %x, i32* %fptr, align 4
ret void ret void
} }
; CHECK-LABEL: {{^}}store_flat_i64: ; CHECK-LABEL: {{^}}store_flat_i64:
; CHECK: flat_store_dwordx2 ; CHECK: flat_store_dwordx2
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llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll

Show First 20 Lines • Show All 903 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @atomic_cmpxchg_i64_soffset(i64* %out, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_soffset(i64* %out, i64 %in, i64 %old) {
entry: entry:
%gep = getelementptr i64, i64* %out, i64 9000 %gep = getelementptr i64, i64* %out, i64 9000
%val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_offset:
; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]{{:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_atomic_cmpswap_x2 v[[[RET:[0-9]+]]{{:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]: ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[RET]]:
define amdgpu_kernel void @atomic_cmpxchg_i64_ret_offset(i64* %out, i64* %out2, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_ret_offset(i64* %out, i64* %out2, i64 %in, i64 %old) {
entry: entry:
%gep = getelementptr i64, i64* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst
%extract0 = extractvalue { i64, i1 } %val, 0 %extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, i64* %out2 store i64 %extract0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64_offset:
; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(i64* %out, i64 %in, i64 %index, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(i64* %out, i64 %in, i64 %index, i64 %old) {
entry: entry:
%ptr = getelementptr i64, i64* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64_offset:
; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_atomic_cmpswap_x2 v[[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]: ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[RET]]:
define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index, i64 %old) {
entry: entry:
%ptr = getelementptr i64, i64* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst
%extract0 = extractvalue { i64, i1 } %val, 0 %extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, i64* %out2 store i64 %extract0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64:
; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64(i64* %out, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64(i64* %out, i64 %in, i64 %old) {
entry: entry:
%val = cmpxchg volatile i64* %out, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %out, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret:
; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_atomic_cmpswap_x2 v[[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]: ; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[[[RET]]:
define amdgpu_kernel void @atomic_cmpxchg_i64_ret(i64* %out, i64* %out2, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_ret(i64* %out, i64* %out2, i64 %in, i64 %old) {
entry: entry:
%val = cmpxchg volatile i64* %out, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %out, i64 %old, i64 %in seq_cst seq_cst
%extract0 = extractvalue { i64, i1 } %val, 0 %extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, i64* %out2 store i64 %extract0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64:
; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(i64* %out, i64 %in, i64 %index, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(i64* %out, i64 %in, i64 %index, i64 %old) {
entry: entry:
%ptr = getelementptr i64, i64* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%val = cmpxchg volatile i64* %ptr, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %ptr, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64:
; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_atomic_cmpswap_x2 v[[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]: ; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[[[RET]]:
define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index, i64 %old) {
entry: entry:
%ptr = getelementptr i64, i64* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%val = cmpxchg volatile i64* %ptr, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %ptr, i64 %old, i64 %in seq_cst seq_cst
%extract0 = extractvalue { i64, i1 } %val, 0 %extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, i64* %out2 store i64 %extract0, i64* %out2
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/fmin_legacy.ll

Show All 25 Linesdefine amdgpu_kernel void @s_test_fmin_legacy_subreg_inputs_f32(float addrspace(1)* %out, <4 x float> %reg0) #0 {
%r1 = extractelement <4 x float> %reg0, i32 1 %r1 = extractelement <4 x float> %reg0, i32 1
%r2 = fcmp uge float %r0, %r1 %r2 = fcmp uge float %r0, %r1
%r3 = select i1 %r2, float %r1, float %r0 %r3 = select i1 %r2, float %r1, float %r0
store float %r3, float addrspace(1)* %out store float %r3, float addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}s_test_fmin_legacy_ule_f32: ; FUNC-LABEL: {{^}}s_test_fmin_legacy_ule_f32:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[A:[0-9]+]]:[[B:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} ; GCN-DAG: s_load_dwordx2 s[[[A:[0-9]+]]:[[B:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
; SI-SAFE: v_mov_b32_e32 [[VA:v[0-9]+]], s[[A]] ; SI-SAFE: v_mov_b32_e32 [[VA:v[0-9]+]], s[[A]]
; GCN-NONAN: v_mov_b32_e32 [[VB:v[0-9]+]], s[[B]] ; GCN-NONAN: v_mov_b32_e32 [[VB:v[0-9]+]], s[[B]]
; VI-SAFE: v_mov_b32_e32 [[VB:v[0-9]+]], s[[B]] ; VI-SAFE: v_mov_b32_e32 [[VB:v[0-9]+]], s[[B]]
; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, s[[B]], [[VA]] ; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, s[[B]], [[VA]]
; VI-SAFE: v_mov_b32_e32 [[VA:v[0-9]+]], s[[A]] ; VI-SAFE: v_mov_b32_e32 [[VA:v[0-9]+]], s[[A]]
; VI-SAFE: v_cmp_ngt_f32_e32 vcc, s[[A]], [[VB]] ; VI-SAFE: v_cmp_ngt_f32_e32 vcc, s[[A]], [[VB]]
; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[VB]], [[VA]] ; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[VB]], [[VA]]
; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, s[[A]], [[VB]] ; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, s[[A]], [[VB]]
define amdgpu_kernel void @s_test_fmin_legacy_ule_f32(float addrspace(1)* %out, float %a, float %b) #0 { define amdgpu_kernel void @s_test_fmin_legacy_ule_f32(float addrspace(1)* %out, float %a, float %b) #0 {
%cmp = fcmp ule float %a, %b %cmp = fcmp ule float %a, %b
%val = select i1 %cmp, float %a, float %b %val = select i1 %cmp, float %a, float %b
store float %val, float addrspace(1)* %out, align 4 store float %val, float addrspace(1)* %out, align 4
ret void ret void
} }
; Nsz also needed ; Nsz also needed
; FIXME: Should separate tests ; FIXME: Should separate tests
; GCN-LABEL: {{^}}s_test_fmin_legacy_ule_f32_nnan_src: ; GCN-LABEL: {{^}}s_test_fmin_legacy_ule_f32_nnan_src:
; GCN: s_load_dwordx2 s{{\[}}[[A:[0-9]+]]:[[B:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} ; GCN: s_load_dwordx2 s[[[A:[0-9]+]]:[[B:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
; GCN-DAG: v_add_f32_e64 [[ADD_A:v[0-9]+]], s[[A]], 1.0 ; GCN-DAG: v_add_f32_e64 [[ADD_A:v[0-9]+]], s[[A]], 1.0
; GCN-DAG: v_add_f32_e64 [[ADD_B:v[0-9]+]], s[[B]], 2.0 ; GCN-DAG: v_add_f32_e64 [[ADD_B:v[0-9]+]], s[[B]], 2.0
; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]] ; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]]
; VI-SAFE: v_cmp_ngt_f32_e32 vcc, [[ADD_A]], [[ADD_B]] ; VI-SAFE: v_cmp_ngt_f32_e32 vcc, [[ADD_A]], [[ADD_B]]
; VI-SAFE: v_cndmask_b32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]], vcc ; VI-SAFE: v_cndmask_b32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]], vcc
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llvm/test/CodeGen/AMDGPU/fmul.f16.ll

Show First 20 Lines • Show All 160 Lines • ▼ Show 20 Lines
entry: entry:
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
%r.val = fmul <2 x half> %a.val, <half 4.0, half 3.0> %r.val = fmul <2 x half> %a.val, <half 4.0, half 3.0>
store <2 x half> %r.val, <2 x half> addrspace(1)* %r store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void ret void
} }
; GCN-LABEL: {{^}}fmul_v4f16: ; GCN-LABEL: {{^}}fmul_v4f16:
; GFX9: buffer_load_dwordx2 v{{\[}}[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]{{\]}} ; GFX9: buffer_load_dwordx2 v[[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]]
; GFX9: buffer_load_dwordx2 v{{\[}}[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]{{\]}} ; GFX9: buffer_load_dwordx2 v[[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]]
; GFX9-DAG: v_pk_mul_f16 v[[MUL_LO:[0-9]+]], v[[A_LO]], v[[B_LO]] ; GFX9-DAG: v_pk_mul_f16 v[[MUL_LO:[0-9]+]], v[[A_LO]], v[[B_LO]]
; GFX9-DAG: v_pk_mul_f16 v[[MUL_HI:[0-9]+]], v[[A_HI]], v[[B_HI]] ; GFX9-DAG: v_pk_mul_f16 v[[MUL_HI:[0-9]+]], v[[A_HI]], v[[B_HI]]
; GFX9: buffer_store_dwordx2 v{{\[}}[[MUL_LO]]:[[MUL_HI]]{{\]}} ; GFX9: buffer_store_dwordx2 v[[[MUL_LO]]:[[MUL_HI]]]
; VI: buffer_load_dwordx2 v{{\[}}[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]{{\]}} ; VI: buffer_load_dwordx2 v[[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]]
; VI: buffer_load_dwordx2 v{{\[}}[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]{{\]}} ; VI: buffer_load_dwordx2 v[[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]]
; VI: v_mul_f16_sdwa ; VI: v_mul_f16_sdwa
; VI: v_mul_f16_e32 ; VI: v_mul_f16_e32
; VI: v_mul_f16_sdwa ; VI: v_mul_f16_sdwa
; VI: v_mul_f16_e32 ; VI: v_mul_f16_e32
; VI: v_or_b32 ; VI: v_or_b32
; VI: v_or_b32 ; VI: v_or_b32
define amdgpu_kernel void @fmul_v4f16( define amdgpu_kernel void @fmul_v4f16(
<4 x half> addrspace(1)* %r, <4 x half> addrspace(1)* %r,
<4 x half> addrspace(1)* %a, <4 x half> addrspace(1)* %a,
<4 x half> addrspace(1)* %b) { <4 x half> addrspace(1)* %b) {
entry: entry:
%a.val = load <4 x half>, <4 x half> addrspace(1)* %a %a.val = load <4 x half>, <4 x half> addrspace(1)* %a
%b.val = load <4 x half>, <4 x half> addrspace(1)* %b %b.val = load <4 x half>, <4 x half> addrspace(1)* %b
%r.val = fmul <4 x half> %a.val, %b.val %r.val = fmul <4 x half> %a.val, %b.val
store <4 x half> %r.val, <4 x half> addrspace(1)* %r store <4 x half> %r.val, <4 x half> addrspace(1)* %r
ret void ret void
} }
; GCN-LABEL: {{^}}fmul_v4f16_imm_a: ; GCN-LABEL: {{^}}fmul_v4f16_imm_a:
; GFX89-DAG: buffer_load_dwordx2 v{{\[}}[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]{{\]}} ; GFX89-DAG: buffer_load_dwordx2 v[[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]]
; GFX9-DAG: s_mov_b32 [[K1:s[0-9]+]], 0x44004200 ; GFX9-DAG: s_mov_b32 [[K1:s[0-9]+]], 0x44004200
; GFX9-DAG: s_mov_b32 [[K0:s[0-9]+]], 0x40004800 ; GFX9-DAG: s_mov_b32 [[K0:s[0-9]+]], 0x40004800
; GFX9-DAG: v_pk_mul_f16 v[[MUL_LO:[0-9]+]], v[[A_LO]], [[K0]] ; GFX9-DAG: v_pk_mul_f16 v[[MUL_LO:[0-9]+]], v[[A_LO]], [[K0]]
; GFX9-DAG: v_pk_mul_f16 v[[MUL_HI:[0-9]+]], v[[A_HI]], [[K1]] ; GFX9-DAG: v_pk_mul_f16 v[[MUL_HI:[0-9]+]], v[[A_HI]], [[K1]]
; GFX9: buffer_store_dwordx2 v{{\[}}[[MUL_LO]]:[[MUL_HI]]{{\]}} ; GFX9: buffer_store_dwordx2 v[[[MUL_LO]]:[[MUL_HI]]]
; VI-DAG: v_mov_b32_e32 [[K4:v[0-9]+]], 0x4400 ; VI-DAG: v_mov_b32_e32 [[K4:v[0-9]+]], 0x4400
; VI-DAG: v_mul_f16_sdwa v[[MUL_HI_HI:[0-9]+]], v[[A_HI]], [[K4]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-DAG: v_mul_f16_sdwa v[[MUL_HI_HI:[0-9]+]], v[[A_HI]], [[K4]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-DAG: v_mul_f16_e32 v[[MUL_HI_LO:[0-9]+]], 0x4200, v[[A_HI]] ; VI-DAG: v_mul_f16_e32 v[[MUL_HI_LO:[0-9]+]], 0x4200, v[[A_HI]]
; VI-DAG: v_add_f16_sdwa v[[MUL_LO_HI:[0-9]+]], v[[A_LO]], v[[A_LO]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-DAG: v_add_f16_sdwa v[[MUL_LO_HI:[0-9]+]], v[[A_LO]], v[[A_LO]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-DAG: v_mul_f16_e32 v[[MUL_LO_LO:[0-9]+]], 0x4800, v[[A_LO]] ; VI-DAG: v_mul_f16_e32 v[[MUL_LO_LO:[0-9]+]], 0x4800, v[[A_LO]]
; VI-DAG: v_or_b32_e32 v[[OR0:[0-9]+]], v[[MUL_LO_LO]], v[[MUL_LO_HI]] ; VI-DAG: v_or_b32_e32 v[[OR0:[0-9]+]], v[[MUL_LO_LO]], v[[MUL_LO_HI]]
; VI-DAG: v_or_b32_e32 v[[OR1:[0-9]+]], v[[MUL_HI_LO]], v[[MUL_HI_HI]] ; VI-DAG: v_or_b32_e32 v[[OR1:[0-9]+]], v[[MUL_HI_LO]], v[[MUL_HI_HI]]
; VI: buffer_store_dwordx2 v{{\[}}[[OR0]]:[[OR1]]{{\]}} ; VI: buffer_store_dwordx2 v[[[OR0]]:[[OR1]]]
define amdgpu_kernel void @fmul_v4f16_imm_a( define amdgpu_kernel void @fmul_v4f16_imm_a(
<4 x half> addrspace(1)* %r, <4 x half> addrspace(1)* %r,
<4 x half> addrspace(1)* %b) { <4 x half> addrspace(1)* %b) {
entry: entry:
%b.val = load <4 x half>, <4 x half> addrspace(1)* %b %b.val = load <4 x half>, <4 x half> addrspace(1)* %b
%r.val = fmul <4 x half> <half 8.0, half 2.0, half 3.0, half 4.0>, %b.val %r.val = fmul <4 x half> <half 8.0, half 2.0, half 3.0, half 4.0>, %b.val
store <4 x half> %r.val, <4 x half> addrspace(1)* %r store <4 x half> %r.val, <4 x half> addrspace(1)* %r
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/fneg-combines.ll

Show First 20 Lines • Show All 686 Lines • ▼ Show 20 Lines
} }
; GCN-LABEL: {{^}}v_fneg_inv2pi_minnum_f64: ; GCN-LABEL: {{^}}v_fneg_inv2pi_minnum_f64:
; GCN-DAG: {{buffer|flat}}_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]] ; GCN-DAG: {{buffer|flat}}_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]]
; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0xbfc45f30 ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0xbfc45f30
; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0x6dc9c882 ; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0x6dc9c882
; SI-DAG: v_max_f64 [[NEG_QUIET:v\[[0-9]+:[0-9]+\]]], -[[A]], -[[A]] ; SI-DAG: v_max_f64 [[NEG_QUIET:v\[[0-9]+:[0-9]+\]]], -[[A]], -[[A]]
; SI: v_max_f64 v{{\[}}[[RESULT_LO:[0-9]+]]:[[RESULT_HI:[0-9]+]]{{\]}}, [[NEG_QUIET]], s{{\[}}[[K_LO]]:[[K_HI]]{{\]}} ; SI: v_max_f64 v[[[RESULT_LO:[0-9]+]]:[[RESULT_HI:[0-9]+]]], [[NEG_QUIET]], s[[[K_LO]]:[[K_HI]]]
; VI: v_min_f64 v{{\[}}[[RESULT_LO:[0-9]+]]:[[RESULT_HI:[0-9]+]]{{\]}}, [[A]], 0.15915494 ; VI: v_min_f64 v[[[RESULT_LO:[0-9]+]]:[[RESULT_HI:[0-9]+]]], [[A]], 0.15915494
; VI: v_xor_b32_e32 v[[RESULT_HI]], 0x80000000, v[[RESULT_HI]] ; VI: v_xor_b32_e32 v[[RESULT_HI]], 0x80000000, v[[RESULT_HI]]
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}} ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[RESULT_LO]]:[[RESULT_HI]]]
define amdgpu_kernel void @v_fneg_inv2pi_minnum_f64(double addrspace(1)* %out, double addrspace(1)* %a.ptr) #0 { define amdgpu_kernel void @v_fneg_inv2pi_minnum_f64(double addrspace(1)* %out, double addrspace(1)* %a.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds double, double addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds double, double addrspace(1)* %a.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds double, double addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i64 %tid.ext
%a = load volatile double, double addrspace(1)* %a.gep %a = load volatile double, double addrspace(1)* %a.gep
%min = call double @llvm.minnum.f64(double 0x3fc45f306dc9c882, double %a) %min = call double @llvm.minnum.f64(double 0x3fc45f306dc9c882, double %a)
%fneg = fsub double -0.000000e+00, %min %fneg = fsub double -0.000000e+00, %min
store double %fneg, double addrspace(1)* %out.gep store double %fneg, double addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_fneg_neg_inv2pi_minnum_f64: ; GCN-LABEL: {{^}}v_fneg_neg_inv2pi_minnum_f64:
; GCN-DAG: {{buffer|flat}}_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]] ; GCN-DAG: {{buffer|flat}}_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]]
; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0x3fc45f30 ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0x3fc45f30
; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0x6dc9c882 ; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0x6dc9c882
; SI-DAG: v_max_f64 [[NEG_QUIET:v\[[0-9]+:[0-9]+\]]], -[[A]], -[[A]] ; SI-DAG: v_max_f64 [[NEG_QUIET:v\[[0-9]+:[0-9]+\]]], -[[A]], -[[A]]
; SI: v_max_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[NEG_QUIET]], s{{\[}}[[K_LO]]:[[K_HI]]{{\]}} ; SI: v_max_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[NEG_QUIET]], s[[[K_LO]]:[[K_HI]]]
; VI: v_max_f64 [[NEG_QUIET:v\[[0-9]+:[0-9]+\]]], -[[A]], -[[A]] ; VI: v_max_f64 [[NEG_QUIET:v\[[0-9]+:[0-9]+\]]], -[[A]], -[[A]]
; VI: v_max_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[NEG_QUIET]], 0.15915494 ; VI: v_max_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[NEG_QUIET]], 0.15915494
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
define amdgpu_kernel void @v_fneg_neg_inv2pi_minnum_f64(double addrspace(1)* %out, double addrspace(1)* %a.ptr) #0 { define amdgpu_kernel void @v_fneg_neg_inv2pi_minnum_f64(double addrspace(1)* %out, double addrspace(1)* %a.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
▲ Show 20 Lines • Show All 801 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_fneg_fp_extend_store_use_fneg_f32_to_f64(double addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
%fneg = fsub double -0.000000e+00, %fpext %fneg = fsub double -0.000000e+00, %fpext
store volatile double %fneg, double addrspace(1)* %out.gep store volatile double %fneg, double addrspace(1)* %out.gep
store volatile float %fneg.a, float addrspace(1)* undef store volatile float %fneg.a, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}v_fneg_multi_use_fp_extend_fneg_f32_to_f64: ; GCN-LABEL: {{^}}v_fneg_multi_use_fp_extend_fneg_f32_to_f64:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN-DAG: v_cvt_f64_f32_e32 v{{\[}}[[CVT_LO:[0-9]+]]:[[CVT_HI:[0-9]+]]{{\]}}, [[A]] ; GCN-DAG: v_cvt_f64_f32_e32 v[[[CVT_LO:[0-9]+]]:[[CVT_HI:[0-9]+]]], [[A]]
; GCN-DAG: v_xor_b32_e32 v[[FNEG_A:[0-9]+]], 0x80000000, v[[CVT_HI]] ; GCN-DAG: v_xor_b32_e32 v[[FNEG_A:[0-9]+]], 0x80000000, v[[CVT_HI]]
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[FNEG_A]]{{\]}} ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[FNEG_A]]]
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[CVT_LO]]:[[CVT_HI]]{{\]}} ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[CVT_LO]]:[[CVT_HI]]]
define amdgpu_kernel void @v_fneg_multi_use_fp_extend_fneg_f32_to_f64(double addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 { define amdgpu_kernel void @v_fneg_multi_use_fp_extend_fneg_f32_to_f64(double addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds double, double addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
%fpext = fpext float %a to double %fpext = fpext float %a to double
%fneg = fsub double -0.000000e+00, %fpext %fneg = fsub double -0.000000e+00, %fpext
store volatile double %fneg, double addrspace(1)* %out.gep store volatile double %fneg, double addrspace(1)* %out.gep
store volatile double %fpext, double addrspace(1)* undef store volatile double %fpext, double addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}v_fneg_multi_foldable_use_fp_extend_fneg_f32_to_f64: ; GCN-LABEL: {{^}}v_fneg_multi_foldable_use_fp_extend_fneg_f32_to_f64:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN-DAG: v_cvt_f64_f32_e32 v{{\[}}[[CVT_LO:[0-9]+]]:[[CVT_HI:[0-9]+]]{{\]}}, [[A]] ; GCN-DAG: v_cvt_f64_f32_e32 v[[[CVT_LO:[0-9]+]]:[[CVT_HI:[0-9]+]]], [[A]]
; GCN-DAG: v_xor_b32_e32 v[[FNEG_A:[0-9]+]], 0x80000000, v[[CVT_HI]] ; GCN-DAG: v_xor_b32_e32 v[[FNEG_A:[0-9]+]], 0x80000000, v[[CVT_HI]]
; GCN-DAG: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[CVT_LO]]:[[CVT_HI]]{{\]}}, 4.0 ; GCN-DAG: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], v[[[CVT_LO]]:[[CVT_HI]]], 4.0
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[FNEG_A]]{{\]}} ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[FNEG_A]]]
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[MUL]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[MUL]]
define amdgpu_kernel void @v_fneg_multi_foldable_use_fp_extend_fneg_f32_to_f64(double addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 { define amdgpu_kernel void @v_fneg_multi_foldable_use_fp_extend_fneg_f32_to_f64(double addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds double, double addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
%fpext = fpext float %a to double %fpext = fpext float %a to double
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_fneg_fp_round_fneg_f64_to_f32(float addrspace(1)* %out, double addrspace(1)* %a.ptr) #0 {
%fneg.a = fsub double -0.000000e+00, %a %fneg.a = fsub double -0.000000e+00, %a
%fpround = fptrunc double %fneg.a to float %fpround = fptrunc double %fneg.a to float
%fneg = fneg float %fpround %fneg = fneg float %fpround
store float %fneg, float addrspace(1)* %out.gep store float %fneg, float addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_fneg_fp_round_store_use_fneg_f64_to_f32: ; GCN-LABEL: {{^}}v_fneg_fp_round_store_use_fneg_f64_to_f32:
; GCN: {{buffer|flat}}_load_dwordx2 v{{\[}}[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]{{\]}} ; GCN: {{buffer|flat}}_load_dwordx2 v[[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]]
; GCN-DAG: v_cvt_f32_f64_e32 [[RESULT:v[0-9]+]], v{{\[}}[[A_LO]]:[[A_HI]]{{\]}} ; GCN-DAG: v_cvt_f32_f64_e32 [[RESULT:v[0-9]+]], v[[[A_LO]]:[[A_HI]]]
; GCN-DAG: v_xor_b32_e32 v[[NEG_A_HI:[0-9]+]], 0x80000000, v[[A_HI]] ; GCN-DAG: v_xor_b32_e32 v[[NEG_A_HI:[0-9]+]], 0x80000000, v[[A_HI]]
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[A_LO]]:[[NEG_A_HI]]{{\]}} ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[A_LO]]:[[NEG_A_HI]]]
define amdgpu_kernel void @v_fneg_fp_round_store_use_fneg_f64_to_f32(float addrspace(1)* %out, double addrspace(1)* %a.ptr) #0 { define amdgpu_kernel void @v_fneg_fp_round_store_use_fneg_f64_to_f32(float addrspace(1)* %out, double addrspace(1)* %a.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds double, double addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds double, double addrspace(1)* %a.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile double, double addrspace(1)* %a.gep %a = load volatile double, double addrspace(1)* %a.gep
%fneg.a = fsub double -0.000000e+00, %a %fneg.a = fsub double -0.000000e+00, %a
%fpround = fptrunc double %fneg.a to float %fpround = fptrunc double %fneg.a to float
%fneg = fneg float %fpround %fneg = fneg float %fpround
store volatile float %fneg, float addrspace(1)* %out.gep store volatile float %fneg, float addrspace(1)* %out.gep
store volatile double %fneg.a, double addrspace(1)* undef store volatile double %fneg.a, double addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}v_fneg_fp_round_multi_use_fneg_f64_to_f32: ; GCN-LABEL: {{^}}v_fneg_fp_round_multi_use_fneg_f64_to_f32:
; GCN: {{buffer|flat}}_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]] ; GCN: {{buffer|flat}}_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]]
; GCN-DAG: v_cvt_f32_f64_e32 [[RESULT:v[0-9]+]], [[A]] ; GCN-DAG: v_cvt_f32_f64_e32 [[RESULT:v[0-9]+]], [[A]]
; GCN-DAG: v_mul_f64 [[USE1:v\[[0-9]+:[0-9]+\]]], -[[A]], s{{\[}} ; GCN-DAG: v_mul_f64 [[USE1:v\[[0-9]+:[0-9]+\]]], -[[A]], s[
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[USE1]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[USE1]]
define amdgpu_kernel void @v_fneg_fp_round_multi_use_fneg_f64_to_f32(float addrspace(1)* %out, double addrspace(1)* %a.ptr, double %c) #0 { define amdgpu_kernel void @v_fneg_fp_round_multi_use_fneg_f64_to_f32(float addrspace(1)* %out, double addrspace(1)* %a.ptr, double %c) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds double, double addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds double, double addrspace(1)* %a.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
▲ Show 20 Lines • Show All 999 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
%bc = bitcast i64 %in to double %bc = bitcast i64 %in to double
%fabs = call double @fabs(double %bc) %fabs = call double @fabs(double %bc)
%fsub = fsub double -0.000000e+00, %fabs %fsub = fsub double -0.000000e+00, %fabs
store double %fsub, double addrspace(1)* %out store double %fsub, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}fneg_fabs_f64: ; GCN-LABEL: {{^}}fneg_fabs_f64:
; SI-DAG: s_load_dwordx2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x13 ; SI-DAG: s_load_dwordx2 s[[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]], s[{{[0-9]+:[0-9]+}}], 0x13
; VI-DAG: s_load_dwordx2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x4c ; VI-DAG: s_load_dwordx2 s[[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]], s[{{[0-9]+:[0-9]+}}], 0x4c
; GCN-DAG: s_bitset1_b32 s[[HI_X]], 31 ; GCN-DAG: s_bitset1_b32 s[[HI_X]], 31
; GCN-DAG: v_mov_b32_e32 v[[LO_V:[0-9]+]], s[[LO_X]] ; GCN-DAG: v_mov_b32_e32 v[[LO_V:[0-9]+]], s[[LO_X]]
; GCN-DAG: v_mov_b32_e32 v[[HI_V:[0-9]+]], s[[HI_X]] ; GCN-DAG: v_mov_b32_e32 v[[HI_V:[0-9]+]], s[[HI_X]]
; GCN: buffer_store_dwordx2 v{{\[}}[[LO_V]]:[[HI_V]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LO_V]]:[[HI_V]]]
define amdgpu_kernel void @fneg_fabs_f64(double addrspace(1)* %out, [8 x i32], double %in) { define amdgpu_kernel void @fneg_fabs_f64(double addrspace(1)* %out, [8 x i32], double %in) {
%fabs = call double @llvm.fabs.f64(double %in) %fabs = call double @llvm.fabs.f64(double %in)
%fsub = fsub double -0.000000e+00, %fabs %fsub = fsub double -0.000000e+00, %fabs
store double %fsub, double addrspace(1)* %out, align 8 store double %fsub, double addrspace(1)* %out, align 8
ret void ret void
} }
; GCN-LABEL: {{^}}fneg_fabs_v2f64: ; GCN-LABEL: {{^}}fneg_fabs_v2f64:
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llvm/test/CodeGen/AMDGPU/fp_to_sint.f64.ll

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} }
; FUNC-LABEL: @fp_to_sint_i64_f64 ; FUNC-LABEL: @fp_to_sint_i64_f64
; CI-DAG: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] ; CI-DAG: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]
; CI-DAG: v_trunc_f64_e32 [[TRUNC:v\[[0-9]+:[0-9]+\]]], [[VAL]] ; CI-DAG: v_trunc_f64_e32 [[TRUNC:v\[[0-9]+:[0-9]+\]]], [[VAL]]
; CI-DAG: s_mov_b32 s[[K0_LO:[0-9]+]], 0{{$}} ; CI-DAG: s_mov_b32 s[[K0_LO:[0-9]+]], 0{{$}}
; CI-DAG: s_mov_b32 s[[K0_HI:[0-9]+]], 0x3df00000 ; CI-DAG: s_mov_b32 s[[K0_HI:[0-9]+]], 0x3df00000
; CI-DAG: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[VAL]], s{{\[}}[[K0_LO]]:[[K0_HI]]{{\]}} ; CI-DAG: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[VAL]], s[[[K0_LO]]:[[K0_HI]]]
; CI-DAG: v_floor_f64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[MUL]] ; CI-DAG: v_floor_f64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[MUL]]
; CI-DAG: s_mov_b32 s[[K1_HI:[0-9]+]], 0xc1f00000 ; CI-DAG: s_mov_b32 s[[K1_HI:[0-9]+]], 0xc1f00000
; CI-DAG: v_fma_f64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]{{\]}}, [[TRUNC]] ; CI-DAG: v_fma_f64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]], [[TRUNC]]
; CI-DAG: v_cvt_u32_f64_e32 v[[LO:[0-9]+]], [[FMA]] ; CI-DAG: v_cvt_u32_f64_e32 v[[LO:[0-9]+]], [[FMA]]
; CI-DAG: v_cvt_i32_f64_e32 v[[HI:[0-9]+]], [[FLOOR]] ; CI-DAG: v_cvt_i32_f64_e32 v[[HI:[0-9]+]], [[FLOOR]]
; CI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; CI: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
define amdgpu_kernel void @fp_to_sint_i64_f64(i64 addrspace(1)* %out, double addrspace(1)* %in) { define amdgpu_kernel void @fp_to_sint_i64_f64(i64 addrspace(1)* %out, double addrspace(1)* %in) {
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
%gep = getelementptr double, double addrspace(1)* %in, i32 %tid %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
%val = load double, double addrspace(1)* %gep, align 8 %val = load double, double addrspace(1)* %gep, align 8
%cast = fptosi double %val to i64 %cast = fptosi double %val to i64
store i64 %cast, i64 addrspace(1)* %out, align 8 store i64 %cast, i64 addrspace(1)* %out, align 8
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/fp_to_uint.f64.ll

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} }
; FUNC-LABEL: @fp_to_uint_i64_f64 ; FUNC-LABEL: @fp_to_uint_i64_f64
; CI-DAG: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] ; CI-DAG: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]
; CI-DAG: v_trunc_f64_e32 [[TRUNC:v\[[0-9]+:[0-9]+\]]], [[VAL]] ; CI-DAG: v_trunc_f64_e32 [[TRUNC:v\[[0-9]+:[0-9]+\]]], [[VAL]]
; CI-DAG: s_mov_b32 s[[K0_LO:[0-9]+]], 0{{$}} ; CI-DAG: s_mov_b32 s[[K0_LO:[0-9]+]], 0{{$}}
; CI-DAG: s_mov_b32 s[[K0_HI:[0-9]+]], 0x3df00000 ; CI-DAG: s_mov_b32 s[[K0_HI:[0-9]+]], 0x3df00000
; CI-DAG: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[VAL]], s{{\[}}[[K0_LO]]:[[K0_HI]]{{\]}} ; CI-DAG: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[VAL]], s[[[K0_LO]]:[[K0_HI]]]
; CI-DAG: v_floor_f64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[MUL]] ; CI-DAG: v_floor_f64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[MUL]]
; CI-DAG: s_mov_b32 s[[K1_HI:[0-9]+]], 0xc1f00000 ; CI-DAG: s_mov_b32 s[[K1_HI:[0-9]+]], 0xc1f00000
; CI-DAG: v_fma_f64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]{{\]}}, [[TRUNC]] ; CI-DAG: v_fma_f64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]], [[TRUNC]]
; CI-DAG: v_cvt_u32_f64_e32 v[[LO:[0-9]+]], [[FMA]] ; CI-DAG: v_cvt_u32_f64_e32 v[[LO:[0-9]+]], [[FMA]]
; CI-DAG: v_cvt_u32_f64_e32 v[[HI:[0-9]+]], [[FLOOR]] ; CI-DAG: v_cvt_u32_f64_e32 v[[HI:[0-9]+]], [[FLOOR]]
; CI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; CI: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
define amdgpu_kernel void @fp_to_uint_i64_f64(i64 addrspace(1)* %out, double addrspace(1)* %in) { define amdgpu_kernel void @fp_to_uint_i64_f64(i64 addrspace(1)* %out, double addrspace(1)* %in) {
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
%gep = getelementptr double, double addrspace(1)* %in, i32 %tid %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
%val = load double, double addrspace(1)* %gep, align 8 %val = load double, double addrspace(1)* %gep, align 8
%cast = fptoui double %val to i64 %cast = fptoui double %val to i64
store i64 %cast, i64 addrspace(1)* %out, align 4 store i64 %cast, i64 addrspace(1)* %out, align 4
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/fpext.f16.ll

Show All 14 Linesentry:
%r.val = fpext half %a.val to float %r.val = fpext half %a.val to float
store float %r.val, float addrspace(1)* %r store float %r.val, float addrspace(1)* %r
ret void ret void
} }
; GCN-LABEL: {{^}}fpext_f16_to_f64 ; GCN-LABEL: {{^}}fpext_f16_to_f64
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; GCN: v_cvt_f64_f32_e32 v{{\[}}[[R_F64_0:[0-9]+]]:[[R_F64_1:[0-9]+]]{{\]}}, v[[A_F32]] ; GCN: v_cvt_f64_f32_e32 v[[[R_F64_0:[0-9]+]]:[[R_F64_1:[0-9]+]]], v[[A_F32]]
; GCN: buffer_store_dwordx2 v{{\[}}[[R_F64_0]]:[[R_F64_1]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[R_F64_0]]:[[R_F64_1]]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @fpext_f16_to_f64( define amdgpu_kernel void @fpext_f16_to_f64(
double addrspace(1)* %r, double addrspace(1)* %r,
half addrspace(1)* %a) #0 { half addrspace(1)* %a) #0 {
entry: entry:
%a.val = load half, half addrspace(1)* %a %a.val = load half, half addrspace(1)* %a
%r.val = fpext half %a.val to double %r.val = fpext half %a.val to double
store double %r.val, double addrspace(1)* %r store double %r.val, double addrspace(1)* %r
ret void ret void
} }
; GCN-LABEL: {{^}}fpext_v2f16_to_v2f32 ; GCN-LABEL: {{^}}fpext_v2f16_to_v2f32
; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]] ; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]]
; GCN-DAG: v_cvt_f32_f16_e32 v[[R_F32_0:[0-9]+]], v[[A_V2_F16]] ; GCN-DAG: v_cvt_f32_f16_e32 v[[R_F32_0:[0-9]+]], v[[A_V2_F16]]
; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] ; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
; SI: v_cvt_f32_f16_e32 v[[R_F32_1:[0-9]+]], v[[A_F16_1]] ; SI: v_cvt_f32_f16_e32 v[[R_F32_1:[0-9]+]], v[[A_F16_1]]
; GFX89: v_cvt_f32_f16_sdwa v[[R_F32_1:[0-9]+]], v[[A_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX89: v_cvt_f32_f16_sdwa v[[R_F32_1:[0-9]+]], v[[A_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GCN: buffer_store_dwordx2 v{{\[}}[[R_F32_0]]:[[R_F32_1]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[R_F32_0]]:[[R_F32_1]]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @fpext_v2f16_to_v2f32( define amdgpu_kernel void @fpext_v2f16_to_v2f32(
<2 x float> addrspace(1)* %r, <2 x float> addrspace(1)* %r,
<2 x half> addrspace(1)* %a) #0 { <2 x half> addrspace(1)* %a) #0 {
entry: entry:
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
%r.val = fpext <2 x half> %a.val to <2 x float> %r.val = fpext <2 x half> %a.val to <2 x float>
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llvm/test/CodeGen/AMDGPU/fptosi.f16.ll

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; Need to make sure we promote f16 to f32 when converting f16 to i64. Existing ; Need to make sure we promote f16 to f32 when converting f16 to i64. Existing
; test checks code generated for 'i64 = fp_to_sint f32'. ; test checks code generated for 'i64 = fp_to_sint f32'.
; GCN-LABEL: {{^}}fptosi_f16_to_i64 ; GCN-LABEL: {{^}}fptosi_f16_to_i64
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; GCN: v_cvt_i32_f32_e32 v[[R_I64_Low:[0-9]+]], v[[A_F32]] ; GCN: v_cvt_i32_f32_e32 v[[R_I64_Low:[0-9]+]], v[[A_F32]]
; GCN: v_ashrrev_i32_e32 v[[R_I64_High:[0-9]+]], 31, v[[R_I64_Low]] ; GCN: v_ashrrev_i32_e32 v[[R_I64_High:[0-9]+]], 31, v[[R_I64_Low]]
; GCN: buffer_store_dwordx2 v{{\[}}[[R_I64_Low]]{{\:}}[[R_I64_High]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[R_I64_Low]]{{\:}}[[R_I64_High]]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @fptosi_f16_to_i64( define amdgpu_kernel void @fptosi_f16_to_i64(
i64 addrspace(1)* %r, i64 addrspace(1)* %r,
half addrspace(1)* %a) { half addrspace(1)* %a) {
entry: entry:
%a.val = load half, half addrspace(1)* %a %a.val = load half, half addrspace(1)* %a
%r.val = fptosi half %a.val to i64 %r.val = fptosi half %a.val to i64
store i64 %r.val, i64 addrspace(1)* %r store i64 %r.val, i64 addrspace(1)* %r
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; SI: v_ashrrev_i32_e32 v[[R_I64_1_High:[0-9]+]], 31, v[[R_I64_1_Low]] ; SI: v_ashrrev_i32_e32 v[[R_I64_1_High:[0-9]+]], 31, v[[R_I64_1_Low]]
; VI-DAG: v_cvt_f32_f16_sdwa v[[A_F32_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; VI-DAG: v_cvt_f32_f16_sdwa v[[A_F32_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; VI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]] ; VI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
; VI-DAG: v_cvt_i32_f32_e32 v[[R_I64_1_Low:[0-9]+]], v[[A_F32_1]] ; VI-DAG: v_cvt_i32_f32_e32 v[[R_I64_1_Low:[0-9]+]], v[[A_F32_1]]
; VI-DAG: v_cvt_i32_f32_e32 v[[R_I64_0_Low:[0-9]+]], v[[A_F32_0]] ; VI-DAG: v_cvt_i32_f32_e32 v[[R_I64_0_Low:[0-9]+]], v[[A_F32_0]]
; VI-NOT: DEADBEEF ; VI-NOT: DEADBEEF
; VI-DAG: v_ashrrev_i32_e32 v[[R_I64_1_High:[0-9]+]], 31, v[[R_I64_1_Low]] ; VI-DAG: v_ashrrev_i32_e32 v[[R_I64_1_High:[0-9]+]], 31, v[[R_I64_1_Low]]
; VI-DAG: v_ashrrev_i32_e32 v[[R_I64_0_High:[0-9]+]], 31, v[[R_I64_0_Low]] ; VI-DAG: v_ashrrev_i32_e32 v[[R_I64_0_High:[0-9]+]], 31, v[[R_I64_0_Low]]
; GCN: buffer_store_dwordx4 v{{\[}}[[R_I64_0_Low]]{{\:}}[[R_I64_1_High]]{{\]}} ; GCN: buffer_store_dwordx4 v[[[R_I64_0_Low]]{{\:}}[[R_I64_1_High]]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @fptosi_v2f16_to_v2i64( define amdgpu_kernel void @fptosi_v2f16_to_v2i64(
<2 x i64> addrspace(1)* %r, <2 x i64> addrspace(1)* %r,
<2 x half> addrspace(1)* %a) { <2 x half> addrspace(1)* %a) {
entry: entry:
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
%r.val = fptosi <2 x half> %a.val to <2 x i64> %r.val = fptosi <2 x half> %a.val to <2 x i64>
store <2 x i64> %r.val, <2 x i64> addrspace(1)* %r store <2 x i64> %r.val, <2 x i64> addrspace(1)* %r
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llvm/test/CodeGen/AMDGPU/fptoui.f16.ll

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; Need to make sure we promote f16 to f32 when converting f16 to i64. Existing ; Need to make sure we promote f16 to f32 when converting f16 to i64. Existing
; test checks code generated for 'i64 = fp_to_uint f32'. ; test checks code generated for 'i64 = fp_to_uint f32'.
; GCN-LABEL: {{^}}fptoui_f16_to_i64 ; GCN-LABEL: {{^}}fptoui_f16_to_i64
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: v_mov_b32_e32 v[[R_I64_High:[0-9]+]], 0 ; GCN: v_mov_b32_e32 v[[R_I64_High:[0-9]+]], 0
; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; GCN: v_cvt_u32_f32_e32 v[[R_I64_Low:[0-9]+]], v[[A_F32]] ; GCN: v_cvt_u32_f32_e32 v[[R_I64_Low:[0-9]+]], v[[A_F32]]
; GCN: buffer_store_dwordx2 v{{\[}}[[R_I64_Low]]{{\:}}[[R_I64_High]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[R_I64_Low]]{{\:}}[[R_I64_High]]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @fptoui_f16_to_i64( define amdgpu_kernel void @fptoui_f16_to_i64(
i64 addrspace(1)* %r, i64 addrspace(1)* %r,
half addrspace(1)* %a) { half addrspace(1)* %a) {
entry: entry:
%a.val = load half, half addrspace(1)* %a %a.val = load half, half addrspace(1)* %a
%r.val = fptoui half %a.val to i64 %r.val = fptoui half %a.val to i64
store i64 %r.val, i64 addrspace(1)* %r store i64 %r.val, i64 addrspace(1)* %r
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; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] ; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
; SI: v_cvt_u32_f32_e32 v[[R_I64_0_Low:[0-9]+]], v[[A_F32_0]] ; SI: v_cvt_u32_f32_e32 v[[R_I64_0_Low:[0-9]+]], v[[A_F32_0]]
; SI: v_cvt_u32_f32_e32 v[[R_I64_1_Low:[0-9]+]], v[[A_F32_1]] ; SI: v_cvt_u32_f32_e32 v[[R_I64_1_Low:[0-9]+]], v[[A_F32_1]]
; VI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]] ; VI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
; VI: v_cvt_f32_f16_sdwa v[[A_F32_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; VI: v_cvt_f32_f16_sdwa v[[A_F32_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; VI: v_cvt_u32_f32_e32 v[[R_I64_0_Low:[0-9]+]], v[[A_F32_0]] ; VI: v_cvt_u32_f32_e32 v[[R_I64_0_Low:[0-9]+]], v[[A_F32_0]]
; VI: v_cvt_u32_f32_e32 v[[R_I64_1_Low:[0-9]+]], v[[A_F32_1]] ; VI: v_cvt_u32_f32_e32 v[[R_I64_1_Low:[0-9]+]], v[[A_F32_1]]
; GCN: v_mov_b32_e32 v[[R_I64_0_High:[0-9]+]], 0 ; GCN: v_mov_b32_e32 v[[R_I64_0_High:[0-9]+]], 0
; GCN: buffer_store_dwordx4 v{{\[}}[[R_I64_0_Low]]{{\:}}[[R_I64_1_High]]{{\]}} ; GCN: buffer_store_dwordx4 v[[[R_I64_0_Low]]{{\:}}[[R_I64_1_High]]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @fptoui_v2f16_to_v2i64( define amdgpu_kernel void @fptoui_v2f16_to_v2i64(
<2 x i64> addrspace(1)* %r, <2 x i64> addrspace(1)* %r,
<2 x half> addrspace(1)* %a) { <2 x half> addrspace(1)* %a) {
entry: entry:
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
%r.val = fptoui <2 x half> %a.val to <2 x i64> %r.val = fptoui <2 x half> %a.val to <2 x i64>
store <2 x i64> %r.val, <2 x i64> addrspace(1)* %r store <2 x i64> %r.val, <2 x i64> addrspace(1)* %r
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llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll

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entry: entry:
%a.val = load float, float addrspace(1)* %a %a.val = load float, float addrspace(1)* %a
%r.val = fptrunc float %a.val to half %r.val = fptrunc float %a.val to half
store half %r.val, half addrspace(1)* %r store half %r.val, half addrspace(1)* %r
ret void ret void
} }
; GCN-LABEL: {{^}}fptrunc_f64_to_f16: ; GCN-LABEL: {{^}}fptrunc_f64_to_f16:
; GCN: buffer_load_dwordx2 v{{\[}}[[A_F64_0:[0-9]+]]:[[A_F64_1:[0-9]+]]{{\]}} ; GCN: buffer_load_dwordx2 v[[[A_F64_0:[0-9]+]]:[[A_F64_1:[0-9]+]]]
; GCN: v_cvt_f32_f64_e32 v[[A_F32:[0-9]+]], v{{\[}}[[A_F64_0]]:[[A_F64_1]]{{\]}} ; GCN: v_cvt_f32_f64_e32 v[[A_F32:[0-9]+]], v[[[A_F64_0]]:[[A_F64_1]]]
; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_F32]] ; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_F32]]
; GCN: buffer_store_short v[[R_F16]] ; GCN: buffer_store_short v[[R_F16]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @fptrunc_f64_to_f16( define amdgpu_kernel void @fptrunc_f64_to_f16(
half addrspace(1)* %r, half addrspace(1)* %r,
double addrspace(1)* %a) { double addrspace(1)* %a) {
entry: entry:
%a.val = load double, double addrspace(1)* %a %a.val = load double, double addrspace(1)* %a
%r.val = fptrunc double %a.val to half %r.val = fptrunc double %a.val to half
store half %r.val, half addrspace(1)* %r store half %r.val, half addrspace(1)* %r
ret void ret void
} }
; GCN-LABEL: {{^}}fptrunc_v2f32_to_v2f16: ; GCN-LABEL: {{^}}fptrunc_v2f32_to_v2f16:
; GCN: buffer_load_dwordx2 v{{\[}}[[A_F32_0:[0-9]+]]:[[A_F32_1:[0-9]+]]{{\]}} ; GCN: buffer_load_dwordx2 v[[[A_F32_0:[0-9]+]]:[[A_F32_1:[0-9]+]]]
; GCN-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[A_F32_0]] ; GCN-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[A_F32_0]]
; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[A_F32_1]] ; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[A_F32_1]]
; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]] ; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
; VI-DAG: v_cvt_f16_f32_sdwa v[[R_F16_1:[0-9]+]], v[[A_F32_1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD ; VI-DAG: v_cvt_f16_f32_sdwa v[[R_F16_1:[0-9]+]], v[[A_F32_1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]] ; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]]
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entry: entry:
%a.val = load <2 x float>, <2 x float> addrspace(1)* %a %a.val = load <2 x float>, <2 x float> addrspace(1)* %a
%r.val = fptrunc <2 x float> %a.val to <2 x half> %r.val = fptrunc <2 x float> %a.val to <2 x half>
store <2 x half> %r.val, <2 x half> addrspace(1)* %r store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void ret void
} }
; GCN-LABEL: {{^}}fptrunc_v2f64_to_v2f16: ; GCN-LABEL: {{^}}fptrunc_v2f64_to_v2f16:
; GCN: buffer_load_dwordx4 v{{\[}}[[A_F64_0:[0-9]+]]:[[A_F64_3:[0-9]+]]{{\]}} ; GCN: buffer_load_dwordx4 v[[[A_F64_0:[0-9]+]]:[[A_F64_3:[0-9]+]]]
; GCN-DAG: v_cvt_f32_f64_e32 v[[A_F32_0:[0-9]+]], v{{\[}}[[A_F64_0]]:{{[0-9]+}}{{\]}} ; GCN-DAG: v_cvt_f32_f64_e32 v[[A_F32_0:[0-9]+]], v[[[A_F64_0]]:{{[0-9]+}}]
; GCN-DAG: v_cvt_f32_f64_e32 v[[A_F32_1:[0-9]+]], v{{\[}}{{[0-9]+}}:[[A_F64_3]]{{\]}} ; GCN-DAG: v_cvt_f32_f64_e32 v[[A_F32_1:[0-9]+]], v[{{[0-9]+}}:[[A_F64_3]]]
; VI: v_cvt_f16_f32_sdwa v[[R_F16_HI:[0-9]+]], v[[A_F32_1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD ; VI: v_cvt_f16_f32_sdwa v[[R_F16_HI:[0-9]+]], v[[A_F32_1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; GCN-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[A_F32_0]] ; GCN-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[A_F32_0]]
; ;
; SI-DAG: v_cvt_f16_f32_e32 v[[CVTHI:[0-9]+]], v[[A_F32_1]] ; SI-DAG: v_cvt_f16_f32_e32 v[[CVTHI:[0-9]+]], v[[A_F32_1]]
; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[CVTHI]] ; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[CVTHI]]
; SIVI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]] ; SIVI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
▲ Show 20 Lines • Show All 122 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/fract.f64.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,SI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,SI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,CI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,CI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,CI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,CI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-UNSAFE,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-UNSAFE,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-UNSAFE,VI-UNSAFE,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-UNSAFE,VI-UNSAFE,FUNC %s
declare double @llvm.fabs.f64(double) #0 declare double @llvm.fabs.f64(double) #0
declare double @llvm.floor.f64(double) #0 declare double @llvm.floor.f64(double) #0
; FUNC-LABEL: {{^}}fract_f64: ; FUNC-LABEL: {{^}}fract_f64:
; SI-DAG: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]] ; SI-DAG: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1 ; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff ; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v{{\[}}[[UPLO]]:[[UPHI]]] ; SI-DAG: v_min_f64 v[[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v[[[UPLO]]:[[UPHI]]]
; SI-DAG: v_cmp_class_f64_e64 vcc, v{{\[}}[[LO]]:[[HI]]], 3 ; SI-DAG: v_cmp_class_f64_e64 vcc, v[[[LO]]:[[HI]]], 3
; SI: v_cndmask_b32_e32 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], vcc ; SI: v_cndmask_b32_e32 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], vcc
; SI: v_cndmask_b32_e32 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], vcc ; SI: v_cndmask_b32_e32 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], vcc
; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]{{\]}}, -v{{\[}}[[RESLO]]:[[RESHI]]{{\]}} ; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], v[[[LO]]:[[HI]]], -v[[[RESLO]]:[[RESHI]]]
; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]{{\]}}, -[[SUB0]] ; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], v[[[LO]]:[[HI]]], -[[SUB0]]
; CI: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]] ; CI: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]]
; CI: v_floor_f64_e32 [[FLOORX:v\[[0-9]+:[0-9]+\]]], [[X]] ; CI: v_floor_f64_e32 [[FLOORX:v\[[0-9]+:[0-9]+\]]], [[X]]
; CI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], [[X]], -[[FLOORX]] ; CI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], [[X]], -[[FLOORX]]
; GCN-UNSAFE: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]] ; GCN-UNSAFE: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]]
; GCN-UNSAFE: v_fract_f64_e32 [[FRACT:v\[[0-9]+:[0-9]+\]]], [[X]] ; GCN-UNSAFE: v_fract_f64_e32 [[FRACT:v\[[0-9]+:[0-9]+\]]], [[X]]
; GCN: buffer_store_dwordx2 [[FRACT]] ; GCN: buffer_store_dwordx2 [[FRACT]]
define amdgpu_kernel void @fract_f64(double addrspace(1)* %out, double addrspace(1)* %src) #1 { define amdgpu_kernel void @fract_f64(double addrspace(1)* %out, double addrspace(1)* %src) #1 {
%x = load double, double addrspace(1)* %src %x = load double, double addrspace(1)* %src
%floor.x = call double @llvm.floor.f64(double %x) %floor.x = call double @llvm.floor.f64(double %x)
%fract = fsub double %x, %floor.x %fract = fsub double %x, %floor.x
store double %fract, double addrspace(1)* %out store double %fract, double addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}fract_f64_neg: ; FUNC-LABEL: {{^}}fract_f64_neg:
; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]] ; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1 ; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff ; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v{{\[}}[[UPLO]]:[[UPHI]]] ; SI-DAG: v_min_f64 v[[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v[[[UPLO]]:[[UPHI]]]
; SI-DAG: v_cmp_class_f64_e64 vcc, v{{\[}}[[LO]]:[[HI]]], 3 ; SI-DAG: v_cmp_class_f64_e64 vcc, v[[[LO]]:[[HI]]], 3
; SI: v_cndmask_b32_e32 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], vcc ; SI: v_cndmask_b32_e32 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], vcc
; SI: v_cndmask_b32_e32 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], vcc ; SI: v_cndmask_b32_e32 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], vcc
; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO]]:[[HI]]{{\]}}, -v{{\[}}[[RESLO]]:[[RESHI]]{{\]}} ; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], -v[[[LO]]:[[HI]]], -v[[[RESLO]]:[[RESHI]]]
; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO]]:[[HI]]{{\]}}, -[[SUB0]] ; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -v[[[LO]]:[[HI]]], -[[SUB0]]
; CI: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]] ; CI: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]]
; CI: v_floor_f64_e64 [[FLOORX:v\[[0-9]+:[0-9]+\]]], -[[X]] ; CI: v_floor_f64_e64 [[FLOORX:v\[[0-9]+:[0-9]+\]]], -[[X]]
; CI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -[[X]], -[[FLOORX]] ; CI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -[[X]], -[[FLOORX]]
; GCN-UNSAFE: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]] ; GCN-UNSAFE: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]]
; GCN-UNSAFE: v_fract_f64_e64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -[[X]] ; GCN-UNSAFE: v_fract_f64_e64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -[[X]]
; GCN: buffer_store_dwordx2 [[FRACT]] ; GCN: buffer_store_dwordx2 [[FRACT]]
define amdgpu_kernel void @fract_f64_neg(double addrspace(1)* %out, double addrspace(1)* %src) #1 { define amdgpu_kernel void @fract_f64_neg(double addrspace(1)* %out, double addrspace(1)* %src) #1 {
%x = load double, double addrspace(1)* %src %x = load double, double addrspace(1)* %src
%neg.x = fsub double -0.0, %x %neg.x = fsub double -0.0, %x
%floor.neg.x = call double @llvm.floor.f64(double %neg.x) %floor.neg.x = call double @llvm.floor.f64(double %neg.x)
%fract = fsub double %neg.x, %floor.neg.x %fract = fsub double %neg.x, %floor.neg.x
store double %fract, double addrspace(1)* %out store double %fract, double addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}fract_f64_neg_abs: ; FUNC-LABEL: {{^}}fract_f64_neg_abs:
; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]| ; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]|
; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1 ; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff ; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v{{\[}}[[UPLO]]:[[UPHI]]] ; SI-DAG: v_min_f64 v[[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v[[[UPLO]]:[[UPHI]]]
; SI-DAG: v_cmp_class_f64_e64 vcc, v{{\[}}[[LO]]:[[HI]]], 3 ; SI-DAG: v_cmp_class_f64_e64 vcc, v[[[LO]]:[[HI]]], 3
; SI: v_cndmask_b32_e32 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], vcc ; SI: v_cndmask_b32_e32 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], vcc
; SI: v_cndmask_b32_e32 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], vcc ; SI: v_cndmask_b32_e32 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], vcc
; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO]]:[[HI]]{{\]}}|, -v{{\[}}[[RESLO]]:[[RESHI]]{{\]}} ; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], -|v[[[LO]]:[[HI]]]|, -v[[[RESLO]]:[[RESHI]]]
; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO]]:[[HI]]{{\]}}|, -[[SUB0]] ; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -|v[[[LO]]:[[HI]]]|, -[[SUB0]]
; CI: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]] ; CI: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]]
; CI: v_floor_f64_e64 [[FLOORX:v\[[0-9]+:[0-9]+\]]], -|[[X]]| ; CI: v_floor_f64_e64 [[FLOORX:v\[[0-9]+:[0-9]+\]]], -|[[X]]|
; CI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -|[[X]]|, -[[FLOORX]] ; CI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -|[[X]]|, -[[FLOORX]]
; GCN-UNSAFE: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]] ; GCN-UNSAFE: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]]
; GCN-UNSAFE: v_fract_f64_e64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -|[[X]]| ; GCN-UNSAFE: v_fract_f64_e64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -|[[X]]|
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llvm/test/CodeGen/AMDGPU/function-args.ll

Show First 20 Lines • Show All 553 Lines • ▼ Show 20 Linesdefine void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0, { i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg1, i32 %arg2) #0 {
ret void ret void
} }
; GCN-LABEL: {{^}}void_func_byval_i32_byval_i64: ; GCN-LABEL: {{^}}void_func_byval_i32_byval_i64:
; GCN-DAG: buffer_load_dword v[[ARG0_LOAD:[0-9]+]], off, s[0:3], s32{{$}} ; GCN-DAG: buffer_load_dword v[[ARG0_LOAD:[0-9]+]], off, s[0:3], s32{{$}}
; GCN-DAG: buffer_load_dword v[[ARG1_LOAD0:[0-9]+]], off, s[0:3], s32 offset:8{{$}} ; GCN-DAG: buffer_load_dword v[[ARG1_LOAD0:[0-9]+]], off, s[0:3], s32 offset:8{{$}}
; GCN-DAG: buffer_load_dword v[[ARG1_LOAD1:[0-9]+]], off, s[0:3], s32 offset:12{{$}} ; GCN-DAG: buffer_load_dword v[[ARG1_LOAD1:[0-9]+]], off, s[0:3], s32 offset:12{{$}}
; GCN-DAG: buffer_store_dword v[[ARG0_LOAD]], off ; GCN-DAG: buffer_store_dword v[[ARG0_LOAD]], off
; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ARG1_LOAD0]]:[[ARG1_LOAD1]]{{\]}}, off ; GCN-DAG: buffer_store_dwordx2 v[[[ARG1_LOAD0]]:[[ARG1_LOAD1]]], off
define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval(i32) %arg0, i64 addrspace(5)* byval(i64) %arg1) #0 { define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval(i32) %arg0, i64 addrspace(5)* byval(i64) %arg1) #0 {
%arg0.load = load i32, i32 addrspace(5)* %arg0 %arg0.load = load i32, i32 addrspace(5)* %arg0
%arg1.load = load i64, i64 addrspace(5)* %arg1 %arg1.load = load i64, i64 addrspace(5)* %arg1
store i32 %arg0.load, i32 addrspace(1)* undef store i32 %arg0.load, i32 addrspace(1)* undef
store i64 %arg1.load, i64 addrspace(1)* undef store i64 %arg1.load, i64 addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}void_func_v32i32_i32_i64: ; GCN-LABEL: {{^}}void_func_v32i32_i32_i64:
; GCN-DAG: buffer_store_dwordx4 v[0:3], off ; GCN-DAG: buffer_store_dwordx4 v[0:3], off
; GCN-DAG: buffer_store_dwordx4 v[4:7], off ; GCN-DAG: buffer_store_dwordx4 v[4:7], off
; GCN-DAG: buffer_store_dwordx4 v[8:11], off ; GCN-DAG: buffer_store_dwordx4 v[8:11], off
; GCN-DAG: buffer_store_dwordx4 v[12:15], off ; GCN-DAG: buffer_store_dwordx4 v[12:15], off
; GCN-DAG: buffer_store_dwordx4 v[16:19], off ; GCN-DAG: buffer_store_dwordx4 v[16:19], off
; GCN-DAG: buffer_store_dwordx4 v[20:23], off ; GCN-DAG: buffer_store_dwordx4 v[20:23], off
; GCN-DAG: buffer_store_dwordx4 v[24:27], off ; GCN-DAG: buffer_store_dwordx4 v[24:27], off
; GCN-DAG: buffer_store_dwordx4 v[28:31], off ; GCN-DAG: buffer_store_dwordx4 v[28:31], off
; GCN-DAG: buffer_load_dword v[[LOAD_ARG0_31:[0-9]+]], off, s[0:3], s32{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG0_31:[0-9]+]], off, s[0:3], s32{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG1:[0-9]+]], off, s[0:3], s32 offset:4{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG1:[0-9]+]], off, s[0:3], s32 offset:4{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_0:[0-9]+]], off, s[0:3], s32 offset:8 ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_0:[0-9]+]], off, s[0:3], s32 offset:8
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_1:[0-9]+]], off, s[0:3], s32 offset:12 ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_1:[0-9]+]], off, s[0:3], s32 offset:12
; GCN: buffer_store_dword v[[LOAD_ARG1]] ; GCN: buffer_store_dword v[[LOAD_ARG1]]
; GCN: buffer_store_dwordx2 v{{\[}}[[LOAD_ARG2_0]]:[[LOAD_ARG2_1]]{{\]}}, off ; GCN: buffer_store_dwordx2 v[[[LOAD_ARG2_0]]:[[LOAD_ARG2_1]]], off
define void @void_func_v32i32_i32_i64(<32 x i32> %arg0, i32 %arg1, i64 %arg2) #0 { define void @void_func_v32i32_i32_i64(<32 x i32> %arg0, i32 %arg1, i64 %arg2) #0 {
store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef
store volatile i32 %arg1, i32 addrspace(1)* undef store volatile i32 %arg1, i32 addrspace(1)* undef
store volatile i64 %arg2, i64 addrspace(1)* undef store volatile i64 %arg2, i64 addrspace(1)* undef
ret void ret void
} }
; FIXME: Different ext load types on CI vs. VI ; FIXME: Different ext load types on CI vs. VI
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} }
; GCN-LABEL: {{^}}void_func_v32i32_v2i32_v2f32: ; GCN-LABEL: {{^}}void_func_v32i32_v2i32_v2f32:
; GCN-DAG: buffer_load_dword v[[LOAD_ARG1_0:[0-9]+]], off, s[0:3], s32 offset:4{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG1_0:[0-9]+]], off, s[0:3], s32 offset:4{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG1_1:[0-9]+]], off, s[0:3], s32 offset:8{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG1_1:[0-9]+]], off, s[0:3], s32 offset:8{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_0:[0-9]+]], off, s[0:3], s32 offset:12{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_0:[0-9]+]], off, s[0:3], s32 offset:12{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_1:[0-9]+]], off, s[0:3], s32 offset:16{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_1:[0-9]+]], off, s[0:3], s32 offset:16{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LOAD_ARG1_0]]:[[LOAD_ARG1_1]]{{\]}}, off ; GCN: buffer_store_dwordx2 v[[[LOAD_ARG1_0]]:[[LOAD_ARG1_1]]], off
; GCN: buffer_store_dwordx2 v{{\[}}[[LOAD_ARG2_0]]:[[LOAD_ARG2_1]]{{\]}}, off ; GCN: buffer_store_dwordx2 v[[[LOAD_ARG2_0]]:[[LOAD_ARG2_1]]], off
define void @void_func_v32i32_v2i32_v2f32(<32 x i32> %arg0, <2 x i32> %arg1, <2 x float> %arg2) #0 { define void @void_func_v32i32_v2i32_v2f32(<32 x i32> %arg0, <2 x i32> %arg1, <2 x float> %arg2) #0 {
store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef
store volatile <2 x i32> %arg1, <2 x i32> addrspace(1)* undef store volatile <2 x i32> %arg1, <2 x i32> addrspace(1)* undef
store volatile <2 x float> %arg2, <2 x float> addrspace(1)* undef store volatile <2 x float> %arg2, <2 x float> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}void_func_v32i32_v2i16_v2f16: ; GCN-LABEL: {{^}}void_func_v32i32_v2i16_v2f16:
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; GCN-DAG: buffer_load_dword v[[LOAD_ARG1_2:[0-9]+]], off, s[0:3], s32 offset:12{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG1_2:[0-9]+]], off, s[0:3], s32 offset:12{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG1_3:[0-9]+]], off, s[0:3], s32 offset:16{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG1_3:[0-9]+]], off, s[0:3], s32 offset:16{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_0:[0-9]+]], off, s[0:3], s32 offset:20{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_0:[0-9]+]], off, s[0:3], s32 offset:20{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_1:[0-9]+]], off, s[0:3], s32 offset:24{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_1:[0-9]+]], off, s[0:3], s32 offset:24{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_2:[0-9]+]], off, s[0:3], s32 offset:28{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_2:[0-9]+]], off, s[0:3], s32 offset:28{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_3:[0-9]+]], off, s[0:3], s32 offset:32{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_3:[0-9]+]], off, s[0:3], s32 offset:32{{$}}
; GCN: buffer_store_dwordx4 v{{\[}}[[LOAD_ARG1_0]]:[[LOAD_ARG1_3]]{{\]}}, off ; GCN: buffer_store_dwordx4 v[[[LOAD_ARG1_0]]:[[LOAD_ARG1_3]]], off
; GCN: buffer_store_dwordx4 v{{\[}}[[LOAD_ARG2_0]]:[[LOAD_ARG2_3]]{{\]}}, off ; GCN: buffer_store_dwordx4 v[[[LOAD_ARG2_0]]:[[LOAD_ARG2_3]]], off
define void @void_func_v32i32_v2i64_v2f64(<32 x i32> %arg0, <2 x i64> %arg1, <2 x double> %arg2) #0 { define void @void_func_v32i32_v2i64_v2f64(<32 x i32> %arg0, <2 x i64> %arg1, <2 x double> %arg2) #0 {
store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef
store volatile <2 x i64> %arg1, <2 x i64> addrspace(1)* undef store volatile <2 x i64> %arg1, <2 x i64> addrspace(1)* undef
store volatile <2 x double> %arg2, <2 x double> addrspace(1)* undef store volatile <2 x double> %arg2, <2 x double> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}void_func_v32i32_v4i32_v4f32: ; GCN-LABEL: {{^}}void_func_v32i32_v4i32_v4f32:
; GCN-DAG: buffer_load_dword v[[LOAD_ARG1_0:[0-9]+]], off, s[0:3], s32 offset:4{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG1_0:[0-9]+]], off, s[0:3], s32 offset:4{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG1_1:[0-9]+]], off, s[0:3], s32 offset:8{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG1_1:[0-9]+]], off, s[0:3], s32 offset:8{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG1_2:[0-9]+]], off, s[0:3], s32 offset:12{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG1_2:[0-9]+]], off, s[0:3], s32 offset:12{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG1_3:[0-9]+]], off, s[0:3], s32 offset:16{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG1_3:[0-9]+]], off, s[0:3], s32 offset:16{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_0:[0-9]+]], off, s[0:3], s32 offset:20{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_0:[0-9]+]], off, s[0:3], s32 offset:20{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_1:[0-9]+]], off, s[0:3], s32 offset:24{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_1:[0-9]+]], off, s[0:3], s32 offset:24{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_2:[0-9]+]], off, s[0:3], s32 offset:28{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_2:[0-9]+]], off, s[0:3], s32 offset:28{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_3:[0-9]+]], off, s[0:3], s32 offset:32{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_3:[0-9]+]], off, s[0:3], s32 offset:32{{$}}
; GCN: buffer_store_dwordx4 v{{\[}}[[LOAD_ARG1_0]]:[[LOAD_ARG1_3]]{{\]}}, off ; GCN: buffer_store_dwordx4 v[[[LOAD_ARG1_0]]:[[LOAD_ARG1_3]]], off
; GCN: buffer_store_dwordx4 v{{\[}}[[LOAD_ARG2_0]]:[[LOAD_ARG2_3]]{{\]}}, off ; GCN: buffer_store_dwordx4 v[[[LOAD_ARG2_0]]:[[LOAD_ARG2_3]]], off
define void @void_func_v32i32_v4i32_v4f32(<32 x i32> %arg0, <4 x i32> %arg1, <4 x float> %arg2) #0 { define void @void_func_v32i32_v4i32_v4f32(<32 x i32> %arg0, <4 x i32> %arg1, <4 x float> %arg2) #0 {
store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef
store volatile <4 x i32> %arg1, <4 x i32> addrspace(1)* undef store volatile <4 x i32> %arg1, <4 x i32> addrspace(1)* undef
store volatile <4 x float> %arg2, <4 x float> addrspace(1)* undef store volatile <4 x float> %arg2, <4 x float> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}void_func_v32i32_v8i32_v8f32: ; GCN-LABEL: {{^}}void_func_v32i32_v8i32_v8f32:
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; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_1:[0-9]+]], off, s[0:3], s32 offset:40{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_1:[0-9]+]], off, s[0:3], s32 offset:40{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_2:[0-9]+]], off, s[0:3], s32 offset:44{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_2:[0-9]+]], off, s[0:3], s32 offset:44{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_3:[0-9]+]], off, s[0:3], s32 offset:48{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_3:[0-9]+]], off, s[0:3], s32 offset:48{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_4:[0-9]+]], off, s[0:3], s32 offset:52{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_4:[0-9]+]], off, s[0:3], s32 offset:52{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_5:[0-9]+]], off, s[0:3], s32 offset:56{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_5:[0-9]+]], off, s[0:3], s32 offset:56{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_6:[0-9]+]], off, s[0:3], s32 offset:60{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_6:[0-9]+]], off, s[0:3], s32 offset:60{{$}}
; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_7:[0-9]+]], off, s[0:3], s32 offset:64{{$}} ; GCN-DAG: buffer_load_dword v[[LOAD_ARG2_7:[0-9]+]], off, s[0:3], s32 offset:64{{$}}
; GCN: buffer_store_dwordx4 v{{\[}}[[LOAD_ARG1_4]]:[[LOAD_ARG1_7]]{{\]}}, off ; GCN: buffer_store_dwordx4 v[[[LOAD_ARG1_4]]:[[LOAD_ARG1_7]]], off
; GCN: buffer_store_dwordx4 v{{\[}}[[LOAD_ARG1_0]]:[[LOAD_ARG1_3]]{{\]}}, off ; GCN: buffer_store_dwordx4 v[[[LOAD_ARG1_0]]:[[LOAD_ARG1_3]]], off
; GCN: buffer_store_dwordx4 v{{\[}}[[LOAD_ARG2_4]]:[[LOAD_ARG2_7]]{{\]}}, off ; GCN: buffer_store_dwordx4 v[[[LOAD_ARG2_4]]:[[LOAD_ARG2_7]]], off
; GCN: buffer_store_dwordx4 v{{\[}}[[LOAD_ARG2_0]]:[[LOAD_ARG2_3]]{{\]}}, off ; GCN: buffer_store_dwordx4 v[[[LOAD_ARG2_0]]:[[LOAD_ARG2_3]]], off
define void @void_func_v32i32_v8i32_v8f32(<32 x i32> %arg0, <8 x i32> %arg1, <8 x float> %arg2) #0 { define void @void_func_v32i32_v8i32_v8f32(<32 x i32> %arg0, <8 x i32> %arg1, <8 x float> %arg2) #0 {
store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef
store volatile <8 x i32> %arg1, <8 x i32> addrspace(1)* undef store volatile <8 x i32> %arg1, <8 x i32> addrspace(1)* undef
store volatile <8 x float> %arg2, <8 x float> addrspace(1)* undef store volatile <8 x float> %arg2, <8 x float> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}void_func_v32i32_v16i32_v16f32: ; GCN-LABEL: {{^}}void_func_v32i32_v16i32_v16f32:
▲ Show 20 Lines • Show All 95 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/function-call-relocs.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji < %s | FileCheck %s
declare void @func(i32 addrspace(1)* %out) declare void @func(i32 addrspace(1)* %out)
declare protected void @protected_func(i32 addrspace(1)* %out) declare protected void @protected_func(i32 addrspace(1)* %out)
declare hidden void @hidden_func(i32 addrspace(1)* %out) declare hidden void @hidden_func(i32 addrspace(1)* %out)
; CHECK-LABEL: call_func: ; CHECK-LABEL: call_func:
; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; CHECK: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; CHECK: s_add_u32 s[[GOT_ADDR_LO:[0-9]+]], s[[PC_LO]], func@gotpcrel32@lo+4 ; CHECK: s_add_u32 s[[GOT_ADDR_LO:[0-9]+]], s[[PC_LO]], func@gotpcrel32@lo+4
; CHECK: s_addc_u32 s[[GOT_ADDR_HI:[0-9]+]], s[[PC_HI]], func@gotpcrel32@hi+12 ; CHECK: s_addc_u32 s[[GOT_ADDR_HI:[0-9]+]], s[[PC_HI]], func@gotpcrel32@hi+12
; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOT_ADDR_LO]]:[[GOT_ADDR_HI]]{{\]}}, 0x0 ; CHECK: s_load_dwordx2 s[[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]], s[[[GOT_ADDR_LO]]:[[GOT_ADDR_HI]]], 0x0
; CHECK: s_swappc_b64 s{{\[}}{{[0-9]+:[0-9]+}}{{\]}}, s{{\[}}[[ADDR_LO]]:[[ADDR_HI]]{{\]}} ; CHECK: s_swappc_b64 s[{{[0-9]+:[0-9]+}}], s[[[ADDR_LO]]:[[ADDR_HI]]]
define amdgpu_kernel void @call_func(i32 addrspace(1)* %out) { define amdgpu_kernel void @call_func(i32 addrspace(1)* %out) {
call void @func(i32 addrspace(1)* %out) call void @func(i32 addrspace(1)* %out)
ret void ret void
} }
; CHECK-LABEL: call_protected_func: ; CHECK-LABEL: call_protected_func:
; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; CHECK: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], protected_func@rel32@lo+4 ; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], protected_func@rel32@lo+4
; CHECK: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], protected_func@rel32@hi+12 ; CHECK: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], protected_func@rel32@hi+12
; CHECK: s_swappc_b64 s{{\[}}{{[0-9]+:[0-9]+}}{{\]}}, s{{\[}}[[ADDR_LO]]:[[ADDR_HI]]{{\]}} ; CHECK: s_swappc_b64 s[{{[0-9]+:[0-9]+}}], s[[[ADDR_LO]]:[[ADDR_HI]]]
define amdgpu_kernel void @call_protected_func(i32 addrspace(1)* %out) { define amdgpu_kernel void @call_protected_func(i32 addrspace(1)* %out) {
call void @protected_func(i32 addrspace(1)* %out) call void @protected_func(i32 addrspace(1)* %out)
ret void ret void
} }
; CHECK-LABEL: call_hidden_func: ; CHECK-LABEL: call_hidden_func:
; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; CHECK: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], hidden_func@rel32@lo+4 ; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], hidden_func@rel32@lo+4
; CHECK: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], hidden_func@rel32@hi+12 ; CHECK: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], hidden_func@rel32@hi+12
; CHECK: s_swappc_b64 s{{\[}}{{[0-9]+:[0-9]+}}{{\]}}, s{{\[}}[[ADDR_LO]]:[[ADDR_HI]]{{\]}} ; CHECK: s_swappc_b64 s[{{[0-9]+:[0-9]+}}], s[[[ADDR_LO]]:[[ADDR_HI]]]
define amdgpu_kernel void @call_hidden_func(i32 addrspace(1)* %out) { define amdgpu_kernel void @call_hidden_func(i32 addrspace(1)* %out) {
call void @hidden_func(i32 addrspace(1)* %out) call void @hidden_func(i32 addrspace(1)* %out)
ret void ret void
} }
declare i64 @funci() declare i64 @funci()
; CHECK-LABEL: tail_call_func: ; CHECK-LABEL: tail_call_func:
; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; CHECK: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; CHECK: s_add_u32 s[[GOT_ADDR_LO:[0-9]+]], s[[PC_LO]], funci@gotpcrel32@lo+4 ; CHECK: s_add_u32 s[[GOT_ADDR_LO:[0-9]+]], s[[PC_LO]], funci@gotpcrel32@lo+4
; CHECK: s_addc_u32 s[[GOT_ADDR_HI:[0-9]+]], s[[PC_HI]], funci@gotpcrel32@hi+12 ; CHECK: s_addc_u32 s[[GOT_ADDR_HI:[0-9]+]], s[[PC_HI]], funci@gotpcrel32@hi+12
; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOT_ADDR_LO]]:[[GOT_ADDR_HI]]{{\]}}, 0x0 ; CHECK: s_load_dwordx2 s[[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]], s[[[GOT_ADDR_LO]]:[[GOT_ADDR_HI]]], 0x0
; CHECK: s_setpc_b64 s{{\[}}[[ADDR_LO]]:[[ADDR_HI]]{{\]}} ; CHECK: s_setpc_b64 s[[[ADDR_LO]]:[[ADDR_HI]]]
define i64 @tail_call_func() { define i64 @tail_call_func() {
%ret = tail call i64 @funci() %ret = tail call i64 @funci()
ret i64 %ret ret i64 %ret
} }

llvm/test/CodeGen/AMDGPU/global-constant.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=r600-- -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=R600 %s ; RUN: llc -mtriple=r600-- -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=R600 %s
@private1 = private unnamed_addr addrspace(4) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0] @private1 = private unnamed_addr addrspace(4) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0]
@private2 = private unnamed_addr addrspace(4) constant [4 x float] [float 4.0, float 5.0, float 6.0, float 7.0] @private2 = private unnamed_addr addrspace(4) constant [4 x float] [float 4.0, float 5.0, float 6.0, float 7.0]
@available_externally = available_externally addrspace(4) global [256 x i32] zeroinitializer @available_externally = available_externally addrspace(4) global [256 x i32] zeroinitializer
; GCN-LABEL: {{^}}private_test: ; GCN-LABEL: {{^}}private_test:
; GCN: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s[[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]]
; Non-R600 OSes use relocations. ; Non-R600 OSes use relocations.
; GCN: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1@rel32@lo+4 ; GCN: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1@rel32@lo+4
; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], private1@rel32@hi+12 ; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], private1@rel32@hi+12
; GCN: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s[[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]]
; GCN: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2@rel32@lo+4 ; GCN: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2@rel32@lo+4
; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], private2@rel32@hi+12 ; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], private2@rel32@hi+12
; R600-LABEL: private_test ; R600-LABEL: private_test
define amdgpu_kernel void @private_test(i32 %index, float addrspace(1)* %out) { define amdgpu_kernel void @private_test(i32 %index, float addrspace(1)* %out) {
%ptr = getelementptr [4 x float], [4 x float] addrspace(4) * @private1, i32 0, i32 %index %ptr = getelementptr [4 x float], [4 x float] addrspace(4) * @private1, i32 0, i32 %index
%val = load float, float addrspace(4)* %ptr %val = load float, float addrspace(4)* %ptr
store volatile float %val, float addrspace(1)* %out store volatile float %val, float addrspace(1)* %out
%ptr2 = getelementptr [4 x float], [4 x float] addrspace(4) * @private2, i32 0, i32 %index %ptr2 = getelementptr [4 x float], [4 x float] addrspace(4) * @private2, i32 0, i32 %index
%val2 = load float, float addrspace(4)* %ptr2 %val2 = load float, float addrspace(4)* %ptr2
store volatile float %val2, float addrspace(1)* %out store volatile float %val2, float addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}available_externally_test: ; GCN-LABEL: {{^}}available_externally_test:
; GCN: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s[[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]]
; GCN: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], available_externally@gotpcrel32@lo+4 ; GCN: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], available_externally@gotpcrel32@lo+4
; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], available_externally@gotpcrel32@hi+12 ; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], available_externally@gotpcrel32@hi+12
; R600-LABEL: available_externally_test ; R600-LABEL: available_externally_test
define amdgpu_kernel void @available_externally_test(i32 addrspace(1)* %out) { define amdgpu_kernel void @available_externally_test(i32 addrspace(1)* %out) {
%ptr = getelementptr [256 x i32], [256 x i32] addrspace(4)* @available_externally, i32 0, i32 1 %ptr = getelementptr [256 x i32], [256 x i32] addrspace(4)* @available_externally, i32 0, i32 1
%val = load i32, i32 addrspace(4)* %ptr %val = load i32, i32 addrspace(4)* %ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
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llvm/test/CodeGen/AMDGPU/global-extload-i16.ll

Show First 20 Lines • Show All 150 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @sextload_global_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(1)* nocapture %in) nounwind {
%ext = sext <64 x i16> %load to <64 x i32> %ext = sext <64 x i16> %load to <64 x i32>
store <64 x i32> %ext, <64 x i32> addrspace(1)* %out store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}zextload_global_i16_to_i64: ; FUNC-LABEL: {{^}}zextload_global_i16_to_i64:
; SI-DAG: buffer_load_ushort v[[LO:[0-9]+]], ; SI-DAG: buffer_load_ushort v[[LO:[0-9]+]],
; SI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; SI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] ; SI: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
define amdgpu_kernel void @zextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind { define amdgpu_kernel void @zextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind {
%a = load i16, i16 addrspace(1)* %in %a = load i16, i16 addrspace(1)* %in
%ext = zext i16 %a to i64 %ext = zext i16 %a to i64
store i64 %ext, i64 addrspace(1)* %out store i64 %ext, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}sextload_global_i16_to_i64: ; FUNC-LABEL: {{^}}sextload_global_i16_to_i64:
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llvm/test/CodeGen/AMDGPU/global-variable-relocs.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji < %s | FileCheck %s
@private = private addrspace(1) global [256 x i32] zeroinitializer @private = private addrspace(1) global [256 x i32] zeroinitializer
@internal = internal addrspace(1) global [256 x i32] zeroinitializer @internal = internal addrspace(1) global [256 x i32] zeroinitializer
@available_externally = available_externally addrspace(1) global [256 x i32] zeroinitializer @available_externally = available_externally addrspace(1) global [256 x i32] zeroinitializer
@linkonce = linkonce addrspace(1) global [256 x i32] zeroinitializer @linkonce = linkonce addrspace(1) global [256 x i32] zeroinitializer
@weak= weak addrspace(1) global [256 x i32] zeroinitializer @weak= weak addrspace(1) global [256 x i32] zeroinitializer
@common = common addrspace(1) global [256 x i32] zeroinitializer @common = common addrspace(1) global [256 x i32] zeroinitializer
@extern_weak = extern_weak addrspace(1) global [256 x i32] @extern_weak = extern_weak addrspace(1) global [256 x i32]
@linkonce_odr = linkonce_odr addrspace(1) global [256 x i32] zeroinitializer @linkonce_odr = linkonce_odr addrspace(1) global [256 x i32] zeroinitializer
@weak_odr = weak_odr addrspace(1) global [256 x i32] zeroinitializer @weak_odr = weak_odr addrspace(1) global [256 x i32] zeroinitializer
@external = external addrspace(1) global [256 x i32] @external = external addrspace(1) global [256 x i32]
@external_w_init = addrspace(1) global [256 x i32] zeroinitializer @external_w_init = addrspace(1) global [256 x i32] zeroinitializer
; CHECK-LABEL: private_test: ; CHECK-LABEL: private_test:
; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; CHECK: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], private@rel32@lo+8 ; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], private@rel32@lo+8
; CHECK: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], private@rel32@hi+16 ; CHECK: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], private@rel32@hi+16
; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[ADDR_LO]] ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[ADDR_LO]]
; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[ADDR_HI]] ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[ADDR_HI]]
; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} ; CHECK: flat_load_dword v{{[0-9]+}}, v[[[V_LO]]:[[V_HI]]]
define amdgpu_kernel void @private_test(i32 addrspace(1)* %out) { define amdgpu_kernel void @private_test(i32 addrspace(1)* %out) {
%ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @private, i32 0, i32 1 %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @private, i32 0, i32 1
%val = load i32, i32 addrspace(1)* %ptr %val = load i32, i32 addrspace(1)* %ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: internal_test: ; CHECK-LABEL: internal_test:
; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; CHECK: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], internal@rel32@lo+8 ; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], internal@rel32@lo+8
; CHECK: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], internal@rel32@hi+16 ; CHECK: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], internal@rel32@hi+16
; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[ADDR_LO]] ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[ADDR_LO]]
; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[ADDR_HI]] ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[ADDR_HI]]
; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} ; CHECK: flat_load_dword v{{[0-9]+}}, v[[[V_LO]]:[[V_HI]]]
define amdgpu_kernel void @internal_test(i32 addrspace(1)* %out) { define amdgpu_kernel void @internal_test(i32 addrspace(1)* %out) {
%ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @internal, i32 0, i32 1 %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @internal, i32 0, i32 1
%val = load i32, i32 addrspace(1)* %ptr %val = load i32, i32 addrspace(1)* %ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: available_externally_test: ; CHECK-LABEL: available_externally_test:
; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; CHECK: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], available_externally@gotpcrel32@lo+4 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], available_externally@gotpcrel32@lo+4
; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], available_externally@gotpcrel32@hi+12 ; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], available_externally@gotpcrel32@hi+12
; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 ; CHECK: s_load_dwordx2 s[[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]], s[[[GOTADDR_LO]]:[[GOTADDR_HI]]], 0x0
; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 ; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0
; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]]
; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]]
; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} ; CHECK: flat_load_dword v{{[0-9]+}}, v[[[V_LO]]:[[V_HI]]]
define amdgpu_kernel void @available_externally_test(i32 addrspace(1)* %out) { define amdgpu_kernel void @available_externally_test(i32 addrspace(1)* %out) {
%ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @available_externally, i32 0, i32 1 %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @available_externally, i32 0, i32 1
%val = load i32, i32 addrspace(1)* %ptr %val = load i32, i32 addrspace(1)* %ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: linkonce_test: ; CHECK-LABEL: linkonce_test:
; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; CHECK: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], linkonce@gotpcrel32@lo+4 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], linkonce@gotpcrel32@lo+4
; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], linkonce@gotpcrel32@hi+12 ; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], linkonce@gotpcrel32@hi+12
; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 ; CHECK: s_load_dwordx2 s[[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]], s[[[GOTADDR_LO]]:[[GOTADDR_HI]]], 0x0
; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 ; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0
; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]]
; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]]
; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} ; CHECK: flat_load_dword v{{[0-9]+}}, v[[[V_LO]]:[[V_HI]]]
define amdgpu_kernel void @linkonce_test(i32 addrspace(1)* %out) { define amdgpu_kernel void @linkonce_test(i32 addrspace(1)* %out) {
%ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @linkonce, i32 0, i32 1 %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @linkonce, i32 0, i32 1
%val = load i32, i32 addrspace(1)* %ptr %val = load i32, i32 addrspace(1)* %ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: weak_test: ; CHECK-LABEL: weak_test:
; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; CHECK: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], weak@gotpcrel32@lo+4 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], weak@gotpcrel32@lo+4
; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], weak@gotpcrel32@hi+12 ; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], weak@gotpcrel32@hi+12
; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 ; CHECK: s_load_dwordx2 s[[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]], s[[[GOTADDR_LO]]:[[GOTADDR_HI]]], 0x0
; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 ; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0
; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]]
; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]]
; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} ; CHECK: flat_load_dword v{{[0-9]+}}, v[[[V_LO]]:[[V_HI]]]
define amdgpu_kernel void @weak_test(i32 addrspace(1)* %out) { define amdgpu_kernel void @weak_test(i32 addrspace(1)* %out) {
%ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @weak, i32 0, i32 1 %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @weak, i32 0, i32 1
%val = load i32, i32 addrspace(1)* %ptr %val = load i32, i32 addrspace(1)* %ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: common_test: ; CHECK-LABEL: common_test:
; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; CHECK: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], common@gotpcrel32@lo+4 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], common@gotpcrel32@lo+4
; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], common@gotpcrel32@hi+12 ; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], common@gotpcrel32@hi+12
; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 ; CHECK: s_load_dwordx2 s[[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]], s[[[GOTADDR_LO]]:[[GOTADDR_HI]]], 0x0
; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 ; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0
; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]]
; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]]
; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} ; CHECK: flat_load_dword v{{[0-9]+}}, v[[[V_LO]]:[[V_HI]]]
define amdgpu_kernel void @common_test(i32 addrspace(1)* %out) { define amdgpu_kernel void @common_test(i32 addrspace(1)* %out) {
%ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @common, i32 0, i32 1 %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @common, i32 0, i32 1
%val = load i32, i32 addrspace(1)* %ptr %val = load i32, i32 addrspace(1)* %ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: extern_weak_test: ; CHECK-LABEL: extern_weak_test:
; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; CHECK: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], extern_weak@gotpcrel32@lo+4 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], extern_weak@gotpcrel32@lo+4
; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], extern_weak@gotpcrel32@hi+12 ; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], extern_weak@gotpcrel32@hi+12
; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 ; CHECK: s_load_dwordx2 s[[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]], s[[[GOTADDR_LO]]:[[GOTADDR_HI]]], 0x0
; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 ; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0
; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]]
; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]]
; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} ; CHECK: flat_load_dword v{{[0-9]+}}, v[[[V_LO]]:[[V_HI]]]
define amdgpu_kernel void @extern_weak_test(i32 addrspace(1)* %out) { define amdgpu_kernel void @extern_weak_test(i32 addrspace(1)* %out) {
%ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @extern_weak, i32 0, i32 1 %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @extern_weak, i32 0, i32 1
%val = load i32, i32 addrspace(1)* %ptr %val = load i32, i32 addrspace(1)* %ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: linkonce_odr_test: ; CHECK-LABEL: linkonce_odr_test:
; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; CHECK: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], linkonce_odr@gotpcrel32@lo+4 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], linkonce_odr@gotpcrel32@lo+4
; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], linkonce_odr@gotpcrel32@hi+12 ; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], linkonce_odr@gotpcrel32@hi+12
; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 ; CHECK: s_load_dwordx2 s[[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]], s[[[GOTADDR_LO]]:[[GOTADDR_HI]]], 0x0
; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 ; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0
; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]]
; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]]
; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} ; CHECK: flat_load_dword v{{[0-9]+}}, v[[[V_LO]]:[[V_HI]]]
define amdgpu_kernel void @linkonce_odr_test(i32 addrspace(1)* %out) { define amdgpu_kernel void @linkonce_odr_test(i32 addrspace(1)* %out) {
%ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @linkonce_odr, i32 0, i32 1 %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @linkonce_odr, i32 0, i32 1
%val = load i32, i32 addrspace(1)* %ptr %val = load i32, i32 addrspace(1)* %ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: weak_odr_test: ; CHECK-LABEL: weak_odr_test:
; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; CHECK: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], weak_odr@gotpcrel32@lo+4 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], weak_odr@gotpcrel32@lo+4
; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], weak_odr@gotpcrel32@hi+12 ; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], weak_odr@gotpcrel32@hi+12
; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 ; CHECK: s_load_dwordx2 s[[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]], s[[[GOTADDR_LO]]:[[GOTADDR_HI]]], 0x0
; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 ; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0
; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]]
; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]]
; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} ; CHECK: flat_load_dword v{{[0-9]+}}, v[[[V_LO]]:[[V_HI]]]
define amdgpu_kernel void @weak_odr_test(i32 addrspace(1)* %out) { define amdgpu_kernel void @weak_odr_test(i32 addrspace(1)* %out) {
%ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @weak_odr, i32 0, i32 1 %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @weak_odr, i32 0, i32 1
%val = load i32, i32 addrspace(1)* %ptr %val = load i32, i32 addrspace(1)* %ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: external_test: ; CHECK-LABEL: external_test:
; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; CHECK: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], external@gotpcrel32@lo+4 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], external@gotpcrel32@lo+4
; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], external@gotpcrel32@hi+12 ; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], external@gotpcrel32@hi+12
; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 ; CHECK: s_load_dwordx2 s[[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]], s[[[GOTADDR_LO]]:[[GOTADDR_HI]]], 0x0
; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 ; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0
; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]]
; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]]
; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} ; CHECK: flat_load_dword v{{[0-9]+}}, v[[[V_LO]]:[[V_HI]]]
define amdgpu_kernel void @external_test(i32 addrspace(1)* %out) { define amdgpu_kernel void @external_test(i32 addrspace(1)* %out) {
%ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @external, i32 0, i32 1 %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @external, i32 0, i32 1
%val = load i32, i32 addrspace(1)* %ptr %val = load i32, i32 addrspace(1)* %ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: external_w_init_test: ; CHECK-LABEL: external_w_init_test:
; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; CHECK: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], external_w_init@gotpcrel32@lo+4 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], external_w_init@gotpcrel32@lo+4
; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], external_w_init@gotpcrel32@hi+12 ; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], external_w_init@gotpcrel32@hi+12
; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 ; CHECK: s_load_dwordx2 s[[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]], s[[[GOTADDR_LO]]:[[GOTADDR_HI]]], 0x0
; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 ; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0
; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]]
; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]]
; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} ; CHECK: flat_load_dword v{{[0-9]+}}, v[[[V_LO]]:[[V_HI]]]
define amdgpu_kernel void @external_w_init_test(i32 addrspace(1)* %out) { define amdgpu_kernel void @external_w_init_test(i32 addrspace(1)* %out) {
%ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @external_w_init, i32 0, i32 1 %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @external_w_init, i32 0, i32 1
%val = load i32, i32 addrspace(1)* %ptr %val = load i32, i32 addrspace(1)* %ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK: .local private ; CHECK: .local private
; CHECK: .local internal ; CHECK: .local internal
; CHECK: .weak linkonce ; CHECK: .weak linkonce
; CHECK: .weak weak ; CHECK: .weak weak
; CHECK: .weak linkonce_odr ; CHECK: .weak linkonce_odr
; CHECK: .weak weak_odr ; CHECK: .weak weak_odr
; CHECK-NOT: external{{$}} ; CHECK-NOT: external{{$}}
; CHECK: .globl external_w_init ; CHECK: .globl external_w_init

llvm/test/CodeGen/AMDGPU/global_atomics.ll

Show All 31 Linesentry:
%gep = getelementptr i32, i32 addrspace(1)* %out, i64 9000 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 9000
%val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32_huge_offset: ; GCN-LABEL: {{^}}atomic_add_i32_huge_offset:
; SI-DAG: v_mov_b32_e32 v[[PTRLO:[0-9]+]], 0xdeac ; SI-DAG: v_mov_b32_e32 v[[PTRLO:[0-9]+]], 0xdeac
; SI-DAG: v_mov_b32_e32 v[[PTRHI:[0-9]+]], 0xabcd ; SI-DAG: v_mov_b32_e32 v[[PTRHI:[0-9]+]], 0xabcd
; SI: buffer_atomic_add v{{[0-9]+}}, v{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} ; SI: buffer_atomic_add v{{[0-9]+}}, v[[[PTRLO]]:[[PTRHI]]], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
; VI: flat_atomic_add ; VI: flat_atomic_add
; GFX9: s_add_u32 s[[LOW_K:[0-9]+]], s{{[0-9]+}}, 0xdeac ; GFX9: s_add_u32 s[[LOW_K:[0-9]+]], s{{[0-9]+}}, 0xdeac
; GFX9: s_addc_u32 s[[HIGH_K:[0-9]+]], s{{[0-9]+}}, 0xabcd ; GFX9: s_addc_u32 s[[HIGH_K:[0-9]+]], s{{[0-9]+}}, 0xabcd
; GFX9: global_atomic_add v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[LOW_K]]:[[HIGH_K]]]{{$}} ; GFX9: global_atomic_add v{{[0-9]+}}, v{{[0-9]+}}, s[[[LOW_K]]:[[HIGH_K]]]{{$}}
define amdgpu_kernel void @atomic_add_i32_huge_offset(i32 addrspace(1)* %out, i32 %in) { define amdgpu_kernel void @atomic_add_i32_huge_offset(i32 addrspace(1)* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(1)* %out, i64 47224239175595 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 47224239175595
%val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst
ret void ret void
} }
▲ Show 20 Lines • Show All 891 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @atomic_cmpxchg_i32_offset(i32 addrspace(1)* %out, i32 %in, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_offset(i32 addrspace(1)* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4
%val = cmpxchg volatile i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_offset:
; SIVI: buffer_atomic_cmpswap v{{\[}}[[RET:[0-9]+]]{{:[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} ; SIVI: buffer_atomic_cmpswap v[[[RET:[0-9]+]]{{:[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}}
; SIVI: buffer_store_dword v[[RET]] ; SIVI: buffer_store_dword v[[RET]]
; GFX9: global_atomic_cmpswap [[RET:v[0-9]+]], v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}] offset:16 glc{{$}} ; GFX9: global_atomic_cmpswap [[RET:v[0-9]+]], v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}] offset:16 glc{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4
%val = cmpxchg volatile i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst
%extract0 = extractvalue { i32, i1 } %val, 0 %extract0 = extractvalue { i32, i1 } %val, 0
Show All 10 Lines
entry: entry:
%ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4
%val = cmpxchg volatile i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64_offset:
; SI: buffer_atomic_cmpswap v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} ; SI: buffer_atomic_cmpswap v[[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}}
; VI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; VI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; SIVI: buffer_store_dword v[[RET]] ; SIVI: buffer_store_dword v[[RET]]
; GFX9: global_atomic_cmpswap v[[RET:[0-9]+]], v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] offset:16 glc{{$}} ; GFX9: global_atomic_cmpswap v[[RET:[0-9]+]], v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] offset:16 glc{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index, i32 %old) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4
Show All 9 Lines
; GFX9: global_atomic_cmpswap v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]{{$}} ; GFX9: global_atomic_cmpswap v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i32(i32 addrspace(1)* %out, i32 %in, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32(i32 addrspace(1)* %out, i32 %in, i32 %old) {
entry: entry:
%val = cmpxchg volatile i32 addrspace(1)* %out, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32 addrspace(1)* %out, i32 %old, i32 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret:
; SIVI: buffer_atomic_cmpswap v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc ; SIVI: buffer_atomic_cmpswap v[[[RET:[0-9]+]]:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
; SIVI: buffer_store_dword v[[RET]] ; SIVI: buffer_store_dword v[[RET]]
; GFX9: global_atomic_cmpswap [[RET:v[0-9]+]], v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} ; GFX9: global_atomic_cmpswap [[RET:v[0-9]+]], v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i32 %old) {
entry: entry:
%val = cmpxchg volatile i32 addrspace(1)* %out, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32 addrspace(1)* %out, i32 %old, i32 %in seq_cst seq_cst
%extract0 = extractvalue { i32, i1 } %val, 0 %extract0 = extractvalue { i32, i1 } %val, 0
store i32 %extract0, i32 addrspace(1)* %out2 store i32 %extract0, i32 addrspace(1)* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_addr64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_addr64:
; SI: buffer_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} ; SI: buffer_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
; VI: flat_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}} ; VI: flat_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}}
; GFX9: global_atomic_cmpswap v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]{{$}} ; GFX9: global_atomic_cmpswap v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index, i32 %old) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
%val = cmpxchg volatile i32 addrspace(1)* %ptr, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32 addrspace(1)* %ptr, i32 %old, i32 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64:
; SI: buffer_atomic_cmpswap v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} ; SI: buffer_atomic_cmpswap v[[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
; VI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; VI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; SIVI: buffer_store_dword v[[RET]] ; SIVI: buffer_store_dword v[[RET]]
; GFX9: global_atomic_cmpswap v[[RET:[0-9]+]], v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] glc{{$}} ; GFX9: global_atomic_cmpswap v[[RET:[0-9]+]], v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] glc{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index, i32 %old) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
%val = cmpxchg volatile i32 addrspace(1)* %ptr, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32 addrspace(1)* %ptr, i32 %old, i32 %in seq_cst seq_cst
▲ Show 20 Lines • Show All 279 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll

Show First 20 Lines • Show All 995 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @atomic_cmpxchg_i64_soffset(i64 addrspace(1)* %out, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_soffset(i64 addrspace(1)* %out, i64 %in, i64 %old) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(1)* %out, i64 9000 %gep = getelementptr i64, i64 addrspace(1)* %out, i64 9000
%val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_offset:
; CIVI: buffer_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]{{:[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}} ; CIVI: buffer_atomic_cmpswap_x2 v[[[RET:[0-9]+]]{{:[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}}
; CIVI: buffer_store_dwordx2 v{{\[}}[[RET]]: ; CIVI: buffer_store_dwordx2 v[[[RET]]:
; GFX9: global_atomic_cmpswap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}} offset:32 glc{{$}} ; GFX9: global_atomic_cmpswap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}} offset:32 glc{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64_ret_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_ret_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %old) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4
%val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst
%extract0 = extractvalue { i64, i1 } %val, 0 %extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, i64 addrspace(1)* %out2 store i64 %extract0, i64 addrspace(1)* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64_offset:
; CI: buffer_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32{{$}} ; CI: buffer_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32{{$}}
; VI: flat_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; VI: flat_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GFX9: global_atomic_cmpswap_x2 v{{[0-9]+}}, v[{{[0-9]+\:[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}] offset:32{{$}} ; GFX9: global_atomic_cmpswap_x2 v{{[0-9]+}}, v[{{[0-9]+\:[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}] offset:32{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(i64 addrspace(1)* %out, i64 %in, i64 %index, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(i64 addrspace(1)* %out, i64 %in, i64 %index, i64 %old) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4
%val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64_offset:
; CI: buffer_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}} ; CI: buffer_atomic_cmpswap_x2 v[[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}}
; VI: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; VI: flat_atomic_cmpswap_x2 v[[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; CIVI: buffer_store_dwordx2 v{{\[}}[[RET]]: ; CIVI: buffer_store_dwordx2 v[[[RET]]:
; GFX9: global_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] offset:32 glc{{$}} ; GFX9: global_atomic_cmpswap_x2 v[[[RET:[0-9]+]]:{{[0-9]+\]}}, v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] offset:32 glc{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index, i64 %old) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4
%val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst
%extract0 = extractvalue { i64, i1 } %val, 0 %extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, i64 addrspace(1)* %out2 store i64 %extract0, i64 addrspace(1)* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64:
; CIVI: buffer_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} ; CIVI: buffer_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
; GFX9: global_atomic_cmpswap_x2 v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]{{$}} ; GFX9: global_atomic_cmpswap_x2 v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64(i64 addrspace(1)* %out, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64(i64 addrspace(1)* %out, i64 %in, i64 %old) {
entry: entry:
%val = cmpxchg volatile i64 addrspace(1)* %out, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64 addrspace(1)* %out, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret:
; CIVI: buffer_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc ; CIVI: buffer_atomic_cmpswap_x2 v[[[RET:[0-9]+]]:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
; CIVI: buffer_store_dwordx2 v{{\[}}[[RET]]: ; CIVI: buffer_store_dwordx2 v[[[RET]]:
; GFX9: global_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+:[0-9]+}}] glc{{$}} ; GFX9: global_atomic_cmpswap_x2 v[[[RET:[0-9]+]]:{{[0-9]+\]}}, v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+:[0-9]+}}] glc{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64_ret(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_ret(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %old) {
entry: entry:
%val = cmpxchg volatile i64 addrspace(1)* %out, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64 addrspace(1)* %out, i64 %old, i64 %in seq_cst seq_cst
%extract0 = extractvalue { i64, i1 } %val, 0 %extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, i64 addrspace(1)* %out2 store i64 %extract0, i64 addrspace(1)* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64:
; CI: buffer_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} ; CI: buffer_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
; VI: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}} ; VI: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}}
; GFX9: global_atomic_cmpswap_x2 v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]{{$}} ; GFX9: global_atomic_cmpswap_x2 v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(i64 addrspace(1)* %out, i64 %in, i64 %index, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(i64 addrspace(1)* %out, i64 %in, i64 %index, i64 %old) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index
%val = cmpxchg volatile i64 addrspace(1)* %ptr, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64 addrspace(1)* %ptr, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64:
; CI: buffer_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} ; CI: buffer_atomic_cmpswap_x2 v[[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
; VI: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; VI: flat_atomic_cmpswap_x2 v[[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; CIVI: buffer_store_dwordx2 v{{\[}}[[RET]]: ; CIVI: buffer_store_dwordx2 v[[[RET]]:
; GFX9: global_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] glc{{$}} ; GFX9: global_atomic_cmpswap_x2 v[[[RET:[0-9]+]]:{{[0-9]+\]}}, v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] glc{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index, i64 %old) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index
%val = cmpxchg volatile i64 addrspace(1)* %ptr, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64 addrspace(1)* %ptr, i64 %old, i64 %in seq_cst seq_cst
%extract0 = extractvalue { i64, i1 } %val, 0 %extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, i64 addrspace(1)* %out2 store i64 %extract0, i64 addrspace(1)* %out2
ret void ret void
} }
Show All 10 Linesentry:
%val = load atomic i64, i64 addrspace(1)* %gep seq_cst, align 8 %val = load atomic i64, i64 addrspace(1)* %gep seq_cst, align 8
store i64 %val, i64 addrspace(1)* %out store i64 %val, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_load_i64_neg_offset: ; GCN-LABEL: {{^}}atomic_load_i64_neg_offset:
; CI: v_mov_b32_e32 v[[LO:[0-9]+]], 0xffffffe0 ; CI: v_mov_b32_e32 v[[LO:[0-9]+]], 0xffffffe0
; CI: v_mov_b32_e32 v[[HI:[0-9]+]], -1 ; CI: v_mov_b32_e32 v[[HI:[0-9]+]], -1
; CI: buffer_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]{{\]}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} ; CI: buffer_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[[[LO]]:[[HI]]], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
; VI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0xffffffe0 ; VI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0xffffffe0
; VI-NEXT: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, -1 ; VI-NEXT: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, -1
; VI: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} ; VI: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
; CIVI: buffer_store_dwordx2 [[RET]] ; CIVI: buffer_store_dwordx2 [[RET]]
; GFX9: global_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] offset:-32 glc{{$}} ; GFX9: global_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] offset:-32 glc{{$}}
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llvm/test/CodeGen/AMDGPU/global_smrd.ll

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Linesbb:
%tmp17 = getelementptr inbounds float, float addrspace(1)* %arg1, i32 %tmp %tmp17 = getelementptr inbounds float, float addrspace(1)* %arg1, i32 %tmp
store float %tmp16, float addrspace(1)* %tmp17, align 4, !tbaa !8 store float %tmp16, float addrspace(1)* %tmp17, align 4, !tbaa !8
ret void ret void
} }
; uniform load dominated by no-alias store - scalarize ; uniform load dominated by no-alias store - scalarize
; CHECK-LABEL: @no_memdep_alias_arg ; CHECK-LABEL: @no_memdep_alias_arg
; CHECK: s_load_dwordx2 s{{\[}}[[IN_LO:[0-9]+]]:[[IN_HI:[0-9]+]]], s[4:5], 0x0 ; CHECK: s_load_dwordx2 s[[[IN_LO:[0-9]+]]:[[IN_HI:[0-9]+]]], s[4:5], 0x0
; CHECK: s_load_dword [[SVAL:s[0-9]+]], s{{\[}}[[IN_LO]]:[[IN_HI]]], 0x0 ; CHECK: s_load_dword [[SVAL:s[0-9]+]], s[[[IN_LO]]:[[IN_HI]]], 0x0
; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[SVAL]] ; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[SVAL]]
; CHECK: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[VVAL]] ; CHECK: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[VVAL]]
define amdgpu_kernel void @no_memdep_alias_arg(i32 addrspace(1)* noalias %in, [8 x i32], i32 addrspace(1)* %out0, [8 x i32], i32 addrspace(1)* %out1) { define amdgpu_kernel void @no_memdep_alias_arg(i32 addrspace(1)* noalias %in, [8 x i32], i32 addrspace(1)* %out0, [8 x i32], i32 addrspace(1)* %out1) {
store i32 0, i32 addrspace(1)* %out0 store i32 0, i32 addrspace(1)* %out0
%val = load i32, i32 addrspace(1)* %in %val = load i32, i32 addrspace(1)* %in
store i32 %val, i32 addrspace(1)* %out1 store i32 %val, i32 addrspace(1)* %out1
ret void ret void
Show All 31 Lines
} }
; uniform load from global array dominated by alias store ; uniform load from global array dominated by alias store
; CHECK-LABEL: @global_array_alias_store ; CHECK-LABEL: @global_array_alias_store
; CHECK: flat_store_dword ; CHECK: flat_store_dword
; CHECK: v_mov_b32_e32 v[[ADDR_LO:[0-9]+]], s{{[0-9]+}} ; CHECK: v_mov_b32_e32 v[[ADDR_LO:[0-9]+]], s{{[0-9]+}}
; CHECK: v_mov_b32_e32 v[[ADDR_HI:[0-9]+]], s{{[0-9]+}} ; CHECK: v_mov_b32_e32 v[[ADDR_HI:[0-9]+]], s{{[0-9]+}}
; CHECK: flat_load_dwordx2 [[A_ADDR:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[ADDR_LO]]:[[ADDR_HI]]{{\]}} ; CHECK: flat_load_dwordx2 [[A_ADDR:v\[[0-9]+:[0-9]+\]]], v[[[ADDR_LO]]:[[ADDR_HI]]]
; CHECK: flat_load_dword [[VVAL:v[0-9]+]], [[A_ADDR]] ; CHECK: flat_load_dword [[VVAL:v[0-9]+]], [[A_ADDR]]
; CHECK: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[VVAL]] ; CHECK: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[VVAL]]
define amdgpu_kernel void @global_array_alias_store(i32 addrspace(1)* nocapture %out, [8 x i32], i32 %n) { define amdgpu_kernel void @global_array_alias_store(i32 addrspace(1)* nocapture %out, [8 x i32], i32 %n) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(1) * %out, i32 %n %gep = getelementptr i32, i32 addrspace(1) * %out, i32 %n
store i32 12, i32 addrspace(1) * %gep store i32 12, i32 addrspace(1) * %gep
%load0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* @A, align 4 %load0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* @A, align 4
%load1 = load i32, i32 addrspace(1)* %load0, align 4 %load1 = load i32, i32 addrspace(1)* %load0, align 4
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llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @illegal_agpr_to_sgpr_copy_i32() #1 {
%agpr = call i32 asm sideeffect "; def $0", "=${a1}"() %agpr = call i32 asm sideeffect "; def $0", "=${a1}"()
call void asm sideeffect "; use $0", "${s9}"(i32 %agpr) call void asm sideeffect "; use $0", "${s9}"(i32 %agpr)
ret void ret void
} }
; ERR: error: <unknown>:0:0: in function illegal_agpr_to_sgpr_copy_v2i32 void (): illegal SGPR to VGPR copy ; ERR: error: <unknown>:0:0: in function illegal_agpr_to_sgpr_copy_v2i32 void (): illegal SGPR to VGPR copy
; GCN-DAG: v_accvgpr_read_b32 v[[COPY1L:[0-9]+]], a0 ; GCN-DAG: v_accvgpr_read_b32 v[[COPY1L:[0-9]+]], a0
; GCN-DAG: v_accvgpr_read_b32 v[[COPY1H:[0-9]+]], a1 ; GCN-DAG: v_accvgpr_read_b32 v[[COPY1H:[0-9]+]], a1
; GCN: ; illegal copy v{{\[}}[[COPY1L]]:[[COPY1H]]] to s[10:11] ; GCN: ; illegal copy v[[[COPY1L]]:[[COPY1H]]] to s[10:11]
define amdgpu_kernel void @illegal_agpr_to_sgpr_copy_v2i32() #1 { define amdgpu_kernel void @illegal_agpr_to_sgpr_copy_v2i32() #1 {
%vgpr = call <2 x i32> asm sideeffect "; def $0", "=${a[0:1]}"() %vgpr = call <2 x i32> asm sideeffect "; def $0", "=${a[0:1]}"()
call void asm sideeffect "; use $0", "${s[10:11]}"(<2 x i32> %vgpr) call void asm sideeffect "; use $0", "${s[10:11]}"(<2 x i32> %vgpr)
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind "target-cpu"="gfx908" } attributes #1 = { nounwind "target-cpu"="gfx908" }

llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll

; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
declare <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) declare <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)
; GCN-LABEL: {{^}}water_loop_rsrc: ; GCN-LABEL: {{^}}water_loop_rsrc:
; GCN: [[RSRC_LOOP:.L[a-zA-Z0-9_]+]]: ; =>This Inner Loop Header: Depth=1 ; GCN: [[RSRC_LOOP:.L[a-zA-Z0-9_]+]]: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]]
; GCN-NEXT: v_cmp_eq_u64_e32 [[CMP0:vcc]], s{{\[}}[[SREG0]]:[[SREG1]]{{\]}}, v{{\[}}[[VREG0]]:[[VREG1]]{{\]}} ; GCN-NEXT: v_cmp_eq_u64_e32 [[CMP0:vcc]], s[[[SREG0]]:[[SREG1]]], v[[[VREG0]]:[[VREG1]]]
; GCN-NEXT: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SREG2]]:[[SREG3]]{{\]}}, v{{\[}}[[VREG2]]:[[VREG3]]{{\]}} ; GCN-NEXT: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s[[[SREG2]]:[[SREG3]]], v[[[VREG2]]:[[VREG3]]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG4:[0-9]+]], v[[VREG4:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG4:[0-9]+]], v[[VREG4:[0-9]+]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG5:[0-9]+]], v[[VREG5:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG5:[0-9]+]], v[[VREG5:[0-9]+]]
; GCN-NEXT: s_and_b64 [[AND0:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]] ; GCN-NEXT: s_and_b64 [[AND0:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]]
; GCN-NEXT: v_cmp_eq_u64_e32 [[CMP2:vcc]], s{{\[}}[[SREG4]]:[[SREG5]]{{\]}}, v{{\[}}[[VREG4]]:[[VREG5]]{{\]}} ; GCN-NEXT: v_cmp_eq_u64_e32 [[CMP2:vcc]], s[[[SREG4]]:[[SREG5]]], v[[[VREG4]]:[[VREG5]]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG6:[0-9]+]], v[[VREG6:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG6:[0-9]+]], v[[VREG6:[0-9]+]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG7:[0-9]+]], v[[VREG7:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG7:[0-9]+]], v[[VREG7:[0-9]+]]
; GCN-NEXT: v_cmp_eq_u64_e64 [[CMP3:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SREG6]]:[[SREG7]]{{\]}}, v{{\[}}[[VREG6]]:[[VREG7]]{{\]}} ; GCN-NEXT: v_cmp_eq_u64_e64 [[CMP3:s\[[0-9]+:[0-9]+\]]], s[[[SREG6]]:[[SREG7]]], v[[[VREG6]]:[[VREG7]]]
; GCN-NEXT: s_and_b64 [[AND1:s\[[0-9]+:[0-9]+\]]], [[AND0]], [[CMP2]] ; GCN-NEXT: s_and_b64 [[AND1:s\[[0-9]+:[0-9]+\]]], [[AND0]], [[CMP2]]
; GCN-NEXT: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[AND1]], [[CMP3]] ; GCN-NEXT: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[AND1]], [[CMP3]]
; GCN-NEXT: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]] ; GCN-NEXT: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; GCN-NEXT: s_nop 0 ; GCN-NEXT: s_nop 0
; GCN-NEXT: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, s{{\[}}[[SREG0]]:[[SREG7]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 ; GCN-NEXT: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, s[[[SREG0]]:[[SREG7]]], {{s\[[0-9]+:[0-9]+\]}} dmask:0x1
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GCN-NEXT: ; implicit-def: $vgpr8_vgpr9 ; GCN-NEXT: ; implicit-def: $vgpr8_vgpr9
; GCN-NEXT: s_xor_b64 exec, exec, [[SAVE]] ; GCN-NEXT: s_xor_b64 exec, exec, [[SAVE]]
; GCN-NEXT: s_cbranch_execnz [[RSRC_LOOP]] ; GCN-NEXT: s_cbranch_execnz [[RSRC_LOOP]]
define amdgpu_ps <4 x float> @water_loop_rsrc(<8 x i32> %rsrc, <4 x i32> inreg %samp, float %s, float %t) { define amdgpu_ps <4 x float> @water_loop_rsrc(<8 x i32> %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
; GCN-LABEL: {{^}}water_loop_samp: ; GCN-LABEL: {{^}}water_loop_samp:
; GCN: [[SAMP_LOOP:.L[a-zA-Z0-9_]+]]: ; =>This Inner Loop Header: Depth=1 ; GCN: [[SAMP_LOOP:.L[a-zA-Z0-9_]+]]: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]]
; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]] ; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]]
; GCN-NEXT: v_cmp_eq_u64_e32 [[CMP0:vcc]], s{{\[}}[[SREG0]]:[[SREG1]]{{\]}}, v{{\[}}[[VREG0]]:[[VREG1]]{{\]}} ; GCN-NEXT: v_cmp_eq_u64_e32 [[CMP0:vcc]], s[[[SREG0]]:[[SREG1]]], v[[[VREG0]]:[[VREG1]]]
; GCN-NEXT: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SREG2]]:[[SREG3]]{{\]}}, v{{\[}}[[VREG2]]:[[VREG3]]{{\]}} ; GCN-NEXT: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s[[[SREG2]]:[[SREG3]]], v[[[VREG2]]:[[VREG3]]]
; GCN-NEXT: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]] ; GCN-NEXT: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]]
; GCN-NEXT: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]] ; GCN-NEXT: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; GCN-NEXT: s_nop 0 ; GCN-NEXT: s_nop 0
; GCN-NEXT: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, s{{\[}}[[SREG0]]:[[SREG3]]{{\]}} dmask:0x1 ; GCN-NEXT: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, s[[[SREG0]]:[[SREG3]]] dmask:0x1
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GCN-NEXT: ; implicit-def: $vgpr4_vgpr5 ; GCN-NEXT: ; implicit-def: $vgpr4_vgpr5
; GCN-NEXT: s_xor_b64 exec, exec, [[SAVE]] ; GCN-NEXT: s_xor_b64 exec, exec, [[SAVE]]
; GCN-NEXT: s_cbranch_execnz [[SAMP_LOOP]] ; GCN-NEXT: s_cbranch_execnz [[SAMP_LOOP]]
define amdgpu_ps <4 x float> @water_loop_samp(<8 x i32> inreg %rsrc, <4 x i32> %samp, float %s, float %t) { define amdgpu_ps <4 x float> @water_loop_samp(<8 x i32> inreg %rsrc, <4 x i32> %samp, float %s, float %t) {
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }

llvm/test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
; indexing of vectors. ; indexing of vectors.
; Subtest below moved from file test/CodeGen/AMDGPU/indirect-addressing-si.ll ; Subtest below moved from file test/CodeGen/AMDGPU/indirect-addressing-si.ll
; to avoid gfx9 scheduling induced issues. ; to avoid gfx9 scheduling induced issues.
; GCN-LABEL: {{^}}insert_vgpr_offset_multiple_in_block: ; GCN-LABEL: {{^}}insert_vgpr_offset_multiple_in_block:
; GCN-DAG: s_load_dwordx16 s{{\[}}[[S_ELT0:[0-9]+]]:[[S_ELT15:[0-9]+]]{{\]}} ; GCN-DAG: s_load_dwordx16 s[[[S_ELT0:[0-9]+]]:[[S_ELT15:[0-9]+]]]
; GCN-DAG: {{buffer|flat|global}}_load_dword [[IDX0:v[0-9]+]] ; GCN-DAG: {{buffer|flat|global}}_load_dword [[IDX0:v[0-9]+]]
; GCN-DAG: v_mov_b32 [[INS0:v[0-9]+]], 62 ; GCN-DAG: v_mov_b32 [[INS0:v[0-9]+]], 62
; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT15:[0-9]+]], s[[S_ELT15]] ; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT15:[0-9]+]], s[[S_ELT15]]
; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT0:[0-9]+]], s[[S_ELT0]] ; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT0:[0-9]+]], s[[S_ELT0]]
; GCN: v_cmp_eq_u32_e32 ; GCN: v_cmp_eq_u32_e32
; GCN-COUNT-32: v_cndmask_b32 ; GCN-COUNT-32: v_cndmask_b32
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llvm/test/CodeGen/AMDGPU/indirect-addressing-si-pregfx9.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-vgpr-index-mode -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-vgpr-index-mode -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
; Tests for indirect addressing on SI, which is implemented using dynamic ; Tests for indirect addressing on SI, which is implemented using dynamic
; indexing of vectors. ; indexing of vectors.
; Subtest below moved from file test/CodeGen/AMDGPU/indirect-addressing-si.ll ; Subtest below moved from file test/CodeGen/AMDGPU/indirect-addressing-si.ll
; to avoid gfx9 scheduling induced issues. ; to avoid gfx9 scheduling induced issues.
; GCN-LABEL: {{^}}insert_vgpr_offset_multiple_in_block: ; GCN-LABEL: {{^}}insert_vgpr_offset_multiple_in_block:
; GCN-DAG: s_load_dwordx16 s{{\[}}[[S_ELT0:[0-9]+]]:[[S_ELT15:[0-9]+]]{{\]}} ; GCN-DAG: s_load_dwordx16 s[[[S_ELT0:[0-9]+]]:[[S_ELT15:[0-9]+]]]
; GCN-DAG: {{buffer|flat|global}}_load_dword [[IDX0:v[0-9]+]] ; GCN-DAG: {{buffer|flat|global}}_load_dword [[IDX0:v[0-9]+]]
; GCN-DAG: v_mov_b32 [[INS0:v[0-9]+]], 62 ; GCN-DAG: v_mov_b32 [[INS0:v[0-9]+]], 62
; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT15:[0-9]+]], s[[S_ELT15]] ; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT15:[0-9]+]], s[[S_ELT15]]
; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT0:[0-9]+]], s[[S_ELT0]] ; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT0:[0-9]+]], s[[S_ELT0]]
; GCN-DAG: v_add_{{i32|u32}}_e32 [[IDX1:v[0-9]+]], vcc, 1, [[IDX0]] ; GCN-DAG: v_add_{{i32|u32}}_e32 [[IDX1:v[0-9]+]], vcc, 1, [[IDX0]]
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llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Lines
; GCN-DAG: v_mov_b32_e32 v[[ELT0:[0-9]+]], 1.0 ; GCN-DAG: v_mov_b32_e32 v[[ELT0:[0-9]+]], 1.0
; GCN-DAG: v_mov_b32_e32 v[[ELT1:[0-9]+]], 2.0 ; GCN-DAG: v_mov_b32_e32 v[[ELT1:[0-9]+]], 2.0
; GCN-DAG: v_mov_b32_e32 v[[ELT2:[0-9]+]], 0x40400000 ; GCN-DAG: v_mov_b32_e32 v[[ELT2:[0-9]+]], 0x40400000
; GCN-DAG: v_mov_b32_e32 v[[ELT3:[0-9]+]], 4.0 ; GCN-DAG: v_mov_b32_e32 v[[ELT3:[0-9]+]], 4.0
; GCN-DAG: v_mov_b32_e32 v[[ELT15:[0-9]+]], 0x41800000 ; GCN-DAG: v_mov_b32_e32 v[[ELT15:[0-9]+]], 0x41800000
; GCN-DAG: v_mov_b32_e32 v[[INS:[0-9]+]], 0x41880000 ; GCN-DAG: v_mov_b32_e32 v[[INS:[0-9]+]], 0x41880000
; MOVREL: v_movreld_b32_e32 v[[ELT0]], v[[INS]] ; MOVREL: v_movreld_b32_e32 v[[ELT0]], v[[INS]]
; MOVREL: buffer_store_dwordx4 v{{\[}}[[ELT0]]:[[ELT3]]{{\]}} ; MOVREL: buffer_store_dwordx4 v[[[ELT0]]:[[ELT3]]]
define amdgpu_kernel void @insert_w_offset(<16 x float> addrspace(1)* %out, i32 %in) { define amdgpu_kernel void @insert_w_offset(<16 x float> addrspace(1)* %out, i32 %in) {
entry: entry:
%add = add i32 %in, 1 %add = add i32 %in, 1
%ins = insertelement <16 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0>, float 17.0, i32 %add %ins = insertelement <16 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0>, float 17.0, i32 %add
store <16 x float> %ins, <16 x float> addrspace(1)* %out store <16 x float> %ins, <16 x float> addrspace(1)* %out
ret void ret void
} }
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; MOVREL: s_mov_b32 m0, [[IN]] ; MOVREL: s_mov_b32 m0, [[IN]]
; MOVREL: v_movreld_b32_e32 v[[ELT0:[0-9]+]] ; MOVREL: v_movreld_b32_e32 v[[ELT0:[0-9]+]]
; IDXMODE: s_set_gpr_idx_on [[IN]], gpr_idx(DST) ; IDXMODE: s_set_gpr_idx_on [[IN]], gpr_idx(DST)
; IDXMODE-NEXT: v_mov_b32_e32 v[[ELT0:[0-9]+]], v{{[0-9]+}} ; IDXMODE-NEXT: v_mov_b32_e32 v[[ELT0:[0-9]+]], v{{[0-9]+}}
; IDXMODE-NEXT: s_set_gpr_idx_off ; IDXMODE-NEXT: s_set_gpr_idx_off
; GCN: buffer_store_dwordx4 v{{\[}}[[ELT0]]: ; GCN: buffer_store_dwordx4 v[[[ELT0]]:
define amdgpu_kernel void @insert_wo_offset(<16 x float> addrspace(1)* %out, i32 %in) { define amdgpu_kernel void @insert_wo_offset(<16 x float> addrspace(1)* %out, i32 %in) {
entry: entry:
%ins = insertelement <16 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0>, float 17.0, i32 %in %ins = insertelement <16 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0>, float 17.0, i32 %in
store <16 x float> %ins, <16 x float> addrspace(1)* %out store <16 x float> %ins, <16 x float> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}insert_neg_offset_sgpr: ; GCN-LABEL: {{^}}insert_neg_offset_sgpr:
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%tmp8 = extractelement <9 x i32> %tmp7, i32 5 %tmp8 = extractelement <9 x i32> %tmp7, i32 5
store volatile i32 %tmp6, i32 addrspace(3)* undef, align 4 store volatile i32 %tmp6, i32 addrspace(3)* undef, align 4
store volatile i32 %tmp8, i32 addrspace(3)* undef, align 4 store volatile i32 %tmp8, i32 addrspace(3)* undef, align 4
ret void ret void
} }
; offset puts outside of superegister bounaries, so clamp to 1st element. ; offset puts outside of superegister bounaries, so clamp to 1st element.
; GCN-LABEL: {{^}}extract_largest_inbounds_offset: ; GCN-LABEL: {{^}}extract_largest_inbounds_offset:
; GCN-DAG: buffer_load_dwordx4 v{{\[}}[[LO_ELT:[0-9]+]]:[[HI_ELT:[0-9]+]] ; GCN-DAG: buffer_load_dwordx4 v[[[LO_ELT:[0-9]+]]:[[HI_ELT:[0-9]+]]
; GCN-DAG: s_load_dword [[IDX0:s[0-9]+]] ; GCN-DAG: s_load_dword [[IDX0:s[0-9]+]]
; GCN-DAG: s_add_i32 [[IDX:s[0-9]+]], [[IDX0]], 15 ; GCN-DAG: s_add_i32 [[IDX:s[0-9]+]], [[IDX0]], 15
; MOVREL: s_mov_b32 m0, [[IDX]] ; MOVREL: s_mov_b32 m0, [[IDX]]
; MOVREL: v_movrels_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]] ; MOVREL: v_movrels_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]]
; IDXMODE: s_set_gpr_idx_on [[IDX]], gpr_idx(SRC0) ; IDXMODE: s_set_gpr_idx_on [[IDX]], gpr_idx(SRC0)
; IDXMODE: v_mov_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]] ; IDXMODE: v_mov_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]]
; IDXMODE: s_set_gpr_idx_off ; IDXMODE: s_set_gpr_idx_off
; GCN: buffer_store_dword [[EXTRACT]] ; GCN: buffer_store_dword [[EXTRACT]]
define amdgpu_kernel void @extract_largest_inbounds_offset(i32 addrspace(1)* %out, <16 x i32> addrspace(1)* %in, i32 %idx) { define amdgpu_kernel void @extract_largest_inbounds_offset(i32 addrspace(1)* %out, <16 x i32> addrspace(1)* %in, i32 %idx) {
entry: entry:
%ld = load volatile <16 x i32>, <16 x i32> addrspace(1)* %in %ld = load volatile <16 x i32>, <16 x i32> addrspace(1)* %in
%offset = add i32 %idx, 15 %offset = add i32 %idx, 15
%value = extractelement <16 x i32> %ld, i32 %offset %value = extractelement <16 x i32> %ld, i32 %offset
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}extract_out_of_bounds_offset: ; GCN-LABEL: {{^}}extract_out_of_bounds_offset:
; GCN-DAG: buffer_load_dwordx4 v{{\[}}[[LO_ELT:[0-9]+]]:[[HI_ELT:[0-9]+]]{{\]}} ; GCN-DAG: buffer_load_dwordx4 v[[[LO_ELT:[0-9]+]]:[[HI_ELT:[0-9]+]]]
; GCN-DAG: s_load_dword [[IDX:s[0-9]+]] ; GCN-DAG: s_load_dword [[IDX:s[0-9]+]]
; GCN: s_add_i32 [[ADD_IDX:s[0-9]+]], [[IDX]], 16 ; GCN: s_add_i32 [[ADD_IDX:s[0-9]+]], [[IDX]], 16
; MOVREL: s_mov_b32 m0, [[ADD_IDX]] ; MOVREL: s_mov_b32 m0, [[ADD_IDX]]
; MOVREL: v_movrels_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]] ; MOVREL: v_movrels_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]]
; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(SRC0) ; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], gpr_idx(SRC0)
; IDXMODE: v_mov_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]] ; IDXMODE: v_mov_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]]
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llvm/test/CodeGen/AMDGPU/inline-asm.ll

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Linesif:
br label %endif br label %endif
endif: endif:
ret void ret void
} }
; CHECK-LABEL: {{^}}v_cmp_asm: ; CHECK-LABEL: {{^}}v_cmp_asm:
; CHECK: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}} ; CHECK: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}
; CHECK: v_cmp_ne_u32_e64 s{{\[}}[[MASK_LO:[0-9]+]]:[[MASK_HI:[0-9]+]]{{\]}}, 0, [[SRC]] ; CHECK: v_cmp_ne_u32_e64 s[[[MASK_LO:[0-9]+]]:[[MASK_HI:[0-9]+]]], 0, [[SRC]]
; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[MASK_LO]] ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[MASK_LO]]
; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[MASK_HI]] ; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[MASK_HI]]
; CHECK: buffer_store_dwordx2 v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} ; CHECK: buffer_store_dwordx2 v[[[V_LO]]:[[V_HI]]]
define amdgpu_kernel void @v_cmp_asm(i64 addrspace(1)* %out, i32 %in) { define amdgpu_kernel void @v_cmp_asm(i64 addrspace(1)* %out, i32 %in) {
%sgpr = tail call i64 asm "v_cmp_ne_u32_e64 $0, 0, $1", "=s,v"(i32 %in) %sgpr = tail call i64 asm "v_cmp_ne_u32_e64 $0, 0, $1", "=s,v"(i32 %in)
store i64 %sgpr, i64 addrspace(1)* %out store i64 %sgpr, i64 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: {{^}}code_size_inline_asm: ; CHECK-LABEL: {{^}}code_size_inline_asm:
; CHECK: codeLenInByte = 12 ; CHECK: codeLenInByte = 12
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llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll

Show All 9 Lines
; GCN-DAG: s_cselect_b64 [[CC2:[^,]+]], -1, 0 ; GCN-DAG: s_cselect_b64 [[CC2:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC2]] ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC2]]
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 1 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 1
; GCN-DAG: s_cselect_b64 [[CC3:[^,]+]], -1, 0 ; GCN-DAG: s_cselect_b64 [[CC3:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC3]] ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC3]]
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 0 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 0
; GCN-DAG: s_cselect_b64 [[CC4:[^,]+]], -1, 0 ; GCN-DAG: s_cselect_b64 [[CC4:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC4]] ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC4]]
; GCN: flat_store_dwordx4 v[{{[0-9:]+}}], v{{\[}}[[ELT_FIRST]]:[[ELT_LAST]]] ; GCN: flat_store_dwordx4 v[{{[0-9:]+}}], v[[[ELT_FIRST]]:[[ELT_LAST]]]
define amdgpu_kernel void @float4_inselt(<4 x float> addrspace(1)* %out, <4 x float> %vec, i32 %sel) { define amdgpu_kernel void @float4_inselt(<4 x float> addrspace(1)* %out, <4 x float> %vec, i32 %sel) {
entry: entry:
%v = insertelement <4 x float> %vec, float 1.000000e+00, i32 %sel %v = insertelement <4 x float> %vec, float 1.000000e+00, i32 %sel
store <4 x float> %v, <4 x float> addrspace(1)* %out store <4 x float> %v, <4 x float> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}float4_inselt_undef: ; GCN-LABEL: {{^}}float4_inselt_undef:
Show All 22 Lines
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 1 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 1
; GCN-DAG: s_cselect_b32 s[[ELT_1:[0-9]+]], s{{[0-9]+}}, 1 ; GCN-DAG: s_cselect_b32 s[[ELT_1:[0-9]+]], s{{[0-9]+}}, 1
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 0 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 0
; GCN-DAG: s_cselect_b32 s[[ELT_0:[0-9]+]], s{{[0-9]+}}, 1 ; GCN-DAG: s_cselect_b32 s[[ELT_0:[0-9]+]], s{{[0-9]+}}, 1
; GCN-DAG: v_mov_b32_e32 v[[VELT_0:[0-9]+]], s[[ELT_0]] ; GCN-DAG: v_mov_b32_e32 v[[VELT_0:[0-9]+]], s[[ELT_0]]
; GCN-DAG: v_mov_b32_e32 v[[VELT_1:[0-9]+]], s[[ELT_1]] ; GCN-DAG: v_mov_b32_e32 v[[VELT_1:[0-9]+]], s[[ELT_1]]
; GCN-DAG: v_mov_b32_e32 v[[VELT_2:[0-9]+]], s[[ELT_2]] ; GCN-DAG: v_mov_b32_e32 v[[VELT_2:[0-9]+]], s[[ELT_2]]
; GCN-DAG: v_mov_b32_e32 v[[VELT_3:[0-9]+]], s[[ELT_3]] ; GCN-DAG: v_mov_b32_e32 v[[VELT_3:[0-9]+]], s[[ELT_3]]
; GCN: flat_store_dwordx4 v[{{[0-9:]+}}], v{{\[}}[[VELT_0]]:[[VELT_3]]] ; GCN: flat_store_dwordx4 v[{{[0-9:]+}}], v[[[VELT_0]]:[[VELT_3]]]
define amdgpu_kernel void @int4_inselt(<4 x i32> addrspace(1)* %out, <4 x i32> %vec, i32 %sel) { define amdgpu_kernel void @int4_inselt(<4 x i32> addrspace(1)* %out, <4 x i32> %vec, i32 %sel) {
entry: entry:
%v = insertelement <4 x i32> %vec, i32 1, i32 %sel %v = insertelement <4 x i32> %vec, i32 1, i32 %sel
store <4 x i32> %v, <4 x i32> addrspace(1)* %out store <4 x i32> %v, <4 x i32> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}float2_inselt: ; GCN-LABEL: {{^}}float2_inselt:
; GCN-NOT: v_movrel ; GCN-NOT: v_movrel
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: s_cmp_lg_u32 [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_lg_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: s_cselect_b64 [[CC1:[^,]+]], -1, 0 ; GCN-DAG: s_cselect_b64 [[CC1:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v[[ELT_LAST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC1]] ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_LAST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC1]]
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 0 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 0
; GCN-DAG: s_cselect_b64 [[CC2:[^,]+]], -1, 0 ; GCN-DAG: s_cselect_b64 [[CC2:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC2]] ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC2]]
; GCN: flat_store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[ELT_FIRST]]:[[ELT_LAST]]] ; GCN: flat_store_dwordx2 v[{{[0-9:]+}}], v[[[ELT_FIRST]]:[[ELT_LAST]]]
define amdgpu_kernel void @float2_inselt(<2 x float> addrspace(1)* %out, <2 x float> %vec, i32 %sel) { define amdgpu_kernel void @float2_inselt(<2 x float> addrspace(1)* %out, <2 x float> %vec, i32 %sel) {
entry: entry:
%v = insertelement <2 x float> %vec, float 1.000000e+00, i32 %sel %v = insertelement <2 x float> %vec, float 1.000000e+00, i32 %sel
store <2 x float> %v, <2 x float> addrspace(1)* %out store <2 x float> %v, <2 x float> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}float8_inselt: ; GCN-LABEL: {{^}}float8_inselt:
Show All 18 Lines
; GCN-DAG: s_cselect_b64 [[CC6:[^,]+]], -1, 0 ; GCN-DAG: s_cselect_b64 [[CC6:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC6]] ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC6]]
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 5 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 5
; GCN-DAG: s_cselect_b64 [[CC7:[^,]+]], -1, 0 ; GCN-DAG: s_cselect_b64 [[CC7:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC7]] ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC7]]
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 4 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 4
; GCN-DAG: s_cselect_b64 [[CC8:[^,]+]], -1, 0 ; GCN-DAG: s_cselect_b64 [[CC8:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST1:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC8]] ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST1:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC8]]
; GCN-DAG: flat_store_dwordx4 v[{{[0-9:]+}}], v{{\[}}[[ELT_FIRST0]]:[[ELT_LAST0]]] ; GCN-DAG: flat_store_dwordx4 v[{{[0-9:]+}}], v[[[ELT_FIRST0]]:[[ELT_LAST0]]]
; GCN-DAG: flat_store_dwordx4 v[{{[0-9:]+}}], v{{\[}}[[ELT_FIRST1]]:[[ELT_LAST1]]] ; GCN-DAG: flat_store_dwordx4 v[{{[0-9:]+}}], v[[[ELT_FIRST1]]:[[ELT_LAST1]]]
define amdgpu_kernel void @float8_inselt(<8 x float> addrspace(1)* %out, <8 x float> %vec, i32 %sel) { define amdgpu_kernel void @float8_inselt(<8 x float> addrspace(1)* %out, <8 x float> %vec, i32 %sel) {
entry: entry:
%v = insertelement <8 x float> %vec, float 1.000000e+00, i32 %sel %v = insertelement <8 x float> %vec, float 1.000000e+00, i32 %sel
store <8 x float> %v, <8 x float> addrspace(1)* %out store <8 x float> %v, <8 x float> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}float16_inselt: ; GCN-LABEL: {{^}}float16_inselt:
Show All 18 Lines
; GCN-NOT: v_cndmask_b32 ; GCN-NOT: v_cndmask_b32
; GCN-NOT: v_movrel ; GCN-NOT: v_movrel
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN: s_lshl_b32 [[SEL:s[0-9]+]], s{{[0-9]+}}, 4 ; GCN: s_lshl_b32 [[SEL:s[0-9]+]], s{{[0-9]+}}, 4
; GCN: s_lshl_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], [[SEL]] ; GCN: s_lshl_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], [[SEL]]
; GCN: s_mov_b32 s[[KLO:[0-9]+]], 0x3c003c00 ; GCN: s_mov_b32 s[[KLO:[0-9]+]], 0x3c003c00
; GCN: s_mov_b32 s[[KHI:[0-9]+]], s[[KLO]] ; GCN: s_mov_b32 s[[KHI:[0-9]+]], s[[KLO]]
; GCN: s_andn2_b64 ; GCN: s_andn2_b64
; GCN: s_and_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], s{{\[}}[[KLO]]:[[KHI]]] ; GCN: s_and_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], s[[[KLO]]:[[KHI]]]
; GCN: s_or_b64 ; GCN: s_or_b64
define amdgpu_kernel void @half4_inselt(<4 x half> addrspace(1)* %out, <4 x half> %vec, i32 %sel) { define amdgpu_kernel void @half4_inselt(<4 x half> addrspace(1)* %out, <4 x half> %vec, i32 %sel) {
entry: entry:
%v = insertelement <4 x half> %vec, half 1.000000e+00, i32 %sel %v = insertelement <4 x half> %vec, half 1.000000e+00, i32 %sel
store <4 x half> %v, <4 x half> addrspace(1)* %out store <4 x half> %v, <4 x half> addrspace(1)* %out
ret void ret void
} }
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; GCN-NOT: v_cndmask_b32 ; GCN-NOT: v_cndmask_b32
; GCN-NOT: v_movrel ; GCN-NOT: v_movrel
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN: s_lshl_b32 [[SEL:s[0-9]+]], s{{[0-9]+}}, 4 ; GCN: s_lshl_b32 [[SEL:s[0-9]+]], s{{[0-9]+}}, 4
; GCN: s_lshl_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], [[SEL]] ; GCN: s_lshl_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], [[SEL]]
; GCN: s_mov_b32 s[[KLO:[0-9]+]], 0x10001 ; GCN: s_mov_b32 s[[KLO:[0-9]+]], 0x10001
; GCN: s_mov_b32 s[[KHI:[0-9]+]], s[[KLO]] ; GCN: s_mov_b32 s[[KHI:[0-9]+]], s[[KLO]]
; GCN: s_andn2_b64 ; GCN: s_andn2_b64
; GCN: s_and_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], s{{\[}}[[KLO]]:[[KHI]]] ; GCN: s_and_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], s[[[KLO]]:[[KHI]]]
; GCN: s_or_b64 ; GCN: s_or_b64
define amdgpu_kernel void @short4_inselt(<4 x i16> addrspace(1)* %out, <4 x i16> %vec, i32 %sel) { define amdgpu_kernel void @short4_inselt(<4 x i16> addrspace(1)* %out, <4 x i16> %vec, i32 %sel) {
entry: entry:
%v = insertelement <4 x i16> %vec, i16 1, i32 %sel %v = insertelement <4 x i16> %vec, i16 1, i32 %sel
store <4 x i16> %v, <4 x i16> addrspace(1)* %out store <4 x i16> %v, <4 x i16> addrspace(1)* %out
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll

Show All 13 Linesdefine amdgpu_kernel void @test_merge_store_constant_i16_invariant_global_pointer_load(i16 addrspace(1)* addrspace(1)* dereferenceable(4096) nonnull %in) #0 {
%ptr = load i16 addrspace(1)*, i16 addrspace(1)* addrspace(1)* %in, !invariant.load !0 %ptr = load i16 addrspace(1)*, i16 addrspace(1)* addrspace(1)* %in, !invariant.load !0
%ptr.1 = getelementptr i16, i16 addrspace(1)* %ptr, i64 1 %ptr.1 = getelementptr i16, i16 addrspace(1)* %ptr, i64 1
store i16 123, i16 addrspace(1)* %ptr, align 4 store i16 123, i16 addrspace(1)* %ptr, align 4
store i16 456, i16 addrspace(1)* %ptr.1 store i16 456, i16 addrspace(1)* %ptr.1
ret void ret void
} }
; GCN-LABEL: {{^}}test_merge_store_constant_i16_invariant_constant_pointer_load: ; GCN-LABEL: {{^}}test_merge_store_constant_i16_invariant_constant_pointer_load:
; GCN: s_load_dwordx2 s{{\[}}[[SPTR_LO:[0-9]+]]:[[SPTR_HI:[0-9]+]]{{\]}} ; GCN: s_load_dwordx2 s[[[SPTR_LO:[0-9]+]]:[[SPTR_HI:[0-9]+]]]
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x1c8007b ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x1c8007b
; GCN: buffer_store_dword [[K]], off, s{{\[}}[[SPTR_LO]]: ; GCN: buffer_store_dword [[K]], off, s[[[SPTR_LO]]:
define amdgpu_kernel void @test_merge_store_constant_i16_invariant_constant_pointer_load(i16 addrspace(1)* addrspace(4)* dereferenceable(4096) nonnull %in) #0 { define amdgpu_kernel void @test_merge_store_constant_i16_invariant_constant_pointer_load(i16 addrspace(1)* addrspace(4)* dereferenceable(4096) nonnull %in) #0 {
%ptr = load i16 addrspace(1)*, i16 addrspace(1)* addrspace(4)* %in, !invariant.load !0 %ptr = load i16 addrspace(1)*, i16 addrspace(1)* addrspace(4)* %in, !invariant.load !0
%ptr.1 = getelementptr i16, i16 addrspace(1)* %ptr, i64 1 %ptr.1 = getelementptr i16, i16 addrspace(1)* %ptr, i64 1
store i16 123, i16 addrspace(1)* %ptr, align 4 store i16 123, i16 addrspace(1)* %ptr, align 4
store i16 456, i16 addrspace(1)* %ptr.1 store i16 456, i16 addrspace(1)* %ptr.1
ret void ret void
} }
!0 = !{} !0 = !{}
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll

Show First 20 Lines • Show All 242 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @byref_flat_i32_arg(i32 addrspace(1)* nocapture %out, i32* byref(i32) %in.byref) {
%in = load i32, i32* %in.byref %in = load i32, i32* %in.byref
store i32 %in, i32 addrspace(1)* %out, align 4 store i32 %in, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}byref_constant_32bit_i32_arg: ; GCN-LABEL: {{^}}byref_constant_32bit_i32_arg:
; GCN: s_add_i32 s[[PTR_LO:[0-9]+]], s4, 8 ; GCN: s_add_i32 s[[PTR_LO:[0-9]+]], s4, 8
; GCN: s_mov_b32 s[[PTR_HI:[0-9]+]], 0{{$}} ; GCN: s_mov_b32 s[[PTR_HI:[0-9]+]], 0{{$}}
; GCN: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x0{{$}} ; GCN: s_load_dword s{{[0-9]+}}, s[[[PTR_LO]]:[[PTR_HI]]], 0x0{{$}}
define amdgpu_kernel void @byref_constant_32bit_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(6)* byref(i32) %in.byref) { define amdgpu_kernel void @byref_constant_32bit_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(6)* byref(i32) %in.byref) {
%in = load i32, i32 addrspace(6)* %in.byref %in = load i32, i32 addrspace(6)* %in.byref
store i32 %in, i32 addrspace(1)* %out, align 4 store i32 %in, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; define amdgpu_kernel void @byref_unknown_as_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(999)* byref %in.byref) { ; define amdgpu_kernel void @byref_unknown_as_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(999)* byref %in.byref) {
; %in = load i32, i32 addrspace(999)* %in.byref ; %in = load i32, i32 addrspace(999)* %in.byref
Show All 28 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll

Show First 20 Lines • Show All 196 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @flat_atomic_dec_noret_i32_offset_addr64(i32* %ptr) #0 {
%gep = getelementptr i32, i32* %gep.tid, i32 5 %gep = getelementptr i32, i32* %gep.tid, i32 5
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64: ; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]] glc{{$}}
define amdgpu_kernel void @flat_atomic_dec_ret_i64(i64* %out, i64* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i64(i64* %out, i64* %ptr) #0 {
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64* %out store i64 %result, i64* %out
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64_offset: ; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64_offset:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]] glc{{$}}
; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32 glc{{$}} ; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]] offset:32 glc{{$}}
define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset(i64* %out, i64* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset(i64* %out, i64* %ptr) #0 {
%gep = getelementptr i64, i64* %ptr, i32 4 %gep = getelementptr i64, i64* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64* %out store i64 %result, i64* %out
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_noret_i64: ; GCN-LABEL: {{^}}flat_atomic_dec_noret_i64:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]{{\]$}}
define amdgpu_kernel void @flat_atomic_dec_noret_i64(i64* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_dec_noret_i64(i64* %ptr) nounwind {
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_noret_i64_offset: ; GCN-LABEL: {{^}}flat_atomic_dec_noret_i64_offset:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]{{\]$}}
; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32{{$}} ; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]] offset:32{{$}}
define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset(i64* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset(i64* %ptr) nounwind {
%gep = getelementptr i64, i64* %ptr, i32 4 %gep = getelementptr i64, i64* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64_offset_addr64: ; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64_offset_addr64:
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]] glc{{$}}
; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:40 glc{{$}} ; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]] offset:40 glc{{$}}
define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(i64* %out, i64* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(i64* %out, i64* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64* %ptr, i32 %id %gep.tid = getelementptr i64, i64* %ptr, i32 %id
%out.gep = getelementptr i64, i64* %out, i32 %id %out.gep = getelementptr i64, i64* %out, i32 %id
%gep = getelementptr i64, i64* %gep.tid, i32 5 %gep = getelementptr i64, i64* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64* %out.gep store i64 %result, i64* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_noret_i64_offset_addr64: ; GCN-LABEL: {{^}}flat_atomic_dec_noret_i64_offset_addr64:
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]{{\]$}}
; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:40{{$}} ; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]] offset:40{{$}}
define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_addr64(i64* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_addr64(i64* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64* %ptr, i32 %id %gep.tid = getelementptr i64, i64* %ptr, i32 %id
%gep = getelementptr i64, i64* %gep.tid, i32 5 %gep = getelementptr i64, i64* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
Show All 16 Lines
} }
; GCN-LABEL: {{^}}lds_atomic_dec_ret_i64: ; GCN-LABEL: {{^}}lds_atomic_dec_ret_i64:
; CIVI-DAG: s_mov_b32 m0 ; CIVI-DAG: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: ds_dec_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}} ; GCN: ds_dec_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v[[[KLO]]:[[KHI]]]{{$}}
define amdgpu_kernel void @lds_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 { define amdgpu_kernel void @lds_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 {
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %ptr, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}lds_atomic_dec_ret_i64_offset: ; GCN-LABEL: {{^}}lds_atomic_dec_ret_i64_offset:
; CIVI-DAG: s_mov_b32 m0 ; CIVI-DAG: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: ds_dec_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32 ; GCN: ds_dec_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v[[[KLO]]:[[KHI]]] offset:32
define amdgpu_kernel void @lds_atomic_dec_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 { define amdgpu_kernel void @lds_atomic_dec_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 {
%gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4 %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}lds_atomic_dec_noret_i64: ; GCN-LABEL: {{^}}lds_atomic_dec_noret_i64:
; CIVI-DAG: s_mov_b32 m0 ; CIVI-DAG: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: ds_dec_u64 v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}} ; GCN: ds_dec_u64 v{{[0-9]+}}, v[[[KLO]]:[[KHI]]]{{$}}
define amdgpu_kernel void @lds_atomic_dec_noret_i64(i64 addrspace(3)* %ptr) nounwind { define amdgpu_kernel void @lds_atomic_dec_noret_i64(i64 addrspace(3)* %ptr) nounwind {
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %ptr, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}lds_atomic_dec_noret_i64_offset: ; GCN-LABEL: {{^}}lds_atomic_dec_noret_i64_offset:
; CIVI-DAG: s_mov_b32 m0 ; CIVI-DAG: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: ds_dec_u64 v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32{{$}} ; GCN: ds_dec_u64 v{{[0-9]+}}, v[[[KLO]]:[[KHI]]] offset:32{{$}}
define amdgpu_kernel void @lds_atomic_dec_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { define amdgpu_kernel void @lds_atomic_dec_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
%gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4 %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}global_atomic_dec_ret_i64: ; GCN-LABEL: {{^}}global_atomic_dec_ret_i64:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; CIVI: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 glc{{$}} ; CIVI: buffer_atomic_dec_x2 v[[[KLO]]:[[KHI]]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 glc{{$}}
; GFX9: global_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[ZERO]], v{{\[}}[[KLO]]:[[KHI]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GFX9: global_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[ZERO]], v[[[KLO]]:[[KHI]]], s{{\[[0-9]+:[0-9]+\]}} glc{{$}}
define amdgpu_kernel void @global_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}global_atomic_dec_ret_i64_offset: ; GCN-LABEL: {{^}}global_atomic_dec_ret_i64_offset:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; CIVI: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32 glc{{$}} ; CIVI: buffer_atomic_dec_x2 v[[[KLO]]:[[KHI]]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32 glc{{$}}
; GFX9: global_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[ZERO]], v{{\[}}[[KLO]]:[[KHI]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}} offset:32 glc{{$}} ; GFX9: global_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[ZERO]], v[[[KLO]]:[[KHI]]], s{{\[[0-9]+:[0-9]+\]}} offset:32 glc{{$}}
define amdgpu_kernel void @global_atomic_dec_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_dec_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
%gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4 %gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}global_atomic_dec_noret_i64: ; GCN-LABEL: {{^}}global_atomic_dec_noret_i64:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; CIVI: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} ; CIVI: buffer_atomic_dec_x2 v[[[KLO]]:[[KHI]]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
; GFX9: global_atomic_dec_x2 v[[ZERO]], v{{\[}}[[KLO]]:[[KHI]]{{\]}}, s{{\[[0-9]+:[0-9]+\]$}} ; GFX9: global_atomic_dec_x2 v[[ZERO]], v[[[KLO]]:[[KHI]]], s{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @global_atomic_dec_noret_i64(i64 addrspace(1)* %ptr) nounwind { define amdgpu_kernel void @global_atomic_dec_noret_i64(i64 addrspace(1)* %ptr) nounwind {
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}global_atomic_dec_noret_i64_offset: ; GCN-LABEL: {{^}}global_atomic_dec_noret_i64_offset:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; CIVI: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32{{$}} ; CIVI: buffer_atomic_dec_x2 v[[[KLO]]:[[KHI]]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32{{$}}
; GFX9: global_atomic_dec_x2 v[[ZERO]], v{{\[}}[[KLO]]:[[KHI]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}} offset:32{{$}} ; GFX9: global_atomic_dec_x2 v[[ZERO]], v[[[KLO]]:[[KHI]]], s{{\[[0-9]+:[0-9]+\]}} offset:32{{$}}
define amdgpu_kernel void @global_atomic_dec_noret_i64_offset(i64 addrspace(1)* %ptr) nounwind { define amdgpu_kernel void @global_atomic_dec_noret_i64_offset(i64 addrspace(1)* %ptr) nounwind {
%gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4 %gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}global_atomic_dec_ret_i64_offset_addr64: ; GCN-LABEL: {{^}}global_atomic_dec_ret_i64_offset_addr64:
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; CI: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}} ; CI: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}}
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CI: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40 glc{{$}} ; CI: buffer_atomic_dec_x2 v[[[KLO]]:[[KHI]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40 glc{{$}}
; VI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; VI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]] glc{{$}}
define amdgpu_kernel void @global_atomic_dec_ret_i64_offset_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_dec_ret_i64_offset_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id %gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id
%gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5 %gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(1)* %out.gep store i64 %result, i64 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}global_atomic_dec_noret_i64_offset_addr64: ; GCN-LABEL: {{^}}global_atomic_dec_noret_i64_offset_addr64:
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; CI: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}} ; CI: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}}
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CI: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40{{$}} ; CI: buffer_atomic_dec_x2 v[[[KLO]]:[[KHI]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40{{$}}
; VI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}} ; VI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]]{{$}}
define amdgpu_kernel void @global_atomic_dec_noret_i64_offset_addr64(i64 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_dec_noret_i64_offset_addr64(i64 addrspace(1)* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id %gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id
%gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5 %gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
Show All 21 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
store i32 %idx.0, i32 addrspace(1)* %add_use store i32 %idx.0, i32 addrspace(1)* %add_use
store i32 %val0, i32 addrspace(1)* %out store i32 %val0, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}lds_atomic_inc_ret_i64: ; GCN-LABEL: {{^}}lds_atomic_inc_ret_i64:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: ds_inc_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}} ; GCN: ds_inc_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v[[[KLO]]:[[KHI]]]{{$}}
define amdgpu_kernel void @lds_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 { define amdgpu_kernel void @lds_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 {
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %ptr, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}lds_atomic_inc_ret_i64_offset: ; GCN-LABEL: {{^}}lds_atomic_inc_ret_i64_offset:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: ds_inc_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32 ; GCN: ds_inc_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v[[[KLO]]:[[KHI]]] offset:32
define amdgpu_kernel void @lds_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 { define amdgpu_kernel void @lds_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 {
%gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4 %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}lds_atomic_inc_noret_i64: ; GCN-LABEL: {{^}}lds_atomic_inc_noret_i64:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: ds_inc_u64 v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}} ; GCN: ds_inc_u64 v{{[0-9]+}}, v[[[KLO]]:[[KHI]]]{{$}}
define amdgpu_kernel void @lds_atomic_inc_noret_i64(i64 addrspace(3)* %ptr) nounwind { define amdgpu_kernel void @lds_atomic_inc_noret_i64(i64 addrspace(3)* %ptr) nounwind {
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %ptr, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}lds_atomic_inc_noret_i64_offset: ; GCN-LABEL: {{^}}lds_atomic_inc_noret_i64_offset:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: ds_inc_u64 v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32{{$}} ; GCN: ds_inc_u64 v{{[0-9]+}}, v[[[KLO]]:[[KHI]]] offset:32{{$}}
define amdgpu_kernel void @lds_atomic_inc_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { define amdgpu_kernel void @lds_atomic_inc_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
%gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4 %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}global_atomic_inc_ret_i64: ; GCN-LABEL: {{^}}global_atomic_inc_ret_i64:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; CIVI: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 glc{{$}} ; CIVI: buffer_atomic_inc_x2 v[[[KLO]]:[[KHI]]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 glc{{$}}
; GFX9: global_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[ZERO]], v{{\[}}[[KLO]]:[[KHI]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GFX9: global_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[ZERO]], v[[[KLO]]:[[KHI]]], s{{\[[0-9]+:[0-9]+\]}} glc{{$}}
define amdgpu_kernel void @global_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}global_atomic_inc_ret_i64_offset: ; GCN-LABEL: {{^}}global_atomic_inc_ret_i64_offset:
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; CIVI: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32 glc{{$}} ; CIVI: buffer_atomic_inc_x2 v[[[KLO]]:[[KHI]]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32 glc{{$}}
; GFX9: global_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[ZERO]], v{{\[}}[[KLO]]:[[KHI]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}} offset:32 glc{{$}} ; GFX9: global_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[ZERO]], v[[[KLO]]:[[KHI]]], s{{\[[0-9]+:[0-9]+\]}} offset:32 glc{{$}}
define amdgpu_kernel void @global_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
%gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4 %gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}global_atomic_inc_noret_i64: ; GCN-LABEL: {{^}}global_atomic_inc_noret_i64:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; CIVI: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} ; CIVI: buffer_atomic_inc_x2 v[[[KLO]]:[[KHI]]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
; GFX9: global_atomic_inc_x2 v[[ZERO]], v{{\[}}[[KLO]]:[[KHI]]{{\]}}, s{{\[[0-9]+:[0-9]+\]$}} ; GFX9: global_atomic_inc_x2 v[[ZERO]], v[[[KLO]]:[[KHI]]], s{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @global_atomic_inc_noret_i64(i64 addrspace(1)* %ptr) nounwind { define amdgpu_kernel void @global_atomic_inc_noret_i64(i64 addrspace(1)* %ptr) nounwind {
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}global_atomic_inc_noret_i64_offset: ; GCN-LABEL: {{^}}global_atomic_inc_noret_i64_offset:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; CIVI: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32{{$}} ; CIVI: buffer_atomic_inc_x2 v[[[KLO]]:[[KHI]]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32{{$}}
; GFX9: global_atomic_inc_x2 v[[ZERO]], v{{\[}}[[KLO]]:[[KHI]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}} offset:32{{$}} ; GFX9: global_atomic_inc_x2 v[[ZERO]], v[[[KLO]]:[[KHI]]], s{{\[[0-9]+:[0-9]+\]}} offset:32{{$}}
define amdgpu_kernel void @global_atomic_inc_noret_i64_offset(i64 addrspace(1)* %ptr) nounwind { define amdgpu_kernel void @global_atomic_inc_noret_i64_offset(i64 addrspace(1)* %ptr) nounwind {
%gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4 %gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}global_atomic_inc_ret_i64_offset_addr64: ; GCN-LABEL: {{^}}global_atomic_inc_ret_i64_offset_addr64:
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; CI: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}} ; CI: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}}
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CI: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40 glc{{$}} ; CI: buffer_atomic_inc_x2 v[[[KLO]]:[[KHI]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40 glc{{$}}
; VI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; VI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]] glc{{$}}
define amdgpu_kernel void @global_atomic_inc_ret_i64_offset_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_inc_ret_i64_offset_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id %gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id
%gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5 %gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(1)* %out.gep store i64 %result, i64 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}global_atomic_inc_noret_i64_offset_addr64: ; GCN-LABEL: {{^}}global_atomic_inc_noret_i64_offset_addr64:
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; CI: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}} ; CI: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}}
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CI: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40{{$}} ; CI: buffer_atomic_inc_x2 v[[[KLO]]:[[KHI]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40{{$}}
; VI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}} ; VI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]]{{$}}
define amdgpu_kernel void @global_atomic_inc_noret_i64_offset_addr64(i64 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_inc_noret_i64_offset_addr64(i64 addrspace(1)* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id %gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id
%gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5 %gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
store i32 %idx.0, i32 addrspace(1)* %add_use store i32 %idx.0, i32 addrspace(1)* %add_use
store i64 %val0, i64 addrspace(1)* %out store i64 %val0, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64: ; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]] glc{{$}}
define amdgpu_kernel void @flat_atomic_inc_ret_i64(i64* %out, i64* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i64(i64* %out, i64* %ptr) #0 {
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64* %out store i64 %result, i64* %out
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64_offset: ; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64_offset:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]] glc{{$}}
; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32 glc{{$}} ; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]] offset:32 glc{{$}}
define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset(i64* %out, i64* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset(i64* %out, i64* %ptr) #0 {
%gep = getelementptr i64, i64* %ptr, i32 4 %gep = getelementptr i64, i64* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64* %out store i64 %result, i64* %out
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_noret_i64: ; GCN-LABEL: {{^}}flat_atomic_inc_noret_i64:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]{{\]$}}
define amdgpu_kernel void @flat_atomic_inc_noret_i64(i64* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_inc_noret_i64(i64* %ptr) nounwind {
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_noret_i64_offset: ; GCN-LABEL: {{^}}flat_atomic_inc_noret_i64_offset:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]{{\]$}}
; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32{{$}} ; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]] offset:32{{$}}
define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset(i64* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset(i64* %ptr) nounwind {
%gep = getelementptr i64, i64* %ptr, i32 4 %gep = getelementptr i64, i64* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64_offset_addr64: ; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64_offset_addr64:
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]] glc{{$}}
; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:40 glc{{$}} ; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]] offset:40 glc{{$}}
define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(i64* %out, i64* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(i64* %out, i64* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64* %ptr, i32 %id %gep.tid = getelementptr i64, i64* %ptr, i32 %id
%out.gep = getelementptr i64, i64* %out, i32 %id %out.gep = getelementptr i64, i64* %out, i32 %id
%gep = getelementptr i64, i64* %gep.tid, i32 5 %gep = getelementptr i64, i64* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64* %out.gep store i64 %result, i64* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_noret_i64_offset_addr64: ; GCN-LABEL: {{^}}flat_atomic_inc_noret_i64_offset_addr64:
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]{{\]$}}
; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:40{{$}} ; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[[KLO]]:[[KHI]]] offset:40{{$}}
define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(i64* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(i64* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64* %ptr, i32 %id %gep.tid = getelementptr i64, i64* %ptr, i32 %id
%gep = getelementptr i64, i64* %gep.tid, i32 5 %gep = getelementptr i64, i64* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
Show All 16 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.d16.ll

; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s
; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
; GCN-LABEL: {{^}}buffer_load_format_d16_x: ; GCN-LABEL: {{^}}buffer_load_format_d16_x:
; GCN: buffer_load_format_d16_x v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; GCN: buffer_load_format_d16_x v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0
define amdgpu_ps half @buffer_load_format_d16_x(<4 x i32> inreg %rsrc) { define amdgpu_ps half @buffer_load_format_d16_x(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call half @llvm.amdgcn.buffer.load.format.f16(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0) %data = call half @llvm.amdgcn.buffer.load.format.f16(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0)
ret half %data ret half %data
} }
; GCN-LABEL: {{^}}buffer_load_format_d16_xy: ; GCN-LABEL: {{^}}buffer_load_format_d16_xy:
; UNPACKED: buffer_load_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; UNPACKED: buffer_load_format_d16_xy v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0
; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PACKED: buffer_load_format_d16_xy v[[FULL:[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 ; PACKED: buffer_load_format_d16_xy v[[FULL:[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0
; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]] ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]]
define amdgpu_ps half @buffer_load_format_d16_xy(<4 x i32> inreg %rsrc) { define amdgpu_ps half @buffer_load_format_d16_xy(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <2 x half> @llvm.amdgcn.buffer.load.format.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0) %data = call <2 x half> @llvm.amdgcn.buffer.load.format.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0)
%elt = extractelement <2 x half> %data, i32 1 %elt = extractelement <2 x half> %data, i32 1
ret half %elt ret half %elt
} }
; GCN-LABEL: {{^}}buffer_load_format_d16_xyz: ; GCN-LABEL: {{^}}buffer_load_format_d16_xyz:
; UNPACKED: buffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; UNPACKED: buffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0
; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PACKED: buffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; PACKED: buffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0
; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
define amdgpu_ps half @buffer_load_format_d16_xyz(<4 x i32> inreg %rsrc) { define amdgpu_ps half @buffer_load_format_d16_xyz(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <3 x half> @llvm.amdgcn.buffer.load.format.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0) %data = call <3 x half> @llvm.amdgcn.buffer.load.format.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0)
%elt = extractelement <3 x half> %data, i32 2 %elt = extractelement <3 x half> %data, i32 2
ret half %elt ret half %elt
} }
; GCN-LABEL: {{^}}buffer_load_format_d16_xyzw: ; GCN-LABEL: {{^}}buffer_load_format_d16_xyzw:
; UNPACKED: buffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; UNPACKED: buffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0
; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PACKED: buffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; PACKED: buffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0
; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]] ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
define amdgpu_ps half @buffer_load_format_d16_xyzw(<4 x i32> inreg %rsrc) { define amdgpu_ps half @buffer_load_format_d16_xyzw(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <4 x half> @llvm.amdgcn.buffer.load.format.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0) %data = call <4 x half> @llvm.amdgcn.buffer.load.format.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0)
%elt = extractelement <4 x half> %data, i32 3 %elt = extractelement <4 x half> %data, i32 3
ret half %elt ret half %elt
} }
declare half @llvm.amdgcn.buffer.load.format.f16(<4 x i32>, i32, i32, i1, i1) declare half @llvm.amdgcn.buffer.load.format.f16(<4 x i32>, i32, i32, i1, i1)
declare <2 x half> @llvm.amdgcn.buffer.load.format.v2f16(<4 x i32>, i32, i32, i1, i1) declare <2 x half> @llvm.amdgcn.buffer.load.format.v2f16(<4 x i32>, i32, i32, i1, i1)
declare <3 x half> @llvm.amdgcn.buffer.load.format.v3f16(<4 x i32>, i32, i32, i1, i1) declare <3 x half> @llvm.amdgcn.buffer.load.format.v3f16(<4 x i32>, i32, i32, i1, i1)
declare <4 x half> @llvm.amdgcn.buffer.load.format.v4f16(<4 x i32>, i32, i32, i1, i1) declare <4 x half> @llvm.amdgcn.buffer.load.format.v4f16(<4 x i32>, i32, i32, i1, i1)

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll

Show First 20 Lines • Show All 451 Lines • ▼ Show 20 Linesdefine amdgpu_ps float @no_fold_fi_imm_soffset(<4 x i32> inreg %rsrc) {
%ret.val = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %alloca.cast, i32 0, i1 false, i1 false) %ret.val = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %alloca.cast, i32 0, i1 false, i1 false)
ret float %ret.val ret float %ret.val
} }
; CHECK-LABEL: {{^}}no_fold_fi_reg_soffset: ; CHECK-LABEL: {{^}}no_fold_fi_reg_soffset:
; CHECK-DAG: v_mov_b32_e32 v[[FI:[0-9]+]], 4{{$}} ; CHECK-DAG: v_mov_b32_e32 v[[FI:[0-9]+]], 4{{$}}
; CHECK-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s ; CHECK-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s
; CHECK: buffer_load_dword v0, v{{\[}}[[FI]]:[[HI]] ; CHECK: buffer_load_dword v0, v[[[FI]]:[[HI]]
define amdgpu_ps float @no_fold_fi_reg_soffset(<4 x i32> inreg %rsrc, i32 inreg %soffset) { define amdgpu_ps float @no_fold_fi_reg_soffset(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
%alloca = alloca i32, addrspace(5) %alloca = alloca i32, addrspace(5)
%alloca.cast = ptrtoint i32 addrspace(5)* %alloca to i32 %alloca.cast = ptrtoint i32 addrspace(5)* %alloca to i32
%ret.val = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %alloca.cast, i32 %soffset, i1 false, i1 false) %ret.val = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %alloca.cast, i32 %soffset, i1 false, i1 false)
ret float %ret.val ret float %ret.val
} }
declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0 declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0
declare <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32>, i32, i32, i1, i1) #0 declare <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32>, i32, i32, i1, i1) #0
declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #0 declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #0
declare i8 @llvm.amdgcn.buffer.load.i8(<4 x i32>, i32, i32, i1, i1) #0 declare i8 @llvm.amdgcn.buffer.load.i8(<4 x i32>, i32, i32, i1, i1) #0
declare i16 @llvm.amdgcn.buffer.load.i16(<4 x i32>, i32, i32, i1, i1) #0 declare i16 @llvm.amdgcn.buffer.load.i16(<4 x i32>, i32, i32, i1, i1) #0
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
attributes #0 = { nounwind readonly } attributes #0 = { nounwind readonly }

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll

Show All 13 Lines
; GCN-LABEL: {{^}}buffer_store_format_d16_xy: ; GCN-LABEL: {{^}}buffer_store_format_d16_xy:
; UNPACKED: s_load_dword [[S_DATA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x10 ; UNPACKED: s_load_dword [[S_DATA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[S_DATA]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[S_DATA]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}} ; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}}
; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]] ; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]]
; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]] ; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]]
; UNPACKED: buffer_store_format_d16_xy v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; UNPACKED: buffer_store_format_d16_xy v[[[V_LO]]:[[V_HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
; PACKED: buffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; PACKED: buffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_kernel void @buffer_store_format_d16_xy(<4 x i32> %rsrc, <2 x half> %data, i32 %index) { define amdgpu_kernel void @buffer_store_format_d16_xy(<4 x i32> %rsrc, <2 x half> %data, i32 %index) {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.format.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.format.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0)
ret void ret void
} }
define amdgpu_kernel void @buffer_store_format_d16_xyz(<4 x i32> %rsrc, <3 x half> %data, i32 %index) { define amdgpu_kernel void @buffer_store_format_d16_xyz(<4 x i32> %rsrc, <3 x half> %data, i32 %index) {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.format.v3f16(<3 x half> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.format.v3f16(<3 x half> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0)
ret void ret void
} }
; GCN-LABEL: {{^}}buffer_store_format_d16_xyzw: ; GCN-LABEL: {{^}}buffer_store_format_d16_xyzw:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x10 ; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}} ; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}}
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]] ; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]] ; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]]
; UNPACKED: buffer_store_format_d16_xyzw v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; UNPACKED: buffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]] ; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]] ; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]]
; PACKED: buffer_store_format_d16_xyzw v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; PACKED: buffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_kernel void @buffer_store_format_d16_xyzw(<4 x i32> %rsrc, <4 x half> %data, i32 %index) { define amdgpu_kernel void @buffer_store_format_d16_xyzw(<4 x i32> %rsrc, <4 x half> %data, i32 %index) {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.format.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.format.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0)
ret void ret void
} }
declare void @llvm.amdgcn.buffer.store.format.f16(half, <4 x i32>, i32, i32, i1, i1) declare void @llvm.amdgcn.buffer.store.format.f16(half, <4 x i32>, i32, i32, i1, i1)
declare void @llvm.amdgcn.buffer.store.format.v2f16(<2 x half>, <4 x i32>, i32, i32, i1, i1) declare void @llvm.amdgcn.buffer.store.format.v2f16(<2 x half>, <4 x i32>, i32, i32, i1, i1)
declare void @llvm.amdgcn.buffer.store.format.v3f16(<3 x half>, <4 x i32>, i32, i32, i1, i1) declare void @llvm.amdgcn.buffer.store.format.v3f16(<3 x half>, <4 x i32>, i32, i32, i1, i1)
declare void @llvm.amdgcn.buffer.store.format.v4f16(<4 x half>, <4 x i32>, i32, i32, i1, i1) declare void @llvm.amdgcn.buffer.store.format.v4f16(<4 x half>, <4 x i32>, i32, i32, i1, i1)

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}s_cvt_pk_i16_i32: ; GCN-LABEL: {{^}}s_cvt_pk_i16_i32:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[SX:[0-9]+]]:[[SY:[0-9]+]]{{\]}}, s[0:1], 0x{{b|2c}} ; GCN-DAG: s_load_dwordx2 s[[[SX:[0-9]+]]:[[SY:[0-9]+]]], s[0:1], 0x{{b|2c}}
; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], s[[SY]] ; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], s[[SY]]
; SI: v_cvt_pk_i16_i32_e32 v{{[0-9]+}}, s[[SX]], [[VY]] ; SI: v_cvt_pk_i16_i32_e32 v{{[0-9]+}}, s[[SX]], [[VY]]
; VI: v_cvt_pk_i16_i32 v{{[0-9]+}}, s[[SX]], [[VY]] ; VI: v_cvt_pk_i16_i32 v{{[0-9]+}}, s[[SX]], [[VY]]
define amdgpu_kernel void @s_cvt_pk_i16_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 { define amdgpu_kernel void @s_cvt_pk_i16_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 {
%result = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %x, i32 %y) %result = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %x, i32 %y)
%r = bitcast <2 x i16> %result to i32 %r = bitcast <2 x i16> %result to i32
store i32 %r, i32 addrspace(1)* %out store i32 %r, i32 addrspace(1)* %out
ret void ret void
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}s_cvt_pk_u16_u32: ; GCN-LABEL: {{^}}s_cvt_pk_u16_u32:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[SX:[0-9]+]]:[[SY:[0-9]+]]{{\]}}, s[0:1], 0x{{b|2c}} ; GCN-DAG: s_load_dwordx2 s[[[SX:[0-9]+]]:[[SY:[0-9]+]]], s[0:1], 0x{{b|2c}}
; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], s[[SY]] ; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], s[[SY]]
; SI: v_cvt_pk_u16_u32_e32 v{{[0-9]+}}, s[[SX]], [[VY]] ; SI: v_cvt_pk_u16_u32_e32 v{{[0-9]+}}, s[[SX]], [[VY]]
; VI: v_cvt_pk_u16_u32 v{{[0-9]+}}, s[[SX]], [[VY]] ; VI: v_cvt_pk_u16_u32 v{{[0-9]+}}, s[[SX]], [[VY]]
define amdgpu_kernel void @s_cvt_pk_u16_u32(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 { define amdgpu_kernel void @s_cvt_pk_u16_u32(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 {
%result = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %x, i32 %y) %result = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %x, i32 %y)
%r = bitcast <2 x i16> %result to i32 %r = bitcast <2 x i16> %result to i32
store i32 %r, i32 addrspace(1)* %out store i32 %r, i32 addrspace(1)* %out
ret void ret void
▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}s_cvt_pknorm_i16_f32: ; GCN-LABEL: {{^}}s_cvt_pknorm_i16_f32:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[SX:[0-9]+]]:[[SY:[0-9]+]]{{\]}}, s[0:1], 0x{{b|2c}} ; GCN-DAG: s_load_dwordx2 s[[[SX:[0-9]+]]:[[SY:[0-9]+]]], s[0:1], 0x{{b|2c}}
; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], s[[SY]] ; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], s[[SY]]
; SI: v_cvt_pknorm_i16_f32_e32 v{{[0-9]+}}, s[[SX]], [[VY]] ; SI: v_cvt_pknorm_i16_f32_e32 v{{[0-9]+}}, s[[SX]], [[VY]]
; VI: v_cvt_pknorm_i16_f32 v{{[0-9]+}}, s[[SX]], [[VY]] ; VI: v_cvt_pknorm_i16_f32 v{{[0-9]+}}, s[[SX]], [[VY]]
define amdgpu_kernel void @s_cvt_pknorm_i16_f32(i32 addrspace(1)* %out, float %x, float %y) #0 { define amdgpu_kernel void @s_cvt_pknorm_i16_f32(i32 addrspace(1)* %out, float %x, float %y) #0 {
%result = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %x, float %y) %result = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %x, float %y)
%r = bitcast <2 x i16> %result to i32 %r = bitcast <2 x i16> %result to i32
store i32 %r, i32 addrspace(1)* %out store i32 %r, i32 addrspace(1)* %out
ret void ret void
▲ Show 20 Lines • Show All 148 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}s_cvt_pknorm_u16_f32: ; GCN-LABEL: {{^}}s_cvt_pknorm_u16_f32:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[SX:[0-9]+]]:[[SY:[0-9]+]]{{\]}}, s[0:1], 0x{{b|2c}} ; GCN-DAG: s_load_dwordx2 s[[[SX:[0-9]+]]:[[SY:[0-9]+]]], s[0:1], 0x{{b|2c}}
; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], s[[SY]] ; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], s[[SY]]
; SI: v_cvt_pknorm_u16_f32_e32 v{{[0-9]+}}, s[[SX]], [[VY]] ; SI: v_cvt_pknorm_u16_f32_e32 v{{[0-9]+}}, s[[SX]], [[VY]]
; VI: v_cvt_pknorm_u16_f32 v{{[0-9]+}}, s[[SX]], [[VY]] ; VI: v_cvt_pknorm_u16_f32 v{{[0-9]+}}, s[[SX]], [[VY]]
define amdgpu_kernel void @s_cvt_pknorm_u16_f32(i32 addrspace(1)* %out, float %x, float %y) #0 { define amdgpu_kernel void @s_cvt_pknorm_u16_f32(i32 addrspace(1)* %out, float %x, float %y) #0 {
%result = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float %x, float %y) %result = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float %x, float %y)
%r = bitcast <2 x i16> %result to i32 %r = bitcast <2 x i16> %result to i32
store i32 %r, i32 addrspace(1)* %out store i32 %r, i32 addrspace(1)* %out
ret void ret void
▲ Show 20 Lines • Show All 148 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll

; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i64 @llvm.amdgcn.dispatch.id() #1 declare i64 @llvm.amdgcn.dispatch.id() #1
; GCN-LABEL: {{^}}dispatch_id: ; GCN-LABEL: {{^}}dispatch_id:
; GCN: .amd_kernel_code_t ; GCN: .amd_kernel_code_t
; GCN: enable_sgpr_dispatch_id = 1 ; GCN: enable_sgpr_dispatch_id = 1
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s6 ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s6
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s7 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s7
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @dispatch_id(i64 addrspace(1)* %out) #0 { define amdgpu_kernel void @dispatch_id(i64 addrspace(1)* %out) #0 {
%tmp0 = call i64 @llvm.amdgcn.dispatch.id() %tmp0 = call i64 @llvm.amdgcn.dispatch.id()
store i64 %tmp0, i64 addrspace(1)* %out store i64 %tmp0, i64 addrspace(1)* %out
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll

Show First 20 Lines • Show All 252 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @test_div_scale_f32_all_scalar_2(float addrspace(1)* %out, [8 x i32], float %a, [8 x i32], float %b) nounwind { define amdgpu_kernel void @test_div_scale_f32_all_scalar_2(float addrspace(1)* %out, [8 x i32], float %a, [8 x i32], float %b) nounwind {
%result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) nounwind readnone %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
%result0 = extractvalue { float, i1 } %result, 0 %result0 = extractvalue { float, i1 } %result, 0
store float %result0, float addrspace(1)* %out, align 4 store float %result0, float addrspace(1)* %out, align 4
ret void ret void
} }
; SI-LABEL: {{^}}test_div_scale_f64_all_scalar_1: ; SI-LABEL: {{^}}test_div_scale_f64_all_scalar_1:
; SI-DAG: s_load_dwordx2 s{{\[}}[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x13 ; SI-DAG: s_load_dwordx2 s[[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]], {{s\[[0-9]+:[0-9]+\]}}, 0x13
; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x1d ; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x1d
; SI-DAG: v_mov_b32_e32 v[[VA_LO:[0-9]+]], s[[A_LO]] ; SI-DAG: v_mov_b32_e32 v[[VA_LO:[0-9]+]], s[[A_LO]]
; SI-DAG: v_mov_b32_e32 v[[VA_HI:[0-9]+]], s[[A_HI]] ; SI-DAG: v_mov_b32_e32 v[[VA_HI:[0-9]+]], s[[A_HI]]
; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], v{{\[}}[[VA_LO]]:[[VA_HI]]{{\]}} ; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], v[[[VA_LO]]:[[VA_HI]]]
; SI: buffer_store_dwordx2 [[RESULT0]] ; SI: buffer_store_dwordx2 [[RESULT0]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @test_div_scale_f64_all_scalar_1(double addrspace(1)* %out, [8 x i32], double %a, [8 x i32], double %b) nounwind { define amdgpu_kernel void @test_div_scale_f64_all_scalar_1(double addrspace(1)* %out, [8 x i32], double %a, [8 x i32], double %b) nounwind {
%result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 false) nounwind readnone %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
%result0 = extractvalue { double, i1 } %result, 0 %result0 = extractvalue { double, i1 } %result, 0
store double %result0, double addrspace(1)* %out, align 8 store double %result0, double addrspace(1)* %out, align 8
ret void ret void
} }
; SI-LABEL: {{^}}test_div_scale_f64_all_scalar_2: ; SI-LABEL: {{^}}test_div_scale_f64_all_scalar_2:
; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x13 ; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x13
; SI-DAG: s_load_dwordx2 s{{\[}}[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x1d ; SI-DAG: s_load_dwordx2 s[[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]], {{s\[[0-9]+:[0-9]+\]}}, 0x1d
; SI-DAG: v_mov_b32_e32 v[[VB_LO:[0-9]+]], s[[B_LO]] ; SI-DAG: v_mov_b32_e32 v[[VB_LO:[0-9]+]], s[[B_LO]]
; SI-DAG: v_mov_b32_e32 v[[VB_HI:[0-9]+]], s[[B_HI]] ; SI-DAG: v_mov_b32_e32 v[[VB_HI:[0-9]+]], s[[B_HI]]
; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], v{{\[}}[[VB_LO]]:[[VB_HI]]{{\]}}, [[A]] ; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], v[[[VB_LO]]:[[VB_HI]]], [[A]]
; SI: buffer_store_dwordx2 [[RESULT0]] ; SI: buffer_store_dwordx2 [[RESULT0]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @test_div_scale_f64_all_scalar_2(double addrspace(1)* %out, [8 x i32], double %a, [8 x i32], double %b) nounwind { define amdgpu_kernel void @test_div_scale_f64_all_scalar_2(double addrspace(1)* %out, [8 x i32], double %a, [8 x i32], double %b) nounwind {
%result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) nounwind readnone %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
%result0 = extractvalue { double, i1 } %result, 0 %result0 = extractvalue { double, i1 } %result, 0
store double %result0, double addrspace(1)* %out, align 8 store double %result0, double addrspace(1)* %out, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 148 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_div_scale_f32_undef_undef_val(float addrspace(1)* %out) #0 {
%result0 = extractvalue { float, i1 } %result, 0 %result0 = extractvalue { float, i1 } %result, 0
store float %result0, float addrspace(1)* %out, align 4 store float %result0, float addrspace(1)* %out, align 4
ret void ret void
} }
; SI-LABEL: {{^}}test_div_scale_f64_val_undef_val: ; SI-LABEL: {{^}}test_div_scale_f64_val_undef_val:
; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}} ; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}}
; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0x40200000 ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0x40200000
; SI: v_div_scale_f64 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, v[0:1], s{{\[}}[[K_LO]]:[[K_HI]]{{\]}} ; SI: v_div_scale_f64 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s[[[K_LO]]:[[K_HI]]], v[0:1], s[[[K_LO]]:[[K_HI]]]
define amdgpu_kernel void @test_div_scale_f64_val_undef_val(double addrspace(1)* %out) #0 { define amdgpu_kernel void @test_div_scale_f64_val_undef_val(double addrspace(1)* %out) #0 {
%result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double 8.0, double undef, i1 false) %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double 8.0, double undef, i1 false)
%result0 = extractvalue { double, i1 } %result, 0 %result0 = extractvalue { double, i1 } %result, 0
store double %result0, double addrspace(1)* %out, align 8 store double %result0, double addrspace(1)* %out, align 8
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone speculatable } attributes #1 = { nounwind readnone speculatable }

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; NOLOOP: ds_gws_barrier v0 offset:63 gds{{$}} ; NOLOOP: ds_gws_barrier v0 offset:63 gds{{$}}
define amdgpu_kernel void @gws_barrier_offset63(i32 %val) #0 { define amdgpu_kernel void @gws_barrier_offset63(i32 %val) #0 {
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 63) call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 63)
ret void ret void
} }
; FIXME: Should be able to shift directly into m0 ; FIXME: Should be able to shift directly into m0
; GCN-LABEL: {{^}}gws_barrier_sgpr_offset: ; GCN-LABEL: {{^}}gws_barrier_sgpr_offset:
; NOLOOP-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}} ; NOLOOP-DAG: s_load_dwordx2 s[[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]]
; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16 ; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}} ; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
; NOLOOP-GISEL-DAG: s_lshl_b32 m0, s[[OFFSET]], 16 ; NOLOOP-GISEL-DAG: s_lshl_b32 m0, s[[OFFSET]], 16
; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]] ; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]]
; NOLOOP: ds_gws_barrier [[GWS_VAL]] gds{{$}} ; NOLOOP: ds_gws_barrier [[GWS_VAL]] gds{{$}}
define amdgpu_kernel void @gws_barrier_sgpr_offset(i32 %val, i32 %offset) #0 { define amdgpu_kernel void @gws_barrier_sgpr_offset(i32 %val, i32 %offset) #0 {
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 %offset) call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 %offset)
ret void ret void
} }
; Variable offset in SGPR with constant add ; Variable offset in SGPR with constant add
; GCN-LABEL: {{^}}gws_barrier_sgpr_offset_add1: ; GCN-LABEL: {{^}}gws_barrier_sgpr_offset_add1:
; NOLOOP-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}} ; NOLOOP-DAG: s_load_dwordx2 s[[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]]
; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16 ; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}} ; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
; NOLOOP-GISEL-DAG: s_lshl_b32 m0, s[[OFFSET]], 16 ; NOLOOP-GISEL-DAG: s_lshl_b32 m0, s[[OFFSET]], 16
; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]] ; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]]
; NOLOOP: ds_gws_barrier [[GWS_VAL]] offset:1 gds{{$}} ; NOLOOP: ds_gws_barrier [[GWS_VAL]] offset:1 gds{{$}}
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll

Show All 40 Lines
; LOOP-NEXT: s_cbranch_scc1 [[LOOP]] ; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]
define amdgpu_kernel void @gws_init_offset63(i32 %val) #0 { define amdgpu_kernel void @gws_init_offset63(i32 %val) #0 {
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 63) call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 63)
ret void ret void
} }
; FIXME: Should be able to shift directly into m0 ; FIXME: Should be able to shift directly into m0
; GCN-LABEL: {{^}}gws_init_sgpr_offset: ; GCN-LABEL: {{^}}gws_init_sgpr_offset:
; NOLOOP-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}} ; NOLOOP-DAG: s_load_dwordx2 s[[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]]
; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16 ; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}} ; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
; NOLOOP-GISEL-DAG: s_lshl_b32 m0, s[[OFFSET]], 16 ; NOLOOP-GISEL-DAG: s_lshl_b32 m0, s[[OFFSET]], 16
; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]] ; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]]
; NOLOOP: ds_gws_init [[GWS_VAL]] gds{{$}} ; NOLOOP: ds_gws_init [[GWS_VAL]] gds{{$}}
define amdgpu_kernel void @gws_init_sgpr_offset(i32 %val, i32 %offset) #0 { define amdgpu_kernel void @gws_init_sgpr_offset(i32 %val, i32 %offset) #0 {
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset) call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset)
ret void ret void
} }
; Variable offset in SGPR with constant add ; Variable offset in SGPR with constant add
; GCN-LABEL: {{^}}gws_init_sgpr_offset_add1: ; GCN-LABEL: {{^}}gws_init_sgpr_offset_add1:
; NOLOOP-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}} ; NOLOOP-DAG: s_load_dwordx2 s[[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]]
; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16 ; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}} ; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
; NOLOOP-GISEL-DAG: s_lshl_b32 m0, s[[OFFSET]], 16 ; NOLOOP-GISEL-DAG: s_lshl_b32 m0, s[[OFFSET]], 16
; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]] ; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]]
; NOLOOP: ds_gws_init [[GWS_VAL]] offset:1 gds{{$}} ; NOLOOP: ds_gws_init [[GWS_VAL]] offset:1 gds{{$}}
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; GCN-LABEL: {{^}}is_private_vgpr: ; GCN-LABEL: {{^}}is_private_vgpr:
; GCN-DAG: {{flat|global}}_load_dwordx2 v{{\[[0-9]+}}:[[PTR_HI:[0-9]+]]{{\]}} ; GCN-DAG: {{flat|global}}_load_dwordx2 v{{\[[0-9]+}}:[[PTR_HI:[0-9]+]]]
; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11 ; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11
; GFX9-DAG: s_getreg_b32 [[APERTURE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16) ; GFX9-DAG: s_getreg_b32 [[APERTURE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16)
; GFX9: s_lshl_b32 [[APERTURE]], [[APERTURE]], 16 ; GFX9: s_lshl_b32 [[APERTURE]], [[APERTURE]], 16
; GCN: v_cmp_eq_u32_e32 vcc, [[APERTURE]], v[[PTR_HI]] ; GCN: v_cmp_eq_u32_e32 vcc, [[APERTURE]], v[[PTR_HI]]
; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
define amdgpu_kernel void @is_private_vgpr(i8* addrspace(1)* %ptr.ptr) { define amdgpu_kernel void @is_private_vgpr(i8* addrspace(1)* %ptr.ptr) {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i8*, i8* addrspace(1)* %ptr.ptr, i32 %id %gep = getelementptr inbounds i8*, i8* addrspace(1)* %ptr.ptr, i32 %id
Show All 36 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; GCN-LABEL: {{^}}is_local_vgpr: ; GCN-LABEL: {{^}}is_local_vgpr:
; GCN-DAG: {{flat|global}}_load_dwordx2 v{{\[[0-9]+}}:[[PTR_HI:[0-9]+]]{{\]}} ; GCN-DAG: {{flat|global}}_load_dwordx2 v{{\[[0-9]+}}:[[PTR_HI:[0-9]+]]]
; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10 ; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10
; GFX9-DAG: s_getreg_b32 [[APERTURE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) ; GFX9-DAG: s_getreg_b32 [[APERTURE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16)
; GFX9: s_lshl_b32 [[APERTURE]], [[APERTURE]], 16 ; GFX9: s_lshl_b32 [[APERTURE]], [[APERTURE]], 16
; GCN: v_cmp_eq_u32_e32 vcc, [[APERTURE]], v[[PTR_HI]] ; GCN: v_cmp_eq_u32_e32 vcc, [[APERTURE]], v[[PTR_HI]]
; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
define amdgpu_kernel void @is_local_vgpr(i8* addrspace(1)* %ptr.ptr) { define amdgpu_kernel void @is_local_vgpr(i8* addrspace(1)* %ptr.ptr) {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll

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; GFX90A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} ; GFX90A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
; GFX90A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} ; GFX90A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
; GFX90A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} ; GFX90A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
; GFX90A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} ; GFX90A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
; GFX90A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} ; GFX90A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
; GFX90A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} ; GFX90A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
; GFX90A-DAG: v_mov_b32_e32 v[[TWO:[0-9]+]], 2 ; GFX90A-DAG: v_mov_b32_e32 v[[TWO:[0-9]+]], 2
; GFX90A-DAG: v_mov_b32_e32 v[[ONE:[0-9]+]], 1 ; GFX90A-DAG: v_mov_b32_e32 v[[ONE:[0-9]+]], 1
; GFX90A: v_mfma_f32_32x32x4bf16_1k a[{{[0-9]+:[0-9]+}}], v{{\[}}[[ONE]]:{{[0-9]+}}], v{{\[}}[[TWO]]:{{[0-9]+}}], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3 ; GFX90A: v_mfma_f32_32x32x4bf16_1k a[{{[0-9]+:[0-9]+}}], v[[[ONE]]:{{[0-9]+}}], v[[[TWO]]:{{[0-9]+}}], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
; GCN-NOT: v_accvgpr_read_b32 ; GCN-NOT: v_accvgpr_read_b32
; GCN-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, a[{{[0-9:]+}}] ; GCN-COUNT-8: global_store_dwordx4 v{{[0-9]+}}, a[{{[0-9:]+}}]
define amdgpu_kernel void @test_mfma_f32_32x32x4bf16_1k(<32 x float> addrspace(1)* %arg) { define amdgpu_kernel void @test_mfma_f32_32x32x4bf16_1k(<32 x float> addrspace(1)* %arg) {
bb: bb:
%in.1 = load <32 x float>, <32 x float> addrspace(1)* %arg %in.1 = load <32 x float>, <32 x float> addrspace(1)* %arg
%a = bitcast i64 1 to <4 x i16> %a = bitcast i64 1 to <4 x i16>
%b = bitcast i64 2 to <4 x i16> %b = bitcast i64 2 to <4 x i16>
%mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4bf16.1k(<4 x i16> %a, <4 x i16> %b, <32 x float> %in.1, i32 1, i32 2, i32 3) %mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4bf16.1k(<4 x i16> %a, <4 x i16> %b, <32 x float> %in.1, i32 1, i32 2, i32 3)
store <32 x float> %mai.1, <32 x float> addrspace(1)* %arg store <32 x float> %mai.1, <32 x float> addrspace(1)* %arg
ret void ret void
} }
; GCN-LABEL: {{^}}test_mfma_f32_16x16x4bf16_1k: ; GCN-LABEL: {{^}}test_mfma_f32_16x16x4bf16_1k:
; GCN-DAG: s_load_dwordx16 ; GCN-DAG: s_load_dwordx16
; GCN-DAG: v_mov_b32_e32 v[[TWO:[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 v[[TWO:[0-9]+]], 2
; GCN-DAG: v_mov_b32_e32 v[[ONE:[0-9]+]], 1 ; GCN-DAG: v_mov_b32_e32 v[[ONE:[0-9]+]], 1
; GFX90A-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} ; GFX90A-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
; GFX90A: v_mfma_f32_16x16x4bf16_1k a[{{[0-9]+:[0-9]+}}], v{{\[}}[[ONE]]:{{[0-9]+}}], v{{\[}}[[TWO]]:{{[0-9]+}}], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3 ; GFX90A: v_mfma_f32_16x16x4bf16_1k a[{{[0-9]+:[0-9]+}}], v[[[ONE]]:{{[0-9]+}}], v[[[TWO]]:{{[0-9]+}}], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
; GCN-NOT: v_accvgpr_read_b32 ; GCN-NOT: v_accvgpr_read_b32
; GCN-COUNT-4: global_store_dwordx4 v{{[0-9]+}}, a[{{[0-9:]+}}] ; GCN-COUNT-4: global_store_dwordx4 v{{[0-9]+}}, a[{{[0-9:]+}}]
define amdgpu_kernel void @test_mfma_f32_16x16x4bf16_1k(<16 x float> addrspace(1)* %arg) { define amdgpu_kernel void @test_mfma_f32_16x16x4bf16_1k(<16 x float> addrspace(1)* %arg) {
bb: bb:
%in.1 = load <16 x float>, <16 x float> addrspace(1)* %arg %in.1 = load <16 x float>, <16 x float> addrspace(1)* %arg
%a = bitcast i64 1 to <4 x i16> %a = bitcast i64 1 to <4 x i16>
%b = bitcast i64 2 to <4 x i16> %b = bitcast i64 2 to <4 x i16>
%mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.16x16x4bf16.1k(<4 x i16> %a, <4 x i16> %b, <16 x float> %in.1, i32 1, i32 2, i32 3) %mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.16x16x4bf16.1k(<4 x i16> %a, <4 x i16> %b, <16 x float> %in.1, i32 1, i32 2, i32 3)
store <16 x float> %mai.1, <16 x float> addrspace(1)* %arg store <16 x float> %mai.1, <16 x float> addrspace(1)* %arg
ret void ret void
} }
; GCN-LABEL: {{^}}test_mfma_f32_4x4x4bf16_1k: ; GCN-LABEL: {{^}}test_mfma_f32_4x4x4bf16_1k:
; GCN-DAG: s_load_dwordx4 ; GCN-DAG: s_load_dwordx4
; GCN-DAG: v_mov_b32_e32 v[[TWO:[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 v[[TWO:[0-9]+]], 2
; GCN-DAG: v_mov_b32_e32 v[[ONE:[0-9]+]], 1 ; GCN-DAG: v_mov_b32_e32 v[[ONE:[0-9]+]], 1
; GFX90A-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} ; GFX90A-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
; GFX90A: v_mfma_f32_4x4x4bf16_1k [[RES:a\[[0-9]+:[0-9]+\]]], v{{\[}}[[ONE]]:{{[0-9]+}}], v{{\[}}[[TWO]]:{{[0-9]+}}], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3 ; GFX90A: v_mfma_f32_4x4x4bf16_1k [[RES:a\[[0-9]+:[0-9]+\]]], v[[[ONE]]:{{[0-9]+}}], v[[[TWO]]:{{[0-9]+}}], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
; GCN-NOT: v_accvgpr_read_b32 ; GCN-NOT: v_accvgpr_read_b32
; GCN: global_store_dwordx4 v{{[0-9]+}}, [[RES]], ; GCN: global_store_dwordx4 v{{[0-9]+}}, [[RES]],
define amdgpu_kernel void @test_mfma_f32_4x4x4bf16_1k(<4 x float> addrspace(1)* %arg) { define amdgpu_kernel void @test_mfma_f32_4x4x4bf16_1k(<4 x float> addrspace(1)* %arg) {
bb: bb:
%in.1 = load <4 x float>, <4 x float> addrspace(1)* %arg %in.1 = load <4 x float>, <4 x float> addrspace(1)* %arg
%a = bitcast i64 1 to <4 x i16> %a = bitcast i64 1 to <4 x i16>
%b = bitcast i64 2 to <4 x i16> %b = bitcast i64 2 to <4 x i16>
%mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x4bf16.1k(<4 x i16> %a, <4 x i16> %b, <4 x float> %in.1, i32 1, i32 2, i32 3) %mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x4bf16.1k(<4 x i16> %a, <4 x i16> %b, <4 x float> %in.1, i32 1, i32 2, i32 3)
store <4 x float> %mai.1, <4 x float> addrspace(1)* %arg store <4 x float> %mai.1, <4 x float> addrspace(1)* %arg
ret void ret void
} }
; GCN-LABEL: {{^}}test_mfma_f32_32x32x8bf16_1k: ; GCN-LABEL: {{^}}test_mfma_f32_32x32x8bf16_1k:
; GCN-DAG: s_load_dwordx16 ; GCN-DAG: s_load_dwordx16
; GCN-DAG: v_mov_b32_e32 v[[TWO:[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 v[[TWO:[0-9]+]], 2
; GCN-DAG: v_mov_b32_e32 v[[ONE:[0-9]+]], 1 ; GCN-DAG: v_mov_b32_e32 v[[ONE:[0-9]+]], 1
; GFX90A-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} ; GFX90A-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
; GFX90A: v_mfma_f32_32x32x8bf16_1k a[{{[0-9]+:[0-9]+}}], v{{\[}}[[ONE]]:{{[0-9]+}}], v{{\[}}[[TWO]]:{{[0-9]+}}], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3 ; GFX90A: v_mfma_f32_32x32x8bf16_1k a[{{[0-9]+:[0-9]+}}], v[[[ONE]]:{{[0-9]+}}], v[[[TWO]]:{{[0-9]+}}], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
; GCN-NOT: v_accvgpr_read_b32 ; GCN-NOT: v_accvgpr_read_b32
; GCN-COUNT-4: global_store_dwordx4 v{{[0-9]+}}, a[{{[0-9:]+}}] ; GCN-COUNT-4: global_store_dwordx4 v{{[0-9]+}}, a[{{[0-9:]+}}]
define amdgpu_kernel void @test_mfma_f32_32x32x8bf16_1k(<16 x float> addrspace(1)* %arg) { define amdgpu_kernel void @test_mfma_f32_32x32x8bf16_1k(<16 x float> addrspace(1)* %arg) {
bb: bb:
%in.1 = load <16 x float>, <16 x float> addrspace(1)* %arg %in.1 = load <16 x float>, <16 x float> addrspace(1)* %arg
%a = bitcast i64 1 to <4 x i16> %a = bitcast i64 1 to <4 x i16>
%b = bitcast i64 2 to <4 x i16> %b = bitcast i64 2 to <4 x i16>
%mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.32x32x8bf16.1k(<4 x i16> %a, <4 x i16> %b, <16 x float> %in.1, i32 1, i32 2, i32 3) %mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.32x32x8bf16.1k(<4 x i16> %a, <4 x i16> %b, <16 x float> %in.1, i32 1, i32 2, i32 3)
store <16 x float> %mai.1, <16 x float> addrspace(1)* %arg store <16 x float> %mai.1, <16 x float> addrspace(1)* %arg
ret void ret void
} }
; GCN-LABEL: {{^}}test_mfma_f32_16x16x16bf16_1k: ; GCN-LABEL: {{^}}test_mfma_f32_16x16x16bf16_1k:
; GCN-DAG: s_load_dwordx4 ; GCN-DAG: s_load_dwordx4
; GCN-DAG: v_mov_b32_e32 v[[TWO:[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 v[[TWO:[0-9]+]], 2
; GCN-DAG: v_mov_b32_e32 v[[ONE:[0-9]+]], 1 ; GCN-DAG: v_mov_b32_e32 v[[ONE:[0-9]+]], 1
; GFX90A-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} ; GFX90A-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
; GFX90A: v_mfma_f32_16x16x16bf16_1k [[RES:a\[[0-9]+:[0-9]+\]]], v{{\[}}[[ONE]]:{{[0-9]+}}], v{{\[}}[[TWO]]:{{[0-9]+}}], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3 ; GFX90A: v_mfma_f32_16x16x16bf16_1k [[RES:a\[[0-9]+:[0-9]+\]]], v[[[ONE]]:{{[0-9]+}}], v[[[TWO]]:{{[0-9]+}}], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
; GCN-NOT: v_accvgpr_read_b32 ; GCN-NOT: v_accvgpr_read_b32
; GCN: global_store_dwordx4 v{{[0-9]+}}, [[RES]], ; GCN: global_store_dwordx4 v{{[0-9]+}}, [[RES]],
define amdgpu_kernel void @test_mfma_f32_16x16x16bf16_1k(<4 x float> addrspace(1)* %arg) { define amdgpu_kernel void @test_mfma_f32_16x16x16bf16_1k(<4 x float> addrspace(1)* %arg) {
bb: bb:
%in.1 = load <4 x float>, <4 x float> addrspace(1)* %arg %in.1 = load <4 x float>, <4 x float> addrspace(1)* %arg
%a = bitcast i64 1 to <4 x i16> %a = bitcast i64 1 to <4 x i16>
%b = bitcast i64 2 to <4 x i16> %b = bitcast i64 2 to <4 x i16>
%mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16bf16.1k(<4 x i16> %a, <4 x i16> %b, <4 x float> %in.1, i32 1, i32 2, i32 3) %mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16bf16.1k(<4 x i16> %a, <4 x i16> %b, <4 x float> %in.1, i32 1, i32 2, i32 3)
▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll

Show First 20 Lines • Show All 405 Lines • ▼ Show 20 Linesbb:
store <16 x float> %mai.1, <16 x float> addrspace(1)* %arg store <16 x float> %mai.1, <16 x float> addrspace(1)* %arg
ret void ret void
} }
; GCN-LABEL: {{^}}test_mfma_f32_32x32x8f16_imm_splat: ; GCN-LABEL: {{^}}test_mfma_f32_32x32x8f16_imm_splat:
; GCN-DAG: v_mov_b32_e32 v[[TWO:[0-9]+]], 0x40004000 ; GCN-DAG: v_mov_b32_e32 v[[TWO:[0-9]+]], 0x40004000
; GCN-DAG: v_mov_b32_e32 v[[ONE:[0-9]+]], 0x3c003c00 ; GCN-DAG: v_mov_b32_e32 v[[ONE:[0-9]+]], 0x3c003c00
; NOLIT-SRCC-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, 1.0 ; NOLIT-SRCC-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, 1.0
; NOLIT-SRCC: v_mfma_f32_32x32x8f16 a[{{[0-9]+:[0-9]+}}], v{{\[}}[[ONE]]:{{[0-9]+}}], v{{\[}}[[TWO]]:{{[0-9]+}}], a[{{[0-9:]+}}] ; NOLIT-SRCC: v_mfma_f32_32x32x8f16 a[{{[0-9]+:[0-9]+}}], v[[[ONE]]:{{[0-9]+}}], v[[[TWO]]:{{[0-9]+}}], a[{{[0-9:]+}}]
; LIT-SRCC: v_mfma_f32_32x32x8f16 a[{{[0-9]+:[0-9]+}}], v{{\[}}[[ONE]]:{{[0-9]+}}], v{{\[}}[[TWO]]:{{[0-9]+}}], 1.0 ; LIT-SRCC: v_mfma_f32_32x32x8f16 a[{{[0-9]+:[0-9]+}}], v[[[ONE]]:{{[0-9]+}}], v[[[TWO]]:{{[0-9]+}}], 1.0
; GFX90A: v_mfma_f32_32x32x8f16 a[{{[0-9]+:[0-9]+}}], v{{\[}}[[ONE]]:{{[0-9]+}}], v{{\[}}[[TWO]]:{{[0-9]+}}], 1.0 ; GFX90A: v_mfma_f32_32x32x8f16 a[{{[0-9]+:[0-9]+}}], v[[[ONE]]:{{[0-9]+}}], v[[[TWO]]:{{[0-9]+}}], 1.0
; GFX908-COUNT-16: v_accvgpr_read_b32 ; GFX908-COUNT-16: v_accvgpr_read_b32
; GFX908: global_store_dwordx4 ; GFX908: global_store_dwordx4
; GFX90A-NOT: v_accvgpr_read_b32 ; GFX90A-NOT: v_accvgpr_read_b32
; GFX90A-COUNT-4: global_store_dwordx4 {{v[0-9]+}}, a[{{[0-9:]+}}], ; GFX90A-COUNT-4: global_store_dwordx4 {{v[0-9]+}}, a[{{[0-9:]+}}],
define amdgpu_kernel void @test_mfma_f32_32x32x8f16_imm_splat(<16 x float> addrspace(1)* %arg) { define amdgpu_kernel void @test_mfma_f32_32x32x8f16_imm_splat(<16 x float> addrspace(1)* %arg) {
bb: bb:
%mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.32x32x8f16(<4 x half> <half 1.0, half 1.0, half 1.0, half 1.0>, <4 x half> <half 2.0, half 2.0, half 2.0, half 2.0>, <16 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, i32 0, i32 0, i32 0) %mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.32x32x8f16(<4 x half> <half 1.0, half 1.0, half 1.0, half 1.0>, <4 x half> <half 2.0, half 2.0, half 2.0, half 2.0>, <16 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, i32 0, i32 0, i32 0)
store <16 x float> %mai.1, <16 x float> addrspace(1)* %arg store <16 x float> %mai.1, <16 x float> addrspace(1)* %arg
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.d16.ll

; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s
; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
; GCN-LABEL: {{^}}buffer_load_format_d16_x: ; GCN-LABEL: {{^}}buffer_load_format_d16_x:
; GCN: buffer_load_format_d16_x v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; GCN: buffer_load_format_d16_x v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0
define amdgpu_ps half @buffer_load_format_d16_x(<4 x i32> inreg %rsrc) { define amdgpu_ps half @buffer_load_format_d16_x(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call half @llvm.amdgcn.raw.buffer.load.format.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) %data = call half @llvm.amdgcn.raw.buffer.load.format.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
ret half %data ret half %data
} }
; GCN-LABEL: {{^}}buffer_load_format_d16_xy: ; GCN-LABEL: {{^}}buffer_load_format_d16_xy:
; UNPACKED: buffer_load_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; UNPACKED: buffer_load_format_d16_xy v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0
; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PACKED: buffer_load_format_d16_xy v[[FULL:[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 ; PACKED: buffer_load_format_d16_xy v[[FULL:[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0
; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]] ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]]
define amdgpu_ps half @buffer_load_format_d16_xy(<4 x i32> inreg %rsrc) { define amdgpu_ps half @buffer_load_format_d16_xy(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <2 x half> @llvm.amdgcn.raw.buffer.load.format.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) %data = call <2 x half> @llvm.amdgcn.raw.buffer.load.format.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%elt = extractelement <2 x half> %data, i32 1 %elt = extractelement <2 x half> %data, i32 1
ret half %elt ret half %elt
} }
; GCN-LABEL: {{^}}buffer_load_format_d16_xyz: ; GCN-LABEL: {{^}}buffer_load_format_d16_xyz:
; UNPACKED: buffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; UNPACKED: buffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0
; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PACKED: buffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; PACKED: buffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0
define amdgpu_ps half @buffer_load_format_d16_xyz(<4 x i32> inreg %rsrc) { define amdgpu_ps half @buffer_load_format_d16_xyz(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <3 x half> @llvm.amdgcn.raw.buffer.load.format.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) %data = call <3 x half> @llvm.amdgcn.raw.buffer.load.format.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%elt = extractelement <3 x half> %data, i32 2 %elt = extractelement <3 x half> %data, i32 2
ret half %elt ret half %elt
} }
; GCN-LABEL: {{^}}buffer_load_format_d16_xyzw: ; GCN-LABEL: {{^}}buffer_load_format_d16_xyzw:
; UNPACKED: buffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; UNPACKED: buffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0
; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PACKED: buffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 ; PACKED: buffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0
; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]] ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
define amdgpu_ps half @buffer_load_format_d16_xyzw(<4 x i32> inreg %rsrc) { define amdgpu_ps half @buffer_load_format_d16_xyzw(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <4 x half> @llvm.amdgcn.raw.buffer.load.format.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) %data = call <4 x half> @llvm.amdgcn.raw.buffer.load.format.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%elt = extractelement <4 x half> %data, i32 3 %elt = extractelement <4 x half> %data, i32 3
ret half %elt ret half %elt
} }
declare half @llvm.amdgcn.raw.buffer.load.format.f16(<4 x i32>, i32, i32, i32) declare half @llvm.amdgcn.raw.buffer.load.format.f16(<4 x i32>, i32, i32, i32)
declare <2 x half> @llvm.amdgcn.raw.buffer.load.format.v2f16(<4 x i32>, i32, i32, i32) declare <2 x half> @llvm.amdgcn.raw.buffer.load.format.v2f16(<4 x i32>, i32, i32, i32)
declare <3 x half> @llvm.amdgcn.raw.buffer.load.format.v3f16(<4 x i32>, i32, i32, i32) declare <3 x half> @llvm.amdgcn.raw.buffer.load.format.v3f16(<4 x i32>, i32, i32, i32)
declare <4 x half> @llvm.amdgcn.raw.buffer.load.format.v4f16(<4 x i32>, i32, i32, i32) declare <4 x half> @llvm.amdgcn.raw.buffer.load.format.v4f16(<4 x i32>, i32, i32, i32)

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.d16.ll

Show All 13 Lines
; GCN-LABEL: {{^}}buffer_store_format_d16_xy: ; GCN-LABEL: {{^}}buffer_store_format_d16_xy:
; UNPACKED: s_load_dword [[S_DATA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x10 ; UNPACKED: s_load_dword [[S_DATA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[S_DATA]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[S_DATA]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}} ; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}}
; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]] ; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]]
; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]] ; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]]
; UNPACKED: buffer_store_format_d16_xy v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen ; UNPACKED: buffer_store_format_d16_xy v[[[V_LO]]:[[V_HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; PACKED: buffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen ; PACKED: buffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
define amdgpu_kernel void @buffer_store_format_d16_xy(<4 x i32> %rsrc, <2 x half> %data, i32 %voffset) { define amdgpu_kernel void @buffer_store_format_d16_xy(<4 x i32> %rsrc, <2 x half> %data, i32 %voffset) {
main_body: main_body:
call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0) call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
ret void ret void
} }
; GCN-LABEL: {{^}}buffer_store_format_d16_xyz: ; GCN-LABEL: {{^}}buffer_store_format_d16_xyz:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x10 ; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}} ; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}}
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]] ; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED1]] ; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED1]]
; UNPACKED: buffer_store_format_d16_xyz v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen ; UNPACKED: buffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; PACKED: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}} ; PACKED: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]] ; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED0]] ; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED0]]
; PACKED: buffer_store_format_d16_xyz v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen ; PACKED: buffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
define amdgpu_kernel void @buffer_store_format_d16_xyz(<4 x i32> %rsrc, <4 x half> %data, i32 %voffset) { define amdgpu_kernel void @buffer_store_format_d16_xyz(<4 x i32> %rsrc, <4 x half> %data, i32 %voffset) {
main_body: main_body:
%data_subvec = shufflevector <4 x half> %data, <4 x half> undef, <3 x i32> <i32 0, i32 1, i32 2> %data_subvec = shufflevector <4 x half> %data, <4 x half> undef, <3 x i32> <i32 0, i32 1, i32 2>
call void @llvm.amdgcn.raw.buffer.store.format.v3f16(<3 x half> %data_subvec, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0) call void @llvm.amdgcn.raw.buffer.store.format.v3f16(<3 x half> %data_subvec, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
ret void ret void
} }
; GCN-LABEL: {{^}}buffer_store_format_d16_xyzw: ; GCN-LABEL: {{^}}buffer_store_format_d16_xyzw:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x10 ; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}} ; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}}
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]] ; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]] ; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]]
; UNPACKED: buffer_store_format_d16_xyzw v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen ; UNPACKED: buffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]] ; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]] ; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]]
; PACKED: buffer_store_format_d16_xyzw v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen ; PACKED: buffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
define amdgpu_kernel void @buffer_store_format_d16_xyzw(<4 x i32> %rsrc, <4 x half> %data, i32 %voffset) { define amdgpu_kernel void @buffer_store_format_d16_xyzw(<4 x i32> %rsrc, <4 x half> %data, i32 %voffset) {
main_body: main_body:
call void @llvm.amdgcn.raw.buffer.store.format.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0) call void @llvm.amdgcn.raw.buffer.store.format.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
ret void ret void
} }
declare void @llvm.amdgcn.raw.buffer.store.format.f16(half, <4 x i32>, i32, i32, i32) declare void @llvm.amdgcn.raw.buffer.store.format.f16(half, <4 x i32>, i32, i32, i32)
declare void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half>, <4 x i32>, i32, i32, i32) declare void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half>, <4 x i32>, i32, i32, i32)
declare void @llvm.amdgcn.raw.buffer.store.format.v3f16(<3 x half>, <4 x i32>, i32, i32, i32) declare void @llvm.amdgcn.raw.buffer.store.format.v3f16(<3 x half>, <4 x i32>, i32, i32, i32)
declare void @llvm.amdgcn.raw.buffer.store.format.v4f16(<4 x half>, <4 x i32>, i32, i32, i32) declare void @llvm.amdgcn.raw.buffer.store.format.v4f16(<4 x half>, <4 x i32>, i32, i32, i32)

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll

; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefixes=GCN,UNPACKED,PREGFX10,PREGFX10-UNPACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefixes=GCN,UNPACKED,PREGFX10,PREGFX10-UNPACKED %s
; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED,PREGFX10,PREGFX10-PACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED,PREGFX10,PREGFX10-PACKED %s
; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED,PREGFX10,PREGFX10-PACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED,PREGFX10,PREGFX10-PACKED %s
; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED,GFX10,GFX10-PACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED,GFX10,GFX10-PACKED %s
; GCN-LABEL: {{^}}tbuffer_load_d16_x: ; GCN-LABEL: {{^}}tbuffer_load_d16_x:
; PREGFX10: tbuffer_load_format_d16_x v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; PREGFX10: tbuffer_load_format_d16_x v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; GFX10: tbuffer_load_format_d16_x v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] ; GFX10: tbuffer_load_format_d16_x v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT]
define amdgpu_ps half @tbuffer_load_d16_x(<4 x i32> inreg %rsrc) { define amdgpu_ps half @tbuffer_load_d16_x(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 22, i32 0) %data = call half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 22, i32 0)
ret half %data ret half %data
} }
; GCN-LABEL: {{^}}tbuffer_load_d16_xy: ; GCN-LABEL: {{^}}tbuffer_load_d16_xy:
; PREGFX10-UNPACKED: tbuffer_load_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; PREGFX10-UNPACKED: tbuffer_load_format_d16_xy v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PREGFX10-PACKED: tbuffer_load_format_d16_xy v[[FULL:[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; PREGFX10-PACKED: tbuffer_load_format_d16_xy v[[FULL:[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; GFX10-PACKED: tbuffer_load_format_d16_xy v[[FULL:[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] ; GFX10-PACKED: tbuffer_load_format_d16_xy v[[FULL:[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT]
; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]] ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]]
define amdgpu_ps half @tbuffer_load_d16_xy(<4 x i32> inreg %rsrc) { define amdgpu_ps half @tbuffer_load_d16_xy(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <2 x half> @llvm.amdgcn.raw.tbuffer.load.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 22, i32 0) %data = call <2 x half> @llvm.amdgcn.raw.tbuffer.load.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <2 x half> %data, i32 1 %elt = extractelement <2 x half> %data, i32 1
ret half %elt ret half %elt
} }
; GCN-LABEL: {{^}}tbuffer_load_d16_xyz: ; GCN-LABEL: {{^}}tbuffer_load_d16_xyz:
; PREGFX10-UNPACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; PREGFX10-UNPACKED: tbuffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; GFX10-UNPACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] ; GFX10-UNPACKED: tbuffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT]
; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PREGFX10-PACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; PREGFX10-PACKED: tbuffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; GFX10-PACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] ; GFX10-PACKED: tbuffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT]
; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
define amdgpu_ps half @tbuffer_load_d16_xyz(<4 x i32> inreg %rsrc) { define amdgpu_ps half @tbuffer_load_d16_xyz(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <3 x half> @llvm.amdgcn.raw.tbuffer.load.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 22, i32 0) %data = call <3 x half> @llvm.amdgcn.raw.tbuffer.load.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <3 x half> %data, i32 2 %elt = extractelement <3 x half> %data, i32 2
ret half %elt ret half %elt
} }
; GCN-LABEL: {{^}}tbuffer_load_d16_xyzw: ; GCN-LABEL: {{^}}tbuffer_load_d16_xyzw:
; PREGFX10-UNPACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; PREGFX10-UNPACKED: tbuffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; GFX10-UNPACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] ; GFX10-UNPACKED: tbuffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT]
; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PREGFX10-PACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; PREGFX10-PACKED: tbuffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; GFX10-PACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] ; GFX10-PACKED: tbuffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT]
; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]] ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
define amdgpu_ps half @tbuffer_load_d16_xyzw(<4 x i32> inreg %rsrc) { define amdgpu_ps half @tbuffer_load_d16_xyzw(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <4 x half> @llvm.amdgcn.raw.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 22, i32 0) %data = call <4 x half> @llvm.amdgcn.raw.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <4 x half> %data, i32 3 %elt = extractelement <4 x half> %data, i32 3
ret half %elt ret half %elt
} }
declare half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32>, i32, i32, i32, i32) declare half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32>, i32, i32, i32, i32)
declare <2 x half> @llvm.amdgcn.raw.tbuffer.load.v2f16(<4 x i32>, i32, i32, i32, i32) declare <2 x half> @llvm.amdgcn.raw.tbuffer.load.v2f16(<4 x i32>, i32, i32, i32, i32)
declare <3 x half> @llvm.amdgcn.raw.tbuffer.load.v3f16(<4 x i32>, i32, i32, i32, i32) declare <3 x half> @llvm.amdgcn.raw.tbuffer.load.v3f16(<4 x i32>, i32, i32, i32, i32)
declare <4 x half> @llvm.amdgcn.raw.tbuffer.load.v4f16(<4 x i32>, i32, i32, i32, i32) declare <4 x half> @llvm.amdgcn.raw.tbuffer.load.v4f16(<4 x i32>, i32, i32, i32, i32)

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll

Show All 16 Lines
} }
; GCN-LABEL: {{^}}tbuffer_store_d16_xy: ; GCN-LABEL: {{^}}tbuffer_store_d16_xy:
; GCN: s_load_dword [[S_DATA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, ; GCN: s_load_dword [[S_DATA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}},
; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[S_DATA]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[S_DATA]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}} ; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}}
; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]] ; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]]
; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]] ; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]]
; PREGFX10-UNPACKED: tbuffer_store_format_d16_xy v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] ; PREGFX10-UNPACKED: tbuffer_store_format_d16_xy v[[[V_LO]]:[[V_HI]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED]
; PREGFX10-PACKED: tbuffer_store_format_d16_xy v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] ; PREGFX10-PACKED: tbuffer_store_format_d16_xy v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED]
; GFX10-PACKED: tbuffer_store_format_d16_xy v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED] ; GFX10-PACKED: tbuffer_store_format_d16_xy v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED]
define amdgpu_kernel void @tbuffer_store_d16_xy(<4 x i32> %rsrc, <2 x half> %data) { define amdgpu_kernel void @tbuffer_store_d16_xy(<4 x i32> %rsrc, <2 x half> %data) {
main_body: main_body:
call void @llvm.amdgcn.raw.tbuffer.store.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 0, i32 0, i32 33, i32 0) call void @llvm.amdgcn.raw.tbuffer.store.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 0, i32 0, i32 33, i32 0)
ret void ret void
} }
; GCN-LABEL: {{^}}tbuffer_store_d16_xyz: ; GCN-LABEL: {{^}}tbuffer_store_d16_xyz:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, ; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}},
; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}} ; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}}
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]] ; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED1]] ; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED1]]
; PREGFX10-UNPACKED: tbuffer_store_format_d16_xyz v{{\[}}[[LO]]:[[HI]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] ; PREGFX10-UNPACKED: tbuffer_store_format_d16_xyz v[[[LO]]:[[HI]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED]
; PACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}} ; PACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
; PACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]] ; PACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED0]] ; PACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED0]]
; PREGFX10-PACKED: tbuffer_store_format_d16_xyz v{{\[}}[[LO]]:[[HI]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] ; PREGFX10-PACKED: tbuffer_store_format_d16_xyz v[[[LO]]:[[HI]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED]
; GFX10-PACKED: tbuffer_store_format_d16_xyz v{{\[}}[[LO]]:[[HI]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED] ; GFX10-PACKED: tbuffer_store_format_d16_xyz v[[[LO]]:[[HI]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED]
define amdgpu_kernel void @tbuffer_store_d16_xyz(<4 x i32> %rsrc, <4 x half> %data) { define amdgpu_kernel void @tbuffer_store_d16_xyz(<4 x i32> %rsrc, <4 x half> %data) {
main_body: main_body:
%data_subvec = shufflevector <4 x half> %data, <4 x half> undef, <3 x i32> <i32 0, i32 1, i32 2> %data_subvec = shufflevector <4 x half> %data, <4 x half> undef, <3 x i32> <i32 0, i32 1, i32 2>
call void @llvm.amdgcn.raw.tbuffer.store.v3f16(<3 x half> %data_subvec, <4 x i32> %rsrc, i32 0, i32 0, i32 33, i32 0) call void @llvm.amdgcn.raw.tbuffer.store.v3f16(<3 x half> %data_subvec, <4 x i32> %rsrc, i32 0, i32 0, i32 33, i32 0)
ret void ret void
} }
; GCN-LABEL: {{^}}tbuffer_store_d16_xyzw: ; GCN-LABEL: {{^}}tbuffer_store_d16_xyzw:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, ; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}},
; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}} ; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}}
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]] ; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]] ; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]]
; PREGFX10-UNPACKED: tbuffer_store_format_d16_xyzw v{{\[}}[[LO]]:[[HI]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] ; PREGFX10-UNPACKED: tbuffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED]
; PACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]] ; PACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]] ; PACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]]
; PREGFX10-PACKED: tbuffer_store_format_d16_xyzw v{{\[}}[[LO]]:[[HI]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] ; PREGFX10-PACKED: tbuffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED]
; GFX10-PACKED: tbuffer_store_format_d16_xyzw v{{\[}}[[LO]]:[[HI]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED] ; GFX10-PACKED: tbuffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED]
define amdgpu_kernel void @tbuffer_store_d16_xyzw(<4 x i32> %rsrc, <4 x half> %data) { define amdgpu_kernel void @tbuffer_store_d16_xyzw(<4 x i32> %rsrc, <4 x half> %data) {
main_body: main_body:
call void @llvm.amdgcn.raw.tbuffer.store.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 0, i32 0, i32 33, i32 0) call void @llvm.amdgcn.raw.tbuffer.store.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 0, i32 0, i32 33, i32 0)
ret void ret void
} }
declare void @llvm.amdgcn.raw.tbuffer.store.f16(half, <4 x i32>, i32, i32, i32, i32) declare void @llvm.amdgcn.raw.tbuffer.store.f16(half, <4 x i32>, i32, i32, i32, i32)
declare void @llvm.amdgcn.raw.tbuffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32) declare void @llvm.amdgcn.raw.tbuffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32)
declare void @llvm.amdgcn.raw.tbuffer.store.v3f16(<3 x half>, <4 x i32>, i32, i32, i32, i32) declare void @llvm.amdgcn.raw.tbuffer.store.v3f16(<3 x half>, <4 x i32>, i32, i32, i32, i32)
declare void @llvm.amdgcn.raw.tbuffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32, i32) declare void @llvm.amdgcn.raw.tbuffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32, i32)

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll

Show All 22 Lines
; SI: v_rsq_clamp_f64_e32 ; SI: v_rsq_clamp_f64_e32
; TODO: this constant should be folded: ; TODO: this constant should be folded:
; VI-DAG: s_mov_b32 [[NEG1:s[0-9]+]], -1 ; VI-DAG: s_mov_b32 [[NEG1:s[0-9]+]], -1
; VI-DAG: s_mov_b32 s[[LOW1:[0-9]+]], [[NEG1]] ; VI-DAG: s_mov_b32 s[[LOW1:[0-9]+]], [[NEG1]]
; VI-DAG: s_mov_b32 s[[HIGH1:[0-9]+]], 0x7fefffff ; VI-DAG: s_mov_b32 s[[HIGH1:[0-9]+]], 0x7fefffff
; VI-DAG: s_mov_b32 s[[HIGH2:[0-9]+]], 0xffefffff ; VI-DAG: s_mov_b32 s[[HIGH2:[0-9]+]], 0xffefffff
; VI-DAG: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}} ; VI-DAG: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}
; VI-DAG: v_min_f64 v[0:1], [[RSQ]], s{{\[}}[[LOW1]]:[[HIGH1]]] ; VI-DAG: v_min_f64 v[0:1], [[RSQ]], s[[[LOW1]]:[[HIGH1]]]
; VI-DAG: v_max_f64 v[0:1], v[0:1], s{{\[}}[[LOW1]]:[[HIGH2]]] ; VI-DAG: v_max_f64 v[0:1], v[0:1], s[[[LOW1]]:[[HIGH2]]]
define amdgpu_kernel void @rsq_clamp_f64(double addrspace(1)* %out, double %src) #0 { define amdgpu_kernel void @rsq_clamp_f64(double addrspace(1)* %out, double %src) #0 {
%rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double %src) %rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double %src)
store double %rsq_clamp, double addrspace(1)* %out store double %rsq_clamp, double addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}rsq_clamp_undef_f32: ; FUNC-LABEL: {{^}}rsq_clamp_undef_f32:
; SI-NOT: v_rsq_clamp_f32 ; SI-NOT: v_rsq_clamp_f32
define amdgpu_kernel void @rsq_clamp_undef_f32(float addrspace(1)* %out) #0 { define amdgpu_kernel void @rsq_clamp_undef_f32(float addrspace(1)* %out) #0 {
%rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float undef) %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float undef)
store float %rsq_clamp, float addrspace(1)* %out store float %rsq_clamp, float addrspace(1)* %out
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.d16.ll

; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s
; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
; GCN-LABEL: {{^}}buffer_load_format_d16_x: ; GCN-LABEL: {{^}}buffer_load_format_d16_x:
; GCN: buffer_load_format_d16_x v{{[0-9]+}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; GCN: buffer_load_format_d16_x v{{[0-9]+}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_ps half @buffer_load_format_d16_x(<4 x i32> inreg %rsrc) { define amdgpu_ps half @buffer_load_format_d16_x(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call half @llvm.amdgcn.struct.buffer.load.format.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) %data = call half @llvm.amdgcn.struct.buffer.load.format.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
ret half %data ret half %data
} }
; GCN-LABEL: {{^}}buffer_load_format_d16_xy: ; GCN-LABEL: {{^}}buffer_load_format_d16_xy:
; UNPACKED: buffer_load_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; UNPACKED: buffer_load_format_d16_xy v[{{[0-9]+}}:[[HI:[0-9]+]]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PACKED: buffer_load_format_d16_xy v[[FULL:[0-9]+]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; PACKED: buffer_load_format_d16_xy v[[FULL:[0-9]+]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]] ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]]
define amdgpu_ps half @buffer_load_format_d16_xy(<4 x i32> inreg %rsrc) { define amdgpu_ps half @buffer_load_format_d16_xy(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <2 x half> @llvm.amdgcn.struct.buffer.load.format.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) %data = call <2 x half> @llvm.amdgcn.struct.buffer.load.format.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%elt = extractelement <2 x half> %data, i32 1 %elt = extractelement <2 x half> %data, i32 1
ret half %elt ret half %elt
} }
; GCN-LABEL: {{^}}buffer_load_format_d16_xyz: ; GCN-LABEL: {{^}}buffer_load_format_d16_xyz:
; UNPACKED: buffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; UNPACKED: buffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PACKED: buffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; PACKED: buffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
define amdgpu_ps half @buffer_load_format_d16_xyz(<4 x i32> inreg %rsrc) { define amdgpu_ps half @buffer_load_format_d16_xyz(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) %data = call <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%elt = extractelement <3 x half> %data, i32 2 %elt = extractelement <3 x half> %data, i32 2
ret half %elt ret half %elt
} }
; GCN-LABEL: {{^}}buffer_load_format_d16_xyzw: ; GCN-LABEL: {{^}}buffer_load_format_d16_xyzw:
; UNPACKED: buffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; UNPACKED: buffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PACKED: buffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; PACKED: buffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]] ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
define amdgpu_ps half @buffer_load_format_d16_xyzw(<4 x i32> inreg %rsrc) { define amdgpu_ps half @buffer_load_format_d16_xyzw(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <4 x half> @llvm.amdgcn.struct.buffer.load.format.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) %data = call <4 x half> @llvm.amdgcn.struct.buffer.load.format.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%elt = extractelement <4 x half> %data, i32 3 %elt = extractelement <4 x half> %data, i32 3
ret half %elt ret half %elt
} }
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.d16.ll

Show All 13 Lines
; GCN-LABEL: {{^}}buffer_store_format_d16_xy: ; GCN-LABEL: {{^}}buffer_store_format_d16_xy:
; UNPACKED: s_load_dword [[S_DATA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x10 ; UNPACKED: s_load_dword [[S_DATA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[S_DATA]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[S_DATA]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}} ; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}}
; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]] ; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]]
; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]] ; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]]
; UNPACKED: buffer_store_format_d16_xy v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; UNPACKED: buffer_store_format_d16_xy v[[[V_LO]]:[[V_HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
; PACKED: buffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; PACKED: buffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_kernel void @buffer_store_format_d16_xy(<4 x i32> %rsrc, <2 x half> %data, i32 %index) { define amdgpu_kernel void @buffer_store_format_d16_xy(<4 x i32> %rsrc, <2 x half> %data, i32 %index) {
main_body: main_body:
call void @llvm.amdgcn.struct.buffer.store.format.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0) call void @llvm.amdgcn.struct.buffer.store.format.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void ret void
} }
; GCN-LABEL: {{^}}buffer_store_format_d16_xyz: ; GCN-LABEL: {{^}}buffer_store_format_d16_xyz:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x10 ; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}} ; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}}
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]] ; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED1]] ; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED1]]
; UNPACKED: buffer_store_format_d16_xyz v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; UNPACKED: buffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
; PACKED: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}} ; PACKED: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]] ; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED0]] ; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED0]]
; PACKED: buffer_store_format_d16_xyz v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; PACKED: buffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_kernel void @buffer_store_format_d16_xyz(<4 x i32> %rsrc, <4 x half> %data, i32 %index) { define amdgpu_kernel void @buffer_store_format_d16_xyz(<4 x i32> %rsrc, <4 x half> %data, i32 %index) {
main_body: main_body:
%data_subvec = shufflevector <4 x half> %data, <4 x half> undef, <3 x i32> <i32 0, i32 1, i32 2> %data_subvec = shufflevector <4 x half> %data, <4 x half> undef, <3 x i32> <i32 0, i32 1, i32 2>
call void @llvm.amdgcn.struct.buffer.store.format.v3f16(<3 x half> %data_subvec, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0) call void @llvm.amdgcn.struct.buffer.store.format.v3f16(<3 x half> %data_subvec, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void ret void
} }
; GCN-LABEL: {{^}}buffer_store_format_d16_xyzw: ; GCN-LABEL: {{^}}buffer_store_format_d16_xyzw:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x10 ; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}} ; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}}
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]] ; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]] ; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]]
; UNPACKED: buffer_store_format_d16_xyzw v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; UNPACKED: buffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]] ; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]] ; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]]
; PACKED: buffer_store_format_d16_xyzw v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen ; PACKED: buffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_kernel void @buffer_store_format_d16_xyzw(<4 x i32> %rsrc, <4 x half> %data, i32 %index) { define amdgpu_kernel void @buffer_store_format_d16_xyzw(<4 x i32> %rsrc, <4 x half> %data, i32 %index) {
main_body: main_body:
call void @llvm.amdgcn.struct.buffer.store.format.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0) call void @llvm.amdgcn.struct.buffer.store.format.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void ret void
} }
; GCN-LABEL: {{^}}buffer_store_format_i16_x: ; GCN-LABEL: {{^}}buffer_store_format_i16_x:
; GCN: s_load_dword s[[LO:[0-9]+]] ; GCN: s_load_dword s[[LO:[0-9]+]]
Show All 13 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll

Show All 9 Lines
define amdgpu_ps half @tbuffer_load_d16_x(<4 x i32> inreg %rsrc) { define amdgpu_ps half @tbuffer_load_d16_x(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call half @llvm.amdgcn.struct.tbuffer.load.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0) %data = call half @llvm.amdgcn.struct.tbuffer.load.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0)
ret half %data ret half %data
} }
; GCN-LABEL: {{^}}tbuffer_load_d16_xy: ; GCN-LABEL: {{^}}tbuffer_load_d16_xy:
; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0 ; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
; PREGFX10-UNPACKED: tbuffer_load_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen ; PREGFX10-UNPACKED: tbuffer_load_format_d16_xy v[{{[0-9]+}}:[[HI:[0-9]+]]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
; PREGFX10-UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; PREGFX10-UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PREGFX10-PACKED: tbuffer_load_format_d16_xy v[[FULL:[0-9]+]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen ; PREGFX10-PACKED: tbuffer_load_format_d16_xy v[[FULL:[0-9]+]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
; GFX10-PACKED: tbuffer_load_format_d16_xy v[[FULL:[0-9]+]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] idxen ; GFX10-PACKED: tbuffer_load_format_d16_xy v[[FULL:[0-9]+]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] idxen
; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]] ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]]
define amdgpu_ps half @tbuffer_load_d16_xy(<4 x i32> inreg %rsrc) { define amdgpu_ps half @tbuffer_load_d16_xy(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <2 x half> @llvm.amdgcn.struct.tbuffer.load.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0) %data = call <2 x half> @llvm.amdgcn.struct.tbuffer.load.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <2 x half> %data, i32 1 %elt = extractelement <2 x half> %data, i32 1
ret half %elt ret half %elt
} }
; GCN-LABEL: {{^}}tbuffer_load_d16_xyz: ; GCN-LABEL: {{^}}tbuffer_load_d16_xyz:
; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0 ; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
; PREGFX10-UNPACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen ; PREGFX10-UNPACKED: tbuffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
; PREGFX10-UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; PREGFX10-UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PREGFX10-PACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen ; PREGFX10-PACKED: tbuffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
; GFX10-PACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] idxen ; GFX10-PACKED: tbuffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] idxen
; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
define amdgpu_ps half @tbuffer_load_d16_xyz(<4 x i32> inreg %rsrc) { define amdgpu_ps half @tbuffer_load_d16_xyz(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <3 x half> @llvm.amdgcn.struct.tbuffer.load.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0) %data = call <3 x half> @llvm.amdgcn.struct.tbuffer.load.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <3 x half> %data, i32 2 %elt = extractelement <3 x half> %data, i32 2
ret half %elt ret half %elt
} }
; GCN-LABEL: {{^}}tbuffer_load_d16_xyzw: ; GCN-LABEL: {{^}}tbuffer_load_d16_xyzw:
; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0 ; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
; PREGFX10-UNPACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen ; PREGFX10-UNPACKED: tbuffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
; PREGFX10-UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; PREGFX10-UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PREGFX10-PACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen ; PREGFX10-PACKED: tbuffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
; GFX10-PACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] idxen ; GFX10-PACKED: tbuffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] idxen
; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]] ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
define amdgpu_ps half @tbuffer_load_d16_xyzw(<4 x i32> inreg %rsrc) { define amdgpu_ps half @tbuffer_load_d16_xyzw(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <4 x half> @llvm.amdgcn.struct.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0) %data = call <4 x half> @llvm.amdgcn.struct.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <4 x half> %data, i32 3 %elt = extractelement <4 x half> %data, i32 3
ret half %elt ret half %elt
} }
declare half @llvm.amdgcn.struct.tbuffer.load.f16(<4 x i32>, i32, i32, i32, i32, i32) declare half @llvm.amdgcn.struct.tbuffer.load.f16(<4 x i32>, i32, i32, i32, i32, i32)
declare <2 x half> @llvm.amdgcn.struct.tbuffer.load.v2f16(<4 x i32>, i32, i32, i32, i32, i32) declare <2 x half> @llvm.amdgcn.struct.tbuffer.load.v2f16(<4 x i32>, i32, i32, i32, i32, i32)
declare <3 x half> @llvm.amdgcn.struct.tbuffer.load.v3f16(<4 x i32>, i32, i32, i32, i32, i32) declare <3 x half> @llvm.amdgcn.struct.tbuffer.load.v3f16(<4 x i32>, i32, i32, i32, i32, i32)
declare <4 x half> @llvm.amdgcn.struct.tbuffer.load.v4f16(<4 x i32>, i32, i32, i32, i32, i32) declare <4 x half> @llvm.amdgcn.struct.tbuffer.load.v4f16(<4 x i32>, i32, i32, i32, i32, i32)

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,PREGFX10,UNPACKED,PREGFX10-UNPACKED %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,PREGFX10,UNPACKED,PREGFX10-UNPACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,PREGFX10,PACKED,PREGFX10-PACKED %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,PREGFX10,PACKED,PREGFX10-PACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,PREGFX10,PACKED,PREGFX10-PACKED %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,PREGFX10,PACKED,PREGFX10-PACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10,PACKED,GFX10-PACKED %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10,PACKED,GFX10-PACKED %s
; GCN-LABEL: {{^}}tbuffer_store_d16_x: ; GCN-LABEL: {{^}}tbuffer_store_d16_x:
; GCN-DAG: s_load_dwordx4 ; GCN-DAG: s_load_dwordx4
; GCN-DAG: s_load_dword{{[x0-2]*}} s{{\[}}[[S_LO:[0-9]+]] ; GCN-DAG: s_load_dword{{[x0-2]*}} s[[[S_LO:[0-9]+]]
; GCN-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[S_LO]] ; GCN-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[S_LO]]
; PREGFX10: tbuffer_store_format_d16_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen ; PREGFX10: tbuffer_store_format_d16_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; GFX10: tbuffer_store_format_d16_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen ; GFX10: tbuffer_store_format_d16_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
define amdgpu_kernel void @tbuffer_store_d16_x(<4 x i32> %rsrc, half %data, i32 %vindex) { define amdgpu_kernel void @tbuffer_store_d16_x(<4 x i32> %rsrc, half %data, i32 %vindex) {
main_body: main_body:
call void @llvm.amdgcn.struct.tbuffer.store.f16(half %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0) call void @llvm.amdgcn.struct.tbuffer.store.f16(half %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
ret void ret void
} }
; GCN-LABEL: {{^}}tbuffer_store_d16_xy: ; GCN-LABEL: {{^}}tbuffer_store_d16_xy:
; GCN: s_load_dword [[S_DATA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x10 ; GCN: s_load_dword [[S_DATA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[S_DATA]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[S_DATA]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}} ; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}}
; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]] ; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]]
; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]] ; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]]
; PREGFX10-UNPACKED: tbuffer_store_format_d16_xy v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen ; PREGFX10-UNPACKED: tbuffer_store_format_d16_xy v[[[V_LO]]:[[V_HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; PREGFX10-PACKED: tbuffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen ; PREGFX10-PACKED: tbuffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; GFX10-PACKED: tbuffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen ; GFX10-PACKED: tbuffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
define amdgpu_kernel void @tbuffer_store_d16_xy(<4 x i32> %rsrc, <2 x half> %data, i32 %vindex) { define amdgpu_kernel void @tbuffer_store_d16_xy(<4 x i32> %rsrc, <2 x half> %data, i32 %vindex) {
main_body: main_body:
call void @llvm.amdgcn.struct.tbuffer.store.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0) call void @llvm.amdgcn.struct.tbuffer.store.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
ret void ret void
} }
; GCN-LABEL: {{^}}tbuffer_store_d16_xyz: ; GCN-LABEL: {{^}}tbuffer_store_d16_xyz:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x10 ; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}} ; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}}
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]] ; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED1]] ; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED1]]
; PREGFX10-UNPACKED: tbuffer_store_format_d16_xyz v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen ; PREGFX10-UNPACKED: tbuffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; PACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}} ; PACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
; PACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]] ; PACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED0]] ; PACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED0]]
; PREGFX10-PACKED: tbuffer_store_format_d16_xyz v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen ; PREGFX10-PACKED: tbuffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; GFX10-PACKED: tbuffer_store_format_d16_xyz v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen ; GFX10-PACKED: tbuffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
define amdgpu_kernel void @tbuffer_store_d16_xyz(<4 x i32> %rsrc, <4 x half> %data, i32 %vindex) { define amdgpu_kernel void @tbuffer_store_d16_xyz(<4 x i32> %rsrc, <4 x half> %data, i32 %vindex) {
main_body: main_body:
%data_subvec = shufflevector <4 x half> %data, <4 x half> undef, <3 x i32> <i32 0, i32 1, i32 2> %data_subvec = shufflevector <4 x half> %data, <4 x half> undef, <3 x i32> <i32 0, i32 1, i32 2>
call void @llvm.amdgcn.struct.tbuffer.store.v3f16(<3 x half> %data_subvec, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0) call void @llvm.amdgcn.struct.tbuffer.store.v3f16(<3 x half> %data_subvec, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
ret void ret void
} }
; GCN-LABEL: {{^}}tbuffer_store_d16_xyzw: ; GCN-LABEL: {{^}}tbuffer_store_d16_xyzw:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x10 ; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}} ; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}}
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]] ; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]] ; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]]
; PREGFX10-UNPACKED: tbuffer_store_format_d16_xyzw v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen ; PREGFX10-UNPACKED: tbuffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; PACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]] ; PACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]] ; PACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]]
; PREGFX10-PACKED: tbuffer_store_format_d16_xyzw v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen ; PREGFX10-PACKED: tbuffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; GFX10-PACKED: tbuffer_store_format_d16_xyzw v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen ; GFX10-PACKED: tbuffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
define amdgpu_kernel void @tbuffer_store_d16_xyzw(<4 x i32> %rsrc, <4 x half> %data, i32 %vindex) { define amdgpu_kernel void @tbuffer_store_d16_xyzw(<4 x i32> %rsrc, <4 x half> %data, i32 %vindex) {
main_body: main_body:
call void @llvm.amdgcn.struct.tbuffer.store.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0) call void @llvm.amdgcn.struct.tbuffer.store.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
ret void ret void
} }
declare void @llvm.amdgcn.struct.tbuffer.store.f16(half, <4 x i32>, i32, i32, i32, i32, i32) declare void @llvm.amdgcn.struct.tbuffer.store.f16(half, <4 x i32>, i32, i32, i32, i32, i32)
declare void @llvm.amdgcn.struct.tbuffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32, i32) declare void @llvm.amdgcn.struct.tbuffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32, i32)
declare void @llvm.amdgcn.struct.tbuffer.store.v3f16(<3 x half>, <4 x i32>, i32, i32, i32, i32, i32) declare void @llvm.amdgcn.struct.tbuffer.store.v3f16(<3 x half>, <4 x i32>, i32, i32, i32, i32, i32)
declare void @llvm.amdgcn.struct.tbuffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32, i32, i32) declare void @llvm.amdgcn.struct.tbuffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32, i32, i32)

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll

; RUN: llc -global-isel=0 < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s ; RUN: llc -global-isel=0 < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s
; RUN: llc -global-isel=0 < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s ; RUN: llc -global-isel=0 < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
; RUN: llc -global-isel=0 < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s ; RUN: llc -global-isel=0 < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
; GCN-LABEL: {{^}}tbuffer_load_d16_x: ; GCN-LABEL: {{^}}tbuffer_load_d16_x:
; GCN: tbuffer_load_format_d16_x v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; GCN: tbuffer_load_format_d16_x v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
define amdgpu_ps half @tbuffer_load_d16_x(<4 x i32> inreg %rsrc) { define amdgpu_ps half @tbuffer_load_d16_x(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call half @llvm.amdgcn.tbuffer.load.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0, i32 6, i32 1, i1 0, i1 0) %data = call half @llvm.amdgcn.tbuffer.load.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0, i32 6, i32 1, i1 0, i1 0)
ret half %data ret half %data
} }
; GCN-LABEL: {{^}}tbuffer_load_d16_xy: ; GCN-LABEL: {{^}}tbuffer_load_d16_xy:
; UNPACKED: tbuffer_load_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; UNPACKED: tbuffer_load_format_d16_xy v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PACKED: tbuffer_load_format_d16_xy v[[FULL:[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; PACKED: tbuffer_load_format_d16_xy v[[FULL:[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]] ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]]
define amdgpu_ps half @tbuffer_load_d16_xy(<4 x i32> inreg %rsrc) { define amdgpu_ps half @tbuffer_load_d16_xy(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <2 x half> @llvm.amdgcn.tbuffer.load.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0, i32 6, i32 1, i1 0, i1 0) %data = call <2 x half> @llvm.amdgcn.tbuffer.load.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0, i32 6, i32 1, i1 0, i1 0)
%elt = extractelement <2 x half> %data, i32 1 %elt = extractelement <2 x half> %data, i32 1
ret half %elt ret half %elt
} }
; GCN-LABEL: {{^}}tbuffer_load_d16_xyz: ; GCN-LABEL: {{^}}tbuffer_load_d16_xyz:
; UNPACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; UNPACKED: tbuffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PACKED: tbuffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; PACKED: tbuffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
define amdgpu_ps half @tbuffer_load_d16_xyz(<4 x i32> inreg %rsrc) { define amdgpu_ps half @tbuffer_load_d16_xyz(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <3 x half> @llvm.amdgcn.tbuffer.load.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0, i32 6, i32 1, i1 0, i1 0) %data = call <3 x half> @llvm.amdgcn.tbuffer.load.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0, i32 6, i32 1, i1 0, i1 0)
%elt = extractelement <3 x half> %data, i32 2 %elt = extractelement <3 x half> %data, i32 2
ret half %elt ret half %elt
} }
; GCN-LABEL: {{^}}tbuffer_load_d16_xyzw: ; GCN-LABEL: {{^}}tbuffer_load_d16_xyzw:
; UNPACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; UNPACKED: tbuffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
; PACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; PACKED: tbuffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]] ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
define amdgpu_ps half @tbuffer_load_d16_xyzw(<4 x i32> inreg %rsrc) { define amdgpu_ps half @tbuffer_load_d16_xyzw(<4 x i32> inreg %rsrc) {
main_body: main_body:
%data = call <4 x half> @llvm.amdgcn.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0, i32 6, i32 1, i1 0, i1 0) %data = call <4 x half> @llvm.amdgcn.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0, i32 6, i32 1, i1 0, i1 0)
%elt = extractelement <4 x half> %data, i32 3 %elt = extractelement <4 x half> %data, i32 3
ret half %elt ret half %elt
} }
declare half @llvm.amdgcn.tbuffer.load.f16(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) declare half @llvm.amdgcn.tbuffer.load.f16(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
declare <2 x half> @llvm.amdgcn.tbuffer.load.v2f16(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) declare <2 x half> @llvm.amdgcn.tbuffer.load.v2f16(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
declare <3 x half> @llvm.amdgcn.tbuffer.load.v3f16(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) declare <3 x half> @llvm.amdgcn.tbuffer.load.v3f16(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
declare <4 x half> @llvm.amdgcn.tbuffer.load.v4f16(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) declare <4 x half> @llvm.amdgcn.tbuffer.load.v4f16(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll

Show All 13 Lines
} }
; GCN-LABEL: {{^}}tbuffer_store_d16_xy: ; GCN-LABEL: {{^}}tbuffer_store_d16_xy:
; GCN: s_load_dword [[S_DATA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x10 ; GCN: s_load_dword [[S_DATA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[S_DATA]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[S_DATA]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}} ; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}}
; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]] ; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]]
; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]] ; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]]
; UNPACKED: tbuffer_store_format_d16_xy v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen ; UNPACKED: tbuffer_store_format_d16_xy v[[[V_LO]]:[[V_HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; PACKED: tbuffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen ; PACKED: tbuffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
define amdgpu_kernel void @tbuffer_store_d16_xy(<4 x i32> %rsrc, <2 x half> %data, i32 %vindex) { define amdgpu_kernel void @tbuffer_store_d16_xy(<4 x i32> %rsrc, <2 x half> %data, i32 %vindex) {
main_body: main_body:
call void @llvm.amdgcn.tbuffer.store.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0, i32 1, i32 2, i1 0, i1 0) call void @llvm.amdgcn.tbuffer.store.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0, i32 1, i32 2, i1 0, i1 0)
ret void ret void
} }
; GCN-LABEL: {{^}}tbuffer_store_d16_xyz: ; GCN-LABEL: {{^}}tbuffer_store_d16_xyz:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x10 ; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}} ; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}}
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
; UNPACKED-DAG: s_and_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], [[K]] ; UNPACKED-DAG: s_and_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], [[K]]
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]] ; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]] ; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]]
; UNPACKED: tbuffer_store_format_d16_xyz v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen ; UNPACKED: tbuffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; PACKED-DAG: s_and_b32 [[SHR0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}} ; PACKED-DAG: s_and_b32 [[SHR0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
; PACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]] ; PACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR0]] ; PACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR0]]
; PACKED: tbuffer_store_format_d16_xyz v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen ; PACKED: tbuffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
define amdgpu_kernel void @tbuffer_store_d16_xyz(<4 x i32> %rsrc, <3 x half> %data, i32 %vindex) { define amdgpu_kernel void @tbuffer_store_d16_xyz(<4 x i32> %rsrc, <3 x half> %data, i32 %vindex) {
main_body: main_body:
call void @llvm.amdgcn.tbuffer.store.v3f16(<3 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0, i32 1, i32 2, i1 0, i1 0) call void @llvm.amdgcn.tbuffer.store.v3f16(<3 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0, i32 1, i32 2, i1 0, i1 0)
ret void ret void
} }
; GCN-LABEL: {{^}}tbuffer_store_d16_xyzw: ; GCN-LABEL: {{^}}tbuffer_store_d16_xyzw:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x10 ; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}} ; UNPACKED-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}}
; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16 ; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16
; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]] ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]] ; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]] ; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]]
; UNPACKED: tbuffer_store_format_d16_xyzw v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen ; UNPACKED: tbuffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; PACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]] ; PACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
; PACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]] ; PACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]]
; PACKED: tbuffer_store_format_d16_xyzw v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen ; PACKED: tbuffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
define amdgpu_kernel void @tbuffer_store_d16_xyzw(<4 x i32> %rsrc, <4 x half> %data, i32 %vindex) { define amdgpu_kernel void @tbuffer_store_d16_xyzw(<4 x i32> %rsrc, <4 x half> %data, i32 %vindex) {
main_body: main_body:
call void @llvm.amdgcn.tbuffer.store.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0, i32 1, i32 2, i1 0, i1 0) call void @llvm.amdgcn.tbuffer.store.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0, i32 1, i32 2, i1 0, i1 0)
ret void ret void
} }
declare void @llvm.amdgcn.tbuffer.store.f16(half, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) declare void @llvm.amdgcn.tbuffer.store.f16(half, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
declare void @llvm.amdgcn.tbuffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) declare void @llvm.amdgcn.tbuffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
declare void @llvm.amdgcn.tbuffer.store.v3f16(<3 x half>, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) declare void @llvm.amdgcn.tbuffer.store.v3f16(<3 x half>, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
declare void @llvm.amdgcn.tbuffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) declare void @llvm.amdgcn.tbuffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Linesbb:
%tmp5 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp4, i32 177, i32 15, i32 15, i1 zeroext false) %tmp5 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp4, i32 177, i32 15, i32 15, i1 zeroext false)
%tmp6 = add nsw i32 %tmp5, %tmp4 %tmp6 = add nsw i32 %tmp5, %tmp4
%tmp7 = getelementptr inbounds i32, i32* %arg, i64 %tmp1 %tmp7 = getelementptr inbounds i32, i32* %arg, i64 %tmp1
store i32 %tmp6, i32* %tmp7, align 4 store i32 %tmp6, i32* %tmp7, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}update_dpp64_test: ; GCN-LABEL: {{^}}update_dpp64_test:
; GCN: load_dwordx2 v{{\[}}[[SRC_LO:[0-9]+]]:[[SRC_HI:[0-9]+]]] ; GCN: load_dwordx2 v[[[SRC_LO:[0-9]+]]:[[SRC_HI:[0-9]+]]]
; GCN-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} ; GCN-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
; GCN-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} ; GCN-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
define amdgpu_kernel void @update_dpp64_test(i64 addrspace(1)* %arg, i64 %in1, i64 %in2) { define amdgpu_kernel void @update_dpp64_test(i64 addrspace(1)* %arg, i64 %in1, i64 %in2) {
%id = tail call i32 @llvm.amdgcn.workitem.id.x() %id = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id %gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
%load = load i64, i64 addrspace(1)* %gep %load = load i64, i64 addrspace(1)* %gep
%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 1, i32 1, i32 1, i1 0) #0 %tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 1, i32 1, i32 1, i1 0) #0
store i64 %tmp0, i64 addrspace(1)* %gep store i64 %tmp0, i64 addrspace(1)* %gep
ret void ret void
} }
; GCN-LABEL: {{^}}update_dpp64_imm_old_test: ; GCN-LABEL: {{^}}update_dpp64_imm_old_test:
; GCN-OPT-DAG: v_mov_b32_e32 v[[OLD_LO:[0-9]+]], 0x3afaedd9 ; GCN-OPT-DAG: v_mov_b32_e32 v[[OLD_LO:[0-9]+]], 0x3afaedd9
; GCN-OPT-DAG: v_mov_b32_e32 v[[OLD_HI:[0-9]+]], 0x7047 ; GCN-OPT-DAG: v_mov_b32_e32 v[[OLD_HI:[0-9]+]], 0x7047
; GFX8-NOOPT-DAG: s_mov_b32 s[[SOLD_LO:[0-9]+]], 0x3afaedd9 ; GFX8-NOOPT-DAG: s_mov_b32 s[[SOLD_LO:[0-9]+]], 0x3afaedd9
; GFX8-NOOPT-DAG: s_mov_b32 s[[SOLD_HI:[0-9]+]], 0x7047 ; GFX8-NOOPT-DAG: s_mov_b32 s[[SOLD_HI:[0-9]+]], 0x7047
; GCN-DAG: load_dwordx2 v{{\[}}[[SRC_LO:[0-9]+]]:[[SRC_HI:[0-9]+]]] ; GCN-DAG: load_dwordx2 v[[[SRC_LO:[0-9]+]]:[[SRC_HI:[0-9]+]]]
; GCN-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[SRC_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} ; GCN-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[SRC_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
; GCN-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[SRC_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} ; GCN-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[SRC_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
; GCN-NOOPT-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} ; GCN-NOOPT-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
; GCN-NOOPT-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} ; GCN-NOOPT-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
define amdgpu_kernel void @update_dpp64_imm_old_test(i64 addrspace(1)* %arg, i64 %in2) { define amdgpu_kernel void @update_dpp64_imm_old_test(i64 addrspace(1)* %arg, i64 %in2) {
%id = tail call i32 @llvm.amdgcn.workitem.id.x() %id = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id %gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
%load = load i64, i64 addrspace(1)* %gep %load = load i64, i64 addrspace(1)* %gep
Show All 26 Lines

llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll

Show First 20 Lines • Show All 285 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @fma_v2f16_imm_c(
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
%b.val = load <2 x half>, <2 x half> addrspace(1)* %b %b.val = load <2 x half>, <2 x half> addrspace(1)* %b
%r.val = call <2 x half> @llvm.fma.v2f16(<2 x half> %a.val, <2 x half> %b.val, <2 x half> <half 3.0, half 3.0>) %r.val = call <2 x half> @llvm.fma.v2f16(<2 x half> %a.val, <2 x half> %b.val, <2 x half> <half 3.0, half 3.0>)
store <2 x half> %r.val, <2 x half> addrspace(1)* %r store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void ret void
} }
; GCN-LABEL: {{^}}fma_v4f16 ; GCN-LABEL: {{^}}fma_v4f16
; GCN: buffer_load_dwordx2 v{{\[}}[[A_V4_F16_LO:[0-9]+]]:[[A_V4_F16_HI:[0-9]+]]{{\]}} ; GCN: buffer_load_dwordx2 v[[[A_V4_F16_LO:[0-9]+]]:[[A_V4_F16_HI:[0-9]+]]]
; GCN: buffer_load_dwordx2 v{{\[}}[[B_V4_F16_LO:[0-9]+]]:[[B_V4_F16_HI:[0-9]+]]{{\]}} ; GCN: buffer_load_dwordx2 v[[[B_V4_F16_LO:[0-9]+]]:[[B_V4_F16_HI:[0-9]+]]]
; GCN: buffer_load_dwordx2 v{{\[}}[[C_V4_F16_LO:[0-9]+]]:[[C_V4_F16_HI:[0-9]+]]{{\]}} ; GCN: buffer_load_dwordx2 v[[[C_V4_F16_LO:[0-9]+]]:[[C_V4_F16_HI:[0-9]+]]]
; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V4_F16_LO]] ; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V4_F16_LO]]
; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_0:[0-9]+]], 16, v[[A_V4_F16_LO]] ; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_0:[0-9]+]], 16, v[[A_V4_F16_LO]]
; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_V4_F16_HI]] ; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_V4_F16_HI]]
; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_2:[0-9]+]], 16, v[[A_V4_F16_HI]] ; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_2:[0-9]+]], 16, v[[A_V4_F16_HI]]
; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V4_F16_LO]] ; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V4_F16_LO]]
; SI-DAG: v_cvt_f32_f16_e32 v[[C_F32_0:[0-9]+]], v[[C_V4_F16_LO]] ; SI-DAG: v_cvt_f32_f16_e32 v[[C_F32_0:[0-9]+]], v[[C_V4_F16_LO]]
; SI-DAG: v_lshrrev_b32_e32 v[[B_F16_0:[0-9]+]], 16, v[[B_V4_F16_LO]] ; SI-DAG: v_lshrrev_b32_e32 v[[B_F16_0:[0-9]+]], 16, v[[B_V4_F16_LO]]
Show All 35 Lines
; VI-DAG: v_fma_f16 v[[R1_F16_1:[0-9]+]], v[[C_F16_1]], v[[B_F16_1]], v[[A_F16_1]] ; VI-DAG: v_fma_f16 v[[R1_F16_1:[0-9]+]], v[[C_F16_1]], v[[B_F16_1]], v[[A_F16_1]]
; SIVI-DAG: v_or_b32_e32 v[[R_V4_F16_LO:[0-9]+]], v[[R_F16_0]], v[[R1_F16_0]] ; SIVI-DAG: v_or_b32_e32 v[[R_V4_F16_LO:[0-9]+]], v[[R_F16_0]], v[[R1_F16_0]]
; SIVI-DAG: v_or_b32_e32 v[[R_V4_F16_HI:[0-9]+]], v[[R_F16_1]], v[[R1_F16_1]] ; SIVI-DAG: v_or_b32_e32 v[[R_V4_F16_HI:[0-9]+]], v[[R_F16_1]], v[[R1_F16_1]]
; GFX9-DAG: v_pk_fma_f16 v[[R_V4_F16_LO:[0-9]+]], v[[A_V4_F16_LO]], v[[B_V4_F16_LO]], v[[C_V4_F16_LO]] ; GFX9-DAG: v_pk_fma_f16 v[[R_V4_F16_LO:[0-9]+]], v[[A_V4_F16_LO]], v[[B_V4_F16_LO]], v[[C_V4_F16_LO]]
; GFX9-DAG: v_pk_fma_f16 v[[R_V4_F16_HI:[0-9]+]], v[[A_V4_F16_HI]], v[[B_V4_F16_HI]], v[[C_V4_F16_HI]] ; GFX9-DAG: v_pk_fma_f16 v[[R_V4_F16_HI:[0-9]+]], v[[A_V4_F16_HI]], v[[B_V4_F16_HI]], v[[C_V4_F16_HI]]
; GCN: buffer_store_dwordx2 v{{\[}}[[R_V4_F16_LO]]:[[R_V4_F16_HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[R_V4_F16_LO]]:[[R_V4_F16_HI]]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @fma_v4f16( define amdgpu_kernel void @fma_v4f16(
<4 x half> addrspace(1)* %r, <4 x half> addrspace(1)* %r,
<4 x half> addrspace(1)* %a, <4 x half> addrspace(1)* %a,
<4 x half> addrspace(1)* %b, <4 x half> addrspace(1)* %b,
<4 x half> addrspace(1)* %c) { <4 x half> addrspace(1)* %c) {
%a.val = load <4 x half>, <4 x half> addrspace(1)* %a %a.val = load <4 x half>, <4 x half> addrspace(1)* %a
%b.val = load <4 x half>, <4 x half> addrspace(1)* %b %b.val = load <4 x half>, <4 x half> addrspace(1)* %b
%c.val = load <4 x half>, <4 x half> addrspace(1)* %c %c.val = load <4 x half>, <4 x half> addrspace(1)* %c
%r.val = call <4 x half> @llvm.fma.v4f16(<4 x half> %a.val, <4 x half> %b.val, <4 x half> %c.val) %r.val = call <4 x half> @llvm.fma.v4f16(<4 x half> %a.val, <4 x half> %b.val, <4 x half> %c.val)
store <4 x half> %r.val, <4 x half> addrspace(1)* %r store <4 x half> %r.val, <4 x half> addrspace(1)* %r
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/load-constant-i8.ll

Show First 20 Lines • Show All 557 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @constant_sextload_v64i8_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i8> addrspace(4)* %in) #0 {
store <64 x i32> %ext, <64 x i32> addrspace(1)* %out store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_i8_to_i64: ; FUNC-LABEL: {{^}}constant_zextload_i8_to_i64:
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; GCN-NOHSA-DAG: buffer_load_ubyte v[[LO:[0-9]+]], ; GCN-NOHSA-DAG: buffer_load_ubyte v[[LO:[0-9]+]],
; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] ; GCN-NOHSA: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
; GCN-HSA-DAG: flat_load_ubyte v[[LO:[0-9]+]], ; GCN-HSA-DAG: flat_load_ubyte v[[LO:[0-9]+]],
; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]] ; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; EG: MOV {{.*}}, 0.0 ; EG: MOV {{.*}}, 0.0
define amdgpu_kernel void @constant_zextload_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(4)* %in) #0 { define amdgpu_kernel void @constant_zextload_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(4)* %in) #0 {
%a = load i8, i8 addrspace(4)* %in %a = load i8, i8 addrspace(4)* %in
%ext = zext i8 %a to i64 %ext = zext i8 %a to i64
store i64 %ext, i64 addrspace(1)* %out store i64 %ext, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_i8_to_i64: ; FUNC-LABEL: {{^}}constant_sextload_i8_to_i64:
; GCN-NOHSA: buffer_load_sbyte v[[LO:[0-9]+]], ; GCN-NOHSA: buffer_load_sbyte v[[LO:[0-9]+]],
; GCN-HSA: flat_load_sbyte v[[LO:[0-9]+]], ; GCN-HSA: flat_load_sbyte v[[LO:[0-9]+]],
; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN-NOHSA: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; EG: ASHR {{\**}} {{T[0-9]\.[XYZW]}}, {{.*}}, literal ; EG: ASHR {{\**}} {{T[0-9]\.[XYZW]}}, {{.*}}, literal
; TODO: Why not 7 ? ; TODO: Why not 7 ?
; EG: 31 ; EG: 31
define amdgpu_kernel void @constant_sextload_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(4)* %in) #0 { define amdgpu_kernel void @constant_sextload_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(4)* %in) #0 {
%a = load i8, i8 addrspace(4)* %in %a = load i8, i8 addrspace(4)* %in
%ext = sext i8 %a to i64 %ext = sext i8 %a to i64
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llvm/test/CodeGen/AMDGPU/load-global-i32.ll

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; FUNC-LABEL: {{^}}global_zextload_i32_to_i64: ; FUNC-LABEL: {{^}}global_zextload_i32_to_i64:
; GCN-NOHSA-DAG: buffer_load_dword v[[LO:[0-9]+]], ; GCN-NOHSA-DAG: buffer_load_dword v[[LO:[0-9]+]],
; GCN-HSA-DAG: {{flat|global}}_load_dword v[[LO:[0-9]+]], ; GCN-HSA-DAG: {{flat|global}}_load_dword v[[LO:[0-9]+]],
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] ; GCN-NOHSA: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
; GCN-HSA: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]] ; GCN-HSA: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY ; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
define amdgpu_kernel void @global_zextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { define amdgpu_kernel void @global_zextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
%ld = load i32, i32 addrspace(1)* %in %ld = load i32, i32 addrspace(1)* %in
%ext = zext i32 %ld to i64 %ext = zext i32 %ld to i64
store i64 %ext, i64 addrspace(1)* %out store i64 %ext, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_sextload_i32_to_i64: ; FUNC-LABEL: {{^}}global_sextload_i32_to_i64:
; GCN-NOHSA: buffer_load_dword v[[LO:[0-9]+]] ; GCN-NOHSA: buffer_load_dword v[[LO:[0-9]+]]
; GCN-HSA: {{flat|global}}_load_dword v[[LO:[0-9]+]] ; GCN-HSA: {{flat|global}}_load_dword v[[LO:[0-9]+]]
; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN-NOHSA: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
; GCN-HSA: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN-HSA: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
; EG: MEM_RAT ; EG: MEM_RAT
; EG: VTX_READ_32 ; EG: VTX_READ_32
; EG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal. ; EG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal.
; EG: 31 ; EG: 31
define amdgpu_kernel void @global_sextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { define amdgpu_kernel void @global_sextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
%ld = load i32, i32 addrspace(1)* %in %ld = load i32, i32 addrspace(1)* %in
Show All 14 Linesdefine amdgpu_kernel void @global_zextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* %in) #0 {
store <1 x i64> %ext, <1 x i64> addrspace(1)* %out store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_sextload_v1i32_to_v1i64: ; FUNC-LABEL: {{^}}global_sextload_v1i32_to_v1i64:
; GCN-NOHSA: buffer_load_dword v[[LO:[0-9]+]] ; GCN-NOHSA: buffer_load_dword v[[LO:[0-9]+]]
; GCN-HSA: {{flat|global}}_load_dword v[[LO:[0-9]+]] ; GCN-HSA: {{flat|global}}_load_dword v[[LO:[0-9]+]]
; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN-NOHSA: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
; GCN-HSA: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN-HSA: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @global_sextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_sextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* %in) #0 {
%ld = load <1 x i32>, <1 x i32> addrspace(1)* %in %ld = load <1 x i32>, <1 x i32> addrspace(1)* %in
%ext = sext <1 x i32> %ld to <1 x i64> %ext = sext <1 x i32> %ld to <1 x i64>
store <1 x i64> %ext, <1 x i64> addrspace(1)* %out store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_zextload_v2i32_to_v2i64: ; FUNC-LABEL: {{^}}global_zextload_v2i32_to_v2i64:
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llvm/test/CodeGen/AMDGPU/load-global-i8.ll

Show First 20 Lines • Show All 563 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @global_sextload_v64i8_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i8> addrspace(1)* %in) #0 {
store <64 x i32> %ext, <64 x i32> addrspace(1)* %out store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_zextload_i8_to_i64: ; FUNC-LABEL: {{^}}global_zextload_i8_to_i64:
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; GCN-NOHSA-DAG: buffer_load_ubyte v[[LO:[0-9]+]], ; GCN-NOHSA-DAG: buffer_load_ubyte v[[LO:[0-9]+]],
; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] ; GCN-NOHSA: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
; GCN-HSA-DAG: flat_load_ubyte v[[LO:[0-9]+]], ; GCN-HSA-DAG: flat_load_ubyte v[[LO:[0-9]+]],
; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]] ; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; EG: MOV {{.*}}, 0.0 ; EG: MOV {{.*}}, 0.0
define amdgpu_kernel void @global_zextload_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* %in) #0 { define amdgpu_kernel void @global_zextload_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* %in) #0 {
%a = load i8, i8 addrspace(1)* %in %a = load i8, i8 addrspace(1)* %in
%ext = zext i8 %a to i64 %ext = zext i8 %a to i64
store i64 %ext, i64 addrspace(1)* %out store i64 %ext, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_sextload_i8_to_i64: ; FUNC-LABEL: {{^}}global_sextload_i8_to_i64:
; GCN-NOHSA: buffer_load_sbyte v[[LO:[0-9]+]], ; GCN-NOHSA: buffer_load_sbyte v[[LO:[0-9]+]],
; GCN-HSA: flat_load_sbyte v[[LO:[0-9]+]], ; GCN-HSA: flat_load_sbyte v[[LO:[0-9]+]],
; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN-NOHSA: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; EG: ASHR {{\**}} {{T[0-9]\.[XYZW]}}, {{.*}}, literal ; EG: ASHR {{\**}} {{T[0-9]\.[XYZW]}}, {{.*}}, literal
; TODO: Why not 7 ? ; TODO: Why not 7 ?
; EG: 31 ; EG: 31
define amdgpu_kernel void @global_sextload_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* %in) #0 { define amdgpu_kernel void @global_sextload_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* %in) #0 {
%a = load i8, i8 addrspace(1)* %in %a = load i8, i8 addrspace(1)* %in
%ext = sext i8 %a to i64 %ext = sext i8 %a to i64
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llvm/test/CodeGen/AMDGPU/load-local-i16.ll

Show First 20 Lines • Show All 600 Lines • ▼ Show 20 Lines
; FUNC-LABEL: {{^}}local_zextload_i16_to_i64: ; FUNC-LABEL: {{^}}local_zextload_i16_to_i64:
; GFX9-NOT: m0 ; GFX9-NOT: m0
; SICIVI: s_mov_b32 m0 ; SICIVI: s_mov_b32 m0
; GCN-DAG: ds_read_u16 v[[LO:[0-9]+]], ; GCN-DAG: ds_read_u16 v[[LO:[0-9]+]],
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; GCN: ds_write_b64 v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]] ; GCN: ds_write_b64 v{{[0-9]+}}, v[[[LO]]:[[HI]]]
; EG: MOV {{[* ]*}}[[FROM:T[0-9]+\.[XYZW]]], KC0[2].Z ; EG: MOV {{[* ]*}}[[FROM:T[0-9]+\.[XYZW]]], KC0[2].Z
; EG: LDS_USHORT_READ_RET {{.*}} [[FROM]] ; EG: LDS_USHORT_READ_RET {{.*}} [[FROM]]
; EG-DAG: MOV {{[* ]*}}[[DATA:T[0-9]+\.[XYZW]]], OQAP ; EG-DAG: MOV {{[* ]*}}[[DATA:T[0-9]+\.[XYZW]]], OQAP
; EG-DAG: MOV {{[* ]*}}[[TO:T[0-9]+\.[XYZW]]], KC0[2].Y ; EG-DAG: MOV {{[* ]*}}[[TO:T[0-9]+\.[XYZW]]], KC0[2].Y
; EG-DAG: LDS_WRITE ; EG-DAG: LDS_WRITE
define amdgpu_kernel void @local_zextload_i16_to_i64(i64 addrspace(3)* %out, i16 addrspace(3)* %in) #0 { define amdgpu_kernel void @local_zextload_i16_to_i64(i64 addrspace(3)* %out, i16 addrspace(3)* %in) #0 {
%a = load i16, i16 addrspace(3)* %in %a = load i16, i16 addrspace(3)* %in
Show All 10 Lines
; t25: i32,ch = load<LD2[%in(addrspace=3)], anyext from i16> t12, t10, undef:i32 ; t25: i32,ch = load<LD2[%in(addrspace=3)], anyext from i16> t12, t10, undef:i32
; t28: i64 = any_extend t25 ; t28: i64 = any_extend t25
; t30: i64 = sign_extend_inreg t28, ValueType:ch:i16 ; t30: i64 = sign_extend_inreg t28, ValueType:ch:i16
; SI: ds_read_i16 v[[LO:[0-9]+]], ; SI: ds_read_i16 v[[LO:[0-9]+]],
; GFX89: ds_read_u16 v[[ULO:[0-9]+]] ; GFX89: ds_read_u16 v[[ULO:[0-9]+]]
; GFX89: v_bfe_i32 v[[LO:[0-9]+]], v[[ULO]], 0, 16 ; GFX89: v_bfe_i32 v[[LO:[0-9]+]], v[[ULO]], 0, 16
; GCN-DAG: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN-DAG: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; GCN: ds_write_b64 v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]] ; GCN: ds_write_b64 v{{[0-9]+}}, v[[[LO]]:[[HI]]]
; EG: MOV {{[* ]*}}[[FROM:T[0-9]+\.[XYZW]]], KC0[2].Z ; EG: MOV {{[* ]*}}[[FROM:T[0-9]+\.[XYZW]]], KC0[2].Z
; EG: LDS_USHORT_READ_RET {{.*}} [[FROM]] ; EG: LDS_USHORT_READ_RET {{.*}} [[FROM]]
; EG-DAG: MOV {{[* ]*}}[[TMP:T[0-9]+\.[XYZW]]], OQAP ; EG-DAG: MOV {{[* ]*}}[[TMP:T[0-9]+\.[XYZW]]], OQAP
; EG-DAG: MOV {{[* ]*}}[[TO:T[0-9]+\.[XYZW]]], KC0[2].Y ; EG-DAG: MOV {{[* ]*}}[[TO:T[0-9]+\.[XYZW]]], KC0[2].Y
; EG-DAG: BFE_INT {{[* ]*}}[[DATA:T[0-9]+\.[XYZW]]], {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}[[DATA:T[0-9]+\.[XYZW]]], {{.*}}, 0.0, literal
; EG-DAG: LDS_WRITE ; EG-DAG: LDS_WRITE
; EG-DAG: 16 ; EG-DAG: 16
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llvm/test/CodeGen/AMDGPU/load-local-i8.ll

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
entry: entry:
%ld = load <8 x i8>, <8 x i8> addrspace(3)* %in %ld = load <8 x i8>, <8 x i8> addrspace(3)* %in
store <8 x i8> %ld, <8 x i8> addrspace(3)* %out store <8 x i8> %ld, <8 x i8> addrspace(3)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}local_load_v16i8: ; FUNC-LABEL: {{^}}local_load_v16i8:
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN: ds_read2_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}} ; GCN: ds_read2_b64 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]], v{{[0-9]+}} offset1:1{{$}}
; GCN: ds_write2_b64 v{{[0-9]+}}, v{{\[}}[[LO]]:{{[0-9]+}}], v[{{[0-9]+}}:[[HI]]{{\]}} offset1:1{{$}} ; GCN: ds_write2_b64 v{{[0-9]+}}, v[[[LO]]:{{[0-9]+}}], v[{{[0-9]+}}:[[HI]]] offset1:1{{$}}
; EG: LDS_READ_RET ; EG: LDS_READ_RET
; EG: LDS_READ_RET ; EG: LDS_READ_RET
; EG: LDS_READ_RET ; EG: LDS_READ_RET
; EG: LDS_READ_RET ; EG: LDS_READ_RET
define amdgpu_kernel void @local_load_v16i8(<16 x i8> addrspace(3)* %out, <16 x i8> addrspace(3)* %in) #0 { define amdgpu_kernel void @local_load_v16i8(<16 x i8> addrspace(3)* %out, <16 x i8> addrspace(3)* %in) #0 {
entry: entry:
%ld = load <16 x i8>, <16 x i8> addrspace(3)* %in %ld = load <16 x i8>, <16 x i8> addrspace(3)* %in
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} }
; FUNC-LABEL: {{^}}local_zextload_i8_to_i64: ; FUNC-LABEL: {{^}}local_zextload_i8_to_i64:
; SICIVI: s_mov_b32 m0 ; SICIVI: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; GCN-DAG: ds_read_u8 v[[LO:[0-9]+]], ; GCN-DAG: ds_read_u8 v[[LO:[0-9]+]],
; GCN: ds_write_b64 v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]] ; GCN: ds_write_b64 v{{[0-9]+}}, v[[[LO]]:[[HI]]]
; EG: LDS_UBYTE_READ_RET ; EG: LDS_UBYTE_READ_RET
; EG: MOV {{.*}}, literal ; EG: MOV {{.*}}, literal
; EG: 0.0 ; EG: 0.0
define amdgpu_kernel void @local_zextload_i8_to_i64(i64 addrspace(3)* %out, i8 addrspace(3)* %in) #0 { define amdgpu_kernel void @local_zextload_i8_to_i64(i64 addrspace(3)* %out, i8 addrspace(3)* %in) #0 {
%a = load i8, i8 addrspace(3)* %in %a = load i8, i8 addrspace(3)* %in
%ext = zext i8 %a to i64 %ext = zext i8 %a to i64
store i64 %ext, i64 addrspace(3)* %out store i64 %ext, i64 addrspace(3)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}local_sextload_i8_to_i64: ; FUNC-LABEL: {{^}}local_sextload_i8_to_i64:
; SICIVI: s_mov_b32 m0 ; SICIVI: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN: ds_read_i8 v[[LO:[0-9]+]], ; GCN: ds_read_i8 v[[LO:[0-9]+]],
; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; GCN: ds_write_b64 v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: ds_write_b64 v{{[0-9]+}}, v[[[LO]]:[[HI]]]
; EG: LDS_UBYTE_READ_RET ; EG: LDS_UBYTE_READ_RET
; EG: ASHR ; EG: ASHR
; TODO: why not 7? ; TODO: why not 7?
; EG: 31 ; EG: 31
define amdgpu_kernel void @local_sextload_i8_to_i64(i64 addrspace(3)* %out, i8 addrspace(3)* %in) #0 { define amdgpu_kernel void @local_sextload_i8_to_i64(i64 addrspace(3)* %out, i8 addrspace(3)* %in) #0 {
%a = load i8, i8 addrspace(3)* %in %a = load i8, i8 addrspace(3)* %in
%ext = sext i8 %a to i64 %ext = sext i8 %a to i64
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llvm/test/CodeGen/AMDGPU/local-atomics64.ll

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; SICIVI-DAG: s_mov_b32 m0 ; SICIVI-DAG: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; SI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c ; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
; GCN-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 9 ; GCN-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 9
; GCN-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0 ; GCN-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0
; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v[[[LOVDATA]]:[[HIVDATA]]] offset:32
; GCN: buffer_store_dwordx2 [[RESULT]], ; GCN: buffer_store_dwordx2 [[RESULT]],
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @lds_atomic_add_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { define amdgpu_kernel void @lds_atomic_add_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
%gep = getelementptr i64, i64 addrspace(3)* %ptr, i64 4 %gep = getelementptr i64, i64 addrspace(3)* %ptr, i64 4
%result = atomicrmw add i64 addrspace(3)* %gep, i64 9 seq_cst %result = atomicrmw add i64 addrspace(3)* %gep, i64 9 seq_cst
store i64 %result, i64 addrspace(1)* %out, align 8 store i64 %result, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; GCN-LABEL: {{^}}lds_atomic_add1_ret_i64: ; GCN-LABEL: {{^}}lds_atomic_add1_ret_i64:
; SICIVI-DAG: s_mov_b32 m0 ; SICIVI-DAG: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 1{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 1{{$}}
; GCN-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0{{$}}
; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v[[[LOVDATA]]:[[HIVDATA]]]
; GCN: buffer_store_dwordx2 [[RESULT]], ; GCN: buffer_store_dwordx2 [[RESULT]],
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @lds_atomic_add1_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { define amdgpu_kernel void @lds_atomic_add1_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
%result = atomicrmw add i64 addrspace(3)* %ptr, i64 1 seq_cst %result = atomicrmw add i64 addrspace(3)* %ptr, i64 1 seq_cst
store i64 %result, i64 addrspace(1)* %out, align 8 store i64 %result, i64 addrspace(1)* %out, align 8
ret void ret void
} }
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} }
; GCN-LABEL: {{^}}lds_atomic_sub1_ret_i64: ; GCN-LABEL: {{^}}lds_atomic_sub1_ret_i64:
; SICIVI-DAG: s_mov_b32 m0 ; SICIVI-DAG: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 1{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 1{{$}}
; GCN-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0{{$}}
; GCN: ds_sub_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} ; GCN: ds_sub_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v[[[LOVDATA]]:[[HIVDATA]]]
; GCN: buffer_store_dwordx2 [[RESULT]], ; GCN: buffer_store_dwordx2 [[RESULT]],
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @lds_atomic_sub1_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { define amdgpu_kernel void @lds_atomic_sub1_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
%result = atomicrmw sub i64 addrspace(3)* %ptr, i64 1 seq_cst %result = atomicrmw sub i64 addrspace(3)* %ptr, i64 1 seq_cst
store i64 %result, i64 addrspace(1)* %out, align 8 store i64 %result, i64 addrspace(1)* %out, align 8
ret void ret void
} }
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; SICIVI-DAG: s_mov_b32 m0 ; SICIVI-DAG: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; SI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9 ; SI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24 ; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24
; GCN-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 9 ; GCN-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 9
; GCN-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0 ; GCN-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0
; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
; GCN: ds_add_u64 {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32 ; GCN: ds_add_u64 {{v[0-9]+}}, v[[[LOVDATA]]:[[HIVDATA]]] offset:32
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @lds_atomic_add_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { define amdgpu_kernel void @lds_atomic_add_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
%gep = getelementptr i64, i64 addrspace(3)* %ptr, i64 4 %gep = getelementptr i64, i64 addrspace(3)* %ptr, i64 4
%result = atomicrmw add i64 addrspace(3)* %gep, i64 9 seq_cst %result = atomicrmw add i64 addrspace(3)* %gep, i64 9 seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}lds_atomic_add1_noret_i64: ; GCN-LABEL: {{^}}lds_atomic_add1_noret_i64:
; SICIVI-DAG: s_mov_b32 m0 ; SICIVI-DAG: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 1{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 1{{$}}
; GCN-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0{{$}}
; GCN: ds_add_u64 {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} ; GCN: ds_add_u64 {{v[0-9]+}}, v[[[LOVDATA]]:[[HIVDATA]]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @lds_atomic_add1_noret_i64(i64 addrspace(3)* %ptr) nounwind { define amdgpu_kernel void @lds_atomic_add1_noret_i64(i64 addrspace(3)* %ptr) nounwind {
%result = atomicrmw add i64 addrspace(3)* %ptr, i64 1 seq_cst %result = atomicrmw add i64 addrspace(3)* %ptr, i64 1 seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}lds_atomic_add1_noret_i64_offset: ; GCN-LABEL: {{^}}lds_atomic_add1_noret_i64_offset:
; SICIVI: s_mov_b32 m0 ; SICIVI: s_mov_b32 m0
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} }
; GCN-LABEL: {{^}}lds_atomic_sub1_noret_i64: ; GCN-LABEL: {{^}}lds_atomic_sub1_noret_i64:
; SICIVI-DAG: s_mov_b32 m0 ; SICIVI-DAG: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 1{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 1{{$}}
; GCN-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0{{$}}
; GCN: ds_sub_u64 {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} ; GCN: ds_sub_u64 {{v[0-9]+}}, v[[[LOVDATA]]:[[HIVDATA]]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @lds_atomic_sub1_noret_i64(i64 addrspace(3)* %ptr) nounwind { define amdgpu_kernel void @lds_atomic_sub1_noret_i64(i64 addrspace(3)* %ptr) nounwind {
%result = atomicrmw sub i64 addrspace(3)* %ptr, i64 1 seq_cst %result = atomicrmw sub i64 addrspace(3)* %ptr, i64 1 seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}lds_atomic_sub1_noret_i64_offset: ; GCN-LABEL: {{^}}lds_atomic_sub1_noret_i64_offset:
; SICIVI: s_mov_b32 m0 ; SICIVI: s_mov_b32 m0
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llvm/test/CodeGen/AMDGPU/memcpy-scoped-aa.ll

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; MIR-DAG: ![[SET1:[0-9]+]] = !{![[SCOPE1]]} ; MIR-DAG: ![[SET1:[0-9]+]] = !{![[SCOPE1]]}
; MIR-LABEL: name: test_memcpy ; MIR-LABEL: name: test_memcpy
; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (load (s128) from %ir.p1, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1) ; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (load (s128) from %ir.p1, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1) ; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
define i32 @test_memcpy(i32 addrspace(1)* nocapture %p, i32 addrspace(1)* nocapture readonly %q) { define i32 @test_memcpy(i32 addrspace(1)* nocapture %p, i32 addrspace(1)* nocapture readonly %q) {
; Check loads of %q are scheduled ahead of that store of the memcpy on %p. ; Check loads of %q are scheduled ahead of that store of the memcpy on %p.
; CHECK-LABEL: test_memcpy: ; CHECK-LABEL: test_memcpy:
; CHECK-DAG: global_load_dwordx2 v{{\[}}[[Q0:[0-9]+]]:[[Q1:[0-9]+]]{{\]}}, v[2:3], off ; CHECK-DAG: global_load_dwordx2 v[[[Q0:[0-9]+]]:[[Q1:[0-9]+]]], v[2:3], off
; CHECK-DAG: global_load_dwordx4 [[PVAL:v\[[0-9]+:[0-9]+\]]], v[0:1], off offset:16 ; CHECK-DAG: global_load_dwordx4 [[PVAL:v\[[0-9]+:[0-9]+\]]], v[0:1], off offset:16
; CHECK-DAG: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]] ; CHECK-DAG: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]]
; CHECK: global_store_dwordx4 v[0:1], [[PVAL]], off ; CHECK: global_store_dwordx4 v[0:1], [[PVAL]], off
; CHECK: s_setpc_b64 s[30:31] ; CHECK: s_setpc_b64 s[30:31]
%p0 = bitcast i32 addrspace(1)* %p to i8 addrspace(1)* %p0 = bitcast i32 addrspace(1)* %p to i8 addrspace(1)*
%add.ptr = getelementptr inbounds i32, i32 addrspace(1)* %p, i64 4 %add.ptr = getelementptr inbounds i32, i32 addrspace(1)* %p, i64 4
%p1 = bitcast i32 addrspace(1)* %add.ptr to i8 addrspace(1)* %p1 = bitcast i32 addrspace(1)* %add.ptr to i8 addrspace(1)*
tail call void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p0, i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p1, i64 16, i1 false), !alias.scope !2, !noalias !4 tail call void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p0, i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p1, i64 16, i1 false), !alias.scope !2, !noalias !4
%v0 = load i32, i32 addrspace(1)* %q, align 4, !alias.scope !4, !noalias !2 %v0 = load i32, i32 addrspace(1)* %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, i32 addrspace(1)* %q, i64 1 %q1 = getelementptr inbounds i32, i32 addrspace(1)* %q, i64 1
%v1 = load i32, i32 addrspace(1)* %q1, align 4, !alias.scope !4, !noalias !2 %v1 = load i32, i32 addrspace(1)* %q1, align 4, !alias.scope !4, !noalias !2
%add = add i32 %v0, %v1 %add = add i32 %v0, %v1
ret i32 %add ret i32 %add
} }
; MIR-LABEL: name: test_memcpy_inline ; MIR-LABEL: name: test_memcpy_inline
; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (load (s128) from %ir.p1, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1) ; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (load (s128) from %ir.p1, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1) ; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
define i32 @test_memcpy_inline(i32 addrspace(1)* nocapture %p, i32 addrspace(1)* nocapture readonly %q) { define i32 @test_memcpy_inline(i32 addrspace(1)* nocapture %p, i32 addrspace(1)* nocapture readonly %q) {
; Check loads of %q are scheduled ahead of that store of the memcpy on %p. ; Check loads of %q are scheduled ahead of that store of the memcpy on %p.
; CHECK-LABEL: test_memcpy_inline: ; CHECK-LABEL: test_memcpy_inline:
; CHECK-DAG: global_load_dwordx2 v{{\[}}[[Q0:[0-9]+]]:[[Q1:[0-9]+]]{{\]}}, v[2:3], off ; CHECK-DAG: global_load_dwordx2 v[[[Q0:[0-9]+]]:[[Q1:[0-9]+]]], v[2:3], off
; CHECK-DAG: global_load_dwordx4 [[PVAL:v\[[0-9]+:[0-9]+\]]], v[0:1], off offset:16 ; CHECK-DAG: global_load_dwordx4 [[PVAL:v\[[0-9]+:[0-9]+\]]], v[0:1], off offset:16
; CHECK-DAG: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]] ; CHECK-DAG: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]]
; CHECK: global_store_dwordx4 v[0:1], [[PVAL]], off ; CHECK: global_store_dwordx4 v[0:1], [[PVAL]], off
; CHECK: s_setpc_b64 s[30:31] ; CHECK: s_setpc_b64 s[30:31]
%p0 = bitcast i32 addrspace(1)* %p to i8 addrspace(1)* %p0 = bitcast i32 addrspace(1)* %p to i8 addrspace(1)*
%add.ptr = getelementptr inbounds i32, i32 addrspace(1)* %p, i64 4 %add.ptr = getelementptr inbounds i32, i32 addrspace(1)* %p, i64 4
%p1 = bitcast i32 addrspace(1)* %add.ptr to i8 addrspace(1)* %p1 = bitcast i32 addrspace(1)* %add.ptr to i8 addrspace(1)*
tail call void @llvm.memcpy.inline.p1i8.p1i8.i64(i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p0, i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p1, i64 16, i1 false), !alias.scope !2, !noalias !4 tail call void @llvm.memcpy.inline.p1i8.p1i8.i64(i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p0, i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p1, i64 16, i1 false), !alias.scope !2, !noalias !4
%v0 = load i32, i32 addrspace(1)* %q, align 4, !alias.scope !4, !noalias !2 %v0 = load i32, i32 addrspace(1)* %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, i32 addrspace(1)* %q, i64 1 %q1 = getelementptr inbounds i32, i32 addrspace(1)* %q, i64 1
%v1 = load i32, i32 addrspace(1)* %q1, align 4, !alias.scope !4, !noalias !2 %v1 = load i32, i32 addrspace(1)* %q1, align 4, !alias.scope !4, !noalias !2
%add = add i32 %v0, %v1 %add = add i32 %v0, %v1
ret i32 %add ret i32 %add
} }
; MIR-LABEL: name: test_memmove ; MIR-LABEL: name: test_memmove
; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (load (s128) from %ir.p1, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1) ; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (load (s128) from %ir.p1, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1) ; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
define i32 @test_memmove(i32 addrspace(1)* nocapture %p, i32 addrspace(1)* nocapture readonly %q) { define i32 @test_memmove(i32 addrspace(1)* nocapture %p, i32 addrspace(1)* nocapture readonly %q) {
; Check loads of %q are scheduled ahead of that store of the memmove on %p. ; Check loads of %q are scheduled ahead of that store of the memmove on %p.
; CHECK-LABEL: test_memmove: ; CHECK-LABEL: test_memmove:
; CHECK-DAG: global_load_dwordx2 v{{\[}}[[Q0:[0-9]+]]:[[Q1:[0-9]+]]{{\]}}, v[2:3], off ; CHECK-DAG: global_load_dwordx2 v[[[Q0:[0-9]+]]:[[Q1:[0-9]+]]], v[2:3], off
; CHECK-DAG: global_load_dwordx4 [[PVAL:v\[[0-9]+:[0-9]+\]]], v[0:1], off offset:16 ; CHECK-DAG: global_load_dwordx4 [[PVAL:v\[[0-9]+:[0-9]+\]]], v[0:1], off offset:16
; CHECK-DAG: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]] ; CHECK-DAG: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]]
; CHECK: global_store_dwordx4 v[0:1], [[PVAL]] ; CHECK: global_store_dwordx4 v[0:1], [[PVAL]]
; CHECK: s_setpc_b64 s[30:31] ; CHECK: s_setpc_b64 s[30:31]
%p0 = bitcast i32 addrspace(1)* %p to i8 addrspace(1)* %p0 = bitcast i32 addrspace(1)* %p to i8 addrspace(1)*
%add.ptr = getelementptr inbounds i32, i32 addrspace(1)* %p, i64 4 %add.ptr = getelementptr inbounds i32, i32 addrspace(1)* %p, i64 4
%p1 = bitcast i32 addrspace(1)* %add.ptr to i8 addrspace(1)* %p1 = bitcast i32 addrspace(1)* %add.ptr to i8 addrspace(1)*
tail call void @llvm.memmove.p1i8.p1i8.i64(i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p0, i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p1, i64 16, i1 false), !alias.scope !2, !noalias !4 tail call void @llvm.memmove.p1i8.p1i8.i64(i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p0, i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p1, i64 16, i1 false), !alias.scope !2, !noalias !4
%v0 = load i32, i32 addrspace(1)* %q, align 4, !alias.scope !4, !noalias !2 %v0 = load i32, i32 addrspace(1)* %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, i32 addrspace(1)* %q, i64 1 %q1 = getelementptr inbounds i32, i32 addrspace(1)* %q, i64 1
%v1 = load i32, i32 addrspace(1)* %q1, align 4, !alias.scope !4, !noalias !2 %v1 = load i32, i32 addrspace(1)* %q1, align 4, !alias.scope !4, !noalias !2
%add = add i32 %v0, %v1 %add = add i32 %v0, %v1
ret i32 %add ret i32 %add
} }
; MIR-LABEL: name: test_memset ; MIR-LABEL: name: test_memset
; MIR: GLOBAL_STORE_DWORDX4 killed %{{[0-9]+}}, killed %{{[0-9]+}}, 0, 0, implicit $exec :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1) ; MIR: GLOBAL_STORE_DWORDX4 killed %{{[0-9]+}}, killed %{{[0-9]+}}, 0, 0, implicit $exec :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
define i32 @test_memset(i32 addrspace(1)* nocapture %p, i32 addrspace(1)* nocapture readonly %q) { define i32 @test_memset(i32 addrspace(1)* nocapture %p, i32 addrspace(1)* nocapture readonly %q) {
; Check loads of %q are scheduled ahead of that store of the memset on %p. ; Check loads of %q are scheduled ahead of that store of the memset on %p.
; CHECK-LABEL: test_memset: ; CHECK-LABEL: test_memset:
; CHECK-DAG: global_load_dwordx2 v{{\[}}[[Q0:[0-9]+]]:[[Q1:[0-9]+]]{{\]}}, v[2:3], off ; CHECK-DAG: global_load_dwordx2 v[[[Q0:[0-9]+]]:[[Q1:[0-9]+]]], v[2:3], off
; CHECK-DAG: v_mov_b32_e32 v[[PVAL:[0-9]+]], 0xaaaaaaaa ; CHECK-DAG: v_mov_b32_e32 v[[PVAL:[0-9]+]], 0xaaaaaaaa
; CHECK: global_store_dwordx4 v[0:1], v{{\[}}[[PVAL]]{{:[0-9]+\]}}, off ; CHECK: global_store_dwordx4 v[0:1], v[[[PVAL]]{{:[0-9]+\]}}, off
; CHECK: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]] ; CHECK: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]]
; CHECK: s_setpc_b64 s[30:31] ; CHECK: s_setpc_b64 s[30:31]
%p0 = bitcast i32 addrspace(1)* %p to i8 addrspace(1)* %p0 = bitcast i32 addrspace(1)* %p to i8 addrspace(1)*
tail call void @llvm.memset.p1i8.i64(i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p0, i8 170, i64 16, i1 false), !alias.scope !2, !noalias !4 tail call void @llvm.memset.p1i8.i64(i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p0, i8 170, i64 16, i1 false), !alias.scope !2, !noalias !4
%v0 = load i32, i32 addrspace(1)* %q, align 4, !alias.scope !4, !noalias !2 %v0 = load i32, i32 addrspace(1)* %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, i32 addrspace(1)* %q, i64 1 %q1 = getelementptr inbounds i32, i32 addrspace(1)* %q, i64 1
%v1 = load i32, i32 addrspace(1)* %q1, align 4, !alias.scope !4, !noalias !2 %v1 = load i32, i32 addrspace(1)* %q1, align 4, !alias.scope !4, !noalias !2
%add = add i32 %v0, %v1 %add = add i32 %v0, %v1
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llvm/test/CodeGen/AMDGPU/merge-stores.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @merge_global_store_2_constants_i16_natural_align(i16 addrspace(1)* %out) #0 {
store i16 123, i16 addrspace(1)* %out.gep.1 store i16 123, i16 addrspace(1)* %out.gep.1
store i16 456, i16 addrspace(1)* %out store i16 456, i16 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}merge_global_store_2_constants_i32: ; GCN-LABEL: {{^}}merge_global_store_2_constants_i32:
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0x1c8 ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0x1c8
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7b ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7b
; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
define amdgpu_kernel void @merge_global_store_2_constants_i32(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @merge_global_store_2_constants_i32(i32 addrspace(1)* %out) #0 {
%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1 %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
store i32 123, i32 addrspace(1)* %out.gep.1 store i32 123, i32 addrspace(1)* %out.gep.1
store i32 456, i32 addrspace(1)* %out store i32 456, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}merge_global_store_2_constants_i32_f32: ; GCN-LABEL: {{^}}merge_global_store_2_constants_i32_f32:
; GCN: buffer_store_dwordx2 ; GCN: buffer_store_dwordx2
define amdgpu_kernel void @merge_global_store_2_constants_i32_f32(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @merge_global_store_2_constants_i32_f32(i32 addrspace(1)* %out) #0 {
%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1 %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
%out.gep.1.bc = bitcast i32 addrspace(1)* %out.gep.1 to float addrspace(1)* %out.gep.1.bc = bitcast i32 addrspace(1)* %out.gep.1 to float addrspace(1)*
store float 1.0, float addrspace(1)* %out.gep.1.bc store float 1.0, float addrspace(1)* %out.gep.1.bc
store i32 456, i32 addrspace(1)* %out store i32 456, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}merge_global_store_2_constants_f32_i32: ; GCN-LABEL: {{^}}merge_global_store_2_constants_f32_i32:
; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], 4.0 ; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], 4.0
; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], 0x7b ; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], 0x7b
; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[VLO]]:[[VHI]]]
define amdgpu_kernel void @merge_global_store_2_constants_f32_i32(float addrspace(1)* %out) #0 { define amdgpu_kernel void @merge_global_store_2_constants_f32_i32(float addrspace(1)* %out) #0 {
%out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1 %out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
%out.gep.1.bc = bitcast float addrspace(1)* %out.gep.1 to i32 addrspace(1)* %out.gep.1.bc = bitcast float addrspace(1)* %out.gep.1 to i32 addrspace(1)*
store i32 123, i32 addrspace(1)* %out.gep.1.bc store i32 123, i32 addrspace(1)* %out.gep.1.bc
store float 4.0, float addrspace(1)* %out store float 4.0, float addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}merge_global_store_4_constants_i32: ; GCN-LABEL: {{^}}merge_global_store_4_constants_i32:
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x14d{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x14d{{$}}
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x1c8{{$}} ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x1c8{{$}}
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x7b{{$}} ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x7b{{$}}
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0x4d2{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0x4d2{{$}}
; GCN: buffer_store_dwordx4 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: buffer_store_dwordx4 v[[[LO]]:[[HI]]]
define amdgpu_kernel void @merge_global_store_4_constants_i32(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @merge_global_store_4_constants_i32(i32 addrspace(1)* %out) #0 {
%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1 %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
%out.gep.2 = getelementptr i32, i32 addrspace(1)* %out, i32 2 %out.gep.2 = getelementptr i32, i32 addrspace(1)* %out, i32 2
%out.gep.3 = getelementptr i32, i32 addrspace(1)* %out, i32 3 %out.gep.3 = getelementptr i32, i32 addrspace(1)* %out, i32 3
store i32 123, i32 addrspace(1)* %out.gep.1 store i32 123, i32 addrspace(1)* %out.gep.1
store i32 456, i32 addrspace(1)* %out.gep.2 store i32 456, i32 addrspace(1)* %out.gep.2
store i32 333, i32 addrspace(1)* %out.gep.3 store i32 333, i32 addrspace(1)* %out.gep.3
▲ Show 20 Lines • Show All 410 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @merge_local_store_4_constants_i32(i32 addrspace(3)* %out) #0 {
store i32 333, i32 addrspace(3)* %out.gep.3 store i32 333, i32 addrspace(3)* %out.gep.3
store i32 1234, i32 addrspace(3)* %out store i32 1234, i32 addrspace(3)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}merge_global_store_5_constants_i32: ; GCN-LABEL: {{^}}merge_global_store_5_constants_i32:
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 9{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 9{{$}}
; GCN-DAG: v_mov_b32_e32 v[[HI4:[0-9]+]], -12{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI4:[0-9]+]], -12{{$}}
; GCN: buffer_store_dwordx4 v{{\[}}[[LO]]:[[HI4]]{{\]}} ; GCN: buffer_store_dwordx4 v[[[LO]]:[[HI4]]]
; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], 11{{$}} ; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], 11{{$}}
; GCN: buffer_store_dword v[[HI]] ; GCN: buffer_store_dword v[[HI]]
define amdgpu_kernel void @merge_global_store_5_constants_i32(i32 addrspace(1)* %out) { define amdgpu_kernel void @merge_global_store_5_constants_i32(i32 addrspace(1)* %out) {
store i32 9, i32 addrspace(1)* %out, align 4 store i32 9, i32 addrspace(1)* %out, align 4
%idx1 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 1 %idx1 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 1
store i32 12, i32 addrspace(1)* %idx1, align 4 store i32 12, i32 addrspace(1)* %idx1, align 4
%idx2 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 2 %idx2 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 2
store i32 16, i32 addrspace(1)* %idx2, align 4 store i32 16, i32 addrspace(1)* %idx2, align 4
▲ Show 20 Lines • Show All 148 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/missing-store.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
@ptr_load = addrspace(3) global i32 addrspace(4)* undef, align 8 @ptr_load = addrspace(3) global i32 addrspace(4)* undef, align 8
; Make sure when the load from %ptr2 is folded the chain isn't lost, ; Make sure when the load from %ptr2 is folded the chain isn't lost,
; resulting in losing the store to gptr ; resulting in losing the store to gptr
; FUNC-LABEL: {{^}}missing_store_reduced: ; FUNC-LABEL: {{^}}missing_store_reduced:
; SI: s_load_dwordx4 ; SI: s_load_dwordx4
; SI-DAG: ds_read_b64 ; SI-DAG: ds_read_b64
; SI-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}} ; SI-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
; SI-DAG: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}} ; SI-DAG: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
; SI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}} ; SI-DAG: s_load_dword s{{[0-9]+}}, s[[[PTR_LO]]:[[PTR_HI]]]
; SI-DAG: buffer_store_dword ; SI-DAG: buffer_store_dword
; SI-DAG: buffer_store_dword ; SI-DAG: buffer_store_dword
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @missing_store_reduced(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 { define amdgpu_kernel void @missing_store_reduced(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
%ptr0 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(3)* @ptr_load, align 8 %ptr0 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(3)* @ptr_load, align 8
%ptr2 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 2 %ptr2 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 2
store i32 99, i32 addrspace(1)* %gptr, align 4 store i32 99, i32 addrspace(1)* %gptr, align 4
%tmp2 = load i32, i32 addrspace(4)* %ptr2, align 4 %tmp2 = load i32, i32 addrspace(4)* %ptr2, align 4
store i32 %tmp2, i32 addrspace(1)* %out, align 4 store i32 %tmp2, i32 addrspace(1)* %out, align 4
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll

; RUN: llc -march=amdgcn -mcpu=kaveri -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=kaveri -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s
; Check that when mubuf addr64 instruction is handled in moveToVALU ; Check that when mubuf addr64 instruction is handled in moveToVALU
; from the pointer, dead register writes are not emitted. ; from the pointer, dead register writes are not emitted.
; FIXME: We should be able to use the SGPR directly as src0 to v_add_i32 ; FIXME: We should be able to use the SGPR directly as src0 to v_add_i32
; GCN-LABEL: {{^}}clobber_vgpr_pair_pointer_add: ; GCN-LABEL: {{^}}clobber_vgpr_pair_pointer_add:
; GCN-DAG: buffer_load_dwordx2 v{{\[}}[[LDPTRLO:[0-9]+]]:[[LDPTRHI:[0-9]+]]{{\]}} ; GCN-DAG: buffer_load_dwordx2 v[[[LDPTRLO:[0-9]+]]:[[LDPTRHI:[0-9]+]]]
; GCN-DAG: s_load_dwordx2 s{{\[}}[[ARG1LO:[0-9]+]]:[[ARG1HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}} ; GCN-DAG: s_load_dwordx2 s[[[ARG1LO:[0-9]+]]:[[ARG1HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
; GCN-DAG: v_mov_b32_e32 v[[VARG1LO:[0-9]+]], s[[ARG1LO]] ; GCN-DAG: v_mov_b32_e32 v[[VARG1LO:[0-9]+]], s[[ARG1LO]]
; GCN-DAG: v_mov_b32_e32 v[[VARG1HI:[0-9]+]], s[[ARG1HI]] ; GCN-DAG: v_mov_b32_e32 v[[VARG1HI:[0-9]+]], s[[ARG1HI]]
; GCN-NOT: v_mov_b32 ; GCN-NOT: v_mov_b32
; GCN-NOT: v_mov_b32 ; GCN-NOT: v_mov_b32
; GCN: v_add_i32_e32 v[[PTRLO:[0-9]+]], vcc, v[[LDPTRLO]], v[[VARG1LO]] ; GCN: v_add_i32_e32 v[[PTRLO:[0-9]+]], vcc, v[[LDPTRLO]], v[[VARG1LO]]
; GCN: v_addc_u32_e32 v[[PTRHI:[0-9]+]], vcc, v[[LDPTRHI]], v[[VARG1HI]] ; GCN: v_addc_u32_e32 v[[PTRHI:[0-9]+]], vcc, v[[LDPTRHI]], v[[VARG1HI]]
; GCN: buffer_load_ubyte v{{[0-9]+}}, v{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, ; GCN: buffer_load_ubyte v{{[0-9]+}}, v[[[PTRLO]]:[[PTRHI]]],
define amdgpu_kernel void @clobber_vgpr_pair_pointer_add(i64 %arg1, [8 x i32], i8 addrspace(1)* addrspace(1)* %ptrarg, i32 %arg3) #0 { define amdgpu_kernel void @clobber_vgpr_pair_pointer_add(i64 %arg1, [8 x i32], i8 addrspace(1)* addrspace(1)* %ptrarg, i32 %arg3) #0 {
bb: bb:
%tmp = icmp sgt i32 %arg3, 0 %tmp = icmp sgt i32 %arg3, 0
br i1 %tmp, label %bb4, label %bb17 br i1 %tmp, label %bb4, label %bb17
bb4: bb4:
%tmp14 = load volatile i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* %ptrarg %tmp14 = load volatile i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* %ptrarg
Show All 9 Lines

llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll

; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W64 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W64
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W32 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W32
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W64 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W64
; RUN: llc -O0 -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W64-O0 ; RUN: llc -O0 -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W64-O0
; Test that we correctly legalize VGPR Rsrc operands in MUBUF instructions. ; Test that we correctly legalize VGPR Rsrc operands in MUBUF instructions.
; W64-LABEL: mubuf_vgpr ; W64-LABEL: mubuf_vgpr
; W64: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec ; W64: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec
; W64: [[LOOPBB:.LBB[0-9]+_[0-9]+]]: ; W64: [[LOOPBB:.LBB[0-9]+_[0-9]+]]:
; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W64: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W64: v_cmp_eq_u64_e32 vcc, s[[[SRSRC0]]:[[SRSRC1]]], v[[[VRSRC0]]:[[VRSRC1]]]
; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s[[[SRSRC2]]:[[SRSRC3]]], v[[[VRSRC2]]:[[VRSRC3]]]
; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]] ; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]]
; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]] ; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; W64: buffer_load_format_x [[RES:v[0-9]+]], v{{[0-9]+}}, s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W64: buffer_load_format_x [[RES:v[0-9]+]], v{{[0-9]+}}, s[[[SRSRC0]]:[[SRSRC3]]], 0 idxen
; W64: s_xor_b64 exec, exec, [[AND]] ; W64: s_xor_b64 exec, exec, [[AND]]
; W64: s_cbranch_execnz [[LOOPBB]] ; W64: s_cbranch_execnz [[LOOPBB]]
; W64: s_mov_b64 exec, [[SAVEEXEC]] ; W64: s_mov_b64 exec, [[SAVEEXEC]]
; W64: v_mov_b32_e32 v0, [[RES]] ; W64: v_mov_b32_e32 v0, [[RES]]
; W32-LABEL: mubuf_vgpr ; W32-LABEL: mubuf_vgpr
; W32: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo ; W32: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo
; W32: [[LOOPBB:.LBB[0-9]+_[0-9]+]]: ; W32: [[LOOPBB:.LBB[0-9]+_[0-9]+]]:
; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W32: v_cmp_eq_u64_e32 vcc_lo, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W32: v_cmp_eq_u64_e32 vcc_lo, s[[[SRSRC0]]:[[SRSRC1]]], v[[[VRSRC0]]:[[VRSRC1]]]
; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s[[[SRSRC2]]:[[SRSRC3]]], v[[[VRSRC2]]:[[VRSRC3]]]
; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]] ; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]]
; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]] ; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]]
; W32: buffer_load_format_x [[RES:v[0-9]+]], v{{[0-9]+}}, s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W32: buffer_load_format_x [[RES:v[0-9]+]], v{{[0-9]+}}, s[[[SRSRC0]]:[[SRSRC3]]], 0 idxen
; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]] ; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]]
; W32: s_cbranch_execnz [[LOOPBB]] ; W32: s_cbranch_execnz [[LOOPBB]]
; W32: s_mov_b32 exec_lo, [[SAVEEXEC]] ; W32: s_mov_b32 exec_lo, [[SAVEEXEC]]
; W32: v_mov_b32_e32 v0, [[RES]] ; W32: v_mov_b32_e32 v0, [[RES]]
define float @mubuf_vgpr(<4 x i32> %i, i32 %c) #0 { define float @mubuf_vgpr(<4 x i32> %i, i32 %c) #0 {
%call = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %i, i32 %c, i32 0, i32 0, i32 0) #1 %call = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %i, i32 %c, i32 0, i32 0, i32 0) #1
ret float %call ret float %call
} }
; W64-LABEL: mubuf_vgpr_adjacent_in_block ; W64-LABEL: mubuf_vgpr_adjacent_in_block
; W64: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec ; W64: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec
; W64: [[LOOPBB0:.LBB[0-9]+_[0-9]+]]: ; W64: [[LOOPBB0:.LBB[0-9]+_[0-9]+]]:
; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W64: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W64: v_cmp_eq_u64_e32 vcc, s[[[SRSRC0]]:[[SRSRC1]]], v[[[VRSRC0]]:[[VRSRC1]]]
; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s[[[SRSRC2]]:[[SRSRC3]]], v[[[VRSRC2]]:[[VRSRC3]]]
; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]] ; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]]
; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]] ; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; W64: buffer_load_format_x [[RES0:v[0-9]+]], v{{[0-9]+}}, s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W64: buffer_load_format_x [[RES0:v[0-9]+]], v{{[0-9]+}}, s[[[SRSRC0]]:[[SRSRC3]]], 0 idxen
; W64: s_xor_b64 exec, exec, [[SAVE]] ; W64: s_xor_b64 exec, exec, [[SAVE]]
; W64: s_cbranch_execnz [[LOOPBB0]] ; W64: s_cbranch_execnz [[LOOPBB0]]
; W64: s_mov_b64 exec, [[SAVEEXEC]] ; W64: s_mov_b64 exec, [[SAVEEXEC]]
; FIXME: redundant s_mov ; FIXME: redundant s_mov
; W64: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec ; W64: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec
; W64: [[LOOPBB1:.LBB[0-9]+_[0-9]+]]: ; W64: [[LOOPBB1:.LBB[0-9]+_[0-9]+]]:
; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W64: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W64: v_cmp_eq_u64_e32 vcc, s[[[SRSRC0]]:[[SRSRC1]]], v[[[VRSRC0]]:[[VRSRC1]]]
; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s[[[SRSRC2]]:[[SRSRC3]]], v[[[VRSRC2]]:[[VRSRC3]]]
; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]] ; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]]
; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]] ; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; W64: buffer_load_format_x [[RES1:v[0-9]+]], v{{[0-9]+}}, s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W64: buffer_load_format_x [[RES1:v[0-9]+]], v{{[0-9]+}}, s[[[SRSRC0]]:[[SRSRC3]]], 0 idxen
; W64: s_xor_b64 exec, exec, [[SAVE]] ; W64: s_xor_b64 exec, exec, [[SAVE]]
; W64: s_cbranch_execnz [[LOOPBB1]] ; W64: s_cbranch_execnz [[LOOPBB1]]
; W64: s_mov_b64 exec, [[SAVEEXEC]] ; W64: s_mov_b64 exec, [[SAVEEXEC]]
; W64-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES0]], off ; W64-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES0]], off
; W64-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES1]], off ; W64-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES1]], off
; W32-LABEL: mubuf_vgpr_adjacent_in_block ; W32-LABEL: mubuf_vgpr_adjacent_in_block
; W32: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo ; W32: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo
; W32: [[LOOPBB0:.LBB[0-9]+_[0-9]+]]: ; W32: [[LOOPBB0:.LBB[0-9]+_[0-9]+]]:
; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W32: v_cmp_eq_u64_e32 vcc_lo, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W32: v_cmp_eq_u64_e32 vcc_lo, s[[[SRSRC0]]:[[SRSRC1]]], v[[[VRSRC0]]:[[VRSRC1]]]
; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s[[[SRSRC2]]:[[SRSRC3]]], v[[[VRSRC2]]:[[VRSRC3]]]
; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]] ; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]]
; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]] ; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]]
; W32: buffer_load_format_x [[RES0:v[0-9]+]], v{{[0-9]+}}, s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W32: buffer_load_format_x [[RES0:v[0-9]+]], v{{[0-9]+}}, s[[[SRSRC0]]:[[SRSRC3]]], 0 idxen
; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]] ; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]]
; W32: s_cbranch_execnz [[LOOPBB0]] ; W32: s_cbranch_execnz [[LOOPBB0]]
; W32: s_mov_b32 exec_lo, [[SAVEEXEC]] ; W32: s_mov_b32 exec_lo, [[SAVEEXEC]]
; FIXME: redundant s_mov ; FIXME: redundant s_mov
; W32: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo ; W32: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo
; W32: [[LOOPBB1:.LBB[0-9]+_[0-9]+]]: ; W32: [[LOOPBB1:.LBB[0-9]+_[0-9]+]]:
; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W32: v_cmp_eq_u64_e32 vcc_lo, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W32: v_cmp_eq_u64_e32 vcc_lo, s[[[SRSRC0]]:[[SRSRC1]]], v[[[VRSRC0]]:[[VRSRC1]]]
; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s[[[SRSRC2]]:[[SRSRC3]]], v[[[VRSRC2]]:[[VRSRC3]]]
; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]] ; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]]
; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]] ; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]]
; W32: buffer_load_format_x [[RES1:v[0-9]+]], v8, s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W32: buffer_load_format_x [[RES1:v[0-9]+]], v8, s[[[SRSRC0]]:[[SRSRC3]]], 0 idxen
; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]] ; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]]
; W32: s_cbranch_execnz [[LOOPBB1]] ; W32: s_cbranch_execnz [[LOOPBB1]]
; W32: s_mov_b32 exec_lo, [[SAVEEXEC]] ; W32: s_mov_b32 exec_lo, [[SAVEEXEC]]
; W32-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES0]], off ; W32-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES0]], off
; W32-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES1]], off ; W32-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES1]], off
define void @mubuf_vgpr_adjacent_in_block(<4 x i32> %i, <4 x i32> %j, i32 %c, float addrspace(1)* %out0, float addrspace(1)* %out1) #0 { define void @mubuf_vgpr_adjacent_in_block(<4 x i32> %i, <4 x i32> %j, i32 %c, float addrspace(1)* %out0, float addrspace(1)* %out1) #0 {
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; W64-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s{{[0-9]+}} ; W64-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s{{[0-9]+}}
; W64-DAG: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec ; W64-DAG: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec
; W64: [[LOOPBB0:.LBB[0-9]+_[0-9]+]]: ; W64: [[LOOPBB0:.LBB[0-9]+_[0-9]+]]:
; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W64: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W64: v_cmp_eq_u64_e32 vcc, s[[[SRSRC0]]:[[SRSRC1]]], v[[[VRSRC0]]:[[VRSRC1]]]
; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s[[[SRSRC2]]:[[SRSRC3]]], v[[[VRSRC2]]:[[VRSRC3]]]
; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]] ; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]]
; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]] ; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; W64: buffer_load_format_x [[RES:v[0-9]+]], [[IDX]], s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W64: buffer_load_format_x [[RES:v[0-9]+]], [[IDX]], s[[[SRSRC0]]:[[SRSRC3]]], 0 idxen
; W64: s_xor_b64 exec, exec, [[SAVE]] ; W64: s_xor_b64 exec, exec, [[SAVE]]
; W64: s_cbranch_execnz [[LOOPBB0]] ; W64: s_cbranch_execnz [[LOOPBB0]]
; W64: s_mov_b64 exec, [[SAVEEXEC]] ; W64: s_mov_b64 exec, [[SAVEEXEC]]
; W64: s_cbranch_execz [[TERMBB:.LBB[0-9]+_[0-9]+]] ; W64: s_cbranch_execz [[TERMBB:.LBB[0-9]+_[0-9]+]]
; W64: ; %bb.{{[0-9]+}}: ; W64: ; %bb.{{[0-9]+}}:
; W64-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s{{[0-9]+}} ; W64-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s{{[0-9]+}}
; W64-DAG: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec ; W64-DAG: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec
; W64: [[LOOPBB1:.LBB[0-9]+_[0-9]+]]: ; W64: [[LOOPBB1:.LBB[0-9]+_[0-9]+]]:
; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W64: v_cmp_eq_u64_e32 vcc, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W64: v_cmp_eq_u64_e32 vcc, s[[[SRSRC0]]:[[SRSRC1]]], v[[[VRSRC0]]:[[VRSRC1]]]
; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W64: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s[[[SRSRC2]]:[[SRSRC3]]], v[[[VRSRC2]]:[[VRSRC3]]]
; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]] ; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]]
; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]] ; W64: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; W64: buffer_load_format_x [[RES]], [[IDX]], s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W64: buffer_load_format_x [[RES]], [[IDX]], s[[[SRSRC0]]:[[SRSRC3]]], 0 idxen
; W64: s_xor_b64 exec, exec, [[SAVE]] ; W64: s_xor_b64 exec, exec, [[SAVE]]
; W64: s_cbranch_execnz [[LOOPBB1]] ; W64: s_cbranch_execnz [[LOOPBB1]]
; W64: s_mov_b64 exec, [[SAVEEXEC]] ; W64: s_mov_b64 exec, [[SAVEEXEC]]
; W64: [[TERMBB]]: ; W64: [[TERMBB]]:
; W64: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]], off ; W64: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]], off
; W32-LABEL: mubuf_vgpr_outside_entry ; W32-LABEL: mubuf_vgpr_outside_entry
; W32-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s4 ; W32-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s4
; W32-DAG: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo ; W32-DAG: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo
; W32: [[LOOPBB0:.LBB[0-9]+_[0-9]+]]: ; W32: [[LOOPBB0:.LBB[0-9]+_[0-9]+]]:
; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W32: v_cmp_eq_u64_e32 vcc_lo, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W32: v_cmp_eq_u64_e32 vcc_lo, s[[[SRSRC0]]:[[SRSRC1]]], v[[[VRSRC0]]:[[VRSRC1]]]
; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s[[[SRSRC2]]:[[SRSRC3]]], v[[[VRSRC2]]:[[VRSRC3]]]
; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]] ; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]]
; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]] ; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]]
; W32: buffer_load_format_x [[RES:v[0-9]+]], [[IDX]], s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W32: buffer_load_format_x [[RES:v[0-9]+]], [[IDX]], s[[[SRSRC0]]:[[SRSRC3]]], 0 idxen
; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]] ; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]]
; W32: s_cbranch_execnz [[LOOPBB0]] ; W32: s_cbranch_execnz [[LOOPBB0]]
; W32: s_mov_b32 exec_lo, [[SAVEEXEC]] ; W32: s_mov_b32 exec_lo, [[SAVEEXEC]]
; W32: s_cbranch_execz [[TERMBB:.LBB[0-9]+_[0-9]+]] ; W32: s_cbranch_execz [[TERMBB:.LBB[0-9]+_[0-9]+]]
; W32: ; %bb.{{[0-9]+}}: ; W32: ; %bb.{{[0-9]+}}:
; W32-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s4 ; W32-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s4
; W32-DAG: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo ; W32-DAG: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo
; W32: [[LOOPBB1:.LBB[0-9]+_[0-9]+]]: ; W32: [[LOOPBB1:.LBB[0-9]+_[0-9]+]]:
; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]]
; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]]
; W32: v_cmp_eq_u64_e32 vcc_lo, s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W32: v_cmp_eq_u64_e32 vcc_lo, s[[[SRSRC0]]:[[SRSRC1]]], v[[[VRSRC0]]:[[VRSRC1]]]
; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W32: v_cmp_eq_u64_e64 [[CMP0:s[0-9]+]], s[[[SRSRC2]]:[[SRSRC3]]], v[[[VRSRC2]]:[[VRSRC3]]]
; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]] ; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]]
; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]] ; W32: s_and_saveexec_b32 [[SAVE:s[0-9]+]], [[AND]]
; W32: buffer_load_format_x [[RES]], [[IDX]], s{{\[}}[[SRSRC0]]:[[SRSRC3]]{{\]}}, 0 idxen ; W32: buffer_load_format_x [[RES]], [[IDX]], s[[[SRSRC0]]:[[SRSRC3]]], 0 idxen
; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]] ; W32: s_xor_b32 exec_lo, exec_lo, [[SAVE]]
; W32: s_cbranch_execnz [[LOOPBB1]] ; W32: s_cbranch_execnz [[LOOPBB1]]
; W32: s_mov_b32 exec_lo, [[SAVEEXEC]] ; W32: s_mov_b32 exec_lo, [[SAVEEXEC]]
; W32: [[TERMBB]]: ; W32: [[TERMBB]]:
; W32: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]], off ; W32: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]], off
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; W64-O0: buffer_load_dword v[[VRSRC1:[0-9]+]], off, s[0:3], s32 offset:32 ; 4-byte Folded Reload ; W64-O0: buffer_load_dword v[[VRSRC1:[0-9]+]], off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC2:[0-9]+]], off, s[0:3], s32 offset:36 ; 4-byte Folded Reload ; W64-O0: buffer_load_dword v[[VRSRC2:[0-9]+]], off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC3:[0-9]+]], off, s[0:3], s32 offset:40 ; 4-byte Folded Reload ; W64-O0: buffer_load_dword v[[VRSRC3:[0-9]+]], off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; W64-O0: s_waitcnt vmcnt(0) ; W64-O0: s_waitcnt vmcnt(0)
; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]] ; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]]
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP1:[0-9]+]], v[[VRSRC1]] ; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP1:[0-9]+]], v[[VRSRC1]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC0:[0-9]+]], s[[S0]] ; W64-O0-DAG: s_mov_b32 s[[SRSRC0:[0-9]+]], s[[S0]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC1:[0-9]+]], s[[SRSRCTMP1]] ; W64-O0-DAG: s_mov_b32 s[[SRSRC1:[0-9]+]], s[[SRSRCTMP1]]
; W64-O0-DAG: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W64-O0-DAG: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s[[[SRSRC0]]:[[SRSRC1]]], v[[[VRSRC0]]:[[VRSRC1]]]
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP2:[0-9]+]], v[[VRSRC2]] ; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP2:[0-9]+]], v[[VRSRC2]]
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP3:[0-9]+]], v[[VRSRC3]] ; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP3:[0-9]+]], v[[VRSRC3]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC2:[0-9]+]], s[[SRSRCTMP2]] ; W64-O0-DAG: s_mov_b32 s[[SRSRC2:[0-9]+]], s[[SRSRCTMP2]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC3:[0-9]+]], s[[SRSRCTMP3]] ; W64-O0-DAG: s_mov_b32 s[[SRSRC3:[0-9]+]], s[[SRSRCTMP3]]
; W64-O0-DAG: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W64-O0-DAG: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s[[[SRSRC2]]:[[SRSRC3]]], v[[[VRSRC2]]:[[VRSRC3]]]
; W64-O0-DAG: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]] ; W64-O0-DAG: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]]
; W64-O0-DAG: s_mov_b32 s[[S1:[0-9]+]], s[[SRSRCTMP1]] ; W64-O0-DAG: s_mov_b32 s[[S1:[0-9]+]], s[[SRSRCTMP1]]
; W64-O0-DAG: s_mov_b32 s[[S2:[0-9]+]], s[[SRSRCTMP2]] ; W64-O0-DAG: s_mov_b32 s[[S2:[0-9]+]], s[[SRSRCTMP2]]
; W64-O0-DAG: s_mov_b32 s[[S3:[0-9]+]], s[[SRSRCTMP3]] ; W64-O0-DAG: s_mov_b32 s[[S3:[0-9]+]], s[[SRSRCTMP3]]
; W64-O0: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]] ; W64-O0: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; W64-O0: buffer_load_format_x [[RES:v[0-9]+]], [[IDX]], s{{\[}}[[S0]]:[[S3]]{{\]}}, {{.*}} idxen ; W64-O0: buffer_load_format_x [[RES:v[0-9]+]], [[IDX]], s[[[S0]]:[[S3]]], {{.*}} idxen
; W64-O0: s_waitcnt vmcnt(0) ; W64-O0: s_waitcnt vmcnt(0)
; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP:[0-9]+]] ; 4-byte Folded Spill ; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP:[0-9]+]] ; 4-byte Folded Spill
; W64-O0: s_xor_b64 exec, exec, [[SAVE]] ; W64-O0: s_xor_b64 exec, exec, [[SAVE]]
; W64-O0-NEXT: s_cbranch_execnz [[LOOPBB0]] ; W64-O0-NEXT: s_cbranch_execnz [[LOOPBB0]]
; XXX-W64-O0: s_mov_b64 exec, [[SAVEEXEC]] ; XXX-W64-O0: s_mov_b64 exec, [[SAVEEXEC]]
; W64-O0: buffer_load_dword [[RES:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP]] ; 4-byte Folded Reload ; W64-O0: buffer_load_dword [[RES:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP]] ; 4-byte Folded Reload
; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF:[0-9]+]] ; 4-byte Folded Spill ; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF:[0-9]+]] ; 4-byte Folded Spill
; W64-O0: s_cbranch_execz [[TERMBB:.LBB[0-9]+_[0-9]+]] ; W64-O0: s_cbranch_execz [[TERMBB:.LBB[0-9]+_[0-9]+]]
; W64-O0: ; %bb.{{[0-9]+}}: ; %bb1 ; W64-O0: ; %bb.{{[0-9]+}}: ; %bb1
; W64-O0-DAG: buffer_store_dword {{v[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s32 offset:[[IDX_OFF:[0-9]+]] ; 4-byte Folded Spill ; W64-O0-DAG: buffer_store_dword {{v[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s32 offset:[[IDX_OFF:[0-9]+]] ; 4-byte Folded Spill
; W64-O0-DAG: s_mov_b64 s{{\[}}[[SAVEEXEC0:[0-9]+]]:[[SAVEEXEC1:[0-9]+]]{{\]}}, exec ; W64-O0-DAG: s_mov_b64 s[[[SAVEEXEC0:[0-9]+]]:[[SAVEEXEC1:[0-9]+]]], exec
; W64-O0: v_writelane_b32 [[VSAVEEXEC:v[0-9]+]], s[[SAVEEXEC0]], [[SAVEEXEC_IDX0:[0-9]+]] ; W64-O0: v_writelane_b32 [[VSAVEEXEC:v[0-9]+]], s[[SAVEEXEC0]], [[SAVEEXEC_IDX0:[0-9]+]]
; W64-O0: v_writelane_b32 [[VSAVEEXEC]], s[[SAVEEXEC1]], [[SAVEEXEC_IDX1:[0-9]+]] ; W64-O0: v_writelane_b32 [[VSAVEEXEC]], s[[SAVEEXEC1]], [[SAVEEXEC_IDX1:[0-9]+]]
; W64-O0: [[LOOPBB1:.LBB[0-9]+_[0-9]+]]: ; =>This Inner Loop Header: Depth=1 ; W64-O0: [[LOOPBB1:.LBB[0-9]+_[0-9]+]]: ; =>This Inner Loop Header: Depth=1
; W64-O0: buffer_load_dword [[IDX:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s32 offset:[[IDX_OFF]] ; 4-byte Folded Reload ; W64-O0: buffer_load_dword [[IDX:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s32 offset:[[IDX_OFF]] ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC0:[0-9]+]], off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; W64-O0: buffer_load_dword v[[VRSRC0:[0-9]+]], off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC1:[0-9]+]], off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; W64-O0: buffer_load_dword v[[VRSRC1:[0-9]+]], off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC2:[0-9]+]], off, s[0:3], s32 offset:12 ; 4-byte Folded Reload ; W64-O0: buffer_load_dword v[[VRSRC2:[0-9]+]], off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC3:[0-9]+]], off, s[0:3], s32 offset:16 ; 4-byte Folded Reload ; W64-O0: buffer_load_dword v[[VRSRC3:[0-9]+]], off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; W64-O0: s_waitcnt vmcnt(0) ; W64-O0: s_waitcnt vmcnt(0)
; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]] ; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]]
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP1:[0-9]+]], v[[VRSRC1]] ; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP1:[0-9]+]], v[[VRSRC1]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC0:[0-9]+]], s[[S0]] ; W64-O0-DAG: s_mov_b32 s[[SRSRC0:[0-9]+]], s[[S0]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC1:[0-9]+]], s[[SRSRCTMP1]] ; W64-O0-DAG: s_mov_b32 s[[SRSRC1:[0-9]+]], s[[SRSRCTMP1]]
; W64-O0-DAG: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}} ; W64-O0-DAG: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s[[[SRSRC0]]:[[SRSRC1]]], v[[[VRSRC0]]:[[VRSRC1]]]
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP2:[0-9]+]], v[[VRSRC2]] ; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP2:[0-9]+]], v[[VRSRC2]]
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP3:[0-9]+]], v[[VRSRC3]] ; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP3:[0-9]+]], v[[VRSRC3]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC2:[0-9]+]], s[[SRSRCTMP2]] ; W64-O0-DAG: s_mov_b32 s[[SRSRC2:[0-9]+]], s[[SRSRCTMP2]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC3:[0-9]+]], s[[SRSRCTMP3]] ; W64-O0-DAG: s_mov_b32 s[[SRSRC3:[0-9]+]], s[[SRSRCTMP3]]
; W64-O0-DAG: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}} ; W64-O0-DAG: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s[[[SRSRC2]]:[[SRSRC3]]], v[[[VRSRC2]]:[[VRSRC3]]]
; W64-O0-DAG: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]] ; W64-O0-DAG: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]]
; W64-O0-DAG: s_mov_b32 s[[S1:[0-9]+]], s[[SRSRCTMP1]] ; W64-O0-DAG: s_mov_b32 s[[S1:[0-9]+]], s[[SRSRCTMP1]]
; W64-O0-DAG: s_mov_b32 s[[S2:[0-9]+]], s[[SRSRCTMP2]] ; W64-O0-DAG: s_mov_b32 s[[S2:[0-9]+]], s[[SRSRCTMP2]]
; W64-O0-DAG: s_mov_b32 s[[S3:[0-9]+]], s[[SRSRCTMP3]] ; W64-O0-DAG: s_mov_b32 s[[S3:[0-9]+]], s[[SRSRCTMP3]]
; W64-O0: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]] ; W64-O0: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; W64-O0: buffer_load_format_x [[RES:v[0-9]+]], [[IDX]], s{{\[}}[[S0]]:[[S3]]{{\]}}, {{.*}} idxen ; W64-O0: buffer_load_format_x [[RES:v[0-9]+]], [[IDX]], s[[[S0]]:[[S3]]], {{.*}} idxen
; W64-O0: s_waitcnt vmcnt(0) ; W64-O0: s_waitcnt vmcnt(0)
; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP:[0-9]+]] ; 4-byte Folded Spill ; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP:[0-9]+]] ; 4-byte Folded Spill
; W64-O0: s_xor_b64 exec, exec, [[SAVE]] ; W64-O0: s_xor_b64 exec, exec, [[SAVE]]
; W64-O0-NEXT: s_cbranch_execnz [[LOOPBB1]] ; W64-O0-NEXT: s_cbranch_execnz [[LOOPBB1]]
; W64-O0: v_readlane_b32 s[[SAVEEXEC0:[0-9]+]], [[VSAVEEXEC]], [[SAVEEXEC_IDX0]] ; W64-O0: v_readlane_b32 s[[SAVEEXEC0:[0-9]+]], [[VSAVEEXEC]], [[SAVEEXEC_IDX0]]
; W64-O0: v_readlane_b32 s[[SAVEEXEC1:[0-9]+]], [[VSAVEEXEC]], [[SAVEEXEC_IDX1]] ; W64-O0: v_readlane_b32 s[[SAVEEXEC1:[0-9]+]], [[VSAVEEXEC]], [[SAVEEXEC_IDX1]]
; W64-O0: s_mov_b64 exec, s{{\[}}[[SAVEEXEC0]]:[[SAVEEXEC1]]{{\]}} ; W64-O0: s_mov_b64 exec, s[[[SAVEEXEC0]]:[[SAVEEXEC1]]]
; W64-O0: buffer_load_dword [[RES:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP]] ; 4-byte Folded Reload ; W64-O0: buffer_load_dword [[RES:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP]] ; 4-byte Folded Reload
; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF]] ; 4-byte Folded Spill ; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF]] ; 4-byte Folded Spill
; W64-O0: [[TERMBB]]: ; W64-O0: [[TERMBB]]:
; W64-O0: buffer_load_dword [[RES:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF]] ; 4-byte Folded Reload ; W64-O0: buffer_load_dword [[RES:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF]] ; 4-byte Folded Reload
; W64-O0: global_store_dword v[{{[0-9]+:[0-9]+}}], [[RES]], off ; W64-O0: global_store_dword v[{{[0-9]+:[0-9]+}}], [[RES]], off
define void @mubuf_vgpr_outside_entry(<4 x i32> %i, <4 x i32> %j, i32 %c, float addrspace(1)* %in, float addrspace(1)* %out) #0 { define void @mubuf_vgpr_outside_entry(<4 x i32> %i, <4 x i32> %j, i32 %c, float addrspace(1)* %in, float addrspace(1)* %out) #0 {
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llvm/test/CodeGen/AMDGPU/not-scalarize-volatile-load.ll

; RUN: llc -mtriple amdgcn--amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple amdgcn--amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: @volatile_load ; GCN-LABEL: @volatile_load
; GCN: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:[[HI_SREG:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0 ; GCN: s_load_dwordx2 s[[[LO_SREG:[0-9]+]]:[[HI_SREG:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x0
; GCN: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]] ; GCN: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]]
; GCN: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]] ; GCN: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]]
; GCN: flat_load_dword v{{[0-9]+}}, v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} ; GCN: flat_load_dword v{{[0-9]+}}, v[[[LO_VREG]]:[[HI_VREG]]]
define amdgpu_kernel void @volatile_load(i32 addrspace(1)* %arg, [8 x i32], i32 addrspace(1)* nocapture %arg1) { define amdgpu_kernel void @volatile_load(i32 addrspace(1)* %arg, [8 x i32], i32 addrspace(1)* nocapture %arg1) {
bb: bb:
%tmp18 = load volatile i32, i32 addrspace(1)* %arg, align 4 %tmp18 = load volatile i32, i32 addrspace(1)* %arg, align 4
%tmp26 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 5 %tmp26 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 5
store i32 %tmp18, i32 addrspace(1)* %tmp26, align 4 store i32 %tmp18, i32 addrspace(1)* %tmp26, align 4
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/operand-folding.ll

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; CHECK-LABEL: {{^}}fold_64bit_constant_add: ; CHECK-LABEL: {{^}}fold_64bit_constant_add:
; CHECK-NOT: s_mov_b64 ; CHECK-NOT: s_mov_b64
; FIXME: It would be better if we could use v_add here and drop the extra ; FIXME: It would be better if we could use v_add here and drop the extra
; v_mov_b32 instructions. ; v_mov_b32 instructions.
; CHECK-DAG: s_add_u32 [[LO:s[0-9]+]], s{{[0-9]+}}, 1 ; CHECK-DAG: s_add_u32 [[LO:s[0-9]+]], s{{[0-9]+}}, 1
; CHECK-DAG: s_addc_u32 [[HI:s[0-9]+]], s{{[0-9]+}}, 0 ; CHECK-DAG: s_addc_u32 [[HI:s[0-9]+]], s{{[0-9]+}}, 0
; CHECK-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], [[LO]] ; CHECK-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], [[LO]]
; CHECK-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[HI]] ; CHECK-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[HI]]
; CHECK: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}}, ; CHECK: buffer_store_dwordx2 v[[[VLO]]:[[VHI]]],
define amdgpu_kernel void @fold_64bit_constant_add(i64 addrspace(1)* %out, i32 %cmp, i64 %val) #1 { define amdgpu_kernel void @fold_64bit_constant_add(i64 addrspace(1)* %out, i32 %cmp, i64 %val) #1 {
entry: entry:
%tmp0 = add i64 %val, 1 %tmp0 = add i64 %val, 1
store i64 %tmp0, i64 addrspace(1)* %out store i64 %tmp0, i64 addrspace(1)* %out
ret void ret void
} }
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%vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3 %vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3
%tmp4 = xor <4 x i32> <i32 100, i32 100, i32 100, i32 100>, %vec3 %tmp4 = xor <4 x i32> <i32 100, i32 100, i32 100, i32 100>, %vec3
store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %out store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %out
ret void ret void
} }
; A subregister use operand should not be tied. ; A subregister use operand should not be tied.
; CHECK-LABEL: {{^}}no_fold_tied_subregister: ; CHECK-LABEL: {{^}}no_fold_tied_subregister:
; CHECK: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} ; CHECK: buffer_load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
; CHECK: v_mac_f32_e32 v[[LO]], 0x41200000, v[[HI]] ; CHECK: v_mac_f32_e32 v[[LO]], 0x41200000, v[[HI]]
; CHECK: buffer_store_dword v[[LO]] ; CHECK: buffer_store_dword v[[LO]]
define amdgpu_kernel void @no_fold_tied_subregister() #1 { define amdgpu_kernel void @no_fold_tied_subregister() #1 {
%tmp1 = load volatile <2 x float>, <2 x float> addrspace(1)* undef %tmp1 = load volatile <2 x float>, <2 x float> addrspace(1)* undef
%tmp2 = extractelement <2 x float> %tmp1, i32 0 %tmp2 = extractelement <2 x float> %tmp1, i32 0
%tmp3 = extractelement <2 x float> %tmp1, i32 1 %tmp3 = extractelement <2 x float> %tmp1, i32 1
%tmp4 = fmul float %tmp3, 10.0 %tmp4 = fmul float %tmp3, 10.0
%tmp5 = fadd float %tmp4, %tmp2 %tmp5 = fadd float %tmp4, %tmp2
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llvm/test/CodeGen/AMDGPU/or.ll

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; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1869f ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1869f
define amdgpu_kernel void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) { define amdgpu_kernel void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) {
%or = or i32 %a, 99999 %or = or i32 %a, 99999
store i32 %or, i32 addrspace(1)* %out, align 4 store i32 %or, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; FUNC-LABEL: {{^}}scalar_or_literal_i64: ; FUNC-LABEL: {{^}}scalar_or_literal_i64:
; SI: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}} ; SI: s_load_dwordx2 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
; SI-DAG: s_or_b32 s[[RES_HI:[0-9]+]], s[[HI]], 0xf237b ; SI-DAG: s_or_b32 s[[RES_HI:[0-9]+]], s[[HI]], 0xf237b
; SI-DAG: s_or_b32 s[[RES_LO:[0-9]+]], s[[LO]], 0x3039 ; SI-DAG: s_or_b32 s[[RES_LO:[0-9]+]], s[[LO]], 0x3039
; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[RES_LO]] ; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[RES_LO]]
; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[RES_HI]] ; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[RES_HI]]
define amdgpu_kernel void @scalar_or_literal_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) { define amdgpu_kernel void @scalar_or_literal_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
%or = or i64 %a, 4261135838621753 %or = or i64 %a, 4261135838621753
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}scalar_or_literal_multi_use_i64: ; FUNC-LABEL: {{^}}scalar_or_literal_multi_use_i64:
; SI: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}} ; SI: s_load_dwordx2 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0xf237b ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0xf237b
; SI-DAG: s_movk_i32 s[[K_LO:[0-9]+]], 0x3039 ; SI-DAG: s_movk_i32 s[[K_LO:[0-9]+]], 0x3039
; SI: s_or_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}} ; SI: s_or_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s[[[K_LO]]:[[K_HI]]]
; SI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, s[[K_LO]] ; SI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, s[[K_LO]]
; SI: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, s[[K_HI]] ; SI: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, s[[K_HI]]
define amdgpu_kernel void @scalar_or_literal_multi_use_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a, [8 x i32], i64 %b) { define amdgpu_kernel void @scalar_or_literal_multi_use_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {
%or = or i64 %a, 4261135838621753 %or = or i64 %a, 4261135838621753
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
%foo = add i64 %b, 4261135838621753 %foo = add i64 %b, 4261135838621753
store volatile i64 %foo, i64 addrspace(1)* undef store volatile i64 %foo, i64 addrspace(1)* undef
ret void ret void
} }
; FUNC-LABEL: {{^}}scalar_or_inline_imm_i64: ; FUNC-LABEL: {{^}}scalar_or_inline_imm_i64:
; SI: s_load_dwordx2 s{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}} ; SI: s_load_dwordx2 s[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
; SI-NOT: or_b32 ; SI-NOT: or_b32
; SI: s_or_b32 s[[VAL_LO]], s[[VAL_LO]], 63 ; SI: s_or_b32 s[[VAL_LO]], s[[VAL_LO]], 63
; SI-NOT: or_b32 ; SI-NOT: or_b32
; SI: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[VAL_LO]] ; SI: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[VAL_LO]]
; SI-NOT: or_b32 ; SI-NOT: or_b32
; SI: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[VAL_HI]] ; SI: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[VAL_HI]]
; SI-NOT: or_b32 ; SI-NOT: or_b32
; SI: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} ; SI: buffer_store_dwordx2 v[[[VLO]]:[[VHI]]]
define amdgpu_kernel void @scalar_or_inline_imm_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) { define amdgpu_kernel void @scalar_or_inline_imm_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
%or = or i64 %a, 63 %or = or i64 %a, 63
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}scalar_or_inline_imm_multi_use_i64: ; FUNC-LABEL: {{^}}scalar_or_inline_imm_multi_use_i64:
; SI-NOT: or_b32 ; SI-NOT: or_b32
; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 63 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 63
; SI-NOT: or_b32 ; SI-NOT: or_b32
define amdgpu_kernel void @scalar_or_inline_imm_multi_use_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { define amdgpu_kernel void @scalar_or_inline_imm_multi_use_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
%or = or i64 %a, 63 %or = or i64 %a, 63
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
%foo = add i64 %b, 63 %foo = add i64 %b, 63
store volatile i64 %foo, i64 addrspace(1)* undef store volatile i64 %foo, i64 addrspace(1)* undef
ret void ret void
} }
; FUNC-LABEL: {{^}}scalar_or_neg_inline_imm_i64: ; FUNC-LABEL: {{^}}scalar_or_neg_inline_imm_i64:
; SI-DAG: s_load_dword [[VAL:s[0-9]+]] ; SI-DAG: s_load_dword [[VAL:s[0-9]+]]
; SI-DAG: s_or_b32 [[VAL]], [[VAL]], -8 ; SI-DAG: s_or_b32 [[VAL]], [[VAL]], -8
; SI-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], -1{{$}} ; SI-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], -1{{$}}
; SI-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[VAL]] ; SI-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[VAL]]
; SI: buffer_store_dwordx2 v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} ; SI: buffer_store_dwordx2 v[[[V_LO]]:[[V_HI]]]
define amdgpu_kernel void @scalar_or_neg_inline_imm_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) { define amdgpu_kernel void @scalar_or_neg_inline_imm_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
%or = or i64 %a, -8 %or = or i64 %a, -8
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}vector_or_literal_i32: ; FUNC-LABEL: {{^}}vector_or_literal_i32:
; SI: v_or_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}} ; SI: v_or_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
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define amdgpu_kernel void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 %b) { define amdgpu_kernel void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 %b) {
%loada = load i64, i64 addrspace(1)* %a %loada = load i64, i64 addrspace(1)* %a
%or = or i64 %loada, %b %or = or i64 %loada, %b
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}vector_or_i64_loadimm: ; FUNC-LABEL: {{^}}vector_or_i64_loadimm:
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xdf77987f, v[[LO_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xdf77987f, v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x146f, v[[HI_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x146f, v[[HI_VREG]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 8 %loada = load i64, i64 addrspace(1)* %a, align 8
%or = or i64 %loada, 22470723082367 %or = or i64 %loada, 22470723082367
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
ret void ret void
} }
; FIXME: The or 0 should really be removed. ; FIXME: The or 0 should really be removed.
; FUNC-LABEL: {{^}}vector_or_i64_imm: ; FUNC-LABEL: {{^}}vector_or_i64_imm:
; SI: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI: v_or_b32_e32 v[[LO_RESULT:[0-9]+]], 8, v[[LO_VREG]] ; SI: v_or_b32_e32 v[[LO_RESULT:[0-9]+]], 8, v[[LO_VREG]]
; SI-NOT: v_or_b32_e32 {{v[0-9]+}}, 0 ; SI-NOT: v_or_b32_e32 {{v[0-9]+}}, 0
; SI: buffer_store_dwordx2 v{{\[}}[[LO_RESULT]]:[[HI_VREG]]{{\]}} ; SI: buffer_store_dwordx2 v[[[LO_RESULT]]:[[HI_VREG]]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @vector_or_i64_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @vector_or_i64_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 8 %loada = load i64, i64 addrspace(1)* %a, align 8
%or = or i64 %loada, 8 %or = or i64 %loada, 8
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}vector_or_i64_neg_inline_imm: ; FUNC-LABEL: {{^}}vector_or_i64_neg_inline_imm:
; SI-DAG: buffer_load_dword v[[LO_VREG:[0-9]+]] ; SI-DAG: buffer_load_dword v[[LO_VREG:[0-9]+]]
; SI-DAG: v_or_b32_e32 v[[RES_LO:[0-9]+]], -8, v[[LO_VREG]] ; SI-DAG: v_or_b32_e32 v[[RES_LO:[0-9]+]], -8, v[[LO_VREG]]
; SI-DAG: v_mov_b32_e32 v[[RES_HI:[0-9]+]], -1{{$}} ; SI-DAG: v_mov_b32_e32 v[[RES_HI:[0-9]+]], -1{{$}}
; SI: buffer_store_dwordx2 v{{\[}}[[RES_LO]]:[[RES_HI]]{{\]}} ; SI: buffer_store_dwordx2 v[[[RES_LO]]:[[RES_HI]]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @vector_or_i64_neg_inline_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @vector_or_i64_neg_inline_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 8 %loada = load i64, i64 addrspace(1)* %a, align 8
%or = or i64 %loada, -8 %or = or i64 %loada, -8
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/packed-fp32.ll

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @fadd_v32_vs(<32 x float> addrspace(1)* %a, <32 x float> %x) {
%add = fadd <32 x float> %load, %x %add = fadd <32 x float> %load, %x
store <32 x float> %add, <32 x float> addrspace(1)* %gep, align 128 store <32 x float> %add, <32 x float> addrspace(1)* %gep, align 128
ret void ret void
} }
; GCN-LABEL: {{^}}fadd_v2_v_imm: ; GCN-LABEL: {{^}}fadd_v2_v_imm:
; GCN: s_mov_b32 s[[K:[0-9]+]], 0x42c80000 ; GCN: s_mov_b32 s[[K:[0-9]+]], 0x42c80000
; GFX900-COUNT-2: v_add_f32_e32 v{{[0-9]+}}, s[[K]], v{{[0-9]+}} ; GFX900-COUNT-2: v_add_f32_e32 v{{[0-9]+}}, s[[K]], v{{[0-9]+}}
; GFX90A: v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s{{\[}}[[K]]:{{[0-9:]+}}] op_sel_hi:[1,0]{{$}} ; GFX90A: v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[[[K]]:{{[0-9:]+}}] op_sel_hi:[1,0]{{$}}
define amdgpu_kernel void @fadd_v2_v_imm(<2 x float> addrspace(1)* %a) { define amdgpu_kernel void @fadd_v2_v_imm(<2 x float> addrspace(1)* %a) {
%id = tail call i32 @llvm.amdgcn.workitem.id.x() %id = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
%load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8 %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
%add = fadd <2 x float> %load, <float 100.0, float 100.0> %add = fadd <2 x float> %load, <float 100.0, float 100.0>
store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8 store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8
ret void ret void
} }
Show All 39 Linesdefine amdgpu_kernel void @fadd_v2_v_lit_hi0(<2 x float> addrspace(1)* %a) {
ret void ret void
} }
; GCN-LABEL: {{^}}fadd_v2_v_lit_lo0: ; GCN-LABEL: {{^}}fadd_v2_v_lit_lo0:
; GFX900-DAG: v_add_f32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} ; GFX900-DAG: v_add_f32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
; GFX900-DAG: v_add_f32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}} ; GFX900-DAG: v_add_f32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}
; GFX90A-DAG: s_mov_b32 s[[LO:[0-9]+]], 0 ; GFX90A-DAG: s_mov_b32 s[[LO:[0-9]+]], 0
; GFX90A-DAG: s_mov_b32 s[[HI:[0-9]+]], 1.0 ; GFX90A-DAG: s_mov_b32 s[[HI:[0-9]+]], 1.0
; GFX90A: v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s{{\[}}[[LO]]:[[HI]]]{{$}} ; GFX90A: v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[[[LO]]:[[HI]]]{{$}}
define amdgpu_kernel void @fadd_v2_v_lit_lo0(<2 x float> addrspace(1)* %a) { define amdgpu_kernel void @fadd_v2_v_lit_lo0(<2 x float> addrspace(1)* %a) {
%id = tail call i32 @llvm.amdgcn.workitem.id.x() %id = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
%load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8 %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
%add = fadd <2 x float> %load, <float 0.0, float 1.0> %add = fadd <2 x float> %load, <float 0.0, float 1.0>
store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8 store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @fmul_v32_vs(<32 x float> addrspace(1)* %a, <32 x float> %x) {
%mul = fmul <32 x float> %load, %x %mul = fmul <32 x float> %load, %x
store <32 x float> %mul, <32 x float> addrspace(1)* %gep, align 128 store <32 x float> %mul, <32 x float> addrspace(1)* %gep, align 128
ret void ret void
} }
; GCN-LABEL: {{^}}fmul_v2_v_imm: ; GCN-LABEL: {{^}}fmul_v2_v_imm:
; GCN: s_mov_b32 s[[K:[0-9]+]], 0x42c80000 ; GCN: s_mov_b32 s[[K:[0-9]+]], 0x42c80000
; GFX900-COUNT-2: v_mul_f32_e32 v{{[0-9]+}}, s[[K]], v{{[0-9]+}} ; GFX900-COUNT-2: v_mul_f32_e32 v{{[0-9]+}}, s[[K]], v{{[0-9]+}}
; GFX90A: v_pk_mul_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s{{\[}}[[K]]:{{[0-9:]+}}] op_sel_hi:[1,0]{{$}} ; GFX90A: v_pk_mul_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[[[K]]:{{[0-9:]+}}] op_sel_hi:[1,0]{{$}}
define amdgpu_kernel void @fmul_v2_v_imm(<2 x float> addrspace(1)* %a) { define amdgpu_kernel void @fmul_v2_v_imm(<2 x float> addrspace(1)* %a) {
%id = tail call i32 @llvm.amdgcn.workitem.id.x() %id = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
%load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8 %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
%mul = fmul <2 x float> %load, <float 100.0, float 100.0> %mul = fmul <2 x float> %load, <float 100.0, float 100.0>
store <2 x float> %mul, <2 x float> addrspace(1)* %gep, align 8 store <2 x float> %mul, <2 x float> addrspace(1)* %gep, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @fma_v32_vs(<32 x float> addrspace(1)* %a, <32 x float> %x) {
store <32 x float> %fma, <32 x float> addrspace(1)* %gep, align 128 store <32 x float> %fma, <32 x float> addrspace(1)* %gep, align 128
ret void ret void
} }
; GCN-LABEL: {{^}}fma_v2_v_imm: ; GCN-LABEL: {{^}}fma_v2_v_imm:
; GCN-DAG: s_mov_b32 s[[K1:[0-9]+]], 0x42c80000 ; GCN-DAG: s_mov_b32 s[[K1:[0-9]+]], 0x42c80000
; GCN-DAG: v_mov_b32_e32 v[[K2:[0-9]+]], 0x43480000 ; GCN-DAG: v_mov_b32_e32 v[[K2:[0-9]+]], 0x43480000
; GFX900-COUNT-2: v_fma_f32 v{{[0-9]+}}, v{{[0-9]+}}, s[[K1]], v[[K2]] ; GFX900-COUNT-2: v_fma_f32 v{{[0-9]+}}, v{{[0-9]+}}, s[[K1]], v[[K2]]
; GFX90A: v_pk_fma_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s{{\[}}[[K1]]:{{[0-9:]+}}], v{{\[}}[[K2]]:{{[0-9:]+}}] op_sel_hi:[1,0,0]{{$}} ; GFX90A: v_pk_fma_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[[[K1]]:{{[0-9:]+}}], v[[[K2]]:{{[0-9:]+}}] op_sel_hi:[1,0,0]{{$}}
define amdgpu_kernel void @fma_v2_v_imm(<2 x float> addrspace(1)* %a) { define amdgpu_kernel void @fma_v2_v_imm(<2 x float> addrspace(1)* %a) {
%id = tail call i32 @llvm.amdgcn.workitem.id.x() %id = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
%load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8 %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
%fma = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %load, <2 x float> <float 100.0, float 100.0>, <2 x float> <float 200.0, float 200.0>) %fma = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %load, <2 x float> <float 100.0, float 100.0>, <2 x float> <float 200.0, float 200.0>)
store <2 x float> %fma, <2 x float> addrspace(1)* %gep, align 8 store <2 x float> %fma, <2 x float> addrspace(1)* %gep, align 8
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPT %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPT %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPT %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPT %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=iceland -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPT %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=iceland -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPT %s
; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPTNONE %s ; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPTNONE %s
; There are no stack objects, but still a private memory access. The ; There are no stack objects, but still a private memory access. The
; private access regiters need to be correctly initialized anyway, and ; private access regiters need to be correctly initialized anyway, and
; shifted down to the end of the used registers. ; shifted down to the end of the used registers.
; GCN-LABEL: {{^}}store_to_undef: ; GCN-LABEL: {{^}}store_to_undef:
; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1] ; OPT-DAG: s_mov_b64 s[[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3] ; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]], s[2:3]
; OPT: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, 0 offen{{$}} ; OPT: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[[[RSRC_LO]]:[[RSRC_HI]]], 0 offen{{$}}
; -O0 should assume spilling, so the input scratch resource descriptor ; -O0 should assume spilling, so the input scratch resource descriptor
; -should be used directly without any copies. ; -should be used directly without any copies.
; OPTNONE-NOT: s_mov_b32 ; OPTNONE-NOT: s_mov_b32
; OPTNONE: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen{{$}} ; OPTNONE: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen{{$}}
define amdgpu_kernel void @store_to_undef() #0 { define amdgpu_kernel void @store_to_undef() #0 {
store volatile i32 0, i32 addrspace(5)* undef store volatile i32 0, i32 addrspace(5)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}store_to_inttoptr: ; GCN-LABEL: {{^}}store_to_inttoptr:
; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1] ; OPT-DAG: s_mov_b64 s[[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3] ; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]], s[2:3]
; OPT: buffer_store_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, 0 offset:124{{$}} ; OPT: buffer_store_dword v{{[0-9]+}}, off, s[[[RSRC_LO]]:[[RSRC_HI]]], 0 offset:124{{$}}
define amdgpu_kernel void @store_to_inttoptr() #0 { define amdgpu_kernel void @store_to_inttoptr() #0 {
store volatile i32 0, i32 addrspace(5)* inttoptr (i32 124 to i32 addrspace(5)*) store volatile i32 0, i32 addrspace(5)* inttoptr (i32 124 to i32 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}load_from_undef: ; GCN-LABEL: {{^}}load_from_undef:
; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1] ; OPT-DAG: s_mov_b64 s[[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3] ; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]], s[2:3]
; OPT: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, 0 offen glc{{$}} ; OPT: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[[[RSRC_LO]]:[[RSRC_HI]]], 0 offen glc{{$}}
define amdgpu_kernel void @load_from_undef() #0 { define amdgpu_kernel void @load_from_undef() #0 {
%ld = load volatile i32, i32 addrspace(5)* undef %ld = load volatile i32, i32 addrspace(5)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_from_inttoptr: ; GCN-LABEL: {{^}}load_from_inttoptr:
; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1] ; OPT-DAG: s_mov_b64 s[[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3] ; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]], s[2:3]
; OPT: buffer_load_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, 0 offset:124 glc{{$}} ; OPT: buffer_load_dword v{{[0-9]+}}, off, s[[[RSRC_LO]]:[[RSRC_HI]]], 0 offset:124 glc{{$}}
define amdgpu_kernel void @load_from_inttoptr() #0 { define amdgpu_kernel void @load_from_inttoptr() #0 {
%ld = load volatile i32, i32 addrspace(5)* inttoptr (i32 124 to i32 addrspace(5)*) %ld = load volatile i32, i32 addrspace(5)* inttoptr (i32 124 to i32 addrspace(5)*)
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/AMDGPU/private-element-size.ll

Show First 20 Lines • Show All 137 Lines • ▼ Show 20 Lines
; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:16{{$}} ; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:16{{$}}
; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:20{{$}} ; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:20{{$}}
; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:24{{$}} ; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:24{{$}}
; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:28{{$}} ; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:28{{$}}
; HSA-ELT4-DAG: buffer_load_dword v[[HI:[0-9]+]], v{{[0-9]+}}, s[0:3], 0 offen offset:4{{$}} ; HSA-ELT4-DAG: buffer_load_dword v[[HI:[0-9]+]], v{{[0-9]+}}, s[0:3], 0 offen offset:4{{$}}
; HSA-ELT4-DAG: buffer_load_dword v[[LO:[0-9]+]], v{{[0-9]+}}, s[0:3], 0 offen{{$}} ; HSA-ELT4-DAG: buffer_load_dword v[[LO:[0-9]+]], v{{[0-9]+}}, s[0:3], 0 offen{{$}}
; HSA-ELT4: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]] ; HSA-ELT4: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @private_elt_size_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 { define amdgpu_kernel void @private_elt_size_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%idxprom = sext i32 %tid to i64 %idxprom = sext i32 %tid to i64
%gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom
%index.load = load i32, i32 addrspace(1)* %gep.index %index.load = load i32, i32 addrspace(1)* %gep.index
%index = and i32 %index.load, 2 %index = and i32 %index.load, 2
%alloca = alloca [2 x i64], align 16, addrspace(5) %alloca = alloca [2 x i64], align 16, addrspace(5)
Show All 20 Lines
; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:16{{$}} ; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:16{{$}}
; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:20{{$}} ; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:20{{$}}
; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:24{{$}} ; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:24{{$}}
; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:28{{$}} ; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:28{{$}}
; HSA-ELT4-DAG: buffer_load_dword v[[HI:[0-9]+]], v{{[0-9]+}}, s[0:3], 0 offen offset:4{{$}} ; HSA-ELT4-DAG: buffer_load_dword v[[HI:[0-9]+]], v{{[0-9]+}}, s[0:3], 0 offen offset:4{{$}}
; HSA-ELT4-DAG: buffer_load_dword v[[LO:[0-9]+]], v{{[0-9]+}}, s[0:3], 0 offen{{$}} ; HSA-ELT4-DAG: buffer_load_dword v[[LO:[0-9]+]], v{{[0-9]+}}, s[0:3], 0 offen{{$}}
; HSA-ELT4: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]] ; HSA-ELT4: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @private_elt_size_f64(double addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 { define amdgpu_kernel void @private_elt_size_f64(double addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%idxprom = sext i32 %tid to i64 %idxprom = sext i32 %tid to i64
%gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom
%index.load = load i32, i32 addrspace(1)* %gep.index %index.load = load i32, i32 addrspace(1)* %gep.index
%index = and i32 %index.load, 2 %index = and i32 %index.load, 2
%alloca = alloca [2 x double], align 16, addrspace(5) %alloca = alloca [2 x double], align 16, addrspace(5)
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llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
} }
; GCN-LABEL: {{^}}half4_alloca_store4: ; GCN-LABEL: {{^}}half4_alloca_store4:
; OPT-LABEL: define amdgpu_kernel void @half4_alloca_store4 ; OPT-LABEL: define amdgpu_kernel void @half4_alloca_store4
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x44004200 ; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x44004200
; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x40003c00 ; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x40003c00
; GCN: v_lshrrev_b64 v[{{[0-9:]+}}], v{{[0-9]+}}, s{{\[}}[[SL]]:[[SH]]] ; GCN: v_lshrrev_b64 v[{{[0-9:]+}}], v{{[0-9]+}}, s[[[SL]]:[[SH]]]
; OPT: %gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(5)* %alloca, i32 0, i32 %sel2 ; OPT: %gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(5)* %alloca, i32 0, i32 %sel2
; OPT: store <4 x half> <half 0xH3C00, half 0xH4000, half 0xH4200, half 0xH4400>, <4 x half> addrspace(5)* %alloca, align 2 ; OPT: store <4 x half> <half 0xH3C00, half 0xH4000, half 0xH4200, half 0xH4400>, <4 x half> addrspace(5)* %alloca, align 2
; OPT: %0 = load <4 x half>, <4 x half> addrspace(5)* %alloca ; OPT: %0 = load <4 x half>, <4 x half> addrspace(5)* %alloca
; OPT: %1 = extractelement <4 x half> %0, i32 %sel2 ; OPT: %1 = extractelement <4 x half> %0, i32 %sel2
; OPT: store half %1, half addrspace(1)* %out, align 2 ; OPT: store half %1, half addrspace(1)* %out, align 2
define amdgpu_kernel void @half4_alloca_store4(half addrspace(1)* %out, half addrspace(3)* %dummy_lds) { define amdgpu_kernel void @half4_alloca_store4(half addrspace(1)* %out, half addrspace(3)* %dummy_lds) {
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} }
; GCN-LABEL: {{^}}short4_alloca_store4: ; GCN-LABEL: {{^}}short4_alloca_store4:
; OPT-LABEL: define amdgpu_kernel void @short4_alloca_store4 ; OPT-LABEL: define amdgpu_kernel void @short4_alloca_store4
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x40003 ; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x40003
; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x20001 ; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x20001
; GCN: v_lshrrev_b64 v[{{[0-9:]+}}], v{{[0-9]+}}, s{{\[}}[[SL]]:[[SH]]] ; GCN: v_lshrrev_b64 v[{{[0-9:]+}}], v{{[0-9]+}}, s[[[SL]]:[[SH]]]
; OPT: %gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(5)* %alloca, i32 0, i32 %sel2 ; OPT: %gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(5)* %alloca, i32 0, i32 %sel2
; OPT: store <4 x i16> <i16 1, i16 2, i16 3, i16 4>, <4 x i16> addrspace(5)* %alloca, align 2 ; OPT: store <4 x i16> <i16 1, i16 2, i16 3, i16 4>, <4 x i16> addrspace(5)* %alloca, align 2
; OPT: %0 = load <4 x i16>, <4 x i16> addrspace(5)* %alloca ; OPT: %0 = load <4 x i16>, <4 x i16> addrspace(5)* %alloca
; OPT: %1 = extractelement <4 x i16> %0, i32 %sel2 ; OPT: %1 = extractelement <4 x i16> %0, i32 %sel2
; OPT: store i16 %1, i16 addrspace(1)* %out, align 2 ; OPT: store i16 %1, i16 addrspace(1)* %out, align 2
define amdgpu_kernel void @short4_alloca_store4(i16 addrspace(1)* %out, i16 addrspace(3)* %dummy_lds) { define amdgpu_kernel void @short4_alloca_store4(i16 addrspace(1)* %out, i16 addrspace(3)* %dummy_lds) {
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llvm/test/CodeGen/AMDGPU/read_register.ll

Show All 11 Linesdefine amdgpu_kernel void @test_read_m0(i32 addrspace(1)* %out) #0 {
%m0 = call i32 @llvm.read_register.i32(metadata !0) %m0 = call i32 @llvm.read_register.i32(metadata !0)
store i32 %m0, i32 addrspace(1)* %out store i32 %m0, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: {{^}}test_read_exec: ; CHECK-LABEL: {{^}}test_read_exec:
; CHECK: v_mov_b32_e32 v[[LO:[0-9]+]], exec_lo ; CHECK: v_mov_b32_e32 v[[LO:[0-9]+]], exec_lo
; CHECK: v_mov_b32_e32 v[[HI:[0-9]+]], exec_hi ; CHECK: v_mov_b32_e32 v[[HI:[0-9]+]], exec_hi
; CHECK: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; CHECK: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_read_exec(i64 addrspace(1)* %out) #0 { define amdgpu_kernel void @test_read_exec(i64 addrspace(1)* %out) #0 {
%exec = call i64 @llvm.read_register.i64(metadata !1) %exec = call i64 @llvm.read_register.i64(metadata !1)
store i64 %exec, i64 addrspace(1)* %out store i64 %exec, i64 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: {{^}}test_read_flat_scratch: ; CHECK-LABEL: {{^}}test_read_flat_scratch:
; CHECK: v_mov_b32_e32 v[[LO:[0-9]+]], flat_scratch_lo ; CHECK: v_mov_b32_e32 v[[LO:[0-9]+]], flat_scratch_lo
; CHECK: v_mov_b32_e32 v[[HI:[0-9]+]], flat_scratch_hi ; CHECK: v_mov_b32_e32 v[[HI:[0-9]+]], flat_scratch_hi
; CHECK: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; CHECK: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @test_read_flat_scratch(i64 addrspace(1)* %out) #0 { define amdgpu_kernel void @test_read_flat_scratch(i64 addrspace(1)* %out) #0 {
%flat_scratch = call i64 @llvm.read_register.i64(metadata !2) %flat_scratch = call i64 @llvm.read_register.i64(metadata !2)
store i64 %flat_scratch, i64 addrspace(1)* %out store i64 %flat_scratch, i64 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: {{^}}test_read_flat_scratch_lo: ; CHECK-LABEL: {{^}}test_read_flat_scratch_lo:
; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], flat_scratch_lo ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], flat_scratch_lo
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llvm/test/CodeGen/AMDGPU/readcyclecounter.ll

Show All 13 Lines
; MEMTIME: s_memtime s{{\[[0-9]+:[0-9]+\]}} ; MEMTIME: s_memtime s{{\[[0-9]+:[0-9]+\]}}
; MEMTIME: store_dwordx2 ; MEMTIME: store_dwordx2
; GETREG-GISEL-DAG: s_mov_b32 s[[SZERO:[0-9]+]], 0 ; GETREG-GISEL-DAG: s_mov_b32 s[[SZERO:[0-9]+]], 0
; GETREG-GISEL-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], s[[SZERO]] ; GETREG-GISEL-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], s[[SZERO]]
; GETREG-SDAG-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0 ; GETREG-SDAG-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0
; GETREG-DAG: s_getreg_b32 [[CNT1:s[0-9]+]], hwreg(HW_REG_SHADER_CYCLES, 0, 20) ; GETREG-DAG: s_getreg_b32 [[CNT1:s[0-9]+]], hwreg(HW_REG_SHADER_CYCLES, 0, 20)
; GETREG-DAG: v_mov_b32_e32 v[[VCNT1:[0-9]+]], [[CNT1]] ; GETREG-DAG: v_mov_b32_e32 v[[VCNT1:[0-9]+]], [[CNT1]]
; GETREG: global_store_dwordx2 v{{.+}}, v{{\[}}[[VCNT1]]:[[ZERO]]] ; GETREG: global_store_dwordx2 v{{.+}}, v[[[VCNT1]]:[[ZERO]]]
; GETREG: s_getreg_b32 [[CNT2:s[0-9]+]], hwreg(HW_REG_SHADER_CYCLES, 0, 20) ; GETREG: s_getreg_b32 [[CNT2:s[0-9]+]], hwreg(HW_REG_SHADER_CYCLES, 0, 20)
; GETREG: v_mov_b32_e32 v[[VCNT2:[0-9]+]], [[CNT2]] ; GETREG: v_mov_b32_e32 v[[VCNT2:[0-9]+]], [[CNT2]]
; GETREG: global_store_dwordx2 v{{.+}}, v{{\[}}[[VCNT2]]:[[ZERO]]] ; GETREG: global_store_dwordx2 v{{.+}}, v[[[VCNT2]]:[[ZERO]]]
define amdgpu_kernel void @test_readcyclecounter(i64 addrspace(1)* %out) #0 { define amdgpu_kernel void @test_readcyclecounter(i64 addrspace(1)* %out) #0 {
%cycle0 = call i64 @llvm.readcyclecounter() %cycle0 = call i64 @llvm.readcyclecounter()
store volatile i64 %cycle0, i64 addrspace(1)* %out store volatile i64 %cycle0, i64 addrspace(1)* %out
%cycle1 = call i64 @llvm.readcyclecounter() %cycle1 = call i64 @llvm.readcyclecounter()
store volatile i64 %cycle1, i64 addrspace(1)* %out store volatile i64 %cycle1, i64 addrspace(1)* %out
ret void ret void
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llvm/test/CodeGen/AMDGPU/rel32.ll

; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s
@g = protected local_unnamed_addr addrspace(4) externally_initialized global i32 0, align 4 @g = protected local_unnamed_addr addrspace(4) externally_initialized global i32 0, align 4
; CHECK-LABEL: rel32_neg_offset: ; CHECK-LABEL: rel32_neg_offset:
; CHECK: s_getpc_b64 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{]}} ; CHECK: s_getpc_b64 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]{{]}}
; CHECK-NEXT: s_add_u32 s[[LO]], s[[LO]], g@rel32@lo-4 ; CHECK-NEXT: s_add_u32 s[[LO]], s[[LO]], g@rel32@lo-4
; CHECK-NEXT: s_addc_u32 s[[HI]], s[[HI]], g@rel32@hi+4 ; CHECK-NEXT: s_addc_u32 s[[HI]], s[[HI]], g@rel32@hi+4
define i32 addrspace(4)* @rel32_neg_offset() { define i32 addrspace(4)* @rel32_neg_offset() {
%r = getelementptr i32, i32 addrspace(4)* @g, i64 -2 %r = getelementptr i32, i32 addrspace(4)* @g, i64 -2
ret i32 addrspace(4)* %r ret i32 addrspace(4)* %r
} }

llvm/test/CodeGen/AMDGPU/returnaddress.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Linesentry:
unreachable unreachable
} }
declare void @callee() declare void @callee()
; GCN-LABEL: {{^}}multi_use: ; GCN-LABEL: {{^}}multi_use:
; GCN-DAG: v_mov_b32_e32 v[[LO:4[0-9]+]], s30 ; GCN-DAG: v_mov_b32_e32 v[[LO:4[0-9]+]], s30
; GCN-DAG: v_mov_b32_e32 v[[HI:4[0-9]+]], s31 ; GCN-DAG: v_mov_b32_e32 v[[HI:4[0-9]+]], s31
; GCN: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
define void @multi_use() nounwind { define void @multi_use() nounwind {
entry: entry:
%ret0 = tail call i8* @llvm.returnaddress(i32 0) %ret0 = tail call i8* @llvm.returnaddress(i32 0)
store volatile i8* %ret0, i8* addrspace(1)* undef store volatile i8* %ret0, i8* addrspace(1)* undef
call void @callee() call void @callee()
%ret1 = tail call i8* @llvm.returnaddress(i32 0) %ret1 = tail call i8* @llvm.returnaddress(i32 0)
store volatile i8* %ret1, i8* addrspace(1)* undef store volatile i8* %ret1, i8* addrspace(1)* undef
ret void ret void
} }
declare i8* @llvm.returnaddress(i32) nounwind readnone declare i8* @llvm.returnaddress(i32) nounwind readnone

llvm/test/CodeGen/AMDGPU/s_movk_i32.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; SI-LABEL: {{^}}s_movk_i32_k0: ; SI-LABEL: {{^}}s_movk_i32_k0:
; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xffff{{$}} ; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xffff{{$}}
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 1, v[[HI_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 1, v[[HI_VREG]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k0(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @s_movk_i32_k0(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4 %loada = load i64, i64 addrspace(1)* %a, align 4
%or = or i64 %loada, 4295032831 ; ((1 << 16) - 1) | (1 << 32) %or = or i64 %loada, 4295032831 ; ((1 << 16) - 1) | (1 << 32)
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
call void asm sideeffect "; use $0", "s"(i64 4295032831) call void asm sideeffect "; use $0", "s"(i64 4295032831)
ret void ret void
} }
; SI-LABEL: {{^}}s_movk_i32_k1: ; SI-LABEL: {{^}}s_movk_i32_k1:
; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x7fff{{$}} ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x7fff{{$}}
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 1, v[[HI_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 1, v[[HI_VREG]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k1(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @s_movk_i32_k1(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4 %loada = load i64, i64 addrspace(1)* %a, align 4
%or = or i64 %loada, 4295000063 ; ((1 << 15) - 1) | (1 << 32) %or = or i64 %loada, 4295000063 ; ((1 << 15) - 1) | (1 << 32)
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
call void asm sideeffect "; use $0", "s"(i64 4295000063) call void asm sideeffect "; use $0", "s"(i64 4295000063)
ret void ret void
} }
; SI-LABEL: {{^}}s_movk_i32_k2: ; SI-LABEL: {{^}}s_movk_i32_k2:
; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x7fff{{$}} ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x7fff{{$}}
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 64, v[[HI_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 64, v[[HI_VREG]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k2(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @s_movk_i32_k2(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4 %loada = load i64, i64 addrspace(1)* %a, align 4
%or = or i64 %loada, 274877939711 ; ((1 << 15) - 1) | (64 << 32) %or = or i64 %loada, 274877939711 ; ((1 << 15) - 1) | (64 << 32)
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
call void asm sideeffect "; use $0", "s"(i64 274877939711) call void asm sideeffect "; use $0", "s"(i64 274877939711)
ret void ret void
} }
; SI-LABEL: {{^}}s_movk_i32_k3: ; SI-LABEL: {{^}}s_movk_i32_k3:
; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0x8000{{$}} ; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0x8000{{$}}
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 1, v[[HI_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 1, v[[HI_VREG]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k3(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @s_movk_i32_k3(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4 %loada = load i64, i64 addrspace(1)* %a, align 4
%or = or i64 %loada, 4295000064 ; (1 << 15) | (1 << 32) %or = or i64 %loada, 4295000064 ; (1 << 15) | (1 << 32)
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
call void asm sideeffect "; use $0", "s"(i64 4295000064) call void asm sideeffect "; use $0", "s"(i64 4295000064)
ret void ret void
} }
; SI-LABEL: {{^}}s_movk_i32_k4: ; SI-LABEL: {{^}}s_movk_i32_k4:
; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0x20000{{$}} ; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0x20000{{$}}
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 1, v[[HI_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 1, v[[HI_VREG]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k4(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @s_movk_i32_k4(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4 %loada = load i64, i64 addrspace(1)* %a, align 4
%or = or i64 %loada, 4295098368 ; (1 << 17) | (1 << 32) %or = or i64 %loada, 4295098368 ; (1 << 17) | (1 << 32)
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
call void asm sideeffect "; use $0", "s"(i64 4295098368) call void asm sideeffect "; use $0", "s"(i64 4295098368)
ret void ret void
} }
; SI-LABEL: {{^}}s_movk_i32_k5: ; SI-LABEL: {{^}}s_movk_i32_k5:
; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0xffef{{$}} ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0xffef{{$}}
; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0xff00ffff{{$}} ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0xff00ffff{{$}}
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k5(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @s_movk_i32_k5(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4 %loada = load i64, i64 addrspace(1)* %a, align 4
%or = or i64 %loada, 18374967954648334319 ; -17 & 0xff00ffffffffffff %or = or i64 %loada, 18374967954648334319 ; -17 & 0xff00ffffffffffff
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
call void asm sideeffect "; use $0", "s"(i64 18374967954648334319) call void asm sideeffect "; use $0", "s"(i64 18374967954648334319)
ret void ret void
} }
; SI-LABEL: {{^}}s_movk_i32_k6: ; SI-LABEL: {{^}}s_movk_i32_k6:
; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x41{{$}} ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x41{{$}}
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 63, v[[HI_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 63, v[[HI_VREG]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k6(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @s_movk_i32_k6(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4 %loada = load i64, i64 addrspace(1)* %a, align 4
%or = or i64 %loada, 270582939713 ; 65 | (63 << 32) %or = or i64 %loada, 270582939713 ; 65 | (63 << 32)
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
call void asm sideeffect "; use $0", "s"(i64 270582939713) call void asm sideeffect "; use $0", "s"(i64 270582939713)
ret void ret void
} }
; SI-LABEL: {{^}}s_movk_i32_k7: ; SI-LABEL: {{^}}s_movk_i32_k7:
; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x2000{{$}} ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x2000{{$}}
; SI-DAG: s_movk_i32 [[HI_S_IMM:s[0-9]+]], 0x4000{{$}} ; SI-DAG: s_movk_i32 [[HI_S_IMM:s[0-9]+]], 0x4000{{$}}
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k7(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @s_movk_i32_k7(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4 %loada = load i64, i64 addrspace(1)* %a, align 4
%or = or i64 %loada, 70368744185856; ((1 << 13)) | ((1 << 14) << 32) %or = or i64 %loada, 70368744185856; ((1 << 13)) | ((1 << 14) << 32)
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
call void asm sideeffect "; use $0", "s"(i64 70368744185856) call void asm sideeffect "; use $0", "s"(i64 70368744185856)
ret void ret void
} }
; SI-LABEL: {{^}}s_movk_i32_k8: ; SI-LABEL: {{^}}s_movk_i32_k8:
; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x8000{{$}} ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x8000{{$}}
; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}} ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k8(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @s_movk_i32_k8(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4 %loada = load i64, i64 addrspace(1)* %a, align 4
%or = or i64 %loada, 1229782942255906816 ; 0x11111111ffff8000 %or = or i64 %loada, 1229782942255906816 ; 0x11111111ffff8000
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
call void asm sideeffect "; use $0", "s"(i64 1229782942255906816) call void asm sideeffect "; use $0", "s"(i64 1229782942255906816)
ret void ret void
} }
; SI-LABEL: {{^}}s_movk_i32_k9: ; SI-LABEL: {{^}}s_movk_i32_k9:
; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x8001{{$}} ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x8001{{$}}
; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}} ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k9(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @s_movk_i32_k9(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4 %loada = load i64, i64 addrspace(1)* %a, align 4
%or = or i64 %loada, 1229782942255906817 ; 0x11111111ffff8001 %or = or i64 %loada, 1229782942255906817 ; 0x11111111ffff8001
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
call void asm sideeffect "; use $0", "s"(i64 1229782942255906817) call void asm sideeffect "; use $0", "s"(i64 1229782942255906817)
ret void ret void
} }
; SI-LABEL: {{^}}s_movk_i32_k10: ; SI-LABEL: {{^}}s_movk_i32_k10:
; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x8888{{$}} ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x8888{{$}}
; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}} ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k10(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @s_movk_i32_k10(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4 %loada = load i64, i64 addrspace(1)* %a, align 4
%or = or i64 %loada, 1229782942255909000 ; 0x11111111ffff8888 %or = or i64 %loada, 1229782942255909000 ; 0x11111111ffff8888
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
call void asm sideeffect "; use $0", "s"(i64 1229782942255909000) call void asm sideeffect "; use $0", "s"(i64 1229782942255909000)
ret void ret void
} }
; SI-LABEL: {{^}}s_movk_i32_k11: ; SI-LABEL: {{^}}s_movk_i32_k11:
; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x8fff{{$}} ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x8fff{{$}}
; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}} ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k11(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @s_movk_i32_k11(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4 %loada = load i64, i64 addrspace(1)* %a, align 4
%or = or i64 %loada, 1229782942255910911 ; 0x11111111ffff8fff %or = or i64 %loada, 1229782942255910911 ; 0x11111111ffff8fff
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
call void asm sideeffect "; use $0", "s"(i64 1229782942255910911) call void asm sideeffect "; use $0", "s"(i64 1229782942255910911)
ret void ret void
} }
; SI-LABEL: {{^}}s_movk_i32_k12: ; SI-LABEL: {{^}}s_movk_i32_k12:
; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xffff7001{{$}} ; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xffff7001{{$}}
; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}} ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]] ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @s_movk_i32_k12(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @s_movk_i32_k12(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 4 %loada = load i64, i64 addrspace(1)* %a, align 4
%or = or i64 %loada, 1229782942255902721 ; 0x11111111ffff7001 %or = or i64 %loada, 1229782942255902721 ; 0x11111111ffff7001
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
call void asm sideeffect "; use $0", "s"(i64 1229782942255902721) call void asm sideeffect "; use $0", "s"(i64 1229782942255902721)
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/salu-to-valu.ll

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; Test moving an SMRD instruction to the VALU ; Test moving an SMRD instruction to the VALU
; FIXME: movs can be moved before nop to reduce count ; FIXME: movs can be moved before nop to reduce count
; GCN-LABEL: {{^}}smrd_valu: ; GCN-LABEL: {{^}}smrd_valu:
; SI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x2ee0 ; SI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x2ee0
; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}} ; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}} ; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
; SI-DAG: s_mov_b32 ; SI-DAG: s_mov_b32
; SI-DAG: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, [[OFFSET]] ; SI-DAG: s_load_dword [[OUT:s[0-9]+]], s[[[PTR_LO]]:[[PTR_HI]]], [[OFFSET]]
; CI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xbb8 ; CI: s_load_dword [[OUT:s[0-9]+]], s[[[PTR_LO]]:[[PTR_HI]]], 0xbb8
; GCN: v_mov_b32_e32 [[V_OUT:v[0-9]+]], [[OUT]] ; GCN: v_mov_b32_e32 [[V_OUT:v[0-9]+]], [[OUT]]
; GCN-NOHSA: buffer_store_dword [[V_OUT]] ; GCN-NOHSA: buffer_store_dword [[V_OUT]]
; GCN-HSA: flat_store_dword {{.*}}, [[V_OUT]] ; GCN-HSA: flat_store_dword {{.*}}, [[V_OUT]]
define amdgpu_kernel void @smrd_valu(i32 addrspace(4)* addrspace(1)* %in, i32 %a, i32 %b, i32 addrspace(1)* %out) #1 { define amdgpu_kernel void @smrd_valu(i32 addrspace(4)* addrspace(1)* %in, i32 %a, i32 %b, i32 addrspace(1)* %out) #1 {
entry: entry:
%tmp = icmp ne i32 %a, 0 %tmp = icmp ne i32 %a, 0
br i1 %tmp, label %if, label %else br i1 %tmp, label %if, label %else
▲ Show 20 Lines • Show All 441 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/select-opt.ll

Show All 40 Lines
; GCN-LABEL: {{^}}opt_select_i64_and_cmp_i32: ; GCN-LABEL: {{^}}opt_select_i64_and_cmp_i32:
; GCN-DAG: s_cmp_lg_u32 ; GCN-DAG: s_cmp_lg_u32
; GCN: s_cselect_b64 [[CMP1:s\[[0-9]+:[0-9]+\]]], -1, 0 ; GCN: s_cselect_b64 [[CMP1:s\[[0-9]+:[0-9]+\]]], -1, 0
; GCN-DAG: s_cmp_lg_u32 ; GCN-DAG: s_cmp_lg_u32
; GCN: s_cselect_b64 [[CMP2:s\[[0-9]+:[0-9]+\]]], -1, 0 ; GCN: s_cselect_b64 [[CMP2:s\[[0-9]+:[0-9]+\]]], -1, 0
; GCN: s_and_b64 vcc, [[CMP1]], [[CMP2]] ; GCN: s_and_b64 vcc, [[CMP1]], [[CMP2]]
; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc ; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc ; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT0]]:[[RESULT1]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[RESULT0]]:[[RESULT1]]]
define amdgpu_kernel void @opt_select_i64_and_cmp_i32(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i64 %x, i64 %y) #0 { define amdgpu_kernel void @opt_select_i64_and_cmp_i32(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i64 %x, i64 %y) #0 {
%icmp0 = icmp ne i32 %a, %b %icmp0 = icmp ne i32 %a, %b
%icmp1 = icmp ne i32 %a, %c %icmp1 = icmp ne i32 %a, %c
%and = and i1 %icmp0, %icmp1 %and = and i1 %icmp0, %icmp1
%select = select i1 %and, i64 %x, i64 %y %select = select i1 %and, i64 %x, i64 %y
store i64 %select, i64 addrspace(1)* %out store i64 %select, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}opt_select_i64_and_cmp_f32: ; GCN-LABEL: {{^}}opt_select_i64_and_cmp_f32:
; GCN-DAG: v_cmp_lg_f32_e32 vcc, ; GCN-DAG: v_cmp_lg_f32_e32 vcc,
; GCN-DAG: v_cmp_lg_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]] ; GCN-DAG: v_cmp_lg_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
; GCN: s_and_b64 vcc, vcc, [[CMP1]] ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc ; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc ; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT0]]:[[RESULT1]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[RESULT0]]:[[RESULT1]]]
define amdgpu_kernel void @opt_select_i64_and_cmp_f32(i64 addrspace(1)* %out, float %a, float %b, float %c, i64 %x, i64 %y) #0 { define amdgpu_kernel void @opt_select_i64_and_cmp_f32(i64 addrspace(1)* %out, float %a, float %b, float %c, i64 %x, i64 %y) #0 {
%fcmp0 = fcmp one float %a, %b %fcmp0 = fcmp one float %a, %b
%fcmp1 = fcmp one float %a, %c %fcmp1 = fcmp one float %a, %c
%and = and i1 %fcmp0, %fcmp1 %and = and i1 %fcmp0, %fcmp1
%select = select i1 %and, i64 %x, i64 %y %select = select i1 %and, i64 %x, i64 %y
store i64 %select, i64 addrspace(1)* %out store i64 %select, i64 addrspace(1)* %out
ret void ret void
} }
Show All 36 Lines
; GCN-LABEL: {{^}}opt_select_i64_or_cmp_i32: ; GCN-LABEL: {{^}}opt_select_i64_or_cmp_i32:
; GCN-DAG: s_cmp_lg_u32 ; GCN-DAG: s_cmp_lg_u32
; GCN: s_cselect_b64 [[CMP1:s\[[0-9]+:[0-9]+\]]], -1, 0 ; GCN: s_cselect_b64 [[CMP1:s\[[0-9]+:[0-9]+\]]], -1, 0
; GCN-DAG: s_cmp_lg_u32 ; GCN-DAG: s_cmp_lg_u32
; GCN: s_cselect_b64 [[CMP2:s\[[0-9]+:[0-9]+\]]], -1, 0 ; GCN: s_cselect_b64 [[CMP2:s\[[0-9]+:[0-9]+\]]], -1, 0
; GCN: s_or_b64 vcc, [[CMP1]], [[CMP2]] ; GCN: s_or_b64 vcc, [[CMP1]], [[CMP2]]
; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc ; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc ; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT0]]:[[RESULT1]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[RESULT0]]:[[RESULT1]]]
define amdgpu_kernel void @opt_select_i64_or_cmp_i32(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i64 %x, i64 %y) #0 { define amdgpu_kernel void @opt_select_i64_or_cmp_i32(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i64 %x, i64 %y) #0 {
%icmp0 = icmp ne i32 %a, %b %icmp0 = icmp ne i32 %a, %b
%icmp1 = icmp ne i32 %a, %c %icmp1 = icmp ne i32 %a, %c
%or = or i1 %icmp0, %icmp1 %or = or i1 %icmp0, %icmp1
%select = select i1 %or, i64 %x, i64 %y %select = select i1 %or, i64 %x, i64 %y
store i64 %select, i64 addrspace(1)* %out store i64 %select, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}opt_select_i64_or_cmp_f32: ; GCN-LABEL: {{^}}opt_select_i64_or_cmp_f32:
; GCN-DAG: v_cmp_lg_f32_e32 vcc, ; GCN-DAG: v_cmp_lg_f32_e32 vcc,
; GCN-DAG: v_cmp_lg_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]] ; GCN-DAG: v_cmp_lg_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
; GCN: s_or_b64 vcc, vcc, [[CMP1]] ; GCN: s_or_b64 vcc, vcc, [[CMP1]]
; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc ; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc ; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT0]]:[[RESULT1]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[RESULT0]]:[[RESULT1]]]
define amdgpu_kernel void @opt_select_i64_or_cmp_f32(i64 addrspace(1)* %out, float %a, float %b, float %c, i64 %x, i64 %y) #0 { define amdgpu_kernel void @opt_select_i64_or_cmp_f32(i64 addrspace(1)* %out, float %a, float %b, float %c, i64 %x, i64 %y) #0 {
%fcmp0 = fcmp one float %a, %b %fcmp0 = fcmp one float %a, %b
%fcmp1 = fcmp one float %a, %c %fcmp1 = fcmp one float %a, %c
%or = or i1 %fcmp0, %fcmp1 %or = or i1 %fcmp0, %fcmp1
%select = select i1 %or, i64 %x, i64 %y %select = select i1 %or, i64 %x, i64 %y
store i64 %select, i64 addrspace(1)* %out store i64 %select, i64 addrspace(1)* %out
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/select-vectors.ll

Show First 20 Lines • Show All 210 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @select_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b, i32 %c) #0 { define amdgpu_kernel void @select_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b, i32 %c) #0 {
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, <8 x i32> %a, <8 x i32> %b %select = select i1 %cmp, <8 x i32> %a, <8 x i32> %b
store <8 x i32> %select, <8 x i32> addrspace(1)* %out, align 16 store <8 x i32> %select, <8 x i32> addrspace(1)* %out, align 16
ret void ret void
} }
; GCN-LABEL: {{^}}s_select_v2f32: ; GCN-LABEL: {{^}}s_select_v2f32:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[ALO:[0-9]+]]:[[AHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} ; GCN-DAG: s_load_dwordx2 s[[[ALO:[0-9]+]]:[[AHI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
; GCN-DAG: s_load_dwordx2 s{{\[}}[[BLO:[0-9]+]]:[[BHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xd|0x34}} ; GCN-DAG: s_load_dwordx2 s[[[BLO:[0-9]+]]:[[BHI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0xd|0x34}}
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[AHI]] ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[AHI]]
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BHI]] ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BHI]]
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[ALO]] ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[ALO]]
; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}} ; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}}
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BLO]] ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BLO]]
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llvm/test/CodeGen/AMDGPU/sext-in-reg.ll

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @sext_in_reg_i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i32> %a, <1 x i32> %b) #0 {
%shl = shl <1 x i32> %c, <i32 24> %shl = shl <1 x i32> %c, <i32 24>
%ashr = ashr <1 x i32> %shl, <i32 24> %ashr = ashr <1 x i32> %shl, <i32 24>
store <1 x i32> %ashr, <1 x i32> addrspace(1)* %out, align 4 store <1 x i32> %ashr, <1 x i32> addrspace(1)* %out, align 4
ret void ret void
} }
; FUNC-LABEL: {{^}}sext_in_reg_i1_to_i64: ; FUNC-LABEL: {{^}}sext_in_reg_i1_to_i64:
; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]] ; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]]
; GCN-DAG: s_bfe_i64 s{{\[}}[[SLO:[0-9]+]]:[[SHI:[0-9]+]]{{\]}}, [[VAL]], 0x10000 ; GCN-DAG: s_bfe_i64 s[[[SLO:[0-9]+]]:[[SHI:[0-9]+]]], [[VAL]], 0x10000
; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]] ; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]]
; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] ; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]]
; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[VLO]]:[[VHI]]]
define amdgpu_kernel void @sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 { define amdgpu_kernel void @sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 {
%c = shl i64 %a, %b %c = shl i64 %a, %b
%shl = shl i64 %c, 63 %shl = shl i64 %c, 63
%ashr = ashr i64 %shl, 63 %ashr = ashr i64 %shl, 63
store i64 %ashr, i64 addrspace(1)* %out, align 8 store i64 %ashr, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i64: ; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i64:
; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]] ; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]]
; GCN-DAG: s_bfe_i64 s{{\[}}[[SLO:[0-9]+]]:[[SHI:[0-9]+]]{{\]}}, [[VAL]], 0x80000 ; GCN-DAG: s_bfe_i64 s[[[SLO:[0-9]+]]:[[SHI:[0-9]+]]], [[VAL]], 0x80000
; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]] ; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]]
; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] ; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]]
; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[VLO]]:[[VHI]]]
define amdgpu_kernel void @sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 { define amdgpu_kernel void @sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 {
%c = shl i64 %a, %b %c = shl i64 %a, %b
%shl = shl i64 %c, 56 %shl = shl i64 %c, 56
%ashr = ashr i64 %shl, 56 %ashr = ashr i64 %shl, 56
store i64 %ashr, i64 addrspace(1)* %out, align 8 store i64 %ashr, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}sext_in_reg_i16_to_i64: ; FUNC-LABEL: {{^}}sext_in_reg_i16_to_i64:
; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]] ; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]]
; GCN-DAG: s_bfe_i64 s{{\[}}[[SLO:[0-9]+]]:[[SHI:[0-9]+]]{{\]}}, [[VAL]], 0x100000 ; GCN-DAG: s_bfe_i64 s[[[SLO:[0-9]+]]:[[SHI:[0-9]+]]], [[VAL]], 0x100000
; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]] ; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]]
; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] ; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]]
; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[VLO]]:[[VHI]]]
define amdgpu_kernel void @sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 { define amdgpu_kernel void @sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 {
%c = shl i64 %a, %b %c = shl i64 %a, %b
%shl = shl i64 %c, 48 %shl = shl i64 %c, 48
%ashr = ashr i64 %shl, 48 %ashr = ashr i64 %shl, 48
store i64 %ashr, i64 addrspace(1)* %out, align 8 store i64 %ashr, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}sext_in_reg_i32_to_i64: ; FUNC-LABEL: {{^}}sext_in_reg_i32_to_i64:
; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]] ; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]]
; GCN-DAG: s_bfe_i64 s{{\[}}[[SLO:[0-9]+]]:[[SHI:[0-9]+]]{{\]}}, [[VAL]], 0x200000 ; GCN-DAG: s_bfe_i64 s[[[SLO:[0-9]+]]:[[SHI:[0-9]+]]], [[VAL]], 0x200000
; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]] ; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]]
; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] ; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]]
; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[VLO]]:[[VHI]]]
define amdgpu_kernel void @sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 { define amdgpu_kernel void @sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 {
%c = shl i64 %a, %b %c = shl i64 %a, %b
%shl = shl i64 %c, 32 %shl = shl i64 %c, 32
%ashr = ashr i64 %shl, 32 %ashr = ashr i64 %shl, 32
store i64 %ashr, i64 addrspace(1)* %out, align 8 store i64 %ashr, i64 addrspace(1)* %out, align 8
ret void ret void
} }
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; %shl = shl <1 x i64> %c, <i64 56> ; %shl = shl <1 x i64> %c, <i64 56>
; %ashr = ashr <1 x i64> %shl, <i64 56> ; %ashr = ashr <1 x i64> %shl, <i64 56>
; store <1 x i64> %ashr, <1 x i64> addrspace(1)* %out, align 8 ; store <1 x i64> %ashr, <1 x i64> addrspace(1)* %out, align 8
; ret void ; ret void
; } ; }
; FUNC-LABEL: {{^}}v_sext_in_reg_i1_to_i64: ; FUNC-LABEL: {{^}}v_sext_in_reg_i1_to_i64:
; SI: buffer_load_dwordx2 ; SI: buffer_load_dwordx2
; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} ; SI: v_lshl_b64 v[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]]
; GFX89: {{flat|global}}_load_dwordx2 ; GFX89: {{flat|global}}_load_dwordx2
; GFX89: v_lshlrev_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} ; GFX89: v_lshlrev_b64 v[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]]
; GCN: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 1 ; GCN: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 1
; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; SI: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @v_sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) #0 { define amdgpu_kernel void @v_sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid %a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
%b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid %b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
%a = load i64, i64 addrspace(1)* %a.gep, align 8 %a = load i64, i64 addrspace(1)* %a.gep, align 8
%b = load i64, i64 addrspace(1)* %b.gep, align 8 %b = load i64, i64 addrspace(1)* %b.gep, align 8
%c = shl i64 %a, %b %c = shl i64 %a, %b
%shl = shl i64 %c, 63 %shl = shl i64 %c, 63
%ashr = ashr i64 %shl, 63 %ashr = ashr i64 %shl, 63
store i64 %ashr, i64 addrspace(1)* %out.gep, align 8 store i64 %ashr, i64 addrspace(1)* %out.gep, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}v_sext_in_reg_i8_to_i64: ; FUNC-LABEL: {{^}}v_sext_in_reg_i8_to_i64:
; SI: buffer_load_dwordx2 ; SI: buffer_load_dwordx2
; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} ; SI: v_lshl_b64 v[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]]
; GFX89: {{flat|global}}_load_dwordx2 ; GFX89: {{flat|global}}_load_dwordx2
; GFX89: v_lshlrev_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} ; GFX89: v_lshlrev_b64 v[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]]
; GCN: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 8 ; GCN: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 8
; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; SI: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @v_sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) #0 { define amdgpu_kernel void @v_sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid %a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
%b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid %b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
%a = load i64, i64 addrspace(1)* %a.gep, align 8 %a = load i64, i64 addrspace(1)* %a.gep, align 8
%b = load i64, i64 addrspace(1)* %b.gep, align 8 %b = load i64, i64 addrspace(1)* %b.gep, align 8
%c = shl i64 %a, %b %c = shl i64 %a, %b
%shl = shl i64 %c, 56 %shl = shl i64 %c, 56
%ashr = ashr i64 %shl, 56 %ashr = ashr i64 %shl, 56
store i64 %ashr, i64 addrspace(1)* %out.gep, align 8 store i64 %ashr, i64 addrspace(1)* %out.gep, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}v_sext_in_reg_i16_to_i64: ; FUNC-LABEL: {{^}}v_sext_in_reg_i16_to_i64:
; SI: buffer_load_dwordx2 ; SI: buffer_load_dwordx2
; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} ; SI: v_lshl_b64 v[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]]
; GFX89: {{flat|global}}_load_dwordx2 ; GFX89: {{flat|global}}_load_dwordx2
; GFX89: v_lshlrev_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} ; GFX89: v_lshlrev_b64 v[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]]
; GCN: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 16 ; GCN: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 16
; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; SI: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[HI]]]
define amdgpu_kernel void @v_sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) #0 { define amdgpu_kernel void @v_sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid %a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
%b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid %b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
%a = load i64, i64 addrspace(1)* %a.gep, align 8 %a = load i64, i64 addrspace(1)* %a.gep, align 8
%b = load i64, i64 addrspace(1)* %b.gep, align 8 %b = load i64, i64 addrspace(1)* %b.gep, align 8
%c = shl i64 %a, %b %c = shl i64 %a, %b
%shl = shl i64 %c, 48 %shl = shl i64 %c, 48
%ashr = ashr i64 %shl, 48 %ashr = ashr i64 %shl, 48
store i64 %ashr, i64 addrspace(1)* %out.gep, align 8 store i64 %ashr, i64 addrspace(1)* %out.gep, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}v_sext_in_reg_i32_to_i64: ; FUNC-LABEL: {{^}}v_sext_in_reg_i32_to_i64:
; SI: buffer_load_dwordx2 ; SI: buffer_load_dwordx2
; SI: v_lshl_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, ; SI: v_lshl_b64 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]],
; GFX89: {{flat|global}}_load_dwordx2 ; GFX89: {{flat|global}}_load_dwordx2
; GFX89: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, ; GFX89: v_lshlrev_b64 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]],
; GCN: v_ashrrev_i32_e32 v[[SHR:[0-9]+]], 31, v[[LO]] ; GCN: v_ashrrev_i32_e32 v[[SHR:[0-9]+]], 31, v[[LO]]
; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[LO]]:[[SHR]]{{\]}} ; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[LO]]:[[SHR]]]
define amdgpu_kernel void @v_sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) #0 { define amdgpu_kernel void @v_sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid %a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
%b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid %b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
%a = load i64, i64 addrspace(1)* %a.gep, align 8 %a = load i64, i64 addrspace(1)* %a.gep, align 8
%b = load i64, i64 addrspace(1)* %b.gep, align 8 %b = load i64, i64 addrspace(1)* %b.gep, align 8
▲ Show 20 Lines • Show All 207 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) #0 {
store i16 %tmp6, i16 addrspace(1)* %out, align 2 store i16 %tmp6, i16 addrspace(1)* %out, align 2
ret void ret void
} }
; Make sure we propagate the VALUness to users of a moved scalar BFE. ; Make sure we propagate the VALUness to users of a moved scalar BFE.
; FUNC-LABEL: {{^}}v_sext_in_reg_i1_to_i64_move_use: ; FUNC-LABEL: {{^}}v_sext_in_reg_i1_to_i64_move_use:
; SI: buffer_load_dwordx2 ; SI: buffer_load_dwordx2
; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} ; SI: v_lshl_b64 v[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]]
; GFX89: {{flat|global}}_load_dwordx2 ; GFX89: {{flat|global}}_load_dwordx2
; GFX89: v_lshlrev_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} ; GFX89: v_lshlrev_b64 v[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]]
; GCN-DAG: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 1 ; GCN-DAG: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 1
; GCN-DAG: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN-DAG: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; GCN-DAG: v_and_b32_e32 v[[RESULT_LO:[0-9]+]], s{{[0-9]+}}, v[[LO]] ; GCN-DAG: v_and_b32_e32 v[[RESULT_LO:[0-9]+]], s{{[0-9]+}}, v[[LO]]
; GCN-DAG: v_and_b32_e32 v[[RESULT_HI:[0-9]+]], s{{[0-9]+}}, v[[HI]] ; GCN-DAG: v_and_b32_e32 v[[RESULT_HI:[0-9]+]], s{{[0-9]+}}, v[[HI]]
; SI: buffer_store_dwordx2 v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}} ; SI: buffer_store_dwordx2 v[[[RESULT_LO]]:[[RESULT_HI]]]
; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}} ; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[RESULT_LO]]:[[RESULT_HI]]]
define amdgpu_kernel void @v_sext_in_reg_i1_to_i64_move_use(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 %s.val) #0 { define amdgpu_kernel void @v_sext_in_reg_i1_to_i64_move_use(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 %s.val) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid %a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
%b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid %b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
%a = load i64, i64 addrspace(1)* %a.gep, align 8 %a = load i64, i64 addrspace(1)* %a.gep, align 8
%b = load i64, i64 addrspace(1)* %b.gep, align 8 %b = load i64, i64 addrspace(1)* %b.gep, align 8
%c = shl i64 %a, %b %c = shl i64 %a, %b
%shl = shl i64 %c, 63 %shl = shl i64 %c, 63
%ashr = ashr i64 %shl, 63 %ashr = ashr i64 %shl, 63
%and = and i64 %ashr, %s.val %and = and i64 %ashr, %s.val
store i64 %and, i64 addrspace(1)* %out.gep, align 8 store i64 %and, i64 addrspace(1)* %out.gep, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}v_sext_in_reg_i32_to_i64_move_use: ; FUNC-LABEL: {{^}}v_sext_in_reg_i32_to_i64_move_use:
; SI: buffer_load_dwordx2 ; SI: buffer_load_dwordx2
; SI: v_lshl_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, ; SI: v_lshl_b64 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]],
; GFX89: {{flat|global}}_load_dwordx2 ; GFX89: {{flat|global}}_load_dwordx2
; GFX89: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, ; GFX89: v_lshlrev_b64 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]],
; GCN-DAG: v_ashrrev_i32_e32 v[[SHR:[0-9]+]], 31, v[[LO]] ; GCN-DAG: v_ashrrev_i32_e32 v[[SHR:[0-9]+]], 31, v[[LO]]
; GCN-DAG: v_and_b32_e32 v[[RESULT_LO:[0-9]+]], s{{[0-9]+}}, v[[LO]] ; GCN-DAG: v_and_b32_e32 v[[RESULT_LO:[0-9]+]], s{{[0-9]+}}, v[[LO]]
; GCN-DAG: v_and_b32_e32 v[[RESULT_HI:[0-9]+]], s{{[0-9]+}}, v[[SHR]] ; GCN-DAG: v_and_b32_e32 v[[RESULT_HI:[0-9]+]], s{{[0-9]+}}, v[[SHR]]
; SI: buffer_store_dwordx2 v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}} ; SI: buffer_store_dwordx2 v[[[RESULT_LO]]:[[RESULT_HI]]]
; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}} ; GFX89: {{flat|global}}_store_dwordx2 v{{.+}}, v[[[RESULT_LO]]:[[RESULT_HI]]]
define amdgpu_kernel void @v_sext_in_reg_i32_to_i64_move_use(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 %s.val) #0 { define amdgpu_kernel void @v_sext_in_reg_i32_to_i64_move_use(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 %s.val) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid %a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
%b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid %b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
%a = load i64, i64 addrspace(1)* %a.gep, align 8 %a = load i64, i64 addrspace(1)* %a.gep, align 8
%b = load i64, i64 addrspace(1)* %b.gep, align 8 %b = load i64, i64 addrspace(1)* %b.gep, align 8
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llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -o - %s | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -o - %s | FileCheck %s
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-ni:7" target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-ni:7"
target triple = "amdgcn-amd-amdhsa" target triple = "amdgcn-amd-amdhsa"
; CHECK-LABEL: {{^}}t0: ; CHECK-LABEL: {{^}}t0:
; CHECK: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]], s[4:5], 0x0 ; CHECK: s_load_dwordx2 s[[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]], s[4:5], 0x0
; CHECK: v_mov_b32_e32 v{{[0-9]+}}, s[[PTR_HI]] ; CHECK: v_mov_b32_e32 v{{[0-9]+}}, s[[PTR_HI]]
; There should be no redundant copies from PTR_HI. ; There should be no redundant copies from PTR_HI.
; CHECK-NOT: v_mov_b32_e32 v{{[0-9]+}}, s[[PTR_HI]] ; CHECK-NOT: v_mov_b32_e32 v{{[0-9]+}}, s[[PTR_HI]]
define protected amdgpu_kernel void @t0(float addrspace(1)* %p, i32 %i0, i32 %j0, i32 %k0) { define protected amdgpu_kernel void @t0(float addrspace(1)* %p, i32 %i0, i32 %j0, i32 %k0) {
entry: entry:
%0 = tail call i32 @llvm.amdgcn.workitem.id.x() %0 = tail call i32 @llvm.amdgcn.workitem.id.x()
%i = add i32 %0, %i0 %i = add i32 %0, %i0
%j = add i32 %0, %j0 %j = add i32 %0, %j0
Show All 12 Lines

llvm/test/CodeGen/AMDGPU/sgpr-copy.ll

Show First 20 Lines • Show All 213 Lines • ▼ Show 20 Lines
; CHECK: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 5 ; CHECK: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 5
; CHECK: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 7 ; CHECK: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 7
; CHECK: s_branch ; CHECK: s_branch
; CHECK: BB{{[0-9]+_[0-9]+}}: ; CHECK: BB{{[0-9]+_[0-9]+}}:
; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 11 ; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 11
; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 13 ; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 13
; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[SAMPLE_LO]]:[[SAMPLE_HI]]{{\]}} ; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v[[[SAMPLE_LO]]:[[SAMPLE_HI]]]
; CHECK: exp ; CHECK: exp
; CHECK: s_endpgm ; CHECK: s_endpgm
define amdgpu_ps void @sample_v3([17 x <4 x i32>] addrspace(4)* inreg %arg, [32 x <4 x i32>] addrspace(4)* inreg %arg1, [16 x <8 x i32>] addrspace(4)* inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { define amdgpu_ps void @sample_v3([17 x <4 x i32>] addrspace(4)* inreg %arg, [32 x <4 x i32>] addrspace(4)* inreg %arg1, [16 x <8 x i32>] addrspace(4)* inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
entry: entry:
%tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg, i64 0, i32 0 %tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg, i64 0, i32 0
%tmp21 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0 %tmp21 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0
%tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 16, i32 0) %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 16, i32 0)
%tmp23 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 0 %tmp23 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 0
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; CHECK-LABEL:{{^}}sample_rsrc ; CHECK-LABEL:{{^}}sample_rsrc
; CHECK: s_cmp_eq_u32 ; CHECK: s_cmp_eq_u32
; CHECK: s_cbranch_scc0 [[END:.LBB[0-9]+_[0-9]+]] ; CHECK: s_cbranch_scc0 [[END:.LBB[0-9]+_[0-9]+]]
; CHECK: v_add_{{[iu]}}32_e32 v[[ADD:[0-9]+]], vcc, 1, v{{[0-9]+}} ; CHECK: v_add_{{[iu]}}32_e32 v[[ADD:[0-9]+]], vcc, 1, v{{[0-9]+}}
; [[END]]: ; [[END]]:
; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[ADD]]{{\]}} ; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[ADD]]]
; CHECK: s_endpgm ; CHECK: s_endpgm
define amdgpu_ps void @sample_rsrc([6 x <4 x i32>] addrspace(4)* inreg %arg, [17 x <4 x i32>] addrspace(4)* inreg %arg1, [16 x <4 x i32>] addrspace(4)* inreg %arg2, [32 x <8 x i32>] addrspace(4)* inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { define amdgpu_ps void @sample_rsrc([6 x <4 x i32>] addrspace(4)* inreg %arg, [17 x <4 x i32>] addrspace(4)* inreg %arg1, [16 x <4 x i32>] addrspace(4)* inreg %arg2, [32 x <8 x i32>] addrspace(4)* inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
bb: bb:
%tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg1, i32 0, i32 0 %tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg1, i32 0, i32 0
%tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !3 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !3
%tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp22, i32 16, i32 0) %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp22, i32 16, i32 0)
%tmp25 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(4)* %arg3, i32 0, i32 0 %tmp25 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(4)* %arg3, i32 0, i32 0
%tmp26 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp25, !tbaa !3 %tmp26 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp25, !tbaa !3
▲ Show 20 Lines • Show All 91 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; FIXME: Fails with -enable-var-scope ; FIXME: Fails with -enable-var-scope
; Make sure 64-bit BFE pattern does a 32-bit BFE on the relevant half. ; Make sure 64-bit BFE pattern does a 32-bit BFE on the relevant half.
; Extract the high bit of the low half ; Extract the high bit of the low half
; GCN-LABEL: {{^}}v_uextract_bit_31_i64: ; GCN-LABEL: {{^}}v_uextract_bit_31_i64:
; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]] ; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[SHIFT]]:[[ZERO]]]
define amdgpu_kernel void @v_uextract_bit_31_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_31_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workgroup.id.x() %id.x = tail call i32 @llvm.amdgcn.workgroup.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 31 %srl = lshr i64 %ld.64, 31
%bit = and i64 %srl, 1 %bit = and i64 %srl, 1
store i64 %bit, i64 addrspace(1)* %out.gep store i64 %bit, i64 addrspace(1)* %out.gep
ret void ret void
} }
; Extract the high bit of the high half ; Extract the high bit of the high half
; GCN-LABEL: {{^}}v_uextract_bit_63_i64: ; GCN-LABEL: {{^}}v_uextract_bit_63_i64:
; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]] ; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]] ; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]]
; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO1]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[SHIFT]]:[[ZERO1]]]
define amdgpu_kernel void @v_uextract_bit_63_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_63_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 63 %srl = lshr i64 %ld.64, 63
%bit = and i64 %srl, 1 %bit = and i64 %srl, 1
store i64 %bit, i64 addrspace(1)* %out.gep store i64 %bit, i64 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_uextract_bit_1_i64: ; GCN-LABEL: {{^}}v_uextract_bit_1_i64:
; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 1 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 1
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO]]]
define amdgpu_kernel void @v_uextract_bit_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workgroup.id.x() %id.x = tail call i32 @llvm.amdgcn.workgroup.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 1 %srl = lshr i64 %ld.64, 1
%bit = and i64 %srl, 1 %bit = and i64 %srl, 1
store i64 %bit, i64 addrspace(1)* %out.gep store i64 %bit, i64 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_uextract_bit_20_i64: ; GCN-LABEL: {{^}}v_uextract_bit_20_i64:
; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 20, 1 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 20, 1
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO]]]
define amdgpu_kernel void @v_uextract_bit_20_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_20_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workgroup.id.x() %id.x = tail call i32 @llvm.amdgcn.workgroup.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 20 %srl = lshr i64 %ld.64, 20
%bit = and i64 %srl, 1 %bit = and i64 %srl, 1
store i64 %bit, i64 addrspace(1)* %out.gep store i64 %bit, i64 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_uextract_bit_32_i64: ; GCN-LABEL: {{^}}v_uextract_bit_32_i64:
; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
; GCN-DAG: v_and_b32_e32 v[[AND:[0-9]+]], 1, [[VAL]] ; GCN-DAG: v_and_b32_e32 v[[AND:[0-9]+]], 1, [[VAL]]
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]]{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]]{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[AND]]:[[ZERO1]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[AND]]:[[ZERO1]]]
define amdgpu_kernel void @v_uextract_bit_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 32 %srl = lshr i64 %ld.64, 32
%bit = and i64 %srl, 1 %bit = and i64 %srl, 1
store i64 %bit, i64 addrspace(1)* %out.gep store i64 %bit, i64 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_uextract_bit_33_i64: ; GCN-LABEL: {{^}}v_uextract_bit_33_i64:
; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 1{{$}} ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 1{{$}}
; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]] ; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]]
; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO1]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO1]]]
define amdgpu_kernel void @v_uextract_bit_33_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_33_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 33 %srl = lshr i64 %ld.64, 33
%bit = and i64 %srl, 1 %bit = and i64 %srl, 1
store i64 %bit, i64 addrspace(1)* %out.gep store i64 %bit, i64 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_uextract_bit_20_21_i64: ; GCN-LABEL: {{^}}v_uextract_bit_20_21_i64:
; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 20, 2 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 20, 2
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO]]]
define amdgpu_kernel void @v_uextract_bit_20_21_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_20_21_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workgroup.id.x() %id.x = tail call i32 @llvm.amdgcn.workgroup.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 20 %srl = lshr i64 %ld.64, 20
%bit = and i64 %srl, 3 %bit = and i64 %srl, 3
store i64 %bit, i64 addrspace(1)* %out.gep store i64 %bit, i64 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_uextract_bit_1_30_i64: ; GCN-LABEL: {{^}}v_uextract_bit_1_30_i64:
; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 30 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 30
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO]]]
define amdgpu_kernel void @v_uextract_bit_1_30_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_1_30_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workgroup.id.x() %id.x = tail call i32 @llvm.amdgcn.workgroup.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 1 %srl = lshr i64 %ld.64, 1
%bit = and i64 %srl, 1073741823 %bit = and i64 %srl, 1073741823
store i64 %bit, i64 addrspace(1)* %out.gep store i64 %bit, i64 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_uextract_bit_1_31_i64: ; GCN-LABEL: {{^}}v_uextract_bit_1_31_i64:
; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 1, [[VAL]] ; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 1, [[VAL]]
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[SHIFT]]:[[ZERO]]]
define amdgpu_kernel void @v_uextract_bit_1_31_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_1_31_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workgroup.id.x() %id.x = tail call i32 @llvm.amdgcn.workgroup.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 1 %srl = lshr i64 %ld.64, 1
%bit = and i64 %srl, 2147483647 %bit = and i64 %srl, 2147483647
store i64 %bit, i64 addrspace(1)* %out.gep store i64 %bit, i64 addrspace(1)* %out.gep
ret void ret void
} }
; Spans the dword boundary, so requires full shift. ; Spans the dword boundary, so requires full shift.
; Truncated after the shift, so only low shift result is used. ; Truncated after the shift, so only low shift result is used.
; GCN-LABEL: {{^}}v_uextract_bit_31_32_i64: ; GCN-LABEL: {{^}}v_uextract_bit_31_32_i64:
; GCN: buffer_load_dwordx2 v{{\[}}[[VALLO:[0-9]+]]:[[VALHI:[0-9]+]]{{\]}} ; GCN: buffer_load_dwordx2 v[[[VALLO:[0-9]+]]:[[VALHI:[0-9]+]]]
; GCN: v_alignbit_b32 v[[SHRLO:[0-9]+]], v[[VALHI]], v[[VALLO]], 31 ; GCN: v_alignbit_b32 v[[SHRLO:[0-9]+]], v[[VALHI]], v[[VALLO]], 31
; GCN-DAG: v_and_b32_e32 v[[AND:[0-9]+]], 3, v[[SHRLO]]{{$}} ; GCN-DAG: v_and_b32_e32 v[[AND:[0-9]+]], 3, v[[SHRLO]]{{$}}
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[AND]]:[[ZERO]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[AND]]:[[ZERO]]]
define amdgpu_kernel void @v_uextract_bit_31_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_31_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workgroup.id.x() %id.x = tail call i32 @llvm.amdgcn.workgroup.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 31 %srl = lshr i64 %ld.64, 31
%bit = and i64 %srl, 3 %bit = and i64 %srl, 3
store i64 %bit, i64 addrspace(1)* %out.gep store i64 %bit, i64 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_uextract_bit_32_33_i64: ; GCN-LABEL: {{^}}v_uextract_bit_32_33_i64:
; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 2 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 2
; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]] ; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]]
; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO1]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO1]]]
define amdgpu_kernel void @v_uextract_bit_32_33_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_32_33_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 33 %srl = lshr i64 %ld.64, 33
%bit = and i64 %srl, 3 %bit = and i64 %srl, 3
store i64 %bit, i64 addrspace(1)* %out.gep store i64 %bit, i64 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_uextract_bit_30_60_i64: ; GCN-LABEL: {{^}}v_uextract_bit_30_60_i64:
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: buffer_load_dwordx2 v{{\[}}[[VALLO:[0-9]+]]:[[VALHI:[0-9]+]]{{\]}} ; GCN: buffer_load_dwordx2 v[[[VALLO:[0-9]+]]:[[VALHI:[0-9]+]]]
; GCN: v_alignbit_b32 v[[SHRLO:[0-9]+]], v[[VALHI]], v[[VALLO]], 30 ; GCN: v_alignbit_b32 v[[SHRLO:[0-9]+]], v[[VALHI]], v[[VALLO]], 30
; GCN-DAG: v_and_b32_e32 v[[AND:[0-9]+]], 0x3fffffff, v[[SHRLO]]{{$}} ; GCN-DAG: v_and_b32_e32 v[[AND:[0-9]+]], 0x3fffffff, v[[SHRLO]]{{$}}
; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]] ; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]]
; GCN: buffer_store_dwordx2 v{{\[}}[[AND]]:[[ZERO1]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[AND]]:[[ZERO1]]]
define amdgpu_kernel void @v_uextract_bit_30_60_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_30_60_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 30 %srl = lshr i64 %ld.64, 30
%bit = and i64 %srl, 1073741823 %bit = and i64 %srl, 1073741823
store i64 %bit, i64 addrspace(1)* %out.gep store i64 %bit, i64 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_uextract_bit_33_63_i64: ; GCN-LABEL: {{^}}v_uextract_bit_33_63_i64:
; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 30 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 30
; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]] ; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]]
; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO1]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO1]]]
define amdgpu_kernel void @v_uextract_bit_33_63_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_33_63_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 33 %srl = lshr i64 %ld.64, 33
%bit = and i64 %srl, 1073741823 %bit = and i64 %srl, 1073741823
store i64 %bit, i64 addrspace(1)* %out.gep store i64 %bit, i64 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_uextract_bit_31_63_i64: ; GCN-LABEL: {{^}}v_uextract_bit_31_63_i64:
; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: buffer_load_dwordx2 v{{\[}}[[VALLO:[0-9]+]]:[[VALHI:[0-9]+]]{{\]}} ; GCN: buffer_load_dwordx2 v[[[VALLO:[0-9]+]]:[[VALHI:[0-9]+]]]
; GCN: v_alignbit_b32 v[[SHRLO:[0-9]+]], v[[VALHI]], v[[VALLO]], 31 ; GCN: v_alignbit_b32 v[[SHRLO:[0-9]+]], v[[VALHI]], v[[VALLO]], 31
; GCN: buffer_store_dwordx2 v{{\[}}[[SHRLO]]:[[ZERO]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[SHRLO]]:[[ZERO]]]
define amdgpu_kernel void @v_uextract_bit_31_63_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_31_63_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 31 %srl = lshr i64 %ld.64, 31
%and = and i64 %srl, 4294967295 %and = and i64 %srl, 4294967295
store i64 %and, i64 addrspace(1)* %out store i64 %and, i64 addrspace(1)* %out
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_uextract_bit_33_i64_trunc_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%srl = lshr i64 %ld.64, 33 %srl = lshr i64 %ld.64, 33
%trunc = trunc i64 %srl to i32 %trunc = trunc i64 %srl to i32
%bit = and i32 %trunc, 1 %bit = and i32 %trunc, 1
store i32 %bit, i32 addrspace(1)* %out.gep store i32 %bit, i32 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}v_uextract_bit_31_32_i64_trunc_i32: ; GCN-LABEL: {{^}}v_uextract_bit_31_32_i64_trunc_i32:
; GCN: buffer_load_dwordx2 v{{\[}}[[VALLO:[0-9]+]]:[[VALHI:[0-9]+]]{{\]}} ; GCN: buffer_load_dwordx2 v[[[VALLO:[0-9]+]]:[[VALHI:[0-9]+]]]
; GCN: v_alignbit_b32 v[[SHRLO:[0-9]+]], v[[VALHI]], v[[VALLO]], 31 ; GCN: v_alignbit_b32 v[[SHRLO:[0-9]+]], v[[VALHI]], v[[VALLO]], 31
; GCN-NEXT: v_and_b32_e32 v[[SHRLO]], 3, v[[SHRLO]] ; GCN-NEXT: v_and_b32_e32 v[[SHRLO]], 3, v[[SHRLO]]
; GCN-NOT: v[[SHRLO]] ; GCN-NOT: v[[SHRLO]]
; GCN: buffer_store_dword v[[SHRLO]] ; GCN: buffer_store_dword v[[SHRLO]]
define amdgpu_kernel void @v_uextract_bit_31_32_i64_trunc_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_31_32_i64_trunc_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 31 %srl = lshr i64 %ld.64, 31
%trunc = trunc i64 %srl to i32 %trunc = trunc i64 %srl to i32
%bit = and i32 %trunc, 3 %bit = and i32 %trunc, 3
store i32 %bit, i32 addrspace(1)* %out.gep store i32 %bit, i32 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}and_not_mask_i64: ; GCN-LABEL: {{^}}and_not_mask_i64:
; GCN-DAG: buffer_load_dword v[[VAL:[0-9]+]] ; GCN-DAG: buffer_load_dword v[[VAL:[0-9]+]]
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN-DAG: v_mov_b32_e32 v[[SHRHI:[0-9]+]], v[[ZERO]]{{$}} ; GCN-DAG: v_mov_b32_e32 v[[SHRHI:[0-9]+]], v[[ZERO]]{{$}}
; GCN: v_lshrrev_b32_e32 [[SHR:v[0-9]+]], 20, v[[VAL]] ; GCN: v_lshrrev_b32_e32 [[SHR:v[0-9]+]], 20, v[[VAL]]
; GCN-DAG: v_and_b32_e32 v[[SHRLO:[0-9]+]], 4, [[SHR]] ; GCN-DAG: v_and_b32_e32 v[[SHRLO:[0-9]+]], 4, [[SHR]]
; GCN-NOT: v[[SHRLO]] ; GCN-NOT: v[[SHRLO]]
; GCN-NOT: v[[SHRHI]] ; GCN-NOT: v[[SHRHI]]
; GCN: buffer_store_dwordx2 v{{\[}}[[SHRLO]]:[[SHRHI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[SHRLO]]:[[SHRHI]]]
define amdgpu_kernel void @and_not_mask_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @and_not_mask_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 20 %srl = lshr i64 %ld.64, 20
%bit = and i64 %srl, 4 %bit = and i64 %srl, 4
store i64 %bit, i64 addrspace(1)* %out.gep store i64 %bit, i64 addrspace(1)* %out.gep
ret void ret void
} }
; The instruction count is the same with/without hasOneUse, but ; The instruction count is the same with/without hasOneUse, but
; keeping the 32-bit and has a smaller encoding size than the bfe. ; keeping the 32-bit and has a smaller encoding size than the bfe.
; GCN-LABEL: {{^}}v_uextract_bit_27_29_multi_use_shift_i64: ; GCN-LABEL: {{^}}v_uextract_bit_27_29_multi_use_shift_i64:
; GCN-DAG: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] ; GCN-DAG: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]
; GCN-DAG: v_lshr_b64 v{{\[}}[[SHRLO:[0-9]+]]:[[SHRHI:[0-9]+]]{{\]}}, [[VAL]], 27 ; GCN-DAG: v_lshr_b64 v[[[SHRLO:[0-9]+]]:[[SHRHI:[0-9]+]]], [[VAL]], 27
; GCN-DAG: v_and_b32_e32 v[[AND:[0-9]+]], 3, v[[SHRLO]] ; GCN-DAG: v_and_b32_e32 v[[AND:[0-9]+]], 3, v[[SHRLO]]
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[SHRLO]]:[[SHRHI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[SHRLO]]:[[SHRHI]]]
; GCN: buffer_store_dwordx2 v{{\[}}[[AND]]:[[ZERO]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[AND]]:[[ZERO]]]
define amdgpu_kernel void @v_uextract_bit_27_29_multi_use_shift_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_27_29_multi_use_shift_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 27 %srl = lshr i64 %ld.64, 27
%bit = and i64 %srl, 3 %bit = and i64 %srl, 3
store volatile i64 %srl, i64 addrspace(1)* %out store volatile i64 %srl, i64 addrspace(1)* %out
store volatile i64 %bit, i64 addrspace(1)* %out store volatile i64 %bit, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_uextract_bit_34_37_multi_use_shift_i64: ; GCN-LABEL: {{^}}v_uextract_bit_34_37_multi_use_shift_i64:
; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
; GCN-DAG: v_mov_b32_e32 v[[ZERO_SHR:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO_SHR:[0-9]+]], 0{{$}}
; GCN: v_mov_b32_e32 v[[ZERO_BFE:[0-9]+]], v[[ZERO_SHR]] ; GCN: v_mov_b32_e32 v[[ZERO_BFE:[0-9]+]], v[[ZERO_SHR]]
; GCN-DAG: v_lshrrev_b32_e32 v[[SHR:[0-9]+]], 2, [[VAL]] ; GCN-DAG: v_lshrrev_b32_e32 v[[SHR:[0-9]+]], 2, [[VAL]]
; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 2, 3 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 2, 3
; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[SHR]]:[[ZERO_SHR]]{{\]}} ; GCN-DAG: buffer_store_dwordx2 v[[[SHR]]:[[ZERO_SHR]]]
; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO_BFE]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO_BFE]]]
define amdgpu_kernel void @v_uextract_bit_34_37_multi_use_shift_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_34_37_multi_use_shift_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 34 %srl = lshr i64 %ld.64, 34
%bit = and i64 %srl, 7 %bit = and i64 %srl, 7
store volatile i64 %srl, i64 addrspace(1)* %out store volatile i64 %srl, i64 addrspace(1)* %out
store volatile i64 %bit, i64 addrspace(1)* %out store volatile i64 %bit, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_uextract_bit_33_36_use_upper_half_shift_i64: ; GCN-LABEL: {{^}}v_uextract_bit_33_36_use_upper_half_shift_i64:
; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 3 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 3
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:{{[0-9]+\]}} ; GCN: buffer_store_dwordx2 v[[[BFE]]:{{[0-9]+\]}}
; GCN: buffer_store_dword v[[ZERO]] ; GCN: buffer_store_dword v[[ZERO]]
define amdgpu_kernel void @v_uextract_bit_33_36_use_upper_half_shift_i64(i64 addrspace(1)* %out0, i32 addrspace(1)* %out1, i64 addrspace(1)* %in) #1 { define amdgpu_kernel void @v_uextract_bit_33_36_use_upper_half_shift_i64(i64 addrspace(1)* %out0, i32 addrspace(1)* %out1, i64 addrspace(1)* %in) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x
%out0.gep = getelementptr i64, i64 addrspace(1)* %out0, i32 %id.x %out0.gep = getelementptr i64, i64 addrspace(1)* %out0, i32 %id.x
%out1.gep = getelementptr i32, i32 addrspace(1)* %out1, i32 %id.x %out1.gep = getelementptr i32, i32 addrspace(1)* %out1, i32 %id.x
%ld.64 = load i64, i64 addrspace(1)* %in.gep %ld.64 = load i64, i64 addrspace(1)* %in.gep
%srl = lshr i64 %ld.64, 33 %srl = lshr i64 %ld.64, 33
Show All 15 Lines

llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=GCN %s
; lshr (i64 x), c: c > 32 => reg_sequence lshr (i32 hi_32(x)), (c - 32), 0 ; lshr (i64 x), c: c > 32 => reg_sequence lshr (i32 hi_32(x)), (c - 32), 0
; GCN-LABEL: {{^}}lshr_i64_35: ; GCN-LABEL: {{^}}lshr_i64_35:
; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]] ; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]]
; GCN-DAG: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 3, [[VAL]] ; GCN-DAG: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 3, [[VAL]]
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
define amdgpu_kernel void @lshr_i64_35(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { define amdgpu_kernel void @lshr_i64_35(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
%val = load i64, i64 addrspace(1)* %in %val = load i64, i64 addrspace(1)* %in
%shl = lshr i64 %val, 35 %shl = lshr i64 %val, 35
store i64 %shl, i64 addrspace(1)* %out store i64 %shl, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}lshr_i64_63: ; GCN-LABEL: {{^}}lshr_i64_63:
; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]] ; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]]
; GCN-DAG: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 31, [[VAL]] ; GCN-DAG: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 31, [[VAL]]
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
define amdgpu_kernel void @lshr_i64_63(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { define amdgpu_kernel void @lshr_i64_63(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
%val = load i64, i64 addrspace(1)* %in %val = load i64, i64 addrspace(1)* %in
%shl = lshr i64 %val, 63 %shl = lshr i64 %val, 63
store i64 %shl, i64 addrspace(1)* %out store i64 %shl, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}lshr_i64_33: ; GCN-LABEL: {{^}}lshr_i64_33:
; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]] ; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]]
; GCN-DAG: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 1, [[VAL]] ; GCN-DAG: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 1, [[VAL]]
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
define amdgpu_kernel void @lshr_i64_33(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { define amdgpu_kernel void @lshr_i64_33(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
%val = load i64, i64 addrspace(1)* %in %val = load i64, i64 addrspace(1)* %in
%shl = lshr i64 %val, 33 %shl = lshr i64 %val, 33
store i64 %shl, i64 addrspace(1)* %out store i64 %shl, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}lshr_i64_32: ; GCN-LABEL: {{^}}lshr_i64_32:
; GCN-DAG: buffer_load_dword v[[LO:[0-9]+]] ; GCN-DAG: buffer_load_dword v[[LO:[0-9]+]]
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
define amdgpu_kernel void @lshr_i64_32(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { define amdgpu_kernel void @lshr_i64_32(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
%val = load i64, i64 addrspace(1)* %in %val = load i64, i64 addrspace(1)* %in
%shl = lshr i64 %val, 32 %shl = lshr i64 %val, 32
store i64 %shl, i64 addrspace(1)* %out store i64 %shl, i64 addrspace(1)* %out
ret void ret void
} }
; Make sure the and of the constant doesn't prevent bfe from forming ; Make sure the and of the constant doesn't prevent bfe from forming
; after 64-bit shift is split. ; after 64-bit shift is split.
; GCN-LABEL: {{^}}lshr_and_i64_35: ; GCN-LABEL: {{^}}lshr_and_i64_35:
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN-DAG: buffer_load_dword v[[LO:[0-9]+]] ; GCN-DAG: buffer_load_dword v[[LO:[0-9]+]]
; GCN: v_bfe_u32 v[[BFE:[0-9]+]], v[[LO]], 8, 23 ; GCN: v_bfe_u32 v[[BFE:[0-9]+]], v[[LO]], 8, 23
; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO]]]
define amdgpu_kernel void @lshr_and_i64_35(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { define amdgpu_kernel void @lshr_and_i64_35(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
%val = load i64, i64 addrspace(1)* %in %val = load i64, i64 addrspace(1)* %in
%and = and i64 %val, 9223372036854775807 ; 0x7fffffffffffffff %and = and i64 %val, 9223372036854775807 ; 0x7fffffffffffffff
%shl = lshr i64 %and, 40 %shl = lshr i64 %and, 40
store i64 %shl, i64 addrspace(1)* %out store i64 %shl, i64 addrspace(1)* %out
ret void ret void
} }
; lshl (i64 x), c: c > 32 => reg_sequence lshl 0, (i32 lo_32(x)), (c - 32) ; lshl (i64 x), c: c > 32 => reg_sequence lshl 0, (i32 lo_32(x)), (c - 32)
; GCN-LABEL: {{^}}shl_i64_const_35: ; GCN-LABEL: {{^}}shl_i64_const_35:
; GCN: buffer_load_dword [[VAL:v[0-9]+]] ; GCN: buffer_load_dword [[VAL:v[0-9]+]]
; GCN: v_lshlrev_b32_e32 v[[HI:[0-9]+]], 3, [[VAL]] ; GCN: v_lshlrev_b32_e32 v[[HI:[0-9]+]], 3, [[VAL]]
; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
define amdgpu_kernel void @shl_i64_const_35(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { define amdgpu_kernel void @shl_i64_const_35(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
%val = load i64, i64 addrspace(1)* %in %val = load i64, i64 addrspace(1)* %in
%shl = shl i64 %val, 35 %shl = shl i64 %val, 35
store i64 %shl, i64 addrspace(1)* %out store i64 %shl, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}shl_i64_const_32: ; GCN-LABEL: {{^}}shl_i64_const_32:
; GCN-DAG: buffer_load_dword v[[HI:[0-9]+]] ; GCN-DAG: buffer_load_dword v[[HI:[0-9]+]]
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
define amdgpu_kernel void @shl_i64_const_32(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { define amdgpu_kernel void @shl_i64_const_32(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
%val = load i64, i64 addrspace(1)* %in %val = load i64, i64 addrspace(1)* %in
%shl = shl i64 %val, 32 %shl = shl i64 %val, 32
store i64 %shl, i64 addrspace(1)* %out store i64 %shl, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}shl_i64_const_63: ; GCN-LABEL: {{^}}shl_i64_const_63:
; GCN: buffer_load_dword [[VAL:v[0-9]+]] ; GCN: buffer_load_dword [[VAL:v[0-9]+]]
; GCN: v_lshlrev_b32_e32 v[[HI:[0-9]+]], 31, [[VAL]] ; GCN: v_lshlrev_b32_e32 v[[HI:[0-9]+]], 31, [[VAL]]
; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
define amdgpu_kernel void @shl_i64_const_63(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { define amdgpu_kernel void @shl_i64_const_63(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
%val = load i64, i64 addrspace(1)* %in %val = load i64, i64 addrspace(1)* %in
%shl = shl i64 %val, 63 %shl = shl i64 %val, 63
store i64 %shl, i64 addrspace(1)* %out store i64 %shl, i64 addrspace(1)* %out
ret void ret void
} }
; ashr (i64 x), 63 => (ashr lo(x), 31), lo(x) ; ashr (i64 x), 63 => (ashr lo(x), 31), lo(x)
▲ Show 20 Lines • Show All 106 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @trunc_shl_33_i32_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) {
%val = load i64, i64 addrspace(1)* %in %val = load i64, i64 addrspace(1)* %in
%shl = shl i64 %val, 33 %shl = shl i64 %val, 33
%trunc = trunc i64 %shl to i32 %trunc = trunc i64 %shl to i32
store i32 %trunc, i32 addrspace(1)* %out store i32 %trunc, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}trunc_shl_16_v2i32_v2i64: ; GCN-LABEL: {{^}}trunc_shl_16_v2i32_v2i64:
; GCN: buffer_load_dwordx4 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} ; GCN: buffer_load_dwordx4 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
; GCN-DAG: v_lshlrev_b32_e32 v[[RESHI:[0-9]+]], 16, v{{[0-9]+}} ; GCN-DAG: v_lshlrev_b32_e32 v[[RESHI:[0-9]+]], 16, v{{[0-9]+}}
; GCN-DAG: v_lshlrev_b32_e32 v[[RESLO:[0-9]+]], 16, v[[LO]] ; GCN-DAG: v_lshlrev_b32_e32 v[[RESLO:[0-9]+]], 16, v[[LO]]
; GCN: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[RESLO]]:[[RESHI]]]
define amdgpu_kernel void @trunc_shl_16_v2i32_v2i64(<2 x i32> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { define amdgpu_kernel void @trunc_shl_16_v2i32_v2i64(<2 x i32> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
%val = load <2 x i64>, <2 x i64> addrspace(1)* %in %val = load <2 x i64>, <2 x i64> addrspace(1)* %in
%shl = shl <2 x i64> %val, <i64 16, i64 16> %shl = shl <2 x i64> %val, <i64 16, i64 16>
%trunc = trunc <2 x i64> %shl to <2 x i32> %trunc = trunc <2 x i64> %shl to <2 x i32>
store <2 x i32> %trunc, <2 x i32> addrspace(1)* %out store <2 x i32> %trunc, <2 x i32> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}trunc_shl_31_i32_i64_multi_use: ; GCN-LABEL: {{^}}trunc_shl_31_i32_i64_multi_use:
; GCN: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] ; GCN: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]
; GCN: v_lshl_b64 v{{\[}}[[RESLO:[0-9]+]]:[[RESHI:[0-9]+]]{{\]}}, [[VAL]], 31 ; GCN: v_lshl_b64 v[[[RESLO:[0-9]+]]:[[RESHI:[0-9]+]]], [[VAL]], 31
; GCN: buffer_store_dword v[[RESLO]] ; GCN: buffer_store_dword v[[RESLO]]
; GCN: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[RESLO]]:[[RESHI]]]
define amdgpu_kernel void @trunc_shl_31_i32_i64_multi_use(i32 addrspace(1)* %out, i64 addrspace(1)* %in) { define amdgpu_kernel void @trunc_shl_31_i32_i64_multi_use(i32 addrspace(1)* %out, i64 addrspace(1)* %in) {
%val = load i64, i64 addrspace(1)* %in %val = load i64, i64 addrspace(1)* %in
%shl = shl i64 %val, 31 %shl = shl i64 %val, 31
%trunc = trunc i64 %shl to i32 %trunc = trunc i64 %shl to i32
store volatile i32 %trunc, i32 addrspace(1)* %out store volatile i32 %trunc, i32 addrspace(1)* %out
store volatile i64 %shl, i64 addrspace(1)* %in store volatile i64 %shl, i64 addrspace(1)* %in
ret void ret void
} }
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/shl-add-to-add-shl.ll

; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck %s ; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck %s
; Check transformation shl (or|add x, c2), c1 => or|add (shl x, c1), (c2 << c1) ; Check transformation shl (or|add x, c2), c1 => or|add (shl x, c1), (c2 << c1)
; Only one shift if expected, GEP shall not produce a separate shift ; Only one shift if expected, GEP shall not produce a separate shift
; CHECK-LABEL: {{^}}add_const_offset: ; CHECK-LABEL: {{^}}add_const_offset:
; CHECK: v_lshlrev_b32_e32 v[[SHL:[0-9]+]], 4, v0 ; CHECK: v_lshlrev_b32_e32 v[[SHL:[0-9]+]], 4, v0
; CHECK: v_add_u32_e32 v[[ADD:[0-9]+]], vcc, 0xc80, v[[SHL]] ; CHECK: v_add_u32_e32 v[[ADD:[0-9]+]], vcc, 0xc80, v[[SHL]]
; CHECK-NOT: v_lshl ; CHECK-NOT: v_lshl
; CHECK: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADD]] ; CHECK: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADD]]
; CHECK: load_dword v{{[0-9]+}}, v{{\[}}[[ADDRLO]]: ; CHECK: load_dword v{{[0-9]+}}, v[[[ADDRLO]]:
define amdgpu_kernel void @add_const_offset(i32 addrspace(1)* nocapture %arg) { define amdgpu_kernel void @add_const_offset(i32 addrspace(1)* nocapture %arg) {
bb: bb:
%id = tail call i32 @llvm.amdgcn.workitem.id.x() %id = tail call i32 @llvm.amdgcn.workitem.id.x()
%add = add i32 %id, 200 %add = add i32 %id, 200
%shl = shl i32 %add, 2 %shl = shl i32 %add, 2
%ptr = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %shl %ptr = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %shl
%val = load i32, i32 addrspace(1)* %ptr, align 4 %val = load i32, i32 addrspace(1)* %ptr, align 4
store i32 %val, i32 addrspace(1)* %arg, align 4 store i32 %val, i32 addrspace(1)* %arg, align 4
ret void ret void
} }
; CHECK-LABEL: {{^}}or_const_offset: ; CHECK-LABEL: {{^}}or_const_offset:
; CHECK: v_lshlrev_b32_e32 v[[SHL:[0-9]+]], 4, v0 ; CHECK: v_lshlrev_b32_e32 v[[SHL:[0-9]+]], 4, v0
; CHECK: v_or_b32_e32 v[[OR:[0-9]+]], 0x1000, v[[SHL]] ; CHECK: v_or_b32_e32 v[[OR:[0-9]+]], 0x1000, v[[SHL]]
; CHECK-NOT: v_lshl ; CHECK-NOT: v_lshl
; CHECK: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[OR]] ; CHECK: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[OR]]
; CHECK: load_dword v{{[0-9]+}}, v{{\[}}[[ADDRLO]]: ; CHECK: load_dword v{{[0-9]+}}, v[[[ADDRLO]]:
define amdgpu_kernel void @or_const_offset(i32 addrspace(1)* nocapture %arg) { define amdgpu_kernel void @or_const_offset(i32 addrspace(1)* nocapture %arg) {
bb: bb:
%id = tail call i32 @llvm.amdgcn.workitem.id.x() %id = tail call i32 @llvm.amdgcn.workitem.id.x()
%add = or i32 %id, 256 %add = or i32 %id, 256
%shl = shl i32 %add, 2 %shl = shl i32 %add, 2
%ptr = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %shl %ptr = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %shl
%val = load i32, i32 addrspace(1)* %ptr, align 4 %val = load i32, i32 addrspace(1)* %ptr, align 4
store i32 %val, i32 addrspace(1)* %arg, align 4 store i32 %val, i32 addrspace(1)* %arg, align 4
ret void ret void
} }
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()

llvm/test/CodeGen/AMDGPU/shl_add_constant.ll

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @shl_2_add_999_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
%val = load i32, i32 addrspace(1)* %ptr, align 4 %val = load i32, i32 addrspace(1)* %ptr, align 4
%shl = add i32 %val, 999 %shl = add i32 %val, 999
%result = shl i32 %shl, 2 %result = shl i32 %shl, 2
store i32 %result, i32 addrspace(1)* %out, align 4 store i32 %result, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; SI-LABEL: {{^}}test_add_shl_add_constant: ; SI-LABEL: {{^}}test_add_shl_add_constant:
; SI-DAG: s_load_dwordx2 s{{\[}}[[X:[0-9]+]]:[[Y:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x13 ; SI-DAG: s_load_dwordx2 s[[[X:[0-9]+]]:[[Y:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
; SI-DAG: s_lshl_b32 [[SHL3:s[0-9]+]], s[[X]], 3 ; SI-DAG: s_lshl_b32 [[SHL3:s[0-9]+]], s[[X]], 3
; SI: s_add_i32 [[RESULT:s[0-9]+]], [[SHL3]], s[[Y]] ; SI: s_add_i32 [[RESULT:s[0-9]+]], [[SHL3]], s[[Y]]
; SI: s_addk_i32 [[RESULT]], 0x3d8 ; SI: s_addk_i32 [[RESULT]], 0x3d8
; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]] ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]]
; SI: buffer_store_dword [[VRESULT]] ; SI: buffer_store_dword [[VRESULT]]
define amdgpu_kernel void @test_add_shl_add_constant(i32 addrspace(1)* %out, [8 x i32], i32 %x, i32 %y) #0 { define amdgpu_kernel void @test_add_shl_add_constant(i32 addrspace(1)* %out, [8 x i32], i32 %x, i32 %y) #0 {
%add.0 = add i32 %x, 123 %add.0 = add i32 %x, 123
%shl = shl i32 %add.0, 3 %shl = shl i32 %add.0, 3
%add.1 = add i32 %shl, %y %add.1 = add i32 %shl, %y
store i32 %add.1, i32 addrspace(1)* %out, align 4 store i32 %add.1, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; SI-LABEL: {{^}}test_add_shl_add_constant_inv: ; SI-LABEL: {{^}}test_add_shl_add_constant_inv:
; SI-DAG: s_load_dwordx2 s{{\[}}[[X:[0-9]+]]:[[Y:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x13 ; SI-DAG: s_load_dwordx2 s[[[X:[0-9]+]]:[[Y:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
; SI: s_lshl_b32 [[SHL3:s[0-9]+]], s[[X]], 3 ; SI: s_lshl_b32 [[SHL3:s[0-9]+]], s[[X]], 3
; SI: s_add_i32 [[TMP:s[0-9]+]], [[SHL3]], s[[Y]] ; SI: s_add_i32 [[TMP:s[0-9]+]], [[SHL3]], s[[Y]]
; SI: s_addk_i32 [[TMP]], 0x3d8 ; SI: s_addk_i32 [[TMP]], 0x3d8
; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[TMP]] ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[TMP]]
; SI: buffer_store_dword [[VRESULT]] ; SI: buffer_store_dword [[VRESULT]]
define amdgpu_kernel void @test_add_shl_add_constant_inv(i32 addrspace(1)* %out, [8 x i32], i32 %x, i32 %y) #0 { define amdgpu_kernel void @test_add_shl_add_constant_inv(i32 addrspace(1)* %out, [8 x i32], i32 %x, i32 %y) #0 {
%add.0 = add i32 %x, 123 %add.0 = add i32 %x, 123
%shl = shl i32 %add.0, 3 %shl = shl i32 %add.0, 3
%add.1 = add i32 %y, %shl %add.1 = add i32 %y, %shl
store i32 %add.1, i32 addrspace(1)* %out, align 4 store i32 %add.1, i32 addrspace(1)* %out, align 4
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

llvm/test/CodeGen/AMDGPU/shl_add_ptr_csub.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
; GCN-LABEL: {{^}}shl_base_atomicrmw_global_atomic_csub_ptr: ; GCN-LABEL: {{^}}shl_base_atomicrmw_global_atomic_csub_ptr:
; GCN-DAG: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, 2, v[4:5] ; GCN-DAG: v_lshlrev_b64 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]], 2, v[4:5]
; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 43 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 43
; GCN: v_add_co_u32 v[[EXTRA_LO:[0-9]+]], vcc_lo, 0x80, v4 ; GCN: v_add_co_u32 v[[EXTRA_LO:[0-9]+]], vcc_lo, 0x80, v4
; GCN: v_add_co_ci_u32_e32 v[[EXTRA_HI:[0-9]+]], vcc_lo, 0, v5, vcc_lo ; GCN: v_add_co_ci_u32_e32 v[[EXTRA_HI:[0-9]+]], vcc_lo, 0, v5, vcc_lo
; GCN: global_atomic_csub v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]], off offset:512 glc ; GCN: global_atomic_csub v{{[0-9]+}}, v[[[LO]]:[[HI]]], [[K]], off offset:512 glc
; GCN: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[EXTRA_LO]]:[[EXTRA_HI]]{{\]}} ; GCN: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[EXTRA_LO]]:[[EXTRA_HI]]]
define i32 @shl_base_atomicrmw_global_atomic_csub_ptr(i32 addrspace(1)* %out, i64 addrspace(1)* %extra.use, [512 x i32] addrspace(1)* %ptr) #0 { define i32 @shl_base_atomicrmw_global_atomic_csub_ptr(i32 addrspace(1)* %out, i64 addrspace(1)* %extra.use, [512 x i32] addrspace(1)* %ptr) #0 {
%arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(1)* %ptr, i64 0, i64 32 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(1)* %ptr, i64 0, i64 32
%cast = ptrtoint i32 addrspace(1)* %arrayidx0 to i64 %cast = ptrtoint i32 addrspace(1)* %arrayidx0 to i64
%shl = shl i64 %cast, 2 %shl = shl i64 %cast, 2
%castback = inttoptr i64 %shl to i32 addrspace(1)* %castback = inttoptr i64 %shl to i32 addrspace(1)*
%val = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %castback, i32 43) %val = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %castback, i32 43)
store volatile i64 %cast, i64 addrspace(1)* %extra.use, align 4 store volatile i64 %cast, i64 addrspace(1)* %extra.use, align 4
ret i32 %val ret i32 %val
} }
declare i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* nocapture, i32) #0 declare i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* nocapture, i32) #0
attributes #0 = { argmemonly nounwind } attributes #0 = { argmemonly nounwind }

llvm/test/CodeGen/AMDGPU/shl_add_ptr_global.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
; GCN-LABEL: {{^}}shl_base_atomicrmw_global_ptr: ; GCN-LABEL: {{^}}shl_base_atomicrmw_global_ptr:
; GCN-DAG: v_add_co_u32_e32 v[[EXTRA_LO:[0-9]+]], vcc, 0x80, v4 ; GCN-DAG: v_add_co_u32_e32 v[[EXTRA_LO:[0-9]+]], vcc, 0x80, v4
; GCN-DAG: v_addc_co_u32_e32 v[[EXTRA_HI:[0-9]+]], vcc, 0, v5, vcc ; GCN-DAG: v_addc_co_u32_e32 v[[EXTRA_HI:[0-9]+]], vcc, 0, v5, vcc
; GCN-DAG: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, 2, v[4:5] ; GCN-DAG: v_lshlrev_b64 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]], 2, v[4:5]
; GCN-DAG: v_mov_b32_e32 [[THREE:v[0-9]+]], 3 ; GCN-DAG: v_mov_b32_e32 [[THREE:v[0-9]+]], 3
; GCN-DAG: global_atomic_and v{{\[}}[[LO]]:[[HI]]{{\]}}, [[THREE]], off offset:512 ; GCN-DAG: global_atomic_and v[[[LO]]:[[HI]]], [[THREE]], off offset:512
; GCN-DAG: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[EXTRA_LO]]:[[EXTRA_HI]]{{\]}} ; GCN-DAG: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[EXTRA_LO]]:[[EXTRA_HI]]]
define void @shl_base_atomicrmw_global_ptr(i32 addrspace(1)* %out, i64 addrspace(1)* %extra.use, [512 x i32] addrspace(1)* %ptr) #0 { define void @shl_base_atomicrmw_global_ptr(i32 addrspace(1)* %out, i64 addrspace(1)* %extra.use, [512 x i32] addrspace(1)* %ptr) #0 {
%arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(1)* %ptr, i64 0, i64 32 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(1)* %ptr, i64 0, i64 32
%cast = ptrtoint i32 addrspace(1)* %arrayidx0 to i64 %cast = ptrtoint i32 addrspace(1)* %arrayidx0 to i64
%shl = shl i64 %cast, 2 %shl = shl i64 %cast, 2
%castback = inttoptr i64 %shl to i32 addrspace(1)* %castback = inttoptr i64 %shl to i32 addrspace(1)*
%val = atomicrmw and i32 addrspace(1)* %castback, i32 3 seq_cst %val = atomicrmw and i32 addrspace(1)* %castback, i32 3 seq_cst
store volatile i64 %cast, i64 addrspace(1)* %extra.use, align 4 store volatile i64 %cast, i64 addrspace(1)* %extra.use, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}shl_base_global_ptr_global_atomic_fadd: ; GCN-LABEL: {{^}}shl_base_global_ptr_global_atomic_fadd:
; GCN-DAG: v_add_co_u32_e32 v[[EXTRA_LO:[0-9]+]], vcc, 0x80, v4 ; GCN-DAG: v_add_co_u32_e32 v[[EXTRA_LO:[0-9]+]], vcc, 0x80, v4
; GCN-DAG: v_addc_co_u32_e32 v[[EXTRA_HI:[0-9]+]], vcc, 0, v5, vcc ; GCN-DAG: v_addc_co_u32_e32 v[[EXTRA_HI:[0-9]+]], vcc, 0, v5, vcc
; GCN-DAG: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, 2, v[4:5] ; GCN-DAG: v_lshlrev_b64 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]], 2, v[4:5]
; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x42c80000 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x42c80000
; GCN-DAG: global_atomic_add_f32 v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]], off offset:512 ; GCN-DAG: global_atomic_add_f32 v[[[LO]]:[[HI]]], [[K]], off offset:512
; GCN-DAG: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[EXTRA_LO]]:[[EXTRA_HI]]{{\]}} ; GCN-DAG: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[EXTRA_LO]]:[[EXTRA_HI]]]
define void @shl_base_global_ptr_global_atomic_fadd(i32 addrspace(1)* %out, i64 addrspace(1)* %extra.use, [512 x i32] addrspace(1)* %ptr) #0 { define void @shl_base_global_ptr_global_atomic_fadd(i32 addrspace(1)* %out, i64 addrspace(1)* %extra.use, [512 x i32] addrspace(1)* %ptr) #0 {
%arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(1)* %ptr, i64 0, i64 32 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(1)* %ptr, i64 0, i64 32
%cast = ptrtoint i32 addrspace(1)* %arrayidx0 to i64 %cast = ptrtoint i32 addrspace(1)* %arrayidx0 to i64
%shl = shl i64 %cast, 2 %shl = shl i64 %cast, 2
%castback = inttoptr i64 %shl to float addrspace(1)* %castback = inttoptr i64 %shl to float addrspace(1)*
call float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* %castback, float 100.0) call float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* %castback, float 100.0)
store volatile i64 %cast, i64 addrspace(1)* %extra.use, align 4 store volatile i64 %cast, i64 addrspace(1)* %extra.use, align 4
ret void ret void
} }
declare float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* nocapture, float) #1 declare float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* nocapture, float) #1
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { argmemonly nounwind willreturn } attributes #1 = { argmemonly nounwind willreturn }

llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll

Show First 20 Lines • Show All 77 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @no_reorder_barrier_local_load_global_store_local_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
store i32 %add, i32 addrspace(1)* %out, align 4 store i32 %add, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}reorder_constant_load_global_store_constant_load: ; GCN-LABEL: {{^}}reorder_constant_load_global_store_constant_load:
; GCN-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}} ; GCN-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}} ; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
; CI: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x1 ; CI: s_load_dword s{{[0-9]+}}, s[[[PTR_LO]]:[[PTR_HI]]], 0x1
; CI: buffer_store_dword ; CI: buffer_store_dword
; CI: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x3 ; CI: s_load_dword s{{[0-9]+}}, s[[[PTR_LO]]:[[PTR_HI]]], 0x3
; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x4 ; GFX9: s_load_dword s{{[0-9]+}}, s[[[PTR_LO]]:[[PTR_HI]]], 0x4
; GFX9: global_store_dword ; GFX9: global_store_dword
; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xc ; GFX9: s_load_dword s{{[0-9]+}}, s[[[PTR_LO]]:[[PTR_HI]]], 0xc
; CI: buffer_store_dword ; CI: buffer_store_dword
; GFX9: global_store_dword ; GFX9: global_store_dword
define amdgpu_kernel void @reorder_constant_load_global_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 { define amdgpu_kernel void @reorder_constant_load_global_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
%ptr0 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(3)* @stored_constant_ptr, align 8 %ptr0 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(3)* @stored_constant_ptr, align 8
%ptr1 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 1 %ptr1 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 1
%ptr2 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 3 %ptr2 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 3
%tmp1 = load i32, i32 addrspace(4)* %ptr1, align 4 %tmp1 = load i32, i32 addrspace(4)* %ptr1, align 4
store i32 99, i32 addrspace(1)* %gptr, align 4 store i32 99, i32 addrspace(1)* %gptr, align 4
%tmp2 = load i32, i32 addrspace(4)* %ptr2, align 4 %tmp2 = load i32, i32 addrspace(4)* %ptr2, align 4
%add = add nsw i32 %tmp1, %tmp2 %add = add nsw i32 %tmp1, %tmp2
store i32 %add, i32 addrspace(1)* %out, align 4 store i32 %add, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}reorder_constant_load_local_store_constant_load: ; GCN-LABEL: {{^}}reorder_constant_load_local_store_constant_load:
; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}} ; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}} ; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x1 ; CI-DAG: s_load_dword s{{[0-9]+}}, s[[[PTR_LO]]:[[PTR_HI]]], 0x1
; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x3 ; CI-DAG: s_load_dword s{{[0-9]+}}, s[[[PTR_LO]]:[[PTR_HI]]], 0x3
; GFX9-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x4 ; GFX9-DAG: s_load_dword s{{[0-9]+}}, s[[[PTR_LO]]:[[PTR_HI]]], 0x4
; GFX9-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xc ; GFX9-DAG: s_load_dword s{{[0-9]+}}, s[[[PTR_LO]]:[[PTR_HI]]], 0xc
; GCN-DAG: ds_write_b32 ; GCN-DAG: ds_write_b32
; CI: buffer_store_dword ; CI: buffer_store_dword
; GFX9: global_store_dword ; GFX9: global_store_dword
define amdgpu_kernel void @reorder_constant_load_local_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(3)* %lptr) #0 { define amdgpu_kernel void @reorder_constant_load_local_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(3)* %lptr) #0 {
%ptr0 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(3)* @stored_constant_ptr, align 8 %ptr0 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(3)* @stored_constant_ptr, align 8
%ptr1 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 1 %ptr1 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 1
▲ Show 20 Lines • Show All 194 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll

Show All 13 Lines
; We can't fold the SGPRs into v_cndmask_b32_e64, because it already ; We can't fold the SGPRs into v_cndmask_b32_e64, because it already
; uses an SGPR (implicit vcc). ; uses an SGPR (implicit vcc).
; GCN-LABEL: {{^}}sint_to_fp_i1_f64: ; GCN-LABEL: {{^}}sint_to_fp_i1_f64:
; VI-DAG: s_cmp_eq_u32 ; VI-DAG: s_cmp_eq_u32
; VI-DAG: s_cselect_b32 s[[SSEL:[0-9]+]], 0xbff00000, 0 ; VI-DAG: s_cselect_b32 s[[SSEL:[0-9]+]], 0xbff00000, 0
; VI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; VI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; VI-DAG: v_mov_b32_e32 v[[SEL:[0-9]+]], s[[SSEL]] ; VI-DAG: v_mov_b32_e32 v[[SEL:[0-9]+]], s[[SSEL]]
; VI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[ZERO]]:[[SEL]]{{\]}} ; VI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[ZERO]]:[[SEL]]]
; VI: s_endpgm ; VI: s_endpgm
; SI-DAG: s_cmp_eq_u32 ; SI-DAG: s_cmp_eq_u32
; SI-DAG: s_cselect_b64 vcc, -1, 0 ; SI-DAG: s_cselect_b64 vcc, -1, 0
; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}}, vcc ; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}}, vcc
; SI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; SI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; SI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[ZERO]]:[[SEL]]{{\]}} ; SI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[ZERO]]:[[SEL]]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @sint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) { define amdgpu_kernel void @sint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) {
%cmp = icmp eq i32 %in, 0 %cmp = icmp eq i32 %in, 0
%fp = sitofp i1 %cmp to double %fp = sitofp i1 %cmp to double
store double %fp, double addrspace(1)* %out, align 4 store double %fp, double addrspace(1)* %out, align 4
ret void ret void
} }
Show All 11 Lines
; GCN-LABEL: @s_sint_to_fp_i64_to_f64 ; GCN-LABEL: @s_sint_to_fp_i64_to_f64
define amdgpu_kernel void @s_sint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 %in) { define amdgpu_kernel void @s_sint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 %in) {
%result = sitofp i64 %in to double %result = sitofp i64 %in to double
store double %result, double addrspace(1)* %out store double %result, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: @v_sint_to_fp_i64_to_f64 ; GCN-LABEL: @v_sint_to_fp_i64_to_f64
; GCN: flat_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} ; GCN: flat_load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
; GCN-DAG: v_cvt_f64_i32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]] ; GCN-DAG: v_cvt_f64_i32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]]
; GCN-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]] ; GCN-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]]
; GCN-DAG: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32 ; GCN-DAG: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32
; GCN: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]] ; GCN: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]]
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
define amdgpu_kernel void @v_sint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) { define amdgpu_kernel void @v_sint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) {
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
%gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
Show All 29 Lines

llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_abs_v2i16_2(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %src) #0 {
%cond = icmp sgt <2 x i16> %val, %neg %cond = icmp sgt <2 x i16> %val, %neg
%res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg %res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg
%res2 = add <2 x i16> %res, %t1 %res2 = add <2 x i16> %res, %t1
store <2 x i16> %res2, <2 x i16> addrspace(1)* %out, align 4 store <2 x i16> %res2, <2 x i16> addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}s_abs_v4i16: ; GCN-LABEL: {{^}}s_abs_v4i16:
; GFX9: s_load_dwordx2 s{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}, s[0:1], 0x2c ; GFX9: s_load_dwordx2 s[[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]], s[0:1], 0x2c
; GFX9-DAG: v_pk_sub_i16 [[SUB0:v[0-9]+]], 0, s[[VAL0]] ; GFX9-DAG: v_pk_sub_i16 [[SUB0:v[0-9]+]], 0, s[[VAL0]]
; GFX9-DAG: v_pk_sub_i16 [[SUB1:v[0-9]+]], 0, s[[VAL1]] ; GFX9-DAG: v_pk_sub_i16 [[SUB1:v[0-9]+]], 0, s[[VAL1]]
; GFX9-DAG: v_pk_max_i16 [[MAX0:v[0-9]+]], s[[VAL0]], [[SUB0]] ; GFX9-DAG: v_pk_max_i16 [[MAX0:v[0-9]+]], s[[VAL0]], [[SUB0]]
; GFX9-DAG: v_pk_max_i16 [[MAX1:v[0-9]+]], s[[VAL1]], [[SUB1]] ; GFX9-DAG: v_pk_max_i16 [[MAX1:v[0-9]+]], s[[VAL1]], [[SUB1]]
; GFX9-DAG: v_pk_sub_u16 [[ADD0:v[0-9]+]], [[MAX0]], -2 op_sel_hi:[1,0] ; GFX9-DAG: v_pk_sub_u16 [[ADD0:v[0-9]+]], [[MAX0]], -2 op_sel_hi:[1,0]
; GFX9-DAG: v_pk_sub_u16 [[ADD1:v[0-9]+]], [[MAX1]], -2 op_sel_hi:[1,0] ; GFX9-DAG: v_pk_sub_u16 [[ADD1:v[0-9]+]], [[MAX1]], -2 op_sel_hi:[1,0]
define amdgpu_kernel void @s_abs_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %val) #0 { define amdgpu_kernel void @s_abs_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %val) #0 {
%z0 = insertelement <4 x i16> undef, i16 0, i16 0 %z0 = insertelement <4 x i16> undef, i16 0, i16 0
%z1 = insertelement <4 x i16> %z0, i16 0, i16 1 %z1 = insertelement <4 x i16> %z0, i16 0, i16 1
%z2 = insertelement <4 x i16> %z1, i16 0, i16 2 %z2 = insertelement <4 x i16> %z1, i16 0, i16 2
%z3 = insertelement <4 x i16> %z2, i16 0, i16 3 %z3 = insertelement <4 x i16> %z2, i16 0, i16 3
%t0 = insertelement <4 x i16> undef, i16 2, i16 0 %t0 = insertelement <4 x i16> undef, i16 2, i16 0
%t1 = insertelement <4 x i16> %t0, i16 2, i16 1 %t1 = insertelement <4 x i16> %t0, i16 2, i16 1
%t2 = insertelement <4 x i16> %t1, i16 2, i16 2 %t2 = insertelement <4 x i16> %t1, i16 2, i16 2
%t3 = insertelement <4 x i16> %t2, i16 2, i16 3 %t3 = insertelement <4 x i16> %t2, i16 2, i16 3
%neg = sub <4 x i16> %z3, %val %neg = sub <4 x i16> %z3, %val
%cond = icmp sgt <4 x i16> %val, %neg %cond = icmp sgt <4 x i16> %val, %neg
%res = select <4 x i1> %cond, <4 x i16> %val, <4 x i16> %neg %res = select <4 x i1> %cond, <4 x i16> %val, <4 x i16> %neg
%res2 = add <4 x i16> %res, %t3 %res2 = add <4 x i16> %res, %t3
store <4 x i16> %res2, <4 x i16> addrspace(1)* %out, align 4 store <4 x i16> %res2, <4 x i16> addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}v_abs_v4i16: ; GCN-LABEL: {{^}}v_abs_v4i16:
; GFX9: global_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}} ; GFX9: global_load_dwordx2 v[[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]]
; GFX9-DAG: v_pk_sub_i16 [[SUB0:v[0-9]+]], 0, v[[VAL0]] ; GFX9-DAG: v_pk_sub_i16 [[SUB0:v[0-9]+]], 0, v[[VAL0]]
; GFX9-DAG: v_pk_max_i16 [[MAX0:v[0-9]+]], v[[VAL0]], [[SUB0]] ; GFX9-DAG: v_pk_max_i16 [[MAX0:v[0-9]+]], v[[VAL0]], [[SUB0]]
; GFX9-DAG: v_pk_sub_u16 [[ADD0:v[0-9]+]], [[MAX0]], -2 op_sel_hi:[1,0] ; GFX9-DAG: v_pk_sub_u16 [[ADD0:v[0-9]+]], [[MAX0]], -2 op_sel_hi:[1,0]
; GFX9-DAG: v_pk_sub_i16 [[SUB1:v[0-9]+]], 0, v[[VAL1]] ; GFX9-DAG: v_pk_sub_i16 [[SUB1:v[0-9]+]], 0, v[[VAL1]]
; GFX9-DAG: v_pk_max_i16 [[MAX1:v[0-9]+]], v[[VAL1]], [[SUB1]] ; GFX9-DAG: v_pk_max_i16 [[MAX1:v[0-9]+]], v[[VAL1]], [[SUB1]]
; GFX9-DAG: v_pk_sub_u16 [[ADD1:v[0-9]+]], [[MAX1]], -2 op_sel_hi:[1,0] ; GFX9-DAG: v_pk_sub_u16 [[ADD1:v[0-9]+]], [[MAX1]], -2 op_sel_hi:[1,0]
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llvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll

; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
; GCN-LABEL: ; %bb.0: ; GCN-LABEL: ; %bb.0:
; GCN: s_load_dword s{{[0-9]+}}, s{{\[}}[[ADDR_LO:[0-9]+]]{{\:}}[[ADDR_HI:[0-9]+]]{{\]}}, 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[[[ADDR_LO:[0-9]+]]{{\:}}[[ADDR_HI:[0-9]+]]], 0x0
; GCN: s_waitcnt lgkmcnt(0) ; GCN: s_waitcnt lgkmcnt(0)
; GCN: global_store_dword v ; GCN: global_store_dword v
define amdgpu_kernel void @zot(i32 addrspace(1)* nocapture %arg, i64 addrspace(1)* nocapture %arg1) { define amdgpu_kernel void @zot(i32 addrspace(1)* nocapture %arg, i64 addrspace(1)* nocapture %arg1) {
bb: bb:
%tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp2 = icmp eq i32 %tmp, 0 %tmp2 = icmp eq i32 %tmp, 0
br i1 %tmp2, label %bb3, label %bb8 br i1 %tmp2, label %bb3, label %bb8
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llvm/test/CodeGen/AMDGPU/sopk-compares.ll

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endif: endif:
store volatile i32 1, i32 addrspace(1)* %out store volatile i32 1, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}br_scc_eq_i64_simm16: ; GCN-LABEL: {{^}}br_scc_eq_i64_simm16:
; VI-DAG: s_movk_i32 s[[K_LO:[0-9]+]], 0x4d2 ; VI-DAG: s_movk_i32 s[[K_LO:[0-9]+]], 0x4d2
; VI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 1 ; VI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 1
; VI: s_cmp_eq_u64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}} ; VI: s_cmp_eq_u64 s{{\[[0-9]+:[0-9]+\]}}, s[[[K_LO]]:[[K_HI]]]
; SI: v_cmp_eq_u64_e32 ; SI: v_cmp_eq_u64_e32
define amdgpu_kernel void @br_scc_eq_i64_simm16(i64 %cond, i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @br_scc_eq_i64_simm16(i64 %cond, i32 addrspace(1)* %out) #0 {
entry: entry:
%cmp0 = icmp eq i64 %cond, 4294968530 %cmp0 = icmp eq i64 %cond, 4294968530
br i1 %cmp0, label %endif, label %if br i1 %cmp0, label %endif, label %if
if: if:
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endif: endif:
store volatile i32 1, i32 addrspace(1)* %out store volatile i32 1, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}br_scc_ne_i64_simm16: ; GCN-LABEL: {{^}}br_scc_ne_i64_simm16:
; VI-DAG: s_movk_i32 s[[K_LO:[0-9]+]], 0x4d2 ; VI-DAG: s_movk_i32 s[[K_LO:[0-9]+]], 0x4d2
; VI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 1 ; VI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 1
; VI: s_cmp_lg_u64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}} ; VI: s_cmp_lg_u64 s{{\[[0-9]+:[0-9]+\]}}, s[[[K_LO]]:[[K_HI]]]
; SI: v_cmp_ne_u64_e32 ; SI: v_cmp_ne_u64_e32
define amdgpu_kernel void @br_scc_ne_i64_simm16(i64 %cond, i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @br_scc_ne_i64_simm16(i64 %cond, i32 addrspace(1)* %out) #0 {
entry: entry:
%cmp0 = icmp ne i64 %cond, 4294968530 %cmp0 = icmp ne i64 %cond, 4294968530
br i1 %cmp0, label %endif, label %if br i1 %cmp0, label %endif, label %if
if: if:
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llvm/test/CodeGen/AMDGPU/sub.i16.ll

Show First 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
} }
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
; GCN-LABEL: {{^}}v_test_sub_i16_zext_to_i64: ; GCN-LABEL: {{^}}v_test_sub_i16_zext_to_i64:
; VI: flat_load_ushort [[A:v[0-9]+]] ; VI: flat_load_ushort [[A:v[0-9]+]]
; VI: flat_load_ushort [[B:v[0-9]+]] ; VI: flat_load_ushort [[B:v[0-9]+]]
; VI: v_mov_b32_e32 v[[VZERO:[0-9]+]], 0 ; VI: v_mov_b32_e32 v[[VZERO:[0-9]+]], 0
; VI-DAG: v_sub_u16_e32 v[[ADD:[0-9]+]], [[A]], [[B]] ; VI-DAG: v_sub_u16_e32 v[[ADD:[0-9]+]], [[A]], [[B]]
; VI: buffer_store_dwordx2 v{{\[}}[[ADD]]:[[VZERO]]{{\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0{{$}} ; VI: buffer_store_dwordx2 v[[[ADD]]:[[VZERO]]], off, {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
define amdgpu_kernel void @v_test_sub_i16_zext_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 { define amdgpu_kernel void @v_test_sub_i16_zext_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds i64, i64 addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds i64, i64 addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
%gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid %gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid
%a = load volatile i16, i16 addrspace(1)* %gep.in0 %a = load volatile i16, i16 addrspace(1)* %gep.in0
%b = load volatile i16, i16 addrspace(1)* %gep.in1 %b = load volatile i16, i16 addrspace(1)* %gep.in1
%add = sub i16 %a, %b %add = sub i16 %a, %b
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; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
; GCN-LABEL: {{^}}v_test_sub_i16_sext_to_i64: ; GCN-LABEL: {{^}}v_test_sub_i16_sext_to_i64:
; VI: flat_load_ushort [[A:v[0-9]+]] ; VI: flat_load_ushort [[A:v[0-9]+]]
; VI: flat_load_ushort [[B:v[0-9]+]] ; VI: flat_load_ushort [[B:v[0-9]+]]
; VI: v_sub_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]] ; VI: v_sub_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
; VI-NEXT: v_bfe_i32 v[[LO:[0-9]+]], [[ADD]], 0, 16 ; VI-NEXT: v_bfe_i32 v[[LO:[0-9]+]], [[ADD]], 0, 16
; VI: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; VI: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; VI-NEXT: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; VI-NEXT: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
define amdgpu_kernel void @v_test_sub_i16_sext_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 { define amdgpu_kernel void @v_test_sub_i16_sext_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds i64, i64 addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds i64, i64 addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
%gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid %gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid
%a = load i16, i16 addrspace(1)* %gep.in0 %a = load i16, i16 addrspace(1)* %gep.in0
%b = load i16, i16 addrspace(1)* %gep.in1 %b = load i16, i16 addrspace(1)* %gep.in1
%add = sub i16 %a, %b %add = sub i16 %a, %b
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llvm/test/CodeGen/AMDGPU/sub.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX89 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX89 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX89 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX89 %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone speculatable declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone speculatable
; GCN-LABEL: {{^}}s_sub_i32: ; GCN-LABEL: {{^}}s_sub_i32:
; GCN: s_load_dwordx2 s{{\[}}[[A:[0-9]+]]:[[B:[0-9]+]]{{\]}} ; GCN: s_load_dwordx2 s[[[A:[0-9]+]]:[[B:[0-9]+]]]
; GCN: s_load_dwordx2 ; GCN: s_load_dwordx2
; GCN: s_sub_i32 s{{[0-9]+}}, s[[A]], s[[B]] ; GCN: s_sub_i32 s{{[0-9]+}}, s[[A]], s[[B]]
define amdgpu_kernel void @s_sub_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { define amdgpu_kernel void @s_sub_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
%result = sub i32 %a, %b %result = sub i32 %a, %b
store i32 %result, i32 addrspace(1)* %out store i32 %result, i32 addrspace(1)* %out
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/trunc.ll

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define amdgpu_kernel void @trunc_load_shl_i64(i32 addrspace(1)* %out, [8 x i32], i64 %a) { define amdgpu_kernel void @trunc_load_shl_i64(i32 addrspace(1)* %out, [8 x i32], i64 %a) {
%b = shl i64 %a, 2 %b = shl i64 %a, 2
%result = trunc i64 %b to i32 %result = trunc i64 %b to i32
store i32 %result, i32 addrspace(1)* %out, align 4 store i32 %result, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}trunc_shl_i64: ; GCN-LABEL: {{^}}trunc_shl_i64:
; SI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd ; SI: s_load_dwordx2 s[[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
; VI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34 ; VI: s_load_dwordx2 s[[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
; GCN: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2 ; GCN: s_lshl_b64 s[[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s[[[LO_SREG]]:{{[0-9]+\]}}, 2
; GCN: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]], ; GCN: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]],
; GCN: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]] ; GCN: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]
; SI: buffer_store_dword v[[LO_VREG]], ; SI: buffer_store_dword v[[LO_VREG]],
; VI: flat_store_dword v[{{[0-9:]+}}], v[[LO_VREG]] ; VI: flat_store_dword v[{{[0-9:]+}}], v[[LO_VREG]]
; GCN: v_mov_b32_e32 ; GCN: v_mov_b32_e32
; GCN: v_mov_b32_e32 ; GCN: v_mov_b32_e32
define amdgpu_kernel void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) { define amdgpu_kernel void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) {
%aa = add i64 %a, 234 ; Prevent shrinking store. %aa = add i64 %a, 234 ; Prevent shrinking store.
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define amdgpu_kernel void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) { define amdgpu_kernel void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) {
%trunc = trunc i32 %a to i1 %trunc = trunc i32 %a to i1
%result = select i1 %trunc, i32 1, i32 0 %result = select i1 %trunc, i32 1, i32 0
store i32 %result, i32 addrspace(1)* %out, align 4 store i32 %result, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}s_trunc_i64_to_i1: ; GCN-LABEL: {{^}}s_trunc_i64_to_i1:
; SI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x13 ; SI: s_load_dwordx2 s[[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x13
; VI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x4c ; VI: s_load_dwordx2 s[[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x4c
; GCN: s_bitcmp1_b32 s[[SLO]], 0 ; GCN: s_bitcmp1_b32 s[[SLO]], 0
; SI: s_cselect_b64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], -1, 0 ; SI: s_cselect_b64 s[[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], -1, 0
; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s{{\[}}[[VLO]]:[[VHI]]] ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s[[[VLO]]:[[VHI]]]
; VI: s_cselect_b32 {{s[0-9]+}}, 63, -12 ; VI: s_cselect_b32 {{s[0-9]+}}, 63, -12
define amdgpu_kernel void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, [8 x i32], i64 %x) { define amdgpu_kernel void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, [8 x i32], i64 %x) {
%trunc = trunc i64 %x to i1 %trunc = trunc i64 %x to i1
%sel = select i1 %trunc, i32 63, i32 -12 %sel = select i1 %trunc, i32 63, i32 -12
store i32 %sel, i32 addrspace(1)* %out store i32 %sel, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_trunc_i64_to_i1: ; GCN-LABEL: {{^}}v_trunc_i64_to_i1:
; SI: buffer_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}} ; SI: buffer_load_dwordx2 v[[[VLO:[0-9]+]]:{{[0-9]+\]}}
; VI: flat_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}} ; VI: flat_load_dwordx2 v[[[VLO:[0-9]+]]:{{[0-9]+\]}}
; GCN: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]] ; GCN: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]
; GCN: v_cmp_eq_u32_e32 vcc, 1, [[MASKED]] ; GCN: v_cmp_eq_u32_e32 vcc, 1, [[MASKED]]
; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc ; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc
define amdgpu_kernel void @v_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 addrspace(1)* %in) { define amdgpu_kernel void @v_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 addrspace(1)* %in) {
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
%gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
%x = load i64, i64 addrspace(1)* %gep %x = load i64, i64 addrspace(1)* %gep
%trunc = trunc i64 %x to i1 %trunc = trunc i64 %x to i1
%sel = select i1 %trunc, i32 63, i32 -12 %sel = select i1 %trunc, i32 63, i32 -12
store i32 %sel, i32 addrspace(1)* %out.gep store i32 %sel, i32 addrspace(1)* %out.gep
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
; GCN-LABEL: {{^}}v_uint_to_fp_i64_to_f64 ; GCN-LABEL: {{^}}v_uint_to_fp_i64_to_f64
; GCN: flat_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} ; GCN: flat_load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
; GCN-DAG: v_cvt_f64_u32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]] ; GCN-DAG: v_cvt_f64_u32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]]
; GCN-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]] ; GCN-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]]
; GCN-DAG: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32 ; GCN-DAG: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32
; GCN: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]] ; GCN: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]]
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
define amdgpu_kernel void @v_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) { define amdgpu_kernel void @v_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) {
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
%gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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; GCN-LABEL: {{^}}uint_to_fp_i1_to_f64: ; GCN-LABEL: {{^}}uint_to_fp_i1_to_f64:
; VI-DAG: s_cmp_eq_u32 ; VI-DAG: s_cmp_eq_u32
; VI-DAG: s_cselect_b32 s[[SSEL:[0-9]+]], 0x3ff00000, 0 ; VI-DAG: s_cselect_b32 s[[SSEL:[0-9]+]], 0x3ff00000, 0
; VI-DAG: v_mov_b32_e32 v[[SEL:[0-9]+]], s[[SSEL]] ; VI-DAG: v_mov_b32_e32 v[[SEL:[0-9]+]], s[[SSEL]]
; SI-DAG: s_cmp_eq_u32 ; SI-DAG: s_cmp_eq_u32
; SI-DAG: s_cselect_b64 vcc, -1, 0 ; SI-DAG: s_cselect_b64 vcc, -1, 0
; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, {{v[0-9]+}}, vcc ; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, {{v[0-9]+}}, vcc
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[ZERO]]:[[SEL]]{{\]}} ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[ZERO]]:[[SEL]]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @uint_to_fp_i1_to_f64(double addrspace(1)* %out, i32 %in) { define amdgpu_kernel void @uint_to_fp_i1_to_f64(double addrspace(1)* %out, i32 %in) {
%cmp = icmp eq i32 %in, 0 %cmp = icmp eq i32 %in, 0
%fp = uitofp i1 %cmp to double %fp = uitofp i1 %cmp to double
store double %fp, double addrspace(1)* %out, align 4 store double %fp, double addrspace(1)* %out, align 4
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll

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; SI: buffer_store_byte ; SI: buffer_store_byte
define amdgpu_kernel void @constant_align2_load_i8(i8 addrspace(4)* %p, i8 addrspace(1)* %r) #0 { define amdgpu_kernel void @constant_align2_load_i8(i8 addrspace(4)* %p, i8 addrspace(1)* %r) #0 {
%v = load i8, i8 addrspace(4)* %p, align 2 %v = load i8, i8 addrspace(4)* %p, align 2
store i8 %v, i8 addrspace(1)* %r, align 2 store i8 %v, i8 addrspace(1)* %r, align 2
ret void ret void
} }
; SI-LABEL: {{^}}constant_align4_merge_load_2_i32: ; SI-LABEL: {{^}}constant_align4_merge_load_2_i32:
; SI: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}} ; SI: s_load_dwordx2 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[LO]] ; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[LO]]
; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[HI]] ; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[HI]]
; SI: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} ; SI: buffer_store_dwordx2 v[[[VLO]]:[[VHI]]]
define amdgpu_kernel void @constant_align4_merge_load_2_i32(i32 addrspace(4)* %p, i32 addrspace(1)* %r) #0 { define amdgpu_kernel void @constant_align4_merge_load_2_i32(i32 addrspace(4)* %p, i32 addrspace(1)* %r) #0 {
%gep0 = getelementptr i32, i32 addrspace(4)* %p, i64 1 %gep0 = getelementptr i32, i32 addrspace(4)* %p, i64 1
%v0 = load i32, i32 addrspace(4)* %p, align 4 %v0 = load i32, i32 addrspace(4)* %p, align 4
%v1 = load i32, i32 addrspace(4)* %gep0, align 4 %v1 = load i32, i32 addrspace(4)* %gep0, align 4
%gep1 = getelementptr i32, i32 addrspace(1)* %r, i64 1 %gep1 = getelementptr i32, i32 addrspace(1)* %r, i64 1
store i32 %v0, i32 addrspace(1)* %r, align 4 store i32 %v0, i32 addrspace(1)* %r, align 4
store i32 %v1, i32 addrspace(1)* %gep1, align 4 store i32 %v1, i32 addrspace(1)* %gep1, align 4
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llvm/test/CodeGen/AMDGPU/uniform-cfg.ll

Show First 20 Lines • Show All 242 Lines • ▼ Show 20 LinesIF:
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
br label %ENDIF br label %ENDIF
ENDIF: ; preds = %IF, %main_body ENDIF: ; preds = %IF, %main_body
ret void ret void
} }
; GCN-LABEL: {{^}}icmp_users_different_blocks: ; GCN-LABEL: {{^}}icmp_users_different_blocks:
; GCN: s_load_dwordx2 s{{\[}}[[COND0:[0-9]+]]:[[COND1:[0-9]+]]{{\]}} ; GCN: s_load_dwordx2 s[[[COND0:[0-9]+]]:[[COND1:[0-9]+]]]
; GCN: s_cmp_lt_i32 s[[COND0]], 1 ; GCN: s_cmp_lt_i32 s[[COND0]], 1
; GCN: s_cbranch_scc1 [[EXIT:.L[0-9_A-Za-z]+]] ; GCN: s_cbranch_scc1 [[EXIT:.L[0-9_A-Za-z]+]]
; GCN: s_cmp_gt_i32 s[[COND1]], 0{{$}} ; GCN: s_cmp_gt_i32 s[[COND1]], 0{{$}}
; GCN: s_cbranch_vccz [[BODY:.L[0-9_A-Za-z]+]] ; GCN: s_cbranch_vccz [[BODY:.L[0-9_A-Za-z]+]]
; GCN: {{^}}[[EXIT]]: ; GCN: {{^}}[[EXIT]]:
; GCN: s_endpgm ; GCN: s_endpgm
; GCN: {{^}}[[BODY]]: ; GCN: {{^}}[[BODY]]:
; GCN: buffer_store ; GCN: buffer_store
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llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll

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; GCN: buffer_store_dword [[RESULT]] ; GCN: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @test_sgpr_use_three_ternary_op(float addrspace(1)* %out, float %a) #0 { define amdgpu_kernel void @test_sgpr_use_three_ternary_op(float addrspace(1)* %out, float %a) #0 {
%fma = call float @llvm.fma.f32(float %a, float %a, float %a) #1 %fma = call float @llvm.fma.f32(float %a, float %a, float %a) #1
store float %fma, float addrspace(1)* %out, align 4 store float %fma, float addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_b: ; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_b:
; SI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SI-DAG: s_load_dwordx2 s[[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
; VI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c ; VI-DAG: s_load_dwordx2 s[[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]] ; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]]
; GCN: v_fma_f32 [[RESULT:v[0-9]+]], s[[SGPR0]], s[[SGPR0]], [[VGPR1]] ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], s[[SGPR0]], s[[SGPR0]], [[VGPR1]]
; GCN: buffer_store_dword [[RESULT]] ; GCN: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_a_b(float addrspace(1)* %out, float %a, float %b) #0 { define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_a_b(float addrspace(1)* %out, float %a, float %b) #0 {
%fma = call float @llvm.fma.f32(float %a, float %a, float %b) #1 %fma = call float @llvm.fma.f32(float %a, float %a, float %b) #1
store float %fma, float addrspace(1)* %out, align 4 store float %fma, float addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}test_use_s_v_s: ; GCN-LABEL: {{^}}test_use_s_v_s:
; SI: s_load_dwordx2 s{{\[}}[[SA:[0-9]+]]:[[SB:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} ; SI: s_load_dwordx2 s[[[SA:[0-9]+]]:[[SB:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
; SI: buffer_load_dword [[VA0:v[0-9]+]] ; SI: buffer_load_dword [[VA0:v[0-9]+]]
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_dword [[VA1:v[0-9]+]] ; SI-NEXT: buffer_load_dword [[VA1:v[0-9]+]]
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOT: v_mov_b32 ; GCN-NOT: v_mov_b32
; VI: buffer_load_dword [[VA0:v[0-9]+]] ; VI: buffer_load_dword [[VA0:v[0-9]+]]
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_dword [[VA1:v[0-9]+]] ; VI-NEXT: buffer_load_dword [[VA1:v[0-9]+]]
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI: s_load_dwordx2 s{{\[}}[[SA:[0-9]+]]:[[SB:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} ; VI: s_load_dwordx2 s[[[SA:[0-9]+]]:[[SB:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
; GCN-NOT: v_mov_b32 ; GCN-NOT: v_mov_b32
; GCN: v_mov_b32_e32 [[VB:v[0-9]+]], s[[SB]] ; GCN: v_mov_b32_e32 [[VB:v[0-9]+]], s[[SB]]
; GCN-NOT: v_mov_b32 ; GCN-NOT: v_mov_b32
; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], s[[SA]], [[VA0]], [[VB]] ; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], s[[SA]], [[VA0]], [[VB]]
; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], s[[SA]], [[VA1]], [[VB]] ; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], s[[SA]], [[VA1]], [[VB]]
; GCN: buffer_store_dword [[RESULT0]] ; GCN: buffer_store_dword [[RESULT0]]
; GCN: buffer_store_dword [[RESULT1]] ; GCN: buffer_store_dword [[RESULT1]]
define amdgpu_kernel void @test_use_s_v_s(float addrspace(1)* %out, float %a, float %b, float addrspace(1)* %in) #0 { define amdgpu_kernel void @test_use_s_v_s(float addrspace(1)* %out, float %a, float %b, float addrspace(1)* %in) #0 {
%va0 = load volatile float, float addrspace(1)* %in %va0 = load volatile float, float addrspace(1)* %in
%va1 = load volatile float, float addrspace(1)* %in %va1 = load volatile float, float addrspace(1)* %in
%fma0 = call float @llvm.fma.f32(float %a, float %va0, float %b) #1 %fma0 = call float @llvm.fma.f32(float %a, float %va0, float %b) #1
%fma1 = call float @llvm.fma.f32(float %a, float %va1, float %b) #1 %fma1 = call float @llvm.fma.f32(float %a, float %va1, float %b) #1
store volatile float %fma0, float addrspace(1)* %out store volatile float %fma0, float addrspace(1)* %out
store volatile float %fma1, float addrspace(1)* %out store volatile float %fma1, float addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_b_a: ; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_b_a:
; SI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SI-DAG: s_load_dwordx2 s[[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
; VI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c ; VI-DAG: s_load_dwordx2 s[[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]] ; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]]
; GCN: v_fma_f32 [[RESULT:v[0-9]+]], s[[SGPR0]], [[VGPR1]], s[[SGPR0]] ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], s[[SGPR0]], [[VGPR1]], s[[SGPR0]]
; GCN: buffer_store_dword [[RESULT]] ; GCN: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_b_a(float addrspace(1)* %out, float %a, float %b) #0 { define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_b_a(float addrspace(1)* %out, float %a, float %b) #0 {
%fma = call float @llvm.fma.f32(float %a, float %b, float %a) #1 %fma = call float @llvm.fma.f32(float %a, float %b, float %a) #1
store float %fma, float addrspace(1)* %out, align 4 store float %fma, float addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_b_a_a: ; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_b_a_a:
; SI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SI-DAG: s_load_dwordx2 s[[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
; VI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c ; VI-DAG: s_load_dwordx2 s[[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]] ; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]]
; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], s[[SGPR0]], s[[SGPR0]] ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], s[[SGPR0]], s[[SGPR0]]
; GCN: buffer_store_dword [[RESULT]] ; GCN: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_b_a_a(float addrspace(1)* %out, float %a, float %b) #0 { define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_b_a_a(float addrspace(1)* %out, float %a, float %b) #0 {
%fma = call float @llvm.fma.f32(float %b, float %a, float %a) #1 %fma = call float @llvm.fma.f32(float %b, float %a, float %a) #1
store float %fma, float addrspace(1)* %out, align 4 store float %fma, float addrspace(1)* %out, align 4
ret void ret void
} }
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; GCN: buffer_store_dword [[RESULT0]] ; GCN: buffer_store_dword [[RESULT0]]
define amdgpu_kernel void @test_literal_use_twice_ternary_op_k_k_s(float addrspace(1)* %out, float %a) #0 { define amdgpu_kernel void @test_literal_use_twice_ternary_op_k_k_s(float addrspace(1)* %out, float %a) #0 {
%fma = call float @llvm.fma.f32(float 1024.0, float 1024.0, float %a) #1 %fma = call float @llvm.fma.f32(float 1024.0, float 1024.0, float %a) #1
store float %fma, float addrspace(1)* %out store float %fma, float addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_k_k_s_x2: ; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_k_k_s_x2:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]{{\:}}[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} ; GCN-DAG: s_load_dwordx2 s[[[SGPR0:[0-9]+]]{{\:}}[[SGPR1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[SGPR0]] ; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[SGPR0]]
; GCN-DAG: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]] ; GCN-DAG: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]]
; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000 ; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000
; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[SK]], [[SK]], [[VGPR0]] ; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[SK]], [[SK]], [[VGPR0]]
; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[SK]], [[SK]], [[VGPR1]] ; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[SK]], [[SK]], [[VGPR1]]
; GCN: buffer_store_dword [[RESULT0]] ; GCN: buffer_store_dword [[RESULT0]]
; GCN: buffer_store_dword [[RESULT1]] ; GCN: buffer_store_dword [[RESULT1]]
; GCN: s_endpgm ; GCN: s_endpgm
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; GCN: buffer_store_dword [[RESULT]] ; GCN: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @test_literal_use_twice_ternary_op_k_s_k(float addrspace(1)* %out, float %a) #0 { define amdgpu_kernel void @test_literal_use_twice_ternary_op_k_s_k(float addrspace(1)* %out, float %a) #0 {
%fma = call float @llvm.fma.f32(float 1024.0, float %a, float 1024.0) #1 %fma = call float @llvm.fma.f32(float 1024.0, float %a, float 1024.0) #1
store float %fma, float addrspace(1)* %out store float %fma, float addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_k_s_k_x2: ; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_k_s_k_x2:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]{{\:}}[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} ; GCN-DAG: s_load_dwordx2 s[[[SGPR0:[0-9]+]]{{\:}}[[SGPR1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[SGPR0]] ; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[SGPR0]]
; GCN-DAG: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]] ; GCN-DAG: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]]
; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000 ; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000
; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[VGPR0]], [[SK]], [[SK]] ; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[VGPR0]], [[SK]], [[SK]]
; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[VGPR1]], [[SK]], [[SK]] ; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[VGPR1]], [[SK]], [[SK]]
; GCN: buffer_store_dword [[RESULT0]] ; GCN: buffer_store_dword [[RESULT0]]
; GCN: buffer_store_dword [[RESULT1]] ; GCN: buffer_store_dword [[RESULT1]]
; GCN: s_endpgm ; GCN: s_endpgm
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; GCN: buffer_store_dword [[RESULT]] ; GCN: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @test_literal_use_twice_ternary_op_s_k_k(float addrspace(1)* %out, float %a) #0 { define amdgpu_kernel void @test_literal_use_twice_ternary_op_s_k_k(float addrspace(1)* %out, float %a) #0 {
%fma = call float @llvm.fma.f32(float %a, float 1024.0, float 1024.0) #1 %fma = call float @llvm.fma.f32(float %a, float 1024.0, float 1024.0) #1
store float %fma, float addrspace(1)* %out store float %fma, float addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_s_k_k_x2: ; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_s_k_k_x2:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]{{\:}}[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} ; GCN-DAG: s_load_dwordx2 s[[[SGPR0:[0-9]+]]{{\:}}[[SGPR1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[SGPR0]] ; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[SGPR0]]
; GCN-DAG: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]] ; GCN-DAG: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]]
; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000 ; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000
; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[VGPR0]], [[SK]], [[SK]] ; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[VGPR0]], [[SK]], [[SK]]
; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[VGPR1]], [[SK]], [[SK]] ; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[VGPR1]], [[SK]], [[SK]]
; GCN: buffer_store_dword [[RESULT0]] ; GCN: buffer_store_dword [[RESULT0]]
; GCN: buffer_store_dword [[RESULT1]] ; GCN: buffer_store_dword [[RESULT1]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @test_literal_use_twice_ternary_op_s_k_k_x2(float addrspace(1)* %out, float %a, float %b) #0 { define amdgpu_kernel void @test_literal_use_twice_ternary_op_s_k_k_x2(float addrspace(1)* %out, float %a, float %b) #0 {
%fma0 = call float @llvm.fma.f32(float %a, float 1024.0, float 1024.0) #1 %fma0 = call float @llvm.fma.f32(float %a, float 1024.0, float 1024.0) #1
%fma1 = call float @llvm.fma.f32(float %b, float 1024.0, float 1024.0) #1 %fma1 = call float @llvm.fma.f32(float %b, float 1024.0, float 1024.0) #1
store volatile float %fma0, float addrspace(1)* %out store volatile float %fma0, float addrspace(1)* %out
store volatile float %fma1, float addrspace(1)* %out store volatile float %fma1, float addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_s0_s1_k_f32: ; GCN-LABEL: {{^}}test_s0_s1_k_f32:
; SI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SI-DAG: s_load_dwordx2 s[[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
; VI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c ; VI-DAG: s_load_dwordx2 s[[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
; GCN-DAG: v_mov_b32_e32 [[VK0:v[0-9]+]], 0x44800000 ; GCN-DAG: v_mov_b32_e32 [[VK0:v[0-9]+]], 0x44800000
; GCN-DAG: v_mov_b32_e32 [[VS1:v[0-9]+]], s[[SGPR1]] ; GCN-DAG: v_mov_b32_e32 [[VS1:v[0-9]+]], s[[SGPR1]]
; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], s[[SGPR0]], [[VS1]], [[VK0]] ; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], s[[SGPR0]], [[VS1]], [[VK0]]
; GCN-DAG: v_mov_b32_e32 [[VK1:v[0-9]+]], 0x45800000 ; GCN-DAG: v_mov_b32_e32 [[VK1:v[0-9]+]], 0x45800000
; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], s[[SGPR0]], [[VS1]], [[VK1]] ; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], s[[SGPR0]], [[VS1]], [[VK1]]
; GCN: buffer_store_dword [[RESULT0]] ; GCN: buffer_store_dword [[RESULT0]]
; GCN: buffer_store_dword [[RESULT1]] ; GCN: buffer_store_dword [[RESULT1]]
define amdgpu_kernel void @test_s0_s1_k_f32(float addrspace(1)* %out, float %a, float %b) #0 { define amdgpu_kernel void @test_s0_s1_k_f32(float addrspace(1)* %out, float %a, float %b) #0 {
%fma0 = call float @llvm.fma.f32(float %a, float %b, float 1024.0) #1 %fma0 = call float @llvm.fma.f32(float %a, float %b, float 1024.0) #1
%fma1 = call float @llvm.fma.f32(float %a, float %b, float 4096.0) #1 %fma1 = call float @llvm.fma.f32(float %a, float %b, float 4096.0) #1
store volatile float %fma0, float addrspace(1)* %out store volatile float %fma0, float addrspace(1)* %out
store volatile float %fma1, float addrspace(1)* %out store volatile float %fma1, float addrspace(1)* %out
ret void ret void
} }
; FIXME: Immediate in SGPRs just copied to VGPRs ; FIXME: Immediate in SGPRs just copied to VGPRs
; GCN-LABEL: {{^}}test_s0_s1_k_f64: ; GCN-LABEL: {{^}}test_s0_s1_k_f64:
; GCN-DAG: s_load_dwordx2 [[SGPR0:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}} ; GCN-DAG: s_load_dwordx2 [[SGPR0:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
; GCN-DAG: s_load_dwordx2 s{{\[}}[[SGPR1_SUB0:[0-9]+]]:[[SGPR1_SUB1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x1d|0x74}} ; GCN-DAG: s_load_dwordx2 s[[[SGPR1_SUB0:[0-9]+]]:[[SGPR1_SUB1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x1d|0x74}}
; GCN-DAG: v_mov_b32_e32 v[[VK0_SUB1:[0-9]+]], 0x40900000 ; GCN-DAG: v_mov_b32_e32 v[[VK0_SUB1:[0-9]+]], 0x40900000
; GCN-DAG: v_mov_b32_e32 v[[VZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[VZERO:[0-9]+]], 0{{$}}
; GCN-DAG: v_mov_b32_e32 v[[VS1_SUB0:[0-9]+]], s[[SGPR1_SUB0]] ; GCN-DAG: v_mov_b32_e32 v[[VS1_SUB0:[0-9]+]], s[[SGPR1_SUB0]]
; GCN-DAG: v_mov_b32_e32 v[[VS1_SUB1:[0-9]+]], s[[SGPR1_SUB1]] ; GCN-DAG: v_mov_b32_e32 v[[VS1_SUB1:[0-9]+]], s[[SGPR1_SUB1]]
; GCN: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[SGPR0]], v{{\[}}[[VS1_SUB0]]:[[VS1_SUB1]]{{\]}}, v{{\[}}[[VZERO]]:[[VK0_SUB1]]{{\]}} ; GCN: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[SGPR0]], v[[[VS1_SUB0]]:[[VS1_SUB1]]], v[[[VZERO]]:[[VK0_SUB1]]]
; Same zero component is re-used for half of each immediate. ; Same zero component is re-used for half of each immediate.
; GCN: v_mov_b32_e32 v[[VK1_SUB1:[0-9]+]], 0x40b00000 ; GCN: v_mov_b32_e32 v[[VK1_SUB1:[0-9]+]], 0x40b00000
; GCN: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[SGPR0]], v{{\[}}[[VS1_SUB0]]:[[VS1_SUB1]]{{\]}}, v{{\[}}[[VZERO]]:[[VK1_SUB1]]{{\]}} ; GCN: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[SGPR0]], v[[[VS1_SUB0]]:[[VS1_SUB1]]], v[[[VZERO]]:[[VK1_SUB1]]]
; GCN: buffer_store_dwordx2 [[RESULT0]] ; GCN: buffer_store_dwordx2 [[RESULT0]]
; GCN: buffer_store_dwordx2 [[RESULT1]] ; GCN: buffer_store_dwordx2 [[RESULT1]]
define amdgpu_kernel void @test_s0_s1_k_f64(double addrspace(1)* %out, [8 x i32], double %a, [8 x i32], double %b) #0 { define amdgpu_kernel void @test_s0_s1_k_f64(double addrspace(1)* %out, [8 x i32], double %a, [8 x i32], double %b) #0 {
%fma0 = call double @llvm.fma.f64(double %a, double %b, double 1024.0) #1 %fma0 = call double @llvm.fma.f64(double %a, double %b, double 1024.0) #1
%fma1 = call double @llvm.fma.f64(double %a, double %b, double 4096.0) #1 %fma1 = call double @llvm.fma.f64(double %a, double %b, double 4096.0) #1
store volatile double %fma0, double addrspace(1)* %out store volatile double %fma0, double addrspace(1)* %out
store volatile double %fma1, double addrspace(1)* %out store volatile double %fma1, double addrspace(1)* %out
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

llvm/test/CodeGen/AMDGPU/v_cndmask.ll

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_cnd_nan(float addrspace(1)* %out, i32 %c, float %f) #0 {
ret void ret void
} }
; Test different compare and select operand types for optimal code ; Test different compare and select operand types for optimal code
; shrinking. ; shrinking.
; (select (cmp (sgprX, constant)), constant, sgprZ) ; (select (cmp (sgprX, constant)), constant, sgprZ)
; GCN-LABEL: {{^}}fcmp_sgprX_k0_select_k1_sgprZ_f32: ; GCN-LABEL: {{^}}fcmp_sgprX_k0_select_k1_sgprZ_f32:
; GCN: s_load_dwordx2 s{{\[}}[[X:[0-9]+]]:[[Z:[0-9]+]]{{\]}}, s[0:1], {{0x4c|0x13}} ; GCN: s_load_dwordx2 s[[[X:[0-9]+]]:[[Z:[0-9]+]]], s[0:1], {{0x4c|0x13}}
; SIVI-DAG: v_cmp_nlg_f32_e64 [[CC:vcc]], s[[X]], 0 ; SIVI-DAG: v_cmp_nlg_f32_e64 [[CC:vcc]], s[[X]], 0
; GFX10-DAG: v_cmp_nlg_f32_e64 [[CC:s\[[0-9:]+\]]], s[[X]], 0 ; GFX10-DAG: v_cmp_nlg_f32_e64 [[CC:s\[[0-9:]+\]]], s[[X]], 0
; SIVI-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], s[[Z]] ; SIVI-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], s[[Z]]
; SIVI: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[VZ]], [[CC]] ; SIVI: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[VZ]], [[CC]]
; GFX10: v_cndmask_b32_e64 v{{[0-9]+}}, 1.0, s[[Z]], [[CC]] ; GFX10: v_cndmask_b32_e64 v{{[0-9]+}}, 1.0, s[[Z]], [[CC]]
define amdgpu_kernel void @fcmp_sgprX_k0_select_k1_sgprZ_f32(float addrspace(1)* %out, [8 x i32], float %x, float %z) #0 { define amdgpu_kernel void @fcmp_sgprX_k0_select_k1_sgprZ_f32(float addrspace(1)* %out, [8 x i32], float %x, float %z) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
Show All 18 Linesdefine amdgpu_kernel void @fcmp_sgprX_k0_select_k1_sgprX_f32(float addrspace(1)* %out, float %x) #0 {
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%setcc = fcmp one float %x, 0.0 %setcc = fcmp one float %x, 0.0
%select = select i1 %setcc, float 1.0, float %x %select = select i1 %setcc, float 1.0, float %x
store float %select, float addrspace(1)* %out.gep store float %select, float addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}fcmp_sgprX_k0_select_k0_sgprZ_f32: ; GCN-LABEL: {{^}}fcmp_sgprX_k0_select_k0_sgprZ_f32:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[X:[0-9]+]]:[[Z:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}} ; GCN-DAG: s_load_dwordx2 s[[[X:[0-9]+]]:[[Z:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
; SIVI-DAG: v_cmp_nlg_f32_e64 [[CC:vcc]], s[[X]], 0 ; SIVI-DAG: v_cmp_nlg_f32_e64 [[CC:vcc]], s[[X]], 0
; GFX10-DAG: v_cmp_nlg_f32_e64 [[CC:s\[[0-9:]+\]]], s[[X]], 0 ; GFX10-DAG: v_cmp_nlg_f32_e64 [[CC:s\[[0-9:]+\]]], s[[X]], 0
; SIVI-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], s[[Z]] ; SIVI-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], s[[Z]]
; SIVI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, [[VZ]], [[CC]] ; SIVI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, [[VZ]], [[CC]]
; GFX10: v_cndmask_b32_e64 v{{[0-9]+}}, 0, s[[Z]], [[CC]] ; GFX10: v_cndmask_b32_e64 v{{[0-9]+}}, 0, s[[Z]], [[CC]]
define amdgpu_kernel void @fcmp_sgprX_k0_select_k0_sgprZ_f32(float addrspace(1)* %out, [8 x i32], float %x, float %z) #0 { define amdgpu_kernel void @fcmp_sgprX_k0_select_k0_sgprZ_f32(float addrspace(1)* %out, [8 x i32], float %x, float %z) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @icmp_vgprX_k0_select_k1_vgprZ_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %x.ptr, i32 addrspace(1)* %z.ptr) #0 {
%z = load volatile i32, i32 addrspace(1)* %z.gep %z = load volatile i32, i32 addrspace(1)* %z.gep
%setcc = icmp slt i32 %x, 0 %setcc = icmp slt i32 %x, 0
%select = select i1 %setcc, i32 2, i32 %z %select = select i1 %setcc, i32 2, i32 %z
store i32 %select, i32 addrspace(1)* %out.gep store i32 %select, i32 addrspace(1)* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}icmp_vgprX_k0_select_k1_vgprZ_i64: ; GCN-LABEL: {{^}}icmp_vgprX_k0_select_k1_vgprZ_i64:
; GCN: {{buffer|flat|global}}_load_dwordx2 v{{\[}}[[X_LO:[0-9]+]]:[[X_HI:[0-9]+]]{{\]}} ; GCN: {{buffer|flat|global}}_load_dwordx2 v[[[X_LO:[0-9]+]]:[[X_HI:[0-9]+]]]
; GCN-DAG: {{buffer|flat|global}}_load_dwordx2 v{{\[}}[[Z_LO:[0-9]+]]:[[Z_HI:[0-9]+]]{{\]}} ; GCN-DAG: {{buffer|flat|global}}_load_dwordx2 v[[[Z_LO:[0-9]+]]:[[Z_HI:[0-9]+]]]
; GCN-DAG: v_cmp_lt_i64_e32 vcc, -1, v{{\[}}[[X_LO]]:[[X_HI]]{{\]}} ; GCN-DAG: v_cmp_lt_i64_e32 vcc, -1, v[[[X_LO]]:[[X_HI]]]
; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v[[Z_HI]], vcc ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v[[Z_HI]], vcc
; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 2, v[[Z_LO]], vcc ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 2, v[[Z_LO]], vcc
define amdgpu_kernel void @icmp_vgprX_k0_select_k1_vgprZ_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %x.ptr, i64 addrspace(1)* %z.ptr) #0 { define amdgpu_kernel void @icmp_vgprX_k0_select_k1_vgprZ_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %x.ptr, i64 addrspace(1)* %z.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%x.gep = getelementptr inbounds i64, i64 addrspace(1)* %x.ptr, i64 %tid.ext %x.gep = getelementptr inbounds i64, i64 addrspace(1)* %x.ptr, i64 %tid.ext
%z.gep = getelementptr inbounds i64, i64 addrspace(1)* %z.ptr, i64 %tid.ext %z.gep = getelementptr inbounds i64, i64 addrspace(1)* %z.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds i64, i64 addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds i64, i64 addrspace(1)* %out, i64 %tid.ext
▲ Show 20 Lines • Show All 241 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/vectorize-loads.ll

Show All 19 Linesentry:
%conv = zext i16 %add to i32 %conv = zext i16 %add to i32
store i32 %conv, i32 addrspace(1)* %out, align 4 store i32 %conv, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; A little more complicated case where more sub-dword loads could be coalesced ; A little more complicated case where more sub-dword loads could be coalesced
; if they are not widening earlier. ; if they are not widening earlier.
; GCN-LABEL: {{^}}load_4i16: ; GCN-LABEL: {{^}}load_4i16:
; GCN: s_load_dwordx2 s{{\[}}[[D0:[0-9]+]]:[[D1:[0-9]+]]{{\]}}, s[4:5], 0x4 ; GCN: s_load_dwordx2 s[[[D0:[0-9]+]]:[[D1:[0-9]+]]], s[4:5], 0x4
; GCN-NOT: s_load_dword {{s[0-9]+}}, s[4:5], 0x4 ; GCN-NOT: s_load_dword {{s[0-9]+}}, s[4:5], 0x4
; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s[[D0]], 16 ; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s[[D0]], 16
; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s[[D1]], 16 ; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s[[D1]], 16
; GCN: s_endpgm ; GCN: s_endpgm
define protected amdgpu_kernel void @load_4i16(i32 addrspace(1)* %out) { define protected amdgpu_kernel void @load_4i16(i32 addrspace(1)* %out) {
entry: entry:
%disp = tail call align 4 dereferenceable(64) i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() %disp = tail call align 4 dereferenceable(64) i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
%gep_x = getelementptr i8, i8 addrspace(4)* %disp, i64 4 %gep_x = getelementptr i8, i8 addrspace(4)* %disp, i64 4
Show All 22 Lines

llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll

Show All 16 Lines
; GCN-DAG: s_mov_b32 s[[DESC0:[0-9]+]], SCRATCH_RSRC_DWORD0 ; GCN-DAG: s_mov_b32 s[[DESC0:[0-9]+]], SCRATCH_RSRC_DWORD0
; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
; GCN-DAG: s_mov_b32 s{{[0-9]+}}, -1 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, -1
; SI-DAG: s_mov_b32 s[[DESC3:[0-9]+]], 0xe8f000 ; SI-DAG: s_mov_b32 s[[DESC3:[0-9]+]], 0xe8f000
; VI-DAG: s_mov_b32 s[[DESC3:[0-9]+]], 0xe80000 ; VI-DAG: s_mov_b32 s[[DESC3:[0-9]+]], 0xe80000
; GFX9-DAG: s_mov_b32 s[[DESC3:[0-9]+]], 0xe00000 ; GFX9-DAG: s_mov_b32 s[[DESC3:[0-9]+]], 0xe00000
; OFFREG is offset system SGPR ; OFFREG is offset system SGPR
; GCN: buffer_store_dword {{v[0-9]+}}, off, s{{\[}}[[DESC0]]:[[DESC3]]], 0 offset:{{[0-9]+}} ; 4-byte Folded Spill ; GCN: buffer_store_dword {{v[0-9]+}}, off, s[[[DESC0]]:[[DESC3]]], 0 offset:{{[0-9]+}} ; 4-byte Folded Spill
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[}}[[DESC0]]:[[DESC3]]], 0 offset:{{[0-9]+}} ; 4-byte Folded Reload ; GCN: buffer_load_dword v{{[0-9]+}}, off, s[[[DESC0]]:[[DESC3]]], 0 offset:{{[0-9]+}} ; 4-byte Folded Reload
; GCN: NumVgprs: 256 ; GCN: NumVgprs: 256
; GCN: ScratchSize: 768 ; GCN: ScratchSize: 768
define amdgpu_vs void @main([9 x <4 x i32>] addrspace(4)* inreg %arg, [17 x <4 x i32>] addrspace(4)* inreg %arg1, [17 x <4 x i32>] addrspace(4)* inreg %arg2, [34 x <8 x i32>] addrspace(4)* inreg %arg3, [16 x <4 x i32>] addrspace(4)* inreg %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 { define amdgpu_vs void @main([9 x <4 x i32>] addrspace(4)* inreg %arg, [17 x <4 x i32>] addrspace(4)* inreg %arg1, [17 x <4 x i32>] addrspace(4)* inreg %arg2, [34 x <8 x i32>] addrspace(4)* inreg %arg3, [16 x <4 x i32>] addrspace(4)* inreg %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 {
bb: bb:
%tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg1, i64 0, i64 0 %tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg1, i64 0, i64 0
%tmp11 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, align 16, !tbaa !0 %tmp11 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, align 16, !tbaa !0
%tmp12 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp11, i32 0, i32 0) %tmp12 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp11, i32 0, i32 0)
▲ Show 20 Lines • Show All 466 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/wave32.ll

Show First 20 Lines • Show All 822 Lines • ▼ Show 20 Linesmain_body:
%out.2 = bitcast i32 %out.1 to float %out.2 = bitcast i32 %out.1 to float
ret float %out.2 ret float %out.2
} }
; GCN-LABEL: {{^}}test_intr_fcmp_i64: ; GCN-LABEL: {{^}}test_intr_fcmp_i64:
; GFX1032-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], 0{{$}} ; GFX1032-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], 0{{$}}
; GFX1032-DAG: v_cmp_eq_f32_e64 s[[C_LO:[0-9]+]], {{s[0-9]+}}, |{{[vs][0-9]+}}| ; GFX1032-DAG: v_cmp_eq_f32_e64 s[[C_LO:[0-9]+]], {{s[0-9]+}}, |{{[vs][0-9]+}}|
; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]] ; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]
; GFX1064: v_cmp_eq_f32_e64 s{{\[}}[[C_LO:[0-9]+]]:[[C_HI:[0-9]+]]], {{s[0-9]+}}, |{{[vs][0-9]+}}| ; GFX1064: v_cmp_eq_f32_e64 s[[[C_LO:[0-9]+]]:[[C_HI:[0-9]+]]], {{s[0-9]+}}, |{{[vs][0-9]+}}|
; GFX1064-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]] ; GFX1064-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]
; GFX1064-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[C_HI]] ; GFX1064-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[C_HI]]
; GCN: store_dwordx2 v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]], s ; GCN: store_dwordx2 v{{[0-9]+}}, v[[[V_LO]]:[[V_HI]]], s
define amdgpu_kernel void @test_intr_fcmp_i64(i64 addrspace(1)* %out, float %src, float %a) { define amdgpu_kernel void @test_intr_fcmp_i64(i64 addrspace(1)* %out, float %src, float %a) {
%temp = call float @llvm.fabs.f32(float %a) %temp = call float @llvm.fabs.f32(float %a)
%result = call i64 @llvm.amdgcn.fcmp.i64.f32(float %src, float %temp, i32 1) %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float %src, float %temp, i32 1)
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_intr_icmp_i64: ; GCN-LABEL: {{^}}test_intr_icmp_i64:
; GFX1032-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], 0{{$}} ; GFX1032-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], 0{{$}}
; GFX1032-DAG: v_cmp_eq_u32_e64 [[C_LO:vcc_lo|s[0-9]+]], 0x64, {{s[0-9]+}} ; GFX1032-DAG: v_cmp_eq_u32_e64 [[C_LO:vcc_lo|s[0-9]+]], 0x64, {{s[0-9]+}}
; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[C_LO]] ; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[C_LO]]
; GFX1064: v_cmp_eq_u32_e64 s{{\[}}[[C_LO:[0-9]+]]:[[C_HI:[0-9]+]]], 0x64, {{s[0-9]+}} ; GFX1064: v_cmp_eq_u32_e64 s[[[C_LO:[0-9]+]]:[[C_HI:[0-9]+]]], 0x64, {{s[0-9]+}}
; GFX1064-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]] ; GFX1064-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]
; GFX1064-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[C_HI]] ; GFX1064-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[C_HI]]
; GCN: store_dwordx2 v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]], s ; GCN: store_dwordx2 v{{[0-9]+}}, v[[[V_LO]]:[[V_HI]]], s
define amdgpu_kernel void @test_intr_icmp_i64(i64 addrspace(1)* %out, i32 %src) { define amdgpu_kernel void @test_intr_icmp_i64(i64 addrspace(1)* %out, i32 %src) {
%result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %src, i32 100, i32 32) %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %src, i32 100, i32 32)
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_intr_fcmp_i32: ; GCN-LABEL: {{^}}test_intr_fcmp_i32:
; GFX1032-DAG: v_cmp_eq_f32_e64 s[[C_LO:[0-9]+]], {{s[0-9]+}}, |{{[vs][0-9]+}}| ; GFX1032-DAG: v_cmp_eq_f32_e64 s[[C_LO:[0-9]+]], {{s[0-9]+}}, |{{[vs][0-9]+}}|
; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]] ; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]
; GFX1064: v_cmp_eq_f32_e64 s{{\[}}[[C_LO:[0-9]+]]:[[C_HI:[0-9]+]]], {{s[0-9]+}}, |{{[vs][0-9]+}}| ; GFX1064: v_cmp_eq_f32_e64 s[[[C_LO:[0-9]+]]:[[C_HI:[0-9]+]]], {{s[0-9]+}}, |{{[vs][0-9]+}}|
; GFX1064-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]] ; GFX1064-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]
; GCN: store_dword v{{[0-9]+}}, v[[V_LO]], s ; GCN: store_dword v{{[0-9]+}}, v[[V_LO]], s
define amdgpu_kernel void @test_intr_fcmp_i32(i32 addrspace(1)* %out, float %src, float %a) { define amdgpu_kernel void @test_intr_fcmp_i32(i32 addrspace(1)* %out, float %src, float %a) {
%temp = call float @llvm.fabs.f32(float %a) %temp = call float @llvm.fabs.f32(float %a)
%result = call i32 @llvm.amdgcn.fcmp.i32.f32(float %src, float %temp, i32 1) %result = call i32 @llvm.amdgcn.fcmp.i32.f32(float %src, float %temp, i32 1)
store i32 %result, i32 addrspace(1)* %out store i32 %result, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_intr_icmp_i32: ; GCN-LABEL: {{^}}test_intr_icmp_i32:
; GFX1032-DAG: v_cmp_eq_u32_e64 s[[C_LO:[0-9]+]], 0x64, {{s[0-9]+}} ; GFX1032-DAG: v_cmp_eq_u32_e64 s[[C_LO:[0-9]+]], 0x64, {{s[0-9]+}}
; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]{{$}} ; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]{{$}}
; GFX1064: v_cmp_eq_u32_e64 s{{\[}}[[C_LO:[0-9]+]]:{{[0-9]+}}], 0x64, {{s[0-9]+}} ; GFX1064: v_cmp_eq_u32_e64 s[[[C_LO:[0-9]+]]:{{[0-9]+}}], 0x64, {{s[0-9]+}}
; GFX1064-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]{{$}} ; GFX1064-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]{{$}}
; GCN: store_dword v{{[0-9]+}}, v[[V_LO]], s ; GCN: store_dword v{{[0-9]+}}, v[[V_LO]], s
define amdgpu_kernel void @test_intr_icmp_i32(i32 addrspace(1)* %out, i32 %src) { define amdgpu_kernel void @test_intr_icmp_i32(i32 addrspace(1)* %out, i32 %src) {
%result = call i32 @llvm.amdgcn.icmp.i32.i32(i32 %src, i32 100, i32 32) %result = call i32 @llvm.amdgcn.icmp.i32.i32(i32 %src, i32 100, i32 32)
store i32 %result, i32 addrspace(1)* %out store i32 %result, i32 addrspace(1)* %out
ret void ret void
} }
▲ Show 20 Lines • Show All 315 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; Check that DAGTypeLegalizer::WidenVSELECTAndMask doesn't try to ; Check that DAGTypeLegalizer::WidenVSELECTAndMask doesn't try to
; create vselects with i64 condition masks. ; create vselects with i64 condition masks.
; FIXME: Should be able to avoid intermediate vselect ; FIXME: Should be able to avoid intermediate vselect
; GCN-LABEL: {{^}}widen_vselect_and_mask_v4f64: ; GCN-LABEL: {{^}}widen_vselect_and_mask_v4f64:
; GCN: v_cmp_u_f64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], ; GCN: v_cmp_u_f64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]],
; GCN: v_cndmask_b32_e64 v[[VSEL:[0-9]+]], 0, -1, [[CMP]] ; GCN: v_cndmask_b32_e64 v[[VSEL:[0-9]+]], 0, -1, [[CMP]]
; GCN: v_mov_b32_e32 v[[VSEL_EXT:[0-9]+]], v[[VSEL]] ; GCN: v_mov_b32_e32 v[[VSEL_EXT:[0-9]+]], v[[VSEL]]
; GCN: v_cmp_lt_i64_e32 vcc, -1, v{{\[}}[[VSEL]]:[[VSEL_EXT]]{{\]}} ; GCN: v_cmp_lt_i64_e32 vcc, -1, v[[[VSEL]]:[[VSEL_EXT]]]
define amdgpu_kernel void @widen_vselect_and_mask_v4f64(<4 x double> %arg) #0 { define amdgpu_kernel void @widen_vselect_and_mask_v4f64(<4 x double> %arg) #0 {
bb: bb:
%tmp = extractelement <4 x double> %arg, i64 0 %tmp = extractelement <4 x double> %arg, i64 0
%tmp1 = fcmp uno double %tmp, 0.000000e+00 %tmp1 = fcmp uno double %tmp, 0.000000e+00
%tmp2 = sext i1 %tmp1 to i64 %tmp2 = sext i1 %tmp1 to i64
%tmp3 = insertelement <4 x i64> undef, i64 %tmp2, i32 0 %tmp3 = insertelement <4 x i64> undef, i64 %tmp2, i32 0
%tmp4 = insertelement <4 x i64> %tmp3, i64 undef, i32 1 %tmp4 = insertelement <4 x i64> %tmp3, i64 undef, i32 1
%tmp5 = insertelement <4 x i64> %tmp4, i64 undef, i32 2 %tmp5 = insertelement <4 x i64> %tmp4, i64 undef, i32 2
%tmp6 = insertelement <4 x i64> %tmp5, i64 undef, i32 3 %tmp6 = insertelement <4 x i64> %tmp5, i64 undef, i32 3
%tmp7 = fcmp une <4 x double> %arg, zeroinitializer %tmp7 = fcmp une <4 x double> %arg, zeroinitializer
%tmp8 = icmp sgt <4 x i64> %tmp6, <i64 -1, i64 -1, i64 -1, i64 -1> %tmp8 = icmp sgt <4 x i64> %tmp6, <i64 -1, i64 -1, i64 -1, i64 -1>
%tmp9 = and <4 x i1> %tmp8, %tmp7 %tmp9 = and <4 x i1> %tmp8, %tmp7
%tmp10 = select <4 x i1> %tmp9, <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>, <4 x double> zeroinitializer %tmp10 = select <4 x i1> %tmp9, <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>, <4 x double> zeroinitializer
store <4 x double> %tmp10, <4 x double> addrspace(1)* null, align 32 store <4 x double> %tmp10, <4 x double> addrspace(1)* null, align 32
ret void ret void
} }
; GCN-LABEL: {{^}}widen_vselect_and_mask_v4i64: ; GCN-LABEL: {{^}}widen_vselect_and_mask_v4i64:
; GCN: v_cmp_eq_u64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], ; GCN: v_cmp_eq_u64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]],
; GCN: v_cndmask_b32_e64 v[[VSEL:[0-9]+]], 0, -1, [[CMP]] ; GCN: v_cndmask_b32_e64 v[[VSEL:[0-9]+]], 0, -1, [[CMP]]
; GCN: v_mov_b32_e32 v[[VSEL_EXT:[0-9]+]], v[[VSEL]] ; GCN: v_mov_b32_e32 v[[VSEL_EXT:[0-9]+]], v[[VSEL]]
; GCN: v_cmp_lt_i64_e32 vcc, -1, v{{\[}}[[VSEL]]:[[VSEL_EXT]]{{\]}} ; GCN: v_cmp_lt_i64_e32 vcc, -1, v[[[VSEL]]:[[VSEL_EXT]]]
define amdgpu_kernel void @widen_vselect_and_mask_v4i64(<4 x i64> %arg) #0 { define amdgpu_kernel void @widen_vselect_and_mask_v4i64(<4 x i64> %arg) #0 {
bb: bb:
%tmp = extractelement <4 x i64> %arg, i64 0 %tmp = extractelement <4 x i64> %arg, i64 0
%tmp1 = icmp eq i64 %tmp, 0 %tmp1 = icmp eq i64 %tmp, 0
%tmp2 = sext i1 %tmp1 to i64 %tmp2 = sext i1 %tmp1 to i64
%tmp3 = insertelement <4 x i64> undef, i64 %tmp2, i32 0 %tmp3 = insertelement <4 x i64> undef, i64 %tmp2, i32 0
%tmp4 = insertelement <4 x i64> %tmp3, i64 undef, i32 1 %tmp4 = insertelement <4 x i64> %tmp3, i64 undef, i32 1
%tmp5 = insertelement <4 x i64> %tmp4, i64 undef, i32 2 %tmp5 = insertelement <4 x i64> %tmp4, i64 undef, i32 2
Show All 11 Lines

llvm/test/CodeGen/AMDGPU/wwm-reserved.ll

; RUN: llc -O0 -march=amdgcn -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-O0 %s ; RUN: llc -O0 -march=amdgcn -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-O0 %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-O3 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-O3 %s
; NOTE: llvm.amdgcn.wwm is deprecated, use llvm.amdgcn.strict.wwm instead. ; NOTE: llvm.amdgcn.wwm is deprecated, use llvm.amdgcn.strict.wwm instead.
; GFX9-LABEL: {{^}}no_cfg: ; GFX9-LABEL: {{^}}no_cfg:
define amdgpu_cs void @no_cfg(<4 x i32> inreg %tmp14) { define amdgpu_cs void @no_cfg(<4 x i32> inreg %tmp14) {
%tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0) %tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0)
%tmp101 = bitcast <2 x float> %tmp100 to <2 x i32> %tmp101 = bitcast <2 x float> %tmp100 to <2 x i32>
%tmp102 = extractelement <2 x i32> %tmp101, i32 0 %tmp102 = extractelement <2 x i32> %tmp101, i32 0
%tmp103 = extractelement <2 x i32> %tmp101, i32 1 %tmp103 = extractelement <2 x i32> %tmp101, i32 1
%tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0) %tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0)
%tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0) %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0)
; GFX9: s_or_saveexec_b64 s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, -1 ; GFX9: s_or_saveexec_b64 s[{{[0-9]+}}:{{[0-9]+}}], -1
; GFX9-DAG: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-DAG: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-O3-DAG: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] ; GFX9-O3-DAG: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]]
; GFX9-O0-DAG: v_add_u32_e64 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] ; GFX9-O0-DAG: v_add_u32_e64 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]]
; GFX9-DAG: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]] ; GFX9-DAG: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]]
%tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false) %tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false)
%tmp121 = add i32 %tmp105, %tmp120 %tmp121 = add i32 %tmp105, %tmp120
%tmp122 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp121) %tmp122 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp121)
; GFX9-DAG: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-DAG: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-O3-DAG: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] ; GFX9-O3-DAG: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]]
; GFX9-O0-DAG: v_add_u32_e64 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] ; GFX9-O0-DAG: v_add_u32_e64 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]]
; GFX9-DAG: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]] ; GFX9-DAG: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]]
%tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false) %tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false)
%tmp136 = add i32 %tmp107, %tmp135 %tmp136 = add i32 %tmp107, %tmp135
%tmp137 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp136) %tmp137 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp136)
; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]] ; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]]
; GFX9-O0: v_cmp_eq_u32_e64 s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v[[FIRST]], v[[SECOND]] ; GFX9-O0: v_cmp_eq_u32_e64 s[{{[0-9]+}}:{{[0-9]+}}], v[[FIRST]], v[[SECOND]]
%tmp138 = icmp eq i32 %tmp122, %tmp137 %tmp138 = icmp eq i32 %tmp122, %tmp137
%tmp139 = sext i1 %tmp138 to i32 %tmp139 = sext i1 %tmp138 to i32
%tmp140 = shl nsw i32 %tmp139, 1 %tmp140 = shl nsw i32 %tmp139, 1
%tmp141 = and i32 %tmp140, 2 %tmp141 = and i32 %tmp140, 2
%tmp145 = bitcast i32 %tmp141 to float %tmp145 = bitcast i32 %tmp141 to float
call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0) call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0)
ret void ret void
} }
; GFX9-LABEL: {{^}}cfg: ; GFX9-LABEL: {{^}}cfg:
define amdgpu_cs void @cfg(<4 x i32> inreg %tmp14, i32 %arg) { define amdgpu_cs void @cfg(<4 x i32> inreg %tmp14, i32 %arg) {
entry: entry:
%tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0) %tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0)
%tmp101 = bitcast <2 x float> %tmp100 to <2 x i32> %tmp101 = bitcast <2 x float> %tmp100 to <2 x i32>
%tmp102 = extractelement <2 x i32> %tmp101, i32 0 %tmp102 = extractelement <2 x i32> %tmp101, i32 0
%tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0) %tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0)
; GFX9: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-O3: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] ; GFX9-O3: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]]
; GFX9-O0: v_add_u32_e64 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] ; GFX9-O0: v_add_u32_e64 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]]
; GFX9: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]] ; GFX9: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]]
; GFX9-O0: buffer_store_dword v[[FIRST]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[FIRST_IMM_OFFSET:[0-9]+]] ; GFX9-O0: buffer_store_dword v[[FIRST]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:[[FIRST_IMM_OFFSET:[0-9]+]]
%tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false) %tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false)
%tmp121 = add i32 %tmp105, %tmp120 %tmp121 = add i32 %tmp105, %tmp120
%tmp122 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp121) %tmp122 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp121)
%cond = icmp eq i32 %arg, 0 %cond = icmp eq i32 %arg, 0
br i1 %cond, label %if, label %merge br i1 %cond, label %if, label %merge
if: if:
%tmp103 = extractelement <2 x i32> %tmp101, i32 1 %tmp103 = extractelement <2 x i32> %tmp101, i32 1
%tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0) %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0)
; GFX9: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-O3: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] ; GFX9-O3: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]]
; GFX9-O0: v_add_u32_e64 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] ; GFX9-O0: v_add_u32_e64 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]]
; GFX9: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]] ; GFX9: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]]
; GFX9-O0: buffer_store_dword v[[SECOND]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[SECOND_IMM_OFFSET:[0-9]+]] ; GFX9-O0: buffer_store_dword v[[SECOND]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:[[SECOND_IMM_OFFSET:[0-9]+]]
%tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false) %tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false)
%tmp136 = add i32 %tmp107, %tmp135 %tmp136 = add i32 %tmp107, %tmp135
%tmp137 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp136) %tmp137 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp136)
br label %merge br label %merge
merge: merge:
%merge_value = phi i32 [ 0, %entry ], [%tmp137, %if ] %merge_value = phi i32 [ 0, %entry ], [%tmp137, %if ]
; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]] ; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]]
; GFX9-O0: buffer_load_dword v[[FIRST:[0-9]+]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[FIRST_IMM_OFFSET]] ; GFX9-O0: buffer_load_dword v[[FIRST:[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:[[FIRST_IMM_OFFSET]]
; GFX9-O0: buffer_load_dword v[[SECOND:[0-9]+]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[SECOND_IMM_OFFSET]] ; GFX9-O0: buffer_load_dword v[[SECOND:[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:[[SECOND_IMM_OFFSET]]
; GFX9-O0: v_cmp_eq_u32_e64 s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v[[FIRST]], v[[SECOND]] ; GFX9-O0: v_cmp_eq_u32_e64 s[{{[0-9]+}}:{{[0-9]+}}], v[[FIRST]], v[[SECOND]]
%tmp138 = icmp eq i32 %tmp122, %merge_value %tmp138 = icmp eq i32 %tmp122, %merge_value
%tmp139 = sext i1 %tmp138 to i32 %tmp139 = sext i1 %tmp138 to i32
%tmp140 = shl nsw i32 %tmp139, 1 %tmp140 = shl nsw i32 %tmp139, 1
%tmp141 = and i32 %tmp140, 2 %tmp141 = and i32 %tmp140, 2
%tmp145 = bitcast i32 %tmp141 to float %tmp145 = bitcast i32 %tmp141 to float
call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0) call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0)
ret void ret void
} }
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesdefine i64 @called_i64(i64 %a) noinline {
%add = add i64 %a, %a %add = add i64 %a, %a
%mul = mul i64 %add, %a %mul = mul i64 %add, %a
%sub = sub i64 %mul, %add %sub = sub i64 %mul, %add
ret i64 %sub ret i64 %sub
} }
; GFX9-LABEL: {{^}}call_i64: ; GFX9-LABEL: {{^}}call_i64:
define amdgpu_kernel void @call_i64(<4 x i32> inreg %tmp14, i64 inreg %arg) { define amdgpu_kernel void @call_i64(<4 x i32> inreg %tmp14, i64 inreg %arg) {
; GFX9: s_load_dwordx2 s{{\[}}[[ARG_LO:[0-9]+]]:[[ARG_HI:[0-9]+]]{{\]}} ; GFX9: s_load_dwordx2 s[[[ARG_LO:[0-9]+]]:[[ARG_HI:[0-9]+]]]
; GFX9-O0: s_mov_b64 s{{\[}}[[ZERO_LO:[0-9]+]]:[[ZERO_HI:[0-9]+]]{{\]}}, 0{{$}} ; GFX9-O0: s_mov_b64 s[[[ZERO_LO:[0-9]+]]:[[ZERO_HI:[0-9]+]]], 0{{$}}
; GFX9-O0: v_mov_b32_e32 v0, s[[ARG_LO]] ; GFX9-O0: v_mov_b32_e32 v0, s[[ARG_LO]]
; GFX9-O0: v_mov_b32_e32 v1, s[[ARG_HI]] ; GFX9-O0: v_mov_b32_e32 v1, s[[ARG_HI]]
; GFX9-O0-DAG: v_mov_b32_e32 v9, v1 ; GFX9-O0-DAG: v_mov_b32_e32 v9, v1
; GFX9-O0-DAG: v_mov_b32_e32 v8, v0 ; GFX9-O0-DAG: v_mov_b32_e32 v8, v0
; GFX9-O3-DAG: v_mov_b32_e32 v7, s[[ARG_HI]] ; GFX9-O3-DAG: v_mov_b32_e32 v7, s[[ARG_HI]]
; GFX9-O3-DAG: v_mov_b32_e32 v6, s[[ARG_LO]] ; GFX9-O3-DAG: v_mov_b32_e32 v6, s[[ARG_LO]]
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define amdgpu_cs void @strict_wwm_no_cfg(<4 x i32> inreg %tmp14) { define amdgpu_cs void @strict_wwm_no_cfg(<4 x i32> inreg %tmp14) {
%tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0) %tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0)
%tmp101 = bitcast <2 x float> %tmp100 to <2 x i32> %tmp101 = bitcast <2 x float> %tmp100 to <2 x i32>
%tmp102 = extractelement <2 x i32> %tmp101, i32 0 %tmp102 = extractelement <2 x i32> %tmp101, i32 0
%tmp103 = extractelement <2 x i32> %tmp101, i32 1 %tmp103 = extractelement <2 x i32> %tmp101, i32 1
%tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0) %tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0)
%tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0) %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0)
; GFX9: s_or_saveexec_b64 s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, -1 ; GFX9: s_or_saveexec_b64 s[{{[0-9]+}}:{{[0-9]+}}], -1
; GFX9-DAG: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-DAG: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-O3-DAG: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] ; GFX9-O3-DAG: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]]
; GFX9-O0-DAG: v_add_u32_e64 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] ; GFX9-O0-DAG: v_add_u32_e64 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]]
; GFX9-DAG: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]] ; GFX9-DAG: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]]
%tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false) %tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false)
%tmp121 = add i32 %tmp105, %tmp120 %tmp121 = add i32 %tmp105, %tmp120
%tmp122 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp121) %tmp122 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp121)
; GFX9-DAG: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9-DAG: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-O3-DAG: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] ; GFX9-O3-DAG: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]]
; GFX9-O0-DAG: v_add_u32_e64 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] ; GFX9-O0-DAG: v_add_u32_e64 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]]
; GFX9-DAG: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]] ; GFX9-DAG: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]]
%tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false) %tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false)
%tmp136 = add i32 %tmp107, %tmp135 %tmp136 = add i32 %tmp107, %tmp135
%tmp137 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp136) %tmp137 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp136)
; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]] ; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]]
; GFX9-O0: v_cmp_eq_u32_e64 s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v[[FIRST]], v[[SECOND]] ; GFX9-O0: v_cmp_eq_u32_e64 s[{{[0-9]+}}:{{[0-9]+}}], v[[FIRST]], v[[SECOND]]
%tmp138 = icmp eq i32 %tmp122, %tmp137 %tmp138 = icmp eq i32 %tmp122, %tmp137
%tmp139 = sext i1 %tmp138 to i32 %tmp139 = sext i1 %tmp138 to i32
%tmp140 = shl nsw i32 %tmp139, 1 %tmp140 = shl nsw i32 %tmp139, 1
%tmp141 = and i32 %tmp140, 2 %tmp141 = and i32 %tmp140, 2
%tmp145 = bitcast i32 %tmp141 to float %tmp145 = bitcast i32 %tmp141 to float
call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0) call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0)
ret void ret void
} }
; GFX9-LABEL: {{^}}strict_wwm_cfg: ; GFX9-LABEL: {{^}}strict_wwm_cfg:
define amdgpu_cs void @strict_wwm_cfg(<4 x i32> inreg %tmp14, i32 %arg) { define amdgpu_cs void @strict_wwm_cfg(<4 x i32> inreg %tmp14, i32 %arg) {
entry: entry:
%tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0) %tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0)
%tmp101 = bitcast <2 x float> %tmp100 to <2 x i32> %tmp101 = bitcast <2 x float> %tmp100 to <2 x i32>
%tmp102 = extractelement <2 x i32> %tmp101, i32 0 %tmp102 = extractelement <2 x i32> %tmp101, i32 0
%tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0) %tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0)
; GFX9: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-O3: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] ; GFX9-O3: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]]
; GFX9-O0: v_add_u32_e64 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] ; GFX9-O0: v_add_u32_e64 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]]
; GFX9: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]] ; GFX9: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]]
; GFX9-O0: buffer_store_dword v[[FIRST]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[FIRST_IMM_OFFSET:[0-9]+]] ; GFX9-O0: buffer_store_dword v[[FIRST]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:[[FIRST_IMM_OFFSET:[0-9]+]]
%tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false) %tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false)
%tmp121 = add i32 %tmp105, %tmp120 %tmp121 = add i32 %tmp105, %tmp120
%tmp122 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp121) %tmp122 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp121)
%cond = icmp eq i32 %arg, 0 %cond = icmp eq i32 %arg, 0
br i1 %cond, label %if, label %merge br i1 %cond, label %if, label %merge
if: if:
%tmp103 = extractelement <2 x i32> %tmp101, i32 1 %tmp103 = extractelement <2 x i32> %tmp101, i32 1
%tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0) %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0)
; GFX9: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf ; GFX9: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf
; GFX9-O3: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] ; GFX9-O3: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]]
; GFX9-O0: v_add_u32_e64 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] ; GFX9-O0: v_add_u32_e64 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]]
; GFX9: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]] ; GFX9: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]]
; GFX9-O0: buffer_store_dword v[[SECOND]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[SECOND_IMM_OFFSET:[0-9]+]] ; GFX9-O0: buffer_store_dword v[[SECOND]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:[[SECOND_IMM_OFFSET:[0-9]+]]
%tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false) %tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false)
%tmp136 = add i32 %tmp107, %tmp135 %tmp136 = add i32 %tmp107, %tmp135
%tmp137 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp136) %tmp137 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp136)
br label %merge br label %merge
merge: merge:
%merge_value = phi i32 [ 0, %entry ], [%tmp137, %if ] %merge_value = phi i32 [ 0, %entry ], [%tmp137, %if ]
; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]] ; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]]
; GFX9-O0: buffer_load_dword v[[FIRST:[0-9]+]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[FIRST_IMM_OFFSET]] ; GFX9-O0: buffer_load_dword v[[FIRST:[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:[[FIRST_IMM_OFFSET]]
; GFX9-O0: buffer_load_dword v[[SECOND:[0-9]+]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[SECOND_IMM_OFFSET]] ; GFX9-O0: buffer_load_dword v[[SECOND:[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:[[SECOND_IMM_OFFSET]]
; GFX9-O0: v_cmp_eq_u32_e64 s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v[[FIRST]], v[[SECOND]] ; GFX9-O0: v_cmp_eq_u32_e64 s[{{[0-9]+}}:{{[0-9]+}}], v[[FIRST]], v[[SECOND]]
%tmp138 = icmp eq i32 %tmp122, %merge_value %tmp138 = icmp eq i32 %tmp122, %merge_value
%tmp139 = sext i1 %tmp138 to i32 %tmp139 = sext i1 %tmp138 to i32
%tmp140 = shl nsw i32 %tmp139, 1 %tmp140 = shl nsw i32 %tmp139, 1
%tmp141 = and i32 %tmp140, 2 %tmp141 = and i32 %tmp140, 2
%tmp145 = bitcast i32 %tmp141 to float %tmp145 = bitcast i32 %tmp141 to float
call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0) call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0)
ret void ret void
} }
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesdefine i64 @strict_wwm_called_i64(i64 %a) noinline {
%add = add i64 %a, %a %add = add i64 %a, %a
%mul = mul i64 %add, %a %mul = mul i64 %add, %a
%sub = sub i64 %mul, %add %sub = sub i64 %mul, %add
ret i64 %sub ret i64 %sub
} }
; GFX9-LABEL: {{^}}strict_wwm_call_i64: ; GFX9-LABEL: {{^}}strict_wwm_call_i64:
define amdgpu_kernel void @strict_wwm_call_i64(<4 x i32> inreg %tmp14, i64 inreg %arg) { define amdgpu_kernel void @strict_wwm_call_i64(<4 x i32> inreg %tmp14, i64 inreg %arg) {
; GFX9: s_load_dwordx2 s{{\[}}[[ARG_LO:[0-9]+]]:[[ARG_HI:[0-9]+]]{{\]}} ; GFX9: s_load_dwordx2 s[[[ARG_LO:[0-9]+]]:[[ARG_HI:[0-9]+]]]
; GFX9-O0: s_mov_b64 s{{\[}}[[ZERO_LO:[0-9]+]]:[[ZERO_HI:[0-9]+]]{{\]}}, 0{{$}} ; GFX9-O0: s_mov_b64 s[[[ZERO_LO:[0-9]+]]:[[ZERO_HI:[0-9]+]]], 0{{$}}
; GFX9-O0: v_mov_b32_e32 v0, s[[ARG_LO]] ; GFX9-O0: v_mov_b32_e32 v0, s[[ARG_LO]]
; GFX9-O0: v_mov_b32_e32 v1, s[[ARG_HI]] ; GFX9-O0: v_mov_b32_e32 v1, s[[ARG_HI]]
; GFX9-O0-DAG: v_mov_b32_e32 v9, v1 ; GFX9-O0-DAG: v_mov_b32_e32 v9, v1
; GFX9-O0-DAG: v_mov_b32_e32 v8, v0 ; GFX9-O0-DAG: v_mov_b32_e32 v8, v0
; GFX9-O3-DAG: v_mov_b32_e32 v7, s[[ARG_HI]] ; GFX9-O3-DAG: v_mov_b32_e32 v7, s[[ARG_HI]]
; GFX9-O3-DAG: v_mov_b32_e32 v6, s[[ARG_LO]] ; GFX9-O3-DAG: v_mov_b32_e32 v6, s[[ARG_LO]]
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/xor.ll

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
endif: endif:
%3 = phi i64 [%1, %if], [%2, %else] %3 = phi i64 [%1, %if], [%2, %else]
store i64 %3, i64 addrspace(1)* %out store i64 %3, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}scalar_xor_literal_i64: ; FUNC-LABEL: {{^}}scalar_xor_literal_i64:
; SI: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}} ; SI: s_load_dwordx2 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}}
; SI-DAG: s_xor_b32 s[[RES_HI:[0-9]+]], s{{[0-9]+}}, 0xf237b ; SI-DAG: s_xor_b32 s[[RES_HI:[0-9]+]], s{{[0-9]+}}, 0xf237b
; SI-DAG: s_xor_b32 s[[RES_LO:[0-9]+]], s{{[0-9]+}}, 0x3039 ; SI-DAG: s_xor_b32 s[[RES_LO:[0-9]+]], s{{[0-9]+}}, 0x3039
; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[RES_LO]] ; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[RES_LO]]
; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[RES_HI]] ; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[RES_HI]]
define amdgpu_kernel void @scalar_xor_literal_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) { define amdgpu_kernel void @scalar_xor_literal_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
%or = xor i64 %a, 4261135838621753 %or = xor i64 %a, 4261135838621753
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}scalar_xor_literal_multi_use_i64: ; FUNC-LABEL: {{^}}scalar_xor_literal_multi_use_i64:
; SI: s_load_dwordx4 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}} ; SI: s_load_dwordx4 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0xf237b ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0xf237b
; SI-DAG: s_movk_i32 s[[K_LO:[0-9]+]], 0x3039 ; SI-DAG: s_movk_i32 s[[K_LO:[0-9]+]], 0x3039
; SI: s_xor_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}} ; SI: s_xor_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s[[[K_LO]]:[[K_HI]]]
; SI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, s[[K_LO]] ; SI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, s[[K_LO]]
; SI: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, s[[K_HI]] ; SI: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, s[[K_HI]]
define amdgpu_kernel void @scalar_xor_literal_multi_use_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a, i64 %b) { define amdgpu_kernel void @scalar_xor_literal_multi_use_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a, i64 %b) {
%or = xor i64 %a, 4261135838621753 %or = xor i64 %a, 4261135838621753
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
%foo = add i64 %b, 4261135838621753 %foo = add i64 %b, 4261135838621753
store volatile i64 %foo, i64 addrspace(1)* undef store volatile i64 %foo, i64 addrspace(1)* undef
ret void ret void
} }
; FUNC-LABEL: {{^}}scalar_xor_inline_imm_i64: ; FUNC-LABEL: {{^}}scalar_xor_inline_imm_i64:
; SI: s_load_dwordx2 s{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}} ; SI: s_load_dwordx2 s[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
; SI-NOT: xor_b32 ; SI-NOT: xor_b32
; SI: s_xor_b32 s[[VAL_LO]], s{{[0-9]+}}, 63 ; SI: s_xor_b32 s[[VAL_LO]], s{{[0-9]+}}, 63
; SI-NOT: xor_b32 ; SI-NOT: xor_b32
; SI: v_mov_b32_e32 v[[VLO:[0-9]+]], s{{[0-9]+}} ; SI: v_mov_b32_e32 v[[VLO:[0-9]+]], s{{[0-9]+}}
; SI-NOT: xor_b32 ; SI-NOT: xor_b32
; SI: v_mov_b32_e32 v[[VHI:[0-9]+]], s{{[0-9]+}} ; SI: v_mov_b32_e32 v[[VHI:[0-9]+]], s{{[0-9]+}}
; SI-NOT: xor_b32 ; SI-NOT: xor_b32
; SI: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} ; SI: buffer_store_dwordx2 v[[[VLO]]:[[VHI]]]
define amdgpu_kernel void @scalar_xor_inline_imm_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) { define amdgpu_kernel void @scalar_xor_inline_imm_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
%or = xor i64 %a, 63 %or = xor i64 %a, 63
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}scalar_xor_neg_inline_imm_i64: ; FUNC-LABEL: {{^}}scalar_xor_neg_inline_imm_i64:
; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}} ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
; SI: s_xor_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -8 ; SI: s_xor_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -8
define amdgpu_kernel void @scalar_xor_neg_inline_imm_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) { define amdgpu_kernel void @scalar_xor_neg_inline_imm_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
%or = xor i64 %a, -8 %or = xor i64 %a, -8
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}vector_xor_i64_neg_inline_imm: ; FUNC-LABEL: {{^}}vector_xor_i64_neg_inline_imm:
; SI: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI: v_xor_b32_e32 {{v[0-9]+}}, -8, v[[LO_VREG]] ; SI: v_xor_b32_e32 {{v[0-9]+}}, -8, v[[LO_VREG]]
; SI: v_xor_b32_e32 {{v[0-9]+}}, -1, {{.*}} ; SI: v_xor_b32_e32 {{v[0-9]+}}, -1, {{.*}}
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @vector_xor_i64_neg_inline_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @vector_xor_i64_neg_inline_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 8 %loada = load i64, i64 addrspace(1)* %a, align 8
%or = xor i64 %loada, -8 %or = xor i64 %loada, -8
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}vector_xor_literal_i64: ; FUNC-LABEL: {{^}}vector_xor_literal_i64:
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, ; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
; SI-DAG: v_xor_b32_e32 {{v[0-9]+}}, 0xdf77987f, v[[LO_VREG]] ; SI-DAG: v_xor_b32_e32 {{v[0-9]+}}, 0xdf77987f, v[[LO_VREG]]
; SI-DAG: v_xor_b32_e32 {{v[0-9]+}}, 0x146f, v[[HI_VREG]] ; SI-DAG: v_xor_b32_e32 {{v[0-9]+}}, 0x146f, v[[HI_VREG]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @vector_xor_literal_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { define amdgpu_kernel void @vector_xor_literal_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
%loada = load i64, i64 addrspace(1)* %a, align 8 %loada = load i64, i64 addrspace(1)* %a, align 8
%or = xor i64 %loada, 22470723082367 %or = xor i64 %loada, 22470723082367
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/zero_extend.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; R600: {{^}}s_mad_zext_i32_to_i64: ; R600: {{^}}s_mad_zext_i32_to_i64:
; R600: MEM_RAT_CACHELESS STORE_RAW ; R600: MEM_RAT_CACHELESS STORE_RAW
; R600: MEM_RAT_CACHELESS STORE_RAW ; R600: MEM_RAT_CACHELESS STORE_RAW
; GCN: {{^}}s_mad_zext_i32_to_i64: ; GCN: {{^}}s_mad_zext_i32_to_i64:
; GCN: v_mov_b32_e32 v[[V_ZERO:[0-9]]], 0{{$}} ; GCN: v_mov_b32_e32 v[[V_ZERO:[0-9]]], 0{{$}}
; GCN: buffer_store_dwordx2 v[0:[[V_ZERO]]{{\]}} ; GCN: buffer_store_dwordx2 v[0:[[V_ZERO]]]
define amdgpu_kernel void @s_mad_zext_i32_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) #0 { define amdgpu_kernel void @s_mad_zext_i32_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) #0 {
entry: entry:
%tmp0 = mul i32 %a, %b %tmp0 = mul i32 %a, %b
%tmp1 = add i32 %tmp0, %c %tmp1 = add i32 %tmp0, %c
%tmp2 = zext i32 %tmp1 to i64 %tmp2 = zext i32 %tmp1 to i64
store i64 %tmp2, i64 addrspace(1)* %out store i64 %tmp2, i64 addrspace(1)* %out
ret void ret void
} }
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}zext_or_operand_i64: ; GCN-LABEL: {{^}}zext_or_operand_i64:
; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} ; GCN: buffer_load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
; GCN: buffer_load_dword v[[LD32:[0-9]+]] ; GCN: buffer_load_dword v[[LD32:[0-9]+]]
; GCN-NOT: _or_ ; GCN-NOT: _or_
; GCN-NOT: v[[HI]] ; GCN-NOT: v[[HI]]
; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0 ; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
; GCN: v_or_b32_e32 v[[LO]], v[[LO]], v[[LD32]] ; GCN: v_or_b32_e32 v[[LO]], v[[LO]], v[[LD32]]
; GCN-NOT: _or_ ; GCN-NOT: _or_
; GCN-NOT: v[[HI]] ; GCN-NOT: v[[HI]]
; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0 ; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
define amdgpu_kernel void @zext_or_operand_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i32 addrspace(1)* %in1) { define amdgpu_kernel void @zext_or_operand_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i32 addrspace(1)* %in1) {
%ld.64 = load volatile i64, i64 addrspace(1)* %in0 %ld.64 = load volatile i64, i64 addrspace(1)* %in0
%ld.32 = load volatile i32, i32 addrspace(1)* %in1 %ld.32 = load volatile i32, i32 addrspace(1)* %in1
%ext = zext i32 %ld.32 to i64 %ext = zext i32 %ld.32 to i64
%or = or i64 %ld.64, %ext %or = or i64 %ld.64, %ext
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}zext_or_operand_commute_i64: ; GCN-LABEL: {{^}}zext_or_operand_commute_i64:
; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} ; GCN: buffer_load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
; GCN: buffer_load_dword v[[LD32:[0-9]+]] ; GCN: buffer_load_dword v[[LD32:[0-9]+]]
; GCN-NOT: _or_ ; GCN-NOT: _or_
; GCN-NOT: v[[HI]] ; GCN-NOT: v[[HI]]
; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0 ; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
; GCN: v_or_b32_e32 v[[LO]], v[[LO]], v[[LD32]] ; GCN: v_or_b32_e32 v[[LO]], v[[LO]], v[[LD32]]
; GCN-NOT: v[[HI]] ; GCN-NOT: v[[HI]]
; GCN-NOT: _or_ ; GCN-NOT: _or_
; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0 ; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
define amdgpu_kernel void @zext_or_operand_commute_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i32 addrspace(1)* %in1) { define amdgpu_kernel void @zext_or_operand_commute_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i32 addrspace(1)* %in1) {
%ld.64 = load volatile i64, i64 addrspace(1)* %in0 %ld.64 = load volatile i64, i64 addrspace(1)* %in0
%ld.32 = load volatile i32, i32 addrspace(1)* %in1 %ld.32 = load volatile i32, i32 addrspace(1)* %in1
%ext = zext i32 %ld.32 to i64 %ext = zext i32 %ld.32 to i64
%or = or i64 %ext, %ld.64 %or = or i64 %ext, %ld.64
store i64 %or, i64 addrspace(1)* %out store i64 %or, i64 addrspace(1)* %out
ret void ret void
} }

llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll

Show All 23 Lines; CHECK: bic [[REG]], [[REG]], #7
ret void ret void
} }
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val ; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
; CHECK: movt [[BASE]], :upper16:static_val ; CHECK: movt [[BASE]], :upper16:static_val
; ldm is not formed when the coalescer failed to coalesce everything. ; ldm is not formed when the coalescer failed to coalesce everything.
; CHECK: ldrd r2, [[TMP:r[0-9]+]], {{\[}}[[BASE]]{{\]}} ; CHECK: ldrd r2, [[TMP:r[0-9]+]], [[[BASE]]]
; CHECK: movw r0, #555 ; CHECK: movw r0, #555
define i32 @main() { define i32 @main() {
entry: entry:
call void (i32, ...) @test_byval_8_bytes_alignment(i32 555, %struct_t* byval(%struct_t) @static_val) call void (i32, ...) @test_byval_8_bytes_alignment(i32 555, %struct_t* byval(%struct_t) @static_val)
ret i32 0 ret i32 0
} }
declare void @f(double); declare void @f(double);
Show All 10 Linesentry:
call void (double) @f(double %0) call void (double) @f(double %0)
ret void ret void
} }
; CHECK-LABEL: main_fixed_arg: ; CHECK-LABEL: main_fixed_arg:
; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val ; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
; CHECK: movt [[BASE]], :upper16:static_val ; CHECK: movt [[BASE]], :upper16:static_val
; ldm is not formed when the coalescer failed to coalesce everything. ; ldm is not formed when the coalescer failed to coalesce everything.
; CHECK: ldrd r2, [[TMP:r[0-9]+]], {{\[}}[[BASE]]{{\]}} ; CHECK: ldrd r2, [[TMP:r[0-9]+]], [[[BASE]]]
; CHECK: movw r0, #555 ; CHECK: movw r0, #555
define i32 @main_fixed_arg() { define i32 @main_fixed_arg() {
entry: entry:
call void (i32, %struct_t*) @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval(%struct_t) @static_val) call void (i32, %struct_t*) @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval(%struct_t) @static_val)
ret i32 0 ret i32 0
} }

llvm/test/CodeGen/ARM/Windows/tls.ll

Show All 11 Linesdefine i32 @f() {
%1 = load i32, i32* @i %1 = load i32, i32* @i
ret i32 %1 ret i32 %1
} }
; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 ; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index ; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] ; CHECK-NEXT: ldr [[INDEX:r[0-9]]], [[[TLS_INDEX]]]
; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], [[[TEB]], #44]
; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] ; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], [[[TLS_POINTER]], [[INDEX]], lsl #2]
; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]] ; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
; CHECK-NEXT: ldr r0, {{\[}}[[TLS]], [[SLOT]]] ; CHECK-NEXT: ldr r0, [[[TLS]], [[SLOT]]]
; CHECK: [[CPI]]: ; CHECK: [[CPI]]:
; CHECK-NEXT: .long i(SECREL32) ; CHECK-NEXT: .long i(SECREL32)
define i32 @e() { define i32 @e() {
%1 = load i32, i32* @j %1 = load i32, i32* @j
ret i32 %1 ret i32 %1
} }
; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 ; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index ; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] ; CHECK-NEXT: ldr [[INDEX:r[0-9]]], [[[TLS_INDEX]]]
; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], [[[TEB]], #44]
; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] ; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], [[[TLS_POINTER]], [[INDEX]], lsl #2]
; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]] ; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
; CHECK-NEXT: ldr r0, {{\[}}[[TLS]], [[SLOT]]] ; CHECK-NEXT: ldr r0, [[[TLS]], [[SLOT]]]
; CHECK: [[CPI]]: ; CHECK: [[CPI]]:
; CHECK-NEXT: .long j(SECREL32) ; CHECK-NEXT: .long j(SECREL32)
define i32 @d() { define i32 @d() {
%1 = load i32, i32* @k %1 = load i32, i32* @k
ret i32 %1 ret i32 %1
} }
; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 ; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index ; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] ; CHECK-NEXT: ldr [[INDEX:r[0-9]]], [[[TLS_INDEX]]]
; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], [[[TEB]], #44]
; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] ; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], [[[TLS_POINTER]], [[INDEX]], lsl #2]
; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]] ; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
; CHECK-NEXT: ldr r0, {{\[}}[[TLS]], [[SLOT]]] ; CHECK-NEXT: ldr r0, [[[TLS]], [[SLOT]]]
; CHECK: [[CPI]]: ; CHECK: [[CPI]]:
; CHECK-NEXT: .long k(SECREL32) ; CHECK-NEXT: .long k(SECREL32)
define i32 @c() { define i32 @c() {
%1 = load i32, i32* @l %1 = load i32, i32* @l
ret i32 %1 ret i32 %1
} }
; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 ; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index ; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] ; CHECK-NEXT: ldr [[INDEX:r[0-9]]], [[[TLS_INDEX]]]
; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], [[[TEB]], #44]
; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] ; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], [[[TLS_POINTER]], [[INDEX]], lsl #2]
; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]] ; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
; CHECK-NEXT: ldr r0, {{\[}}[[TLS]], [[SLOT]]] ; CHECK-NEXT: ldr r0, [[[TLS]], [[SLOT]]]
; CHECK: [[CPI]]: ; CHECK: [[CPI]]:
; CHECK-NEXT: .long l(SECREL32) ; CHECK-NEXT: .long l(SECREL32)
define i32 @b() { define i32 @b() {
%1 = load i32, i32* @m %1 = load i32, i32* @m
ret i32 %1 ret i32 %1
} }
; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 ; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index ; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] ; CHECK-NEXT: ldr [[INDEX:r[0-9]]], [[[TLS_INDEX]]]
; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], [[[TEB]], #44]
; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] ; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], [[[TLS_POINTER]], [[INDEX]], lsl #2]
; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]] ; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
; CHECK-NEXT: ldr r0, {{\[}}[[TLS]], [[SLOT]]] ; CHECK-NEXT: ldr r0, [[[TLS]], [[SLOT]]]
; CHECK: [[CPI]]: ; CHECK: [[CPI]]:
; CHECK: .long m(SECREL32) ; CHECK: .long m(SECREL32)
define i16 @a() { define i16 @a() {
%1 = load i16, i16* @n %1 = load i16, i16* @n
ret i16 %1 ret i16 %1
} }
; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 ; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index ; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] ; CHECK-NEXT: ldr [[INDEX:r[0-9]]], [[[TLS_INDEX]]]
; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], [[[TEB]], #44]
; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] ; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], [[[TLS_POINTER]], [[INDEX]], lsl #2]
; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]] ; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
; CHECK-NEXT: ldrh r0, {{\[}}[[TLS]], [[SLOT]]] ; CHECK-NEXT: ldrh r0, [[[TLS]], [[SLOT]]]
; CHECK: [[CPI]]: ; CHECK: [[CPI]]:
; CHECK: .long n(SECREL32) ; CHECK: .long n(SECREL32)
define i8 @Z() { define i8 @Z() {
%1 = load i8, i8* @o %1 = load i8, i8* @o
ret i8 %1 ret i8 %1
} }
; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 ; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index ; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] ; CHECK-NEXT: ldr [[INDEX:r[0-9]]], [[[TLS_INDEX]]]
; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], [[[TEB]], #44]
; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] ; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], [[[TLS_POINTER]], [[INDEX]], lsl #2]
; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]] ; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
; CHECK-NEXT: ldrb r0, {{\[}}[[TLS]], [[SLOT]]] ; CHECK-NEXT: ldrb r0, [[[TLS]], [[SLOT]]]
; CHECK: [[CPI]]: ; CHECK: [[CPI]]:
; CHECK-NEXT: .long o(SECREL32) ; CHECK-NEXT: .long o(SECREL32)

llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll

; RUN: llc -verify-machineinstrs -mtriple=armebv8-linux-gnueabi -O0 %s -o - | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=armebv8-linux-gnueabi -O0 %s -o - | FileCheck %s
@x = global i64 10, align 8 @x = global i64 10, align 8
@y = global i64 20, align 8 @y = global i64 20, align 8
@z = global i64 20, align 8 @z = global i64 20, align 8
; CHECK_LABEL: main: ; CHECK_LABEL: main:
; CHECK: ldr [[R2:r[0-9]+]], {{\[}}[[R1:r[0-9]+]]{{\]}} ; CHECK: ldr [[R2:r[0-9]+]], [[[R1:r[0-9]+]]]
; CHECK-NEXT: ldr [[R1]], {{\[}}[[R1]], #4] ; CHECK-NEXT: ldr [[R1]], [[[R1]], #4]
; CHECK: mov [[R4:r[0-9]+]], [[R1]] ; CHECK: mov [[R4:r[0-9]+]], [[R1]]
; CHECK: ldr [[R5:r[0-9]+]], {{\[}}[[R1]]{{\]}} ; CHECK: ldr [[R5:r[0-9]+]], [[[R1]]]
; CHECK-NEXT: ldr [[R6:r[0-9]+]], {{\[}}[[R1]], #4] ; CHECK-NEXT: ldr [[R6:r[0-9]+]], [[[R1]], #4]
; CHECK: mov [[R7:r[0-9]+]], [[R6]] ; CHECK: mov [[R7:r[0-9]+]], [[R6]]
define arm_aapcs_vfpcc i32 @main() #0 { define arm_aapcs_vfpcc i32 @main() #0 {
entry: entry:
%retval = alloca i32, align 4 %retval = alloca i32, align 4
store i32 0, i32* %retval, align 4 store i32 0, i32* %retval, align 4
%0 = load i64, i64* @z, align 8 %0 = load i64, i64* @z, align 8
%1 = load i64, i64* @x, align 8 %1 = load i64, i64* @x, align 8
%2 = cmpxchg i64* @y, i64 %0, i64 %1 seq_cst seq_cst %2 = cmpxchg i64* @y, i64 %0, i64 %1 seq_cst seq_cst
%3 = extractvalue { i64, i1 } %2, 1 %3 = extractvalue { i64, i1 } %2, 1
ret i32 0 ret i32 0
} }

llvm/test/CodeGen/ARM/cmpxchg-O0.ll

; RUN: llc -verify-machineinstrs -mtriple=armv7-linux-gnu -O0 %s -o - | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=armv7-linux-gnu -O0 %s -o - | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=thumbv8-linux-gnu -O0 %s -o - | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=thumbv8-linux-gnu -O0 %s -o - | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=thumbv6m-none-eabi -O0 %s -o - | FileCheck %s --check-prefix=CHECK-T1 ; RUN: llc -verify-machineinstrs -mtriple=thumbv6m-none-eabi -O0 %s -o - | FileCheck %s --check-prefix=CHECK-T1
; CHECK-T1-NOT: ldrex ; CHECK-T1-NOT: ldrex
; CHECK-T1-NOT: strex ; CHECK-T1-NOT: strex
define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind { define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_8: ; CHECK-LABEL: test_cmpxchg_8:
; CHECK-DAG: mov [[ADDR:r[0-9]+]], r0 ; CHECK-DAG: mov [[ADDR:r[0-9]+]], r0
; CHECK-DAG: mov [[NEW:r[0-9]+]], r2 ; CHECK-DAG: mov [[NEW:r[0-9]+]], r2
; CHECK: dmb ish ; CHECK: dmb ish
; CHECK: uxtb [[DESIRED:r[0-9]+]], [[DESIRED]] ; CHECK: uxtb [[DESIRED:r[0-9]+]], [[DESIRED]]
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldrexb [[OLD:[lr0-9]+]], {{\[}}[[ADDR]]{{\]}} ; CHECK: ldrexb [[OLD:[lr0-9]+]], [[[ADDR]]]
; CHECK: cmp [[OLD]], [[DESIRED]] ; CHECK: cmp [[OLD]], [[DESIRED]]
; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]] ; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: strexb [[STATUS:r[0-9]+]], [[NEW]], {{\[}}[[ADDR]]{{\]}} ; CHECK: strexb [[STATUS:r[0-9]+]], [[NEW]], [[[ADDR]]]
; CHECK: cmp{{(\.w)?}} [[STATUS]], #0 ; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
; CHECK: bne [[RETRY]] ; CHECK: bne [[RETRY]]
; CHECK: [[DONE]]: ; CHECK: [[DONE]]:
; Materialisation of a boolean is done with sub/clz/lsr ; Materialisation of a boolean is done with sub/clz/lsr
; CHECK: uxtb [[CMP1:r[0-9]+]], [[DESIRED]] ; CHECK: uxtb [[CMP1:r[0-9]+]], [[DESIRED]]
; CHECK: sub{{(\.w|s)?}} [[CMP1]], [[OLD]], [[CMP1]] ; CHECK: sub{{(\.w|s)?}} [[CMP1]], [[OLD]], [[CMP1]]
; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]] ; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]]
; CHECK: lsr{{(s)?}} {{r[0-9]+}}, [[CMP2]], #5 ; CHECK: lsr{{(s)?}} {{r[0-9]+}}, [[CMP2]], #5
; CHECK: dmb ish ; CHECK: dmb ish
%res = cmpxchg i8* %addr, i8 %desired, i8 %new seq_cst monotonic %res = cmpxchg i8* %addr, i8 %desired, i8 %new seq_cst monotonic
ret { i8, i1 } %res ret { i8, i1 } %res
} }
define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind { define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_16: ; CHECK-LABEL: test_cmpxchg_16:
; CHECK-DAG: mov [[ADDR:r[0-9]+]], r0 ; CHECK-DAG: mov [[ADDR:r[0-9]+]], r0
; CHECK-DAG: mov [[NEW:r[0-9]+]], r2 ; CHECK-DAG: mov [[NEW:r[0-9]+]], r2
; CHECK: dmb ish ; CHECK: dmb ish
; CHECK: uxth [[DESIRED:r[0-9]+]], [[DESIRED]] ; CHECK: uxth [[DESIRED:r[0-9]+]], [[DESIRED]]
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldrexh [[OLD:[lr0-9]+]], {{\[}}[[ADDR]]{{\]}} ; CHECK: ldrexh [[OLD:[lr0-9]+]], [[[ADDR]]]
; CHECK: cmp [[OLD]], [[DESIRED]] ; CHECK: cmp [[OLD]], [[DESIRED]]
; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]] ; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: strexh [[STATUS:r[0-9]+]], [[NEW]], {{\[}}[[ADDR]]{{\]}} ; CHECK: strexh [[STATUS:r[0-9]+]], [[NEW]], [[[ADDR]]]
; CHECK: cmp{{(\.w)?}} [[STATUS]], #0 ; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
; CHECK: bne [[RETRY]] ; CHECK: bne [[RETRY]]
; CHECK: [[DONE]]: ; CHECK: [[DONE]]:
; Materialisation of a boolean is done with sub/clz/lsr ; Materialisation of a boolean is done with sub/clz/lsr
; CHECK: uxth [[CMP1:r[0-9]+]], [[DESIRED]] ; CHECK: uxth [[CMP1:r[0-9]+]], [[DESIRED]]
; CHECK: sub{{(\.w|s)?}} [[CMP1]], [[OLD]], [[CMP1]] ; CHECK: sub{{(\.w|s)?}} [[CMP1]], [[OLD]], [[CMP1]]
; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]] ; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]]
; CHECK: lsr{{(s)?}} {{r[0-9]+}}, [[CMP2]], #5 ; CHECK: lsr{{(s)?}} {{r[0-9]+}}, [[CMP2]], #5
; CHECK: dmb ish ; CHECK: dmb ish
%res = cmpxchg i16* %addr, i16 %desired, i16 %new seq_cst monotonic %res = cmpxchg i16* %addr, i16 %desired, i16 %new seq_cst monotonic
ret { i16, i1 } %res ret { i16, i1 } %res
} }
define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind { define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_32: ; CHECK-LABEL: test_cmpxchg_32:
; CHECK-DAG: mov [[ADDR:r[0-9]+]], r0 ; CHECK-DAG: mov [[ADDR:r[0-9]+]], r0
; CHECK-DAG: mov [[NEW:r[0-9]+]], r2 ; CHECK-DAG: mov [[NEW:r[0-9]+]], r2
; CHECK: dmb ish ; CHECK: dmb ish
; CHECK-NOT: uxt ; CHECK-NOT: uxt
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldrex [[OLD:r[0-9]+]], {{\[}}[[ADDR]]{{\]}} ; CHECK: ldrex [[OLD:r[0-9]+]], [[[ADDR]]]
; CHECK: cmp [[OLD]], [[DESIRED]] ; CHECK: cmp [[OLD]], [[DESIRED]]
; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]] ; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: strex [[STATUS:r[0-9]+]], [[NEW]], {{\[}}[[ADDR]]{{\]}} ; CHECK: strex [[STATUS:r[0-9]+]], [[NEW]], [[[ADDR]]]
; CHECK: cmp{{(\.w)?}} [[STATUS]], #0 ; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
; CHECK: bne [[RETRY]] ; CHECK: bne [[RETRY]]
; CHECK: [[DONE]]: ; CHECK: [[DONE]]:
; Materialisation of a boolean is done with sub/clz/lsr ; Materialisation of a boolean is done with sub/clz/lsr
; CHECK: sub{{(s)?}} [[CMP1:r[0-9]+]], [[OLD]], [[DESIRED]] ; CHECK: sub{{(s)?}} [[CMP1:r[0-9]+]], [[OLD]], [[DESIRED]]
; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]] ; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]]
; CHECK: lsr{{(s)?}} {{r[0-9]+}}, [[CMP2]], #5 ; CHECK: lsr{{(s)?}} {{r[0-9]+}}, [[CMP2]], #5
; CHECK: dmb ish ; CHECK: dmb ish
%res = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic %res = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
ret { i32, i1 } %res ret { i32, i1 } %res
} }
define { i64, i1 } @test_cmpxchg_64(i64* %addr, i64 %desired, i64 %new) nounwind { define { i64, i1 } @test_cmpxchg_64(i64* %addr, i64 %desired, i64 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_64: ; CHECK-LABEL: test_cmpxchg_64:
; CHECK: mov [[ADDR:r[0-9]+]], r0 ; CHECK: mov [[ADDR:r[0-9]+]], r0
; CHECK: dmb ish ; CHECK: dmb ish
; CHECK-NOT: uxt ; CHECK-NOT: uxt
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], {{\[}}[[ADDR]]{{\]}} ; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], [[[ADDR]]]
; CHECK: cmp [[OLDLO]], r6 ; CHECK: cmp [[OLDLO]], r6
; CHECK: cmpeq [[OLDHI]], r7 ; CHECK: cmpeq [[OLDHI]], r7
; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]] ; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: strexd [[STATUS:[lr0-9]+]], r8, r9, [r1] ; CHECK: strexd [[STATUS:[lr0-9]+]], r8, r9, [r1]
; CHECK: cmp{{(\.w)?}} [[STATUS]], #0 ; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
; CHECK: bne [[RETRY]] ; CHECK: bne [[RETRY]]
; CHECK: [[DONE]]: ; CHECK: [[DONE]]:
; CHECK: dmb ish ; CHECK: dmb ish
%res = cmpxchg i64* %addr, i64 %desired, i64 %new seq_cst monotonic %res = cmpxchg i64* %addr, i64 %desired, i64 %new seq_cst monotonic
ret { i64, i1 } %res ret { i64, i1 } %res
} }
define { i64, i1 } @test_nontrivial_args(i64* %addr, i64 %desired, i64 %new) { define { i64, i1 } @test_nontrivial_args(i64* %addr, i64 %desired, i64 %new) {
; CHECK-LABEL: test_nontrivial_args: ; CHECK-LABEL: test_nontrivial_args:
; CHECK: mov [[ADDR:r[0-9]+]], r0 ; CHECK: mov [[ADDR:r[0-9]+]], r0
; CHECK: dmb ish ; CHECK: dmb ish
; CHECK-NOT: uxt ; CHECK-NOT: uxt
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], {{\[}}[[ADDR]]{{\]}} ; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], [[[ADDR]]]
; CHECK: cmp [[OLDLO]], {{r[0-9]+}} ; CHECK: cmp [[OLDLO]], {{r[0-9]+}}
; CHECK: cmpeq [[OLDHI]], {{r[0-9]+}} ; CHECK: cmpeq [[OLDHI]], {{r[0-9]+}}
; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]] ; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: strexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, {{\[}}[[ADDR]]{{\]}} ; CHECK: strexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [[[ADDR]]]
; CHECK: cmp{{(\.w)?}} [[STATUS]], #0 ; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
; CHECK: bne [[RETRY]] ; CHECK: bne [[RETRY]]
; CHECK: [[DONE]]: ; CHECK: [[DONE]]:
; CHECK: dmb ish ; CHECK: dmb ish
%desired1 = add i64 %desired, 1 %desired1 = add i64 %desired, 1
%new1 = add i64 %new, 1 %new1 = add i64 %new, 1
%res = cmpxchg i64* %addr, i64 %desired1, i64 %new1 seq_cst seq_cst %res = cmpxchg i64* %addr, i64 %desired1, i64 %new1 seq_cst seq_cst
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llvm/test/CodeGen/ARM/constantpool-promote-ldrh.ll

; RUN: llc < %s -O0 -fast-isel=false -arm-promote-constant | FileCheck %s ; RUN: llc < %s -O0 -fast-isel=false -arm-promote-constant | FileCheck %s
; RUN: llc < %s -O0 -fast-isel=false -filetype=obj -arm-promote-constant ; RUN: llc < %s -O0 -fast-isel=false -filetype=obj -arm-promote-constant
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv6m-arm-linux-gnueabi" target triple = "thumbv6m-arm-linux-gnueabi"
@fn1.a = private unnamed_addr constant [4 x i16] [i16 6, i16 0, i16 0, i16 0], align 2 @fn1.a = private unnamed_addr constant [4 x i16] [i16 6, i16 0, i16 0, i16 0], align 2
; We must not try and emit this bad instruction: "ldrh r1, .LCPI0_0" ; We must not try and emit this bad instruction: "ldrh r1, .LCPI0_0"
; CHECK-LABEL: fn1: ; CHECK-LABEL: fn1:
; CHECK: adr [[base:r[0-9]+]], .LCPI0_0 ; CHECK: adr [[base:r[0-9]+]], .LCPI0_0
; CHECK-NOT: ldrh {{r[0-9]+}}, .LCPI0_0 ; CHECK-NOT: ldrh {{r[0-9]+}}, .LCPI0_0
; CHECK: ldrh r{{[0-9]+}}, {{\[}}[[base]]] ; CHECK: ldrh r{{[0-9]+}}, [[[base]]]
define hidden i32 @fn1() #0 { define hidden i32 @fn1() #0 {
entry: entry:
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 undef, i8* align 2 bitcast ([4 x i16]* @fn1.a to i8*), i32 8, i1 false) call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 undef, i8* align 2 bitcast ([4 x i16]* @fn1.a to i8*), i32 8, i1 false)
ret i32 undef ret i32 undef
} }
; Function Attrs: argmemonly nounwind ; Function Attrs: argmemonly nounwind
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1) declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1)
attributes #0 = { "target-features"="+strict-align" } attributes #0 = { "target-features"="+strict-align" }

llvm/test/CodeGen/ARM/fast-isel-call.ll

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
; ARM-DAG: str [[R4]], [sp] ; ARM-DAG: str [[R4]], [sp]
; ARM-DAG: and [[R5]], [[R5]], #255 ; ARM-DAG: and [[R5]], [[R5]], #255
; ARM-DAG: str [[R5]], [sp, #4] ; ARM-DAG: str [[R5]], [sp, #4]
; ARM: bl {{_?}}bar ; ARM: bl {{_?}}bar
; ARM-LONG-LABEL: @t10 ; ARM-LONG-LABEL: @t10
; ARM-LONG-MACHO: {{(movw)|(ldr)}} [[R1:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}} ; ARM-LONG-MACHO: {{(movw)|(ldr)}} [[R1:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}}
; ARM-LONG-MACHO: {{(movt [[R1]], :upper16:L_bar\$non_lazy_ptr)?}} ; ARM-LONG-MACHO: {{(movt [[R1]], :upper16:L_bar\$non_lazy_ptr)?}}
; ARM-LONG-MACHO: ldr [[R:r[0-9]+]], {{\[}}[[R1]]] ; ARM-LONG-MACHO: ldr [[R:r[0-9]+]], [[[R1]]]
; ARM-LONG-ELF: movw [[R1:r[0-9]*]], :lower16:bar ; ARM-LONG-ELF: movw [[R1:r[0-9]*]], :lower16:bar
; ARM-LONG-ELF: movt [[R1]], :upper16:bar ; ARM-LONG-ELF: movt [[R1]], :upper16:bar
; ARM-LONG-ELF: ldr [[R:r[0-9]+]], {{\[}}[[R1]]] ; ARM-LONG-ELF: ldr [[R:r[0-9]+]], [[[R1]]]
; ARM-LONG: blx [[R]] ; ARM-LONG: blx [[R]]
; THUMB-LABEL: @t10 ; THUMB-LABEL: @t10
; THUMB-DAG: movs [[R0:l?r[0-9]*]], #0 ; THUMB-DAG: movs [[R0:l?r[0-9]*]], #0
; THUMB-DAG: movs [[R1:l?r[0-9]*]], #248 ; THUMB-DAG: movs [[R1:l?r[0-9]*]], #248
; THUMB-DAG: movs [[R2:l?r[0-9]*]], #187 ; THUMB-DAG: movs [[R2:l?r[0-9]*]], #187
; THUMB-DAG: movs [[R3:l?r[0-9]*]], #28 ; THUMB-DAG: movs [[R3:l?r[0-9]*]], #28
; THUMB-DAG: movw [[R4:l?r[0-9]*]], #40 ; THUMB-DAG: movw [[R4:l?r[0-9]*]], #40
; THUMB-DAG: movw [[R5:l?r[0-9]*]], #186 ; THUMB-DAG: movw [[R5:l?r[0-9]*]], #186
; THUMB-DAG: and [[R0]], [[R0]], #255 ; THUMB-DAG: and [[R0]], [[R0]], #255
; THUMB-DAG: and [[R1]], [[R1]], #255 ; THUMB-DAG: and [[R1]], [[R1]], #255
; THUMB-DAG: and [[R2]], [[R2]], #255 ; THUMB-DAG: and [[R2]], [[R2]], #255
; THUMB-DAG: and [[R3]], [[R3]], #255 ; THUMB-DAG: and [[R3]], [[R3]], #255
; THUMB-DAG: and [[R4]], [[R4]], #255 ; THUMB-DAG: and [[R4]], [[R4]], #255
; THUMB-DAG: str.w [[R4]], [sp] ; THUMB-DAG: str.w [[R4]], [sp]
; THUMB-DAG: and [[R5]], [[R5]], #255 ; THUMB-DAG: and [[R5]], [[R5]], #255
; THUMB-DAG: str.w [[R5]], [sp, #4] ; THUMB-DAG: str.w [[R5]], [sp, #4]
; THUMB: bl {{_?}}bar ; THUMB: bl {{_?}}bar
; THUMB-LONG-LABEL: @t10 ; THUMB-LONG-LABEL: @t10
; THUMB-LONG: {{(movw)|(ldr.n)}} [[R1:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}} ; THUMB-LONG: {{(movw)|(ldr.n)}} [[R1:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}}
; THUMB-LONG: {{(movt [[R1]], :upper16:L_bar\$non_lazy_ptr)?}} ; THUMB-LONG: {{(movt [[R1]], :upper16:L_bar\$non_lazy_ptr)?}}
; THUMB-LONG: ldr{{(.w)?}} [[R:r[0-9]+]], {{\[}}[[R1]]{{\]}} ; THUMB-LONG: ldr{{(.w)?}} [[R:r[0-9]+]], [[[R1]]]
; THUMB-LONG: blx [[R]] ; THUMB-LONG: blx [[R]]
%call = call i32 @bar(i8 zeroext 0, i8 zeroext -8, i8 zeroext -69, i8 zeroext 28, i8 zeroext 40, i8 zeroext -70) %call = call i32 @bar(i8 zeroext 0, i8 zeroext -8, i8 zeroext -69, i8 zeroext 28, i8 zeroext 40, i8 zeroext -70)
ret i32 0 ret i32 0
} }
declare i32 @bar(i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext) declare i32 @bar(i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext)
define i32 @bar0(i32 %i) nounwind { define i32 @bar0(i32 %i) nounwind {
▲ Show 20 Lines • Show All 150 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 Lines
} }
define void @t4() nounwind ssp { define void @t4() nounwind ssp {
; ARM-LABEL: t4: ; ARM-LABEL: t4:
; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} ; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} ; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0] ; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0]
; ARM-MACHO-NEXT: ldr [[REG1:r[0-9]+]], {{\[}}[[REG0]], #16] ; ARM-MACHO-NEXT: ldr [[REG1:r[0-9]+]], [[[REG0]], #16]
; ARM-MACHO-NEXT: str [[REG1]], {{\[}}[[REG0]], #4] ; ARM-MACHO-NEXT: str [[REG1]], [[[REG0]], #4]
; ARM-MACHO-NEXT: ldr [[REG2:r[0-9]+]], {{\[}}[[REG0]], #20] ; ARM-MACHO-NEXT: ldr [[REG2:r[0-9]+]], [[[REG0]], #20]
; ARM-MACHO-NEXT: str [[REG2]], {{\[}}[[REG0]], #8] ; ARM-MACHO-NEXT: str [[REG2]], [[[REG0]], #8]
; ARM-MACHO-NEXT: ldrh [[REG3:r[0-9]+]], {{\[}}[[REG0]], #24] ; ARM-MACHO-NEXT: ldrh [[REG3:r[0-9]+]], [[[REG0]], #24]
; ARM-MACHO-NEXT: strh [[REG3]], {{\[}}[[REG0]], #12] ; ARM-MACHO-NEXT: strh [[REG3]], [[[REG0]], #12]
; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp ; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp
; ARM-ELF: movt [[REG0]], :upper16:temp ; ARM-ELF: movt [[REG0]], :upper16:temp
; ARM: bx lr ; ARM: bx lr
; THUMB-LABEL: t4: ; THUMB-LABEL: t4:
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}} ; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} ; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; THUMB: ldr [[REG1:r[0-9]+]], [r0] ; THUMB: ldr [[REG1:r[0-9]+]], [r0]
; THUMB: ldr [[REG2:r[0-9]+]], {{\[}}[[REG1]], #16] ; THUMB: ldr [[REG2:r[0-9]+]], [[[REG1]], #16]
; THUMB: str [[REG2]], {{\[}}[[REG1]], #4] ; THUMB: str [[REG2]], [[[REG1]], #4]
; THUMB: ldr [[REG3:r[0-9]+]], {{\[}}[[REG1]], #20] ; THUMB: ldr [[REG3:r[0-9]+]], [[[REG1]], #20]
; THUMB: str [[REG3]], {{\[}}[[REG1]], #8] ; THUMB: str [[REG3]], [[[REG1]], #8]
; THUMB: ldrh [[REG4:r[0-9]+]], {{\[}}[[REG1]], #24] ; THUMB: ldrh [[REG4:r[0-9]+]], [[[REG1]], #24]
; THUMB: strh [[REG4]], {{\[}}[[REG1]], #12] ; THUMB: strh [[REG4]], [[[REG1]], #12]
; THUMB: bx lr ; THUMB: bx lr
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false) call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false)
ret void ret void
} }
declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
define void @t5() nounwind ssp { define void @t5() nounwind ssp {
; ARM-LABEL: t5: ; ARM-LABEL: t5:
; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} ; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} ; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0] ; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0]
; ARM-MACHO: ldrh [[REG1:r[0-9]+]], {{\[}}[[REG0]], #16] ; ARM-MACHO: ldrh [[REG1:r[0-9]+]], [[[REG0]], #16]
; ARM-MACHO-NEXT: strh [[REG1]], {{\[}}[[REG0]], #4] ; ARM-MACHO-NEXT: strh [[REG1]], [[[REG0]], #4]
; ARM-MACHO-NEXT: ldrh [[REG2:r[0-9]+]], {{\[}}[[REG0]], #18] ; ARM-MACHO-NEXT: ldrh [[REG2:r[0-9]+]], [[[REG0]], #18]
; ARM-MACHO-NEXT: strh [[REG2]], {{\[}}[[REG0]], #6] ; ARM-MACHO-NEXT: strh [[REG2]], [[[REG0]], #6]
; ARM-MACHO-NEXT: ldrh [[REG3:r[0-9]+]], {{\[}}[[REG0]], #20] ; ARM-MACHO-NEXT: ldrh [[REG3:r[0-9]+]], [[[REG0]], #20]
; ARM-MACHO-NEXT: strh [[REG3]], {{\[}}[[REG0]], #8] ; ARM-MACHO-NEXT: strh [[REG3]], [[[REG0]], #8]
; ARM-MACHO-NEXT: ldrh [[REG4:r[0-9]+]], {{\[}}[[REG0]], #22] ; ARM-MACHO-NEXT: ldrh [[REG4:r[0-9]+]], [[[REG0]], #22]
; ARM-MACHO-NEXT: strh [[REG4]], {{\[}}[[REG0]], #10] ; ARM-MACHO-NEXT: strh [[REG4]], [[[REG0]], #10]
; ARM-MACHO-NEXT: ldrh [[REG5:r[0-9]+]], {{\[}}[[REG0]], #24] ; ARM-MACHO-NEXT: ldrh [[REG5:r[0-9]+]], [[[REG0]], #24]
; ARM-MACHO-NEXT: strh [[REG5]], {{\[}}[[REG0]], #12] ; ARM-MACHO-NEXT: strh [[REG5]], [[[REG0]], #12]
; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp ; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp
; ARM-ELF: movt [[REG0]], :upper16:temp ; ARM-ELF: movt [[REG0]], :upper16:temp
; ARM: bx lr ; ARM: bx lr
; THUMB-LABEL: t5: ; THUMB-LABEL: t5:
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}} ; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} ; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; THUMB: ldr [[REG1:r[0-9]+]], [r0] ; THUMB: ldr [[REG1:r[0-9]+]], [r0]
; THUMB: ldrh [[REG2:r[0-9]+]], {{\[}}[[REG1]], #16] ; THUMB: ldrh [[REG2:r[0-9]+]], [[[REG1]], #16]
; THUMB: strh [[REG2]], {{\[}}[[REG1]], #4] ; THUMB: strh [[REG2]], [[[REG1]], #4]
; THUMB: ldrh [[REG3:r[0-9]+]], {{\[}}[[REG1]], #18] ; THUMB: ldrh [[REG3:r[0-9]+]], [[[REG1]], #18]
; THUMB: strh [[REG3]], {{\[}}[[REG1]], #6] ; THUMB: strh [[REG3]], [[[REG1]], #6]
; THUMB: ldrh [[REG4:r[0-9]+]], {{\[}}[[REG1]], #20] ; THUMB: ldrh [[REG4:r[0-9]+]], [[[REG1]], #20]
; THUMB: strh [[REG4]], {{\[}}[[REG1]], #8] ; THUMB: strh [[REG4]], [[[REG1]], #8]
; THUMB: ldrh [[REG5:r[0-9]+]], {{\[}}[[REG1]], #22] ; THUMB: ldrh [[REG5:r[0-9]+]], [[[REG1]], #22]
; THUMB: strh [[REG5]], {{\[}}[[REG1]], #10] ; THUMB: strh [[REG5]], [[[REG1]], #10]
; THUMB: ldrh [[REG6:r[0-9]+]], {{\[}}[[REG1]], #24] ; THUMB: ldrh [[REG6:r[0-9]+]], [[[REG1]], #24]
; THUMB: strh [[REG6]], {{\[}}[[REG1]], #12] ; THUMB: strh [[REG6]], [[[REG1]], #12]
; THUMB: bx lr ; THUMB: bx lr
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 2 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false) call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 2 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false)
ret void ret void
} }
define void @t6() nounwind ssp { define void @t6() nounwind ssp {
; ARM-LABEL: t6: ; ARM-LABEL: t6:
; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} ; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} ; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0] ; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0]
; ARM-MACHO: ldrb [[REG1:r[0-9]+]], {{\[}}[[REG0]], #16] ; ARM-MACHO: ldrb [[REG1:r[0-9]+]], [[[REG0]], #16]
; ARM-MACHO-NEXT: strb [[REG1]], {{\[}}[[REG0]], #4] ; ARM-MACHO-NEXT: strb [[REG1]], [[[REG0]], #4]
; ARM-MACHO-NEXT: ldrb [[REG2:r[0-9]+]], {{\[}}[[REG0]], #17] ; ARM-MACHO-NEXT: ldrb [[REG2:r[0-9]+]], [[[REG0]], #17]
; ARM-MACHO-NEXT: strb [[REG2]], {{\[}}[[REG0]], #5] ; ARM-MACHO-NEXT: strb [[REG2]], [[[REG0]], #5]
; ARM-MACHO-NEXT: ldrb [[REG3:r[0-9]+]], {{\[}}[[REG0]], #18] ; ARM-MACHO-NEXT: ldrb [[REG3:r[0-9]+]], [[[REG0]], #18]
; ARM-MACHO-NEXT: strb [[REG3]], {{\[}}[[REG0]], #6] ; ARM-MACHO-NEXT: strb [[REG3]], [[[REG0]], #6]
; ARM-MACHO-NEXT: ldrb [[REG4:r[0-9]+]], {{\[}}[[REG0]], #19] ; ARM-MACHO-NEXT: ldrb [[REG4:r[0-9]+]], [[[REG0]], #19]
; ARM-MACHO-NEXT: strb [[REG4]], {{\[}}[[REG0]], #7] ; ARM-MACHO-NEXT: strb [[REG4]], [[[REG0]], #7]
; ARM-MACHO-NEXT: ldrb [[REG5:r[0-9]+]], {{\[}}[[REG0]], #20] ; ARM-MACHO-NEXT: ldrb [[REG5:r[0-9]+]], [[[REG0]], #20]
; ARM-MACHO-NEXT: strb [[REG5]], {{\[}}[[REG0]], #8] ; ARM-MACHO-NEXT: strb [[REG5]], [[[REG0]], #8]
; ARM-MACHO-NEXT: ldrb [[REG6:r[0-9]+]], {{\[}}[[REG0]], #21] ; ARM-MACHO-NEXT: ldrb [[REG6:r[0-9]+]], [[[REG0]], #21]
; ARM-MACHO-NEXT: strb [[REG6]], {{\[}}[[REG0]], #9] ; ARM-MACHO-NEXT: strb [[REG6]], [[[REG0]], #9]
; ARM-MACHO-NEXT: ldrb [[REG7:r[0-9]+]], {{\[}}[[REG0]], #22] ; ARM-MACHO-NEXT: ldrb [[REG7:r[0-9]+]], [[[REG0]], #22]
; ARM-MACHO-NEXT: strb [[REG7]], {{\[}}[[REG0]], #10] ; ARM-MACHO-NEXT: strb [[REG7]], [[[REG0]], #10]
; ARM-MACHO-NEXT: ldrb [[REG8:r[0-9]+]], {{\[}}[[REG0]], #23] ; ARM-MACHO-NEXT: ldrb [[REG8:r[0-9]+]], [[[REG0]], #23]
; ARM-MACHO-NEXT: strb [[REG8]], {{\[}}[[REG0]], #11] ; ARM-MACHO-NEXT: strb [[REG8]], [[[REG0]], #11]
; ARM-MACHO-NEXT: ldrb [[REG9:r[0-9]+]], {{\[}}[[REG0]], #24] ; ARM-MACHO-NEXT: ldrb [[REG9:r[0-9]+]], [[[REG0]], #24]
; ARM-MACHO-NEXT: strb [[REG9]], {{\[}}[[REG0]], #12] ; ARM-MACHO-NEXT: strb [[REG9]], [[[REG0]], #12]
; ARM-MACHO-NEXT: ldrb [[REG10:r[0-9]+]], {{\[}}[[REG0]], #25] ; ARM-MACHO-NEXT: ldrb [[REG10:r[0-9]+]], [[[REG0]], #25]
; ARM-MACHO-NEXT: strb [[REG10]], {{\[}}[[REG0]], #13] ; ARM-MACHO-NEXT: strb [[REG10]], [[[REG0]], #13]
; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp ; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp
; ARM-ELF: movt [[REG0]], :upper16:temp ; ARM-ELF: movt [[REG0]], :upper16:temp
; ARM: bx lr ; ARM: bx lr
; THUMB-LABEL: t6: ; THUMB-LABEL: t6:
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}} ; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} ; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; THUMB: ldr [[REG0:r[0-9]+]], [r0] ; THUMB: ldr [[REG0:r[0-9]+]], [r0]
; THUMB: ldrb [[REG2:r[0-9]+]], {{\[}}[[REG0]], #16] ; THUMB: ldrb [[REG2:r[0-9]+]], [[[REG0]], #16]
; THUMB: strb [[REG2]], {{\[}}[[REG0]], #4] ; THUMB: strb [[REG2]], [[[REG0]], #4]
; THUMB: ldrb [[REG3:r[0-9]+]], {{\[}}[[REG0]], #17] ; THUMB: ldrb [[REG3:r[0-9]+]], [[[REG0]], #17]
; THUMB: strb [[REG3]], {{\[}}[[REG0]], #5] ; THUMB: strb [[REG3]], [[[REG0]], #5]
; THUMB: ldrb [[REG4:r[0-9]+]], {{\[}}[[REG0]], #18] ; THUMB: ldrb [[REG4:r[0-9]+]], [[[REG0]], #18]
; THUMB: strb [[REG4]], {{\[}}[[REG0]], #6] ; THUMB: strb [[REG4]], [[[REG0]], #6]
; THUMB: ldrb [[REG5:r[0-9]+]], {{\[}}[[REG0]], #19] ; THUMB: ldrb [[REG5:r[0-9]+]], [[[REG0]], #19]
; THUMB: strb [[REG5]], {{\[}}[[REG0]], #7] ; THUMB: strb [[REG5]], [[[REG0]], #7]
; THUMB: ldrb [[REG6:r[0-9]+]], {{\[}}[[REG0]], #20] ; THUMB: ldrb [[REG6:r[0-9]+]], [[[REG0]], #20]
; THUMB: strb [[REG6]], {{\[}}[[REG0]], #8] ; THUMB: strb [[REG6]], [[[REG0]], #8]
; THUMB: ldrb [[REG7:r[0-9]+]], {{\[}}[[REG0]], #21] ; THUMB: ldrb [[REG7:r[0-9]+]], [[[REG0]], #21]
; THUMB: strb [[REG7]], {{\[}}[[REG0]], #9] ; THUMB: strb [[REG7]], [[[REG0]], #9]
; THUMB: ldrb [[REG8:r[0-9]+]], {{\[}}[[REG0]], #22] ; THUMB: ldrb [[REG8:r[0-9]+]], [[[REG0]], #22]
; THUMB: strb [[REG8]], {{\[}}[[REG0]], #10] ; THUMB: strb [[REG8]], [[[REG0]], #10]
; THUMB: ldrb [[REG9:r[0-9]+]], {{\[}}[[REG0]], #23] ; THUMB: ldrb [[REG9:r[0-9]+]], [[[REG0]], #23]
; THUMB: strb [[REG9]], {{\[}}[[REG0]], #11] ; THUMB: strb [[REG9]], [[[REG0]], #11]
; THUMB: ldrb [[REG10:r[0-9]+]], {{\[}}[[REG0]], #24] ; THUMB: ldrb [[REG10:r[0-9]+]], [[[REG0]], #24]
; THUMB: strb [[REG10]], {{\[}}[[REG0]], #12] ; THUMB: strb [[REG10]], [[[REG0]], #12]
; THUMB: ldrb [[REG11:r[0-9]+]], {{\[}}[[REG0]], #25] ; THUMB: ldrb [[REG11:r[0-9]+]], [[[REG0]], #25]
; THUMB: strb [[REG11]], {{\[}}[[REG0]], #13] ; THUMB: strb [[REG11]], [[[REG0]], #13]
; THUMB: bx lr ; THUMB: bx lr
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 1 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false) call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 1 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false)
ret void ret void
} }
; rdar://13202135 ; rdar://13202135
define void @t7() nounwind ssp { define void @t7() nounwind ssp {
; Just make sure this doesn't assert when we have an odd length and an alignment of 2. ; Just make sure this doesn't assert when we have an odd length and an alignment of 2.
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llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
} }
define void @t10(i32* nocapture %ptr) nounwind { define void @t10(i32* nocapture %ptr) nounwind {
entry: entry:
; THUMB-LABEL: t10: ; THUMB-LABEL: t10:
%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -1 %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -1
store i32 0, i32* %add.ptr, align 4 store i32 0, i32* %add.ptr, align 4
; THUMB: mov [[REG:r[0-9]+]], r0 ; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: str r{{[0-9]}}, {{\[}}[[REG]], #-4] ; THUMB: str r{{[0-9]}}, [[[REG]], #-4]
ret void ret void
} }
define void @t11(i32* nocapture %ptr) nounwind { define void @t11(i32* nocapture %ptr) nounwind {
entry: entry:
; THUMB-LABEL: t11: ; THUMB-LABEL: t11:
%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -63 %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -63
store i32 0, i32* %add.ptr, align 4 store i32 0, i32* %add.ptr, align 4
; THUMB: mov [[REG:r[0-9]+]], r0 ; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: str r{{[0-9]}}, {{\[}}[[REG]], #-252] ; THUMB: str r{{[0-9]}}, [[[REG]], #-252]
ret void ret void
} }
define void @t12(i32* nocapture %ptr) nounwind { define void @t12(i32* nocapture %ptr) nounwind {
entry: entry:
; THUMB-LABEL: t12: ; THUMB-LABEL: t12:
%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -64 %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -64
store i32 0, i32* %add.ptr, align 4 store i32 0, i32* %add.ptr, align 4
; THUMB: mov [[PTR:r[0-9]+]], r0 ; THUMB: mov [[PTR:r[0-9]+]], r0
; THUMB: movs [[VAL:r[0-9]+]], #0 ; THUMB: movs [[VAL:r[0-9]+]], #0
; THUMB: movw [[REG:r[0-9]+]], #65280 ; THUMB: movw [[REG:r[0-9]+]], #65280
; THUMB: movt [[REG]], #65535 ; THUMB: movt [[REG]], #65535
; THUMB: add [[PTR]], [[REG]] ; THUMB: add [[PTR]], [[REG]]
; THUMB: str [[VAL]], {{\[}}[[PTR]]] ; THUMB: str [[VAL]], [[[PTR]]]
ret void ret void
} }
define void @t13(i16* nocapture %ptr) nounwind { define void @t13(i16* nocapture %ptr) nounwind {
entry: entry:
; THUMB-LABEL: t13: ; THUMB-LABEL: t13:
%add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -1 %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -1
store i16 0, i16* %add.ptr, align 2 store i16 0, i16* %add.ptr, align 2
; THUMB: mov [[REG:r[0-9]+]], r0 ; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: strh r{{[0-9]}}, {{\[}}[[REG]], #-2] ; THUMB: strh r{{[0-9]}}, [[[REG]], #-2]
ret void ret void
} }
define void @t14(i16* nocapture %ptr) nounwind { define void @t14(i16* nocapture %ptr) nounwind {
entry: entry:
; THUMB-LABEL: t14: ; THUMB-LABEL: t14:
%add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -127 %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -127
store i16 0, i16* %add.ptr, align 2 store i16 0, i16* %add.ptr, align 2
; THUMB: mov [[REG:r[0-9]+]], r0 ; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: strh r{{[0-9]}}, {{\[}}[[REG]], #-254] ; THUMB: strh r{{[0-9]}}, [[[REG]], #-254]
ret void ret void
} }
define void @t15(i16* nocapture %ptr) nounwind { define void @t15(i16* nocapture %ptr) nounwind {
entry: entry:
; THUMB-LABEL: t15: ; THUMB-LABEL: t15:
%add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -128 %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -128
store i16 0, i16* %add.ptr, align 2 store i16 0, i16* %add.ptr, align 2
; THUMB: mov [[PTR:r[0-9]+]], r0 ; THUMB: mov [[PTR:r[0-9]+]], r0
; THUMB: movs [[VAL:r[0-9]+]], #0 ; THUMB: movs [[VAL:r[0-9]+]], #0
; THUMB: movw [[REG:r[0-9]+]], #65280 ; THUMB: movw [[REG:r[0-9]+]], #65280
; THUMB: movt [[REG]], #65535 ; THUMB: movt [[REG]], #65535
; THUMB: add [[PTR]], [[REG]] ; THUMB: add [[PTR]], [[REG]]
; THUMB: strh [[VAL]], {{\[}}[[PTR]]] ; THUMB: strh [[VAL]], [[[PTR]]]
ret void ret void
} }
define void @t16(i8* nocapture %ptr) nounwind { define void @t16(i8* nocapture %ptr) nounwind {
entry: entry:
; THUMB-LABEL: t16: ; THUMB-LABEL: t16:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -1 %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -1
store i8 0, i8* %add.ptr, align 1 store i8 0, i8* %add.ptr, align 1
; THUMB: mov [[REG:r[0-9]+]], r0 ; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: strb r{{[0-9]}}, {{\[}}[[REG]], #-1] ; THUMB: strb r{{[0-9]}}, [[[REG]], #-1]
ret void ret void
} }
define void @t17(i8* nocapture %ptr) nounwind { define void @t17(i8* nocapture %ptr) nounwind {
entry: entry:
; THUMB-LABEL: t17: ; THUMB-LABEL: t17:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -255 %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -255
store i8 0, i8* %add.ptr, align 1 store i8 0, i8* %add.ptr, align 1
; THUMB: mov [[REG:r[0-9]+]], r0 ; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: strb r{{[0-9]}}, {{\[}}[[REG]], #-255] ; THUMB: strb r{{[0-9]}}, [[[REG]], #-255]
ret void ret void
} }
define void @t18(i8* nocapture %ptr) nounwind { define void @t18(i8* nocapture %ptr) nounwind {
entry: entry:
; THUMB-LABEL: t18: ; THUMB-LABEL: t18:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -256 %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -256
store i8 0, i8* %add.ptr, align 1 store i8 0, i8* %add.ptr, align 1
; THUMB: mov [[PTR:r[0-9]+]], r0 ; THUMB: mov [[PTR:r[0-9]+]], r0
; THUMB: movs [[VAL]], #0 ; THUMB: movs [[VAL]], #0
; THUMB: movw [[REG:r[0-9]+]], #65280 ; THUMB: movw [[REG:r[0-9]+]], #65280
; THUMB: movt [[REG]], #65535 ; THUMB: movt [[REG]], #65535
; THUMB: add [[PTR]], [[REG]] ; THUMB: add [[PTR]], [[REG]]
; THUMB: strb [[VAL]], {{\[}}[[PTR]]] ; THUMB: strb [[VAL]], [[[PTR]]]
ret void ret void
} }

llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
entry: entry:
; ARM-LABEL: t10: ; ARM-LABEL: t10:
%add.ptr = getelementptr inbounds i16, i16* %a, i64 -128 %add.ptr = getelementptr inbounds i16, i16* %a, i64 -128
store i16 0, i16* %add.ptr, align 2 store i16 0, i16* %add.ptr, align 2
; ARM: mov r1, r0 ; ARM: mov r1, r0
; ARM: movw [[REG1:r[0-9]+]], #0 ; ARM: movw [[REG1:r[0-9]+]], #0
; ARM: mvn [[REG2:r[0-9]+]], #255 ; ARM: mvn [[REG2:r[0-9]+]], #255
; ARM: add [[REG0:r[0-9]+]], r1, [[REG2]] ; ARM: add [[REG0:r[0-9]+]], r1, [[REG2]]
; ARM: strh [[REG1]], {{\[}}[[REG0]]] ; ARM: strh [[REG1]], [[[REG0]]]
ret void ret void
} }
define void @t11(i16* nocapture %a) nounwind uwtable ssp { define void @t11(i16* nocapture %a) nounwind uwtable ssp {
entry: entry:
; ARM-LABEL: t11: ; ARM-LABEL: t11:
%add.ptr = getelementptr inbounds i16, i16* %a, i64 8 %add.ptr = getelementptr inbounds i16, i16* %a, i64 8
store i16 0, i16* %add.ptr, align 2 store i16 0, i16* %add.ptr, align 2
; ARM: movw [[REG1:r[0-9]+]], #0 ; ARM: movw [[REG1:r[0-9]+]], #0
; ARM: strh [[REG1]], [{{r[0-9]+}}, #16] ; ARM: strh [[REG1]], [{{r[0-9]+}}, #16]
ret void ret void
} }
; mov r1, #256 ; mov r1, #256
; strh r2, [r0, r1] ; strh r2, [r0, r1]
define void @t12(i16* nocapture %a) nounwind uwtable ssp { define void @t12(i16* nocapture %a) nounwind uwtable ssp {
entry: entry:
; ARM-LABEL: t12: ; ARM-LABEL: t12:
%add.ptr = getelementptr inbounds i16, i16* %a, i64 128 %add.ptr = getelementptr inbounds i16, i16* %a, i64 128
store i16 0, i16* %add.ptr, align 2 store i16 0, i16* %add.ptr, align 2
; ARM: mov r1, r0 ; ARM: mov r1, r0
; ARM: movw [[REG1:r[0-9]+]], #0 ; ARM: movw [[REG1:r[0-9]+]], #0
; ARM: add [[REG0:r[0-9]+]], r1, #256 ; ARM: add [[REG0:r[0-9]+]], r1, #256
; ARM: strh [[REG1]], {{\[}}[[REG0]]] ; ARM: strh [[REG1]], [[[REG0]]]
ret void ret void
} }
define signext i8 @t13(i8* nocapture %a) nounwind uwtable readonly ssp { define signext i8 @t13(i8* nocapture %a) nounwind uwtable readonly ssp {
entry: entry:
; ARM-LABEL: t13: ; ARM-LABEL: t13:
%add.ptr = getelementptr inbounds i8, i8* %a, i64 -8 %add.ptr = getelementptr inbounds i8, i8* %a, i64 -8
%0 = load i8, i8* %add.ptr, align 2 %0 = load i8, i8* %add.ptr, align 2
Show All 23 Lines

llvm/test/CodeGen/ARM/fast-isel-vararg.ll

Show All 12 Linesentry:
%0 = load i32, i32* %i, align 4 %0 = load i32, i32* %i, align 4
%1 = load i32, i32* %j, align 4 %1 = load i32, i32* %j, align 4
%2 = load i32, i32* %k, align 4 %2 = load i32, i32* %k, align 4
%3 = load i32, i32* %m, align 4 %3 = load i32, i32* %m, align 4
%4 = load i32, i32* %n, align 4 %4 = load i32, i32* %n, align 4
; ARM: VarArg ; ARM: VarArg
; ARM: mov [[FP:r[0-9]+]], sp ; ARM: mov [[FP:r[0-9]+]], sp
; ARM: sub sp, sp, #32 ; ARM: sub sp, sp, #32
; ARM: ldr r1, {{\[}}[[FP]], #-4] ; ARM: ldr r1, [[[FP]], #-4]
; ARM: ldr r2, {{\[}}[[FP]], #-8] ; ARM: ldr r2, [[[FP]], #-8]
; ARM: ldr r3, {{\[}}[[FP]], #-12] ; ARM: ldr r3, [[[FP]], #-12]
; ARM: ldr [[Ra:r[0-9]+|lr]], [sp, #16] ; ARM: ldr [[Ra:r[0-9]+|lr]], [sp, #16]
; ARM: ldr [[Rb:[lr]+[0-9]*]], [sp, #12] ; ARM: ldr [[Rb:[lr]+[0-9]*]], [sp, #12]
; ARM: movw r0, #5 ; ARM: movw r0, #5
; ARM: str [[Ra]], [sp] ; ARM: str [[Ra]], [sp]
; ARM: str [[Rb]], [sp, #4] ; ARM: str [[Rb]], [sp, #4]
; ARM: bl {{_?CallVariadic}} ; ARM: bl {{_?CallVariadic}}
; THUMB: sub sp, #32 ; THUMB: sub sp, #32
; THUMB: ldr r1, [sp, #28] ; THUMB: ldr r1, [sp, #28]
Show All 14 Lines

llvm/test/CodeGen/ARM/fast-isel.ll

Show First 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
; Note that relocations are either movw/movt or constant pool ; Note that relocations are either movw/movt or constant pool
; loads. Different platforms will select different approaches. ; loads. Different platforms will select different approaches.
; THUMB: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr.n r0, .LCPI)}} ; THUMB: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
; THUMB: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}} ; THUMB: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}}
; THUMB: ldr [[REG:r[0-9]+]], [r0] ; THUMB: ldr [[REG:r[0-9]+]], [r0]
; THUMB: ldr [[REG1:r[0-9]+]], {{\[}}[[REG]]] ; THUMB: ldr [[REG1:r[0-9]+]], [[[REG]]]
; THUMB: adds [[REG1]], #1 ; THUMB: adds [[REG1]], #1
; THUMB: {{(movw r1, :lower16:L_test4g\$non_lazy_ptr)|(ldr.n r0, .LCPI)}} ; THUMB: {{(movw r1, :lower16:L_test4g\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
; THUMB: {{(movt r1, :upper16:L_test4g\$non_lazy_ptr)?}} ; THUMB: {{(movt r1, :upper16:L_test4g\$non_lazy_ptr)?}}
; THUMB: ldr [[REG2:r[0-9]+]], [r1] ; THUMB: ldr [[REG2:r[0-9]+]], [r1]
; THUMB: str [[REG1]], {{\[}}[[REG2]]] ; THUMB: str [[REG1]], [[[REG2]]]
; ARM-MACHO: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr r0, .LCPI)}} ; ARM-MACHO: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr r0, .LCPI)}}
; ARM-MACHO: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}} ; ARM-MACHO: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}}
; ARM-MACHO: ldr [[REG:r[0-9]+]], [r0] ; ARM-MACHO: ldr [[REG:r[0-9]+]], [r0]
; ARM-ELF: movw [[REG:r[0-9]+]], :lower16:test4g ; ARM-ELF: movw [[REG:r[0-9]+]], :lower16:test4g
; ARM-ELF: movt [[REG]], :upper16:test4g ; ARM-ELF: movt [[REG]], :upper16:test4g
; ARM: ldr [[REG1:r[0-9]+]], {{\[}}[[REG]]] ; ARM: ldr [[REG1:r[0-9]+]], [[[REG]]]
; ARM: add [[REG2:r[0-9]+]], [[REG1]], #1 ; ARM: add [[REG2:r[0-9]+]], [[REG1]], #1
; ARM-MACHO: {{(movw r1, :lower16:L_test4g\$non_lazy_ptr)|(ldr r0, .LCPI)}} ; ARM-MACHO: {{(movw r1, :lower16:L_test4g\$non_lazy_ptr)|(ldr r0, .LCPI)}}
; ARM-MACHO: {{(movt r1, :upper16:L_test4g\$non_lazy_ptr)?}} ; ARM-MACHO: {{(movt r1, :upper16:L_test4g\$non_lazy_ptr)?}}
; ARM-MACHO: ldr [[REG3:r[0-9]+]], [r1] ; ARM-MACHO: ldr [[REG3:r[0-9]+]], [r1]
; ARM-ELF: movw [[REG3:r[0-9]+]], :lower16:test4g ; ARM-ELF: movw [[REG3:r[0-9]+]], :lower16:test4g
; ARM-ELF: movt [[REG3]], :upper16:test4g ; ARM-ELF: movt [[REG3]], :upper16:test4g
; ARM: str [[REG2]], {{\[}}[[REG3]]] ; ARM: str [[REG2]], [[[REG3]]]
} }
; ARM: @urem_fold ; ARM: @urem_fold
; THUMB: @urem_fold ; THUMB: @urem_fold
; ARM: and r0, r0, #31 ; ARM: and r0, r0, #31
; THUMB: and r0, r0, #31 ; THUMB: and r0, r0, #31
define i32 @urem_fold(i32 %a) nounwind { define i32 @urem_fold(i32 %a) nounwind {
%rem = urem i32 %a, 32 %rem = urem i32 %a, 32
Show All 14 Lines

llvm/test/CodeGen/ARM/fp16-load-store.ll

Show All 18 Lines; CHECK: vldr.16 {{s[0-9]+}}, [r0, #510]
store half %load, half* %out store half %load, half* %out
ret void ret void
} }
define void @load_256(half* %in, half* %out) { define void @load_256(half* %in, half* %out) {
entry: entry:
; CHECK-LABEL: load_256: ; CHECK-LABEL: load_256:
; CHECK: add [[ADDR:r[0-9]+]], r0, #512 ; CHECK: add [[ADDR:r[0-9]+]], r0, #512
; CHECK: vldr.16 {{s[0-9]+}}, {{\[}}[[ADDR]]{{\]}} ; CHECK: vldr.16 {{s[0-9]+}}, [[[ADDR]]]
%arrayidx = getelementptr inbounds half, half* %in, i32 256 %arrayidx = getelementptr inbounds half, half* %in, i32 256
%load = load half, half* %arrayidx, align 2 %load = load half, half* %arrayidx, align 2
store half %load, half* %out store half %load, half* %out
ret void ret void
} }
define void @load_neg_255(half* %in, half* %out) { define void @load_neg_255(half* %in, half* %out) {
entry: entry:
; CHECK-LABEL: load_neg_255: ; CHECK-LABEL: load_neg_255:
; CHECK: vldr.16 {{s[0-9]+}}, [r0, #-510] ; CHECK: vldr.16 {{s[0-9]+}}, [r0, #-510]
%arrayidx = getelementptr inbounds half, half* %in, i32 -255 %arrayidx = getelementptr inbounds half, half* %in, i32 -255
%load = load half, half* %arrayidx, align 2 %load = load half, half* %arrayidx, align 2
store half %load, half* %out store half %load, half* %out
ret void ret void
} }
define void @load_neg_256(half* %in, half* %out) { define void @load_neg_256(half* %in, half* %out) {
entry: entry:
; CHECK-LABEL: load_neg_256: ; CHECK-LABEL: load_neg_256:
; CHECK: sub [[ADDR:r[0-9]+]], r0, #512 ; CHECK: sub [[ADDR:r[0-9]+]], r0, #512
; CHECK: vldr.16 {{s[0-9]+}}, {{\[}}[[ADDR]]{{\]}} ; CHECK: vldr.16 {{s[0-9]+}}, [[[ADDR]]]
%arrayidx = getelementptr inbounds half, half* %in, i32 -256 %arrayidx = getelementptr inbounds half, half* %in, i32 -256
%load = load half, half* %arrayidx, align 2 %load = load half, half* %arrayidx, align 2
store half %load, half* %out store half %load, half* %out
ret void ret void
} }
define void @store_zero(half* %in, half* %out) { define void @store_zero(half* %in, half* %out) {
entry: entry:
Show All 15 Lines; CHECK: vstr.16 {{s[0-9]+}}, [r1, #510]
ret void ret void
} }
define void @store_256(half* %in, half* %out) { define void @store_256(half* %in, half* %out) {
entry: entry:
; CHECK-LABEL: store_256: ; CHECK-LABEL: store_256:
%load = load half, half* %in, align 2 %load = load half, half* %in, align 2
; CHECK: add [[ADDR:r[0-9]+]], r1, #512 ; CHECK: add [[ADDR:r[0-9]+]], r1, #512
; CHECK: vstr.16 {{s[0-9]+}}, {{\[}}[[ADDR]]{{\]}} ; CHECK: vstr.16 {{s[0-9]+}}, [[[ADDR]]]
%arrayidx = getelementptr inbounds half, half* %out, i32 256 %arrayidx = getelementptr inbounds half, half* %out, i32 256
store half %load, half* %arrayidx store half %load, half* %arrayidx
ret void ret void
} }
define void @store_neg_255(half* %in, half* %out) { define void @store_neg_255(half* %in, half* %out) {
entry: entry:
; CHECK-LABEL: store_neg_255: ; CHECK-LABEL: store_neg_255:
%load = load half, half* %in, align 2 %load = load half, half* %in, align 2
; CHECK: vstr.16 {{s[0-9]+}}, [r1, #-510] ; CHECK: vstr.16 {{s[0-9]+}}, [r1, #-510]
%arrayidx = getelementptr inbounds half, half* %out, i32 -255 %arrayidx = getelementptr inbounds half, half* %out, i32 -255
store half %load, half* %arrayidx store half %load, half* %arrayidx
ret void ret void
} }
define void @store_neg_256(half* %in, half* %out) { define void @store_neg_256(half* %in, half* %out) {
entry: entry:
; CHECK-LABEL: store_neg_256: ; CHECK-LABEL: store_neg_256:
%load = load half, half* %in, align 2 %load = load half, half* %in, align 2
; CHECK: sub [[ADDR:r[0-9]+]], r1, #512 ; CHECK: sub [[ADDR:r[0-9]+]], r1, #512
; CHECK: vstr.16 {{s[0-9]+}}, {{\[}}[[ADDR]]{{\]}} ; CHECK: vstr.16 {{s[0-9]+}}, [[[ADDR]]]
%arrayidx = getelementptr inbounds half, half* %out, i32 -256 %arrayidx = getelementptr inbounds half, half* %out, i32 -256
store half %load, half* %arrayidx store half %load, half* %arrayidx
ret void ret void
} }

llvm/test/CodeGen/ARM/i64_volatile_load_store.ll

; RUN: llc -mtriple=armv5e-arm-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-ARMV5TE,CHECK ; RUN: llc -mtriple=armv5e-arm-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-ARMV5TE,CHECK
; RUN: llc -mtriple=thumbv6t2-arm-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-T2,CHECK ; RUN: llc -mtriple=thumbv6t2-arm-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-T2,CHECK
; RUN: llc -mtriple=armv4t-arm-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-ARMV4T,CHECK ; RUN: llc -mtriple=armv4t-arm-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-ARMV4T,CHECK
@x = common dso_local global i64 0, align 8 @x = common dso_local global i64 0, align 8
@y = common dso_local global i64 0, align 8 @y = common dso_local global i64 0, align 8
define void @test() { define void @test() {
entry: entry:
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]] ; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]]
; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]]
; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]]] ; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], [[[ADDR0]]]
; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]]] ; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], [[[ADDR1]]]
; CHECK-T2: movw [[ADDR0:r[0-9]+]], :lower16:x ; CHECK-T2: movw [[ADDR0:r[0-9]+]], :lower16:x
; CHECK-T2-NEXT: movw [[ADDR1:r[0-9]+]], :lower16:y ; CHECK-T2-NEXT: movw [[ADDR1:r[0-9]+]], :lower16:y
; CHECK-T2-NEXT: movt [[ADDR0]], :upper16:x ; CHECK-T2-NEXT: movt [[ADDR0]], :upper16:x
; CHECK-T2-NEXT: movt [[ADDR1]], :upper16:y ; CHECK-T2-NEXT: movt [[ADDR1]], :upper16:y
; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]]] ; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], [[[ADDR0]]]
; CHECK-T2-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]]] ; CHECK-T2-NEXT: strd [[R0]], [[R1]], [[[ADDR1]]]
; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]] ; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]]
; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]]
; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], {{\[}}[[ADDR0]]] ; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], [[[ADDR0]]]
; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], {{\[}}[[ADDR0]], #4] ; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], [[[ADDR0]], #4]
; CHECK-ARMV4T-NEXT: str [[R0]], {{\[}}[[ADDR1]], #4] ; CHECK-ARMV4T-NEXT: str [[R0]], [[[ADDR1]], #4]
; CHECK-ARMV4T-NEXT: str [[R1]], {{\[}}[[ADDR1]]] ; CHECK-ARMV4T-NEXT: str [[R1]], [[[ADDR1]]]
%0 = load volatile i64, i64* @x, align 8 %0 = load volatile i64, i64* @x, align 8
store volatile i64 %0, i64* @y, align 8 store volatile i64 %0, i64* @y, align 8
ret void ret void
} }
define void @test_offset() { define void @test_offset() {
entry: entry:
; CHECK-LABEL: test_offset: ; CHECK-LABEL: test_offset:
; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]] ; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]]
; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]]
; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #-4] ; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], [[[ADDR0]], #-4]
; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]], #-4] ; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], [[[ADDR1]], #-4]
; CHECK-T2: movw [[ADDR0:r[0-9]+]], :lower16:x ; CHECK-T2: movw [[ADDR0:r[0-9]+]], :lower16:x
; CHECK-T2-NEXT: movw [[ADDR1:r[0-9]+]], :lower16:y ; CHECK-T2-NEXT: movw [[ADDR1:r[0-9]+]], :lower16:y
; CHECK-T2-NEXT: movt [[ADDR0]], :upper16:x ; CHECK-T2-NEXT: movt [[ADDR0]], :upper16:x
; CHECK-T2-NEXT: movt [[ADDR1]], :upper16:y ; CHECK-T2-NEXT: movt [[ADDR1]], :upper16:y
; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #-4] ; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], [[[ADDR0]], #-4]
; CHECK-T2-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]], #-4] ; CHECK-T2-NEXT: strd [[R0]], [[R1]], [[[ADDR1]], #-4]
; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]] ; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]]
; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]]
; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], {{\[}}[[ADDR0]], #-4] ; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], [[[ADDR0]], #-4]
; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], {{\[}}[[ADDR0]]] ; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], [[[ADDR0]]]
; CHECK-ARMV4T-NEXT: str [[R1]], {{\[}}[[ADDR1]]] ; CHECK-ARMV4T-NEXT: str [[R1]], [[[ADDR1]]]
; CHECK-ARMV4T-NEXT: str [[R0]], {{\[}}[[ADDR1]], #-4] ; CHECK-ARMV4T-NEXT: str [[R0]], [[[ADDR1]], #-4]
%0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 -4) to i64*), align 8 %0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 -4) to i64*), align 8
store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 -4) to i64*), align 8 store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 -4) to i64*), align 8
ret void ret void
} }
define void @test_offset_1() { define void @test_offset_1() {
; CHECK-LABEL: test_offset_1: ; CHECK-LABEL: test_offset_1:
; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]] ; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]]
; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]]
; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #255] ; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], [[[ADDR0]], #255]
; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]], #255] ; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], [[[ADDR1]], #255]
; CHECK-T2: adds [[ADDR0:r[0-9]+]], #255 ; CHECK-T2: adds [[ADDR0:r[0-9]+]], #255
; CHECK-T2-NEXT: adds [[ADDR1:r[0-9]+]], #255 ; CHECK-T2-NEXT: adds [[ADDR1:r[0-9]+]], #255
; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]]] ; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], [[[ADDR0]]]
; CHECK-T2-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]]] ; CHECK-T2-NEXT: strd [[R0]], [[R1]], [[[ADDR1]]]
; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]] ; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]]
; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]]
; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], {{\[}}[[ADDR0]], #255] ; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], [[[ADDR0]], #255]
; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #259] ; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], [[[ADDR0]], #259]
; CHECK-ARMV4T-NEXT: str [[R1]], {{\[}}[[ADDR1]], #259] ; CHECK-ARMV4T-NEXT: str [[R1]], [[[ADDR1]], #259]
; CHECK-ARMV4T-NEXT: str [[R0]], {{\[}}[[ADDR1]], #255] ; CHECK-ARMV4T-NEXT: str [[R0]], [[[ADDR1]], #255]
entry: entry:
%0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 255) to i64*), align 8 %0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 255) to i64*), align 8
store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 255) to i64*), align 8 store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 255) to i64*), align 8
ret void ret void
} }
define void @test_offset_2() { define void @test_offset_2() {
; CHECK-LABEL: test_offset_2: ; CHECK-LABEL: test_offset_2:
; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]] ; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]]
; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]]
; CHECK-ARMV5TE-NEXT: add [[ADDR0]], [[ADDR0]], #256 ; CHECK-ARMV5TE-NEXT: add [[ADDR0]], [[ADDR0]], #256
; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #256 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #256
; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]]] ; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], [[[ADDR0]]]
; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]]] ; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], [[[ADDR1]]]
; CHECK-T2: movw [[ADDR0:r[0-9]+]], :lower16:x ; CHECK-T2: movw [[ADDR0:r[0-9]+]], :lower16:x
; CHECK-T2-NEXT: movw [[ADDR1:r[0-9]+]], :lower16:y ; CHECK-T2-NEXT: movw [[ADDR1:r[0-9]+]], :lower16:y
; CHECK-T2-NEXT: movt [[ADDR0]], :upper16:x ; CHECK-T2-NEXT: movt [[ADDR0]], :upper16:x
; CHECK-T2-NEXT: movt [[ADDR1]], :upper16:y ; CHECK-T2-NEXT: movt [[ADDR1]], :upper16:y
; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #256] ; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], [[[ADDR0]], #256]
; CHECK-T2-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]], #256] ; CHECK-T2-NEXT: strd [[R0]], [[R1]], [[[ADDR1]], #256]
; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]] ; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]]
; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]]
; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], {{\[}}[[ADDR0]], #256] ; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], [[[ADDR0]], #256]
; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #260] ; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], [[[ADDR0]], #260]
; CHECK-ARMV4T-NEXT: str [[R1]], {{\[}}[[ADDR1]], #260] ; CHECK-ARMV4T-NEXT: str [[R1]], [[[ADDR1]], #260]
; CHECK-ARMV4T-NEXT: str [[R0]], {{\[}}[[ADDR1]], #256] ; CHECK-ARMV4T-NEXT: str [[R0]], [[[ADDR1]], #256]
entry: entry:
%0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 256) to i64*), align 8 %0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 256) to i64*), align 8
store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 256) to i64*), align 8 store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 256) to i64*), align 8
ret void ret void
} }
define void @test_offset_3() { define void @test_offset_3() {
; CHECK-LABEL: test_offset_3: ; CHECK-LABEL: test_offset_3:
; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]] ; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]]
; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]] ; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]]
; CHECK-ARMV5TE-NEXT: add [[ADDR0]], [[ADDR0]], #1020 ; CHECK-ARMV5TE-NEXT: add [[ADDR0]], [[ADDR0]], #1020
; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1020 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1020
; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]]] ; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], [[[ADDR0]]]
; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]]] ; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], [[[ADDR1]]]
; CHECK-T2: movw [[ADDR0:r[0-9]+]], :lower16:x ; CHECK-T2: movw [[ADDR0:r[0-9]+]], :lower16:x
; CHECK-T2-NEXT: movw [[ADDR1:r[0-9]+]], :lower16:y ; CHECK-T2-NEXT: movw [[ADDR1:r[0-9]+]], :lower16:y
; CHECK-T2-NEXT: movt [[ADDR0]], :upper16:x ; CHECK-T2-NEXT: movt [[ADDR0]], :upper16:x
; CHECK-T2-NEXT: movt [[ADDR1]], :upper16:y ; CHECK-T2-NEXT: movt [[ADDR1]], :upper16:y
; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #1020] ; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], [[[ADDR0]], #1020]
; CHECK-T2-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]], #1020] ; CHECK-T2-NEXT: strd [[R0]], [[R1]], [[[ADDR1]], #1020]
; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]] ; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]]
; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]]
; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], {{\[}}[[ADDR0]], #1020] ; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], [[[ADDR0]], #1020]
; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #1024] ; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], [[[ADDR0]], #1024]
; CHECK-ARMV4T-NEXT: str [[R1]], {{\[}}[[ADDR1]], #1024] ; CHECK-ARMV4T-NEXT: str [[R1]], [[[ADDR1]], #1024]
; CHECK-ARMV4T-NEXT: str [[R0]], {{\[}}[[ADDR1]], #1020] ; CHECK-ARMV4T-NEXT: str [[R0]], [[[ADDR1]], #1020]
entry: entry:
%0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 1020) to i64*), align 8 %0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 1020) to i64*), align 8
store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 1020) to i64*), align 8 store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 1020) to i64*), align 8
ret void ret void
} }
define void @test_offset_4() { define void @test_offset_4() {
; CHECK-LABEL: test_offset_4: ; CHECK-LABEL: test_offset_4:
; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]] ; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]]
; CHECK-ARMV5TE: ldr [[ADDR1:r[0-9]+]] ; CHECK-ARMV5TE: ldr [[ADDR1:r[0-9]+]]
; CHECK-ARMV5TE-NEXT: add [[ADDR0]], [[ADDR0]], #1024 ; CHECK-ARMV5TE-NEXT: add [[ADDR0]], [[ADDR0]], #1024
; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1024 ; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1024
; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]]] ; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], [[[ADDR0]]]
; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]]] ; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], [[[ADDR1]]]
; CHECK-T2: movw [[ADDR1:r[0-9]+]], :lower16:y ; CHECK-T2: movw [[ADDR1:r[0-9]+]], :lower16:y
; CHECK-T2-NEXT: movw [[ADDR0:r[0-9]+]], :lower16:x ; CHECK-T2-NEXT: movw [[ADDR0:r[0-9]+]], :lower16:x
; CHECK-T2-NEXT: movt [[ADDR1]], :upper16:y ; CHECK-T2-NEXT: movt [[ADDR1]], :upper16:y
; CHECK-T2-NEXT: movt [[ADDR0]], :upper16:x ; CHECK-T2-NEXT: movt [[ADDR0]], :upper16:x
; CHECK-T2-NEXT: add.w [[ADDR0]], [[ADDR0]], #1024 ; CHECK-T2-NEXT: add.w [[ADDR0]], [[ADDR0]], #1024
; CHECK-T2-NEXT: add.w [[ADDR1]], [[ADDR1]], #1024 ; CHECK-T2-NEXT: add.w [[ADDR1]], [[ADDR1]], #1024
; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]]] ; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], [[[ADDR0]]]
; CHECK-T2-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]]] ; CHECK-T2-NEXT: strd [[R0]], [[R1]], [[[ADDR1]]]
; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]] ; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]]
; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]] ; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]]
; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], {{\[}}[[ADDR0]], #1024] ; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], [[[ADDR0]], #1024]
; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #1028] ; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], [[[ADDR0]], #1028]
; CHECK-ARMV4T-NEXT: str [[R1]], {{\[}}[[ADDR1]], #1028] ; CHECK-ARMV4T-NEXT: str [[R1]], [[[ADDR1]], #1028]
; CHECK-ARMV4T-NEXT: str [[R0]], {{\[}}[[ADDR1]], #1024] ; CHECK-ARMV4T-NEXT: str [[R0]], [[[ADDR1]], #1024]
entry: entry:
%0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 1024) to i64*), align 8 %0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 1024) to i64*), align 8
store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 1024) to i64*), align 8 store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 1024) to i64*), align 8
ret void ret void
} }
define i64 @test_stack() { define i64 @test_stack() {
; CHECK-LABEL: test_stack: ; CHECK-LABEL: test_stack:
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llvm/test/CodeGen/ARM/indirectbr.ll

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
L1: ; preds = %L2, %bb2 L1: ; preds = %L2, %bb2
%res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1] %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1]
; ARM-LABEL: %L1 ; ARM-LABEL: %L1
; ARM: ldr [[R_NEXTADDR:r[0-9]+]], LCPI ; ARM: ldr [[R_NEXTADDR:r[0-9]+]], LCPI
; ARM: ldr [[R1:r[0-9]+]], LCPI ; ARM: ldr [[R1:r[0-9]+]], LCPI
; ARM: add [[R_NEXTADDR_b:r[0-9]+]], pc, [[R_NEXTADDR]] ; ARM: add [[R_NEXTADDR_b:r[0-9]+]], pc, [[R_NEXTADDR]]
; ARM: add [[R1b:r[0-9]+]], pc, [[R1]] ; ARM: add [[R1b:r[0-9]+]], pc, [[R1]]
; ARM: str [[R1b]], {{\[}}[[R_NEXTADDR_b]]] ; ARM: str [[R1b]], [[[R_NEXTADDR_b]]]
; THUMB-LABEL: %L1 ; THUMB-LABEL: %L1
; THUMB: ldr [[R2:r[0-9]+]], LCPI ; THUMB: ldr [[R2:r[0-9]+]], LCPI
; THUMB: add [[R2]], pc ; THUMB: add [[R2]], pc
; THUMB: str [[R2]], [r[[NEXTADDR_REG]]] ; THUMB: str [[R2]], [r[[NEXTADDR_REG]]]
; THUMB2-LABEL: %L1 ; THUMB2-LABEL: %L1
; THUMB2: ldr [[R2:r[0-9]+]], LCPI ; THUMB2: ldr [[R2:r[0-9]+]], LCPI
; THUMB2-NEXT: str{{(.w)?}} [[R2]] ; THUMB2-NEXT: str{{(.w)?}} [[R2]]
store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4 store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4
ret i32 %res.3 ret i32 %res.3
} }
; ARM: .long Ltmp0-(LPC{{.*}}+8) ; ARM: .long Ltmp0-(LPC{{.*}}+8)
; THUMB: .long Ltmp0-(LPC{{.*}}+4) ; THUMB: .long Ltmp0-(LPC{{.*}}+4)
; THUMB: .long _nextaddr-([[NEXTADDR_PCBASE]]+4) ; THUMB: .long _nextaddr-([[NEXTADDR_PCBASE]]+4)
; THUMB2: .long Ltmp0 ; THUMB2: .long Ltmp0

llvm/test/CodeGen/ARM/jump-table-tbh.ll

Show All 14 Lines
; T2-NEXT: .short (.LBB0_[[x:[0-9]+]]-([[ANCHOR]]+4))/2 ; T2-NEXT: .short (.LBB0_[[x:[0-9]+]]-([[ANCHOR]]+4))/2
; T2-NEXT: .short (.LBB0_{{[0-9]+}}-([[ANCHOR]]+4))/2 ; T2-NEXT: .short (.LBB0_{{[0-9]+}}-([[ANCHOR]]+4))/2
; T2-NEXT: .short (.LBB0_{{[0-9]+}}-([[ANCHOR]]+4))/2 ; T2-NEXT: .short (.LBB0_{{[0-9]+}}-([[ANCHOR]]+4))/2
; T2-NEXT: .short (.LBB0_[[x]]-([[ANCHOR]]+4))/2 ; T2-NEXT: .short (.LBB0_[[x]]-([[ANCHOR]]+4))/2
; T1-LABEL: test_tbh: ; T1-LABEL: test_tbh:
; T1: lsls [[x:r[0-9]+]], r4, #1 ; T1: lsls [[x:r[0-9]+]], r4, #1
; T1: add [[x]], pc ; T1: add [[x]], pc
; T1: ldrh [[x]], {{\[}}[[x]], #4] ; T1: ldrh [[x]], [[[x]], #4]
; T1: lsls [[x]], [[x]], #1 ; T1: lsls [[x]], [[x]], #1
; T1: [[ANCHOR:.LCPI[0-9_]+]]: ; T1: [[ANCHOR:.LCPI[0-9_]+]]:
; T1: add pc, [[x]] ; T1: add pc, [[x]]
; T1-NEXT: @ %bb.2 ; T1-NEXT: @ %bb.2
; T1-NEXT: .p2align 2 ; T1-NEXT: .p2align 2
; T1-NEXT: LJTI ; T1-NEXT: LJTI
; T1-NEXT: .short (.LBB0_[[x:[0-9]+]]-([[ANCHOR]]+4))/2 ; T1-NEXT: .short (.LBB0_[[x:[0-9]+]]-([[ANCHOR]]+4))/2
; T1-NEXT: .short (.LBB0_{{[0-9]+}}-([[ANCHOR]]+4))/2 ; T1-NEXT: .short (.LBB0_{{[0-9]+}}-([[ANCHOR]]+4))/2
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llvm/test/CodeGen/ARM/ldrd.ll

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@TestVar = external global %struct.Test @TestVar = external global %struct.Test
; CHECK-LABEL: Func1: ; CHECK-LABEL: Func1:
define void @Func1() nounwind ssp "frame-pointer"="all" { define void @Func1() nounwind ssp "frame-pointer"="all" {
entry: entry:
; A8: movw [[BASER:r[0-9]+]], :lower16:{{.*}}TestVar{{.*}} ; A8: movw [[BASER:r[0-9]+]], :lower16:{{.*}}TestVar{{.*}}
; A8: movt [[BASER]], :upper16:{{.*}}TestVar{{.*}} ; A8: movt [[BASER]], :upper16:{{.*}}TestVar{{.*}}
; A8: ldr [[BASE:r[0-9]+]], {{\[}}[[BASER]]] ; A8: ldr [[BASE:r[0-9]+]], [[[BASER]]]
; A8: ldrd [[FIELD1:r[0-9]+]], [[FIELD2:r[0-9]+]], {{\[}}[[BASE]], #4] ; A8: ldrd [[FIELD1:r[0-9]+]], [[FIELD2:r[0-9]+]], [[[BASE]], #4]
; A8-NEXT: add [[FIELD2]], [[FIELD1]] ; A8-NEXT: add [[FIELD2]], [[FIELD1]]
; A8-NEXT: str [[FIELD2]], {{\[}}[[BASE]]{{\]}} ; A8-NEXT: str [[FIELD2]], [[[BASE]]]
; CONSERVATIVE-NOT: ldrd ; CONSERVATIVE-NOT: ldrd
%orig_blocks = alloca [256 x i16], align 2 %orig_blocks = alloca [256 x i16], align 2
%0 = bitcast [256 x i16]* %orig_blocks to i8*call void @llvm.lifetime.start.p0i8(i64 512, i8* %0) nounwind %0 = bitcast [256 x i16]* %orig_blocks to i8*call void @llvm.lifetime.start.p0i8(i64 512, i8* %0) nounwind
%tmp1 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 1), align 4 %tmp1 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 1), align 4
%tmp2 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 2), align 4 %tmp2 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 2), align 4
%add = add nsw i32 %tmp2, %tmp1 %add = add nsw i32 %tmp2, %tmp1
store i32 %add, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 0), align 4 store i32 %add, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 0), align 4
call void @llvm.lifetime.end.p0i8(i64 512, i8* %0) nounwind call void @llvm.lifetime.end.p0i8(i64 512, i8* %0) nounwind
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llvm/test/CodeGen/ARM/memcpy-ldm-stm.ll

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; CHECK-LABEL: t1: ; CHECK-LABEL: t1:
; CHECKV6: ldr [[LB:r[0-7]]], ; CHECKV6: ldr [[LB:r[0-7]]],
; CHECKV6-NEXT: ldr [[SB:r[0-7]]], ; CHECKV6-NEXT: ldr [[SB:r[0-7]]],
; We use '[rl0-9]+' to allow 'r0'..'r12', 'lr' ; We use '[rl0-9]+' to allow 'r0'..'r12', 'lr'
; CHECKV7: movt [[LB:[rl0-9]+]], :upper16:d ; CHECKV7: movt [[LB:[rl0-9]+]], :upper16:d
; CHECKV7-NEXT: movt [[SB:[rl0-9]+]], :upper16:s ; CHECKV7-NEXT: movt [[SB:[rl0-9]+]], :upper16:s
; CHECK-NEXT: ldm{{(\.w)?}} [[LB]]!, ; CHECK-NEXT: ldm{{(\.w)?}} [[LB]]!,
; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!, ; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!,
; Think of the monstrosity '{{\[}}[[LB]]]' as '[ [[LB]] ]' without the spaces. ; Think of the monstrosity '[[[LB]]]' as '[ [[LB]] ]' without the spaces.
; CHECK-NEXT: ldrb{{(\.w)?}} {{.*}}, {{\[}}[[LB]]] ; CHECK-NEXT: ldrb{{(\.w)?}} {{.*}}, [[[LB]]]
; CHECK-NEXT: strb{{(\.w)?}} {{.*}}, {{\[}}[[SB]]] ; CHECK-NEXT: strb{{(\.w)?}} {{.*}}, [[[SB]]]
tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 bitcast ([64 x i32]* @s to i8*), i8* align 4 bitcast ([64 x i32]* @d to i8*), i32 17, i1 false) tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 bitcast ([64 x i32]* @s to i8*), i8* align 4 bitcast ([64 x i32]* @d to i8*), i32 17, i1 false)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @t2() #0 { define void @t2() #0 {
entry: entry:
; CHECK-LABEL: t2: ; CHECK-LABEL: t2:
; CHECKV6: ldr [[LB:r[0-7]]], ; CHECKV6: ldr [[LB:r[0-7]]],
; CHECKV6-NEXT: ldr [[SB:r[0-7]]], ; CHECKV6-NEXT: ldr [[SB:r[0-7]]],
; CHECKV6-NEXT: ldm{{(\.w)?}} [[LB]]!, ; CHECKV6-NEXT: ldm{{(\.w)?}} [[LB]]!,
; CHECKV6-NEXT: stm{{(\.w)?}} [[SB]]!, ; CHECKV6-NEXT: stm{{(\.w)?}} [[SB]]!,
; CHECKV6-DAG: ldrh{{(\.w)?}} {{.*}}, {{\[}}[[LB]]] ; CHECKV6-DAG: ldrh{{(\.w)?}} {{.*}}, [[[LB]]]
; CHECKV6-DAG: ldrb{{(\.w)?}} {{.*}}, {{\[}}[[LB]], #2] ; CHECKV6-DAG: ldrb{{(\.w)?}} {{.*}}, [[[LB]], #2]
; CHECKV6-DAG: strb{{(\.w)?}} {{.*}}, {{\[}}[[SB]], #2] ; CHECKV6-DAG: strb{{(\.w)?}} {{.*}}, [[[SB]], #2]
; CHECKV6-DAG: strh{{(\.w)?}} {{.*}}, {{\[}}[[SB]]] ; CHECKV6-DAG: strh{{(\.w)?}} {{.*}}, [[[SB]]]
; CHECKV7: movt [[LB:[rl0-9]+]], :upper16:d ; CHECKV7: movt [[LB:[rl0-9]+]], :upper16:d
; CHECKV7-NEXT: movt [[SB:[rl0-9]+]], :upper16:s ; CHECKV7-NEXT: movt [[SB:[rl0-9]+]], :upper16:s
; CHECKV7: ldr{{(\.w)?}} {{.*}}, {{\[}}[[LB]], #11] ; CHECKV7: ldr{{(\.w)?}} {{.*}}, [[[LB]], #11]
; CHECKV7-NEXT: str{{(\.w)?}} {{.*}}, {{\[}}[[SB]], #11] ; CHECKV7-NEXT: str{{(\.w)?}} {{.*}}, [[[SB]], #11]
tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 bitcast ([64 x i32]* @s to i8*), i8* align 4 bitcast ([64 x i32]* @d to i8*), i32 15, i1 false) tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 bitcast ([64 x i32]* @s to i8*), i8* align 4 bitcast ([64 x i32]* @d to i8*), i32 15, i1 false)
ret void ret void
} }
; PR23768 ; PR23768
%struct.T = type { i8, i64, i8 } %struct.T = type { i8, i64, i8 }
@copy = external global %struct.T, align 8 @copy = external global %struct.T, align 8
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llvm/test/CodeGen/ARM/setjmp_longjmp.ll

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declare i8* @llvm.frameaddress(i32) declare i8* @llvm.frameaddress(i32)
declare i8* @llvm.stacksave() declare i8* @llvm.stacksave()
@_ZTIPKc = external constant i8* @_ZTIPKc = external constant i8*
; CHECK-LABEL: foobar ; CHECK-LABEL: foobar
; ;
; setjmp sequence: ; setjmp sequence:
; CHECK: add [[PCREG:r[0-9]+]], pc, #8 ; CHECK: add [[PCREG:r[0-9]+]], pc, #8
; CHECK-NEXT: str [[PCREG]], {{\[}}[[BUFREG:r[0-9]+]], #4] ; CHECK-NEXT: str [[PCREG]], [[[BUFREG:r[0-9]+]], #4]
; CHECK-NEXT: mov r0, #0 ; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: add pc, pc, #0 ; CHECK-NEXT: add pc, pc, #0
; CHECK-NEXT: mov r0, #1 ; CHECK-NEXT: mov r0, #1
; ;
; longjmp sequence: ; longjmp sequence:
; CHECK: ldr sp, [{{\s*}}[[BUFREG:r[0-9]+]], #8] ; CHECK: ldr sp, [{{\s*}}[[BUFREG:r[0-9]+]], #8]
; CHECK-NEXT: ldr [[DESTREG:r[0-9]+]], {{\[}}[[BUFREG]], #4] ; CHECK-NEXT: ldr [[DESTREG:r[0-9]+]], [[[BUFREG]], #4]
; CHECK-NEXT: ldr r7, {{\[}}[[BUFREG]]{{\]}} ; CHECK-NEXT: ldr r7, [[[BUFREG]]]
; CHECK-NEXT: bx [[DESTREG]] ; CHECK-NEXT: bx [[DESTREG]]
; CHECK-LINUX: ldr sp, [{{\s*}}[[BUFREG:r[0-9]+]], #8] ; CHECK-LINUX: ldr sp, [{{\s*}}[[BUFREG:r[0-9]+]], #8]
; CHECK-LINUX-NEXT: ldr [[DESTREG:r[0-9]+]], {{\[}}[[BUFREG]], #4] ; CHECK-LINUX-NEXT: ldr [[DESTREG:r[0-9]+]], [[[BUFREG]], #4]
; CHECK-LINUX-NEXT: ldr r7, {{\[}}[[BUFREG]]{{\]}} ; CHECK-LINUX-NEXT: ldr r7, [[[BUFREG]]]
; CHECK-LINUX-NEXT: ldr r11, {{\[}}[[BUFREG]]{{\]}} ; CHECK-LINUX-NEXT: ldr r11, [[[BUFREG]]]
; CHECK-LINUX-NEXT: bx [[DESTREG]] ; CHECK-LINUX-NEXT: bx [[DESTREG]]
; CHECK-WIN32: ldr.w r11, [{{\s*}}[[BUFREG:r[0-9]+]]] ; CHECK-WIN32: ldr.w r11, [{{\s*}}[[BUFREG:r[0-9]+]]]
; CHECK-WIN32-NEXT: ldr.w sp, {{\[}}[[BUFREG]], #8] ; CHECK-WIN32-NEXT: ldr.w sp, [[[BUFREG]], #8]
; CHECK-WIN32-NEXT: ldr.w pc, {{\[}}[[BUFREG]], #4] ; CHECK-WIN32-NEXT: ldr.w pc, [[[BUFREG]], #4]
define void @foobar() { define void @foobar() {
entry: entry:
%buf = alloca [5 x i8*], align 4 %buf = alloca [5 x i8*], align 4
%arraydecay = getelementptr inbounds [5 x i8*], [5 x i8*]* %buf, i32 0, i32 0 %arraydecay = getelementptr inbounds [5 x i8*], [5 x i8*]* %buf, i32 0, i32 0
%bufptr = bitcast i8** %arraydecay to i8* %bufptr = bitcast i8** %arraydecay to i8*
; Note: This is simplified, in reality you have to store the framepointer + ; Note: This is simplified, in reality you have to store the framepointer +
; stackpointer in the buffer as well for this to be legal! ; stackpointer in the buffer as well for this to be legal!
%setjmpres = call i32 @llvm.eh.sjlj.setjmp(i8* %bufptr) %setjmpres = call i32 @llvm.eh.sjlj.setjmp(i8* %bufptr)
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} }
; CHECK-LABEL: combine_sjlj_eh_and_setjmp_longjmp ; CHECK-LABEL: combine_sjlj_eh_and_setjmp_longjmp
; Check that we can mix sjlj exception handling with __builtin_setjmp ; Check that we can mix sjlj exception handling with __builtin_setjmp
; and __builtin_longjmp. ; and __builtin_longjmp.
; ;
; setjmp sequence: ; setjmp sequence:
; CHECK: add [[PCREG:r[0-9]+]], pc, #8 ; CHECK: add [[PCREG:r[0-9]+]], pc, #8
; CHECK-NEXT: str [[PCREG]], {{\[}}[[BUFREG:r[0-9]+]], #4] ; CHECK-NEXT: str [[PCREG]], [[[BUFREG:r[0-9]+]], #4]
; CHECK-NEXT: mov r0, #0 ; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: add pc, pc, #0 ; CHECK-NEXT: add pc, pc, #0
; CHECK-NEXT: mov r0, #1 ; CHECK-NEXT: mov r0, #1
; ;
; longjmp sequence: ; longjmp sequence:
; CHECK: ldr sp, [{{\s*}}[[BUFREG:r[0-9]+]], #8] ; CHECK: ldr sp, [{{\s*}}[[BUFREG:r[0-9]+]], #8]
; CHECK-NEXT: ldr [[DESTREG:r[0-9]+]], {{\[}}[[BUFREG]], #4] ; CHECK-NEXT: ldr [[DESTREG:r[0-9]+]], [[[BUFREG]], #4]
; CHECK-NEXT: ldr r7, {{\[}}[[BUFREG]]{{\]}} ; CHECK-NEXT: ldr r7, [[[BUFREG]]]
; CHECK-NEXT: bx [[DESTREG]] ; CHECK-NEXT: bx [[DESTREG]]
define void @combine_sjlj_eh_and_setjmp_longjmp() personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) { define void @combine_sjlj_eh_and_setjmp_longjmp() personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
entry: entry:
%buf = alloca [5 x i8*], align 4 %buf = alloca [5 x i8*], align 4
invoke void @may_throw() to label %try.cont unwind label %lpad invoke void @may_throw() to label %try.cont unwind label %lpad
lpad: lpad:
%0 = landingpad { i8*, i32 } catch i8* bitcast (i8** @_ZTIPKc to i8*) %0 = landingpad { i8*, i32 } catch i8* bitcast (i8** @_ZTIPKc to i8*)
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llvm/test/CodeGen/ARM/stack-guard-tls.ll

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;--- a.ll ;--- a.ll
!2 = !{i32 2, !"stack-protector-guard-offset", i32 1296} !2 = !{i32 2, !"stack-protector-guard-offset", i32 1296}
;--- b.ll ;--- b.ll
!2 = !{i32 2, !"stack-protector-guard-offset", i32 4296} !2 = !{i32 2, !"stack-protector-guard-offset", i32 4296}
; CHECK: mrc p15, #0, [[REG1:r[0-9]+]], c13, c0, #3 ; CHECK: mrc p15, #0, [[REG1:r[0-9]+]], c13, c0, #3
; CHECK-SMALL-NEXT: ldr{{(\.w)?}} [[REG1]], {{\[}}[[REG1]], #1296] ; CHECK-SMALL-NEXT: ldr{{(\.w)?}} [[REG1]], [[[REG1]], #1296]
; CHECK-LARGE-NEXT: add{{(\.w)?}} [[REG1]], [[REG1]], #4096 ; CHECK-LARGE-NEXT: add{{(\.w)?}} [[REG1]], [[REG1]], #4096
; CHECK-LARGE-NEXT: ldr{{(\.w)?}} [[REG1]], {{\[}}[[REG1]], #200] ; CHECK-LARGE-NEXT: ldr{{(\.w)?}} [[REG1]], [[[REG1]], #200]
; CHECK: bl baz ; CHECK: bl baz
; CHECK: mrc p15, #0, [[REG2:r[0-9]+]], c13, c0, #3 ; CHECK: mrc p15, #0, [[REG2:r[0-9]+]], c13, c0, #3
; CHECK-SMALL-NEXT: ldr{{(\.w)?}} [[REG2]], {{\[}}[[REG2]], #1296] ; CHECK-SMALL-NEXT: ldr{{(\.w)?}} [[REG2]], [[[REG2]], #1296]
; CHECK-LARGE-NEXT: add{{(\.w)?}} [[REG2]], [[REG2]], #4096 ; CHECK-LARGE-NEXT: add{{(\.w)?}} [[REG2]], [[REG2]], #4096
; CHECK-LARGE-NEXT: ldr{{(\.w)?}} [[REG2]], {{\[}}[[REG2]], #200] ; CHECK-LARGE-NEXT: ldr{{(\.w)?}} [[REG2]], [[[REG2]], #200]

llvm/test/CodeGen/ARM/stack_guard_remat.ll

; RUN: llc < %s -mtriple=arm-apple-ios -relocation-model=pic -no-integrated-as | FileCheck %s -check-prefix=PIC ; RUN: llc < %s -mtriple=arm-apple-ios -relocation-model=pic -no-integrated-as | FileCheck %s -check-prefix=PIC
; RUN: llc < %s -mtriple=arm-apple-ios -relocation-model=static -no-integrated-as | FileCheck %s -check-prefix=NO-PIC -check-prefix=STATIC ; RUN: llc < %s -mtriple=arm-apple-ios -relocation-model=static -no-integrated-as | FileCheck %s -check-prefix=NO-PIC -check-prefix=STATIC
; RUN: llc < %s -mtriple=arm-apple-ios -relocation-model=dynamic-no-pic -no-integrated-as | FileCheck %s -check-prefix=NO-PIC -check-prefix=DYNAMIC-NO-PIC ; RUN: llc < %s -mtriple=arm-apple-ios -relocation-model=dynamic-no-pic -no-integrated-as | FileCheck %s -check-prefix=NO-PIC -check-prefix=DYNAMIC-NO-PIC
; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=cortex-a8 -relocation-model=pic -no-integrated-as | FileCheck %s -check-prefix=PIC-V7 ; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=cortex-a8 -relocation-model=pic -no-integrated-as | FileCheck %s -check-prefix=PIC-V7
; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=cortex-a8 -relocation-model=static -no-integrated-as | FileCheck %s -check-prefix=STATIC-V7 ; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=cortex-a8 -relocation-model=static -no-integrated-as | FileCheck %s -check-prefix=STATIC-V7
; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=cortex-a8 -relocation-model=dynamic-no-pic -no-integrated-as | FileCheck %s -check-prefix=DYNAMIC-NO-PIC-V7 ; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=cortex-a8 -relocation-model=dynamic-no-pic -no-integrated-as | FileCheck %s -check-prefix=DYNAMIC-NO-PIC-V7
;PIC: foo2 ;PIC: foo2
;PIC: ldr [[R0:r[0-9]+]], [[LABEL0:LCPI[0-9_]+]] ;PIC: ldr [[R0:r[0-9]+]], [[LABEL0:LCPI[0-9_]+]]
;PIC: [[LABEL1:LPC0_1]]: ;PIC: [[LABEL1:LPC0_1]]:
;PIC: add [[R1:r[0-9]+]], pc, [[R0]] ;PIC: add [[R1:r[0-9]+]], pc, [[R0]]
;PIC: ldr [[R2:r[0-9]+]], {{\[}}[[R1]]{{\]}} ;PIC: ldr [[R2:r[0-9]+]], [[[R1]]]
;PIC: ldr {{r[0-9]+}}, {{\[}}[[R2]]{{\]}} ;PIC: ldr {{r[0-9]+}}, [[[R2]]]
;PIC: [[LABEL0]]: ;PIC: [[LABEL0]]:
;PIC-NEXT: .long L___stack_chk_guard$non_lazy_ptr-([[LABEL1]]+8) ;PIC-NEXT: .long L___stack_chk_guard$non_lazy_ptr-([[LABEL1]]+8)
;NO-PIC: foo2 ;NO-PIC: foo2
;NO-PIC: ldr [[R0:r[0-9]+]], [[LABEL0:LCPI[0-9_]+]] ;NO-PIC: ldr [[R0:r[0-9]+]], [[LABEL0:LCPI[0-9_]+]]
;NO-PIC-NOT: LPC ;NO-PIC-NOT: LPC
;NO-PIC: ldr {{r[0-9]+}}, {{\[}}[[R0]]{{\]}} ;NO-PIC: ldr {{r[0-9]+}}, [[[R0]]]
;STATIC: [[LABEL0]]: ;STATIC: [[LABEL0]]:
;STATIC-NEXT: .long ___stack_chk_guard ;STATIC-NEXT: .long ___stack_chk_guard
;DYNAMIC-NO-PIC: [[LABEL0]]: ;DYNAMIC-NO-PIC: [[LABEL0]]:
;DYNAMIC-NO-PIC-NEXT: .long L___stack_chk_guard$non_lazy_ptr ;DYNAMIC-NO-PIC-NEXT: .long L___stack_chk_guard$non_lazy_ptr
;PIC-V7: movw [[R0:r[0-9]+]], :lower16:(L___stack_chk_guard$non_lazy_ptr-([[LABEL0:LPC[0-9_]+]]+8)) ;PIC-V7: movw [[R0:r[0-9]+]], :lower16:(L___stack_chk_guard$non_lazy_ptr-([[LABEL0:LPC[0-9_]+]]+8))
;PIC-V7: movt [[R0]], :upper16:(L___stack_chk_guard$non_lazy_ptr-([[LABEL0]]+8)) ;PIC-V7: movt [[R0]], :upper16:(L___stack_chk_guard$non_lazy_ptr-([[LABEL0]]+8))
;PIC-V7: [[LABEL0]]: ;PIC-V7: [[LABEL0]]:
;PIC-V7: ldr [[R0]], {{\[}}pc, [[R0]]{{\]}} ;PIC-V7: ldr [[R0]], [pc, [[R0]]]
;PIC-V7: ldr [[R0]], {{\[}}[[R0]]{{\]}} ;PIC-V7: ldr [[R0]], [[[R0]]]
;PIC-V7: L___stack_chk_guard$non_lazy_ptr: ;PIC-V7: L___stack_chk_guard$non_lazy_ptr:
;PIC-V7: .indirect_symbol ___stack_chk_guard ;PIC-V7: .indirect_symbol ___stack_chk_guard
;STATIC-V7: movw [[R0:r[0-9]+]], :lower16:___stack_chk_guard ;STATIC-V7: movw [[R0:r[0-9]+]], :lower16:___stack_chk_guard
;STATIC-V7: movt [[R0]], :upper16:___stack_chk_guard ;STATIC-V7: movt [[R0]], :upper16:___stack_chk_guard
;STATIC-V7: ldr [[R0]], {{\[}}[[R0]]{{\]}} ;STATIC-V7: ldr [[R0]], [[[R0]]]
;DYNAMIC-NO-PIC-V7: movw [[R0:r[0-9]+]], :lower16:L___stack_chk_guard$non_lazy_ptr ;DYNAMIC-NO-PIC-V7: movw [[R0:r[0-9]+]], :lower16:L___stack_chk_guard$non_lazy_ptr
;DYNAMIC-NO-PIC-V7: movt [[R0]], :upper16:L___stack_chk_guard$non_lazy_ptr ;DYNAMIC-NO-PIC-V7: movt [[R0]], :upper16:L___stack_chk_guard$non_lazy_ptr
;DYNAMIC-NO-PIC-V7: ldr [[R0]], {{\[}}[[R0]]{{\]}} ;DYNAMIC-NO-PIC-V7: ldr [[R0]], [[[R0]]]
;DYNAMIC-NO-PIC-V7: ldr [[R0]], {{\[}}[[R0]]{{\]}} ;DYNAMIC-NO-PIC-V7: ldr [[R0]], [[[R0]]]
;DYNAMIC-NO-PIC-V7: L___stack_chk_guard$non_lazy_ptr: ;DYNAMIC-NO-PIC-V7: L___stack_chk_guard$non_lazy_ptr:
;DYNAMIC-NO-PIC-V7: .indirect_symbol ___stack_chk_guard ;DYNAMIC-NO-PIC-V7: .indirect_symbol ___stack_chk_guard
; Function Attrs: nounwind ssp ; Function Attrs: nounwind ssp
define i32 @test_stack_guard_remat() #0 { define i32 @test_stack_guard_remat() #0 {
%a1 = alloca [256 x i32], align 4 %a1 = alloca [256 x i32], align 4
%1 = bitcast [256 x i32]* %a1 to i8* %1 = bitcast [256 x i32]* %a1 to i8*
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llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
;T1POST-LABEL: <test_A_1>: ;T1POST-LABEL: <test_A_1>:
define void @test_A_1() { define void @test_A_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.A, align 1 %a = alloca %struct.A, align 1
call void @use_A(%struct.A* byval(%struct.A) align 1 %a) call void @use_A(%struct.A* byval(%struct.A) align 1 %a)
ret void ret void
} }
;ARM-LABEL: <test_A_2>: ;ARM-LABEL: <test_A_2>:
;THUMB2-LABEL: <test_A_2>: ;THUMB2-LABEL: <test_A_2>:
;NO_NEON-LABEL:<test_A_2>: ;NO_NEON-LABEL:<test_A_2>:
;THUMB1-LABEL: <test_A_2>: ;THUMB1-LABEL: <test_A_2>:
;T1POST-LABEL: <test_A_2>: ;T1POST-LABEL: <test_A_2>:
define void @test_A_2() { define void @test_A_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.A, align 2 %a = alloca %struct.A, align 2
call void @use_A(%struct.A* byval(%struct.A) align 2 %a) call void @use_A(%struct.A* byval(%struct.A) align 2 %a)
ret void ret void
} }
;ARM-LABEL: <test_A_4>: ;ARM-LABEL: <test_A_4>:
;THUMB2-LABEL: <test_A_4>: ;THUMB2-LABEL: <test_A_4>:
;NO_NEON-LABEL:<test_A_4>: ;NO_NEON-LABEL:<test_A_4>:
;THUMB1-LABEL: <test_A_4>: ;THUMB1-LABEL: <test_A_4>:
;T1POST-LABEL: <test_A_4>: ;T1POST-LABEL: <test_A_4>:
define void @test_A_4() { define void @test_A_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.A, align 4 %a = alloca %struct.A, align 4
call void @use_A(%struct.A* byval(%struct.A) align 4 %a) call void @use_A(%struct.A* byval(%struct.A) align 4 %a)
ret void ret void
} }
;ARM-LABEL: <test_A_8>: ;ARM-LABEL: <test_A_8>:
;THUMB2-LABEL: <test_A_8>: ;THUMB2-LABEL: <test_A_8>:
;NO_NEON-LABEL:<test_A_8>: ;NO_NEON-LABEL:<test_A_8>:
;THUMB1-LABEL: <test_A_8>: ;THUMB1-LABEL: <test_A_8>:
;T1POST-LABEL: <test_A_8>: ;T1POST-LABEL: <test_A_8>:
define void @test_A_8() { define void @test_A_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.A, align 8 %a = alloca %struct.A, align 8
call void @use_A(%struct.A* byval(%struct.A) align 8 %a) call void @use_A(%struct.A* byval(%struct.A) align 8 %a)
ret void ret void
} }
;ARM-LABEL: <test_A_16>: ;ARM-LABEL: <test_A_16>:
;THUMB2-LABEL: <test_A_16>: ;THUMB2-LABEL: <test_A_16>:
;NO_NEON-LABEL:<test_A_16>: ;NO_NEON-LABEL:<test_A_16>:
;THUMB1-LABEL: <test_A_16>: ;THUMB1-LABEL: <test_A_16>:
;T1POST-LABEL: <test_A_16>: ;T1POST-LABEL: <test_A_16>:
define void @test_A_16() { define void @test_A_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.A, align 16 %a = alloca %struct.A, align 16
call void @use_A(%struct.A* byval(%struct.A) align 16 %a) call void @use_A(%struct.A* byval(%struct.A) align 16 %a)
ret void ret void
} }
;ARM-LABEL: <test_B_1>: ;ARM-LABEL: <test_B_1>:
;THUMB2-LABEL: <test_B_1>: ;THUMB2-LABEL: <test_B_1>:
;NO_NEON-LABEL:<test_B_1>: ;NO_NEON-LABEL:<test_B_1>:
;THUMB1-LABEL: <test_B_1>: ;THUMB1-LABEL: <test_B_1>:
;T1POST-LABEL: <test_B_1>: ;T1POST-LABEL: <test_B_1>:
define void @test_B_1() { define void @test_B_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.B, align 1 %a = alloca %struct.B, align 1
call void @use_B(%struct.B* byval(%struct.B) align 1 %a) call void @use_B(%struct.B* byval(%struct.B) align 1 %a)
ret void ret void
} }
;ARM-LABEL: <test_B_2>: ;ARM-LABEL: <test_B_2>:
;THUMB2-LABEL: <test_B_2>: ;THUMB2-LABEL: <test_B_2>:
;NO_NEON-LABEL:<test_B_2>: ;NO_NEON-LABEL:<test_B_2>:
;THUMB1-LABEL: <test_B_2>: ;THUMB1-LABEL: <test_B_2>:
;T1POST-LABEL: <test_B_2>: ;T1POST-LABEL: <test_B_2>:
define void @test_B_2() { define void @test_B_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.B, align 2 %a = alloca %struct.B, align 2
call void @use_B(%struct.B* byval(%struct.B) align 2 %a) call void @use_B(%struct.B* byval(%struct.B) align 2 %a)
ret void ret void
} }
;ARM-LABEL: <test_B_4>: ;ARM-LABEL: <test_B_4>:
;THUMB2-LABEL: <test_B_4>: ;THUMB2-LABEL: <test_B_4>:
;NO_NEON-LABEL:<test_B_4>: ;NO_NEON-LABEL:<test_B_4>:
;THUMB1-LABEL: <test_B_4>: ;THUMB1-LABEL: <test_B_4>:
;T1POST-LABEL: <test_B_4>: ;T1POST-LABEL: <test_B_4>:
define void @test_B_4() { define void @test_B_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.B, align 4 %a = alloca %struct.B, align 4
call void @use_B(%struct.B* byval(%struct.B) align 4 %a) call void @use_B(%struct.B* byval(%struct.B) align 4 %a)
ret void ret void
} }
;ARM-LABEL: <test_B_8>: ;ARM-LABEL: <test_B_8>:
;THUMB2-LABEL: <test_B_8>: ;THUMB2-LABEL: <test_B_8>:
;NO_NEON-LABEL:<test_B_8>: ;NO_NEON-LABEL:<test_B_8>:
;THUMB1-LABEL: <test_B_8>: ;THUMB1-LABEL: <test_B_8>:
;T1POST-LABEL: <test_B_8>: ;T1POST-LABEL: <test_B_8>:
define void @test_B_8() { define void @test_B_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.B, align 8 %a = alloca %struct.B, align 8
call void @use_B(%struct.B* byval(%struct.B) align 8 %a) call void @use_B(%struct.B* byval(%struct.B) align 8 %a)
ret void ret void
} }
;ARM-LABEL: <test_B_16>: ;ARM-LABEL: <test_B_16>:
;THUMB2-LABEL: <test_B_16>: ;THUMB2-LABEL: <test_B_16>:
;NO_NEON-LABEL:<test_B_16>: ;NO_NEON-LABEL:<test_B_16>:
;THUMB1-LABEL: <test_B_16>: ;THUMB1-LABEL: <test_B_16>:
;T1POST-LABEL: <test_B_16>: ;T1POST-LABEL: <test_B_16>:
define void @test_B_16() { define void @test_B_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.B, align 16 %a = alloca %struct.B, align 16
call void @use_B(%struct.B* byval(%struct.B) align 16 %a) call void @use_B(%struct.B* byval(%struct.B) align 16 %a)
ret void ret void
} }
;ARM-LABEL: <test_C_1>: ;ARM-LABEL: <test_C_1>:
;THUMB2-LABEL: <test_C_1>: ;THUMB2-LABEL: <test_C_1>:
;NO_NEON-LABEL:<test_C_1>: ;NO_NEON-LABEL:<test_C_1>:
;THUMB1-LABEL: <test_C_1>: ;THUMB1-LABEL: <test_C_1>:
;T1POST-LABEL: <test_C_1>: ;T1POST-LABEL: <test_C_1>:
define void @test_C_1() { define void @test_C_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.C, align 1 %a = alloca %struct.C, align 1
call void @use_C(%struct.C* byval(%struct.C) align 1 %a) call void @use_C(%struct.C* byval(%struct.C) align 1 %a)
ret void ret void
} }
;ARM-LABEL: <test_C_2>: ;ARM-LABEL: <test_C_2>:
;THUMB2-LABEL: <test_C_2>: ;THUMB2-LABEL: <test_C_2>:
;NO_NEON-LABEL:<test_C_2>: ;NO_NEON-LABEL:<test_C_2>:
;THUMB1-LABEL: <test_C_2>: ;THUMB1-LABEL: <test_C_2>:
;T1POST-LABEL: <test_C_2>: ;T1POST-LABEL: <test_C_2>:
define void @test_C_2() { define void @test_C_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.C, align 2 %a = alloca %struct.C, align 2
call void @use_C(%struct.C* byval(%struct.C) align 2 %a) call void @use_C(%struct.C* byval(%struct.C) align 2 %a)
ret void ret void
} }
;ARM-LABEL: <test_C_4>: ;ARM-LABEL: <test_C_4>:
;THUMB2-LABEL: <test_C_4>: ;THUMB2-LABEL: <test_C_4>:
;NO_NEON-LABEL:<test_C_4>: ;NO_NEON-LABEL:<test_C_4>:
;THUMB1-LABEL: <test_C_4>: ;THUMB1-LABEL: <test_C_4>:
;T1POST-LABEL: <test_C_4>: ;T1POST-LABEL: <test_C_4>:
define void @test_C_4() { define void @test_C_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.C, align 4 %a = alloca %struct.C, align 4
call void @use_C(%struct.C* byval(%struct.C) align 4 %a) call void @use_C(%struct.C* byval(%struct.C) align 4 %a)
ret void ret void
} }
;ARM-LABEL: <test_C_8>: ;ARM-LABEL: <test_C_8>:
;THUMB2-LABEL: <test_C_8>: ;THUMB2-LABEL: <test_C_8>:
;NO_NEON-LABEL:<test_C_8>: ;NO_NEON-LABEL:<test_C_8>:
;THUMB1-LABEL: <test_C_8>: ;THUMB1-LABEL: <test_C_8>:
;T1POST-LABEL: <test_C_8>: ;T1POST-LABEL: <test_C_8>:
define void @test_C_8() { define void @test_C_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.C, align 8 %a = alloca %struct.C, align 8
call void @use_C(%struct.C* byval(%struct.C) align 8 %a) call void @use_C(%struct.C* byval(%struct.C) align 8 %a)
ret void ret void
} }
;ARM-LABEL: <test_C_16>: ;ARM-LABEL: <test_C_16>:
;THUMB2-LABEL: <test_C_16>: ;THUMB2-LABEL: <test_C_16>:
;NO_NEON-LABEL:<test_C_16>: ;NO_NEON-LABEL:<test_C_16>:
;THUMB1-LABEL: <test_C_16>: ;THUMB1-LABEL: <test_C_16>:
;T1POST-LABEL: <test_C_16>: ;T1POST-LABEL: <test_C_16>:
define void @test_C_16() { define void @test_C_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.C, align 16 %a = alloca %struct.C, align 16
call void @use_C(%struct.C* byval(%struct.C) align 16 %a) call void @use_C(%struct.C* byval(%struct.C) align 16 %a)
ret void ret void
} }
;ARM-LABEL: <test_D_1>: ;ARM-LABEL: <test_D_1>:
;THUMB2-LABEL: <test_D_1>: ;THUMB2-LABEL: <test_D_1>:
;NO_NEON-LABEL:<test_D_1>: ;NO_NEON-LABEL:<test_D_1>:
;THUMB1-LABEL: <test_D_1>: ;THUMB1-LABEL: <test_D_1>:
;T1POST-LABEL: <test_D_1>: ;T1POST-LABEL: <test_D_1>:
define void @test_D_1() { define void @test_D_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;ARM: bne ;ARM: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.D, align 1 %a = alloca %struct.D, align 1
call void @use_D(%struct.D* byval(%struct.D) align 1 %a) call void @use_D(%struct.D* byval(%struct.D) align 1 %a)
ret void ret void
} }
;ARM-LABEL: <test_D_2>: ;ARM-LABEL: <test_D_2>:
;THUMB2-LABEL: <test_D_2>: ;THUMB2-LABEL: <test_D_2>:
;NO_NEON-LABEL:<test_D_2>: ;NO_NEON-LABEL:<test_D_2>:
;THUMB1-LABEL: <test_D_2>: ;THUMB1-LABEL: <test_D_2>:
;T1POST-LABEL: <test_D_2>: ;T1POST-LABEL: <test_D_2>:
define void @test_D_2() { define void @test_D_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;ARM: bne ;ARM: bne
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.D, align 2 %a = alloca %struct.D, align 2
call void @use_D(%struct.D* byval(%struct.D) align 2 %a) call void @use_D(%struct.D* byval(%struct.D) align 2 %a)
ret void ret void
} }
;ARM-LABEL: <test_D_4>: ;ARM-LABEL: <test_D_4>:
;THUMB2-LABEL: <test_D_4>: ;THUMB2-LABEL: <test_D_4>:
;NO_NEON-LABEL:<test_D_4>: ;NO_NEON-LABEL:<test_D_4>:
;THUMB1-LABEL: <test_D_4>: ;THUMB1-LABEL: <test_D_4>:
;T1POST-LABEL: <test_D_4>: ;T1POST-LABEL: <test_D_4>:
define void @test_D_4() { define void @test_D_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;ARM: bne ;ARM: bne
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.D, align 4 %a = alloca %struct.D, align 4
call void @use_D(%struct.D* byval(%struct.D) align 4 %a) call void @use_D(%struct.D* byval(%struct.D) align 4 %a)
ret void ret void
Show All 9 Lines
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.D, align 8 %a = alloca %struct.D, align 8
call void @use_D(%struct.D* byval(%struct.D) align 8 %a) call void @use_D(%struct.D* byval(%struct.D) align 8 %a)
ret void ret void
Show All 9 Lines
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.D, align 16 %a = alloca %struct.D, align 16
call void @use_D(%struct.D* byval(%struct.D) align 16 %a) call void @use_D(%struct.D* byval(%struct.D) align 16 %a)
ret void ret void
} }
;ARM-LABEL: <test_E_1>: ;ARM-LABEL: <test_E_1>:
;THUMB2-LABEL: <test_E_1>: ;THUMB2-LABEL: <test_E_1>:
;NO_NEON-LABEL:<test_E_1>: ;NO_NEON-LABEL:<test_E_1>:
;THUMB1-LABEL: <test_E_1>: ;THUMB1-LABEL: <test_E_1>:
;T1POST-LABEL: <test_E_1>: ;T1POST-LABEL: <test_E_1>:
define void @test_E_1() { define void @test_E_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;ARM: bne ;ARM: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.E, align 1 %a = alloca %struct.E, align 1
call void @use_E(%struct.E* byval(%struct.E) align 1 %a) call void @use_E(%struct.E* byval(%struct.E) align 1 %a)
ret void ret void
Show All 11 Lines
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: bne ;THUMB2: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;THUMB1: bne ;THUMB1: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.E, align 2 %a = alloca %struct.E, align 2
call void @use_E(%struct.E* byval(%struct.E) align 2 %a) call void @use_E(%struct.E* byval(%struct.E) align 2 %a)
ret void ret void
} }
;ARM-LABEL: <test_E_4>: ;ARM-LABEL: <test_E_4>:
Show All 9 Lines
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: bne ;THUMB2: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.E, align 4 %a = alloca %struct.E, align 4
call void @use_E(%struct.E* byval(%struct.E) align 4 %a) call void @use_E(%struct.E* byval(%struct.E) align 4 %a)
ret void ret void
} }
;ARM-LABEL: <test_E_8>: ;ARM-LABEL: <test_E_8>:
Show All 10 Lines
;THUMB2: bne ;THUMB2: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.E, align 8 %a = alloca %struct.E, align 8
call void @use_E(%struct.E* byval(%struct.E) align 8 %a) call void @use_E(%struct.E* byval(%struct.E) align 8 %a)
ret void ret void
} }
;ARM-LABEL: <test_E_16>: ;ARM-LABEL: <test_E_16>:
Show All 10 Lines
;THUMB2: bne ;THUMB2: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.E, align 16 %a = alloca %struct.E, align 16
call void @use_E(%struct.E* byval(%struct.E) align 16 %a) call void @use_E(%struct.E* byval(%struct.E) align 16 %a)
ret void ret void
} }
;ARM-LABEL: <test_F_1>: ;ARM-LABEL: <test_F_1>:
;THUMB2-LABEL: <test_F_1>: ;THUMB2-LABEL: <test_F_1>:
;NO_NEON-LABEL:<test_F_1>: ;NO_NEON-LABEL:<test_F_1>:
;THUMB1-LABEL: <test_F_1>: ;THUMB1-LABEL: <test_F_1>:
;T1POST-LABEL: <test_F_1>: ;T1POST-LABEL: <test_F_1>:
define void @test_F_1() { define void @test_F_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;ARM: bne ;ARM: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.F, align 1 %a = alloca %struct.F, align 1
call void @use_F(%struct.F* byval(%struct.F) align 1 %a) call void @use_F(%struct.F* byval(%struct.F) align 1 %a)
ret void ret void
Show All 11 Lines
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: bne ;THUMB2: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;THUMB1: bne ;THUMB1: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.F, align 2 %a = alloca %struct.F, align 2
call void @use_F(%struct.F* byval(%struct.F) align 2 %a) call void @use_F(%struct.F* byval(%struct.F) align 2 %a)
ret void ret void
} }
;ARM-LABEL: <test_F_4>: ;ARM-LABEL: <test_F_4>:
Show All 9 Lines
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: bne ;THUMB2: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.F, align 4 %a = alloca %struct.F, align 4
call void @use_F(%struct.F* byval(%struct.F) align 4 %a) call void @use_F(%struct.F* byval(%struct.F) align 4 %a)
ret void ret void
} }
Show All 11 Lines
;THUMB2: bne ;THUMB2: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.F, align 8 %a = alloca %struct.F, align 8
call void @use_F(%struct.F* byval(%struct.F) align 8 %a) call void @use_F(%struct.F* byval(%struct.F) align 8 %a)
ret void ret void
} }
Show All 11 Lines
;THUMB2: bne ;THUMB2: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.F, align 16 %a = alloca %struct.F, align 16
call void @use_F(%struct.F* byval(%struct.F) align 16 %a) call void @use_F(%struct.F* byval(%struct.F) align 16 %a)
ret void ret void
} }
;ARM-LABEL: <test_G_1>: ;ARM-LABEL: <test_G_1>:
;THUMB2-LABEL: <test_G_1>: ;THUMB2-LABEL: <test_G_1>:
;NO_NEON-LABEL:<test_G_1>: ;NO_NEON-LABEL:<test_G_1>:
;THUMB1-LABEL: <test_G_1>: ;THUMB1-LABEL: <test_G_1>:
;T1POST-LABEL: <test_G_1>: ;T1POST-LABEL: <test_G_1>:
define void @test_G_1() { define void @test_G_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.G, align 1 %a = alloca %struct.G, align 1
call void @use_G(%struct.G* byval(%struct.G) align 1 %a) call void @use_G(%struct.G* byval(%struct.G) align 1 %a)
ret void ret void
} }
;ARM-LABEL: <test_G_2>: ;ARM-LABEL: <test_G_2>:
;THUMB2-LABEL: <test_G_2>: ;THUMB2-LABEL: <test_G_2>:
;NO_NEON-LABEL:<test_G_2>: ;NO_NEON-LABEL:<test_G_2>:
;THUMB1-LABEL: <test_G_2>: ;THUMB1-LABEL: <test_G_2>:
;T1POST-LABEL: <test_G_2>: ;T1POST-LABEL: <test_G_2>:
define void @test_G_2() { define void @test_G_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.G, align 2 %a = alloca %struct.G, align 2
call void @use_G(%struct.G* byval(%struct.G) align 2 %a) call void @use_G(%struct.G* byval(%struct.G) align 2 %a)
ret void ret void
} }
;ARM-LABEL: <test_G_4>: ;ARM-LABEL: <test_G_4>:
;THUMB2-LABEL: <test_G_4>: ;THUMB2-LABEL: <test_G_4>:
;NO_NEON-LABEL:<test_G_4>: ;NO_NEON-LABEL:<test_G_4>:
;THUMB1-LABEL: <test_G_4>: ;THUMB1-LABEL: <test_G_4>:
;T1POST-LABEL: <test_G_4>: ;T1POST-LABEL: <test_G_4>:
define void @test_G_4() { define void @test_G_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.G, align 4 %a = alloca %struct.G, align 4
call void @use_G(%struct.G* byval(%struct.G) align 4 %a) call void @use_G(%struct.G* byval(%struct.G) align 4 %a)
ret void ret void
} }
;ARM-LABEL: <test_G_8>: ;ARM-LABEL: <test_G_8>:
;THUMB2-LABEL: <test_G_8>: ;THUMB2-LABEL: <test_G_8>:
;NO_NEON-LABEL:<test_G_8>: ;NO_NEON-LABEL:<test_G_8>:
;THUMB1-LABEL: <test_G_8>: ;THUMB1-LABEL: <test_G_8>:
;T1POST-LABEL: <test_G_8>: ;T1POST-LABEL: <test_G_8>:
define void @test_G_8() { define void @test_G_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.G, align 8 %a = alloca %struct.G, align 8
call void @use_G(%struct.G* byval(%struct.G) align 8 %a) call void @use_G(%struct.G* byval(%struct.G) align 8 %a)
ret void ret void
} }
;ARM-LABEL: <test_G_16>: ;ARM-LABEL: <test_G_16>:
;THUMB2-LABEL: <test_G_16>: ;THUMB2-LABEL: <test_G_16>:
;NO_NEON-LABEL:<test_G_16>: ;NO_NEON-LABEL:<test_G_16>:
;THUMB1-LABEL: <test_G_16>: ;THUMB1-LABEL: <test_G_16>:
;T1POST-LABEL: <test_G_16>: ;T1POST-LABEL: <test_G_16>:
define void @test_G_16() { define void @test_G_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.G, align 16 %a = alloca %struct.G, align 16
call void @use_G(%struct.G* byval(%struct.G) align 16 %a) call void @use_G(%struct.G* byval(%struct.G) align 16 %a)
ret void ret void
} }
;ARM-LABEL: <test_H_1>: ;ARM-LABEL: <test_H_1>:
;THUMB2-LABEL: <test_H_1>: ;THUMB2-LABEL: <test_H_1>:
;NO_NEON-LABEL:<test_H_1>: ;NO_NEON-LABEL:<test_H_1>:
;THUMB1-LABEL: <test_H_1>: ;THUMB1-LABEL: <test_H_1>:
;T1POST-LABEL: <test_H_1>: ;T1POST-LABEL: <test_H_1>:
define void @test_H_1() { define void @test_H_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.H, align 1 %a = alloca %struct.H, align 1
call void @use_H(%struct.H* byval(%struct.H) align 1 %a) call void @use_H(%struct.H* byval(%struct.H) align 1 %a)
ret void ret void
} }
;ARM-LABEL: <test_H_2>: ;ARM-LABEL: <test_H_2>:
;THUMB2-LABEL: <test_H_2>: ;THUMB2-LABEL: <test_H_2>:
;NO_NEON-LABEL:<test_H_2>: ;NO_NEON-LABEL:<test_H_2>:
;THUMB1-LABEL: <test_H_2>: ;THUMB1-LABEL: <test_H_2>:
;T1POST-LABEL: <test_H_2>: ;T1POST-LABEL: <test_H_2>:
define void @test_H_2() { define void @test_H_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.H, align 2 %a = alloca %struct.H, align 2
call void @use_H(%struct.H* byval(%struct.H) align 2 %a) call void @use_H(%struct.H* byval(%struct.H) align 2 %a)
ret void ret void
} }
;ARM-LABEL: <test_H_4>: ;ARM-LABEL: <test_H_4>:
;THUMB2-LABEL: <test_H_4>: ;THUMB2-LABEL: <test_H_4>:
;NO_NEON-LABEL:<test_H_4>: ;NO_NEON-LABEL:<test_H_4>:
;THUMB1-LABEL: <test_H_4>: ;THUMB1-LABEL: <test_H_4>:
;T1POST-LABEL: <test_H_4>: ;T1POST-LABEL: <test_H_4>:
define void @test_H_4() { define void @test_H_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.H, align 4 %a = alloca %struct.H, align 4
call void @use_H(%struct.H* byval(%struct.H) align 4 %a) call void @use_H(%struct.H* byval(%struct.H) align 4 %a)
ret void ret void
} }
;ARM-LABEL: <test_H_8>: ;ARM-LABEL: <test_H_8>:
;THUMB2-LABEL: <test_H_8>: ;THUMB2-LABEL: <test_H_8>:
;NO_NEON-LABEL:<test_H_8>: ;NO_NEON-LABEL:<test_H_8>:
;THUMB1-LABEL: <test_H_8>: ;THUMB1-LABEL: <test_H_8>:
;T1POST-LABEL: <test_H_8>: ;T1POST-LABEL: <test_H_8>:
define void @test_H_8() { define void @test_H_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.H, align 8 %a = alloca %struct.H, align 8
call void @use_H(%struct.H* byval(%struct.H) align 8 %a) call void @use_H(%struct.H* byval(%struct.H) align 8 %a)
ret void ret void
} }
;ARM-LABEL: <test_H_16>: ;ARM-LABEL: <test_H_16>:
;THUMB2-LABEL: <test_H_16>: ;THUMB2-LABEL: <test_H_16>:
;NO_NEON-LABEL:<test_H_16>: ;NO_NEON-LABEL:<test_H_16>:
;THUMB1-LABEL: <test_H_16>: ;THUMB1-LABEL: <test_H_16>:
;T1POST-LABEL: <test_H_16>: ;T1POST-LABEL: <test_H_16>:
define void @test_H_16() { define void @test_H_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.H, align 16 %a = alloca %struct.H, align 16
call void @use_H(%struct.H* byval(%struct.H) align 16 %a) call void @use_H(%struct.H* byval(%struct.H) align 16 %a)
ret void ret void
} }
;ARM-LABEL: <test_I_1>: ;ARM-LABEL: <test_I_1>:
;THUMB2-LABEL: <test_I_1>: ;THUMB2-LABEL: <test_I_1>:
;NO_NEON-LABEL:<test_I_1>: ;NO_NEON-LABEL:<test_I_1>:
;THUMB1-LABEL: <test_I_1>: ;THUMB1-LABEL: <test_I_1>:
;T1POST-LABEL: <test_I_1>: ;T1POST-LABEL: <test_I_1>:
define void @test_I_1() { define void @test_I_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.I, align 1 %a = alloca %struct.I, align 1
call void @use_I(%struct.I* byval(%struct.I) align 1 %a) call void @use_I(%struct.I* byval(%struct.I) align 1 %a)
ret void ret void
} }
;ARM-LABEL: <test_I_2>: ;ARM-LABEL: <test_I_2>:
;THUMB2-LABEL: <test_I_2>: ;THUMB2-LABEL: <test_I_2>:
;NO_NEON-LABEL:<test_I_2>: ;NO_NEON-LABEL:<test_I_2>:
;THUMB1-LABEL: <test_I_2>: ;THUMB1-LABEL: <test_I_2>:
;T1POST-LABEL: <test_I_2>: ;T1POST-LABEL: <test_I_2>:
define void @test_I_2() { define void @test_I_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.I, align 2 %a = alloca %struct.I, align 2
call void @use_I(%struct.I* byval(%struct.I) align 2 %a) call void @use_I(%struct.I* byval(%struct.I) align 2 %a)
ret void ret void
} }
;ARM-LABEL: <test_I_4>: ;ARM-LABEL: <test_I_4>:
;THUMB2-LABEL: <test_I_4>: ;THUMB2-LABEL: <test_I_4>:
;NO_NEON-LABEL:<test_I_4>: ;NO_NEON-LABEL:<test_I_4>:
;THUMB1-LABEL: <test_I_4>: ;THUMB1-LABEL: <test_I_4>:
;T1POST-LABEL: <test_I_4>: ;T1POST-LABEL: <test_I_4>:
define void @test_I_4() { define void @test_I_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.I, align 4 %a = alloca %struct.I, align 4
call void @use_I(%struct.I* byval(%struct.I) align 4 %a) call void @use_I(%struct.I* byval(%struct.I) align 4 %a)
ret void ret void
} }
;ARM-LABEL: <test_I_8>: ;ARM-LABEL: <test_I_8>:
;THUMB2-LABEL: <test_I_8>: ;THUMB2-LABEL: <test_I_8>:
;NO_NEON-LABEL:<test_I_8>: ;NO_NEON-LABEL:<test_I_8>:
;THUMB1-LABEL: <test_I_8>: ;THUMB1-LABEL: <test_I_8>:
;T1POST-LABEL: <test_I_8>: ;T1POST-LABEL: <test_I_8>:
define void @test_I_8() { define void @test_I_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.I, align 8 %a = alloca %struct.I, align 8
call void @use_I(%struct.I* byval(%struct.I) align 8 %a) call void @use_I(%struct.I* byval(%struct.I) align 8 %a)
ret void ret void
} }
;ARM-LABEL: <test_I_16>: ;ARM-LABEL: <test_I_16>:
;THUMB2-LABEL: <test_I_16>: ;THUMB2-LABEL: <test_I_16>:
;NO_NEON-LABEL:<test_I_16>: ;NO_NEON-LABEL:<test_I_16>:
;THUMB1-LABEL: <test_I_16>: ;THUMB1-LABEL: <test_I_16>:
;T1POST-LABEL: <test_I_16>: ;T1POST-LABEL: <test_I_16>:
define void @test_I_16() { define void @test_I_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.I, align 16 %a = alloca %struct.I, align 16
call void @use_I(%struct.I* byval(%struct.I) align 16 %a) call void @use_I(%struct.I* byval(%struct.I) align 16 %a)
ret void ret void
} }
;ARM-LABEL: <test_J_1>: ;ARM-LABEL: <test_J_1>:
;THUMB2-LABEL: <test_J_1>: ;THUMB2-LABEL: <test_J_1>:
;NO_NEON-LABEL:<test_J_1>: ;NO_NEON-LABEL:<test_J_1>:
;THUMB1-LABEL: <test_J_1>: ;THUMB1-LABEL: <test_J_1>:
;T1POST-LABEL: <test_J_1>: ;T1POST-LABEL: <test_J_1>:
define void @test_J_1() { define void @test_J_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;ARM: bne ;ARM: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.J, align 1 %a = alloca %struct.J, align 1
call void @use_J(%struct.J* byval(%struct.J) align 1 %a) call void @use_J(%struct.J* byval(%struct.J) align 1 %a)
ret void ret void
} }
;ARM-LABEL: <test_J_2>: ;ARM-LABEL: <test_J_2>:
;THUMB2-LABEL: <test_J_2>: ;THUMB2-LABEL: <test_J_2>:
;NO_NEON-LABEL:<test_J_2>: ;NO_NEON-LABEL:<test_J_2>:
;THUMB1-LABEL: <test_J_2>: ;THUMB1-LABEL: <test_J_2>:
;T1POST-LABEL: <test_J_2>: ;T1POST-LABEL: <test_J_2>:
define void @test_J_2() { define void @test_J_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;ARM: bne ;ARM: bne
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.J, align 2 %a = alloca %struct.J, align 2
call void @use_J(%struct.J* byval(%struct.J) align 2 %a) call void @use_J(%struct.J* byval(%struct.J) align 2 %a)
ret void ret void
} }
;ARM-LABEL: <test_J_4>: ;ARM-LABEL: <test_J_4>:
;THUMB2-LABEL: <test_J_4>: ;THUMB2-LABEL: <test_J_4>:
;NO_NEON-LABEL:<test_J_4>: ;NO_NEON-LABEL:<test_J_4>:
;THUMB1-LABEL: <test_J_4>: ;THUMB1-LABEL: <test_J_4>:
;T1POST-LABEL: <test_J_4>: ;T1POST-LABEL: <test_J_4>:
define void @test_J_4() { define void @test_J_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;ARM: bne ;ARM: bne
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.J, align 4 %a = alloca %struct.J, align 4
call void @use_J(%struct.J* byval(%struct.J) align 4 %a) call void @use_J(%struct.J* byval(%struct.J) align 4 %a)
ret void ret void
Show All 9 Lines
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.J, align 8 %a = alloca %struct.J, align 8
call void @use_J(%struct.J* byval(%struct.J) align 8 %a) call void @use_J(%struct.J* byval(%struct.J) align 8 %a)
ret void ret void
Show All 9 Lines
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.J, align 16 %a = alloca %struct.J, align 16
call void @use_J(%struct.J* byval(%struct.J) align 16 %a) call void @use_J(%struct.J* byval(%struct.J) align 16 %a)
ret void ret void
} }
;ARM-LABEL: <test_K_1>: ;ARM-LABEL: <test_K_1>:
;THUMB2-LABEL: <test_K_1>: ;THUMB2-LABEL: <test_K_1>:
;NO_NEON-LABEL:<test_K_1>: ;NO_NEON-LABEL:<test_K_1>:
;THUMB1-LABEL: <test_K_1>: ;THUMB1-LABEL: <test_K_1>:
;T1POST-LABEL: <test_K_1>: ;T1POST-LABEL: <test_K_1>:
define void @test_K_1() { define void @test_K_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;ARM: bne ;ARM: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.K, align 1 %a = alloca %struct.K, align 1
call void @use_K(%struct.K* byval(%struct.K) align 1 %a) call void @use_K(%struct.K* byval(%struct.K) align 1 %a)
ret void ret void
} }
;ARM-LABEL: <test_K_2>: ;ARM-LABEL: <test_K_2>:
;THUMB2-LABEL: <test_K_2>: ;THUMB2-LABEL: <test_K_2>:
;NO_NEON-LABEL:<test_K_2>: ;NO_NEON-LABEL:<test_K_2>:
;THUMB1-LABEL: <test_K_2>: ;THUMB1-LABEL: <test_K_2>:
;T1POST-LABEL: <test_K_2>: ;T1POST-LABEL: <test_K_2>:
define void @test_K_2() { define void @test_K_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;ARM: bne ;ARM: bne
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.K, align 2 %a = alloca %struct.K, align 2
call void @use_K(%struct.K* byval(%struct.K) align 2 %a) call void @use_K(%struct.K* byval(%struct.K) align 2 %a)
ret void ret void
} }
;ARM-LABEL: <test_K_4>: ;ARM-LABEL: <test_K_4>:
;THUMB2-LABEL: <test_K_4>: ;THUMB2-LABEL: <test_K_4>:
;NO_NEON-LABEL:<test_K_4>: ;NO_NEON-LABEL:<test_K_4>:
;THUMB1-LABEL: <test_K_4>: ;THUMB1-LABEL: <test_K_4>:
;T1POST-LABEL: <test_K_4>: ;T1POST-LABEL: <test_K_4>:
define void @test_K_4() { define void @test_K_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;ARM: bne ;ARM: bne
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.K, align 4 %a = alloca %struct.K, align 4
call void @use_K(%struct.K* byval(%struct.K) align 4 %a) call void @use_K(%struct.K* byval(%struct.K) align 4 %a)
ret void ret void
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;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.K, align 8 %a = alloca %struct.K, align 8
call void @use_K(%struct.K* byval(%struct.K) align 8 %a) call void @use_K(%struct.K* byval(%struct.K) align 8 %a)
ret void ret void
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;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.K, align 16 %a = alloca %struct.K, align 16
call void @use_K(%struct.K* byval(%struct.K) align 16 %a) call void @use_K(%struct.K* byval(%struct.K) align 16 %a)
ret void ret void
} }
;ARM-LABEL: <test_L_1>: ;ARM-LABEL: <test_L_1>:
;THUMB2-LABEL: <test_L_1>: ;THUMB2-LABEL: <test_L_1>:
;NO_NEON-LABEL:<test_L_1>: ;NO_NEON-LABEL:<test_L_1>:
;THUMB1-LABEL: <test_L_1>: ;THUMB1-LABEL: <test_L_1>:
;T1POST-LABEL: <test_L_1>: ;T1POST-LABEL: <test_L_1>:
define void @test_L_1() { define void @test_L_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;ARM: bne ;ARM: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.L, align 1 %a = alloca %struct.L, align 1
call void @use_L(%struct.L* byval(%struct.L) align 1 %a) call void @use_L(%struct.L* byval(%struct.L) align 1 %a)
ret void ret void
} }
;ARM-LABEL: <test_L_2>: ;ARM-LABEL: <test_L_2>:
;THUMB2-LABEL: <test_L_2>: ;THUMB2-LABEL: <test_L_2>:
;NO_NEON-LABEL:<test_L_2>: ;NO_NEON-LABEL:<test_L_2>:
;THUMB1-LABEL: <test_L_2>: ;THUMB1-LABEL: <test_L_2>:
;T1POST-LABEL: <test_L_2>: ;T1POST-LABEL: <test_L_2>:
define void @test_L_2() { define void @test_L_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;ARM: bne ;ARM: bne
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.L, align 2 %a = alloca %struct.L, align 2
call void @use_L(%struct.L* byval(%struct.L) align 2 %a) call void @use_L(%struct.L* byval(%struct.L) align 2 %a)
ret void ret void
} }
;ARM-LABEL: <test_L_4>: ;ARM-LABEL: <test_L_4>:
;THUMB2-LABEL: <test_L_4>: ;THUMB2-LABEL: <test_L_4>:
;NO_NEON-LABEL:<test_L_4>: ;NO_NEON-LABEL:<test_L_4>:
;THUMB1-LABEL: <test_L_4>: ;THUMB1-LABEL: <test_L_4>:
;T1POST-LABEL: <test_L_4>: ;T1POST-LABEL: <test_L_4>:
define void @test_L_4() { define void @test_L_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;ARM: bne ;ARM: bne
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.L, align 4 %a = alloca %struct.L, align 4
call void @use_L(%struct.L* byval(%struct.L) align 4 %a) call void @use_L(%struct.L* byval(%struct.L) align 4 %a)
ret void ret void
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;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.L, align 8 %a = alloca %struct.L, align 8
call void @use_L(%struct.L* byval(%struct.L) align 8 %a) call void @use_L(%struct.L* byval(%struct.L) align 8 %a)
ret void ret void
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;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.L, align 16 %a = alloca %struct.L, align 16
call void @use_L(%struct.L* byval(%struct.L) align 16 %a) call void @use_L(%struct.L* byval(%struct.L) align 16 %a)
ret void ret void
} }
;V8MBASE-LABEL: <test_M>: ;V8MBASE-LABEL: <test_M>:
define void @test_M() { define void @test_M() {
;V8MBASE: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;V8MBASE: ldrb r{{[0-9]+}}, [[[BASE:r[0-9]+]]]
;V8MBASE: adds [[BASE]], #1 ;V8MBASE: adds [[BASE]], #1
;V8MBASE-NOT: movw ;V8MBASE-NOT: movw
entry: entry:
%a = alloca %struct.M, align 1 %a = alloca %struct.M, align 1
call void @use_M(%struct.M* byval(%struct.M) align 1 %a) call void @use_M(%struct.M* byval(%struct.M) align 1 %a)
ret void ret void
} }
;V8MBASE-LABEL: <test_N>: ;V8MBASE-LABEL: <test_N>:
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llvm/test/CodeGen/ARM/swifterror.ll

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; CHECK-APPLE-DAG: strb [[ID]], [r{{.*}}, #8] ; CHECK-APPLE-DAG: strb [[ID]], [r{{.*}}, #8]
; CHECK-O0-LABEL: foo: ; CHECK-O0-LABEL: foo:
; CHECK-O0: mov r{{.*}}, #16 ; CHECK-O0: mov r{{.*}}, #16
; CHECK-O0: malloc ; CHECK-O0: malloc
; CHECK-O0: mov [[ID2:r[0-9]+]], r0 ; CHECK-O0: mov [[ID2:r[0-9]+]], r0
; CHECK-O0: mov r8, [[ID2]] ; CHECK-O0: mov r8, [[ID2]]
; CHECK-O0: mov [[ID:r[0-9]+]], #1 ; CHECK-O0: mov [[ID:r[0-9]+]], #1
; CHECK-O0: strb [[ID]], {{\[}}[[ID2]], #8] ; CHECK-O0: strb [[ID]], [[[ID2]], #8]
entry: entry:
%call = call i8* @malloc(i64 16) %call = call i8* @malloc(i64 16)
%call.0 = bitcast i8* %call to %swift_error* %call.0 = bitcast i8* %call to %swift_error*
store %swift_error* %call.0, %swift_error** %error_ptr_ref store %swift_error* %call.0, %swift_error** %error_ptr_ref
%tmp = getelementptr inbounds i8, i8* %call, i64 8 %tmp = getelementptr inbounds i8, i8* %call, i64 8
store i8 1, i8* %tmp store i8 1, i8* %tmp
ret float 1.0 ret float 1.0
} }
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; spill to stack ; spill to stack
; CHECK-O0: str r8 ; CHECK-O0: str r8
; CHECK-O0: cmp r0, #0 ; CHECK-O0: cmp r0, #0
; CHECK-O0: beq ; CHECK-O0: beq
; CHECK-O0: mov r0, #16 ; CHECK-O0: mov r0, #16
; CHECK-O0: malloc ; CHECK-O0: malloc
; CHECK-O0: mov [[ID:r[0-9]+]], r0 ; CHECK-O0: mov [[ID:r[0-9]+]], r0
; CHECK-O0: mov [[ID2:[a-z0-9]+]], #1 ; CHECK-O0: mov [[ID2:[a-z0-9]+]], #1
; CHECK-O0: strb [[ID2]], {{\[}}[[ID]], #8] ; CHECK-O0: strb [[ID2]], [[[ID]], #8]
; reload from stack ; reload from stack
; CHECK-O0: ldr r8 ; CHECK-O0: ldr r8
entry: entry:
%cond = icmp ne i32 %cc, 0 %cond = icmp ne i32 %cc, 0
br i1 %cond, label %gen_error, label %normal br i1 %cond, label %gen_error, label %normal
gen_error: gen_error:
%call = call i8* @malloc(i64 16) %call = call i8* @malloc(i64 16)
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llvm/test/CodeGen/ARM/swiftself.ll

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; We cannot pretend that 'r0' is alive across the thisreturn_attribute call as ; We cannot pretend that 'r0' is alive across the thisreturn_attribute call as
; we normally would. We marked the first parameter with swiftself which means it ; we normally would. We marked the first parameter with swiftself which means it
; will no longer be passed in r0. ; will no longer be passed in r0.
declare swiftcc i8* @thisreturn_attribute(i8* returned swiftself) declare swiftcc i8* @thisreturn_attribute(i8* returned swiftself)
; OPT-LABEL: swiftself_nothisreturn: ; OPT-LABEL: swiftself_nothisreturn:
; OPT-DAG: mov [[CSREG:r[1-9].*]], r0 ; OPT-DAG: mov [[CSREG:r[1-9].*]], r0
; OPT-DAG: ldr r10, [r10] ; OPT-DAG: ldr r10, [r10]
; OPT: bl {{_?}}thisreturn_attribute ; OPT: bl {{_?}}thisreturn_attribute
; OPT: str r0, {{\[}}[[CSREG]] ; OPT: str r0, [[[CSREG]]
define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture sret(i8**), i8** noalias nocapture readonly swiftself) { define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture sret(i8**), i8** noalias nocapture readonly swiftself) {
entry: entry:
%2 = load i8*, i8** %1, align 8 %2 = load i8*, i8** %1, align 8
%3 = tail call swiftcc i8* @thisreturn_attribute(i8* swiftself %2) %3 = tail call swiftcc i8* @thisreturn_attribute(i8* swiftself %2)
store i8* %3, i8** %0, align 8 store i8* %3, i8** %0, align 8
ret void ret void
} }

llvm/test/CodeGen/ARM/thumb-big-stack.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
; RUN: llc %s -O0 -verify-machineinstrs -o - | FileCheck %s ; RUN: llc %s -O0 -verify-machineinstrs -o - | FileCheck %s
; This file uses to trigger a machine verifier error because we ; This file uses to trigger a machine verifier error because we
; were generating a stack adjustement with SP as second argument, ; were generating a stack adjustement with SP as second argument,
; which is unpredictable behavior for t2ADDrr. ; which is unpredictable behavior for t2ADDrr.
; This file has been generated from the constpool test of the test-suite. ; This file has been generated from the constpool test of the test-suite.
target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
target triple = "thumbv7s-apple-ios" target triple = "thumbv7s-apple-ios"
@.str = external unnamed_addr constant [21 x i8], align 1 @.str = external unnamed_addr constant [21 x i8], align 1
; CHECK-LABEL: f: ; CHECK-LABEL: f:
; CHECK: movw [[ADDR:(r[0-9]+|lr)]], # ; CHECK: movw [[ADDR:(r[0-9]+|lr)]], #
; CHECK-NEXT: add [[ADDR]], sp ; CHECK-NEXT: add [[ADDR]], sp
; CHECK-NEXT: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, {{\[}}[[ADDR]]:128] ; CHECK-NEXT: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [[[ADDR]]:128]
define <4 x float> @f(<4 x float> %x) { define <4 x float> @f(<4 x float> %x) {
entry: entry:
%.compoundliteral7837 = alloca <4 x float>, align 16 %.compoundliteral7837 = alloca <4 x float>, align 16
%.compoundliteral7865 = alloca <4 x float>, align 16 %.compoundliteral7865 = alloca <4 x float>, align 16
%.compoundliteral7991 = alloca <4 x float>, align 16 %.compoundliteral7991 = alloca <4 x float>, align 16
%.compoundliteral8019 = alloca <4 x float>, align 16 %.compoundliteral8019 = alloca <4 x float>, align 16
%.compoundliteral8061 = alloca <4 x float>, align 16 %.compoundliteral8061 = alloca <4 x float>, align 16
%.compoundliteral8075 = alloca <4 x float>, align 16 %.compoundliteral8075 = alloca <4 x float>, align 16
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llvm/test/CodeGen/ARM/thumb_indirect_calls.ll

; RUN: llc -mtriple=thumbv4t-eabi %s -o - | FileCheck --check-prefix=CHECK -check-prefix=CHECK-V4T %s ; RUN: llc -mtriple=thumbv4t-eabi %s -o - | FileCheck --check-prefix=CHECK -check-prefix=CHECK-V4T %s
; RUN: llc -mtriple=thumbv5t-eabi %s -o - | FileCheck --check-prefix=CHECK -check-prefix=CHECK-V5T %s ; RUN: llc -mtriple=thumbv5t-eabi %s -o - | FileCheck --check-prefix=CHECK -check-prefix=CHECK-V5T %s
@f = common global void (i32)* null, align 4 @f = common global void (i32)* null, align 4
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
define void @foo(i32 %x) { define void @foo(i32 %x) {
entry: entry:
%0 = load void (i32)*, void (i32)** @f, align 4 %0 = load void (i32)*, void (i32)** @f, align 4
tail call void %0(i32 %x) tail call void %0(i32 %x)
ret void ret void
; CHECK: ldr [[TMP:r[0-3]]], [[F:\.[A-Z0-9_]+]] ; CHECK: ldr [[TMP:r[0-3]]], [[F:\.[A-Z0-9_]+]]
; CHECK: ldr [[CALLEE:r[0-3]]], {{\[}}[[TMP]]{{\]}} ; CHECK: ldr [[CALLEE:r[0-3]]], [[[TMP]]]
; CHECK-V4T-NOT: blx ; CHECK-V4T-NOT: blx
; CHECK-V4T: bl [[INDIRECT_PAD:\.Ltmp[0-9]+]] ; CHECK-V4T: bl [[INDIRECT_PAD:\.Ltmp[0-9]+]]
; CHECK-V4T: [[F]]: ; CHECK-V4T: [[F]]:
; CHECK-V4T: [[INDIRECT_PAD]]: ; CHECK-V4T: [[INDIRECT_PAD]]:
; CHECK-V4T-NEXT: bx [[CALLEE]] ; CHECK-V4T-NEXT: bx [[CALLEE]]
; CHECK-V5T: blx [[CALLEE]] ; CHECK-V5T: blx [[CALLEE]]
} }
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llvm/test/CodeGen/ARM/vector-DAGCombine.ll

Show First 20 Lines • Show All 233 Lines • ▼ Show 20 Lines
} }
; <rdar://problem/14989896> Make sure we manage to truncate a vector from an ; <rdar://problem/14989896> Make sure we manage to truncate a vector from an
; illegal type to a legal type. ; illegal type to a legal type.
define <2 x i8> @test_truncate(<2 x i128> %in) { define <2 x i8> @test_truncate(<2 x i128> %in) {
; CHECK-LABEL: test_truncate: ; CHECK-LABEL: test_truncate:
; CHECK: vmov.32 [[REG:d[0-9]+]][0], r0 ; CHECK: vmov.32 [[REG:d[0-9]+]][0], r0
; CHECK-NEXT: mov [[BASE:r[0-9]+]], sp ; CHECK-NEXT: mov [[BASE:r[0-9]+]], sp
; CHECK-NEXT: vld1.32 {[[REG]][1]}, {{\[}}[[BASE]]:32] ; CHECK-NEXT: vld1.32 {[[REG]][1]}, [[[BASE]]:32]
; CHECK-NEXT: vmov r0, r1, [[REG]] ; CHECK-NEXT: vmov r0, r1, [[REG]]
entry: entry:
%res = trunc <2 x i128> %in to <2 x i8> %res = trunc <2 x i128> %in to <2 x i8>
ret <2 x i8> %res ret <2 x i8> %res
} }

llvm/test/CodeGen/ARM/vld3.ll

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32.p0i8(i8* %tmp0, i32 1)
%tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2 %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2
%tmp4 = add <4 x i32> %tmp2, %tmp3 %tmp4 = add <4 x i32> %tmp2, %tmp3
ret <4 x i32> %tmp4 ret <4 x i32> %tmp4
} }
;Check for a post-increment updating load. ;Check for a post-increment updating load.
define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind { define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind {
;CHECK-LABEL: vld3Qi32_update: ;CHECK-LABEL: vld3Qi32_update:
;CHECK: vld3.32 {d16, d18, d20}, {{\[}}[[R:r[0-9]+|lr]]]! ;CHECK: vld3.32 {d16, d18, d20}, [[[R:r[0-9]+|lr]]]!
;CHECK: vld3.32 {d17, d19, d21}, {{\[}}[[R]]]! ;CHECK: vld3.32 {d17, d19, d21}, [[[R]]]!
%A = load i32*, i32** %ptr %A = load i32*, i32** %ptr
%tmp0 = bitcast i32* %A to i8* %tmp0 = bitcast i32* %A to i8*
%tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32.p0i8(i8* %tmp0, i32 1) %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32.p0i8(i8* %tmp0, i32 1)
%tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0 %tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2 %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2
%tmp4 = add <4 x i32> %tmp2, %tmp3 %tmp4 = add <4 x i32> %tmp2, %tmp3
%tmp5 = getelementptr i32, i32* %A, i32 12 %tmp5 = getelementptr i32, i32* %A, i32 12
store i32* %tmp5, i32** %ptr store i32* %tmp5, i32** %ptr
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llvm/test/CodeGen/ARM/win32-ssp.ll

; RUN: llc -mtriple=thumbv7-w64-mingw32 < %s -o - | FileCheck --check-prefix=MINGW %s ; RUN: llc -mtriple=thumbv7-w64-mingw32 < %s -o - | FileCheck --check-prefix=MINGW %s
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture)
declare dso_local void @other(i8*) declare dso_local void @other(i8*)
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture)
define dso_local void @func() sspstrong { define dso_local void @func() sspstrong {
entry: entry:
; MINGW-LABEL: func: ; MINGW-LABEL: func:
; MINGW: movw [[REG:r[0-9]+]], :lower16:.refptr.__stack_chk_guard ; MINGW: movw [[REG:r[0-9]+]], :lower16:.refptr.__stack_chk_guard
; MINGW: movt [[REG]], :upper16:.refptr.__stack_chk_guard ; MINGW: movt [[REG]], :upper16:.refptr.__stack_chk_guard
; MINGW: ldr [[REG2:r[0-9]+]], {{\[}}[[REG]]] ; MINGW: ldr [[REG2:r[0-9]+]], [[[REG]]]
; MINGW: ldr {{r[0-9]+}}, {{\[}}[[REG2]]] ; MINGW: ldr {{r[0-9]+}}, [[[REG2]]]
; MINGW: bl other ; MINGW: bl other
; MINGW: movw [[REG3:r[0-9]+]], :lower16:.refptr.__stack_chk_guard ; MINGW: movw [[REG3:r[0-9]+]], :lower16:.refptr.__stack_chk_guard
; MINGW: movt [[REG3]], :upper16:.refptr.__stack_chk_guard ; MINGW: movt [[REG3]], :upper16:.refptr.__stack_chk_guard
; MINGW: ldr [[REG4:r[0-9]+]], {{\[}}[[REG3]]] ; MINGW: ldr [[REG4:r[0-9]+]], [[[REG3]]]
; MINGW: ldr {{r[0-9]+}}, {{\[}}[[REG4]]] ; MINGW: ldr {{r[0-9]+}}, [[[REG4]]]
; MINGW: bl __stack_chk_fail ; MINGW: bl __stack_chk_fail
%c = alloca i8, align 1 %c = alloca i8, align 1
call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull %c) call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull %c)
call void @other(i8* nonnull %c) call void @other(i8* nonnull %c)
call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %c) call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %c)
ret void ret void
} }

llvm/test/CodeGen/Thumb/stack_guard_remat.ll

; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=pic -no-integrated-as | FileCheck %s -check-prefix=PIC ; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=pic -no-integrated-as | FileCheck %s -check-prefix=PIC
; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=static -no-integrated-as | FileCheck %s -check-prefix=NO-PIC -check-prefix=STATIC ; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=static -no-integrated-as | FileCheck %s -check-prefix=NO-PIC -check-prefix=STATIC
; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=dynamic-no-pic -no-integrated-as | FileCheck %s -check-prefix=NO-PIC -check-prefix=DYNAMIC-NO-PIC ; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=dynamic-no-pic -no-integrated-as | FileCheck %s -check-prefix=NO-PIC -check-prefix=DYNAMIC-NO-PIC
;PIC: foo2 ;PIC: foo2
;PIC: ldr [[SAVED_GUARD:r[0-9]+]], [[GUARD_STACK_OFFSET:LCPI[0-9_]+]] ;PIC: ldr [[SAVED_GUARD:r[0-9]+]], [[GUARD_STACK_OFFSET:LCPI[0-9_]+]]
;PIC-NEXT: add [[SAVED_GUARD]], sp ;PIC-NEXT: add [[SAVED_GUARD]], sp
;PIC-NEXT: ldr [[SAVED_GUARD]], {{\[}}[[SAVED_GUARD]]{{\]}} ;PIC-NEXT: ldr [[SAVED_GUARD]], [[[SAVED_GUARD]]]
;PIC-NEXT: ldr [[ORIGINAL_GUARD:r[0-9]+]], [[ORIGINAL_GUARD_LABEL:LCPI[0-9_]+]] ;PIC-NEXT: ldr [[ORIGINAL_GUARD:r[0-9]+]], [[ORIGINAL_GUARD_LABEL:LCPI[0-9_]+]]
;PIC-NEXT: [[LABEL1:LPC[0-9_]+]]: ;PIC-NEXT: [[LABEL1:LPC[0-9_]+]]:
;PIC-NEXT: add [[ORIGINAL_GUARD]], pc ;PIC-NEXT: add [[ORIGINAL_GUARD]], pc
;PIC-NEXT: ldr [[ORIGINAL_GUARD]], {{\[}}[[ORIGINAL_GUARD]]{{\]}} ;PIC-NEXT: ldr [[ORIGINAL_GUARD]], [[[ORIGINAL_GUARD]]]
;PIC-NEXT: ldr [[ORIGINAL_GUARD]], {{\[}}[[ORIGINAL_GUARD]]{{\]}} ;PIC-NEXT: ldr [[ORIGINAL_GUARD]], [[[ORIGINAL_GUARD]]]
;PIC-NEXT: cmp [[ORIGINAL_GUARD]], [[SAVED_GUARD]] ;PIC-NEXT: cmp [[ORIGINAL_GUARD]], [[SAVED_GUARD]]
;PIC: [[GUARD_STACK_OFFSET]]: ;PIC: [[GUARD_STACK_OFFSET]]:
;PIC-NEXT: .long 1028 ;PIC-NEXT: .long 1028
;PIC: [[ORIGINAL_GUARD_LABEL]]: ;PIC: [[ORIGINAL_GUARD_LABEL]]:
;PIC-NEXT: .long L___stack_chk_guard$non_lazy_ptr-([[LABEL1]]+4) ;PIC-NEXT: .long L___stack_chk_guard$non_lazy_ptr-([[LABEL1]]+4)
;NO-PIC: foo2 ;NO-PIC: foo2
;NO-PIC: ldr [[SAVED_GUARD:r[0-9]+]], [[GUARD_STACK_OFFSET:LCPI[0-9_]+]] ;NO-PIC: ldr [[SAVED_GUARD:r[0-9]+]], [[GUARD_STACK_OFFSET:LCPI[0-9_]+]]
;NO-PIC-NEXT: add [[SAVED_GUARD]], sp ;NO-PIC-NEXT: add [[SAVED_GUARD]], sp
;NO-PIC-NEXT: ldr [[SAVED_GUARD]], {{\[}}[[SAVED_GUARD]]{{\]}} ;NO-PIC-NEXT: ldr [[SAVED_GUARD]], [[[SAVED_GUARD]]]
;NO-PIC-NEXT: ldr [[ORIGINAL_GUARD:r[0-9]+]], [[ORIGINAL_GUARD_LABEL:LCPI[0-9_]+]] ;NO-PIC-NEXT: ldr [[ORIGINAL_GUARD:r[0-9]+]], [[ORIGINAL_GUARD_LABEL:LCPI[0-9_]+]]
;NO-PIC-NOT: LPC ;NO-PIC-NOT: LPC
;NO-PIC-NEXT: ldr [[ORIGINAL_GUARD]], {{\[}}[[ORIGINAL_GUARD]]{{\]}} ;NO-PIC-NEXT: ldr [[ORIGINAL_GUARD]], [[[ORIGINAL_GUARD]]]
;DYNAMIC-NO-PIC-NEXT: ldr [[ORIGINAL_GUARD]], {{\[}}[[ORIGINAL_GUARD]]{{\]}} ;DYNAMIC-NO-PIC-NEXT: ldr [[ORIGINAL_GUARD]], [[[ORIGINAL_GUARD]]]
;NO-PIC-NEXT: cmp [[ORIGINAL_GUARD]], [[SAVED_GUARD]] ;NO-PIC-NEXT: cmp [[ORIGINAL_GUARD]], [[SAVED_GUARD]]
;STATIC: [[GUARD_STACK_OFFSET]]: ;STATIC: [[GUARD_STACK_OFFSET]]:
;STATIC-NEXT: .long 1028 ;STATIC-NEXT: .long 1028
;STATIC: [[ORIGINAL_GUARD_LABEL]]: ;STATIC: [[ORIGINAL_GUARD_LABEL]]:
;STATIC-NEXT: .long ___stack_chk_guard ;STATIC-NEXT: .long ___stack_chk_guard
;DYNAMIC-NO-PIC: [[GUARD_STACK_OFFSET]]: ;DYNAMIC-NO-PIC: [[GUARD_STACK_OFFSET]]:
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llvm/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll

; RUN: llc -mtriple=thumbv7-apple-darwin10 -arm-atomic-cfg-tidy=0 < %s | FileCheck %s ; RUN: llc -mtriple=thumbv7-apple-darwin10 -arm-atomic-cfg-tidy=0 < %s | FileCheck %s
%struct.op = type { %struct.op*, %struct.op*, %struct.op* ()*, i32, i16, i16, i8, i8 } %struct.op = type { %struct.op*, %struct.op*, %struct.op* ()*, i32, i16, i16, i8, i8 }
; CHECK: Perl_ck_sort ; CHECK: Perl_ck_sort
; CHECK: ldr ; CHECK: ldr
; CHECK: mov [[REGISTER:(r[0-9]+)|(lr)]] ; CHECK: mov [[REGISTER:(r[0-9]+)|(lr)]]
; CHECK: str {{(r[0-9])|(lr)}}, {{\[}}[[REGISTER]]{{\]}}, #24 ; CHECK: str {{(r[0-9])|(lr)}}, [[[REGISTER]]], #24
define void @Perl_ck_sort() nounwind optsize { define void @Perl_ck_sort() nounwind optsize {
entry: entry:
%tmp27 = load %struct.op*, %struct.op** undef, align 4 %tmp27 = load %struct.op*, %struct.op** undef, align 4
switch i16 undef, label %if.end151 [ switch i16 undef, label %if.end151 [
i16 178, label %if.then60 i16 178, label %if.then60
i16 177, label %if.then60 i16 177, label %if.then60
] ]
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llvm/test/CodeGen/Thumb2/stack_guard_remat.ll

; RUN: llc < %s -mtriple=thumbv7-apple-ios -relocation-model=pic -no-integrated-as | FileCheck %s -check-prefix=PIC ; RUN: llc < %s -mtriple=thumbv7-apple-ios -relocation-model=pic -no-integrated-as | FileCheck %s -check-prefix=PIC
; RUN: llc < %s -mtriple=thumbv7-apple-ios -relocation-model=static -no-integrated-as | FileCheck %s -check-prefix=STATIC ; RUN: llc < %s -mtriple=thumbv7-apple-ios -relocation-model=static -no-integrated-as | FileCheck %s -check-prefix=STATIC
; RUN: llc < %s -mtriple=thumbv7-apple-ios -relocation-model=dynamic-no-pic -no-integrated-as | FileCheck %s -check-prefix=DYNAMIC-NO-PIC ; RUN: llc < %s -mtriple=thumbv7-apple-ios -relocation-model=dynamic-no-pic -no-integrated-as | FileCheck %s -check-prefix=DYNAMIC-NO-PIC
;PIC: foo2 ;PIC: foo2
;PIC: movw [[R0:r[0-9]+]], :lower16:(L___stack_chk_guard$non_lazy_ptr-([[LABEL0:LPC[0-9_]+]]+4)) ;PIC: movw [[R0:r[0-9]+]], :lower16:(L___stack_chk_guard$non_lazy_ptr-([[LABEL0:LPC[0-9_]+]]+4))
;PIC: movt [[R0]], :upper16:(L___stack_chk_guard$non_lazy_ptr-([[LABEL0]]+4)) ;PIC: movt [[R0]], :upper16:(L___stack_chk_guard$non_lazy_ptr-([[LABEL0]]+4))
;PIC: [[LABEL0]]: ;PIC: [[LABEL0]]:
;PIC: add [[R0]], pc ;PIC: add [[R0]], pc
;PIC: ldr [[R1:r[0-9]+]], {{\[}}[[R0]]{{\]}} ;PIC: ldr [[R1:r[0-9]+]], [[[R0]]]
;PIC: ldr {{r[0-9]+}}, {{\[}}[[R1]]{{\]}} ;PIC: ldr {{r[0-9]+}}, [[[R1]]]
;STATIC: foo2 ;STATIC: foo2
;STATIC: movw [[R0:r[0-9]+]], :lower16:___stack_chk_guard ;STATIC: movw [[R0:r[0-9]+]], :lower16:___stack_chk_guard
;STATIC: movt [[R0]], :upper16:___stack_chk_guard ;STATIC: movt [[R0]], :upper16:___stack_chk_guard
;STATIC: ldr {{r[0-9]+}}, {{\[}}[[R0]]{{\]}} ;STATIC: ldr {{r[0-9]+}}, [[[R0]]]
;DYNAMIC-NO-PIC: foo2 ;DYNAMIC-NO-PIC: foo2
;DYNAMIC-NO-PIC: movw [[R0:r[0-9]+]], :lower16:L___stack_chk_guard$non_lazy_ptr ;DYNAMIC-NO-PIC: movw [[R0:r[0-9]+]], :lower16:L___stack_chk_guard$non_lazy_ptr
;DYNAMIC-NO-PIC: movt [[R0]], :upper16:L___stack_chk_guard$non_lazy_ptr ;DYNAMIC-NO-PIC: movt [[R0]], :upper16:L___stack_chk_guard$non_lazy_ptr
;DYNAMIC-NO-PIC: ldr {{r[0-9]+}}, {{\[}}[[R0]]{{\]}} ;DYNAMIC-NO-PIC: ldr {{r[0-9]+}}, [[[R0]]]
; Function Attrs: nounwind ssp ; Function Attrs: nounwind ssp
define i32 @test_stack_guard_remat() #0 { define i32 @test_stack_guard_remat() #0 {
%a1 = alloca [256 x i32], align 4 %a1 = alloca [256 x i32], align 4
%1 = bitcast [256 x i32]* %a1 to i8* %1 = bitcast [256 x i32]* %a1 to i8*
call void @llvm.lifetime.start.p0i8(i64 1024, i8* %1) call void @llvm.lifetime.start.p0i8(i64 1024, i8* %1)
%2 = getelementptr inbounds [256 x i32], [256 x i32]* %a1, i32 0, i32 0 %2 = getelementptr inbounds [256 x i32], [256 x i32]* %a1, i32 0, i32 0
call void @foo3(i32* %2) #3 call void @foo3(i32* %2) #3
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llvm/test/CodeGen/XCore/epilogue_prologue.ll

Show First 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
} }
; FP + large frame: spill FP+SR+LR = entsp 2 + 256 + extsp 1 ; FP + large frame: spill FP+SR+LR = entsp 2 + 256 + extsp 1
; CHECKFP-LABEL: f8: ; CHECKFP-LABEL: f8:
; CHECKFP: entsp 258 ; CHECKFP: entsp 258
; CHECKFP-NEXT: stw r10, sp[1] ; CHECKFP-NEXT: stw r10, sp[1]
; CHECKFP-NEXT: ldaw r10, sp[0] ; CHECKFP-NEXT: ldaw r10, sp[0]
; CHECKFP-NEXT: mkmsk [[REG:r[0-9]+]], 8 ; CHECKFP-NEXT: mkmsk [[REG:r[0-9]+]], 8
; CHECKFP-NEXT: ldaw r0, r10{{\[}}[[REG]]{{\]}} ; CHECKFP-NEXT: ldaw r0, r10[[[REG]]]
; CHECKFP-NEXT: extsp 1 ; CHECKFP-NEXT: extsp 1
; CHECKFP-NEXT: bl f5 ; CHECKFP-NEXT: bl f5
; CHECKFP-NEXT: ldaw sp, sp[1] ; CHECKFP-NEXT: ldaw sp, sp[1]
; CHECKFP-NEXT: set sp, r10 ; CHECKFP-NEXT: set sp, r10
; CHECKFP-NEXT: ldw r10, sp[1] ; CHECKFP-NEXT: ldw r10, sp[1]
; CHECKFP-NEXT: retsp 258 ; CHECKFP-NEXT: retsp 258
; ;
; !FP + large frame: spill SR+SR+LR = entsp 3 + 256 ; !FP + large frame: spill SR+SR+LR = entsp 3 + 256
Show All 11 Lines
} }
; FP + large frame: spill FP+SR+LR = entsp 2 + 32768 + extsp 1 ; FP + large frame: spill FP+SR+LR = entsp 2 + 32768 + extsp 1
; CHECKFP-LABEL: f9: ; CHECKFP-LABEL: f9:
; CHECKFP: entsp 32770 ; CHECKFP: entsp 32770
; CHECKFP-NEXT: stw r10, sp[1] ; CHECKFP-NEXT: stw r10, sp[1]
; CHECKFP-NEXT: ldaw r10, sp[0] ; CHECKFP-NEXT: ldaw r10, sp[0]
; CHECKFP-NEXT: ldc [[REG:r[0-9]+]], 32767 ; CHECKFP-NEXT: ldc [[REG:r[0-9]+]], 32767
; CHECKFP-NEXT: ldaw r0, r10{{\[}}[[REG]]{{\]}} ; CHECKFP-NEXT: ldaw r0, r10[[[REG]]]
; CHECKFP-NEXT: extsp 1 ; CHECKFP-NEXT: extsp 1
; CHECKFP-NEXT: bl f5 ; CHECKFP-NEXT: bl f5
; CHECKFP-NEXT: ldaw sp, sp[1] ; CHECKFP-NEXT: ldaw sp, sp[1]
; CHECKFP-NEXT: set sp, r10 ; CHECKFP-NEXT: set sp, r10
; CHECKFP-NEXT: ldw r10, sp[1] ; CHECKFP-NEXT: ldw r10, sp[1]
; CHECKFP-NEXT: retsp 32770 ; CHECKFP-NEXT: retsp 32770
; ;
; !FP + large frame: spill SR+SR+LR = entsp 3 + 32768 ; !FP + large frame: spill SR+SR+LR = entsp 3 + 32768
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llvm/test/CodeGen/XCore/scavenging.ll

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
; !FP + large frame: spill SR+SR = entsp 2 + 100000 ; !FP + large frame: spill SR+SR = entsp 2 + 100000
; CHECK-LABEL: ScavengeSlots: ; CHECK-LABEL: ScavengeSlots:
; CHECK: entsp 65535 ; CHECK: entsp 65535
; CHECK: extsp 34467 ; CHECK: extsp 34467
; scavenge r11 ; scavenge r11
; CHECK: ldaw r11, sp[0] ; CHECK: ldaw r11, sp[0]
; scavenge r4 using SR spill slot ; scavenge r4 using SR spill slot
; CHECK: stw r4, sp[1] ; CHECK: stw r4, sp[1]
; CHECK: ldw r4, cp{{\[}}[[ARG5]]{{\]}} ; CHECK: ldw r4, cp[[[ARG5]]]
; r11 used to load 5th argument ; r11 used to load 5th argument
; CHECK: ldw r11, r11[r4] ; CHECK: ldw r11, r11[r4]
; CHECK: ldaw r4, sp[0] ; CHECK: ldaw r4, sp[0]
; scavenge r5 using SR spill slot ; scavenge r5 using SR spill slot
; CHECK: stw r5, sp[0] ; CHECK: stw r5, sp[0]
; CHECK: ldw r5, cp{{\[}}[[INDEX0]]{{\]}} ; CHECK: ldw r5, cp[[[INDEX0]]]
; r4 & r5 used by InsertSPConstInst() to emit STW_l3r instruction. ; r4 & r5 used by InsertSPConstInst() to emit STW_l3r instruction.
; CHECK: stw r0, r4[r5] ; CHECK: stw r0, r4[r5]
; CHECK: ldaw r0, sp[0] ; CHECK: ldaw r0, sp[0]
; CHECK: ldw r5, cp{{\[}}[[INDEX1]]{{\]}} ; CHECK: ldw r5, cp[[[INDEX1]]]
; CHECK: stw r1, r0[r5] ; CHECK: stw r1, r0[r5]
; CHECK: ldaw r0, sp[0] ; CHECK: ldaw r0, sp[0]
; CHECK: ldw r1, cp{{\[}}[[INDEX2]]{{\]}} ; CHECK: ldw r1, cp[[[INDEX2]]]
; CHECK: stw r2, r0[r1] ; CHECK: stw r2, r0[r1]
; CHECK: ldaw r0, sp[0] ; CHECK: ldaw r0, sp[0]
; CHECK: ldw r1, cp{{\[}}[[INDEX3]]{{\]}} ; CHECK: ldw r1, cp[[[INDEX3]]]
; CHECK: stw r3, r0[r1] ; CHECK: stw r3, r0[r1]
; CHECK: ldaw r0, sp[0] ; CHECK: ldaw r0, sp[0]
; CHECK: ldw r1, cp{{\[}}[[INDEX4]]{{\]}} ; CHECK: ldw r1, cp[[[INDEX4]]]
; CHECK: stw r11, r0[r1] ; CHECK: stw r11, r0[r1]
; CHECK: ldaw sp, sp[65535] ; CHECK: ldaw sp, sp[65535]
; CHECK: ldw r4, sp[1] ; CHECK: ldw r4, sp[1]
; CHECK: ldw r5, sp[0] ; CHECK: ldw r5, sp[0]
; CHECK: retsp 34467 ; CHECK: retsp 34467
define void @ScavengeSlots(i32 %r0, i32 %r1, i32 %r2, i32 %r3, i32 %r4) nounwind { define void @ScavengeSlots(i32 %r0, i32 %r1, i32 %r2, i32 %r3, i32 %r4) nounwind {
entry: entry:
%Data = alloca [100000 x i32] %Data = alloca [100000 x i32]
Show All 12 Lines

llvm/test/CodeGen/XCore/varargs.ll

; RUN: llc < %s -march=xcore | FileCheck %s ; RUN: llc < %s -march=xcore | FileCheck %s
define void @_Z1fz(...) { define void @_Z1fz(...) {
entry: entry:
; CHECK-LABEL: _Z1fz: ; CHECK-LABEL: _Z1fz:
; CHECK: extsp 3 ; CHECK: extsp 3
; CHECK: stw r[[REG:[0-3]{1,1}]] ; CHECK: stw r[[REG:[0-3]{1,1}]]
; CHECK: , sp{{\[}}[[REG]]{{\]}} ; CHECK: , sp[[[REG]]]
; CHECK: stw r[[REG:[0-3]{1,1}]] ; CHECK: stw r[[REG:[0-3]{1,1}]]
; CHECK: , sp{{\[}}[[REG]]{{\]}} ; CHECK: , sp[[[REG]]]
; CHECK: stw r[[REG:[0-3]{1,1}]] ; CHECK: stw r[[REG:[0-3]{1,1}]]
; CHECK: , sp{{\[}}[[REG]]{{\]}} ; CHECK: , sp[[[REG]]]
; CHECK: stw r[[REG:[0-3]{1,1}]] ; CHECK: stw r[[REG:[0-3]{1,1}]]
; CHECK: , sp{{\[}}[[REG]]{{\]}} ; CHECK: , sp[[[REG]]]
; CHECK: ldaw sp, sp[3] ; CHECK: ldaw sp, sp[3]
; CHECK: retsp 0 ; CHECK: retsp 0
ret void ret void
} }
declare void @llvm.va_start(i8*) nounwind declare void @llvm.va_start(i8*) nounwind
declare void @llvm.va_end(i8*) nounwind declare void @llvm.va_end(i8*) nounwind
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llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll

Show All 39 Lines.preheader:
%18 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %7 %18 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %7
%19 = addrspacecast float addrspace(3)* %18 to float* %19 = addrspacecast float addrspace(3)* %18 to float*
%20 = load float, float* %19, align 4 %20 = load float, float* %19, align 4
%21 = fadd float %17, %20 %21 = fadd float %17, %20
store float %21, float* %output, align 4 store float %21, float* %output, align 4
ret void ret void
} }
; PTX-LABEL: sum_of_array( ; PTX-LABEL: sum_of_array(
; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG:%(rd|r)[0-9]+]]{{\]}} ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG:%(rd|r)[0-9]+]]]
; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+4{{\]}} ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+4]
; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+128{{\]}} ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+128]
; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}} ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+132]
; IR-LABEL: @sum_of_array( ; IR-LABEL: @sum_of_array(
; TODO: GVN is unable to preserve the "inbounds" keyword on the first GEP. Need ; TODO: GVN is unable to preserve the "inbounds" keyword on the first GEP. Need
; some infrastructure changes to enable such optimizations. ; some infrastructure changes to enable such optimizations.
; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} ; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 1 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 1
; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 32 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 32
; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 33 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 33
Show All 25 Lines.preheader:
%16 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %6 %16 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %6
%17 = addrspacecast float addrspace(3)* %16 to float* %17 = addrspacecast float addrspace(3)* %16 to float*
%18 = load float, float* %17, align 4 %18 = load float, float* %17, align 4
%19 = fadd float %15, %18 %19 = fadd float %15, %18
store float %19, float* %output, align 4 store float %19, float* %output, align 4
ret void ret void
} }
; PTX-LABEL: sum_of_array2( ; PTX-LABEL: sum_of_array2(
; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG:%(rd|r)[0-9]+]]{{\]}} ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG:%(rd|r)[0-9]+]]]
; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+4{{\]}} ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+4]
; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+128{{\]}} ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+128]
; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}} ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+132]
; IR-LABEL: @sum_of_array2( ; IR-LABEL: @sum_of_array2(
; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} ; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 1 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 1
; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 32 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 32
; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 33 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 33
Show All 30 Lines.preheader:
%18 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %7 %18 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %7
%19 = addrspacecast float addrspace(3)* %18 to float* %19 = addrspacecast float addrspace(3)* %18 to float*
%20 = load float, float* %19, align 4 %20 = load float, float* %19, align 4
%21 = fadd float %17, %20 %21 = fadd float %17, %20
store float %21, float* %output, align 4 store float %21, float* %output, align 4
ret void ret void
} }
; PTX-LABEL: sum_of_array3( ; PTX-LABEL: sum_of_array3(
; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG:%(rd|r)[0-9]+]]{{\]}} ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG:%(rd|r)[0-9]+]]]
; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+4{{\]}} ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+4]
; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+128{{\]}} ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+128]
; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}} ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+132]
; IR-LABEL: @sum_of_array3( ; IR-LABEL: @sum_of_array3(
; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} ; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 1 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 1
; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 32 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 32
; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 33 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 33
Show All 26 Lines.preheader:
%16 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %6 %16 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %6
%17 = addrspacecast float addrspace(3)* %16 to float* %17 = addrspacecast float addrspace(3)* %16 to float*
%18 = load float, float* %17, align 4 %18 = load float, float* %17, align 4
%19 = fadd float %15, %18 %19 = fadd float %15, %18
store float %19, float* %output, align 4 store float %19, float* %output, align 4
ret void ret void
} }
; PTX-LABEL: sum_of_array4( ; PTX-LABEL: sum_of_array4(
; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG:%(rd|r)[0-9]+]]{{\]}} ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG:%(rd|r)[0-9]+]]]
; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+4{{\]}} ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+4]
; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+128{{\]}} ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+128]
; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}} ; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, [[[BASE_REG]]+132]
; IR-LABEL: @sum_of_array4( ; IR-LABEL: @sum_of_array4(
; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} ; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 1 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 1
; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 32 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 32
; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 33 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 33
Show All 12 Lines
define void @reunion(i32 %x, i32 %y, float* %input) { define void @reunion(i32 %x, i32 %y, float* %input) {
; IR-LABEL: @reunion( ; IR-LABEL: @reunion(
; PTX-LABEL: reunion( ; PTX-LABEL: reunion(
entry: entry:
%xy = add nsw i32 %x, %y %xy = add nsw i32 %x, %y
%0 = sext i32 %xy to i64 %0 = sext i32 %xy to i64
%p0 = getelementptr inbounds float, float* %input, i64 %0 %p0 = getelementptr inbounds float, float* %input, i64 %0
%v0 = load float, float* %p0, align 4 %v0 = load float, float* %p0, align 4
; PTX: ld.f32 %f{{[0-9]+}}, {{\[}}[[p0:%rd[0-9]+]]{{\]}} ; PTX: ld.f32 %f{{[0-9]+}}, [[[p0:%rd[0-9]+]]]
call void @use(float %v0) call void @use(float %v0)
%y5 = add nsw i32 %y, 5 %y5 = add nsw i32 %y, 5
%xy5 = add nsw i32 %x, %y5 %xy5 = add nsw i32 %x, %y5
%1 = sext i32 %xy5 to i64 %1 = sext i32 %xy5 to i64
%p1 = getelementptr inbounds float, float* %input, i64 %1 %p1 = getelementptr inbounds float, float* %input, i64 %1
; IR: getelementptr inbounds float, float* %p0, i64 5 ; IR: getelementptr inbounds float, float* %p0, i64 5
%v1 = load float, float* %p1, align 4 %v1 = load float, float* %p1, align 4
; PTX: ld.f32 %f{{[0-9]+}}, {{\[}}[[p0]]+20{{\]}} ; PTX: ld.f32 %f{{[0-9]+}}, [[[p0]]+20]
call void @use(float %v1) call void @use(float %v1)
ret void ret void
} }
declare void @use(float) declare void @use(float)

llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll

Show All 36 Lines; PTX: ld.param.u32 [[i:%r[0-9]+]], [slsr_after_reassociate_geps_param_1];
%i4 = shl nsw i32 %i, 2 %i4 = shl nsw i32 %i, 2
%j1 = add nsw i32 %i, 5 %j1 = add nsw i32 %i, 5
%p1 = getelementptr inbounds float, float* %arr, i32 %j1 %p1 = getelementptr inbounds float, float* %arr, i32 %j1
; CHECK: [[b1:%[0-9]+]] = getelementptr float, float* %arr, i64 [[bump:%[0-9]+]] ; CHECK: [[b1:%[0-9]+]] = getelementptr float, float* %arr, i64 [[bump:%[0-9]+]]
; PTX: mul.wide.s32 [[i4:%rd[0-9]+]], [[i]], 4; ; PTX: mul.wide.s32 [[i4:%rd[0-9]+]], [[i]], 4;
; PTX: add.s64 [[base1:%rd[0-9]+]], [[arr]], [[i4]]; ; PTX: add.s64 [[base1:%rd[0-9]+]], [[arr]], [[i4]];
%v1 = load float, float* %p1, align 4 %v1 = load float, float* %p1, align 4
; PTX: ld.f32 {{%f[0-9]+}}, {{\[}}[[base1]]+20]; ; PTX: ld.f32 {{%f[0-9]+}}, [[[base1]]+20];
call void @foo(float %v1) call void @foo(float %v1)
%j2 = add nsw i32 %i2, 5 %j2 = add nsw i32 %i2, 5
%p2 = getelementptr inbounds float, float* %arr, i32 %j2 %p2 = getelementptr inbounds float, float* %arr, i32 %j2
; CHECK: [[b2:%[0-9]+]] = getelementptr float, float* [[b1]], i64 [[bump]] ; CHECK: [[b2:%[0-9]+]] = getelementptr float, float* [[b1]], i64 [[bump]]
; PTX: add.s64 [[base2:%rd[0-9]+]], [[base1]], [[i4]]; ; PTX: add.s64 [[base2:%rd[0-9]+]], [[base1]], [[i4]];
%v2 = load float, float* %p2, align 4 %v2 = load float, float* %p2, align 4
; PTX: ld.f32 {{%f[0-9]+}}, {{\[}}[[base2]]+20]; ; PTX: ld.f32 {{%f[0-9]+}}, [[[base2]]+20];
call void @foo(float %v2) call void @foo(float %v2)
%j3 = add nsw i32 %i3, 5 %j3 = add nsw i32 %i3, 5
%p3 = getelementptr inbounds float, float* %arr, i32 %j3 %p3 = getelementptr inbounds float, float* %arr, i32 %j3
; CHECK: [[b3:%[0-9]+]] = getelementptr float, float* [[b2]], i64 [[bump]] ; CHECK: [[b3:%[0-9]+]] = getelementptr float, float* [[b2]], i64 [[bump]]
; PTX: add.s64 [[base3:%rd[0-9]+]], [[base2]], [[i4]]; ; PTX: add.s64 [[base3:%rd[0-9]+]], [[base2]], [[i4]];
%v3 = load float, float* %p3, align 4 %v3 = load float, float* %p3, align 4
; PTX: ld.f32 {{%f[0-9]+}}, {{\[}}[[base3]]+20]; ; PTX: ld.f32 {{%f[0-9]+}}, [[[base3]]+20];
call void @foo(float %v3) call void @foo(float %v3)
%j4 = add nsw i32 %i4, 5 %j4 = add nsw i32 %i4, 5
%p4 = getelementptr inbounds float, float* %arr, i32 %j4 %p4 = getelementptr inbounds float, float* %arr, i32 %j4
; CHECK: [[b4:%[0-9]+]] = getelementptr float, float* [[b3]], i64 [[bump]] ; CHECK: [[b4:%[0-9]+]] = getelementptr float, float* [[b3]], i64 [[bump]]
; PTX: add.s64 [[base4:%rd[0-9]+]], [[base3]], [[i4]]; ; PTX: add.s64 [[base4:%rd[0-9]+]], [[base3]], [[i4]];
%v4 = load float, float* %p4, align 4 %v4 = load float, float* %p4, align 4
; PTX: ld.f32 {{%f[0-9]+}}, {{\[}}[[base4]]+20]; ; PTX: ld.f32 {{%f[0-9]+}}, [[[base4]]+20];
call void @foo(float %v4) call void @foo(float %v4)
ret void ret void
} }
declare void @foo(float) declare void @foo(float)