[CSInfo][clang][ISEL][RISCV] Support for recovering optimized debug function parameters

[mmatic05]

Summary

This patch enables functionality in clang frontend and adds call site info
generation support for RISCV targets (riscv64, riscv32).

Debug entry values functionality provides debug information about
call sites and function parameters values at the call entry spot.
Condition for generating this type of information is
compiling with -g option and optimization level higher than zero(-O0).

In ISEL phase, while lowering call instructions, collect info about registers
that forward arguments into following function frame.
We store such info into MachineFunction of the caller function.
This is used very late, when dumping DWARF info about call site parameters.

The call site info is visible at MIR level, as callSites attribute of MachineFunction.
To deal with callSites attribute, we should pass -emit-call-site-info option to llc.

When parameter's value is loaded into a register by RISCV instructions
(which are processed by the solution) , it could be described correctly and emitted
as DW_TAG_call_site_parameter.

We can see increased numbers of parameters (DW_TAG_call_site_parameter) as a consequence of the implemented solution:

• clang binary file (compile with "-g -O3")

$ llvm-dwarfdump --statistics clang

...
"call site parameter DIEs": 558
...

• opt binary file (compile with "-g -O3")

$ llvm-dwarfdump --statistics opt

...
"call site parameter DIEs": 1184
...

• llc binary file (compile with "-g -O3")

$ llvm-dwarfdump --statistics llc

...
"call site parameter DIEs": 375
...

[djtodoro]

Thanks for this. Some initial comments inline.

Please apply the suggestions to all tests.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9143

This is an invariant, could we hoist it outside the loop?

llvm/test/CodeGen/RISCV/call-site-info-output_riscv32.ll

39–42 ↗

(On Diff #396280)

not needed

55 ↗

(On Diff #396280)

I think the lifetime intrinsics are not needed for this.

86–90 ↗

(On Diff #396280)

we don't need most of these

96 ↗

(On Diff #396280)

97 ↗

(On Diff #396280)

104 ↗

(On Diff #396280)

137–141 ↗

(On Diff #396280)

all of these could use just one DILocation

[djtodoro]

Can we put all the dbg-call-site-param-* tests in one MIR file?

[mmatic05]

• addressed comments

Thanks for the suggestions!

[jrtc27]

This whole scheme seems like a pretty bad idea, is that really how the debug infrastructure works, scavenging generated code to figure out what arguments were passed rather than just remembering from the input? This all seems pretty fragile. I mean, if that's what we need to do to make it work then I guess we have to, but I really do not like this code...

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1910

Such as?....

1935

Does this need to be a member function? It doesn't seem to access any state from what I can tell, only its inputs.

Also, the name is misleading. isAddImmediate suggests it's checking for RISCV::ADDI (which would be a pointless function), but it in fact does many more things than that.

1943

This naming convention isn't used anywhere else in the backend that I know of

1963

Does this case really matter for this? Why would we ever generate ANDI X0, 0 as the input to a function? Same goes for a whole bunch of these cases, that would be terrible codegen if we generate them.

[djtodoro]

Hi @jrtc27:)

In D116305#3251884, @jrtc27 wrote:

This whole scheme seems like a pretty bad idea, is that really how the debug infrastructure works, scavenging generated code to figure out what arguments were passed rather than just remembering from the input? This all seems pretty fragile. I mean, if that's what we need to do to make it work then I guess we have to, but I really do not like this code...

I am not sure If I understood this, can you please elaborate what exactly is bad idea?

This is all part of the Debug Entry Values feature that improves debugging user experience of optimized code. The feature was divided into two parts: callee and caller. The callee part implements production of DW_OP_entry_value DWARF expressions, which indicates that debugger should jump into parent's frame and look for a value of the parameter that was available at the call-site. The info at call site we call caller side. The caller side generates info about parameter's value. We need an info about what register was used for passing arguments since we need to express the value that was passed in, in terms of DWARF (expression), very late in the pipeline (when doing the AsmPrinter/DwarfDebug). During the ISel phase, the compiler remembers the info into the MF attribute, so it can be used later.

An alternative was to introduce some additional metadata, that would be generated at fronted, but keeping such info (valid) throughout pipeline is very expensive.

[djtodoro]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1915–1916

This comment sounds confusing -- please fix it.

1935

I guess a more appropriate name would be something like isAddImmLike()

1943

+1 to this, please refactor it

llvm/test/DebugInfo/MIR/RISCV/dbg-call-site-param.mir

486–517

I believe we don't need all of these attrs.

[djtodoro]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1935

In addition to this -- please take a look into the X86 implementation of the describeLoadedValue(). I think that some of these instructions here are moveImmLike (since the offset ends up being 0) rather than addImmLike instructions -- so those could/should be moved out of this predicate for sure.

[mmatic05]

• addressed comments

clang/lib/Frontend/CompilerInvocation.cpp

#undef CODEGEN_OPTION_WITH_MARSHALLING
 
   for (const auto &Arg : Args.getAllArgValues(OPT_fcoverage_prefix_map_EQ)) {
     auto Split = StringRef(Arg).split('=');
     Opts.CoveragePrefixMap.insert(
         {std::string(Split.first), std::string(Split.second)});
   }
 
   const llvm::Triple::ArchType DebugEntryValueArchs[] = {
-      llvm::Triple::x86, llvm::Triple::x86_64, llvm::Triple::aarch64,
-      llvm::Triple::arm, llvm::Triple::armeb, llvm::Triple::mips,
-      llvm::Triple::mipsel, llvm::Triple::mips64, llvm::Triple::mips64el};
+      llvm::Triple::x86,     llvm::Triple::x86_64, llvm::Triple::aarch64,
+      llvm::Triple::arm,     llvm::Triple::armeb,  llvm::Triple::mips,
+      llvm::Triple::mipsel,  llvm::Triple::mips64, llvm::Triple::mips64el,
+      llvm::Triple::riscv32, llvm::Triple::riscv64};
 
   if (Opts.OptimizationLevel > 0 && Opts.hasReducedDebugInfo() &&
       llvm::is_contained(DebugEntryValueArchs, T.getArch()))
     Opts.EmitCallSiteInfo = true;
 
   if (!Opts.EnableDIPreservationVerify && Opts.DIBugsReportFilePath.size()) {
     Diags.Report(diag::warn_ignoring_verify_debuginfo_preserve_export)
         << Opts.DIBugsReportFilePath;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
   bool &IsTailCall = CLI.IsTailCall;
   CallingConv::ID CallConv = CLI.CallConv;
   bool IsVarArg = CLI.IsVarArg;
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
   MVT XLenVT = Subtarget.getXLenVT();
 
   MachineFunction &MF = DAG.getMachineFunction();
 
+  // Call site info for function parameters tracking.
+  MachineFunction::CallSiteInfo CSInfo;
+
   // Analyze the operands of the call, assigning locations to each operand.
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
 
   if (CallConv == CallingConv::GHC)
     ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV_GHC);
   else
     analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI,
Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment,
                           /*AlwaysInline=*/false, IsTailCall,
                           MachinePointerInfo(), MachinePointerInfo());
     ByValArgs.push_back(FIPtr);
   }
 
   if (!IsTailCall)
     Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
 
+  const TargetOptions &Options = DAG.getTarget().Options;
+
   // Copy argument values to their designated locations.
   SmallVector<std::pair<Register, SDValue>, 8> RegsToPass;
   SmallVector<SDValue, 8> MemOpChains;
   SDValue StackPtr;
   for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) {
     CCValAssign &VA = ArgLocs[i];
     SDValue ArgValue = OutVals[i];
     ISD::ArgFlagsTy Flags = Outs[i].Flags;
for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) {
 
     // Use local copy if it is a byval arg.
     if (Flags.isByVal())
       ArgValue = ByValArgs[j++];
 
     if (VA.isRegLoc()) {
       // Queue up the argument copies and emit them at the end.
       RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
+
+      if (Options.SupportsDebugEntryValues)
+        CSInfo.emplace_back(VA.getLocReg(), i);
+      continue;
     } else {
       assert(VA.isMemLoc() && "Argument not register or memory");
       assert(!IsTailCall && "Tail call not allowed if stack is used "
                             "for passing parameters");
 
       // Work out the address of the stack slot.
       if (!StackPtr.getNode())
         StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT);
SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
   if (Glue.getNode())
     Ops.push_back(Glue);
 
   // Emit the call.
   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
 
   if (IsTailCall) {
     MF.getFrameInfo().setHasTailCall();
-    return DAG.getNode(RISCVISD::TAIL, DL, NodeTys, Ops);
+    SDValue Ret = DAG.getNode(RISCVISD::TAIL, DL, NodeTys, Ops);
+    DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
+    return Ret;
   }
 
   Chain = DAG.getNode(RISCVISD::CALL, DL, NodeTys, Ops);
   DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
   Glue = Chain.getValue(1);
 
+  DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
+
   // Mark the end of the call, which is glued to the call itself.
   Chain = DAG.getCALLSEQ_END(Chain,
                              DAG.getConstant(NumBytes, DL, PtrVT, true),
                              DAG.getConstant(0, DL, PtrVT, true),
                              Glue, DL);
   Glue = Chain.getValue(1);
 
   // Assign locations to each value returned by this call.

llvm/lib/Target/RISCV/RISCVInstrInfo.h

public:
   // Returns true if the given MI is an RVV instruction opcode for which we may
   // expect to see a FrameIndex operand. When CheckFIs is true, the instruction
   // must contain at least one FrameIndex operand.
   bool isRVVSpill(const MachineInstr &MI, bool CheckFIs) const;
 
   Optional<std::pair<unsigned, unsigned>>
   isRVVSpillForZvlsseg(unsigned Opcode) const;
 
+  Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
+                                                Register Reg) const override;
+
+  static Optional<RegImmPair> addImmLike(const MachineInstr &, Register);
+
+  static uint64_t *moveImmLike(const MachineInstr &, Register);
+
 protected:
   const RISCVSubtarget &STI;
 };
 
 namespace RISCV {
 
 // Implemented in RISCVGenInstrInfo.inc
 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Analysis/MemoryLocation.h"
 #include "llvm/CodeGen/LiveIntervals.h"
 #include "llvm/CodeGen/LiveVariables.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/IR/DebugInfoMetadata.h"
 #include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/ErrorHandling.h"
 
 using namespace llvm;
 
 #define GEN_CHECK_COMPRESS_INSTR
 #include "RISCVGenCompressInstEmitter.inc"
RISCVInstrInfo::isRVVSpillForZvlsseg(unsigned Opcode) const {
   case RISCV::PseudoVSPILL7_M1:
   case RISCV::PseudoVRELOAD7_M1:
     return std::make_pair(7u, 1u);
   case RISCV::PseudoVSPILL8_M1:
   case RISCV::PseudoVRELOAD8_M1:
     return std::make_pair(8u, 1u);
   }
 }
+
+Optional<ParamLoadedValue>
+RISCVInstrInfo::describeLoadedValue(const MachineInstr &MI,
+                                    Register Reg) const {
+  DIExpression *Expr =
+      DIExpression::get(MI.getMF()->getFunction().getContext(), {});
+
+  // TODO: Special RISCV instructions that need to be described separately.
+  if (auto Offset = RISCVInstrInfo::moveImmLike(MI, Reg)) {
+    return ParamLoadedValue(MachineOperand::CreateImm(*Offset), Expr);
+  } else if (auto RegImm = RISCVInstrInfo::addImmLike(MI, Reg)) {
+    Register SrcReg = RegImm->Reg;
+    int64_t Offset = RegImm->Imm;
+
+    Expr = DIExpression::prepend(Expr, DIExpression::ApplyOffset, Offset);
+    return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
+  } else if (auto DestSrc = isCopyInstr(MI)) {
+    const MachineFunction *MF = MI.getMF();
+    const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
+    Register DestReg = DestSrc->Destination->getReg();
+    // TODO: Handle cases where the Reg is sub- or super-register of the
+    // DestReg.
+    if (TRI->isSuperRegister(Reg, DestReg) || TRI->isSubRegister(Reg, DestReg))
+      return None;
+  }
+
+  return TargetInstrInfo::describeLoadedValue(MI, Reg);
+}
+
+Optional<RegImmPair> RISCVInstrInfo::addImmLike(const MachineInstr &MI,
+                                                Register Reg) {
+  if (!MI.getOperand(0).isReg() || Reg != MI.getOperand(0).getReg() ||
+      MI.getNumOperands() < 3)
+    return None;
+
+  const MachineOperand &Op0 = MI.getOperand(0), &Op1 = MI.getOperand(1),
+                       &Op2 = MI.getOperand(2);
+
+  switch (MI.getOpcode()) {
+  case RISCV::ADDI: {
+    if (Op0.isReg() && Op1.isReg() && Op2.isImm())
+      return RegImmPair{Op1.getReg(), Op2.getImm()};
+    break;
+  }
+  case RISCV::ORI:
+  case RISCV::XORI: {
+    if (Op0.isReg() && Op1.isReg() && Op2.isImm()) {
+      if (Op2.getImm() == (uint64_t)0)
+        return RegImmPair{Op1.getReg(), Op2.getImm()};
+    }
+    break;
+  }
+  case RISCV::SLLI:
+  case RISCV::SRLI:
+  case RISCV::SRAI: {
+    if (Op0.isReg() && Op1.isReg() && Op2.isImm()) {
+      if (Op2.getImm() == (uint64_t)0)
+        return RegImmPair{Op1.getReg(), Op2.getImm()};
+    }
+    break;
+  }
+  case RISCV::AND: {
+    if (Op0.isReg() && Op1.isReg() && Op2.isReg()) {
+      if (Op1.getReg() == Op2.getReg())
+        return RegImmPair{Op1.getReg(), (uint64_t)0};
+    }
+    break;
+  }
+  case RISCV::OR: {
+    if (Op0.isReg() && Op1.isReg() && Op2.isReg()) {
+      if (Op1.getReg() == Op2.getReg())
+        return RegImmPair{Op1.getReg(), (uint64_t)0};
+      if (Op1.getReg() == RISCV::X0)
+        return RegImmPair{Op2.getReg(), (uint64_t)0};
+      if (Op2.getReg() == RISCV::X0)
+        return RegImmPair{Op1.getReg(), (uint64_t)0};
+    }
+    break;
+  }
+  case RISCV::XOR: {
+    if (Op0.isReg() && Op1.isReg() && Op2.isReg()) {
+      if (Op1.getReg() == RISCV::X0)
+        return RegImmPair{Op2.getReg(), (uint64_t)0};
+      if (Op2.getReg() == RISCV::X0)
+        return RegImmPair{Op1.getReg(), (uint64_t)0};
+    }
+    break;
+  }
+  case RISCV::ADD: {
+    if (Op0.isReg() && Op1.isReg() && Op2.isReg()) {
+      if (Op1.getReg() == RISCV::X0)
+        return RegImmPair{Op2.getReg(), (uint64_t)0};
+      if (Op2.getReg() == RISCV::X0)
+        return RegImmPair{Op1.getReg(), (uint64_t)0};
+    }
+    break;
+  }
+  case RISCV::SUB: {
+    if (Op0.isReg() && Op1.isReg() && Op2.isReg()) {
+      if (Op2.getReg() == RISCV::X0)
+        return RegImmPair{Op1.getReg(), (uint64_t)0};
+    }
+    break;
+  }
+  case RISCV::SLL:
+  case RISCV::SRL:
+  case RISCV::SRA: {
+    if (Op0.isReg() && Op1.isReg() && Op2.isReg()) {
+      if (Op2.getReg() == RISCV::X0)
+        return RegImmPair{Op1.getReg(), (uint64_t)0};
+    }
+    break;
+  }
+  }
+  return None;
+}
+
+uint64_t moveImmLikeConst = 0;
+
+uint64_t *RISCVInstrInfo::moveImmLike(const MachineInstr &MI, Register Reg) {
+  if (!MI.getOperand(0).isReg() || Reg != MI.getOperand(0).getReg() ||
+      MI.getNumOperands() < 2)
+    return nullptr;
+
+  const MachineOperand &Op0 = MI.getOperand(0), &Op1 = MI.getOperand(1);
+
+  switch (MI.getOpcode()) {
+  case RISCV::ADDI: {
+    const MachineOperand &Op2 = MI.getOperand(2);
+    if (Op0.isReg() && Op1.isReg() && Op2.isImm())
+      if (Op1.getReg() == RISCV::X0) {
+        moveImmLikeConst = Op2.getImm();
+        return &moveImmLikeConst;
+      }
+    break;
+  }
+  case RISCV::LUI: {
+    if (Op0.isReg() && Op1.isImm()) {
+      moveImmLikeConst = Op1.getImm() << 12;
+      return &moveImmLikeConst;
+    }
+    break;
+  }
+  case RISCV::ANDI: {
+    const MachineOperand &Op2 = MI.getOperand(2);
+    if (Op0.isReg() && Op1.isReg() && Op2.isImm())
+      if (Op1.getReg() == RISCV::X0 || Op2.getImm() == (uint64_t)0)
+        return &moveImmLikeConst;
+    break;
+  }
+  case RISCV::ORI:
+  case RISCV::XORI: {
+    const MachineOperand &Op2 = MI.getOperand(2);
+    if (Op0.isReg() && Op1.isReg() && Op2.isImm()) {
+      if (Op1.getReg() == RISCV::X0) {
+        moveImmLikeConst = Op2.getImm();
+        return &moveImmLikeConst;
+      }
+    }
+    break;
+  }
+  case RISCV::SLLI:
+  case RISCV::SRLI:
+  case RISCV::SRAI: {
+    const MachineOperand &Op2 = MI.getOperand(2);
+    if (Op0.isReg() && Op1.isReg() && Op2.isImm()) {
+      if (Op1.getReg() == RISCV::X0)
+        return &moveImmLikeConst;
+    }
+    break;
+  }
+  case RISCV::AND: {
+    const MachineOperand &Op2 = MI.getOperand(2);
+    if (Op0.isReg() && Op1.isReg() && Op2.isReg()) {
+      if (Op1.getReg() == RISCV::X0 || Op2.getReg() == RISCV::X0)
+        return &moveImmLikeConst;
+    }
+    break;
+  }
+  case RISCV::XOR: {
+    const MachineOperand &Op2 = MI.getOperand(2);
+    if (Op0.isReg() && Op1.isReg() && Op2.isReg()) {
+      if (Op1.getReg() == Op2.getReg())
+        return &moveImmLikeConst;
+    }
+    break;
+  }
+  case RISCV::ADD: {
+    const MachineOperand &Op2 = MI.getOperand(2);
+    if (Op0.isReg() && Op1.isReg() && Op2.isReg()) {
+      if (Op1.getReg() == RISCV::X0 && Op2.getReg() == RISCV::X0)
+        return &moveImmLikeConst;
+    }
+    break;
+  }
+  case RISCV::SUB: {
+    const MachineOperand &Op2 = MI.getOperand(2);
+    if (Op0.isReg() && Op1.isReg() && Op2.isReg()) {
+      if (Op1.getReg() == Op2.getReg())
+        return &moveImmLikeConst;
+    }
+    break;
+  }
+  case RISCV::SLL:
+  case RISCV::SRL:
+  case RISCV::SRA: {
+    const MachineOperand &Op2 = MI.getOperand(2);
+    if (Op0.isReg() && Op1.isReg() && Op2.isReg()) {
+      if (Op1.getReg() == RISCV::X0)
+        return &moveImmLikeConst;
+    }
+    break;
+  }
+  }
+  return nullptr;
+}

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
                         getEffectiveRelocModel(TT, RM),
                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
       TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
   initAsmInfo();
 
   // RISC-V supports the MachineOutliner.
   setMachineOutliner(true);
+
+  // RISC-V supports the debug entry values.
+  setSupportsDebugEntryValues(true);
 }
 
 const RISCVSubtarget *
 RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");
 

llvm/test/CodeGen/RISCV/call-site-info-output.ll

+;; Test riscv32:
+; RUN: llc -mtriple=riscv32 -emit-call-site-info -stop-before=finalize-isel %s -o - | \
+; RUN: llc -mtriple=riscv32 -emit-call-site-info -x='mir' -run-pass=finalize-isel -o -| FileCheck %s
+
+;; Test riscv64:
+; RUN: llc -mtriple=riscv64 -emit-call-site-info -stop-before=finalize-isel %s -o - | \
+; RUN: llc -mtriple=riscv64 -emit-call-site-info -x='mir' -run-pass=finalize-isel -o -| FileCheck %s --check-prefix=CHECK64
+
+
+
+;; Source:
+;; extern void addi_instr (long int, long int, long int);
+;; extern void add_instr (long int, long int, long int);
+;; extern void andi_instr (long int, long int, long int);
+;; extern void and_instr (long int, long int, long int);
+;; extern void lui_instr (long int, long int, long int);
+;; extern void or_instr (long int, long int, long int);
+;; extern void ori_xori_instr (long int, long int, long int);
+;; extern void slli_srli_srai_instr (long int, long int, long int);
+;; extern void sll_srl_sra_instr (long int, long int, long int);
+;; extern void sub_instr (long int, long int, long int);
+;; extern void xor_instr (long int, long int, long int);
+;; long int fn2 (long int a, long int b, long int c) 
+;; {
+;;  long int q = 2 * a;
+;;  addi_instr (1,2,3); 
+;;  add_instr (4,5,6); 
+;;  andi_instr (7,8,9); 
+;;  and_instr (10,11,12); 
+;;  lui_instr (13,14,15); 
+;;  or_instr (16,17,18); 
+;;  ori_xori_instr (19,20,21); 
+;;  slli_srli_srai_instr (22,23,24); 
+;;  sll_srl_sra_instr (25,26,27); 
+;;  sub_instr (28,29,30); 
+;;  xor_instr (31,32,33); 
+;;  return 0;
+;; }
+ 
+;; Test riscv32:
+; CHECK: name: fn2
+; CHECK: callSites:
+; CHECK-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK-NEXT:   arg: 0, reg: '$x10'
+; CHECK-NEXT:   arg: 1, reg: '$x11'
+; CHECK-NEXT:   arg: 2, reg: '$x12'
+; CHECK-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK-NEXT:   arg: 0, reg: '$x10'
+; CHECK-NEXT:   arg: 1, reg: '$x11'
+; CHECK-NEXT:   arg: 2, reg: '$x12'
+; CHECK-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK-NEXT:   arg: 0, reg: '$x10'
+; CHECK-NEXT:   arg: 1, reg: '$x11'
+; CHECK-NEXT:   arg: 2, reg: '$x12'
+; CHECK-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK-NEXT:   arg: 0, reg: '$x10'
+; CHECK-NEXT:   arg: 1, reg: '$x11'
+; CHECK-NEXT:   arg: 2, reg: '$x12'
+; CHECK-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK-NEXT:   arg: 0, reg: '$x10'
+; CHECK-NEXT:   arg: 1, reg: '$x11'
+; CHECK-NEXT:   arg: 2, reg: '$x12'
+; CHECK-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK-NEXT:   arg: 0, reg: '$x10'
+; CHECK-NEXT:   arg: 1, reg: '$x11'
+; CHECK-NEXT:   arg: 2, reg: '$x12'
+; CHECK-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK-NEXT:   arg: 0, reg: '$x10'
+; CHECK-NEXT:   arg: 1, reg: '$x11'
+; CHECK-NEXT:   arg: 2, reg: '$x12'
+; CHECK-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK-NEXT:   arg: 0, reg: '$x10'
+; CHECK-NEXT:   arg: 1, reg: '$x11'
+; CHECK-NEXT:   arg: 2, reg: '$x12'
+; CHECK-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK-NEXT:   arg: 0, reg: '$x10'
+; CHECK-NEXT:   arg: 1, reg: '$x11'
+; CHECK-NEXT:   arg: 2, reg: '$x12'
+; CHECK-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK-NEXT:   arg: 0, reg: '$x10'
+; CHECK-NEXT:   arg: 1, reg: '$x11'
+; CHECK-NEXT:   arg: 2, reg: '$x12'
+; CHECK-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK-NEXT:   arg: 0, reg: '$x10'
+; CHECK-NEXT:   arg: 1, reg: '$x11'
+; CHECK-NEXT:   arg: 2, reg: '$x12'
+
+;; Test riscv64:
+; CHECK64: name: fn2
+; CHECK64: callSites:
+; CHECK64-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK64-NEXT:   arg: 0, reg: '$x10'
+; CHECK64-NEXT:   arg: 1, reg: '$x11'
+; CHECK64-NEXT:   arg: 2, reg: '$x12'
+; CHECK64-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK64-NEXT:   arg: 0, reg: '$x10'
+; CHECK64-NEXT:   arg: 1, reg: '$x11'
+; CHECK64-NEXT:   arg: 2, reg: '$x12'
+; CHECK64-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK64-NEXT:   arg: 0, reg: '$x10'
+; CHECK64-NEXT:   arg: 1, reg: '$x11'
+; CHECK64-NEXT:   arg: 2, reg: '$x12'
+; CHECK64-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK64-NEXT:   arg: 0, reg: '$x10'
+; CHECK64-NEXT:   arg: 1, reg: '$x11'
+; CHECK64-NEXT:   arg: 2, reg: '$x12'
+; CHECK64-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK64-NEXT:   arg: 0, reg: '$x10'
+; CHECK64-NEXT:   arg: 1, reg: '$x11'
+; CHECK64-NEXT:   arg: 2, reg: '$x12'
+; CHECK64-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK64-NEXT:   arg: 0, reg: '$x10'
+; CHECK64-NEXT:   arg: 1, reg: '$x11'
+; CHECK64-NEXT:   arg: 2, reg: '$x12'
+; CHECK64-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK64-NEXT:   arg: 0, reg: '$x10'
+; CHECK64-NEXT:   arg: 1, reg: '$x11'
+; CHECK64-NEXT:   arg: 2, reg: '$x12'
+; CHECK64-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK64-NEXT:   arg: 0, reg: '$x10'
+; CHECK64-NEXT:   arg: 1, reg: '$x11'
+; CHECK64-NEXT:   arg: 2, reg: '$x12'
+; CHECK64-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK64-NEXT:   arg: 0, reg: '$x10'
+; CHECK64-NEXT:   arg: 1, reg: '$x11'
+; CHECK64-NEXT:   arg: 2, reg: '$x12'
+; CHECK64-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK64-NEXT:   arg: 0, reg: '$x10'
+; CHECK64-NEXT:   arg: 1, reg: '$x11'
+; CHECK64-NEXT:   arg: 2, reg: '$x12'
+; CHECK64-NEXT: bb: {{.*}}, offset: {{.*}}, fwdArgRegs:
+; CHECK64-NEXT:   arg: 0, reg: '$x10'
+; CHECK64-NEXT:   arg: 1, reg: '$x11'
+; CHECK64-NEXT:   arg: 2, reg: '$x12'
+
+
+; Function Attrs: nounwind
+define dso_local i32 @fn2(i32 %a, i32 %b, i32 %c) local_unnamed_addr #0 !dbg !8 {
+entry:
+  call void @llvm.dbg.value(metadata i32 %a, metadata !13, metadata !DIExpression()), !dbg !17
+  call void @llvm.dbg.value(metadata i32 %b, metadata !14, metadata !DIExpression()), !dbg !17
+  call void @llvm.dbg.value(metadata i32 %c, metadata !15, metadata !DIExpression()), !dbg !17
+  call void @llvm.dbg.value(metadata !DIArgList(i32 2, i32 %a), metadata !16, metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_mul, DW_OP_stack_value)), !dbg !17
+  tail call void @addi_instr(i32 1, i32 2, i32 3) #3, !dbg !17
+  tail call void @add_instr(i32 4, i32 5, i32 6) #3, !dbg !17
+  tail call void @andi_instr(i32 7, i32 8, i32 9) #3, !dbg !17
+  tail call void @and_instr(i32 10, i32 11, i32 12) #3, !dbg !17
+  tail call void @lui_instr(i32 13, i32 14, i32 15) #3, !dbg !17
+  tail call void @or_instr(i32 16, i32 17, i32 18) #3, !dbg !17
+  tail call void @ori_xori_instr(i32 19, i32 20, i32 21) #3, !dbg !17
+  tail call void @slli_srli_srai_instr(i32 22, i32 23, i32 24) #3, !dbg !17
+  tail call void @sll_srl_sra_instr(i32 25, i32 26, i32 27) #3, !dbg !17
+  tail call void @sub_instr(i32 28, i32 29, i32 30) #3, !dbg !17
+  tail call void @xor_instr(i32 31, i32 32, i32 33) #3, !dbg !17
+  ret i32 0, !dbg !17
+}
+
+declare !dbg !30 dso_local void @addi_instr(i32, i32, i32) local_unnamed_addr #1
+
+declare !dbg !34 dso_local void @add_instr(i32, i32, i32) local_unnamed_addr #1
+
+declare !dbg !35 dso_local void @andi_instr(i32, i32, i32) local_unnamed_addr #1
+
+declare !dbg !36 dso_local void @and_instr(i32, i32, i32) local_unnamed_addr #1
+
+declare !dbg !37 dso_local void @lui_instr(i32, i32, i32) local_unnamed_addr #1
+
+declare !dbg !38 dso_local void @or_instr(i32, i32, i32) local_unnamed_addr #1
+
+declare !dbg !39 dso_local void @ori_xori_instr(i32, i32, i32) local_unnamed_addr #1
+
+declare !dbg !40 dso_local void @slli_srli_srai_instr(i32, i32, i32) local_unnamed_addr #1
+
+declare !dbg !41 dso_local void @sll_srl_sra_instr(i32, i32, i32) local_unnamed_addr #1
+
+declare !dbg !42 dso_local void @sub_instr(i32, i32, i32) local_unnamed_addr #1
+
+declare !dbg !43 dso_local void @xor_instr(i32, i32, i32) local_unnamed_addr #1
+
+; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
+declare void @llvm.dbg.value(metadata, metadata, metadata) #2
+
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 14.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None)
+!1 = !DIFile(filename: "test.c", directory: "/")
+!2 = !{i32 7, !"Dwarf Version", i32 4}
+!3 = !{i32 2, !"Debug Info Version", i32 3}
+!4 = !{i32 1, !"wchar_size", i32 4}
+!5 = !{i32 1, !"target-abi", !"ilp32d"}
+!6 = !{i32 1, !"SmallDataLimit", i32 8}
+!7 = !{!"clang version 14.0.0"}
+!8 = distinct !DISubprogram(name: "fn2", scope: !1, file: !1, line: 14, type: !9, scopeLine: 15, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !12)
+!9 = !DISubroutineType(types: !10)
+!10 = !{!11, !11, !11, !11}
+!11 = !DIBasicType(name: "long", size: 32, encoding: DW_ATE_signed)
+!12 = !{!13, !14, !15, !16}
+!13 = !DILocalVariable(name: "a", arg: 1, scope: !8, file: !1, line: 14, type: !11)
+!14 = !DILocalVariable(name: "b", arg: 2, scope: !8, file: !1, line: 14, type: !11)
+!15 = !DILocalVariable(name: "c", arg: 3, scope: !8, file: !1, line: 14, type: !11)
+!16 = !DILocalVariable(name: "q", scope: !8, file: !1, line: 16, type: !11)
+!17 = !DILocation(line: 0, scope: !8)
+!30 = !DISubprogram(name: "addi_instr", scope: !1, file: !1, line: 1, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+!31 = !DISubroutineType(types: !32)
+!32 = !{null, !11, !11, !11}
+!33 = !{}
+!34 = !DISubprogram(name: "add_instr", scope: !1, file: !1, line: 2, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+!35 = !DISubprogram(name: "andi_instr", scope: !1, file: !1, line: 3, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+!36 = !DISubprogram(name: "and_instr", scope: !1, file: !1, line: 4, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+!37 = !DISubprogram(name: "lui_instr", scope: !1, file: !1, line: 5, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+!38 = !DISubprogram(name: "or_instr", scope: !1, file: !1, line: 6, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+!39 = !DISubprogram(name: "ori_xori_instr", scope: !1, file: !1, line: 7, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+!40 = !DISubprogram(name: "slli_srli_srai_instr", scope: !1, file: !1, line: 8, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+!41 = !DISubprogram(name: "sll_srl_sra_instr", scope: !1, file: !1, line: 9, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+!42 = !DISubprogram(name: "sub_instr", scope: !1, file: !1, line: 10, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+!43 = !DISubprogram(name: "xor_instr", scope: !1, file: !1, line: 11, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)

llvm/test/DebugInfo/MIR/RISCV/dbg-call-site-param.mir

+## Test riscv32:
+# RUN: llc -mtriple=riscv32 -emit-call-site-info -start-after=machineverifier -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s
+
+## Test riscv64:
+# RUN: llc -mtriple=riscv64 -emit-call-site-info -start-after=machineverifier -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s --check-prefix=CHECK64
+
+## Following code is used for producing this test case.
+## Hardcoding for MIR level testing (for instructions other than ADDI instructions) 
+##
+## extern void addi_instr (long int, long int, long int);
+## extern void add_instr (long int, long int, long int);
+## extern void andi_instr (long int, long int, long int);
+## extern void and_instr (long int, long int, long int);
+## extern void lui_instr (long int, long int, long int);
+## extern void or_instr (long int, long int, long int);
+## extern void ori_xori_instr (long int, long int, long int);
+## extern void slli_srli_srai_instr (long int, long int, long int);
+## extern void sll_srl_sra_instr (long int, long int, long int);
+## extern void sub_instr (long int, long int, long int);
+## extern void xor_instr (long int, long int, long int);
+## long int fn2 (long int a, long int b, long int c) 
+## {
+##  long int q = 2 * a;
+##  addi_instr (1,2,3); 
+##  add_instr (4,5,6); 
+##  andi_instr (7,8,9); 
+##  and_instr (10,11,12); 
+##  lui_instr (13,14,15); 
+##  or_instr (16,17,18); 
+##  ori_xori_instr (19,20,21); 
+##  slli_srli_srai_instr (22,23,24); 
+##  sll_srl_sra_instr (25,26,27); 
+##  sub_instr (28,29,30); 
+##  xor_instr (31,32,33); 
+##  return 0;
+## }
+
+
+## Test riscv32:
+
+# CHECK: DW_TAG_GNU_call_site
+# CHECK-NEXT:  DW_AT_abstract_origin  ({{.*}} "addi_instr")
+# CHECK-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit3)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_lit2)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit1)
+
+# CHECK: DW_TAG_GNU_call_site
+# CHECK-NEXT:  DW_AT_abstract_origin  ({{.*}} "add_instr")
+# CHECK-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_lit1)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+
+# CHECK: DW_TAG_GNU_call_site
+# CHECK-NEXT:  DW_AT_abstract_origin  ({{.*}} "andi_instr")
+# CHECK-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit1)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_lit1)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit1)
+
+# CHECK: DW_TAG_GNU_call_site
+# CHECK-NEXT:  DW_AT_abstract_origin  ({{.*}} "and_instr")
+# CHECK-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit1)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_fbreg +0)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit1)
+
+# CHECK: DW_TAG_GNU_call_site
+# CHECK-NEXT:  DW_AT_abstract_origin  ({{.*}} "lui_instr")
+# CHECK-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_constu 0x7000)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_constu 0x6000)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_constu 0x5000)
+
+# CHECK: DW_TAG_GNU_call_site
+# CHECK-NEXT:  DW_AT_abstract_origin  ({{.*}} "or_instr")
+# CHECK-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_fbreg +0)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+
+# CHECK: DW_TAG_GNU_call_site
+# CHECK-NEXT:  DW_AT_abstract_origin  ({{.*}} "ori_xori_instr")
+# CHECK-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit7)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_fbreg +0)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit5)
+
+# CHECK: DW_TAG_GNU_call_site
+# CHECK-NEXT:  DW_AT_abstract_origin  ({{.*}} "slli_srli_srai_instr")
+# CHECK-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit5)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_lit5)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+
+# CHECK: DW_TAG_GNU_call_site
+# CHECK-NEXT:  DW_AT_abstract_origin  ({{.*}} "sll_srl_sra_instr")
+# CHECK-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit5)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_lit5)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+
+# CHECK: DW_TAG_GNU_call_site
+# CHECK-NEXT:  DW_AT_abstract_origin  ({{.*}} "sub_instr")
+# CHECK-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit5)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_lit5)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+
+# CHECK: DW_TAG_GNU_call_site
+# CHECK-NEXT:  DW_AT_abstract_origin  ({{.*}} "xor_instr")
+# CHECK-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_lit5)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+
+## Test riscv64:
+
+# CHECK64: DW_TAG_GNU_call_site
+# CHECK64-NEXT:  DW_AT_abstract_origin  ({{.*}} "addi_instr")
+# CHECK64-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit3)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK64-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_lit2)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit1)
+
+# CHECK64: DW_TAG_GNU_call_site
+# CHECK64-NEXT:  DW_AT_abstract_origin  ({{.*}} "add_instr")
+# CHECK64-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK64-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_lit1)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+
+# CHECK64: DW_TAG_GNU_call_site
+# CHECK64-NEXT:  DW_AT_abstract_origin  ({{.*}} "andi_instr")
+# CHECK64-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit1)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK64-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_lit1)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit1)
+
+# CHECK64: DW_TAG_GNU_call_site
+# CHECK64-NEXT:  DW_AT_abstract_origin  ({{.*}} "and_instr")
+# CHECK64-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit1)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK64-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_fbreg +0)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit1)
+
+# CHECK64: DW_TAG_GNU_call_site
+# CHECK64-NEXT:  DW_AT_abstract_origin  ({{.*}} "lui_instr")
+# CHECK64-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_constu 0x7000)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK64-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_constu 0x6000)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_constu 0x5000)
+
+# CHECK64: DW_TAG_GNU_call_site
+# CHECK64-NEXT:  DW_AT_abstract_origin  ({{.*}} "or_instr")
+# CHECK64-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK64-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_fbreg +0)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+
+# CHECK64: DW_TAG_GNU_call_site
+# CHECK64-NEXT:  DW_AT_abstract_origin  ({{.*}} "ori_xori_instr")
+# CHECK64-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit7)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK64-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_fbreg +0)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit5)
+
+# CHECK64: DW_TAG_GNU_call_site
+# CHECK64-NEXT:  DW_AT_abstract_origin  ({{.*}} "slli_srli_srai_instr")
+# CHECK64-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit5)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK64-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_lit5)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+
+# CHECK64: DW_TAG_GNU_call_site
+# CHECK64-NEXT:  DW_AT_abstract_origin  ({{.*}} "sll_srl_sra_instr")
+# CHECK64-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit5)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK64-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_lit5)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+
+# CHECK64: DW_TAG_GNU_call_site
+# CHECK64-NEXT:  DW_AT_abstract_origin  ({{.*}} "sub_instr")
+# CHECK64-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_lit5)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK64-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_lit5)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+
+# CHECK64: DW_TAG_GNU_call_site
+# CHECK64-NEXT:  DW_AT_abstract_origin  ({{.*}} "xor_instr")
+# CHECK64-NEXT:  DW_AT_low_pc ({{.*}})
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg12 X12)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg11 X11)
+# CHECK64-NEXT:    DW_AT_GNU_call_site_value  (DW_OP_lit5)
+# CHECK64-EMPTY: 
+# CHECK64-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64-NEXT:   DW_AT_location  (DW_OP_reg10 X10)
+# CHECK64-NEXT:   DW_AT_GNU_call_site_value (DW_OP_fbreg +0)
+
+--- |
+
+  ; Function Attrs: nounwind
+  define dso_local i32 @fn2(i32 %a, i32 %b, i32 %c) local_unnamed_addr #0 !dbg !8 {
+  entry:
+    call void @llvm.dbg.value(metadata i32 %a, metadata !13, metadata !DIExpression()), !dbg !17
+    call void @llvm.dbg.value(metadata i32 %b, metadata !14, metadata !DIExpression()), !dbg !17
+    call void @llvm.dbg.value(metadata i32 %c, metadata !15, metadata !DIExpression()), !dbg !17
+    call void @llvm.dbg.value(metadata !DIArgList(i32 2, i32 %a), metadata !16, metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_mul, DW_OP_stack_value)), !dbg !17
+    tail call void @addi_instr(i32 1, i32 2, i32 3) #3, !dbg !17
+    tail call void @add_instr(i32 4, i32 5, i32 6) #3, !dbg !17
+    tail call void @andi_instr(i32 7, i32 8, i32 9) #3, !dbg !17
+    tail call void @and_instr(i32 10, i32 11, i32 12) #3, !dbg !17
+    tail call void @lui_instr(i32 13, i32 14, i32 15) #3, !dbg !17
+    tail call void @or_instr(i32 16, i32 17, i32 18) #3, !dbg !17
+    tail call void @ori_xori_instr(i32 19, i32 20, i32 21) #3, !dbg !17
+    tail call void @slli_srli_srai_instr(i32 22, i32 23, i32 24) #3, !dbg !17
+    tail call void @sll_srl_sra_instr(i32 25, i32 26, i32 27) #3, !dbg !17
+    tail call void @sub_instr(i32 28, i32 29, i32 30) #3, !dbg !17
+    tail call void @xor_instr(i32 31, i32 32, i32 33) #3, !dbg !17
+    ret i32 0, !dbg !17
+  }
+  
+  declare !dbg !30 dso_local void @addi_instr(i32, i32, i32) local_unnamed_addr #1
+  
+  declare !dbg !34 dso_local void @add_instr(i32, i32, i32) local_unnamed_addr #1
+  
+  declare !dbg !35 dso_local void @andi_instr(i32, i32, i32) local_unnamed_addr #1
+  
+  declare !dbg !36 dso_local void @and_instr(i32, i32, i32) local_unnamed_addr #1
+  
+  declare !dbg !37 dso_local void @lui_instr(i32, i32, i32) local_unnamed_addr #1
+  
+  declare !dbg !38 dso_local void @or_instr(i32, i32, i32) local_unnamed_addr #1
+  
+  declare !dbg !39 dso_local void @ori_xori_instr(i32, i32, i32) local_unnamed_addr #1
+  
+  declare !dbg !40 dso_local void @slli_srli_srai_instr(i32, i32, i32) local_unnamed_addr #1
+  
+  declare !dbg !41 dso_local void @sll_srl_sra_instr(i32, i32, i32) local_unnamed_addr #1
+  
+  declare !dbg !42 dso_local void @sub_instr(i32, i32, i32) local_unnamed_addr #1
+  
+  declare !dbg !43 dso_local void @xor_instr(i32, i32, i32) local_unnamed_addr #1
+  
+  ; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
+  declare void @llvm.dbg.value(metadata, metadata, metadata) #2
+  
+  !llvm.dbg.cu = !{!0}
+  !llvm.module.flags = !{!2, !3, !4, !5, !6}
+  !llvm.ident = !{!7}
+  
+  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 14.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None)
+  !1 = !DIFile(filename: "test.c", directory: "/")
+  !2 = !{i32 7, !"Dwarf Version", i32 4}
+  !3 = !{i32 2, !"Debug Info Version", i32 3}
+  !4 = !{i32 1, !"wchar_size", i32 4}
+  !5 = !{i32 1, !"target-abi", !"ilp32d"}
+  !6 = !{i32 1, !"SmallDataLimit", i32 8}
+  !7 = !{!"clang version 14.0.0"}
+  !8 = distinct !DISubprogram(name: "fn2", scope: !1, file: !1, line: 14, type: !9, scopeLine: 15, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !12)
+  !9 = !DISubroutineType(types: !10)
+  !10 = !{!11, !11, !11, !11}
+  !11 = !DIBasicType(name: "long", size: 32, encoding: DW_ATE_signed)
+  !12 = !{!13, !14, !15, !16}
+  !13 = !DILocalVariable(name: "a", arg: 1, scope: !8, file: !1, line: 14, type: !11)
+  !14 = !DILocalVariable(name: "b", arg: 2, scope: !8, file: !1, line: 14, type: !11)
+  !15 = !DILocalVariable(name: "c", arg: 3, scope: !8, file: !1, line: 14, type: !11)
+  !16 = !DILocalVariable(name: "q", scope: !8, file: !1, line: 16, type: !11)
+  !17 = !DILocation(line: 0, scope: !8)
+  !30 = !DISubprogram(name: "addi_instr", scope: !1, file: !1, line: 1, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+  !31 = !DISubroutineType(types: !32)
+  !32 = !{null, !11, !11, !11}
+  !33 = !{}
+  !34 = !DISubprogram(name: "add_instr", scope: !1, file: !1, line: 2, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+  !35 = !DISubprogram(name: "andi_instr", scope: !1, file: !1, line: 3, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+  !36 = !DISubprogram(name: "and_instr", scope: !1, file: !1, line: 4, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+  !37 = !DISubprogram(name: "lui_instr", scope: !1, file: !1, line: 5, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+  !38 = !DISubprogram(name: "or_instr", scope: !1, file: !1, line: 6, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+  !39 = !DISubprogram(name: "ori_xori_instr", scope: !1, file: !1, line: 7, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+  !40 = !DISubprogram(name: "slli_srli_srai_instr", scope: !1, file: !1, line: 8, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+  !41 = !DISubprogram(name: "sll_srl_sra_instr", scope: !1, file: !1, line: 9, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+  !42 = !DISubprogram(name: "sub_instr", scope: !1, file: !1, line: 10, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+  !43 = !DISubprogram(name: "xor_instr", scope: !1, file: !1, line: 11, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !33)
+
+...
+---
+name:            fn2
+alignment:       2
+liveins:         []
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 
+      stack-id: default, callee-saved-register: '$x1', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites:
+  - { bb: 0, offset: 14, fwdArgRegs: 
+      - { arg: 0, reg: '$x10' }
+      - { arg: 1, reg: '$x11' }
+      - { arg: 2, reg: '$x12' } }
+  - { bb: 0, offset: 18, fwdArgRegs: 
+      - { arg: 0, reg: '$x10' }
+      - { arg: 1, reg: '$x11' }
+      - { arg: 2, reg: '$x12' } }
+  - { bb: 0, offset: 22, fwdArgRegs: 
+      - { arg: 0, reg: '$x10' }
+      - { arg: 1, reg: '$x11' }
+      - { arg: 2, reg: '$x12' } }
+  - { bb: 0, offset: 26, fwdArgRegs: 
+      - { arg: 0, reg: '$x10' }
+      - { arg: 1, reg: '$x11' }
+      - { arg: 2, reg: '$x12' } }
+  - { bb: 0, offset: 30, fwdArgRegs: 
+      - { arg: 0, reg: '$x10' }
+      - { arg: 1, reg: '$x11' }
+      - { arg: 2, reg: '$x12' } }
+  - { bb: 0, offset: 34, fwdArgRegs: 
+      - { arg: 0, reg: '$x10' }
+      - { arg: 1, reg: '$x11' }
+      - { arg: 2, reg: '$x12' } }
+  - { bb: 0, offset: 38, fwdArgRegs: 
+      - { arg: 0, reg: '$x10' }
+      - { arg: 1, reg: '$x11' }
+      - { arg: 2, reg: '$x12' } }
+  - { bb: 0, offset: 42, fwdArgRegs: 
+      - { arg: 0, reg: '$x10' }
+      - { arg: 1, reg: '$x11' }
+      - { arg: 2, reg: '$x12' } }
+  - { bb: 0, offset: 46, fwdArgRegs: 
+      - { arg: 0, reg: '$x10' }
+      - { arg: 1, reg: '$x11' }
+      - { arg: 2, reg: '$x12' } }
+  - { bb: 0, offset: 50, fwdArgRegs: 
+      - { arg: 0, reg: '$x10' }
+      - { arg: 1, reg: '$x11' }
+      - { arg: 2, reg: '$x12' } }
+  - { bb: 0, offset: 54, fwdArgRegs: 
+      - { arg: 0, reg: '$x10' }
+      - { arg: 1, reg: '$x11' }
+      - { arg: 2, reg: '$x12' } }
+body:             |
+  bb.0.entry:
+    liveins: $x1
+  
+    DBG_VALUE $x10, $noreg, !13, !DIExpression(), debug-location !17
+    DBG_VALUE $x11, $noreg, !14, !DIExpression(), debug-location !17
+    DBG_VALUE $x12, $noreg, !15, !DIExpression(), debug-location !17
+    $x2 = frame-setup ADDI $x2, -16
+    frame-setup CFI_INSTRUCTION def_cfa_offset 16
+    SW killed $x1, $x2, 12, debug-location !17 :: (store (s32) into %stack.0)
+    frame-setup CFI_INSTRUCTION offset $x1, -4
+    DBG_VALUE $noreg, $noreg, !16, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_mul, DW_OP_stack_value), debug-location !17
+    $x10 = ADDI $x0, 1, debug-location !17
+    DBG_VALUE $x10, $noreg, !13, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !17
+    $x11 = ADDI $x0, 2, debug-location !17
+    DBG_VALUE $x11, $noreg, !14, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !17
+    $x12 = ADDI $x0, 3, debug-location !17
+    DBG_VALUE $x12, $noreg, !15, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !17
+    PseudoCALL target-flags(riscv-call) @addi_instr, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit killed $x11, implicit killed $x12, implicit-def $x2, debug-location !17
+    $x10 = ADD $x2, $x0, debug-location !17
+    $x11 = ADD $x0, $x0, debug-location !17
+    $x12 = ADD $x0, $x2, debug-location !17
+    PseudoCALL target-flags(riscv-call) @add_instr, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit killed $x11, implicit killed $x12, implicit-def $x2, debug-location !17
+    $x10 = ANDI $x0, 5, debug-location !17
+    $x11 = ANDI $x0, 6, debug-location !17
+    $x12 = ANDI $x2, 0, debug-location !17
+    PseudoCALL target-flags(riscv-call) @andi_instr, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit killed $x11, implicit killed $x12, implicit-def $x2, debug-location !17
+    $x10 = AND $x2, $x0, debug-location !17
+    $x11 = AND $x2, $x2, debug-location !17
+    $x12 = AND $x0, $x2, debug-location !17
+    PseudoCALL target-flags(riscv-call) @and_instr, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit killed $x11, implicit killed $x12, implicit-def $x2, debug-location !17
+    $x10 = LUI 5, debug-location !17
+    $x11 = LUI 6, debug-location !17
+    $x12 = LUI 7, debug-location !17
+    PseudoCALL target-flags(riscv-call) @lui_instr, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit killed $x11, implicit killed $x12, implicit-def $x2, debug-location !17
+    $x10 = OR $x2, $x0, debug-location !17
+    $x11 = OR $x2, $x2, debug-location !17
+    $x12 = OR $x0, $x2, debug-location !17
+    PseudoCALL target-flags(riscv-call) @or_instr, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit killed $x11, implicit killed $x12, implicit-def $x2, debug-location !17
+    $x10 = ORI $x0, 5, debug-location !17
+    $x11 = ORI $x2, 0, debug-location !17
+    $x12 = XORI $x0, 7, debug-location !17
+    PseudoCALL target-flags(riscv-call) @ori_xori_instr, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit killed $x11, implicit killed $x12, implicit-def $x2, debug-location !17
+    $x10 = SLLI $x2, 0, debug-location !17
+    $x11 = SRAI $x0, 6, debug-location !17
+    $x12 = SRLI $x0, 7, debug-location !17
+    PseudoCALL target-flags(riscv-call) @slli_srli_srai_instr, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit killed $x11, implicit killed $x12, implicit-def $x2, debug-location !17
+    $x10 = SLL $x2, $x0, debug-location !17
+    $x11 = SRL $x0, $x2, debug-location !17
+    $x12 = SRA $x0, $x2, debug-location !17
+    PseudoCALL target-flags(riscv-call) @sll_srl_sra_instr, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit killed $x11, implicit killed $x12, implicit-def $x2, debug-location !17
+    $x10 = SUB $x2, $x0, debug-location !17
+    $x11 = SUB $x2, $x2, debug-location !17
+    $x12 = SUB $x2, $x2, debug-location !17
+    PseudoCALL target-flags(riscv-call) @sub_instr, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit killed $x11, implicit killed $x12, implicit-def $x2, debug-location !17
+    $x10 = XOR $x2, $x0, debug-location !17
+    $x11 = XOR $x2, $x2, debug-location !17
+    $x12 = XOR $x0, $x2, debug-location !17
+    PseudoCALL target-flags(riscv-call) @xor_instr, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit killed $x11, implicit killed $x12, implicit-def $x2, debug-location !17
+    $x10 = ADDI $x0, 0, debug-location !17
+    $x1 = LW $x2, 12, debug-location !17 :: (load (s32) from %stack.0)
+    $x2 = frame-destroy ADDI $x2, 16, debug-location !17
+    PseudoRET implicit killed $x10, debug-location !17
+
+...