[RISCV] Fix non-sensical intrinsic names in rv64i-single-softfloat.ll. NFC

[craig.topper]

Summary

Many of these had an extra 'f' at the beginning of their name that
caused them to not be treated as intrinsics.

I'm not sure what fpround was supposed to be so I deleted it.

frem was changed from an intrinsic too an instruction.

[jrtc27]

Looks like they've been broken the whole time; see D65497. Also no clue what fpround is meant to be, all seven (floor, ceil, trunc, rint, nearbyint, round, roundeven) of the rounding intrinsics are already tested (modulo the typos).

[craig.topper]

In D113528#3120193, @jrtc27 wrote:

Looks like they've been broken the whole time; see D65497. Also no clue what fpround is meant to be, all seven (floor, ceil, trunc, rint, nearbyint, round, roundeven) of the rounding intrinsics are already tested (modulo the typos).

This is the only place these are tested with softfloat isn't it?

[jrtc27]

In D113528#3120203, @craig.topper wrote:

In D113528#3120193, @jrtc27 wrote:

Looks like they've been broken the whole time; see D65497. Also no clue what fpround is meant to be, all seven (floor, ceil, trunc, rint, nearbyint, round, roundeven) of the rounding intrinsics are already tested (modulo the typos).

This is the only place these are tested with softfloat isn't it?

Looks like it. I don't know why there aren't just RVxxI versions in the {float,double}-intrinsics.ll files; this seems like unnecessary duplication of effort, is under-tested due to not having any RV32I tests and rv64i-double-softfloat.ll is comparatively minimal.

[jrtc27]

I also don't understand why we're not getting tail calls here. Well, the intrinsic calls could be explained by using call rather than tail call in the IR, but I really don't get why the fadd etc instructions aren't converted to tail calls. Does LegalizeFloatTypes just fail to mark its libcalls as tail call candidates?

[craig.topper]

In D113528#3120223, @jrtc27 wrote:

I also don't understand why we're not getting tail calls here. Well, the intrinsic calls could be explained by using call rather than tail call in the IR, but I really don't get why the fadd etc instructions aren't converted to tail calls. Does LegalizeFloatTypes just fail to mark its libcalls as tail call candidates?

I think the TargetLowering::makeLibCall used by LegalizeFloatTypes doesn't set the tail call bit.

[luismarques]

LGTM.

In D113528#3120204, @jrtc27 wrote:

I don't know why there aren't just RVxxI versions in the {float,double}-intrinsics.ll files; this seems like unnecessary duplication of effort, is under-tested due to not having any RV32I tests and rv64i-double-softfloat.ll is comparatively minimal.

@craig.topper Is this something you'd be interested in addressing in a revised version of this patch or in a follow-up patch?

[craig.topper]

In D113528#3124171, @luismarques wrote:

LGTM.

In D113528#3120204, @jrtc27 wrote:

I don't know why there aren't just RVxxI versions in the {float,double}-intrinsics.ll files; this seems like unnecessary duplication of effort, is under-tested due to not having any RV32I tests and rv64i-double-softfloat.ll is comparatively minimal.

@craig.topper Is this something you'd be interested in addressing in a revised version of this patch or in a follow-up patch?

I'll work on it in a follow-up.

llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll

 ; RV64I-NEXT:    call floorf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.floor.f32(float %a)
   ret float %1
 }
 
-declare float @llvm.flog.f32(float)
+declare float @llvm.log.f32(float)
 
-define float @fflog_s(float %a) nounwind {
-; RV64I-LABEL: fflog_s:
+define float @flog_s(float %a) nounwind {
+; RV64I-LABEL: flog_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    call llvm.flog.f32@plt
+; RV64I-NEXT:    call logf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
-  %1 = call float @llvm.flog.f32(float %a)
+  %1 = call float @llvm.log.f32(float %a)
   ret float %1
 }
 
-declare float @llvm.flog2.f32(float)
+declare float @llvm.log2.f32(float)
 
-define float @fflog2_s(float %a) nounwind {
-; RV64I-LABEL: fflog2_s:
+define float @flog2_s(float %a) nounwind {
+; RV64I-LABEL: flog2_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    call llvm.flog2.f32@plt
+; RV64I-NEXT:    call log2f@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
-  %1 = call float @llvm.flog2.f32(float %a)
+  %1 = call float @llvm.log2.f32(float %a)
   ret float %1
 }
 
-declare float @llvm.flog10.f32(float)
+declare float @llvm.log10.f32(float)
 
-define float @fflog10_s(float %a) nounwind {
-; RV64I-LABEL: fflog10_s:
+define float @flog10_s(float %a) nounwind {
+; RV64I-LABEL: flog10_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    call llvm.flog10.f32@plt
+; RV64I-NEXT:    call log10f@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
-  %1 = call float @llvm.flog10.f32(float %a)
+  %1 = call float @llvm.log10.f32(float %a)
   ret float %1
 }
 
-declare float @llvm.fnearbyint.f32(float)
+declare float @llvm.nearbyint.f32(float)
 
 define float @fnearbyint_s(float %a) nounwind {
 ; RV64I-LABEL: fnearbyint_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    call llvm.fnearbyint.f32@plt
+; RV64I-NEXT:    call nearbyintf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
-  %1 = call float @llvm.fnearbyint.f32(float %a)
+  %1 = call float @llvm.nearbyint.f32(float %a)
   ret float %1
 }
 
 declare float @llvm.round.f32(float)
 
 define float @fround_s(float %a) nounwind {
 ; RV64I-LABEL: fround_s:
 ; RV64I:       # %bb.0:

 ; RV64I-NEXT:    call roundevenf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.roundeven.f32(float %a)
   ret float %1
 }
 
-declare float @llvm.fpround.f32(float)
-
-define float @fpround_s(float %a) nounwind {
-; RV64I-LABEL: fpround_s:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    call llvm.fpround.f32@plt
-; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    ret
-  %1 = call float @llvm.fpround.f32(float %a)
-  ret float %1
-}
-
 declare float @llvm.rint.f32(float)
 
 define float @frint_s(float %a) nounwind {
 ; RV64I-LABEL: frint_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call rintf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.rint.f32(float %a)
   ret float %1
 }
 
-declare float @llvm.rem.f32(float)
-
-define float @frem_s(float %a) nounwind {
+define float @frem_s(float %a, float %b) nounwind {
 ; RV64I-LABEL: frem_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    call llvm.rem.f32@plt
+; RV64I-NEXT:    call fmodf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
-  %1 = call float @llvm.rem.f32(float %a)
+  %1 = frem float %a, %b
   ret float %1
 }
 
 declare float @llvm.pow.f32(float %Val, float %power)
 
 define float @fpow_s(float %a, float %b) nounwind {
 ; RV64I-LABEL: fpow_s:
 ; RV64I:       # %bb.0: