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[LegalizeVectorOps][X86] Don't defer BITREVERSE expansion to LegalizeDAG.
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Authored by craig.topper on Oct 21 2021, 11:30 AM.

Details

Summary

By expanding early it allows the shifts to be custom lowered in
LegalizeVectorOps. Then a DAG combine is able to run on them before
LegalizeDAG handles the BUILD_VECTORS for the masks used.

v16Xi8 shift lowering on X86 requires a mask to be applied to a v8i16
shift. The BITREVERSE expansion applied an AND mask before SHL ops and
after SRL ops. This was done to share the same mask constant for both shifts.
It looks like this patch allows DAG combine to remove the AND mask added
after v16i8 SHL by X86 lowering. This maintains the mask sharing that
BITREVERSE was trying to achieve. Prior to this patch it looks like
we kept the mask after the SHL instead which required an extra constant
pool or a PANDN to invert it.

This is dependent on D112248 because RISCV will end up scalarizing the BSWAP
portion of the BITREVERSE expansion if we don't disable BSWAP scalarization in
LegalizeVectorOps first.

Diff Detail

Event Timeline

craig.topper created this revision.Oct 21 2021, 11:30 AM
craig.topper requested review of this revision.Oct 21 2021, 11:30 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 21 2021, 11:30 AM
craig.topper edited the summary of this revision. (Show Details)Oct 21 2021, 11:34 AM
RKSimon accepted this revision.Oct 21 2021, 1:55 PM

LGTM

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
1124

Do we have any consistency on when we use a &Results vs just return the SDValue?

This revision is now accepted and ready to land.Oct 21 2021, 1:55 PM
This revision was landed with ongoing or failed builds.Oct 21 2021, 3:23 PM
This revision was automatically updated to reflect the committed changes.