[RISCV] Optimize immediate materialisation with SH*ADD

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

203

isntruction -> instruction

[craig.topper]

Please add MC layer tests for the "li" pseudo instruction

[benshi001]

In D111484#3056211, @craig.topper wrote:

Please add MC layer tests for the "li" pseudo instruction

Done

[benshi001]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

208

I use Res = TmpSeq instead of return TmpSeq, since there could be other optimization with Zbs, and I would like to do further contrast to select the best instruction sequence.

[luismarques]

LGTM.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
 
   MCRegister SrcReg = RISCV::X0;
   for (RISCVMatInt::Inst &Inst : Seq) {
     if (Inst.Opc == RISCV::LUI) {
       emitToStreamer(
           Out, MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Inst.Imm));
     } else if (Inst.Opc == RISCV::ADDUW) {
       emitToStreamer(Out, MCInstBuilder(RISCV::ADDUW)
                               .addReg(DestReg)
                               .addReg(SrcReg)
                               .addReg(RISCV::X0));
+    } else if (Inst.Opc == RISCV::SH1ADD || Inst.Opc == RISCV::SH2ADD ||
+               Inst.Opc == RISCV::SH3ADD) {
+      emitToStreamer(Out, MCInstBuilder(Inst.Opc)
+                              .addReg(DestReg)
+                              .addReg(SrcReg)
+                              .addReg(SrcReg));
     } else {
       emitToStreamer(
           Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addImm(
                    Inst.Imm));
     }
 
     // Only the first instruction has X0 as its source.
     SrcReg = DestReg;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

if (LeadingZeros == 32 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
         Res = TmpSeq;
         // A 2 instruction sequence is the best we can do.
         if (Res.size() <= 2)
           return Res;
       }
     }
   }
 
+  // Try to generate (SH*ADD r, r), in which r is an int32. The total cost is
+  // at most 3 instructions.
+  if (Res.size() > 3 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
+    assert(ActiveFeatures[RISCV::Feature64Bit] &&
+           "Expected RV32 to only need 2 instructions");
+    int64_t Div = 0;
+    unsigned Opc = 0;
+    // Select the opcode and divisor.
+    if ((Val % 3) == 0 && isInt<32>(Val / 3)) {
+      Div = 3;
+      Opc = RISCV::SH1ADD;
+    } else if ((Val % 5) == 0 && isInt<32>(Val / 5)) {
+      Div = 5;
+      Opc = RISCV::SH2ADD;
+    } else if ((Val % 9) == 0 && isInt<32>(Val / 9)) {
+      Div = 9;
+      Opc = RISCV::SH3ADD;
+    }
+    // Build the new isntruction sequence.
+    if (Div > 0) {
+      Res.clear();
+      generateInstSeqImpl(Val / Div, ActiveFeatures, Res);
+      Res.push_back(RISCVMatInt::Inst(Opc, 0));
+    }
+  }
+
   return Res;
 }
 
 int getIntMatCost(const APInt &Val, unsigned Size,
                   const FeatureBitset &ActiveFeatures,
                   bool CompressionCost) {
   bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
   bool HasRVC = CompressionCost && ActiveFeatures[RISCV::FeatureStdExtC];

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

static SDNode *selectImm(SelectionDAG *CurDAG, const SDLoc &DL, int64_t Imm,
   SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT);
   for (RISCVMatInt::Inst &Inst : Seq) {
     SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, XLenVT);
     if (Inst.Opc == RISCV::LUI)
       Result = CurDAG->getMachineNode(RISCV::LUI, DL, XLenVT, SDImm);
     else if (Inst.Opc == RISCV::ADDUW)
       Result = CurDAG->getMachineNode(RISCV::ADDUW, DL, XLenVT, SrcReg,
                                       CurDAG->getRegister(RISCV::X0, XLenVT));
+    else if (Inst.Opc == RISCV::SH1ADD || Inst.Opc == RISCV::SH2ADD ||
+             Inst.Opc == RISCV::SH3ADD)
+      Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SrcReg);
     else
       Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SDImm);
 
     // Only the first instruction has X0 as its source.
     SrcReg = SDValue(Result, 0);
   }
 
   return Result;

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

if (Inst.Opc == RISCV::LUI) {
       BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result)
           .addImm(Inst.Imm)
           .setMIFlag(Flag);
     } else if (Inst.Opc == RISCV::ADDUW) {
       BuildMI(MBB, MBBI, DL, get(RISCV::ADDUW), Result)
           .addReg(SrcReg, RegState::Kill)
           .addReg(RISCV::X0)
           .setMIFlag(Flag);
+    } else if (Inst.Opc == RISCV::SH1ADD || Inst.Opc == RISCV::SH2ADD ||
+               Inst.Opc == RISCV::SH3ADD) {
+      BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
+          .addReg(SrcReg, RegState::Kill)
+          .addReg(SrcReg, RegState::Kill)
+          .setMIFlag(Flag);
     } else {
       BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
           .addReg(SrcReg, RegState::Kill)
           .addImm(Inst.Imm)
           .setMIFlag(Flag);
     }
     // Only the first instruction has X0 as its source.
     SrcReg = Result;

llvm/test/CodeGen/RISCV/imm.ll

 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    lui a0, 263018
 ; RV32IB-NEXT:    addi a0, a0, -795
 ; RV32IB-NEXT:    addi a1, zero, 1
 ; RV32IB-NEXT:    ret
 ;
 ; RV64IB-LABEL: imm_5372288229:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    lui a0, 160
-; RV64IB-NEXT:    addiw a0, a0, 437
-; RV64IB-NEXT:    slli a0, a0, 13
-; RV64IB-NEXT:    addi a0, a0, -795
+; RV64IB-NEXT:    lui a0, 437198
+; RV64IB-NEXT:    addiw a0, a0, -265
+; RV64IB-NEXT:    sh1add a0, a0, a0
 ; RV64IB-NEXT:    ret
   ret i64 5372288229
 }
 
 define i64 @imm_neg_5372288229() {
 ; RV32IB-LABEL: imm_neg_5372288229:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    lui a0, 785558
 ; RV32IB-NEXT:    addi a0, a0, 795
 ; RV32IB-NEXT:    addi a1, zero, -2
 ; RV32IB-NEXT:    ret
 ;
 ; RV64IB-LABEL: imm_neg_5372288229:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    lui a0, 1048416
-; RV64IB-NEXT:    addiw a0, a0, -437
-; RV64IB-NEXT:    slli a0, a0, 13
-; RV64IB-NEXT:    addi a0, a0, 795
+; RV64IB-NEXT:    lui a0, 611378
+; RV64IB-NEXT:    addiw a0, a0, 265
+; RV64IB-NEXT:    sh1add a0, a0, a0
 ; RV64IB-NEXT:    ret
   ret i64 -5372288229
 }
 
 define i64 @imm_8953813715() {
 ; RV32IB-LABEL: imm_8953813715:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    lui a0, 88838
 ; RV32IB-NEXT:    addi a0, a0, -1325
 ; RV32IB-NEXT:    addi a1, zero, 2
 ; RV32IB-NEXT:    ret
 ;
 ; RV64IB-LABEL: imm_8953813715:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    lui a0, 267
-; RV64IB-NEXT:    addiw a0, a0, -637
-; RV64IB-NEXT:    slli a0, a0, 13
-; RV64IB-NEXT:    addi a0, a0, -1325
+; RV64IB-NEXT:    lui a0, 437198
+; RV64IB-NEXT:    addiw a0, a0, -265
+; RV64IB-NEXT:    sh2add a0, a0, a0
 ; RV64IB-NEXT:    ret
   ret i64 8953813715
 }
 
 define i64 @imm_neg_8953813715() {
 ; RV32IB-LABEL: imm_neg_8953813715:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    lui a0, 959738
 ; RV32IB-NEXT:    addi a0, a0, 1325
 ; RV32IB-NEXT:    addi a1, zero, -3
 ; RV32IB-NEXT:    ret
 ;
 ; RV64IB-LABEL: imm_neg_8953813715:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    lui a0, 1048309
-; RV64IB-NEXT:    addiw a0, a0, 637
-; RV64IB-NEXT:    slli a0, a0, 13
-; RV64IB-NEXT:    addi a0, a0, 1325
+; RV64IB-NEXT:    lui a0, 611378
+; RV64IB-NEXT:    addiw a0, a0, 265
+; RV64IB-NEXT:    sh2add a0, a0, a0
 ; RV64IB-NEXT:    ret
   ret i64 -8953813715
 }
 
 define i64 @imm_16116864687() {
 ; RV32IB-LABEL: imm_16116864687:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    lui a0, 789053
 ; RV32IB-NEXT:    addi a0, a0, 1711
 ; RV32IB-NEXT:    addi a1, zero, 3
 ; RV32IB-NEXT:    ret
 ;
 ; RV64IB-LABEL: imm_16116864687:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    lui a0, 961
-; RV64IB-NEXT:    addiw a0, a0, -1475
-; RV64IB-NEXT:    slli a0, a0, 12
-; RV64IB-NEXT:    addi a0, a0, 1711
+; RV64IB-NEXT:    lui a0, 437198
+; RV64IB-NEXT:    addiw a0, a0, -265
+; RV64IB-NEXT:    sh3add a0, a0, a0
 ; RV64IB-NEXT:    ret
   ret i64 16116864687
 }
 
 define i64 @imm_neg_16116864687() {
 ; RV32IB-LABEL: imm_neg_16116864687:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    lui a0, 259523
 ; RV32IB-NEXT:    addi a0, a0, -1711
 ; RV32IB-NEXT:    addi a1, zero, -4
 ; RV32IB-NEXT:    ret
 ;
 ; RV64IB-LABEL: imm_neg_16116864687:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    lui a0, 1047615
-; RV64IB-NEXT:    addiw a0, a0, 1475
-; RV64IB-NEXT:    slli a0, a0, 12
-; RV64IB-NEXT:    addi a0, a0, -1711
+; RV64IB-NEXT:    lui a0, 611378
+; RV64IB-NEXT:    addiw a0, a0, 265
+; RV64IB-NEXT:    sh3add a0, a0, a0
 ; RV64IB-NEXT:    ret
   ret i64 -16116864687
 }
 
 define i64 @imm_2344336315() {
 ; RV32IB-LABEL: imm_2344336315:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    lui a0, 572348