[RISCV] Optimize immediate materialisation with BCLRI/BSETI

[benshi001]

Summary

Do the following optimization for immediate materialisation:

1. For values in range 0xffffffff 7fffffff ~ 0xffffffff 00000000, first generate the lower 32-bit with Val|0x80000000 (which is expected be an int32), then emit (BCLRI r, 31).

2. For values in range 0x80000000 ~ 0xffffffff, first generate the lower 32-bit with Val&~0x80000000 (which is expected to be an int32), then emit (BSETI r, 31).

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

191

Can this be Val | 0x80000000? That makes more sense to me since BCLRI only affects 1 bit.

[benshi001]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

191

If we change to Val | 0x80000000 instead of Val + 0x80000000,

we still need not to check NewVal != Val, and checking NewVal < 0 && isInt<32>(NewVal) is enough.

Since Val is not int32 while NewVal is.

[craig.topper]

LGTM

[craig.topper]

Since this affects RISCVMatInt.cpp which is used by the assembler as well. We need MC layer tests like the "li" tests in rv64zba-aliases-valid.s

[benshi001]

In D111532#3055747, @craig.topper wrote:

Since this affects RISCVMatInt.cpp which is used by the assembler as well. We need MC layer tests like the "li" tests in rv64zba-aliases-valid.s

Thanks. I have updated according to your advice.

1. MC tests are added in rv64zbs-aliases-valid.s, since BLCRI/BSETI belong to Zbs not Zba.

2. The similiar optimization is also performed against value in 0x80000000 ~ 0xffffffff, although we already optimized with the zext.w. But zext.w belongs to Zba, considering an extrame case that there is only Zbs but no Zba.

3. I use Res = TmpSeq instead of directly return TmpSeq to enable further constrast with future optimization with Zba.

[craig.topper]

Can also test a constant like 0xffffffff7fffffff which we can now do as ADDI+BCLRI. Similarly test a constant that allows ADDI+BSETI.

[craig.topper]

Also please add a description to this patch.

[benshi001]

In D111532#3058983, @craig.topper wrote:

Can also test a constant like 0xffffffff7fffffff which we can now do as ADDI+BCLRI. Similarly test a constant that allows ADDI+BSETI.

Thanks. More tests of ADDI+BCLRI and ADDI+BSETI are added, and also, a short description is added.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

if (LeadingZeros == 32 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
         Res = TmpSeq;
         // A 2 instruction sequence is the best we can do.
         if (Res.size() <= 2)
           return Res;
       }
     }
   }
 
+  // Perform the following optimization with the Zbs extension.
+  // 1. For values in range 0xffffffff 7fffffff ~ 0xffffffff 00000000,
+  //    call generateInstSeqImpl with Val|0x80000000 (which is expected be
+  //    an int32), then emit (BCLRI r, 31).
+  // 2. For values in range 0x80000000 ~ 0xffffffff, call generateInstSeqImpl
+  //    with Val&~0x80000000 (which is expected to be an int32), then
+  //    emit (BSETI r, 31).
+  if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbs]) {
+    assert(ActiveFeatures[RISCV::Feature64Bit] &&
+           "Expected RV32 to only need 2 instructions");
+    int64_t NewVal;
+    unsigned Opc;
+    if (Val < 0) {
+      Opc = RISCV::BCLRI;
+      NewVal = Val | 0x80000000ll;
+    } else {
+      Opc = RISCV::BSETI;
+      NewVal = Val & ~0x80000000ll;
+    }
+    if (isInt<32>(NewVal)) {
+      RISCVMatInt::InstSeq TmpSeq;
+      generateInstSeqImpl(NewVal, ActiveFeatures, TmpSeq);
+      TmpSeq.push_back(RISCVMatInt::Inst(Opc, 31));
+      if (TmpSeq.size() < Res.size())
+        Res = TmpSeq;
+    }
+  }
+
   return Res;
 }
 
 int getIntMatCost(const APInt &Val, unsigned Size,
                   const FeatureBitset &ActiveFeatures,
                   bool CompressionCost) {
   bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
   bool HasRVC = CompressionCost && ActiveFeatures[RISCV::FeatureStdExtC];

llvm/test/CodeGen/RISCV/imm.ll

 ; RV64IZBA:       # %bb.0:
 ; RV64IZBA-NEXT:    lui a0, 699051
 ; RV64IZBA-NEXT:    addiw a0, a0, -1366
 ; RV64IZBA-NEXT:    zext.w a0, a0
 ; RV64IZBA-NEXT:    ret
 ;
 ; RV64IZBS-LABEL: imm_2863311530:
 ; RV64IZBS:       # %bb.0:
-; RV64IZBS-NEXT:    lui a0, 171
-; RV64IZBS-NEXT:    addiw a0, a0, -1365
-; RV64IZBS-NEXT:    slli a0, a0, 12
-; RV64IZBS-NEXT:    addi a0, a0, -1366
+; RV64IZBS-NEXT:    lui a0, 174763
+; RV64IZBS-NEXT:    addiw a0, a0, -1366
+; RV64IZBS-NEXT:    bseti a0, a0, 31
 ; RV64IZBS-NEXT:    ret
   ret i64 2863311530 ; #0xaaaaaaaa
 }
 
 define i64 @imm_neg_2863311530() {
 ; RV32I-LABEL: imm_neg_2863311530:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 349525

 ; RV64IZBA-NEXT:    lui a0, 1048405
 ; RV64IZBA-NEXT:    addiw a0, a0, 1365
 ; RV64IZBA-NEXT:    slli a0, a0, 12
 ; RV64IZBA-NEXT:    addi a0, a0, 1366
 ; RV64IZBA-NEXT:    ret
 ;
 ; RV64IZBS-LABEL: imm_neg_2863311530:
 ; RV64IZBS:       # %bb.0:
-; RV64IZBS-NEXT:    lui a0, 1048405
-; RV64IZBS-NEXT:    addiw a0, a0, 1365
-; RV64IZBS-NEXT:    slli a0, a0, 12
-; RV64IZBS-NEXT:    addi a0, a0, 1366
+; RV64IZBS-NEXT:    lui a0, 873813
+; RV64IZBS-NEXT:    addiw a0, a0, 1366
+; RV64IZBS-NEXT:    bclri a0, a0, 31
 ; RV64IZBS-NEXT:    ret
   ret i64 -2863311530 ; #0xffffffff55555556
 }
+
+define i64 @imm_2147486378() {
+; RV32I-LABEL: imm_2147486378:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a0, 524288
+; RV32I-NEXT:    addi a0, a0, 1365
+; RV32I-NEXT:    mv a1, zero
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: imm_2147486378:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, zero, 1
+; RV64I-NEXT:    slli a0, a0, 31
+; RV64I-NEXT:    addi a0, a0, 1365
+; RV64I-NEXT:    ret
+;
+; RV64IZBA-LABEL: imm_2147486378:
+; RV64IZBA:       # %bb.0:
+; RV64IZBA-NEXT:    addi a0, zero, 1
+; RV64IZBA-NEXT:    slli a0, a0, 31
+; RV64IZBA-NEXT:    addi a0, a0, 1365
+; RV64IZBA-NEXT:    ret
+;
+; RV64IZBS-LABEL: imm_2147486378:
+; RV64IZBS:       # %bb.0:
+; RV64IZBS-NEXT:    addi a0, zero, 1365
+; RV64IZBS-NEXT:    bseti a0, a0, 31
+; RV64IZBS-NEXT:    ret
+  ret i64 2147485013
+}
+
+define i64 @imm_neg_2147485013() {
+; RV32I-LABEL: imm_neg_2147485013:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a0, 524288
+; RV32I-NEXT:    addi a0, a0, -1365
+; RV32I-NEXT:    addi a1, zero, -1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: imm_neg_2147485013:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, zero, -1
+; RV64I-NEXT:    slli a0, a0, 31
+; RV64I-NEXT:    addi a0, a0, -1365
+; RV64I-NEXT:    ret
+;
+; RV64IZBA-LABEL: imm_neg_2147485013:
+; RV64IZBA:       # %bb.0:
+; RV64IZBA-NEXT:    addi a0, zero, -1
+; RV64IZBA-NEXT:    slli a0, a0, 31
+; RV64IZBA-NEXT:    addi a0, a0, -1365
+; RV64IZBA-NEXT:    ret
+;
+; RV64IZBS-LABEL: imm_neg_2147485013:
+; RV64IZBS:       # %bb.0:
+; RV64IZBS-NEXT:    addi a0, zero, -1365
+; RV64IZBS-NEXT:    bclri a0, a0, 31
+; RV64IZBS-NEXT:    ret
+  ret i64 -2147485013
+}

llvm/test/MC/RISCV/rv64zbs-aliases-valid.s

 
 # CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8
 # CHECK-S-OBJ: binvi t0, t1, 8
 binv x5, x6, 8
 
 # CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
 # CHECK-S-OBJ: bexti t0, t1, 8
 bext x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: lui t0, 174763
+# CHECK-S-OBJ-NOALIAS-NEXT: addiw t0, t0, -1366
+# CHECK-S-OBJ-NOALIAS-NEXT: bseti t0, t0, 31
+# CHECK-S-OBJ: lui t0, 174763
+# CHECK-S-OBJ-NEXT: addiw t0, t0, -1366
+# CHECK-S-OBJ-NEXT: bseti t0, t0, 31
+li x5, 2863311530 # 0xaaaaaaaa
+
+# CHECK-S-OBJ-NOALIAS: lui t0, 873813
+# CHECK-S-OBJ-NOALIAS-NEXT: addiw t0, t0, 1366
+# CHECK-S-OBJ-NOALIAS-NEXT: bclri t0, t0, 31
+# CHECK-S-OBJ: lui t0, 873813
+# CHECK-S-OBJ-NEXT: addiw t0, t0, 1366
+# CHECK-S-OBJ-NEXT: bclri t0, t0, 31
+li x5, -2863311530 # 0xffffffff55555556
+
+# CHECK-S-OBJ-NOALIAS: addi t0, zero, 1365
+# CHECK-S-OBJ-NOALIAS-NEXT: bseti t0, t0, 31
+# CHECK-S-OBJ: addi t0, zero, 1365
+# CHECK-S-OBJ-NEXT: bseti t0, t0, 31
+li x5, 2147485013
+
+# CHECK-S-OBJ-NOALIAS: addi t0, zero, -1365
+# CHECK-S-OBJ-NOALIAS-NEXT: bclri t0, t0, 31
+# CHECK-S-OBJ: addi t0, zero, -1365
+# CHECK-S-OBJ-NEXT: bclri t0, t0, 31
+li x5, -2147485013