[RISCV] Optimize immediate materialisation with SH*ADD

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

216

isntruction -> instruction

[craig.topper]

Please add MC layer tests for the "li" pseudo instruction

[benshi001]

In D111484#3056211, @craig.topper wrote:

Please add MC layer tests for the "li" pseudo instruction

Done

[benshi001]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

221

I use Res = TmpSeq instead of return TmpSeq, since there could be other optimization with Zbs, and I would like to do further contrast to select the best instruction sequence.

[luismarques]

LGTM.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

for (RISCVMatInt::Inst &Inst : Seq) {
     if (Inst.Opc == RISCV::LUI) {
       emitToStreamer(
           Out, MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Inst.Imm));
     } else if (Inst.Opc == RISCV::ADDUW) {
       emitToStreamer(Out, MCInstBuilder(RISCV::ADDUW)
                               .addReg(DestReg)
                               .addReg(SrcReg)
                               .addReg(RISCV::X0));
+    } else if (Inst.Opc == RISCV::SH1ADD || Inst.Opc == RISCV::SH2ADD ||
+               Inst.Opc == RISCV::SH3ADD) {
+      emitToStreamer(
+          Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addReg(
+                   SrcReg));
     } else {
       emitToStreamer(
           Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addImm(
                    Inst.Imm));
     }
 
     // Only the first instruction has X0 as its source.
     SrcReg = DestReg;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbs]) {
     //    emit (BSETI r, 31).
     int64_t NewVal;
     unsigned Opc;
     if (Val < 0) {
       Opc = RISCV::BCLRI;
       NewVal = Val | 0x80000000ll;
     } else {
       Opc = RISCV::BSETI;
       NewVal = Val & ~0x80000000ll;
     }
     if (isInt<32>(NewVal)) {
       RISCVMatInt::InstSeq TmpSeq;
       generateInstSeqImpl(NewVal, ActiveFeatures, TmpSeq);
       TmpSeq.push_back(RISCVMatInt::Inst(Opc, 31));
       if (TmpSeq.size() < Res.size())
         Res = TmpSeq;
     }
 
     // Try to use BCLRI for upper 32 bits if the original lower 32 bits are
     // negative int32, or use BSETI for upper 32 bits if the original lower
     // 32 bits are positive int32.
     int32_t Lo = Val;
if (Opc > 0) {
         TmpSeq.push_back(RISCVMatInt::Inst(Opc, Bit + 32));
         Hi &= ~(1 << Bit);
       }
       if (TmpSeq.size() < Res.size())
         Res = TmpSeq;
     }
   }
 
+  // Perform optimization with SH*ADD in the Zba extension.
+  if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
+    assert(ActiveFeatures[RISCV::Feature64Bit] &&
+           "Expected RV32 to only need 2 instructions");
+    int64_t Div = 0;
+    unsigned Opc = 0;
+    RISCVMatInt::InstSeq TmpSeq;
+    // Select the opcode and divisor.
+    if ((Val % 3) == 0 && isInt<32>(Val / 3)) {
+      Div = 3;
+      Opc = RISCV::SH1ADD;
+    } else if ((Val % 5) == 0 && isInt<32>(Val / 5)) {
+      Div = 5;
+      Opc = RISCV::SH2ADD;
+    } else if ((Val % 9) == 0 && isInt<32>(Val / 9)) {
+      Div = 9;
+      Opc = RISCV::SH3ADD;
+    }
+    // Build the new instruction sequence.
+    if (Div > 0) {
+      generateInstSeqImpl(Val / Div, ActiveFeatures, TmpSeq);
+      TmpSeq.push_back(RISCVMatInt::Inst(Opc, 0));
+      if (TmpSeq.size() < Res.size())
+        Res = TmpSeq;
+    }
+  }
+
   return Res;
 }
 
 int getIntMatCost(const APInt &Val, unsigned Size,
                   const FeatureBitset &ActiveFeatures,
                   bool CompressionCost) {
   bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
   bool HasRVC = CompressionCost && ActiveFeatures[RISCV::FeatureStdExtC];

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

static SDNode *selectImm(SelectionDAG *CurDAG, const SDLoc &DL, int64_t Imm,
   SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT);
   for (RISCVMatInt::Inst &Inst : Seq) {
     SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, XLenVT);
     if (Inst.Opc == RISCV::LUI)
       Result = CurDAG->getMachineNode(RISCV::LUI, DL, XLenVT, SDImm);
     else if (Inst.Opc == RISCV::ADDUW)
       Result = CurDAG->getMachineNode(RISCV::ADDUW, DL, XLenVT, SrcReg,
                                       CurDAG->getRegister(RISCV::X0, XLenVT));
+    else if (Inst.Opc == RISCV::SH1ADD || Inst.Opc == RISCV::SH2ADD ||
+             Inst.Opc == RISCV::SH3ADD)
+      Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SrcReg);
     else
       Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SDImm);
 
     // Only the first instruction has X0 as its source.
     SrcReg = SDValue(Result, 0);
   }
 
   return Result;

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

if (Inst.Opc == RISCV::LUI) {
       BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result)
           .addImm(Inst.Imm)
           .setMIFlag(Flag);
     } else if (Inst.Opc == RISCV::ADDUW) {
       BuildMI(MBB, MBBI, DL, get(RISCV::ADDUW), Result)
           .addReg(SrcReg, RegState::Kill)
           .addReg(RISCV::X0)
           .setMIFlag(Flag);
+    } else if (Inst.Opc == RISCV::SH1ADD || Inst.Opc == RISCV::SH2ADD ||
+               Inst.Opc == RISCV::SH3ADD) {
+      BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
+          .addReg(SrcReg, RegState::Kill)
+          .addReg(SrcReg, RegState::Kill)
+          .setMIFlag(Flag);
     } else {
       BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
           .addReg(SrcReg, RegState::Kill)
           .addImm(Inst.Imm)
           .setMIFlag(Flag);
     }
     // Only the first instruction has X0 as its source.
     SrcReg = Result;

llvm/test/CodeGen/RISCV/imm.ll

 ; RV64I-NEXT:    lui a0, 1048416
 ; RV64I-NEXT:    addiw a0, a0, -437
 ; RV64I-NEXT:    slli a0, a0, 13
 ; RV64I-NEXT:    addi a0, a0, 795
 ; RV64I-NEXT:    ret
 ;
 ; RV64IZBA-LABEL: imm_neg_5372288229:
 ; RV64IZBA:       # %bb.0:
-; RV64IZBA-NEXT:    lui a0, 1048416
-; RV64IZBA-NEXT:    addiw a0, a0, -437
-; RV64IZBA-NEXT:    slli a0, a0, 13
-; RV64IZBA-NEXT:    addi a0, a0, 795
+; RV64IZBA-NEXT:    lui a0, 611378
+; RV64IZBA-NEXT:    addiw a0, a0, 265
+; RV64IZBA-NEXT:    sh1add a0, a0, a0
 ; RV64IZBA-NEXT:    ret
 ;
 ; RV64IZBS-LABEL: imm_neg_5372288229:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 785558
 ; RV64IZBS-NEXT:    addiw a0, a0, 795
 ; RV64IZBS-NEXT:    bclri a0, a0, 32
 ; RV64IZBS-NEXT:    ret

 ; RV64I-NEXT:    lui a0, 267
 ; RV64I-NEXT:    addiw a0, a0, -637
 ; RV64I-NEXT:    slli a0, a0, 13
 ; RV64I-NEXT:    addi a0, a0, -1325
 ; RV64I-NEXT:    ret
 ;
 ; RV64IZBA-LABEL: imm_8953813715:
 ; RV64IZBA:       # %bb.0:
-; RV64IZBA-NEXT:    lui a0, 267
-; RV64IZBA-NEXT:    addiw a0, a0, -637
-; RV64IZBA-NEXT:    slli a0, a0, 13
-; RV64IZBA-NEXT:    addi a0, a0, -1325
+; RV64IZBA-NEXT:    lui a0, 437198
+; RV64IZBA-NEXT:    addiw a0, a0, -265
+; RV64IZBA-NEXT:    sh2add a0, a0, a0
 ; RV64IZBA-NEXT:    ret
 ;
 ; RV64IZBS-LABEL: imm_8953813715:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 88838
 ; RV64IZBS-NEXT:    addiw a0, a0, -1325
 ; RV64IZBS-NEXT:    bseti a0, a0, 33
 ; RV64IZBS-NEXT:    ret

 ; RV64I-NEXT:    lui a0, 1048309
 ; RV64I-NEXT:    addiw a0, a0, 637
 ; RV64I-NEXT:    slli a0, a0, 13
 ; RV64I-NEXT:    addi a0, a0, 1325
 ; RV64I-NEXT:    ret
 ;
 ; RV64IZBA-LABEL: imm_neg_8953813715:
 ; RV64IZBA:       # %bb.0:
-; RV64IZBA-NEXT:    lui a0, 1048309
-; RV64IZBA-NEXT:    addiw a0, a0, 637
-; RV64IZBA-NEXT:    slli a0, a0, 13
-; RV64IZBA-NEXT:    addi a0, a0, 1325
+; RV64IZBA-NEXT:    lui a0, 611378
+; RV64IZBA-NEXT:    addiw a0, a0, 265
+; RV64IZBA-NEXT:    sh2add a0, a0, a0
 ; RV64IZBA-NEXT:    ret
 ;
 ; RV64IZBS-LABEL: imm_neg_8953813715:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 959738
 ; RV64IZBS-NEXT:    addiw a0, a0, 1325
 ; RV64IZBS-NEXT:    bclri a0, a0, 33
 ; RV64IZBS-NEXT:    ret

 ; RV64I-NEXT:    lui a0, 961
 ; RV64I-NEXT:    addiw a0, a0, -1475
 ; RV64I-NEXT:    slli a0, a0, 12
 ; RV64I-NEXT:    addi a0, a0, 1711
 ; RV64I-NEXT:    ret
 ;
 ; RV64IZBA-LABEL: imm_16116864687:
 ; RV64IZBA:       # %bb.0:
-; RV64IZBA-NEXT:    lui a0, 961
-; RV64IZBA-NEXT:    addiw a0, a0, -1475
-; RV64IZBA-NEXT:    slli a0, a0, 12
-; RV64IZBA-NEXT:    addi a0, a0, 1711
+; RV64IZBA-NEXT:    lui a0, 437198
+; RV64IZBA-NEXT:    addiw a0, a0, -265
+; RV64IZBA-NEXT:    sh3add a0, a0, a0
 ; RV64IZBA-NEXT:    ret
 ;
 ; RV64IZBS-LABEL: imm_16116864687:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 961
 ; RV64IZBS-NEXT:    addiw a0, a0, -1475
 ; RV64IZBS-NEXT:    slli a0, a0, 12
 ; RV64IZBS-NEXT:    addi a0, a0, 1711

 ; RV64I-NEXT:    lui a0, 1047615
 ; RV64I-NEXT:    addiw a0, a0, 1475
 ; RV64I-NEXT:    slli a0, a0, 12
 ; RV64I-NEXT:    addi a0, a0, -1711
 ; RV64I-NEXT:    ret
 ;
 ; RV64IZBA-LABEL: imm_neg_16116864687:
 ; RV64IZBA:       # %bb.0:
-; RV64IZBA-NEXT:    lui a0, 1047615
-; RV64IZBA-NEXT:    addiw a0, a0, 1475
-; RV64IZBA-NEXT:    slli a0, a0, 12
-; RV64IZBA-NEXT:    addi a0, a0, -1711
+; RV64IZBA-NEXT:    lui a0, 611378
+; RV64IZBA-NEXT:    addiw a0, a0, 265
+; RV64IZBA-NEXT:    sh3add a0, a0, a0
 ; RV64IZBA-NEXT:    ret
 ;
 ; RV64IZBS-LABEL: imm_neg_16116864687:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 1047615
 ; RV64IZBS-NEXT:    addiw a0, a0, 1475
 ; RV64IZBS-NEXT:    slli a0, a0, 12
 ; RV64IZBS-NEXT:    addi a0, a0, -1711

 ; RV64I-NEXT:    lui a0, 1048405
 ; RV64I-NEXT:    addiw a0, a0, 1365
 ; RV64I-NEXT:    slli a0, a0, 12
 ; RV64I-NEXT:    addi a0, a0, 1366
 ; RV64I-NEXT:    ret
 ;
 ; RV64IZBA-LABEL: imm_neg_2863311530:
 ; RV64IZBA:       # %bb.0:
-; RV64IZBA-NEXT:    lui a0, 1048405
-; RV64IZBA-NEXT:    addiw a0, a0, 1365
-; RV64IZBA-NEXT:    slli a0, a0, 12
-; RV64IZBA-NEXT:    addi a0, a0, 1366
+; RV64IZBA-NEXT:    lui a0, 908766
+; RV64IZBA-NEXT:    addiw a0, a0, -546
+; RV64IZBA-NEXT:    sh2add a0, a0, a0
 ; RV64IZBA-NEXT:    ret
 ;
 ; RV64IZBS-LABEL: imm_neg_2863311530:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 873813
 ; RV64IZBS-NEXT:    addiw a0, a0, 1366
 ; RV64IZBS-NEXT:    bclri a0, a0, 31
 ; RV64IZBS-NEXT:    ret

llvm/test/MC/RISCV/rv64zba-aliases-valid.s

 # CHECK-S-OBJ-NEXT: addi t0, t0, 1979
 li x5, 0xbbbbb0007bb
 
 # CHECK-S-OBJ-NOALIAS: lui t0, 768955
 # CHECK-S-OBJ-NOALIAS-NEXT: slli.uw t0, t0, 4
 # CHECK-S-OBJ: lui t0, 768955
 # CHECK-S-OBJ-NEXT: slli.uw t0, t0, 4
 li x5, 0xbbbbb0000
+
+# CHECK-S-OBJ-NOALIAS: lui t1, 611378
+# CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, 265
+# CHECK-S-OBJ-NOALIAS-NEXT: sh1add t1, t1, t1
+# CHECK-S-OBJ: lui t1, 611378
+# CHECK-S-OBJ-NEXT: addiw t1, t1, 265
+# CHECK-S-OBJ-NEXT: sh1add t1, t1, t1
+li x6, -5372288229
+
+# CHECK-S-OBJ-NOALIAS: lui t1, 437198
+# CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, -265
+# CHECK-S-OBJ-NOALIAS-NEXT: sh2add t1, t1, t1
+# CHECK-S-OBJ: lui t1, 437198
+# CHECK-S-OBJ-NEXT: addiw t1, t1, -265
+# CHECK-S-OBJ-NEXT: sh2add t1, t1, t1
+li x6, 8953813715
+
+# CHECK-S-OBJ-NOALIAS: lui t1, 611378
+# CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, 265
+# CHECK-S-OBJ-NOALIAS-NEXT: sh2add t1, t1, t1
+# CHECK-S-OBJ: lui t1, 611378
+# CHECK-S-OBJ-NEXT: addiw t1, t1, 265
+# CHECK-S-OBJ-NEXT: sh2add t1, t1, t1
+li x6, -8953813715
+
+# CHECK-S-OBJ-NOALIAS: lui t1, 437198
+# CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, -265
+# CHECK-S-OBJ-NOALIAS-NEXT: sh3add t1, t1, t1
+# CHECK-S-OBJ: lui t1, 437198
+# CHECK-S-OBJ-NEXT: addiw t1, t1, -265
+# CHECK-S-OBJ-NEXT: sh3add t1, t1, t1
+li x6, 16116864687
+
+# CHECK-S-OBJ-NOALIAS: lui t1, 611378
+# CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, 265
+# CHECK-S-OBJ-NOALIAS-NEXT: sh3add t1, t1, t1
+# CHECK-S-OBJ: lui t1, 611378
+# CHECK-S-OBJ-NEXT: addiw t1, t1, 265
+# CHECK-S-OBJ-NEXT: sh3add t1, t1, t1
+li x6, -16116864687