[AArch64][SVE] Perform FP_EXTEND combine on legal types to fold extend into load

[bsmith]

Summary

The FP_EXTEND combine done to remove extra EXTRACT_SUBVECTORs can also
be done on legal types. In this case there are no EXTRACT_SUBVECTORs
involved, but as a side effect we will end up folding the UUNPKLO generated
by the FP_EXTEND lowering into the load feeding it.

This is a very specific fix that will likely be temporary until a more
general approach is decided upon.

Depends on D110237

[bsmith]

• Redo test changes after recent test reformatting.

[bsmith]

Abandoning in favour of D114628 and D114580

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

 }
 
 static SDValue performFpExtendCombine(SDNode *N, SelectionDAG &DAG,
                                       const AArch64Subtarget *Subtarget) {
   SDLoc DL(N);
   SDValue Op = N->getOperand(0);
   EVT VT = N->getValueType(0);
 
-  if (!VT.isFixedLengthVector())
-    return SDValue();
-
-  if (DAG.getTargetLoweringInfo().isTypeLegal(VT) ||
-      !Subtarget->useSVEForFixedLengthVectors())
+  if (!VT.isFixedLengthVector() || !Subtarget->useSVEForFixedLengthVectors())
     return SDValue();
 
   // In cases where the result of the FP_EXTEND is not legal, it will be
   // expanded into multiple extract_subvectors which cannot be lowered without
   // going through memory.
   //
   // If we push an extend into the load feeding the FP_EXTEND, we can force the
   // load to be be expanded into the same number of parts as the FP_EXTEND,
   // avoiding the need for extract_subvectors completely.
   //
   // As part of the lowering of FP_EXTEND for fixed length types uunpklo nodes
   // will be introduced which will then combine with the truncate introduced
   // after the load.
+  //
+  // In cases where the result of the FP_EXTEND is legal, it is still worth
+  // while to do this, as we will end up folding the integer extend produced by
+  // the FP_EXTEND lowering into the load.
   if (ISD::isNormalLoad(Op.getNode())) {
     LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
 
     // Check if there are other uses. If so, do not combine as it will introduce
     // an extra load.
     for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end();
          UI != UE; ++UI) {
       if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll

 ; CHECK: fcvtl v0.4s, v0.4h
 ; CHECK-NEXT: ret
   %res = fpext <4 x half> %op1 to <4 x float>
   ret <4 x float> %res
 }
 
 define void @fcvt_v8f16_v8f32(<8 x half>* %a, <8 x float>* %b) #0 {
 ; CHECK-LABEL: fcvt_v8f16_v8f32:
-; CHECK: ldr q[[OP:[0-9]+]], [x0]
-; CHECK-NEXT: ptrue [[PG:p[0-9]+]].s, vl8
-; CHECK-NEXT: uunpklo [[UPK:z[0-9]+]].s, z[[OP]].h
-; CHECK-NEXT: fcvt [[RES:z[0-9]+]].s, [[PG]]/m, [[UPK]].h
+; CHECK: ptrue [[PG:p[0-9]+]].s, vl8
+; CHECK-NEXT: ld1h { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; CHECK-NEXT: fcvt [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].h
 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x1]
 ; CHECK-NEXT: ret
   %op1 = load <8 x half>, <8 x half>* %a
   %res = fpext <8 x half> %op1 to <8 x float>
   store <8 x float> %res, <8 x float>* %b
   ret void
 }
 
 define void @fcvt_v16f16_v16f32(<16 x half>* %a, <16 x float>* %b) #0 {
 ; CHECK-LABEL: fcvt_v16f16_v16f32:
-; VBITS_GE_512: ptrue [[PG1:p[0-9]+]].h, vl16
-; VBITS_GE_512-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG1]]/z, [x0]
-; VBITS_GE_512-NEXT: ptrue [[PG2:p[0-9]+]].s, vl16
-; VBITS_GE_512-NEXT: uunpklo [[UPK:z[0-9]+]].s, [[OP]].h
-; VBITS_GE_512-NEXT: fcvt [[RES:z[0-9]+]].s, [[PG2]]/m, [[UPK]].h
-; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG1]], [x1]
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16
+; VBITS_GE_512-NEXT: ld1h { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: fcvt [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].h
+; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x1]
 ; VBITS_GE_512-NEXT: ret
 
 ; Ensure sensible type legalisation
 ; VBITS_EQ_256-DAG: mov x[[NUMELTS:[0-9]+]], #8
 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8
 ; VBITS_EQ_256-DAG: ld1h { [[VEC_LO:z[0-9]+]].s }, [[PG]]/z, [x0]
 ; VBITS_EQ_256-DAG: ld1h { [[VEC_HI:z[0-9]+]].s }, [[PG]]/z, [x0, x[[NUMELTS]], lsl #1]
 ; VBITS_EQ_256-DAG: fcvt [[RES_LO:z[0-9]+]].s, [[PG]]/m, [[VEC_LO]].h
 ; VBITS_EQ_256-DAG: fcvt [[RES_HI:z[0-9]+]].s, [[PG]]/m, [[VEC_HI]].h
 ; VBITS_EQ_256-DAG: st1w { [[RES_LO]].s }, [[PG]], [x1]
 ; VBITS_EQ_256-DAG: st1w { [[RES_HI]].s }, [[PG]], [x1, x[[NUMELTS]], lsl #2]
   %op1 = load <16 x half>, <16 x half>* %a
   %res = fpext <16 x half> %op1 to <16 x float>
   store <16 x float> %res, <16 x float>* %b
   ret void
 }
 
 define void @fcvt_v32f16_v32f32(<32 x half>* %a, <32 x float>* %b) #0 {
 ; CHECK-LABEL: fcvt_v32f16_v32f32:
-; VBITS_GE_1024: ptrue [[PG1:p[0-9]+]].h, vl32
-; VBITS_GE_1024-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG1]]/z, [x0]
-; VBITS_GE_1024-NEXT: ptrue [[PG2:p[0-9]+]].s, vl32
-; VBITS_GE_1024-NEXT: uunpklo [[UPK:z[0-9]+]].s, [[OP]].h
-; VBITS_GE_1024-NEXT: fcvt [[RES:z[0-9]+]].s, [[PG2]]/m, [[UPK]].h
-; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG1]], [x1]
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32
+; VBITS_GE_1024-NEXT: ld1h { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: fcvt [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].h
+; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x1]
 ; VBITS_GE_1024-NEXT: ret
   %op1 = load <32 x half>, <32 x half>* %a
   %res = fpext <32 x half> %op1 to <32 x float>
   store <32 x float> %res, <32 x float>* %b
   ret void
 }
 
 define void @fcvt_v64f16_v64f32(<64 x half>* %a, <64 x float>* %b) #0 {
 ; CHECK-LABEL: fcvt_v64f16_v64f32:
-; VBITS_GE_2048: ptrue [[PG1:p[0-9]+]].h, vl64
-; VBITS_GE_2048-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG1]]/z, [x0]
-; VBITS_GE_2048-NEXT: ptrue [[PG2:p[0-9]+]].s, vl64
-; VBITS_GE_2048-NEXT: uunpklo [[UPK:z[0-9]+]].s, [[OP]].h
-; VBITS_GE_2048-NEXT: fcvt [[RES:z[0-9]+]].s, [[PG2]]/m, [[UPK]].h
-; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG1]], [x1]
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64
+; VBITS_GE_2048-NEXT: ld1h { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: fcvt [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].h
+; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x1]
 ; VBITS_GE_2048-NEXT: ret
   %op1 = load <64 x half>, <64 x half>* %a
   %res = fpext <64 x half> %op1 to <64 x float>
   store <64 x float> %res, <64 x float>* %b
   ret void
 }
 
 ;

 ; CHECK-NEXT: fcvt z0.d, [[PG]]/m, [[UPK2]].h
 ; CHECK-NEXT: ret
   %res = fpext <2 x half> %op1 to <2 x double>
   ret <2 x double> %res
 }
 
 define void @fcvt_v4f16_v4f64(<4 x half>* %a, <4 x double>* %b) #0 {
 ; CHECK-LABEL: fcvt_v4f16_v4f64:
-; CHECK: ldr d[[OP:[0-9]+]], [x0]
-; CHECK-NEXT: ptrue [[PG:p[0-9]+]].d, vl4
-; CHECK-NEXT: uunpklo [[UPK1:z[0-9]+]].s, z[[OP]].h
-; CHECK-NEXT: uunpklo [[UPK2:z[0-9]+]].d, [[UPK1]].s
-; CHECK-NEXT: fcvt [[RES:z[0-9]+]].d, [[PG]]/m, [[UPK2]].h
+; CHECK: ptrue [[PG:p[0-9]+]].d, vl4
+; CHECK-NEXT: ld1h { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; CHECK-NEXT: fcvt [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].h
 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x1]
 ; CHECK-NEXT: ret
   %op1 = load <4 x half>, <4 x half>* %a
   %res = fpext <4 x half> %op1 to <4 x double>
   store <4 x double> %res, <4 x double>* %b
   ret void
 }
 
 define void @fcvt_v8f16_v8f64(<8 x half>* %a, <8 x double>* %b) #0 {
 ; CHECK-LABEL: fcvt_v8f16_v8f64:
-; VBITS_GE_512: ldr q[[OP:[0-9]+]], [x0]
-; VBITS_GE_512-NEXT: ptrue [[PG:p[0-9]+]].d, vl8
-; VBITS_GE_512-NEXT: uunpklo [[UPK1:z[0-9]+]].s, z[[OP]].h
-; VBITS_GE_512-NEXT: uunpklo [[UPK2:z[0-9]+]].d, [[UPK1]].s
-; VBITS_GE_512-NEXT: fcvt [[RES:z[0-9]+]].d, [[PG]]/m, [[UPK2]].h
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl8
+; VBITS_GE_512-NEXT: ld1h { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: fcvt [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].h
 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x1]
 ; VBITS_GE_512-NEXT: ret
 
 ; Ensure sensible type legalisation.
 ; VBITS_EQ_256-DAG: mov x[[NUMELTS:[0-9]+]], #4
 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4
 ; VBITS_EQ_254-DAG: ld1h { [[VEC_HI:z[0-9]+]].d }, [[PG]]/z, [x0, x[[NUMELTS]], lsl #1]
 ; VBITS_EQ_254-DAG: ld1h { [[VEC_LO:z[0-9]+]].d }, [[PG]]/z, [x0]
 ; VBITS_EQ_256-DAG: fcvt [[RES_LO:z[0-9]+]].d, [[PG]]/m, [[VEC_LO]].h
 ; VBITS_EQ_256-DAG: fcvt [[RES_HI:z[0-9]+]].d, [[PG]]/m, [[VEC_HI]].h
 ; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x1]
 ; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x1, x[[NUMELTS]], lsl #3]
   %op1 = load <8 x half>, <8 x half>* %a
   %res = fpext <8 x half> %op1 to <8 x double>
   store <8 x double> %res, <8 x double>* %b
   ret void
 }
 
 define void @fcvt_v16f16_v16f64(<16 x half>* %a, <16 x double>* %b) #0 {
 ; CHECK-LABEL: fcvt_v16f16_v16f64:
-; VBITS_GE_1024: ptrue [[PG1:p[0-9]+]].h, vl16
-; VBITS_GE_1024-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG1]]/z, [x0]
-; VBITS_GE_1024-NEXT: ptrue [[PG2:p[0-9]+]].d, vl16
-; VBITS_GE_1024-NEXT: uunpklo [[UPK1:z[0-9]+]].s, [[OP]].h
-; VBITS_GE_1024-NEXT: uunpklo [[UPK2:z[0-9]+]].d, [[UPK1]].s
-; VBITS_GE_1024-NEXT: fcvt [[RES:z[0-9]+]].d, [[PG2]]/m, [[UPK2]].h
-; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG1]], [x1]
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl16
+; VBITS_GE_1024-NEXT: ld1h { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: fcvt [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].h
+; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x1]
 ; VBITS_GE_1024-NEXT: ret
   %op1 = load <16 x half>, <16 x half>* %a
   %res = fpext <16 x half> %op1 to <16 x double>
   store <16 x double> %res, <16 x double>* %b
   ret void
 }
 
 define void @fcvt_v32f16_v32f64(<32 x half>* %a, <32 x double>* %b) #0 {
 ; CHECK-LABEL: fcvt_v32f16_v32f64:
-; VBITS_GE_2048: ptrue [[PG1:p[0-9]+]].h, vl32
-; VBITS_GE_2048-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG1]]/z, [x0]
-; VBITS_GE_2048-NEXT: ptrue [[PG2:p[0-9]+]].d, vl32
-; VBITS_GE_2048-NEXT: uunpklo [[UPK1:z[0-9]+]].s, [[OP]].h
-; VBITS_GE_2048-NEXT: uunpklo [[UPK2:z[0-9]+]].d, [[UPK]].s
-; VBITS_GE_2048-NEXT: fcvt [[RES:z[0-9]+]].d, [[PG2]]/m, [[UPK2]].h
-; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG1]], [x1]
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl32
+; VBITS_GE_2048-NEXT: ld1h { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: fcvt [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].h
+; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x1]
 ; VBITS_GE_2048-NEXT: ret
   %op1 = load <32 x half>, <32 x half>* %a
   %res = fpext <32 x half> %op1 to <32 x double>
   store <32 x double> %res, <32 x double>* %b
   ret void
 }
 
 ;

 ; CHECK: fcvtl v0.2d, v0.2s
 ; CHECK-NEXT: ret
   %res = fpext <2 x float> %op1 to <2 x double>
   ret <2 x double> %res
 }
 
 define void @fcvt_v4f32_v4f64(<4 x float>* %a, <4 x double>* %b) #0 {
 ; CHECK-LABEL: fcvt_v4f32_v4f64:
-; CHECK: ldr q[[OP:[0-9]+]], [x0]
-; CHECK-NEXT: ptrue [[PG:p[0-9]+]].d, vl4
-; CHECK-NEXT: uunpklo [[UPK:z[0-9]+]].d, z[[OP]].s
-; CHECK-NEXT: fcvt [[RES:z[0-9]+]].d, [[PG]]/m, [[UPK]].s
+; CHECK: ptrue [[PG:p[0-9]+]].d, vl4
+; CHECK-NEXT: ld1w { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; CHECK-NEXT: fcvt [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].s
 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x1]
 ; CHECK-NEXT: ret
   %op1 = load <4 x float>, <4 x float>* %a
   %res = fpext <4 x float> %op1 to <4 x double>
   store <4 x double> %res, <4 x double>* %b
   ret void
 }
 
 define void @fcvt_v8f32_v8f64(<8 x float>* %a, <8 x double>* %b) #0 {
 ; CHECK-LABEL: fcvt_v8f32_v8f64:
-; VBITS_GE_512: ptrue [[PG1:p[0-9]+]].s, vl8
-; VBITS_GE_512-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG1]]/z, [x0]
-; VBITS_GE_512-NEXT: ptrue [[PG:p[0-9]+]].d, vl8
-; VBITS_GE_512-NEXT: uunpklo [[UPK:z[0-9]+]].d, [[OP]].s
-; VBITS_GE_512-NEXT: fcvt [[RES:z[0-9]+]].d, [[PG1]]/m, [[UPK]].s
-; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG1]], [x1]
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl8
+; VBITS_GE_512-NEXT: ld1w { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: fcvt [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].s
+; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x1]
 ; VBITS_GE_512-NEXT: ret
 
 ; Ensure sensible type legalisation
 ; VBITS_EQ_256-DAG: mov x[[NUMELTS:[0-9]+]], #4
 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4
 ; VBITS_EQ_256-DAG: ld1w { [[VEC_HI:z[0-9]+]].d }, [[PG]]/z, [x0, x[[NUMELTS]], lsl #2]
 ; VBITS_EQ_256-DAG: ld1w { [[VEC_LO:z[0-9]+]].d }, [[PG]]/z, [x0]
 ; VBITS_EQ_256-DAG: fcvt [[RES_LO:z[0-9]+]].d, [[PG]]/m, [[VEC_LO]].s
 ; VBITS_EQ_256-DAG: fcvt [[RES_HI:z[0-9]+]].d, [[PG]]/m, [[VEC_HI]].s
 ; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x1]
 ; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x1, x[[NUMELTS]], lsl #3]
   %op1 = load <8 x float>, <8 x float>* %a
   %res = fpext <8 x float> %op1 to <8 x double>
   store <8 x double> %res, <8 x double>* %b
   ret void
 }
 
 define void @fcvt_v16f32_v16f64(<16 x float>* %a, <16 x double>* %b) #0 {
 ; CHECK-LABEL: fcvt_v16f32_v16f64:
-; VBITS_GE_1024: ptrue [[PG1:p[0-9]+]].s, vl16
-; VBITS_GE_1024-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG1]]/z, [x0]
-; VBITS_GE_1024-NEXT: ptrue [[PG2:p[0-9]+]].d, vl16
-; VBITS_GE_1024-NEXT: uunpklo [[UPK:z[0-9]+]].d, [[OP]].s
-; VBITS_GE_1024-NEXT: fcvt [[RES:z[0-9]+]].d, [[PG2]]/m, [[UPK]].s
-; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG1]], [x1]
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl16
+; VBITS_GE_1024-NEXT: ld1w { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: fcvt [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].s
+; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x1]
 ; VBITS_GE_1024-NEXT: ret
   %op1 = load <16 x float>, <16 x float>* %a
   %res = fpext <16 x float> %op1 to <16 x double>
   store <16 x double> %res, <16 x double>* %b
   ret void
 }
 
 define void @fcvt_v32f32_v32f64(<32 x float>* %a, <32 x double>* %b) #0 {
 ; CHECK-LABEL: fcvt_v32f32_v32f64:
-; VBITS_GE_2048: ptrue [[PG1:p[0-9]+]].s, vl32
-; VBITS_GE_2048-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG1]]/z, [x0]
-; VBITS_GE_2048-NEXT: ptrue [[PG2:p[0-9]+]].d, vl32
-; VBITS_GE_2048-NEXT: uunpklo [[UPK:z[0-9]+]].d, [[OP]].s
-; VBITS_GE_2048-NEXT: fcvt [[RES:z[0-9]+]].d, [[PG2]]/m, [[UPK]].s
-; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG1]], [x1]
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl32
+; VBITS_GE_2048-NEXT: ld1w { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: fcvt [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].s
+; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x1]
 ; VBITS_GE_2048-NEXT: ret
   %op1 = load <32 x float>, <32 x float>* %a
   %res = fpext <32 x float> %op1 to <32 x double>
   store <32 x double> %res, <32 x double>* %b
   ret void
 }
 
 ;
; VBITS_GE_1024-NEXT: ret
   ret void
 }
 
 define void @fcvt_v64f32_v64f16(<64 x float>* %a, <64 x half>* %b) #0 {
 ; CHECK-LABEL: fcvt_v64f32_v64f16:
 ; VBITS_GE_2048: ptrue [[PG1:p[0-9]+]].s, vl64
 ; VBITS_GE_2048-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG1]]/z, [x0]
 ; VBITS_GE_2048-NEXT: ptrue [[PG2:p[0-9]+]].s
-; VBITS_GE_2048-NEXT: fcvt [[RES:z[0-9]+]].h, [[PG2]]/m, [[UPK]].s
+; VBITS_GE_2048-NEXT: fcvt [[RES:z[0-9]+]].h, [[PG2]]/m, [[OP]].s
 ; VBITS_GE_2048-NEXT: uzp1 [[RES:z[0-9]+]].h, [[CVT]].h, [[CVT]].h
 ; VBITS_GE_2048-NEXT: ptrue [[PG3:p[0-9]+]].h, vl64
 ; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG3]], [x1]
 ; VBITS_GE_2048-NEXT: ret
   %op1 = load <64 x float>, <64 x float>* %a
   %res = fptrunc <64 x float> %op1 to <64 x half>
   store <64 x half> %res, <64 x half>* %b
   ret void