[TargetLowering][RISCV] Fixed a scalable vector issue when lowering [s|u]mul.overflow intrinsics

[tangxingxin1008]

Summary

Fixed the vector type issue that where we used getVectorNumElements()
should be replaced by getVectorElementCount() when lowering these
intrinsics.

This is similar to D94149

Signed-off-by: Eric Tang <[e-mail]>

[frasercrmck]

LGTM, thanks!

[craig.topper]

Does this affect AArch64 too?

[tangxingxin1008]

In D109809#3008071, @craig.topper wrote:

Does this affect AArch64 too?

Yes, I test it on AArch64 sve.
After add this patch, there is no problem on the legal scalable vector that AArch64 sve support, but failed on the vector that need be Widened, such as <n x 1 x i1>.

[craig.topper]

LGTM. Would be nice if you added AArch64 test cases that would fail without this patch as well.

[tangxingxin1008]

Add AArch64 sve test case. Address Craig Topper's suggestion.

[tangxingxin1008]

Sorry, I don't know how to merged this patch, and get a wrong way to close this revision. Please forgive me for my mistake.

[tangxingxin1008]

Hi @craig.topper @frasercrmck , I don’t have commit access, can you land this patch for me? Thanks.

[frasercrmck]

In D109809#3139396, @tangxingxin1008 wrote:

Hi @craig.topper @frasercrmck , I don’t have commit access, can you land this patch for me? Thanks.

Sure, no problem. I even got to learn how to check out and land other people's patches using arcanist, so that was helpful. Thanks for the patch @tangxingxin1008!

[Orlando]

Hi, the tests added in this commit seem to be failing on some buildbots. E.g. https://lab.llvm.org/buildbot/#/builders/109/builds/26584

[frasercrmck]

In D109809#3139769, @Orlando wrote:

Hi, the tests added in this commit seem to be failing on some buildbots. E.g. https://lab.llvm.org/buildbot/#/builders/109/builds/26584

Hey. Sorry! Thanks for reporting this. I did check out, build & test this patch locally before pushing so I'm not sure what I did wrong. I'll see if it's as simple as re-running the update_llc_test_checks.py script.

[frasercrmck]

In D109809#3139769, @Orlando wrote:

Hi, the tests added in this commit seem to be failing on some buildbots. E.g. https://lab.llvm.org/buildbot/#/builders/109/builds/26584

Just pushed https://reviews.llvm.org/rGe1acbda158b3 which should sort the issue out. Sorry again.

[Orlando]

In D109809#3139805, @frasercrmck wrote:

In D109809#3139769, @Orlando wrote:

Hi, the tests added in this commit seem to be failing on some buildbots. E.g. https://lab.llvm.org/buildbot/#/builders/109/builds/26584

Just pushed https://reviews.llvm.org/rGe1acbda158b3 which should sort the issue out. Sorry again.

No problem. The tests pass for me locally now, thanks!

[tangxingxin1008]

Thank you for all your help! @frasercrmck

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (C.isPowerOf2()) {
                       dl, VT, Result, ShiftAmt),
           LHS, ISD::SETNE);
       return true;
     }
   }
 
   EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getScalarSizeInBits() * 2);
   if (VT.isVector())
     WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
-                              VT.getVectorNumElements());
+                              VT.getVectorElementCount());
 
   SDValue BottomHalf;
   SDValue TopHalf;
   static const unsigned Ops[2][3] =
       { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
         { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
   if (isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
     BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);

llvm/test/CodeGen/RISCV/rvv/smulo-sdnode.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+declare { <vscale x 1 x i8>, <vscale x 1 x i1> } @llvm.smul.with.overflow.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>)
+
+define <vscale x 1 x i8> @smulo_nxv1i8(<vscale x 1 x i8> %x, <vscale x 1 x i8> %y) {
+; CHECK-LABEL: smulo_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
+; CHECK-NEXT:    vmulh.vv v25, v8, v9
+; CHECK-NEXT:    vmul.vv v26, v8, v9
+; CHECK-NEXT:    vsra.vi v27, v26, 7
+; CHECK-NEXT:    vmsne.vv v0, v25, v27
+; CHECK-NEXT:    vmerge.vim v8, v26, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 1 x i8>, <vscale x 1 x i1> } @llvm.smul.with.overflow.nxv1i8(<vscale x 1 x i8> %x, <vscale x 1 x i8> %y)
+  %b = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i1> } %a, 0
+  %c = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i1> } %a, 1
+  %d = select <vscale x 1 x i1> %c, <vscale x 1 x i8> zeroinitializer, <vscale x 1 x i8> %b
+  ret <vscale x 1 x i8> %d
+}
+
+declare { <vscale x 2 x i8>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)
+
+define <vscale x 2 x i8> @smulo_nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y) {
+; CHECK-LABEL: smulo_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
+; CHECK-NEXT:    vmulh.vv v25, v8, v9
+; CHECK-NEXT:    vmul.vv v26, v8, v9
+; CHECK-NEXT:    vsra.vi v27, v26, 7
+; CHECK-NEXT:    vmsne.vv v0, v25, v27
+; CHECK-NEXT:    vmerge.vim v8, v26, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 2 x i8>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y)
+  %b = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i1> } %a, 0
+  %c = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i1> } %a, 1
+  %d = select <vscale x 2 x i1> %c, <vscale x 2 x i8> zeroinitializer, <vscale x 2 x i8> %b
+  ret <vscale x 2 x i8> %d
+}
+
+declare { <vscale x 4 x i8>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
+
+define <vscale x 4 x i8> @smulo_nxv4i8(<vscale x 4 x i8> %x, <vscale x 4 x i8> %y) {
+; CHECK-LABEL: smulo_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
+; CHECK-NEXT:    vmulh.vv v25, v8, v9
+; CHECK-NEXT:    vmul.vv v26, v8, v9
+; CHECK-NEXT:    vsra.vi v27, v26, 7
+; CHECK-NEXT:    vmsne.vv v0, v25, v27
+; CHECK-NEXT:    vmerge.vim v8, v26, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 4 x i8>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i8(<vscale x 4 x i8> %x, <vscale x 4 x i8> %y)
+  %b = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i1> } %a, 0
+  %c = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i1> } %a, 1
+  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i8> zeroinitializer, <vscale x 4 x i8> %b
+  ret <vscale x 4 x i8> %d
+}
+
+declare { <vscale x 8 x i8>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
+
+define <vscale x 8 x i8> @smulo_nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {
+; CHECK-LABEL: smulo_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
+; CHECK-NEXT:    vmulh.vv v25, v8, v9
+; CHECK-NEXT:    vmul.vv v26, v8, v9
+; CHECK-NEXT:    vsra.vi v27, v26, 7
+; CHECK-NEXT:    vmsne.vv v0, v25, v27
+; CHECK-NEXT:    vmerge.vim v8, v26, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 8 x i8>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y)
+  %b = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i1> } %a, 0
+  %c = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i1> } %a, 1
+  %d = select <vscale x 8 x i1> %c, <vscale x 8 x i8> zeroinitializer, <vscale x 8 x i8> %b
+  ret <vscale x 8 x i8> %d
+}
+
+declare { <vscale x 16 x i8>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
+
+define <vscale x 16 x i8> @smulo_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: smulo_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
+; CHECK-NEXT:    vmulh.vv v26, v8, v10
+; CHECK-NEXT:    vmul.vv v28, v8, v10
+; CHECK-NEXT:    vsra.vi v30, v28, 7
+; CHECK-NEXT:    vmsne.vv v0, v26, v30
+; CHECK-NEXT:    vmerge.vim v8, v28, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 16 x i8>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)
+  %b = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i1> } %a, 0
+  %c = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i1> } %a, 1
+  %d = select <vscale x 16 x i1> %c, <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8> %b
+  ret <vscale x 16 x i8> %d
+}
+
+declare { <vscale x 32 x i8>, <vscale x 32 x i1> } @llvm.smul.with.overflow.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>)
+
+define <vscale x 32 x i8> @smulo_nxv32i8(<vscale x 32 x i8> %x, <vscale x 32 x i8> %y) {
+; CHECK-LABEL: smulo_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
+; CHECK-NEXT:    vmulh.vv v28, v8, v12
+; CHECK-NEXT:    vmul.vv v8, v8, v12
+; CHECK-NEXT:    vsra.vi v12, v8, 7
+; CHECK-NEXT:    vmsne.vv v0, v28, v12
+; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 32 x i8>, <vscale x 32 x i1> } @llvm.smul.with.overflow.nxv32i8(<vscale x 32 x i8> %x, <vscale x 32 x i8> %y)
+  %b = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i1> } %a, 0
+  %c = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i1> } %a, 1
+  %d = select <vscale x 32 x i1> %c, <vscale x 32 x i8> zeroinitializer, <vscale x 32 x i8> %b
+  ret <vscale x 32 x i8> %d
+}
+
+declare { <vscale x 64 x i8>, <vscale x 64 x i1> } @llvm.smul.with.overflow.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>)
+
+define <vscale x 64 x i8> @smulo_nxv64i8(<vscale x 64 x i8> %x, <vscale x 64 x i8> %y) {
+; CHECK-LABEL: smulo_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
+; CHECK-NEXT:    vmulh.vv v24, v8, v16
+; CHECK-NEXT:    vmul.vv v8, v8, v16
+; CHECK-NEXT:    vsra.vi v16, v8, 7
+; CHECK-NEXT:    vmsne.vv v0, v24, v16
+; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 64 x i8>, <vscale x 64 x i1> } @llvm.smul.with.overflow.nxv64i8(<vscale x 64 x i8> %x, <vscale x 64 x i8> %y)
+  %b = extractvalue { <vscale x 64 x i8>, <vscale x 64 x i1> } %a, 0
+  %c = extractvalue { <vscale x 64 x i8>, <vscale x 64 x i1> } %a, 1
+  %d = select <vscale x 64 x i1> %c, <vscale x 64 x i8> zeroinitializer, <vscale x 64 x i8> %b
+  ret <vscale x 64 x i8> %d
+}
+
+declare { <vscale x 1 x i16>, <vscale x 1 x i1> } @llvm.smul.with.overflow.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>)
+
+define <vscale x 1 x i16> @smulo_nxv1i16(<vscale x 1 x i16> %x, <vscale x 1 x i16> %y) {
+; CHECK-LABEL: smulo_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vmulh.vv v25, v8, v9
+; CHECK-NEXT:    vmul.vv v26, v8, v9
+; CHECK-NEXT:    vsra.vi v27, v26, 15
+; CHECK-NEXT:    vmsne.vv v0, v25, v27
+; CHECK-NEXT:    vmerge.vim v8, v26, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 1 x i16>, <vscale x 1 x i1> } @llvm.smul.with.overflow.nxv1i16(<vscale x 1 x i16> %x, <vscale x 1 x i16> %y)
+  %b = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i1> } %a, 0
+  %c = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i1> } %a, 1
+  %d = select <vscale x 1 x i1> %c, <vscale x 1 x i16> zeroinitializer, <vscale x 1 x i16> %b
+  ret <vscale x 1 x i16> %d
+}
+
+declare { <vscale x 2 x i16>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
+
+define <vscale x 2 x i16> @smulo_nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y) {
+; CHECK-LABEL: smulo_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vmulh.vv v25, v8, v9
+; CHECK-NEXT:    vmul.vv v26, v8, v9
+; CHECK-NEXT:    vsra.vi v27, v26, 15
+; CHECK-NEXT:    vmsne.vv v0, v25, v27
+; CHECK-NEXT:    vmerge.vim v8, v26, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 2 x i16>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y)
+  %b = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i1> } %a, 0
+  %c = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i1> } %a, 1
+  %d = select <vscale x 2 x i1> %c, <vscale x 2 x i16> zeroinitializer, <vscale x 2 x i16> %b
+  ret <vscale x 2 x i16> %d
+}
+
+declare { <vscale x 4 x i16>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
+
+define <vscale x 4 x i16> @smulo_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y) {
+; CHECK-LABEL: smulo_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vmulh.vv v25, v8, v9
+; CHECK-NEXT:    vmul.vv v26, v8, v9
+; CHECK-NEXT:    vsra.vi v27, v26, 15
+; CHECK-NEXT:    vmsne.vv v0, v25, v27
+; CHECK-NEXT:    vmerge.vim v8, v26, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 4 x i16>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y)
+  %b = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i1> } %a, 0
+  %c = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i1> } %a, 1
+  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i16> zeroinitializer, <vscale x 4 x i16> %b
+  ret <vscale x 4 x i16> %d
+}
+
+declare { <vscale x 8 x i16>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
+
+define <vscale x 8 x i16> @smulo_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: smulo_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vmulh.vv v26, v8, v10
+; CHECK-NEXT:    vmul.vv v28, v8, v10
+; CHECK-NEXT:    vsra.vi v30, v28, 15
+; CHECK-NEXT:    vmsne.vv v0, v26, v30
+; CHECK-NEXT:    vmerge.vim v8, v28, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 8 x i16>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)
+  %b = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i1> } %a, 0
+  %c = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i1> } %a, 1
+  %d = select <vscale x 8 x i1> %c, <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i16> %b
+  ret <vscale x 8 x i16> %d
+}
+
+declare { <vscale x 16 x i16>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
+
+define <vscale x 16 x i16> @smulo_nxv16i16(<vscale x 16 x i16> %x, <vscale x 16 x i16> %y) {
+; CHECK-LABEL: smulo_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vmulh.vv v28, v8, v12
+; CHECK-NEXT:    vmul.vv v8, v8, v12
+; CHECK-NEXT:    vsra.vi v12, v8, 15
+; CHECK-NEXT:    vmsne.vv v0, v28, v12
+; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 16 x i16>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i16(<vscale x 16 x i16> %x, <vscale x 16 x i16> %y)
+  %b = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i1> } %a, 0
+  %c = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i1> } %a, 1
+  %d = select <vscale x 16 x i1> %c, <vscale x 16 x i16> zeroinitializer, <vscale x 16 x i16> %b
+  ret <vscale x 16 x i16> %d
+}
+
+declare { <vscale x 32 x i16>, <vscale x 32 x i1> } @llvm.smul.with.overflow.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>)
+
+define <vscale x 32 x i16> @smulo_nxv32i16(<vscale x 32 x i16> %x, <vscale x 32 x i16> %y) {
+; CHECK-LABEL: smulo_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
+; CHECK-NEXT:    vmulh.vv v24, v8, v16
+; CHECK-NEXT:    vmul.vv v8, v8, v16
+; CHECK-NEXT:    vsra.vi v16, v8, 15
+; CHECK-NEXT:    vmsne.vv v0, v24, v16
+; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 32 x i16>, <vscale x 32 x i1> } @llvm.smul.with.overflow.nxv32i16(<vscale x 32 x i16> %x, <vscale x 32 x i16> %y)
+  %b = extractvalue { <vscale x 32 x i16>, <vscale x 32 x i1> } %a, 0
+  %c = extractvalue { <vscale x 32 x i16>, <vscale x 32 x i1> } %a, 1
+  %d = select <vscale x 32 x i1> %c, <vscale x 32 x i16> zeroinitializer, <vscale x 32 x i16> %b
+  ret <vscale x 32 x i16> %d
+}
+
+declare { <vscale x 1 x i32>, <vscale x 1 x i1> } @llvm.smul.with.overflow.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>)
+
+define <vscale x 1 x i32> @smulo_nxv1i32(<vscale x 1 x i32> %x, <vscale x 1 x i32> %y) {
+; CHECK-LABEL: smulo_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulh.vv v25, v8, v9
+; CHECK-NEXT:    vmul.vv v26, v8, v9
+; CHECK-NEXT:    vsra.vi v27, v26, 31
+; CHECK-NEXT:    vmsne.vv v0, v25, v27
+; CHECK-NEXT:    vmerge.vim v8, v26, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 1 x i32>, <vscale x 1 x i1> } @llvm.smul.with.overflow.nxv1i32(<vscale x 1 x i32> %x, <vscale x 1 x i32> %y)
+  %b = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i1> } %a, 0
+  %c = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i1> } %a, 1
+  %d = select <vscale x 1 x i1> %c, <vscale x 1 x i32> zeroinitializer, <vscale x 1 x i32> %b
+  ret <vscale x 1 x i32> %d
+}
+
+declare { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
+
+define <vscale x 2 x i32> @smulo_nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) {
+; CHECK-LABEL: smulo_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulh.vv v25, v8, v9
+; CHECK-NEXT:    vmul.vv v26, v8, v9
+; CHECK-NEXT:    vsra.vi v27, v26, 31
+; CHECK-NEXT:    vmsne.vv v0, v25, v27
+; CHECK-NEXT:    vmerge.vim v8, v26, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y)
+  %b = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 0
+  %c = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 1
+  %d = select <vscale x 2 x i1> %c, <vscale x 2 x i32> zeroinitializer, <vscale x 2 x i32> %b
+  ret <vscale x 2 x i32> %d
+}
+
+declare { <vscale x 4 x i32>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
+
+define <vscale x 4 x i32> @smulo_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: smulo_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulh.vv v26, v8, v10
+; CHECK-NEXT:    vmul.vv v28, v8, v10
+; CHECK-NEXT:    vsra.vi v30, v28, 31
+; CHECK-NEXT:    vmsne.vv v0, v26, v30
+; CHECK-NEXT:    vmerge.vim v8, v28, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 4 x i32>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)
+  %b = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i1> } %a, 0
+  %c = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i1> } %a, 1
+  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> %b
+  ret <vscale x 4 x i32> %d
+}
+
+declare { <vscale x 8 x i32>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
+
+define <vscale x 8 x i32> @smulo_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y) {
+; CHECK-LABEL: smulo_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulh.vv v28, v8, v12
+; CHECK-NEXT:    vmul.vv v8, v8, v12
+; CHECK-NEXT:    vsra.vi v12, v8, 31
+; CHECK-NEXT:    vmsne.vv v0, v28, v12
+; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 8 x i32>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y)
+  %b = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i1> } %a, 0
+  %c = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i1> } %a, 1
+  %d = select <vscale x 8 x i1> %c, <vscale x 8 x i32> zeroinitializer, <vscale x 8 x i32> %b
+  ret <vscale x 8 x i32> %d
+}
+
+declare { <vscale x 16 x i32>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
+
+define <vscale x 16 x i32> @smulo_nxv16i32(<vscale x 16 x i32> %x, <vscale x 16 x i32> %y) {
+; CHECK-LABEL: smulo_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
+; CHECK-NEXT:    vmulh.vv v24, v8, v16
+; CHECK-NEXT:    vmul.vv v8, v8, v16
+; CHECK-NEXT:    vsra.vi v16, v8, 31
+; CHECK-NEXT:    vmsne.vv v0, v24, v16
+; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 16 x i32>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i32(<vscale x 16 x i32> %x, <vscale x 16 x i32> %y)
+  %b = extractvalue { <vscale x 16 x i32>, <vscale x 16 x i1> } %a, 0
+  %c = extractvalue { <vscale x 16 x i32>, <vscale x 16 x i1> } %a, 1
+  %d = select <vscale x 16 x i1> %c, <vscale x 16 x i32> zeroinitializer, <vscale x 16 x i32> %b
+  ret <vscale x 16 x i32> %d
+}
+
+declare { <vscale x 1 x i64>, <vscale x 1 x i1> } @llvm.smul.with.overflow.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>)
+
+define <vscale x 1 x i64> @smulo_nxv1i64(<vscale x 1 x i64> %x, <vscale x 1 x i64> %y) {
+; CHECK-LABEL: smulo_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vmulh.vv v25, v8, v9
+; CHECK-NEXT:    vmul.vv v26, v8, v9
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsra.vx v27, v26, a0
+; CHECK-NEXT:    vmsne.vv v0, v25, v27
+; CHECK-NEXT:    vmerge.vim v8, v26, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 1 x i64>, <vscale x 1 x i1> } @llvm.smul.with.overflow.nxv1i64(<vscale x 1 x i64> %x, <vscale x 1 x i64> %y)
+  %b = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i1> } %a, 0
+  %c = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i1> } %a, 1
+  %d = select <vscale x 1 x i1> %c, <vscale x 1 x i64> zeroinitializer, <vscale x 1 x i64> %b
+  ret <vscale x 1 x i64> %d
+}
+
+declare { <vscale x 2 x i64>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
+
+define <vscale x 2 x i64> @smulo_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {
+; CHECK-LABEL: smulo_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT:    vmulh.vv v26, v8, v10
+; CHECK-NEXT:    vmul.vv v28, v8, v10
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsra.vx v30, v28, a0
+; CHECK-NEXT:    vmsne.vv v0, v26, v30
+; CHECK-NEXT:    vmerge.vim v8, v28, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 2 x i64>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y)
+  %b = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i1> } %a, 0
+  %c = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i1> } %a, 1
+  %d = select <vscale x 2 x i1> %c, <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i64> %b
+  ret <vscale x 2 x i64> %d
+}
+
+declare { <vscale x 4 x i64>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
+
+define <vscale x 4 x i64> @smulo_nxv4i64(<vscale x 4 x i64> %x, <vscale x 4 x i64> %y) {
+; CHECK-LABEL: smulo_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT:    vmulh.vv v28, v8, v12
+; CHECK-NEXT:    vmul.vv v8, v8, v12
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsra.vx v12, v8, a0
+; CHECK-NEXT:    vmsne.vv v0, v28, v12
+; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 4 x i64>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i64(<vscale x 4 x i64> %x, <vscale x 4 x i64> %y)
+  %b = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i1> } %a, 0
+  %c = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i1> } %a, 1
+  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i64> zeroinitializer, <vscale x 4 x i64> %b
+  ret <vscale x 4 x i64> %d
+}
+
+declare { <vscale x 8 x i64>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
+
+define <vscale x 8 x i64> @smulo_nxv8i64(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y) {
+; CHECK-LABEL: smulo_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT:    vmulh.vv v24, v8, v16
+; CHECK-NEXT:    vmul.vv v8, v8, v16
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsra.vx v16, v8, a0
+; CHECK-NEXT:    vmsne.vv v0, v24, v16
+; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 8 x i64>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i64(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y)
+  %b = extractvalue { <vscale x 8 x i64>, <vscale x 8 x i1> } %a, 0
+  %c = extractvalue { <vscale x 8 x i64>, <vscale x 8 x i1> } %a, 1
+  %d = select <vscale x 8 x i1> %c, <vscale x 8 x i64> zeroinitializer, <vscale x 8 x i64> %b
+  ret <vscale x 8 x i64> %d
+}

llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+declare { <vscale x 1 x i8>, <vscale x 1 x i1> } @llvm.umul.with.overflow.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>)
+
+define <vscale x 1 x i8> @umulo_nxv1i8(<vscale x 1 x i8> %x, <vscale x 1 x i8> %y) {
+; CHECK-LABEL: umulo_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
+; CHECK-NEXT:    vmulhu.vv v25, v8, v9
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    vmul.vv v25, v8, v9
+; CHECK-NEXT:    vmerge.vim v8, v25, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 1 x i8>, <vscale x 1 x i1> } @llvm.umul.with.overflow.nxv1i8(<vscale x 1 x i8> %x, <vscale x 1 x i8> %y)
+  %b = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i1> } %a, 0
+  %c = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i1> } %a, 1
+  %d = select <vscale x 1 x i1> %c, <vscale x 1 x i8> zeroinitializer, <vscale x 1 x i8> %b
+  ret <vscale x 1 x i8> %d
+}
+
+declare { <vscale x 2 x i8>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)
+
+define <vscale x 2 x i8> @umulo_nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y) {
+; CHECK-LABEL: umulo_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
+; CHECK-NEXT:    vmulhu.vv v25, v8, v9
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    vmul.vv v25, v8, v9
+; CHECK-NEXT:    vmerge.vim v8, v25, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 2 x i8>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y)
+  %b = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i1> } %a, 0
+  %c = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i1> } %a, 1
+  %d = select <vscale x 2 x i1> %c, <vscale x 2 x i8> zeroinitializer, <vscale x 2 x i8> %b
+  ret <vscale x 2 x i8> %d
+}
+
+declare { <vscale x 4 x i8>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
+
+define <vscale x 4 x i8> @umulo_nxv4i8(<vscale x 4 x i8> %x, <vscale x 4 x i8> %y) {
+; CHECK-LABEL: umulo_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
+; CHECK-NEXT:    vmulhu.vv v25, v8, v9
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    vmul.vv v25, v8, v9
+; CHECK-NEXT:    vmerge.vim v8, v25, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 4 x i8>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i8(<vscale x 4 x i8> %x, <vscale x 4 x i8> %y)
+  %b = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i1> } %a, 0
+  %c = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i1> } %a, 1
+  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i8> zeroinitializer, <vscale x 4 x i8> %b
+  ret <vscale x 4 x i8> %d
+}
+
+declare { <vscale x 8 x i8>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
+
+define <vscale x 8 x i8> @umulo_nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {
+; CHECK-LABEL: umulo_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
+; CHECK-NEXT:    vmulhu.vv v25, v8, v9
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    vmul.vv v25, v8, v9
+; CHECK-NEXT:    vmerge.vim v8, v25, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 8 x i8>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y)
+  %b = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i1> } %a, 0
+  %c = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i1> } %a, 1
+  %d = select <vscale x 8 x i1> %c, <vscale x 8 x i8> zeroinitializer, <vscale x 8 x i8> %b
+  ret <vscale x 8 x i8> %d
+}
+
+declare { <vscale x 16 x i8>, <vscale x 16 x i1> } @llvm.umul.with.overflow.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
+
+define <vscale x 16 x i8> @umulo_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: umulo_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
+; CHECK-NEXT:    vmulhu.vv v26, v8, v10
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    vmul.vv v26, v8, v10
+; CHECK-NEXT:    vmerge.vim v8, v26, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 16 x i8>, <vscale x 16 x i1> } @llvm.umul.with.overflow.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)
+  %b = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i1> } %a, 0
+  %c = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i1> } %a, 1
+  %d = select <vscale x 16 x i1> %c, <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8> %b
+  ret <vscale x 16 x i8> %d
+}
+
+declare { <vscale x 32 x i8>, <vscale x 32 x i1> } @llvm.umul.with.overflow.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>)
+
+define <vscale x 32 x i8> @umulo_nxv32i8(<vscale x 32 x i8> %x, <vscale x 32 x i8> %y) {
+; CHECK-LABEL: umulo_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vv v28, v8, v12
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    vmul.vv v28, v8, v12
+; CHECK-NEXT:    vmerge.vim v8, v28, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 32 x i8>, <vscale x 32 x i1> } @llvm.umul.with.overflow.nxv32i8(<vscale x 32 x i8> %x, <vscale x 32 x i8> %y)
+  %b = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i1> } %a, 0
+  %c = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i1> } %a, 1
+  %d = select <vscale x 32 x i1> %c, <vscale x 32 x i8> zeroinitializer, <vscale x 32 x i8> %b
+  ret <vscale x 32 x i8> %d
+}
+
+declare { <vscale x 64 x i8>, <vscale x 64 x i1> } @llvm.umul.with.overflow.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>)
+
+define <vscale x 64 x i8> @umulo_nxv64i8(<vscale x 64 x i8> %x, <vscale x 64 x i8> %y) {
+; CHECK-LABEL: umulo_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
+; CHECK-NEXT:    vmulhu.vv v24, v8, v16
+; CHECK-NEXT:    vmsne.vi v0, v24, 0
+; CHECK-NEXT:    vmul.vv v8, v8, v16
+; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 64 x i8>, <vscale x 64 x i1> } @llvm.umul.with.overflow.nxv64i8(<vscale x 64 x i8> %x, <vscale x 64 x i8> %y)
+  %b = extractvalue { <vscale x 64 x i8>, <vscale x 64 x i1> } %a, 0
+  %c = extractvalue { <vscale x 64 x i8>, <vscale x 64 x i1> } %a, 1
+  %d = select <vscale x 64 x i1> %c, <vscale x 64 x i8> zeroinitializer, <vscale x 64 x i8> %b
+  ret <vscale x 64 x i8> %d
+}
+
+declare { <vscale x 1 x i16>, <vscale x 1 x i1> } @llvm.umul.with.overflow.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>)
+
+define <vscale x 1 x i16> @umulo_nxv1i16(<vscale x 1 x i16> %x, <vscale x 1 x i16> %y) {
+; CHECK-LABEL: umulo_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vmulhu.vv v25, v8, v9
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    vmul.vv v25, v8, v9
+; CHECK-NEXT:    vmerge.vim v8, v25, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 1 x i16>, <vscale x 1 x i1> } @llvm.umul.with.overflow.nxv1i16(<vscale x 1 x i16> %x, <vscale x 1 x i16> %y)
+  %b = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i1> } %a, 0
+  %c = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i1> } %a, 1
+  %d = select <vscale x 1 x i1> %c, <vscale x 1 x i16> zeroinitializer, <vscale x 1 x i16> %b
+  ret <vscale x 1 x i16> %d
+}
+
+declare { <vscale x 2 x i16>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
+
+define <vscale x 2 x i16> @umulo_nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y) {
+; CHECK-LABEL: umulo_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vmulhu.vv v25, v8, v9
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    vmul.vv v25, v8, v9
+; CHECK-NEXT:    vmerge.vim v8, v25, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 2 x i16>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y)
+  %b = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i1> } %a, 0
+  %c = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i1> } %a, 1
+  %d = select <vscale x 2 x i1> %c, <vscale x 2 x i16> zeroinitializer, <vscale x 2 x i16> %b
+  ret <vscale x 2 x i16> %d
+}
+
+declare { <vscale x 4 x i16>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
+
+define <vscale x 4 x i16> @umulo_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y) {
+; CHECK-LABEL: umulo_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vmulhu.vv v25, v8, v9
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    vmul.vv v25, v8, v9
+; CHECK-NEXT:    vmerge.vim v8, v25, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 4 x i16>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y)
+  %b = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i1> } %a, 0
+  %c = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i1> } %a, 1
+  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i16> zeroinitializer, <vscale x 4 x i16> %b
+  ret <vscale x 4 x i16> %d
+}
+
+declare { <vscale x 8 x i16>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
+
+define <vscale x 8 x i16> @umulo_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: umulo_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vmulhu.vv v26, v8, v10
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    vmul.vv v26, v8, v10
+; CHECK-NEXT:    vmerge.vim v8, v26, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 8 x i16>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)
+  %b = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i1> } %a, 0
+  %c = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i1> } %a, 1
+  %d = select <vscale x 8 x i1> %c, <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i16> %b
+  ret <vscale x 8 x i16> %d
+}
+
+declare { <vscale x 16 x i16>, <vscale x 16 x i1> } @llvm.umul.with.overflow.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
+
+define <vscale x 16 x i16> @umulo_nxv16i16(<vscale x 16 x i16> %x, <vscale x 16 x i16> %y) {
+; CHECK-LABEL: umulo_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vv v28, v8, v12
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    vmul.vv v28, v8, v12
+; CHECK-NEXT:    vmerge.vim v8, v28, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 16 x i16>, <vscale x 16 x i1> } @llvm.umul.with.overflow.nxv16i16(<vscale x 16 x i16> %x, <vscale x 16 x i16> %y)
+  %b = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i1> } %a, 0
+  %c = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i1> } %a, 1
+  %d = select <vscale x 16 x i1> %c, <vscale x 16 x i16> zeroinitializer, <vscale x 16 x i16> %b
+  ret <vscale x 16 x i16> %d
+}
+
+declare { <vscale x 32 x i16>, <vscale x 32 x i1> } @llvm.umul.with.overflow.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>)
+
+define <vscale x 32 x i16> @umulo_nxv32i16(<vscale x 32 x i16> %x, <vscale x 32 x i16> %y) {
+; CHECK-LABEL: umulo_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
+; CHECK-NEXT:    vmulhu.vv v24, v8, v16
+; CHECK-NEXT:    vmsne.vi v0, v24, 0
+; CHECK-NEXT:    vmul.vv v8, v8, v16
+; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 32 x i16>, <vscale x 32 x i1> } @llvm.umul.with.overflow.nxv32i16(<vscale x 32 x i16> %x, <vscale x 32 x i16> %y)
+  %b = extractvalue { <vscale x 32 x i16>, <vscale x 32 x i1> } %a, 0
+  %c = extractvalue { <vscale x 32 x i16>, <vscale x 32 x i1> } %a, 1
+  %d = select <vscale x 32 x i1> %c, <vscale x 32 x i16> zeroinitializer, <vscale x 32 x i16> %b
+  ret <vscale x 32 x i16> %d
+}
+
+declare { <vscale x 1 x i32>, <vscale x 1 x i1> } @llvm.umul.with.overflow.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>)
+
+define <vscale x 1 x i32> @umulo_nxv1i32(<vscale x 1 x i32> %x, <vscale x 1 x i32> %y) {
+; CHECK-LABEL: umulo_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulhu.vv v25, v8, v9
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    vmul.vv v25, v8, v9
+; CHECK-NEXT:    vmerge.vim v8, v25, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 1 x i32>, <vscale x 1 x i1> } @llvm.umul.with.overflow.nxv1i32(<vscale x 1 x i32> %x, <vscale x 1 x i32> %y)
+  %b = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i1> } %a, 0
+  %c = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i1> } %a, 1
+  %d = select <vscale x 1 x i1> %c, <vscale x 1 x i32> zeroinitializer, <vscale x 1 x i32> %b
+  ret <vscale x 1 x i32> %d
+}
+
+declare { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
+
+define <vscale x 2 x i32> @umulo_nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) {
+; CHECK-LABEL: umulo_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulhu.vv v25, v8, v9
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    vmul.vv v25, v8, v9
+; CHECK-NEXT:    vmerge.vim v8, v25, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y)
+  %b = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 0
+  %c = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 1
+  %d = select <vscale x 2 x i1> %c, <vscale x 2 x i32> zeroinitializer, <vscale x 2 x i32> %b
+  ret <vscale x 2 x i32> %d
+}
+
+declare { <vscale x 4 x i32>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
+
+define <vscale x 4 x i32> @umulo_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: umulo_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulhu.vv v26, v8, v10
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    vmul.vv v26, v8, v10
+; CHECK-NEXT:    vmerge.vim v8, v26, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 4 x i32>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)
+  %b = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i1> } %a, 0
+  %c = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i1> } %a, 1
+  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> %b
+  ret <vscale x 4 x i32> %d
+}
+
+declare { <vscale x 8 x i32>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
+
+define <vscale x 8 x i32> @umulo_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y) {
+; CHECK-LABEL: umulo_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vv v28, v8, v12
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    vmul.vv v28, v8, v12
+; CHECK-NEXT:    vmerge.vim v8, v28, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 8 x i32>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y)
+  %b = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i1> } %a, 0
+  %c = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i1> } %a, 1
+  %d = select <vscale x 8 x i1> %c, <vscale x 8 x i32> zeroinitializer, <vscale x 8 x i32> %b
+  ret <vscale x 8 x i32> %d
+}
+
+declare { <vscale x 16 x i32>, <vscale x 16 x i1> } @llvm.umul.with.overflow.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
+
+define <vscale x 16 x i32> @umulo_nxv16i32(<vscale x 16 x i32> %x, <vscale x 16 x i32> %y) {
+; CHECK-LABEL: umulo_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
+; CHECK-NEXT:    vmulhu.vv v24, v8, v16
+; CHECK-NEXT:    vmsne.vi v0, v24, 0
+; CHECK-NEXT:    vmul.vv v8, v8, v16
+; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 16 x i32>, <vscale x 16 x i1> } @llvm.umul.with.overflow.nxv16i32(<vscale x 16 x i32> %x, <vscale x 16 x i32> %y)
+  %b = extractvalue { <vscale x 16 x i32>, <vscale x 16 x i1> } %a, 0
+  %c = extractvalue { <vscale x 16 x i32>, <vscale x 16 x i1> } %a, 1
+  %d = select <vscale x 16 x i1> %c, <vscale x 16 x i32> zeroinitializer, <vscale x 16 x i32> %b
+  ret <vscale x 16 x i32> %d
+}
+
+declare { <vscale x 1 x i64>, <vscale x 1 x i1> } @llvm.umul.with.overflow.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>)
+
+define <vscale x 1 x i64> @umulo_nxv1i64(<vscale x 1 x i64> %x, <vscale x 1 x i64> %y) {
+; CHECK-LABEL: umulo_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vmulhu.vv v25, v8, v9
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    vmul.vv v25, v8, v9
+; CHECK-NEXT:    vmerge.vim v8, v25, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 1 x i64>, <vscale x 1 x i1> } @llvm.umul.with.overflow.nxv1i64(<vscale x 1 x i64> %x, <vscale x 1 x i64> %y)
+  %b = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i1> } %a, 0
+  %c = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i1> } %a, 1
+  %d = select <vscale x 1 x i1> %c, <vscale x 1 x i64> zeroinitializer, <vscale x 1 x i64> %b
+  ret <vscale x 1 x i64> %d
+}
+
+declare { <vscale x 2 x i64>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
+
+define <vscale x 2 x i64> @umulo_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {
+; CHECK-LABEL: umulo_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT:    vmulhu.vv v26, v8, v10
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    vmul.vv v26, v8, v10
+; CHECK-NEXT:    vmerge.vim v8, v26, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 2 x i64>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y)
+  %b = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i1> } %a, 0
+  %c = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i1> } %a, 1
+  %d = select <vscale x 2 x i1> %c, <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i64> %b
+  ret <vscale x 2 x i64> %d
+}
+
+declare { <vscale x 4 x i64>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
+
+define <vscale x 4 x i64> @umulo_nxv4i64(<vscale x 4 x i64> %x, <vscale x 4 x i64> %y) {
+; CHECK-LABEL: umulo_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vv v28, v8, v12
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    vmul.vv v28, v8, v12
+; CHECK-NEXT:    vmerge.vim v8, v28, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 4 x i64>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i64(<vscale x 4 x i64> %x, <vscale x 4 x i64> %y)
+  %b = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i1> } %a, 0
+  %c = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i1> } %a, 1
+  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i64> zeroinitializer, <vscale x 4 x i64> %b
+  ret <vscale x 4 x i64> %d
+}
+
+declare { <vscale x 8 x i64>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
+
+define <vscale x 8 x i64> @umulo_nxv8i64(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y) {
+; CHECK-LABEL: umulo_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT:    vmulhu.vv v24, v8, v16
+; CHECK-NEXT:    vmsne.vi v0, v24, 0
+; CHECK-NEXT:    vmul.vv v8, v8, v16
+; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 8 x i64>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i64(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y)
+  %b = extractvalue { <vscale x 8 x i64>, <vscale x 8 x i1> } %a, 0
+  %c = extractvalue { <vscale x 8 x i64>, <vscale x 8 x i1> } %a, 1
+  %d = select <vscale x 8 x i1> %c, <vscale x 8 x i64> zeroinitializer, <vscale x 8 x i64> %b
+  ret <vscale x 8 x i64> %d
+}