[PowerPC] Enable track-subreg-liveness by default

[qiucf]

Summary

Enabling this option helps some MMA related cases to reduce unnecessary copies.

For ppc64-acc-regalloc-bugfix.ll, enabling this option causes failure. D108691 tries to fix it.

For pr45709.ll, the function has attribute optnone, the extra dead lfs was not moved to the bottom block. Dead machine instruction eliminator removes it when optnone disabled.

[shchenz]

Thanks for doing this. Could you please show some data about the performance and compile time? Hope they are both good.

[qiucf]

In D108902#3993706, @shchenz wrote:

Thanks for doing this. Could you please show some data about the performance and compile time? Hope they are both good.

I have not observed build/run performance changes through test suite. Since ISA 3.1 functionalities enhanced by this are not available through optimization, this is expected.

[shchenz]

OK. Thanks for testing. Even though there is no improvement in the test suite, the LIT case changes show good improvement about COPY removal and register allocation. So this makes sense to me.

Please wait for some days in case @nemanjai has comments.

llvm/test/CodeGen/PowerPC/pr45709.ll

43

This may be caused by undef, I can not see any store to the same stack slot before? And the f0 is a dead def, so I think this patch just exposes some dead def removal opportunity after eliminating some copy? It is good if we can improve this in following patch.

llvm/lib/Target/PowerPC/PPCSubtarget.cpp

 using namespace llvm;
 
 #define DEBUG_TYPE "ppc-subtarget"
 
 #define GET_SUBTARGETINFO_TARGET_DESC
 #define GET_SUBTARGETINFO_CTOR
 #include "PPCGenSubtargetInfo.inc"
 
-static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
-cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
+static cl::opt<bool>
+    UseSubRegLiveness("ppc-track-subreg-liveness",
+                      cl::desc("Enable subregister liveness tracking for PPC"),
+                      cl::init(true), cl::Hidden);
 
 static cl::opt<bool>
     EnableMachinePipeliner("ppc-enable-pipeliner",
                            cl::desc("Enable Machine Pipeliner for PPC"),
                            cl::init(false), cl::Hidden);
 
 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                             StringRef FS) {

llvm/test/CodeGen/PowerPC/all-atomics.ll

 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lqarx 20, 0, 23
 ; CHECK-NEXT:    nand 19, 25, 21
 ; CHECK-NEXT:    nand 18, 22, 20
 ; CHECK-NEXT:    stqcx. 18, 0, 23
 ; CHECK-NEXT:    bne 0, .LBB2_81
 ; CHECK-NEXT:  # %bb.82: # %entry
 ; CHECK-NEXT:    lwsync
+; CHECK-NEXT:    lbz 20, uc@toc@l(3)
 ; CHECK-NEXT:    nand 25, 21, 25
 ; CHECK-NEXT:    li 21, -1
-; CHECK-NEXT:    lbz 20, uc@toc@l(3)
 ; CHECK-NEXT:    std 21, 8(23)
 ; CHECK-NEXT:    std 25, u128@toc@l(24)
 ; CHECK-NEXT:    addis 25, 2, s128@toc@ha
 ; CHECK-NEXT:    sync
 ; CHECK-NEXT:    addi 24, 25, s128@toc@l
 ; CHECK-NEXT:  .LBB2_83: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lqarx 18, 0, 24

llvm/test/CodeGen/PowerPC/crbits.ll

 define zeroext i1 @test1(float %v1, float %v2) #0 {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxlxor 0, 0, 0
 ; CHECK-NEXT:    fcmpu 0, 1, 2
 ; CHECK-NEXT:    li 3, 1
 ; CHECK-NEXT:    fcmpu 5, 2, 2
 ; CHECK-NEXT:    fcmpu 1, 2, 0
-; CHECK-NEXT:    crnor 24, 3, 0
-; CHECK-NEXT:    crnor 20, 23, 5
-; CHECK-NEXT:    crnand 20, 24, 20
+; CHECK-NEXT:    crnor 20, 3, 0
+; CHECK-NEXT:    crnor 21, 23, 5
+; CHECK-NEXT:    crnand 20, 20, 21
 ; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: test1:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    xxlxor 0, 0, 0
 ; CHECK-NO-ISEL-NEXT:    fcmpu 0, 1, 2
 ; CHECK-NO-ISEL-NEXT:    li 3, 1
 ; CHECK-NO-ISEL-NEXT:    fcmpu 5, 2, 2
 ; CHECK-NO-ISEL-NEXT:    fcmpu 1, 2, 0
-; CHECK-NO-ISEL-NEXT:    crnor 24, 3, 0
-; CHECK-NO-ISEL-NEXT:    crnor 20, 23, 5
-; CHECK-NO-ISEL-NEXT:    crnand 20, 24, 20
+; CHECK-NO-ISEL-NEXT:    crnor 20, 3, 0
+; CHECK-NO-ISEL-NEXT:    crnor 21, 23, 5
+; CHECK-NO-ISEL-NEXT:    crnand 20, 20, 21
 ; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB0_1
 ; CHECK-NO-ISEL-NEXT:    blr
 ; CHECK-NO-ISEL-NEXT:  .LBB0_1: # %entry
 ; CHECK-NO-ISEL-NEXT:    li 3, 0
 ; CHECK-NO-ISEL-NEXT:    blr
 ;
 ; CHECK-P10-LABEL: test1:
 ; CHECK-P10:       # %bb.0: # %entry

 define zeroext i1 @test2(float %v1, float %v2) #0 {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxlxor 0, 0, 0
 ; CHECK-NEXT:    fcmpu 0, 1, 2
 ; CHECK-NEXT:    li 3, 1
 ; CHECK-NEXT:    fcmpu 5, 2, 2
 ; CHECK-NEXT:    fcmpu 1, 2, 0
-; CHECK-NEXT:    crnor 24, 3, 0
-; CHECK-NEXT:    crnor 20, 23, 5
-; CHECK-NEXT:    creqv 20, 24, 20
+; CHECK-NEXT:    crnor 20, 3, 0
+; CHECK-NEXT:    crnor 21, 23, 5
+; CHECK-NEXT:    creqv 20, 20, 21
 ; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: test2:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    xxlxor 0, 0, 0
 ; CHECK-NO-ISEL-NEXT:    fcmpu 0, 1, 2
 ; CHECK-NO-ISEL-NEXT:    li 3, 1
 ; CHECK-NO-ISEL-NEXT:    fcmpu 5, 2, 2
 ; CHECK-NO-ISEL-NEXT:    fcmpu 1, 2, 0
-; CHECK-NO-ISEL-NEXT:    crnor 24, 3, 0
-; CHECK-NO-ISEL-NEXT:    crnor 20, 23, 5
-; CHECK-NO-ISEL-NEXT:    creqv 20, 24, 20
+; CHECK-NO-ISEL-NEXT:    crnor 20, 3, 0
+; CHECK-NO-ISEL-NEXT:    crnor 21, 23, 5
+; CHECK-NO-ISEL-NEXT:    creqv 20, 20, 21
 ; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB1_1
 ; CHECK-NO-ISEL-NEXT:    blr
 ; CHECK-NO-ISEL-NEXT:  .LBB1_1: # %entry
 ; CHECK-NO-ISEL-NEXT:    li 3, 0
 ; CHECK-NO-ISEL-NEXT:    blr
 ;
 ; CHECK-P10-LABEL: test2:
 ; CHECK-P10:       # %bb.0: # %entry

 ; CHECK-LABEL: test3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxlxor 0, 0, 0
 ; CHECK-NEXT:    fcmpu 0, 2, 2
 ; CHECK-NEXT:    li 3, 1
 ; CHECK-NEXT:    fcmpu 5, 1, 2
 ; CHECK-NEXT:    fcmpu 1, 2, 0
 ; CHECK-NEXT:    crnor 20, 23, 20
-; CHECK-NEXT:    crnor 24, 3, 5
+; CHECK-NEXT:    crnor 21, 3, 5
 ; CHECK-NEXT:    cmpwi 5, -2
-; CHECK-NEXT:    crandc 21, 24, 2
+; CHECK-NEXT:    crandc 21, 21, 2
 ; CHECK-NEXT:    creqv 20, 20, 21
 ; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: test3:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    xxlxor 0, 0, 0
 ; CHECK-NO-ISEL-NEXT:    fcmpu 0, 2, 2
 ; CHECK-NO-ISEL-NEXT:    li 3, 1
 ; CHECK-NO-ISEL-NEXT:    fcmpu 5, 1, 2
 ; CHECK-NO-ISEL-NEXT:    fcmpu 1, 2, 0
 ; CHECK-NO-ISEL-NEXT:    crnor 20, 23, 20
-; CHECK-NO-ISEL-NEXT:    crnor 24, 3, 5
+; CHECK-NO-ISEL-NEXT:    crnor 21, 3, 5
 ; CHECK-NO-ISEL-NEXT:    cmpwi 5, -2
-; CHECK-NO-ISEL-NEXT:    crandc 21, 24, 2
+; CHECK-NO-ISEL-NEXT:    crandc 21, 21, 2
 ; CHECK-NO-ISEL-NEXT:    creqv 20, 20, 21
 ; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB2_1
 ; CHECK-NO-ISEL-NEXT:    blr
 ; CHECK-NO-ISEL-NEXT:  .LBB2_1: # %entry
 ; CHECK-NO-ISEL-NEXT:    li 3, 0
 ; CHECK-NO-ISEL-NEXT:    blr
 ;
 ; CHECK-P10-LABEL: test3:

llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll

 define i32 @test_f64_oge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; SPE-LABEL: test_f64_oge_s:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    evmergelo r5, r5, r6
 ; SPE-NEXT:    evmergelo r6, r7, r8
 ; SPE-NEXT:    efdcmpeq cr0, r6, r6
 ; SPE-NEXT:    efdcmpeq cr1, r5, r5
 ; SPE-NEXT:    efdcmplt cr5, r5, r6
-; SPE-NEXT:    crand 4*cr6+lt, 4*cr1+gt, gt
-; SPE-NEXT:    crandc 4*cr5+lt, 4*cr6+lt, 4*cr5+gt
+; SPE-NEXT:    crand 4*cr5+lt, 4*cr1+gt, gt
+; SPE-NEXT:    crandc 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"oge", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }

 define i32 @test_f64_ole_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; SPE-LABEL: test_f64_ole_s:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    evmergelo r5, r5, r6
 ; SPE-NEXT:    evmergelo r6, r7, r8
 ; SPE-NEXT:    efdcmpeq cr0, r6, r6
 ; SPE-NEXT:    efdcmpeq cr1, r5, r5
 ; SPE-NEXT:    efdcmpgt cr5, r5, r6
-; SPE-NEXT:    crand 4*cr6+lt, 4*cr1+gt, gt
-; SPE-NEXT:    crandc 4*cr5+lt, 4*cr6+lt, 4*cr5+gt
+; SPE-NEXT:    crand 4*cr5+lt, 4*cr1+gt, gt
+; SPE-NEXT:    crandc 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ole", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }

 define i32 @test_f64_ugt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; SPE-LABEL: test_f64_ugt_s:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    evmergelo r7, r7, r8
 ; SPE-NEXT:    evmergelo r5, r5, r6
 ; SPE-NEXT:    efdcmpeq cr0, r5, r5
 ; SPE-NEXT:    efdcmpeq cr1, r7, r7
 ; SPE-NEXT:    efdcmpgt cr5, r5, r7
-; SPE-NEXT:    crnand 4*cr6+lt, 4*cr1+gt, gt
-; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr6+lt
+; SPE-NEXT:    crnand 4*cr5+lt, 4*cr1+gt, gt
+; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ugt", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }

 define i32 @test_f64_ult_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; SPE-LABEL: test_f64_ult_s:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    evmergelo r7, r7, r8
 ; SPE-NEXT:    evmergelo r5, r5, r6
 ; SPE-NEXT:    efdcmpeq cr0, r5, r5
 ; SPE-NEXT:    efdcmpeq cr1, r7, r7
 ; SPE-NEXT:    efdcmplt cr5, r5, r7
-; SPE-NEXT:    crnand 4*cr6+lt, 4*cr1+gt, gt
-; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr6+lt
+; SPE-NEXT:    crnand 4*cr5+lt, 4*cr1+gt, gt
+; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ult", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }

llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll

 ; CHECK-NEXT:    lxv v31, 0(r3)
 ; CHECK-NEXT:    lxv v30, 0(r4)
 ; CHECK-NEXT:    addi r3, r1, 32
 ; CHECK-NEXT:    vmr v2, v31
 ; CHECK-NEXT:    vmr v3, v30
 ; CHECK-NEXT:    std r29, -24(r30) # 8-byte Folded Spill
 ; CHECK-NEXT:    mr r29, r5
 ; CHECK-NEXT:    bl _Z15buildVectorPairPu13__vector_pairDv16_hS0_@notoc
-; CHECK-NEXT:    xxsetaccz acc1
-; CHECK-NEXT:    xvf32gerpp acc1, v31, v30
+; CHECK-NEXT:    xxsetaccz acc0
+; CHECK-NEXT:    xvf32gerpp acc0, v31, v30
 ; CHECK-NEXT:    lxv v3, 32(r1)
 ; CHECK-NEXT:    lxv v2, 48(r1)
-; CHECK-NEXT:    xvf32gerpp acc1, v3, v2
-; CHECK-NEXT:    xxmfacc acc1
-; CHECK-NEXT:    xxlor vs0, vs4, vs4
-; CHECK-NEXT:    xxlor vs1, vs5, vs5
-; CHECK-NEXT:    xxlor vs2, vs6, vs6
-; CHECK-NEXT:    xxlor vs3, vs7, vs7
+; CHECK-NEXT:    xvf32gerpp acc0, v3, v2
 ; CHECK-NEXT:    lxv v31, -48(r30) # 16-byte Folded Reload
 ; CHECK-NEXT:    lxv v30, -64(r30) # 16-byte Folded Reload
+; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs3, 0(r29)
 ; CHECK-NEXT:    pstxv vs2, 8(r29), 0
 ; CHECK-NEXT:    stxv vs1, 16(r29)
 ; CHECK-NEXT:    pstxv vs0, 24(r29), 0
 ; CHECK-NEXT:    ld r29, -24(r30) # 8-byte Folded Reload
 ; CHECK-NEXT:    mr r1, r30
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    ld r30, -16(r1)

 ; CHECK-BE-NEXT:    mr r29, r5
 ; CHECK-BE-NEXT:    bl _Z15buildVectorPairPu13__vector_pairDv16_hS0_
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:    xxsetaccz acc1
 ; CHECK-BE-NEXT:    xvf32gerpp acc1, v31, v30
 ; CHECK-BE-NEXT:    lxv v3, 144(r1)
 ; CHECK-BE-NEXT:    lxv v2, 128(r1)
 ; CHECK-BE-NEXT:    xvf32gerpp acc1, v2, v3
+; CHECK-BE-NEXT:    lxv v31, -48(r30) # 16-byte Folded Reload
+; CHECK-BE-NEXT:    lxv v30, -64(r30) # 16-byte Folded Reload
 ; CHECK-BE-NEXT:    xxmfacc acc1
 ; CHECK-BE-NEXT:    xxlor vs1, vs6, vs6
 ; CHECK-BE-NEXT:    xxlor vs0, vs7, vs7
 ; CHECK-BE-NEXT:    xxlor vs3, vs4, vs4
 ; CHECK-BE-NEXT:    xxlor vs2, vs5, vs5
-; CHECK-BE-NEXT:    lxv v31, -48(r30) # 16-byte Folded Reload
-; CHECK-BE-NEXT:    lxv v30, -64(r30) # 16-byte Folded Reload
 ; CHECK-BE-NEXT:    stxv vs0, 0(r29)
 ; CHECK-BE-NEXT:    pstxv vs1, 8(r29), 0
 ; CHECK-BE-NEXT:    stxv vs2, 16(r29)
 ; CHECK-BE-NEXT:    pstxv vs3, 24(r29), 0
 ; CHECK-BE-NEXT:    ld r29, -24(r30) # 8-byte Folded Reload
 ; CHECK-BE-NEXT:    mr r1, r30
 ; CHECK-BE-NEXT:    ld r0, 16(r1)
 ; CHECK-BE-NEXT:    ld r30, -16(r1)

llvm/test/CodeGen/PowerPC/mma-acc-memops.ll

entry:
   ret void
 }
 
 define dso_local void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) {
 ; LE-PAIRED-LABEL: testLdStPair:
 ; LE-PAIRED:       # %bb.0: # %entry
 ; LE-PAIRED-NEXT:    plxv v3, g@PCREL+32(0), 1
 ; LE-PAIRED-NEXT:    plxv v2, g@PCREL+48(0), 1
-; LE-PAIRED-NEXT:    pstxv v3, g@PCREL+64(0), 1
 ; LE-PAIRED-NEXT:    pstxv v2, g@PCREL+80(0), 1
+; LE-PAIRED-NEXT:    pstxv v3, g@PCREL+64(0), 1
 ; LE-PAIRED-NEXT:    blr
 ;
 ; BE-PAIRED-LABEL: testLdStPair:
 ; BE-PAIRED:       # %bb.0: # %entry
 ; BE-PAIRED-NEXT:    addis r3, r2, g@toc@ha
 ; BE-PAIRED-NEXT:    addi r3, r3, g@toc@l
 ; BE-PAIRED-NEXT:    lxv v3, 48(r3)
 ; BE-PAIRED-NEXT:    lxv v2, 32(r3)
entry:
   ret void
 }
 
 define dso_local void @testUnalignedLdStPair() {
 ; LE-PAIRED-LABEL: testUnalignedLdStPair:
 ; LE-PAIRED:       # %bb.0: # %entry
 ; LE-PAIRED-NEXT:    plxv v3, g@PCREL+11(0), 1
 ; LE-PAIRED-NEXT:    plxv v2, g@PCREL+27(0), 1
-; LE-PAIRED-NEXT:    pstxv v3, g@PCREL+19(0), 1
 ; LE-PAIRED-NEXT:    pstxv v2, g@PCREL+35(0), 1
+; LE-PAIRED-NEXT:    pstxv v3, g@PCREL+19(0), 1
 ; LE-PAIRED-NEXT:    blr
 ;
 ; BE-PAIRED-LABEL: testUnalignedLdStPair:
 ; BE-PAIRED:       # %bb.0: # %entry
 ; BE-PAIRED-NEXT:    addis r3, r2, g@toc@ha
 ; BE-PAIRED-NEXT:    addi r3, r3, g@toc@l
 ; BE-PAIRED-NEXT:    plxv v3, 27(r3), 0
 ; BE-PAIRED-NEXT:    plxv v2, 11(r3), 0

llvm/test/CodeGen/PowerPC/mma-acc-spill.ll

 ; CHECK-NEXT:    stxv v29, 112(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    vmr v29, v3
 ; CHECK-NEXT:    vmr v28, v2
 ; CHECK-NEXT:    xxlor vs0, v28, v28
 ; CHECK-NEXT:    stxv v30, 128(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    stxv v31, 144(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    vmr v31, v5
 ; CHECK-NEXT:    vmr v30, v4
-; CHECK-NEXT:    std r30, 160(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    xxlor vs1, v29, v29
 ; CHECK-NEXT:    xxlor vs2, v30, v30
 ; CHECK-NEXT:    xxlor vs3, v31, v31
+; CHECK-NEXT:    std r30, 160(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    ld r30, 272(r1)
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    xvf16ger2pp acc0, v2, v4
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxvp vsp0, 64(r1)
 ; CHECK-NEXT:    stxvp vsp2, 32(r1)
 ; CHECK-NEXT:    bl foo@notoc
 ; CHECK-NEXT:    lxvp vsp0, 64(r1)

 ; CHECK-BE-NEXT:    stxv v29, 192(r1) # 16-byte Folded Spill
 ; CHECK-BE-NEXT:    vmr v29, v3
 ; CHECK-BE-NEXT:    vmr v28, v2
 ; CHECK-BE-NEXT:    xxlor vs0, v28, v28
 ; CHECK-BE-NEXT:    stxv v30, 208(r1) # 16-byte Folded Spill
 ; CHECK-BE-NEXT:    stxv v31, 224(r1) # 16-byte Folded Spill
 ; CHECK-BE-NEXT:    vmr v31, v5
 ; CHECK-BE-NEXT:    vmr v30, v4
-; CHECK-BE-NEXT:    std r30, 240(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    xxlor vs1, v29, v29
 ; CHECK-BE-NEXT:    xxlor vs2, v30, v30
 ; CHECK-BE-NEXT:    xxlor vs3, v31, v31
+; CHECK-BE-NEXT:    std r30, 240(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    ld r30, 368(r1)
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    xvf16ger2pp acc0, v2, v4
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxvp vsp0, 112(r1)
 ; CHECK-BE-NEXT:    stxvp vsp2, 144(r1)
 ; CHECK-BE-NEXT:    bl foo
 ; CHECK-BE-NEXT:    nop

llvm/test/CodeGen/PowerPC/mma-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names \
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names \
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
 
 ; assemble_acc
 declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
 define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: ass_acc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmr v3, v2
-; CHECK-NEXT:    xxlor vs0, v2, v2
-; CHECK-NEXT:    xxlor vs1, v3, v3
+; CHECK-NEXT:    xxlor vs3, v2, v2
 ; CHECK-NEXT:    xxlor vs2, v2, v2
-; CHECK-NEXT:    xxlor vs3, v3, v3
+; CHECK-NEXT:    xxlor vs0, vs2, vs2
+; CHECK-NEXT:    xxlor vs1, vs3, vs3
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
 ; CHECK-NEXT:    stxv vs2, 16(r3)
 ; CHECK-NEXT:    stxv vs3, 0(r3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: ass_acc:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vmr v3, v2
-; CHECK-BE-NEXT:    xxlor vs0, v2, v2
-; CHECK-BE-NEXT:    xxlor vs1, v3, v3
+; CHECK-BE-NEXT:    xxlor vs3, v2, v2
 ; CHECK-BE-NEXT:    xxlor vs2, v2, v2
-; CHECK-BE-NEXT:    xxlor vs3, v3, v3
+; CHECK-BE-NEXT:    xxlor vs0, vs2, vs2
+; CHECK-BE-NEXT:    xxlor vs1, vs3, vs3
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
   store <512 x i1> %0, ptr %ptr, align 64
   ret void
 }
 
 ; xxmtacc
 declare <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1>)
 define void @int_xxmtacc(ptr %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: int_xxmtacc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmr v3, v2
-; CHECK-NEXT:    xxlor vs0, v2, v2
-; CHECK-NEXT:    xxlor vs1, v3, v3
+; CHECK-NEXT:    xxlor vs3, v2, v2
 ; CHECK-NEXT:    xxlor vs2, v2, v2
-; CHECK-NEXT:    xxlor vs3, v3, v3
+; CHECK-NEXT:    xxlor vs0, vs2, vs2
+; CHECK-NEXT:    xxlor vs1, vs3, vs3
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
 ; CHECK-NEXT:    stxv vs2, 16(r3)
 ; CHECK-NEXT:    stxv vs3, 0(r3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: int_xxmtacc:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vmr v3, v2
-; CHECK-BE-NEXT:    xxlor vs0, v2, v2
-; CHECK-BE-NEXT:    xxlor vs1, v3, v3
+; CHECK-BE-NEXT:    xxlor vs3, v2, v2
 ; CHECK-BE-NEXT:    xxlor vs2, v2, v2
-; CHECK-BE-NEXT:    xxlor vs3, v3, v3
+; CHECK-BE-NEXT:    xxlor vs0, vs2, vs2
+; CHECK-BE-NEXT:    xxlor vs1, vs3, vs3
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
 ; One xxmtacc is generated from the call to assemble.acc then one xxmtacc is
 ; generated from the call to xxmtacc then one xxmfacc is generated for the store
   %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
   %1 = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> %0)
   store <512 x i1> %1, ptr %ptr, align 64
   ret void
 }
 
 ; xxmfacc
 declare <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1>)
 define void @int_xxmfacc(ptr %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: int_xxmfacc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmr v3, v2
-; CHECK-NEXT:    xxlor vs0, v2, v2
-; CHECK-NEXT:    xxlor vs1, v3, v3
+; CHECK-NEXT:    xxlor vs3, v2, v2
 ; CHECK-NEXT:    xxlor vs2, v2, v2
-; CHECK-NEXT:    xxlor vs3, v3, v3
+; CHECK-NEXT:    xxlor vs0, vs2, vs2
+; CHECK-NEXT:    xxlor vs1, vs3, vs3
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
 ; CHECK-NEXT:    stxv vs2, 16(r3)
 ; CHECK-NEXT:    stxv vs3, 0(r3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: int_xxmfacc:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vmr v3, v2
-; CHECK-BE-NEXT:    xxlor vs0, v2, v2
-; CHECK-BE-NEXT:    xxlor vs1, v3, v3
+; CHECK-BE-NEXT:    xxlor vs3, v2, v2
 ; CHECK-BE-NEXT:    xxlor vs2, v2, v2
-; CHECK-BE-NEXT:    xxlor vs3, v3, v3
+; CHECK-BE-NEXT:    xxlor vs0, vs2, vs2
+; CHECK-BE-NEXT:    xxlor vs1, vs3, vs3
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
 ; One xxmtacc is generated from the call to assemble.acc then one xxmfacc is
 ; generated from the call to xxmfacc then one xxmfacc is generated for the store

llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll

 ; CHECK-NEXT:    .cfi_offset v29, -64
 ; CHECK-NEXT:    .cfi_offset v30, -48
 ; CHECK-NEXT:    .cfi_offset v31, -32
 ; CHECK-NEXT:    stxv v28, 96(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    stxv v29, 112(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    stxv v30, 128(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    stxv v31, 144(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    vmr v31, v5
-; CHECK-NEXT:    vmr v30, v4
 ; CHECK-NEXT:    vmr v29, v3
+; CHECK-NEXT:    vmr v30, v4
 ; CHECK-NEXT:    vmr v28, v2
 ; CHECK-NEXT:    std r30, 160(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    ld r30, 272(r1)
 ; CHECK-NEXT:    dmxxinstfdmr512 wacc0, vsp60, vsp62, 0
 ; CHECK-NEXT:    xvf16ger2pp wacc0, v2, v4
 ; CHECK-NEXT:    dmxxextfdmr512 wacc0, vsp36, vsp34, 0
 ; CHECK-NEXT:    stxvp vsp36, 64(r1)
 ; CHECK-NEXT:    stxvp vsp34, 32(r1)

 ; CHECK-BE-NEXT:    .cfi_offset v29, -64
 ; CHECK-BE-NEXT:    .cfi_offset v30, -48
 ; CHECK-BE-NEXT:    .cfi_offset v31, -32
 ; CHECK-BE-NEXT:    stxv v28, 176(r1) # 16-byte Folded Spill
 ; CHECK-BE-NEXT:    stxv v29, 192(r1) # 16-byte Folded Spill
 ; CHECK-BE-NEXT:    stxv v30, 208(r1) # 16-byte Folded Spill
 ; CHECK-BE-NEXT:    stxv v31, 224(r1) # 16-byte Folded Spill
 ; CHECK-BE-NEXT:    vmr v31, v5
-; CHECK-BE-NEXT:    vmr v30, v4
 ; CHECK-BE-NEXT:    vmr v29, v3
+; CHECK-BE-NEXT:    vmr v30, v4
 ; CHECK-BE-NEXT:    vmr v28, v2
 ; CHECK-BE-NEXT:    std r30, 240(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    ld r30, 368(r1)
 ; CHECK-BE-NEXT:    dmxxinstfdmr512 wacc0, vsp60, vsp62, 0
 ; CHECK-BE-NEXT:    xvf16ger2pp wacc0, v2, v4
 ; CHECK-BE-NEXT:    dmxxextfdmr512 wacc0, vsp36, vsp34, 0
 ; CHECK-BE-NEXT:    stxvp vsp36, 112(r1)
 ; CHECK-BE-NEXT:    stxvp vsp34, 144(r1)

llvm/test/CodeGen/PowerPC/p10-spill-creq.ll

 define dso_local double @P10_Spill_CR_EQ(ptr %arg) local_unnamed_addr #0 {
 ; CHECK-LABEL: P10_Spill_CR_EQ:
 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    mfcr r12
 ; CHECK-NEXT:    stw r12, 8(r1)
 ; CHECK-NEXT:    ld r3, 0(r3)
 ; CHECK-NEXT:    ld r4, 0(0)
 ; CHECK-NEXT:    ld r5, 56(0)
-; CHECK-NEXT:    cmpdi cr1, r3, 0
-; CHECK-NEXT:    cmpdi cr4, r4, 0
-; CHECK-NEXT:    cmpdi cr6, r5, 0
-; CHECK-NEXT:    cmpldi r3, 0
-; CHECK-NEXT:    beq cr0, .LBB0_3
+; CHECK-NEXT:    cmpdi r3, 0
+; CHECK-NEXT:    cmpdi cr1, r4, 0
+; CHECK-NEXT:    cmpdi cr5, r5, 0
+; CHECK-NEXT:    cmpldi cr6, r3, 0
+; CHECK-NEXT:    beq cr6, .LBB0_3
 ; CHECK-NEXT:  # %bb.1: # %bb10
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    bc 12, 4*cr4+eq, .LBB0_4
+; CHECK-NEXT:    bc 12, 4*cr1+eq, .LBB0_4
 ; CHECK-NEXT:  .LBB0_2: # %bb14
 ; CHECK-NEXT:    lwz r5, 0(r3)
 ; CHECK-NEXT:    b .LBB0_5
 ; CHECK-NEXT:  .LBB0_3:
 ; CHECK-NEXT:    # implicit-def: $r3
-; CHECK-NEXT:    bc 4, 4*cr4+eq, .LBB0_2
+; CHECK-NEXT:    bc 4, 4*cr1+eq, .LBB0_2
 ; CHECK-NEXT:  .LBB0_4:
 ; CHECK-NEXT:    # implicit-def: $r5
 ; CHECK-NEXT:  .LBB0_5: # %bb16
-; CHECK-NEXT:    mfocrf r4, 64
-; CHECK-NEXT:    crnot 4*cr2+un, 4*cr1+eq
-; CHECK-NEXT:    crnot 4*cr5+lt, 4*cr6+eq
-; CHECK-NEXT:    rotlwi r4, r4, 4
-; CHECK-NEXT:    stw r4, -4(r1)
-; CHECK-NEXT:    bc 12, 4*cr6+eq, .LBB0_7
+; CHECK-NEXT:    crnot 4*cr1+lt, eq
+; CHECK-NEXT:    crnot 4*cr5+un, 4*cr5+eq
+; CHECK-NEXT:    bc 12, 4*cr5+eq, .LBB0_7
 ; CHECK-NEXT:  # %bb.6: # %bb18
 ; CHECK-NEXT:    lwz r4, 0(r3)
 ; CHECK-NEXT:    b .LBB0_8
 ; CHECK-NEXT:  .LBB0_7:
 ; CHECK-NEXT:    # implicit-def: $r4
 ; CHECK-NEXT:  .LBB0_8: # %bb20
-; CHECK-NEXT:    cmpwi r3, -1
+; CHECK-NEXT:    cmpwi cr2, r3, -1
 ; CHECK-NEXT:    cmpwi cr3, r4, -1
 ; CHECK-NEXT:    cmpwi cr7, r3, 0
-; CHECK-NEXT:    cmpwi cr1, r4, 0
+; CHECK-NEXT:    cmpwi cr6, r4, 0
 ; CHECK-NEXT:    # implicit-def: $x3
-; CHECK-NEXT:    crand 4*cr5+eq, gt, 4*cr2+un
-; CHECK-NEXT:    crand 4*cr5+gt, 4*cr3+gt, 4*cr5+lt
-; CHECK-NEXT:    setnbc r4, 4*cr5+eq
-; CHECK-NEXT:    stw r4, -20(r1)
-; CHECK-NEXT:    bc 4, 4*cr5+eq, .LBB0_10
+; CHECK-NEXT:    crand 4*cr5+gt, 4*cr2+gt, 4*cr1+lt
+; CHECK-NEXT:    crand 4*cr5+lt, 4*cr3+gt, 4*cr5+un
+; CHECK-NEXT:    bc 4, 4*cr5+gt, .LBB0_10
 ; CHECK-NEXT:  # %bb.9: # %bb34
 ; CHECK-NEXT:    ld r3, 0(r3)
 ; CHECK-NEXT:  .LBB0_10: # %bb36
-; CHECK-NEXT:    mfocrf r4, 2
-; CHECK-NEXT:    cmpwi cr3, r5, 0
-; CHECK-NEXT:    rotlwi r4, r4, 24
-; CHECK-NEXT:    stw r4, -12(r1)
+; CHECK-NEXT:    cmpwi cr2, r5, 0
 ; CHECK-NEXT:    # implicit-def: $x4
-; CHECK-NEXT:    bc 4, 4*cr5+gt, .LBB0_12
+; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_12
 ; CHECK-NEXT:  # %bb.11: # %bb38
 ; CHECK-NEXT:    ld r4, 0(r3)
 ; CHECK-NEXT:  .LBB0_12: # %bb40
-; CHECK-NEXT:    mcrf cr6, cr4
-; CHECK-NEXT:    crnot 4*cr4+eq, 4*cr4+eq
-; CHECK-NEXT:    crand 4*cr4+gt, 4*cr7+lt, 4*cr2+un
-; CHECK-NEXT:    crand 4*cr4+lt, 4*cr1+lt, 4*cr5+lt
+; CHECK-NEXT:    crand 4*cr6+gt, 4*cr7+lt, 4*cr1+lt
+; CHECK-NEXT:    crand 4*cr6+lt, 4*cr6+lt, 4*cr5+un
+; CHECK-NEXT:    crnot 4*cr6+un, 4*cr1+eq
 ; CHECK-NEXT:    # implicit-def: $x6
-; CHECK-NEXT:    bc 4, 4*cr4+lt, .LBB0_14
+; CHECK-NEXT:    bc 4, 4*cr6+lt, .LBB0_14
 ; CHECK-NEXT:  # %bb.13: # %bb48
 ; CHECK-NEXT:    ld r6, 0(r3)
 ; CHECK-NEXT:  .LBB0_14: # %bb50
-; CHECK-NEXT:    cmpwi r5, -1
-; CHECK-NEXT:    crand 4*cr4+un, 4*cr3+lt, 4*cr4+eq
+; CHECK-NEXT:    cmpwi cr3, r5, -1
+; CHECK-NEXT:    crand 4*cr7+lt, 4*cr2+lt, 4*cr6+un
 ; CHECK-NEXT:    # implicit-def: $r5
-; CHECK-NEXT:    bc 4, 4*cr4+gt, .LBB0_16
+; CHECK-NEXT:    bc 4, 4*cr6+gt, .LBB0_16
 ; CHECK-NEXT:  # %bb.15: # %bb52
 ; CHECK-NEXT:    lwz r5, 0(r3)
 ; CHECK-NEXT:  .LBB0_16: # %bb54
-; CHECK-NEXT:    setnbc r7, 4*cr5+gt
-; CHECK-NEXT:    stw r7, -16(r1)
-; CHECK-NEXT:    mfocrf r7, 2
-; CHECK-NEXT:    rotlwi r7, r7, 24
-; CHECK-NEXT:    stw r7, -8(r1)
+; CHECK-NEXT:    mfocrf r7, 128
+; CHECK-NEXT:    stw r7, -4(r1)
 ; CHECK-NEXT:    # implicit-def: $r7
-; CHECK-NEXT:    bc 4, 4*cr4+un, .LBB0_18
+; CHECK-NEXT:    bc 4, 4*cr7+lt, .LBB0_18
 ; CHECK-NEXT:  # %bb.17: # %bb56
 ; CHECK-NEXT:    lwz r7, 0(r3)
 ; CHECK-NEXT:  .LBB0_18: # %bb58
-; CHECK-NEXT:    crand 4*cr5+gt, 4*cr7+eq, 4*cr2+un
-; CHECK-NEXT:    mcrf cr2, cr1
-; CHECK-NEXT:    cmpwi cr1, r5, 1
-; CHECK-NEXT:    crand lt, gt, 4*cr4+eq
-; CHECK-NEXT:    # implicit-def: $x5
-; CHECK-NEXT:    crand 4*cr4+eq, 4*cr3+eq, 4*cr4+eq
-; CHECK-NEXT:    setnbc r8, 4*cr5+gt
-; CHECK-NEXT:    crand 4*cr5+lt, 4*cr2+eq, 4*cr5+lt
-; CHECK-NEXT:    crand gt, 4*cr1+lt, 4*cr4+gt
-; CHECK-NEXT:    stw r8, -24(r1)
-; CHECK-NEXT:    setnbc r8, 4*cr5+lt
-; CHECK-NEXT:    cmpwi cr5, r7, 1
-; CHECK-NEXT:    stw r8, -28(r1)
-; CHECK-NEXT:    crand eq, 4*cr5+lt, 4*cr4+un
 ; CHECK-NEXT:    lwz r6, 92(r6)
-; CHECK-NEXT:    cmpwi cr6, r6, 1
-; CHECK-NEXT:    crand un, 4*cr6+lt, 4*cr4+lt
-; CHECK-NEXT:    bc 4, gt, .LBB0_20
+; CHECK-NEXT:    crand 4*cr7+un, 4*cr3+gt, 4*cr6+un
+; CHECK-NEXT:    cmpwi cr3, r5, 1
+; CHECK-NEXT:    cmpwi cr4, r7, 1
+; CHECK-NEXT:    crand 4*cr7+gt, 4*cr7+eq, 4*cr1+lt
+; CHECK-NEXT:    # implicit-def: $x5
+; CHECK-NEXT:    crand 4*cr6+un, 4*cr2+eq, 4*cr6+un
+; CHECK-NEXT:    crand 4*cr5+un, 4*cr6+eq, 4*cr5+un
+; CHECK-NEXT:    crand 4*cr6+gt, 4*cr3+lt, 4*cr6+gt
+; CHECK-NEXT:    crand 4*cr7+lt, 4*cr4+lt, 4*cr7+lt
+; CHECK-NEXT:    cmpwi r6, 1
+; CHECK-NEXT:    crand 4*cr6+lt, lt, 4*cr6+lt
+; CHECK-NEXT:    bc 4, 4*cr6+gt, .LBB0_20
 ; CHECK-NEXT:  # %bb.19: # %bb68
 ; CHECK-NEXT:    ld r5, 0(r3)
 ; CHECK-NEXT:  .LBB0_20: # %bb70
-; CHECK-NEXT:    lwz r7, -20(r1)
-; CHECK-NEXT:    # implicit-def: $cr5lt
-; CHECK-NEXT:    mfocrf r6, 4
-; CHECK-NEXT:    xxlxor f2, f2, f2
-; CHECK-NEXT:    rlwimi r6, r7, 12, 20, 20
-; CHECK-NEXT:    mtocrf 4, r6
 ; CHECK-NEXT:    ld r6, 0(r3)
-; CHECK-NEXT:    lwz r8, -16(r1)
-; CHECK-NEXT:    crandc 4*cr5+gt, lt, 4*cr3+eq
-; CHECK-NEXT:    # implicit-def: $cr5eq
-; CHECK-NEXT:    crandc 4*cr5+lt, 4*cr5+lt, 4*cr7+eq
-; CHECK-NEXT:    mfocrf r7, 4
-; CHECK-NEXT:    rlwimi r7, r8, 10, 22, 22
-; CHECK-NEXT:    mtocrf 4, r7
-; CHECK-NEXT:    lwz r7, -24(r1)
-; CHECK-NEXT:    # implicit-def: $cr5un
-; CHECK-NEXT:    lwz r9, -28(r1)
-; CHECK-NEXT:    crandc 4*cr5+eq, 4*cr5+eq, 4*cr2+eq
-; CHECK-NEXT:    isel r3, r3, r5, 4*cr5+lt
-; CHECK-NEXT:    crnor 4*cr5+lt, gt, 4*cr5+lt
-; CHECK-NEXT:    crnor 4*cr5+gt, eq, 4*cr5+gt
-; CHECK-NEXT:    crnor 4*cr5+eq, un, 4*cr5+eq
-; CHECK-NEXT:    mfocrf r5, 4
-; CHECK-NEXT:    rlwimi r5, r7, 9, 23, 23
-; CHECK-NEXT:    setbc r7, 4*cr4+eq
-; CHECK-NEXT:    mtocrf 4, r5
-; CHECK-NEXT:    setbc r5, 4*cr5+un
-; CHECK-NEXT:    # implicit-def: $cr5un
-; CHECK-NEXT:    mfocrf r8, 4
-; CHECK-NEXT:    rlwimi r8, r9, 9, 23, 23
 ; CHECK-NEXT:    lwz r9, -4(r1)
-; CHECK-NEXT:    mtocrf 4, r8
-; CHECK-NEXT:    isel r3, 0, r3, 4*cr5+lt
+; CHECK-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr7+eq
+; CHECK-NEXT:    crandc 4*cr7+eq, 4*cr7+un, 4*cr2+eq
+; CHECK-NEXT:    crandc 4*cr5+lt, 4*cr5+lt, 4*cr6+eq
+; CHECK-NEXT:    setbc r7, 4*cr6+un
 ; CHECK-NEXT:    setbc r8, 4*cr5+un
-; CHECK-NEXT:    isel r6, 0, r6, 4*cr5+gt
+; CHECK-NEXT:    lwz r12, 8(r1)
+; CHECK-NEXT:    xxlxor f2, f2, f2
+; CHECK-NEXT:    isel r3, r3, r5, 4*cr5+gt
+; CHECK-NEXT:    setbc r5, 4*cr7+gt
+; CHECK-NEXT:    crnor 4*cr5+gt, 4*cr6+gt, 4*cr5+gt
+; CHECK-NEXT:    crnor 4*cr6+gt, 4*cr7+lt, 4*cr7+eq
+; CHECK-NEXT:    crnor 4*cr5+lt, 4*cr6+lt, 4*cr5+lt
 ; CHECK-NEXT:    add r5, r7, r5
 ; CHECK-NEXT:    add r5, r8, r5
+; CHECK-NEXT:    isel r3, 0, r3, 4*cr5+gt
+; CHECK-NEXT:    isel r4, 0, r4, 4*cr5+lt
+; CHECK-NEXT:    isel r6, 0, r6, 4*cr6+gt
 ; CHECK-NEXT:    mtocrf 128, r9
-; CHECK-NEXT:    lwz r9, -8(r1)
-; CHECK-NEXT:    isel r4, 0, r4, 4*cr5+eq
-; CHECK-NEXT:    iseleq r3, 0, r3
 ; CHECK-NEXT:    mtfprd f0, r5
-; CHECK-NEXT:    xscvsxddp f0, f0
-; CHECK-NEXT:    mtocrf 128, r9
-; CHECK-NEXT:    lwz r9, -12(r1)
-; CHECK-NEXT:    lwz r12, 8(r1)
-; CHECK-NEXT:    iseleq r6, 0, r6
-; CHECK-NEXT:    xsmuldp f0, f0, f2
-; CHECK-NEXT:    mtocrf 128, r9
+; CHECK-NEXT:    isel r4, 0, r4, 4*cr5+eq
 ; CHECK-NEXT:    mtocrf 32, r12
 ; CHECK-NEXT:    mtocrf 16, r12
 ; CHECK-NEXT:    mtocrf 8, r12
-; CHECK-NEXT:    iseleq r4, 0, r4
+; CHECK-NEXT:    iseleq r3, 0, r3
+; CHECK-NEXT:    isel r6, 0, r6, 4*cr1+eq
+; CHECK-NEXT:    xscvsxddp f0, f0
 ; CHECK-NEXT:    add r3, r6, r3
 ; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    mtfprd f1, r3
+; CHECK-NEXT:    xsmuldp f0, f0, f2
 ; CHECK-NEXT:    xscvsxddp f1, f1
 ; CHECK-NEXT:    xsadddp f1, f0, f1
 ; CHECK-NEXT:    blr
 bb:
   %tmp = getelementptr inbounds %4, ptr null, i64 undef, i32 7
   %tmp1 = load i64, ptr undef, align 8
   %tmp2 = load i64, ptr null, align 8
   %tmp3 = load i64, ptr %tmp, align 8

llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll

 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    lwz r12, 8(r1)
 ; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    mtocrf 32, r12
 ; CHECK-NEXT:    mtocrf 16, r12
 ; CHECK-NEXT:    mtocrf 8, r12
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB0_32: # %bb29
-; CHECK-NEXT:    mcrf cr0, cr4
+; CHECK-NEXT:    crmove eq, 4*cr4+eq
 ; CHECK-NEXT:    cmpwi cr3, r5, 366
 ; CHECK-NEXT:    cmpwi cr4, r3, 0
 ; CHECK-NEXT:    li r29, 0
 ; CHECK-NEXT:    setnbc r30, eq
 ; CHECK-NEXT:    bc 12, 4*cr2+lt, .LBB0_36
 ; CHECK-NEXT:    .p2align 5
 ; CHECK-NEXT:  .LBB0_33: # %bb36
 ; CHECK-NEXT:    bc 12, 4*cr4+eq, .LBB0_35

 ; CHECK-BE-NEXT:    ld r0, 16(r1)
 ; CHECK-BE-NEXT:    lwz r12, 8(r1)
 ; CHECK-BE-NEXT:    mtlr r0
 ; CHECK-BE-NEXT:    mtocrf 32, r12
 ; CHECK-BE-NEXT:    mtocrf 16, r12
 ; CHECK-BE-NEXT:    mtocrf 8, r12
 ; CHECK-BE-NEXT:    blr
 ; CHECK-BE-NEXT:  .LBB0_32: # %bb29
-; CHECK-BE-NEXT:    mcrf cr0, cr4
+; CHECK-BE-NEXT:    crmove eq, 4*cr4+eq
 ; CHECK-BE-NEXT:    cmpwi cr3, r5, 366
 ; CHECK-BE-NEXT:    cmpwi cr4, r3, 0
 ; CHECK-BE-NEXT:    li r29, 0
 ; CHECK-BE-NEXT:    setnbc r30, eq
 ; CHECK-BE-NEXT:    bc 12, 4*cr2+lt, .LBB0_36
 ; CHECK-BE-NEXT:    .p2align 4
 ; CHECK-BE-NEXT:  .LBB0_33: # %bb36
 ; CHECK-BE-NEXT:    bc 12, 4*cr4+eq, .LBB0_35

llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll

 
 define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
 ; CHECK-LABEL: P10_Spill_CR_LT:
 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    mfcr r12
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stw r12, 8(r1)
-; CHECK-NEXT:    stdu r1, -80(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 80
+; CHECK-NEXT:    stdu r1, -48(r1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    .cfi_offset r30, -16
 ; CHECK-NEXT:    .cfi_offset cr2, 8
 ; CHECK-NEXT:    .cfi_offset cr3, 8
 ; CHECK-NEXT:    .cfi_offset cr4, 8
-; CHECK-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    std r30, 32(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    bl call_2@notoc
 ; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_13
 ; CHECK-NEXT:  # %bb.1: # %bb
 ; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_14
 ; CHECK-NEXT:  # %bb.2: # %bb4
 ; CHECK-NEXT:    cmpdi cr3, r3, 0
-; CHECK-NEXT:    # implicit-def: $r30
-; CHECK-NEXT:    crnot 4*cr5+lt, 4*cr3+eq
-; CHECK-NEXT:    setnbc r3, 4*cr5+lt
-; CHECK-NEXT:    stw r3, 60(r1)
 ; CHECK-NEXT:    lwz r3, 0(r3)
+; CHECK-NEXT:    # implicit-def: $r30
+; CHECK-NEXT:    crnot 4*cr3+lt, 4*cr3+eq
 ; CHECK-NEXT:    cmpwi cr4, r3, 0
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_3: # %bb12
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    bl call_3@notoc
 ; CHECK-NEXT:    cmpwi r3, 1
 ; CHECK-NEXT:    crnand 4*cr5+lt, eq, 4*cr4+gt
 ; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_8

 ; CHECK-NEXT:    andi. r3, r30, 2
 ; CHECK-NEXT:    mcrf cr2, cr0
 ; CHECK-NEXT:    bl call_4@notoc
 ; CHECK-NEXT:    beq+ cr2, .LBB0_3
 ; CHECK-NEXT:  # %bb.7: # %bb37
 ; CHECK-NEXT:  .LBB0_8: # %bb22
 ; CHECK-NEXT:  .LBB0_9: # %bb35
 ; CHECK-NEXT:  .LBB0_10: # %bb27
-; CHECK-NEXT:    lwz r4, 60(r1)
-; CHECK-NEXT:    # implicit-def: $cr5lt
-; CHECK-NEXT:    mfocrf r3, 4
-; CHECK-NEXT:    rlwimi r3, r4, 12, 20, 20
-; CHECK-NEXT:    mtocrf 4, r3
-; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_12
+; CHECK-NEXT:    bc 4, 4*cr3+lt, .LBB0_12
 ; CHECK-NEXT:  # %bb.11: # %bb28
 ; CHECK-NEXT:  .LBB0_12: # %bb29
 ; CHECK-NEXT:  .LBB0_13: # %bb3
 ; CHECK-NEXT:  .LBB0_14: # %bb2
 ;
 ; CHECK-BE-LABEL: P10_Spill_CR_LT:
 ; CHECK-BE:       # %bb.0: # %bb
 ; CHECK-BE-NEXT:    mfcr r12
 ; CHECK-BE-NEXT:    mflr r0
 ; CHECK-BE-NEXT:    std r0, 16(r1)
 ; CHECK-BE-NEXT:    stw r12, 8(r1)
-; CHECK-BE-NEXT:    stdu r1, -160(r1)
-; CHECK-BE-NEXT:    .cfi_def_cfa_offset 160
+; CHECK-BE-NEXT:    stdu r1, -144(r1)
+; CHECK-BE-NEXT:    .cfi_def_cfa_offset 144
 ; CHECK-BE-NEXT:    .cfi_offset lr, 16
 ; CHECK-BE-NEXT:    .cfi_offset r29, -24
 ; CHECK-BE-NEXT:    .cfi_offset r30, -16
 ; CHECK-BE-NEXT:    .cfi_offset cr2, 8
 ; CHECK-BE-NEXT:    .cfi_offset cr2, 8
 ; CHECK-BE-NEXT:    .cfi_offset cr2, 8
-; CHECK-BE-NEXT:    std r29, 136(r1) # 8-byte Folded Spill
-; CHECK-BE-NEXT:    std r30, 144(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    std r29, 120(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    std r30, 128(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    bl call_2
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:    bc 12, 4*cr5+lt, .LBB0_13
 ; CHECK-BE-NEXT:  # %bb.1: # %bb
 ; CHECK-BE-NEXT:    bc 4, 4*cr5+lt, .LBB0_14
 ; CHECK-BE-NEXT:  # %bb.2: # %bb4
 ; CHECK-BE-NEXT:    cmpdi cr3, r3, 0
+; CHECK-BE-NEXT:    lwz r3, 0(r3)
 ; CHECK-BE-NEXT:    addis r30, r2, call_1@toc@ha
 ; CHECK-BE-NEXT:    # implicit-def: $r29
-; CHECK-BE-NEXT:    crnot 4*cr5+lt, 4*cr3+eq
-; CHECK-BE-NEXT:    setnbc r3, 4*cr5+lt
-; CHECK-BE-NEXT:    stw r3, 132(r1)
-; CHECK-BE-NEXT:    lwz r3, 0(r3)
+; CHECK-BE-NEXT:    crnot 4*cr3+lt, 4*cr3+eq
 ; CHECK-BE-NEXT:    cmpwi cr4, r3, 0
 ; CHECK-BE-NEXT:    .p2align 4
 ; CHECK-BE-NEXT:  .LBB0_3: # %bb12
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    bl call_3
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    crnand 4*cr5+lt, eq, 4*cr4+gt

 ; CHECK-BE-NEXT:    mcrf cr2, cr0
 ; CHECK-BE-NEXT:    bl call_4
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:    beq+ cr2, .LBB0_3
 ; CHECK-BE-NEXT:  # %bb.7: # %bb37
 ; CHECK-BE-NEXT:  .LBB0_8: # %bb22
 ; CHECK-BE-NEXT:  .LBB0_9: # %bb35
 ; CHECK-BE-NEXT:  .LBB0_10: # %bb27
-; CHECK-BE-NEXT:    lwz r4, 132(r1)
-; CHECK-BE-NEXT:    # implicit-def: $cr5lt
-; CHECK-BE-NEXT:    mfocrf r3, 4
-; CHECK-BE-NEXT:    rlwimi r3, r4, 12, 20, 20
-; CHECK-BE-NEXT:    mtocrf 4, r3
-; CHECK-BE-NEXT:    bc 4, 4*cr5+lt, .LBB0_12
+; CHECK-BE-NEXT:    bc 4, 4*cr3+lt, .LBB0_12
 ; CHECK-BE-NEXT:  # %bb.11: # %bb28
 ; CHECK-BE-NEXT:  .LBB0_12: # %bb29
 ; CHECK-BE-NEXT:  .LBB0_13: # %bb3
 ; CHECK-BE-NEXT:  .LBB0_14: # %bb2
 bb:
   %tmp = tail call ptr @call_2()
   %tmp1 = icmp ne ptr %tmp, null
   switch i32 undef, label %bb4 [

llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll

 ; This test also checks that the paired vector intrinsics are available even
 ; when MMA is disabled.
 
 ; assemble_pair
 declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
 define void @ass_pair(ptr %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: ass_pair:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmr v3, v2
+; CHECK-NEXT:    stxv v2, 0(r3)
 ; CHECK-NEXT:    stxv v2, 16(r3)
-; CHECK-NEXT:    stxv v3, 0(r3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: ass_pair:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    vmr v3, v2
+; CHECK-NOMMA-NEXT:    stxv v2, 0(r3)
 ; CHECK-NOMMA-NEXT:    stxv v2, 16(r3)
-; CHECK-NOMMA-NEXT:    stxv v3, 0(r3)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: ass_pair:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vmr v3, v2
 ; CHECK-BE-NEXT:    stxv v2, 16(r3)
 ; CHECK-BE-NEXT:    stxv v2, 0(r3)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: ass_pair:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    vmr v3, v2
 ; CHECK-BE-NOMMA-NEXT:    stxv v2, 16(r3)
 ; CHECK-BE-NOMMA-NEXT:    stxv v2, 0(r3)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc, <16 x i8> %vc)
   store <256 x i1> %0, ptr %ptr, align 32
   ret void
 }

llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
 ; RUN:    | FileCheck %s
 
 define void @copy_novsrp() local_unnamed_addr {
 ; CHECK-LABEL: copy_novsrp:
 ; CHECK:       # %bb.0: # %dmblvi_entry
-; CHECK-NEXT:    xxlxor v2, v2, v2
+; CHECK-NEXT:    xxlxor vs3, vs3, vs3
 ; CHECK-NEXT:    xxlxor vs0, vs0, vs0
-; CHECK-NEXT:    xxlor vs3, v2, v2
 ; CHECK-NEXT:    stxv vs0, 0(0)
 dmblvi_entry:
   %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> undef, <16 x i8> undef, <16 x i8> zeroinitializer)
   %1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)
   %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3
   store <16 x i8> %2, ptr null, align 1
   unreachable
 }
 
 declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
 declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)

llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll

 ; CHECK-NEXT:    lxvdsx v5, 0, r3
 ; CHECK-NEXT:    xvmaddadp v0, v5, v0
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_1: # %bb9
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    addi r6, r6, 2
 ; CHECK-NEXT:    lxv vs0, 16(0)
 ; CHECK-NEXT:    lxv vs1, -64(r5)
-; CHECK-NEXT:    xxlxor v7, v7, v7
-; CHECK-NEXT:    vmr v9, v0
-; CHECK-NEXT:    xxlxor v10, v10, v10
+; CHECK-NEXT:    xxlxor vs7, vs7, vs7
+; CHECK-NEXT:    xxlor vs3, v0, v0
+; CHECK-NEXT:    xxlxor vs2, vs2, vs2
+; CHECK-NEXT:    xxlxor vs12, vs12, vs12
 ; CHECK-NEXT:    mulld r6, r6, r3
-; CHECK-NEXT:    xvmaddadp v7, vs0, v5
-; CHECK-NEXT:    xvmuldp v6, vs0, v2
+; CHECK-NEXT:    xxlor vs10, v2, v2
+; CHECK-NEXT:    xxlor vs4, v2, v2
+; CHECK-NEXT:    xxlor vs8, vs10, vs10
+; CHECK-NEXT:    xxlor vs10, v1, v1
+; CHECK-NEXT:    xvmaddadp vs7, vs0, v5
+; CHECK-NEXT:    xvmuldp vs6, vs0, v2
 ; CHECK-NEXT:    lxv vs0, -16(r5)
-; CHECK-NEXT:    xvmaddadp v9, vs1, v2
-; CHECK-NEXT:    xxlxor v8, v8, v8
-; CHECK-NEXT:    xvmaddadp v7, v2, v2
-; CHECK-NEXT:    xvmaddadp v6, v2, v2
-; CHECK-NEXT:    lxvdsx v14, r6, r4
+; CHECK-NEXT:    xvmaddadp vs3, vs1, v2
+; CHECK-NEXT:    xvmaddadp vs2, vs1, vs2
+; CHECK-NEXT:    lxvdsx v6, r6, r4
 ; CHECK-NEXT:    li r6, 0
-; CHECK-NEXT:    xvmaddadp v8, vs1, v8
-; CHECK-NEXT:    xvmaddadp v10, vs0, v10
-; CHECK-NEXT:    xvmuldp v3, vs1, v14
-; CHECK-NEXT:    xvmuldp v11, vs0, v14
-; CHECK-NEXT:    xvmuldp vs5, v14, v2
-; CHECK-NEXT:    xvmuldp v13, v4, v14
+; CHECK-NEXT:    xvmaddadp vs7, v2, v2
+; CHECK-NEXT:    xvmaddadp vs6, v2, v2
+; CHECK-NEXT:    xvmaddadp vs12, vs0, vs12
+; CHECK-NEXT:    xvmuldp v3, vs1, v6
+; CHECK-NEXT:    xvmuldp vs11, v4, v6
+; CHECK-NEXT:    xvmuldp vs13, vs0, v6
+; CHECK-NEXT:    xvmuldp vs5, v6, v2
 ; CHECK-NEXT:    xxlor vs0, v2, v2
-; CHECK-NEXT:    vmr v12, v2
-; CHECK-NEXT:    xxlor vs14, v10, v10
-; CHECK-NEXT:    xxlor vs4, v2, v2
-; CHECK-NEXT:    # kill: def $vsrp2 killed $vsrp2 def $uacc1
-; CHECK-NEXT:    xxlor vs6, v6, v6
-; CHECK-NEXT:    xxlor vs7, v7, v7
-; CHECK-NEXT:    xxlor vs8, v12, v12
-; CHECK-NEXT:    xxlor vs9, v13, v13
-; CHECK-NEXT:    vmr v12, v1
+; CHECK-NEXT:    xxlor vs14, vs12, vs12
+; CHECK-NEXT:    xxlor vs12, v2, v2
 ; CHECK-NEXT:    xxlor vs1, v3, v3
-; CHECK-NEXT:    xxlor vs2, v8, v8
-; CHECK-NEXT:    xxlor vs3, v9, v9
-; CHECK-NEXT:    xxlor vs15, v11, v11
-; CHECK-NEXT:    vmr v10, v2
-; CHECK-NEXT:    xxlor vs10, v12, v12
-; CHECK-NEXT:    xxlor vs11, v13, v13
+; CHECK-NEXT:    xxlor vs9, vs11, vs11
+; CHECK-NEXT:    xxlor vs15, vs13, vs13
 ; CHECK-NEXT:    xxmtacc acc1
-; CHECK-NEXT:    xxlor vs12, v10, v10
-; CHECK-NEXT:    xxlor vs13, v11, v11
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    xxmtacc acc2
 ; CHECK-NEXT:    xxmtacc acc3
 ; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
 ; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
 ; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
 ; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
 ; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0

llvm/test/CodeGen/PowerPC/pr45709.ll

 ; CHECK-NEXT:    addi r3, r4, 0
 ; CHECK-NEXT:  .LBB0_5:
 ; CHECK-NEXT:    cmpw r3, r3
 ; CHECK-NEXT:    stw r3, -64(r1)
 ; CHECK-NEXT:    addi r3, r1, -64
 ; CHECK-NEXT:    lvx v2, 0, r3
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    stvx v2, 0, r3
+; CHECK-NEXT:    lfs f0, -16(r1)
 ; CHECK-NEXT:  .LBB0_6:
 ; CHECK-NEXT:    blr
   br i1 undef, label %7, label %1
 
 1:                                                ; preds = %1, %0
   br i1 undef, label %2, label %1
 
 2:                                                ; preds = %1

llvm/test/CodeGen/PowerPC/spe.ll

 ; SPE-LABEL: test_dcmpge:
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    evmergelo 3, 3, 4
 ; SPE-NEXT:    evmergelo 4, 5, 6
 ; SPE-NEXT:    li 7, 1
 ; SPE-NEXT:    efdcmpeq 0, 4, 4
 ; SPE-NEXT:    efdcmpeq 1, 3, 3
 ; SPE-NEXT:    efdcmplt 5, 3, 4
-; SPE-NEXT:    crand 24, 5, 1
-; SPE-NEXT:    crorc 20, 21, 24
+; SPE-NEXT:    crand 20, 5, 1
+; SPE-NEXT:    crorc 20, 21, 20
 ; SPE-NEXT:    bc 12, 20, .LBB47_2
 ; SPE-NEXT:  # %bb.1: # %entry
 ; SPE-NEXT:    ori 3, 7, 0
 ; SPE-NEXT:    blr
 ; SPE-NEXT:  .LBB47_2: # %entry
 ; SPE-NEXT:    li 3, 0
 ; SPE-NEXT:    blr
 ;

llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll

 ; PPC32-NEXT:    mcrf 1, 0
 ; PPC32-NEXT:    mfcr 12
 ; PPC32-NEXT:    cmpwi 7, 5, 0
 ; PPC32-NEXT:    cmpwi 2, 7, 0
 ; PPC32-NEXT:    stw 22, 24(1) # 4-byte Folded Spill
 ; PPC32-NEXT:    mulhwu. 26, 5, 8
 ; PPC32-NEXT:    mcrf 5, 0
 ; PPC32-NEXT:    stw 23, 28(1) # 4-byte Folded Spill
-; PPC32-NEXT:    crnor 28, 30, 10
+; PPC32-NEXT:    crnor 20, 30, 10
 ; PPC32-NEXT:    stw 29, 52(1) # 4-byte Folded Spill
-; PPC32-NEXT:    cmpwi 2, 9, 0
+; PPC32-NEXT:    cmpwi 7, 9, 0
 ; PPC32-NEXT:    mulhwu. 26, 3, 10
 ; PPC32-NEXT:    mcrf 6, 0
-; PPC32-NEXT:    cmpwi 3, 3, 0
+; PPC32-NEXT:    cmpwi 2, 3, 0
 ; PPC32-NEXT:    stw 24, 32(1) # 4-byte Folded Spill
-; PPC32-NEXT:    crnor 29, 10, 14
+; PPC32-NEXT:    crnor 21, 30, 10
 ; PPC32-NEXT:    stw 25, 36(1) # 4-byte Folded Spill
 ; PPC32-NEXT:    mulhwu. 26, 9, 4
 ; PPC32-NEXT:    stw 27, 44(1) # 4-byte Folded Spill
-; PPC32-NEXT:    crorc 28, 28, 6
+; PPC32-NEXT:    crorc 20, 20, 6
 ; PPC32-NEXT:    stw 28, 48(1) # 4-byte Folded Spill
-; PPC32-NEXT:    crorc 20, 28, 22
+; PPC32-NEXT:    crorc 21, 21, 26
 ; PPC32-NEXT:    stw 30, 56(1) # 4-byte Folded Spill
 ; PPC32-NEXT:    mulhwu 0, 6, 10
 ; PPC32-NEXT:    stw 12, 20(1)
-; PPC32-NEXT:    crorc 21, 29, 26
+; PPC32-NEXT:    crorc 20, 20, 22
 ; PPC32-NEXT:    crorc 21, 21, 2
 ; PPC32-NEXT:    li 11, 0
 ; PPC32-NEXT:    mullw 26, 5, 10
 ; PPC32-NEXT:    addc 0, 26, 0
 ; PPC32-NEXT:    mulhwu 29, 5, 10
 ; PPC32-NEXT:    addze 29, 29
 ; PPC32-NEXT:    mullw 23, 5, 8
 ; PPC32-NEXT:    mullw 22, 7, 6

 ; PPC32-NEXT:    crnor 22, 2, 6
 ; PPC32-NEXT:    mullw 28, 8, 6
 ; PPC32-NEXT:    adde 8, 12, 4
 ; PPC32-NEXT:    addc 3, 0, 28
 ; PPC32-NEXT:    adde 9, 26, 9
 ; PPC32-NEXT:    addc 4, 7, 3
 ; PPC32-NEXT:    adde 3, 8, 9
 ; PPC32-NEXT:    cror 21, 22, 21
-; PPC32-NEXT:    cmplw   4, 7
+; PPC32-NEXT:    cmplw 4, 7
 ; PPC32-NEXT:    cmplw 1, 3, 8
 ; PPC32-NEXT:    lwz 12, 20(1)
 ; PPC32-NEXT:    cror 20, 21, 20
 ; PPC32-NEXT:    crandc 21, 4, 6
 ; PPC32-NEXT:    crand 22, 6, 0
 ; PPC32-NEXT:    cror 21, 22, 21
 ; PPC32-NEXT:    crnor 20, 20, 21
 ; PPC32-NEXT:    li 7, 1
 ; PPC32-NEXT:    mullw 6, 6, 10
 ; PPC32-NEXT:    bc 12, 20, .LBB0_1
 ; PPC32-NEXT:    b .LBB0_2
 ; PPC32-NEXT:  .LBB0_1: # %start
-; PPC32-NEXT:    li      7, 0
+; PPC32-NEXT:    li 7, 0
 ; PPC32-NEXT:  .LBB0_2: # %start
 ; PPC32-NEXT:    mtcrf 32, 12 # cr2
-; PPC32-NEXT:    mtcrf 16, 12 # cr3
 ; PPC32-NEXT:    lwz 30, 56(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 29, 52(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 28, 48(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 27, 44(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 26, 40(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 25, 36(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 24, 32(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 23, 28(1) # 4-byte Folded Reload

llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll

 ; LE-32BIT-NEXT:    srw 3, 11, 3
 ; LE-32BIT-NEXT:    slw 14, 6, 15
 ; LE-32BIT-NEXT:    cmplwi 5, 30, 64
 ; LE-32BIT-NEXT:    cmplwi 1, 30, 128
 ; LE-32BIT-NEXT:    slw 24, 11, 24
 ; LE-32BIT-NEXT:    mr 21, 8
 ; LE-32BIT-NEXT:    or 8, 14, 3
 ; LE-32BIT-NEXT:    srw 14, 6, 31
-; LE-32BIT-NEXT:    crnand 28, 4, 20
+; LE-32BIT-NEXT:    crnand 21, 4, 20
 ; LE-32BIT-NEXT:    srw 31, 6, 30
 ; LE-32BIT-NEXT:    or 24, 0, 24
 ; LE-32BIT-NEXT:    slw 0, 7, 15
 ; LE-32BIT-NEXT:    mr 23, 7
 ; LE-32BIT-NEXT:    or 17, 17, 14
-; LE-32BIT-NEXT:    bc 12, 28, .LBB9_2
+; LE-32BIT-NEXT:    bc 12, 21, .LBB9_2
 ; LE-32BIT-NEXT:  # %bb.1:
 ; LE-32BIT-NEXT:    ori 14, 31, 0
 ; LE-32BIT-NEXT:    b .LBB9_3
 ; LE-32BIT-NEXT:  .LBB9_2:
 ; LE-32BIT-NEXT:    li 14, 0
 ; LE-32BIT-NEXT:  .LBB9_3:
 ; LE-32BIT-NEXT:    or 20, 20, 0
 ; LE-32BIT-NEXT:    subfic 0, 16, 64

 ; LE-32BIT-NEXT:    slw 25, 11, 9
 ; LE-32BIT-NEXT:    or 26, 0, 26
 ; LE-32BIT-NEXT:    srw 0, 10, 31
 ; LE-32BIT-NEXT:    or 3, 8, 25
 ; LE-32BIT-NEXT:    or 28, 0, 28
 ; LE-32BIT-NEXT:    srw 0, 10, 30
 ; LE-32BIT-NEXT:    srw 5, 10, 5
 ; LE-32BIT-NEXT:    or 3, 0, 3
-; LE-32BIT-NEXT:    bc 12, 28, .LBB9_5
+; LE-32BIT-NEXT:    bc 12, 21, .LBB9_5
 ; LE-32BIT-NEXT:  # %bb.4:
 ; LE-32BIT-NEXT:    ori 0, 17, 0
 ; LE-32BIT-NEXT:    b .LBB9_6
 ; LE-32BIT-NEXT:  .LBB9_5:
 ; LE-32BIT-NEXT:    li 0, 0
 ; LE-32BIT-NEXT:  .LBB9_6:
 ; LE-32BIT-NEXT:    lwz 8, 32(1) # 4-byte Folded Reload
 ; LE-32BIT-NEXT:    or 5, 14, 5

 ; LE-32BIT-NEXT:    addi 24, 18, 0
 ; LE-32BIT-NEXT:  .LBB9_12:
 ; LE-32BIT-NEXT:    srw 19, 9, 4
 ; LE-32BIT-NEXT:    srw 17, 6, 4
 ; LE-32BIT-NEXT:    lwz 4, 20(1) # 4-byte Folded Reload
 ; LE-32BIT-NEXT:    srw 30, 21, 30
 ; LE-32BIT-NEXT:    lwz 8, 24(1) # 4-byte Folded Reload
 ; LE-32BIT-NEXT:    slw 21, 29, 16
-; LE-32BIT-NEXT:    cmplwi 7, 16, 64
+; LE-32BIT-NEXT:    cmplwi 2, 16, 64
 ; LE-32BIT-NEXT:    cmplwi 3, 16, 0
 ; LE-32BIT-NEXT:    li 16, 0
 ; LE-32BIT-NEXT:    srw 18, 6, 0
-; LE-32BIT-NEXT:    bc 12, 28, .LBB9_14
+; LE-32BIT-NEXT:    bc 12, 8, .LBB9_14
 ; LE-32BIT-NEXT:  # %bb.13:
 ; LE-32BIT-NEXT:    ori 0, 16, 0
 ; LE-32BIT-NEXT:    b .LBB9_15
 ; LE-32BIT-NEXT:  .LBB9_14:
 ; LE-32BIT-NEXT:    addi 0, 21, 0
 ; LE-32BIT-NEXT:  .LBB9_15:
 ; LE-32BIT-NEXT:    lwz 21, 60(1) # 4-byte Folded Reload
-; LE-32BIT-NEXT:    bc 12, 28, .LBB9_16
+; LE-32BIT-NEXT:    bc 12, 8, .LBB9_16
 ; LE-32BIT-NEXT:    b .LBB9_17
 ; LE-32BIT-NEXT:  .LBB9_16:
 ; LE-32BIT-NEXT:    addi 4, 7, 0
 ; LE-32BIT-NEXT:  .LBB9_17:
 ; LE-32BIT-NEXT:    bc 12, 20, .LBB9_18
 ; LE-32BIT-NEXT:    b .LBB9_19
 ; LE-32BIT-NEXT:  .LBB9_18:
 ; LE-32BIT-NEXT:    addi 8, 20, 0
 ; LE-32BIT-NEXT:  .LBB9_19:
 ; LE-32BIT-NEXT:    mr 12, 29
 ; LE-32BIT-NEXT:    lwz 7, 48(1) # 4-byte Folded Reload
 ; LE-32BIT-NEXT:    slw 20, 29, 15
 ; LE-32BIT-NEXT:    srw 29, 6, 31
 ; LE-32BIT-NEXT:    bc 12, 2, .LBB9_20
 ; LE-32BIT-NEXT:    b .LBB9_21
 ; LE-32BIT-NEXT:  .LBB9_20:
 ; LE-32BIT-NEXT:    addi 8, 21, 0
 ; LE-32BIT-NEXT:  .LBB9_21:
-; LE-32BIT-NEXT:    cmplwi 2, 31, 0
+; LE-32BIT-NEXT:    cmplwi 7, 31, 0
 ; LE-32BIT-NEXT:    bc 12, 20, .LBB9_23
 ; LE-32BIT-NEXT:  # %bb.22:
 ; LE-32BIT-NEXT:    ori 26, 19, 0
 ; LE-32BIT-NEXT:    ori 3, 17, 0
 ; LE-32BIT-NEXT:    b .LBB9_23
 ; LE-32BIT-NEXT:  .LBB9_23:
 ; LE-32BIT-NEXT:    or 8, 8, 0
 ; LE-32BIT-NEXT:    bc 12, 20, .LBB9_25

 ; LE-32BIT-NEXT:    bc 12, 20, .LBB9_31
 ; LE-32BIT-NEXT:  # %bb.30:
 ; LE-32BIT-NEXT:    ori 29, 16, 0
 ; LE-32BIT-NEXT:    b .LBB9_32
 ; LE-32BIT-NEXT:  .LBB9_31:
 ; LE-32BIT-NEXT:    addi 29, 7, 0
 ; LE-32BIT-NEXT:  .LBB9_32:
 ; LE-32BIT-NEXT:    lwz 7, 44(1) # 4-byte Folded Reload
-; LE-32BIT-NEXT:    bc 12, 10, .LBB9_33
+; LE-32BIT-NEXT:    bc 12, 30, .LBB9_33
 ; LE-32BIT-NEXT:    b .LBB9_34
 ; LE-32BIT-NEXT:  .LBB9_33:
 ; LE-32BIT-NEXT:    addi 25, 12, 0
 ; LE-32BIT-NEXT:  .LBB9_34:
 ; LE-32BIT-NEXT:    bc 12, 14, .LBB9_35
 ; LE-32BIT-NEXT:    b .LBB9_36
 ; LE-32BIT-NEXT:  .LBB9_35:
 ; LE-32BIT-NEXT:    addi 4, 6, 0
 ; LE-32BIT-NEXT:  .LBB9_36:
 ; LE-32BIT-NEXT:    bc 12, 2, .LBB9_38
 ; LE-32BIT-NEXT:  # %bb.37:
 ; LE-32BIT-NEXT:    ori 6, 26, 0
 ; LE-32BIT-NEXT:    b .LBB9_39
 ; LE-32BIT-NEXT:  .LBB9_38:
 ; LE-32BIT-NEXT:    addi 6, 22, 0
 ; LE-32BIT-NEXT:  .LBB9_39:
 ; LE-32BIT-NEXT:    li 26, 0
 ; LE-32BIT-NEXT:    bc 12, 2, .LBB9_40
 ; LE-32BIT-NEXT:    b .LBB9_41
 ; LE-32BIT-NEXT:  .LBB9_40:
 ; LE-32BIT-NEXT:    addi 3, 10, 0
 ; LE-32BIT-NEXT:  .LBB9_41:
-; LE-32BIT-NEXT:    bc 12, 28, .LBB9_43
+; LE-32BIT-NEXT:    bc 12, 8, .LBB9_43
 ; LE-32BIT-NEXT:  # %bb.42:
 ; LE-32BIT-NEXT:    ori 5, 20, 0
 ; LE-32BIT-NEXT:    b .LBB9_43
 ; LE-32BIT-NEXT:  .LBB9_43:
 ; LE-32BIT-NEXT:    bc 12, 4, .LBB9_45
 ; LE-32BIT-NEXT:  # %bb.44:
 ; LE-32BIT-NEXT:    ori 8, 25, 0
 ; LE-32BIT-NEXT:    b .LBB9_45
 ; LE-32BIT-NEXT:  .LBB9_45:
 ; LE-32BIT-NEXT:    bc 12, 24, .LBB9_47
 ; LE-32BIT-NEXT:  # %bb.46:
 ; LE-32BIT-NEXT:    ori 28, 18, 0
 ; LE-32BIT-NEXT:    b .LBB9_47
 ; LE-32BIT-NEXT:  .LBB9_47:
-; LE-32BIT-NEXT:    bc 12, 28, .LBB9_49
+; LE-32BIT-NEXT:    bc 12, 8, .LBB9_49
 ; LE-32BIT-NEXT:  # %bb.48:
 ; LE-32BIT-NEXT:    ori 27, 16, 0
 ; LE-32BIT-NEXT:    b .LBB9_49
 ; LE-32BIT-NEXT:  .LBB9_49:
 ; LE-32BIT-NEXT:    bc 12, 2, .LBB9_51
 ; LE-32BIT-NEXT:  # %bb.50:
 ; LE-32BIT-NEXT:    ori 12, 24, 0
 ; LE-32BIT-NEXT:    b .LBB9_51
 ; LE-32BIT-NEXT:  .LBB9_51:
 ; LE-32BIT-NEXT:    bc 12, 4, .LBB9_53
 ; LE-32BIT-NEXT:  # %bb.52:
 ; LE-32BIT-NEXT:    ori 3, 26, 0
 ; LE-32BIT-NEXT:    b .LBB9_53
 ; LE-32BIT-NEXT:  .LBB9_53:
 ; LE-32BIT-NEXT:    bc 12, 14, .LBB9_54
 ; LE-32BIT-NEXT:    b .LBB9_55
 ; LE-32BIT-NEXT:  .LBB9_54:
 ; LE-32BIT-NEXT:    addi 5, 11, 0
 ; LE-32BIT-NEXT:  .LBB9_55:
-; LE-32BIT-NEXT:    bc 12, 10, .LBB9_56
+; LE-32BIT-NEXT:    bc 12, 30, .LBB9_56
 ; LE-32BIT-NEXT:    b .LBB9_57
 ; LE-32BIT-NEXT:  .LBB9_56:
 ; LE-32BIT-NEXT:    addi 28, 10, 0
 ; LE-32BIT-NEXT:  .LBB9_57:
 ; LE-32BIT-NEXT:    or 6, 6, 27
 ; LE-32BIT-NEXT:    stw 3, 8(14)
 ; LE-32BIT-NEXT:    or 3, 0, 4
 ; LE-32BIT-NEXT:    bc 12, 2, .LBB9_59

 ; LE-32BIT-NEXT:    or 18, 18, 14
 ; LE-32BIT-NEXT:    slw 3, 6, 3
 ; LE-32BIT-NEXT:    srw 14, 5, 22
 ; LE-32BIT-NEXT:    cmplwi 5, 30, 64
 ; LE-32BIT-NEXT:    cmplwi 1, 30, 128
 ; LE-32BIT-NEXT:    srw 24, 6, 24
 ; LE-32BIT-NEXT:    or 10, 14, 3
 ; LE-32BIT-NEXT:    slw 14, 5, 31
-; LE-32BIT-NEXT:    crnand 28, 4, 20
+; LE-32BIT-NEXT:    crnand 21, 4, 20
 ; LE-32BIT-NEXT:    slw 31, 5, 30
 ; LE-32BIT-NEXT:    or 24, 0, 24
 ; LE-32BIT-NEXT:    mr 3, 7
 ; LE-32BIT-NEXT:    stw 7, 28(1) # 4-byte Folded Spill
 ; LE-32BIT-NEXT:    srw 0, 7, 22
 ; LE-32BIT-NEXT:    lwz 7, 24(1) # 4-byte Folded Reload
 ; LE-32BIT-NEXT:    or 17, 17, 14
-; LE-32BIT-NEXT:    bc 12, 28, .LBB10_2
+; LE-32BIT-NEXT:    bc 12, 21, .LBB10_2
 ; LE-32BIT-NEXT:  # %bb.1:
 ; LE-32BIT-NEXT:    ori 14, 31, 0
 ; LE-32BIT-NEXT:    b .LBB10_3
 ; LE-32BIT-NEXT:  .LBB10_2:
 ; LE-32BIT-NEXT:    li 14, 0
 ; LE-32BIT-NEXT:  .LBB10_3:
 ; LE-32BIT-NEXT:    or 20, 20, 0
 ; LE-32BIT-NEXT:    subfic 0, 15, 64
 ; LE-32BIT-NEXT:    stw 14, 28(9)
 ; LE-32BIT-NEXT:    subfic 14, 0, 32
 ; LE-32BIT-NEXT:    srw 14, 11, 14
 ; LE-32BIT-NEXT:    slw 31, 12, 0
 ; LE-32BIT-NEXT:    or 14, 31, 14
 ; LE-32BIT-NEXT:    srw 31, 12, 7
 ; LE-32BIT-NEXT:    or 23, 23, 31
 ; LE-32BIT-NEXT:    srw 31, 3, 25
 ; LE-32BIT-NEXT:    lwz 3, 40(1) # 4-byte Folded Reload
 ; LE-32BIT-NEXT:    or 4, 4, 31
 ; LE-32BIT-NEXT:    slw 0, 11, 0
-; LE-32BIT-NEXT:    cmplwi 3, 15, 0
+; LE-32BIT-NEXT:    cmplwi 2, 15, 64
 ; LE-32BIT-NEXT:    srw 31, 6, 3
 ; LE-32BIT-NEXT:    or 27, 27, 31
 ; LE-32BIT-NEXT:    srw 31, 12, 25
 ; LE-32BIT-NEXT:    or 28, 28, 31
 ; LE-32BIT-NEXT:    srw 31, 6, 7
 ; LE-32BIT-NEXT:    or 26, 26, 31
 ; LE-32BIT-NEXT:    srw 31, 6, 22
 ; LE-32BIT-NEXT:    or 18, 18, 31
 ; LE-32BIT-NEXT:    lwz 31, 36(1) # 4-byte Folded Reload
 ; LE-32BIT-NEXT:    srw 25, 6, 25
 ; LE-32BIT-NEXT:    or 3, 10, 25
 ; LE-32BIT-NEXT:    or 26, 26, 0
 ; LE-32BIT-NEXT:    cmplwi 6, 31, 64
 ; LE-32BIT-NEXT:    slw 0, 11, 30
 ; LE-32BIT-NEXT:    bc 12, 24, .LBB10_5
 ; LE-32BIT-NEXT:  # %bb.4:
 ; LE-32BIT-NEXT:    ori 25, 21, 0
 ; LE-32BIT-NEXT:    b .LBB10_6
 ; LE-32BIT-NEXT:  .LBB10_5:
 ; LE-32BIT-NEXT:    addi 25, 24, 0
 ; LE-32BIT-NEXT:  .LBB10_6:
 ; LE-32BIT-NEXT:    slw 24, 11, 16
 ; LE-32BIT-NEXT:    lwz 10, 32(1) # 4-byte Folded Reload
 ; LE-32BIT-NEXT:    or 3, 0, 3
-; LE-32BIT-NEXT:    bc 12, 28, .LBB10_8
+; LE-32BIT-NEXT:    bc 12, 21, .LBB10_8
 ; LE-32BIT-NEXT:  # %bb.7:
 ; LE-32BIT-NEXT:    ori 0, 17, 0
 ; LE-32BIT-NEXT:    b .LBB10_9
 ; LE-32BIT-NEXT:  .LBB10_8:
 ; LE-32BIT-NEXT:    li 0, 0
 ; LE-32BIT-NEXT:  .LBB10_9:
 ; LE-32BIT-NEXT:    or 24, 14, 24
 ; LE-32BIT-NEXT:    stw 0, 24(9)
 ; LE-32BIT-NEXT:    srw 0, 6, 15
 ; LE-32BIT-NEXT:    or 24, 0, 24
 ; LE-32BIT-NEXT:    lwz 0, 56(1) # 4-byte Folded Reload
 ; LE-32BIT-NEXT:    slw 21, 10, 30
 ; LE-32BIT-NEXT:    bc 12, 20, .LBB10_11
 ; LE-32BIT-NEXT:  # %bb.10:
 ; LE-32BIT-NEXT:    ori 7, 29, 0
 ; LE-32BIT-NEXT:    b .LBB10_12
 ; LE-32BIT-NEXT:  .LBB10_11:
 ; LE-32BIT-NEXT:    addi 7, 20, 0
 ; LE-32BIT-NEXT:  .LBB10_12:
 ; LE-32BIT-NEXT:    or 4, 21, 4
 ; LE-32BIT-NEXT:    slw 21, 11, 31
 ; LE-32BIT-NEXT:    srw 20, 12, 15
-; LE-32BIT-NEXT:    cmplwi 7, 15, 64
+; LE-32BIT-NEXT:    cmplwi 3, 15, 0
 ; LE-32BIT-NEXT:    li 15, 0
 ; LE-32BIT-NEXT:    or 27, 21, 27
 ; LE-32BIT-NEXT:    bc 12, 20, .LBB10_14
 ; LE-32BIT-NEXT:  # %bb.13:
 ; LE-32BIT-NEXT:    ori 21, 19, 0
 ; LE-32BIT-NEXT:    b .LBB10_15
 ; LE-32BIT-NEXT:  .LBB10_14:
 ; LE-32BIT-NEXT:    addi 21, 18, 0
 ; LE-32BIT-NEXT:  .LBB10_15:
 ; LE-32BIT-NEXT:    mr 16, 9
 ; LE-32BIT-NEXT:    lwz 9, 52(1) # 4-byte Folded Reload
 ; LE-32BIT-NEXT:    slw 18, 5, 0
-; LE-32BIT-NEXT:    bc 12, 28, .LBB10_17
+; LE-32BIT-NEXT:    bc 12, 8, .LBB10_17
 ; LE-32BIT-NEXT:  # %bb.16:
 ; LE-32BIT-NEXT:    ori 0, 15, 0
 ; LE-32BIT-NEXT:    b .LBB10_18
 ; LE-32BIT-NEXT:  .LBB10_17:
 ; LE-32BIT-NEXT:    addi 0, 20, 0
 ; LE-32BIT-NEXT:  .LBB10_18:
 ; LE-32BIT-NEXT:    lwz 20, 60(1) # 4-byte Folded Reload
 ; LE-32BIT-NEXT:    slw 30, 8, 30

 ; LE-32BIT-NEXT:  .LBB10_24:
 ; LE-32BIT-NEXT:    bc 12, 24, .LBB10_26
 ; LE-32BIT-NEXT:  # %bb.25:
 ; LE-32BIT-NEXT:    ori 30, 15, 0
 ; LE-32BIT-NEXT:    b .LBB10_27
 ; LE-32BIT-NEXT:  .LBB10_26:
 ; LE-32BIT-NEXT:    addi 30, 29, 0
 ; LE-32BIT-NEXT:  .LBB10_27:
-; LE-32BIT-NEXT:    bc 12, 28, .LBB10_28
+; LE-32BIT-NEXT:    bc 12, 8, .LBB10_28
 ; LE-32BIT-NEXT:    b .LBB10_29
 ; LE-32BIT-NEXT:  .LBB10_28:
 ; LE-32BIT-NEXT:    addi 28, 26, 0
 ; LE-32BIT-NEXT:  .LBB10_29:
 ; LE-32BIT-NEXT:    bc 12, 20, .LBB10_31
 ; LE-32BIT-NEXT:  # %bb.30:
 ; LE-32BIT-NEXT:    ori 3, 17, 0
 ; LE-32BIT-NEXT:    b .LBB10_31

 ; LE-32BIT-NEXT:    b .LBB10_38
 ; LE-32BIT-NEXT:  .LBB10_38:
 ; LE-32BIT-NEXT:    li 28, 0
 ; LE-32BIT-NEXT:    bc 12, 2, .LBB10_39
 ; LE-32BIT-NEXT:    b .LBB10_40
 ; LE-32BIT-NEXT:  .LBB10_39:
 ; LE-32BIT-NEXT:    addi 3, 11, 0
 ; LE-32BIT-NEXT:  .LBB10_40:
-; LE-32BIT-NEXT:    cmplwi 2, 31, 0
+; LE-32BIT-NEXT:    cmplwi 7, 31, 0
 ; LE-32BIT-NEXT:    bc 12, 24, .LBB10_42
 ; LE-32BIT-NEXT:  # %bb.41:
 ; LE-32BIT-NEXT:    ori 27, 18, 0
 ; LE-32BIT-NEXT:    b .LBB10_42
 ; LE-32BIT-NEXT:  .LBB10_42:
-; LE-32BIT-NEXT:    bc 12, 28, .LBB10_44
+; LE-32BIT-NEXT:    bc 12, 8, .LBB10_44
 ; LE-32BIT-NEXT:  # %bb.43:
 ; LE-32BIT-NEXT:    ori 26, 22, 0
 ; LE-32BIT-NEXT:    b .LBB10_45
 ; LE-32BIT-NEXT:  .LBB10_44:
 ; LE-32BIT-NEXT:    addi 26, 24, 0
 ; LE-32BIT-NEXT:  .LBB10_45:
 ; LE-32BIT-NEXT:    bc 12, 2, .LBB10_46
 ; LE-32BIT-NEXT:    b .LBB10_47
 ; LE-32BIT-NEXT:  .LBB10_46:
 ; LE-32BIT-NEXT:    addi 4, 10, 0
 ; LE-32BIT-NEXT:  .LBB10_47:
 ; LE-32BIT-NEXT:    bc 12, 4, .LBB10_49
 ; LE-32BIT-NEXT:  # %bb.48:
 ; LE-32BIT-NEXT:    ori 3, 28, 0
 ; LE-32BIT-NEXT:    b .LBB10_49
 ; LE-32BIT-NEXT:  .LBB10_49:
-; LE-32BIT-NEXT:    bc 12, 10, .LBB10_50
+; LE-32BIT-NEXT:    bc 12, 30, .LBB10_50
 ; LE-32BIT-NEXT:    b .LBB10_51
 ; LE-32BIT-NEXT:  .LBB10_50:
 ; LE-32BIT-NEXT:    addi 25, 12, 0
 ; LE-32BIT-NEXT:  .LBB10_51:
 ; LE-32BIT-NEXT:    or 5, 0, 5
 ; LE-32BIT-NEXT:    bc 12, 24, .LBB10_53
 ; LE-32BIT-NEXT:  # %bb.52:
 ; LE-32BIT-NEXT:    ori 24, 15, 0
 ; LE-32BIT-NEXT:    b .LBB10_54
 ; LE-32BIT-NEXT:  .LBB10_53:
 ; LE-32BIT-NEXT:    addi 24, 7, 0
 ; LE-32BIT-NEXT:  .LBB10_54:
-; LE-32BIT-NEXT:    bc 12, 28, .LBB10_56
+; LE-32BIT-NEXT:    bc 12, 8, .LBB10_56
 ; LE-32BIT-NEXT:  # %bb.55:
 ; LE-32BIT-NEXT:    ori 7, 15, 0
 ; LE-32BIT-NEXT:    b .LBB10_57
 ; LE-32BIT-NEXT:  .LBB10_56:
 ; LE-32BIT-NEXT:    addi 7, 23, 0
 ; LE-32BIT-NEXT:  .LBB10_57:
-; LE-32BIT-NEXT:    bc 12, 10, .LBB10_58
+; LE-32BIT-NEXT:    bc 12, 30, .LBB10_58
 ; LE-32BIT-NEXT:    b .LBB10_59
 ; LE-32BIT-NEXT:  .LBB10_58:
 ; LE-32BIT-NEXT:    addi 27, 11, 0
 ; LE-32BIT-NEXT:  .LBB10_59:
 ; LE-32BIT-NEXT:    stw 3, 20(16)
 ; LE-32BIT-NEXT:    or 3, 4, 7
 ; LE-32BIT-NEXT:    bc 12, 4, .LBB10_61
 ; LE-32BIT-NEXT:  # %bb.60:

 ; LE-32BIT-NEXT:  .LBB11_8:
 ; LE-32BIT-NEXT:    srw 19, 7, 31
 ; LE-32BIT-NEXT:    cmplwi 5, 30, 64
 ; LE-32BIT-NEXT:    cmplwi 1, 30, 128
 ; LE-32BIT-NEXT:    slw 3, 29, 3
 ; LE-32BIT-NEXT:    or 19, 18, 19
 ; LE-32BIT-NEXT:    cmpwi 6, 31, 1
 ; LE-32BIT-NEXT:    sraw 18, 12, 31
-; LE-32BIT-NEXT:    crand 28, 4, 20
+; LE-32BIT-NEXT:    crand 21, 4, 20
 ; LE-32BIT-NEXT:    srawi 14, 12, 31
 ; LE-32BIT-NEXT:    sraw 31, 12, 30
 ; LE-32BIT-NEXT:    or 3, 21, 3
 ; LE-32BIT-NEXT:    slw 21, 8, 15
 ; LE-32BIT-NEXT:    bc 12, 24, .LBB11_10
 ; LE-32BIT-NEXT:  # %bb.9:
 ; LE-32BIT-NEXT:    ori 28, 18, 0
 ; LE-32BIT-NEXT:    b .LBB11_11
 ; LE-32BIT-NEXT:  .LBB11_10:
 ; LE-32BIT-NEXT:    addi 28, 17, 0
 ; LE-32BIT-NEXT:  .LBB11_11:
-; LE-32BIT-NEXT:    bc 12, 28, .LBB11_13
+; LE-32BIT-NEXT:    bc 12, 21, .LBB11_13
 ; LE-32BIT-NEXT:  # %bb.12:
 ; LE-32BIT-NEXT:    ori 18, 14, 0
 ; LE-32BIT-NEXT:    b .LBB11_14
 ; LE-32BIT-NEXT:  .LBB11_13:
 ; LE-32BIT-NEXT:    addi 18, 31, 0
 ; LE-32BIT-NEXT:  .LBB11_14:
 ; LE-32BIT-NEXT:    or 21, 20, 21
 ; LE-32BIT-NEXT:    subfic 20, 16, 64

 ; LE-32BIT-NEXT:    addi 10, 21, 0
 ; LE-32BIT-NEXT:  .LBB11_19:
 ; LE-32BIT-NEXT:    lwz 9, 36(1) # 4-byte Folded Reload
 ; LE-32BIT-NEXT:    bc 12, 20, .LBB11_21
 ; LE-32BIT-NEXT:  # %bb.20:
 ; LE-32BIT-NEXT:    ori 24, 22, 0
 ; LE-32BIT-NEXT:    b .LBB11_21
 ; LE-32BIT-NEXT:  .LBB11_21:
-; LE-32BIT-NEXT:    cmplwi 2, 19, 0
-; LE-32BIT-NEXT:    bc 12, 10, .LBB11_22
+; LE-32BIT-NEXT:    cmplwi 7, 19, 0
+; LE-32BIT-NEXT:    cmplwi 2, 16, 64
+; LE-32BIT-NEXT:    bc 12, 30, .LBB11_22
 ; LE-32BIT-NEXT:    b .LBB11_23
 ; LE-32BIT-NEXT:  .LBB11_22:
 ; LE-32BIT-NEXT:    addi 3, 6, 0
 ; LE-32BIT-NEXT:  .LBB11_23:
 ; LE-32BIT-NEXT:    cmplwi 3, 16, 0
 ; LE-32BIT-NEXT:    srw 25, 9, 30
 ; LE-32BIT-NEXT:    or 25, 25, 0
 ; LE-32BIT-NEXT:    srw 0, 7, 19
 ; LE-32BIT-NEXT:    or 26, 0, 26
 ; LE-32BIT-NEXT:    srw 0, 7, 30
 ; LE-32BIT-NEXT:    or 11, 0, 23
-; LE-32BIT-NEXT:    bc 12, 28, .LBB11_25
+; LE-32BIT-NEXT:    bc 12, 21, .LBB11_25
 ; LE-32BIT-NEXT:  # %bb.24:
 ; LE-32BIT-NEXT:    ori 0, 14, 0
 ; LE-32BIT-NEXT:    b .LBB11_26
 ; LE-32BIT-NEXT:  .LBB11_25:
 ; LE-32BIT-NEXT:    addi 0, 28, 0
 ; LE-32BIT-NEXT:  .LBB11_26:
 ; LE-32BIT-NEXT:    slw 28, 6, 16
 ; LE-32BIT-NEXT:    stw 0, 4(4)
 ; LE-32BIT-NEXT:    slw 0, 29, 16
 ; LE-32BIT-NEXT:    lwz 4, 52(1) # 4-byte Folded Reload
 ; LE-32BIT-NEXT:    or 5, 0, 5
 ; LE-32BIT-NEXT:    lwz 0, 56(1) # 4-byte Folded Reload
-; LE-32BIT-NEXT:    cmplwi 7, 16, 64
 ; LE-32BIT-NEXT:    slw 23, 6, 15
 ; LE-32BIT-NEXT:    srw 22, 17, 4
 ; LE-32BIT-NEXT:    li 15, 0
 ; LE-32BIT-NEXT:    sraw 21, 12, 0
-; LE-32BIT-NEXT:    bc 12, 28, .LBB11_28
+; LE-32BIT-NEXT:    bc 12, 8, .LBB11_28
 ; LE-32BIT-NEXT:  # %bb.27:
 ; LE-32BIT-NEXT:    ori 0, 15, 0
 ; LE-32BIT-NEXT:    b .LBB11_29
 ; LE-32BIT-NEXT:  .LBB11_28:
 ; LE-32BIT-NEXT:    addi 0, 28, 0
 ; LE-32BIT-NEXT:  .LBB11_29:
 ; LE-32BIT-NEXT:    bc 12, 20, .LBB11_31
 ; LE-32BIT-NEXT:  # %bb.30:

 ; LE-32BIT-NEXT:    bc 12, 20, .LBB11_40
 ; LE-32BIT-NEXT:  # %bb.39:
 ; LE-32BIT-NEXT:    ori 25, 15, 0
 ; LE-32BIT-NEXT:    b .LBB11_41
 ; LE-32BIT-NEXT:  .LBB11_40:
 ; LE-32BIT-NEXT:    addi 25, 6, 0
 ; LE-32BIT-NEXT:  .LBB11_41:
 ; LE-32BIT-NEXT:    lwz 6, 44(1) # 4-byte Folded Reload
-; LE-32BIT-NEXT:    bc 12, 28, .LBB11_43
+; LE-32BIT-NEXT:    bc 12, 8, .LBB11_43
 ; LE-32BIT-NEXT:  # %bb.42:
 ; LE-32BIT-NEXT:    ori 8, 27, 0
 ; LE-32BIT-NEXT:    ori 5, 23, 0
 ; LE-32BIT-NEXT:    b .LBB11_43
 ; LE-32BIT-NEXT:  .LBB11_43:
 ; LE-32BIT-NEXT:    bc 12, 2, .LBB11_44
 ; LE-32BIT-NEXT:    b .LBB11_45
 ; LE-32BIT-NEXT:  .LBB11_44:

 ; LE-32BIT-NEXT:    addi 30, 19, 0
 ; LE-32BIT-NEXT:  .LBB11_64:
 ; LE-32BIT-NEXT:    bc 12, 2, .LBB11_65
 ; LE-32BIT-NEXT:    b .LBB11_66
 ; LE-32BIT-NEXT:  .LBB11_65:
 ; LE-32BIT-NEXT:    addi 3, 16, 0
 ; LE-32BIT-NEXT:  .LBB11_66:
 ; LE-32BIT-NEXT:    stw 4, 8(18)
-; LE-32BIT-NEXT:    bc 12, 28, .LBB11_68
+; LE-32BIT-NEXT:    bc 12, 8, .LBB11_68
 ; LE-32BIT-NEXT:  # %bb.67:
 ; LE-32BIT-NEXT:    ori 27, 15, 0
 ; LE-32BIT-NEXT:    b .LBB11_69
 ; LE-32BIT-NEXT:  .LBB11_68:
 ; LE-32BIT-NEXT:    addi 27, 6, 0
 ; LE-32BIT-NEXT:  .LBB11_69:
 ; LE-32BIT-NEXT:    bc 12, 14, .LBB11_71
 ; LE-32BIT-NEXT:  # %bb.70:
 ; LE-32BIT-NEXT:    ori 6, 8, 0
 ; LE-32BIT-NEXT:    b .LBB11_72
 ; LE-32BIT-NEXT:  .LBB11_71:
 ; LE-32BIT-NEXT:    addi 6, 12, 0
 ; LE-32BIT-NEXT:  .LBB11_72:
 ; LE-32BIT-NEXT:    bc 12, 2, .LBB11_74
 ; LE-32BIT-NEXT:  # %bb.73:
 ; LE-32BIT-NEXT:    ori 8, 28, 0
 ; LE-32BIT-NEXT:    b .LBB11_75
 ; LE-32BIT-NEXT:  .LBB11_74:
 ; LE-32BIT-NEXT:    addi 8, 9, 0
 ; LE-32BIT-NEXT:  .LBB11_75:
-; LE-32BIT-NEXT:    bc 12, 10, .LBB11_77
+; LE-32BIT-NEXT:    bc 12, 30, .LBB11_77
 ; LE-32BIT-NEXT:  # %bb.76:
 ; LE-32BIT-NEXT:    ori 28, 26, 0
 ; LE-32BIT-NEXT:    b .LBB11_78
 ; LE-32BIT-NEXT:  .LBB11_77:
 ; LE-32BIT-NEXT:    addi 28, 7, 0
 ; LE-32BIT-NEXT:  .LBB11_78:
 ; LE-32BIT-NEXT:    stw 3, 28(18)
 ; LE-32BIT-NEXT:    or 7, 8, 27