[PowerPC] enable Policy.ShouldTrackLaneMasks

[tingwang]

Summary

This depends on D108902.

Once we started track subreg liveness, we shall enable this policy to model subregister usage better particularly for vector-pair registers. Unfortunately vector-pair is disabled on P10 right now, so I'm not able to show the real motivation case here.

This change did not observe performance change through test suite.

[tingwang]

Plan to enable 256bit vector ld/st codegen, and then add the motivation case.

llvm/lib/Target/PowerPC/PPCSubtarget.cpp

void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
   // We want to schedule from both the top and the bottom and so we set
   // OnlyBottomUp to false.
   // We want to do bi-directional scheduling since it provides a more balanced
   // schedule leading to better performance.
   Policy.OnlyBottomUp = false;
   // Spilling is generally expensive on all PPC cores, so always enable
   // register-pressure tracking.
   Policy.ShouldTrackPressure = true;
+  if (UseSubRegLiveness)
+    Policy.ShouldTrackLaneMasks = true;
 }
 
 bool PPCSubtarget::useAA() const {
   return true;
 }
 
 bool PPCSubtarget::enableSubRegLiveness() const {
   return UseSubRegLiveness;

llvm/test/CodeGen/PowerPC/mma-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names \
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names \
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
 
 ; assemble_acc
 declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
 define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: ass_acc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor vs3, v2, v2
-; CHECK-NEXT:    xxlor vs2, v2, v2
-; CHECK-NEXT:    xxlor vs0, vs2, vs2
-; CHECK-NEXT:    xxlor vs1, vs3, vs3
+; CHECK-NEXT:    xxlor vs1, v2, v2
+; CHECK-NEXT:    xxlor vs0, v2, v2
+; CHECK-NEXT:    xxlor vs2, vs0, vs0
+; CHECK-NEXT:    xxlor vs3, vs1, vs1
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
 ; CHECK-NEXT:    stxv vs2, 16(r3)
 ; CHECK-NEXT:    stxv vs3, 0(r3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: ass_acc:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxlor vs3, v2, v2
-; CHECK-BE-NEXT:    xxlor vs2, v2, v2
-; CHECK-BE-NEXT:    xxlor vs0, vs2, vs2
-; CHECK-BE-NEXT:    xxlor vs1, vs3, vs3
+; CHECK-BE-NEXT:    xxlor vs1, v2, v2
+; CHECK-BE-NEXT:    xxlor vs0, v2, v2
+; CHECK-BE-NEXT:    xxlor vs2, vs0, vs0
+; CHECK-BE-NEXT:    xxlor vs3, vs1, vs1
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
   store <512 x i1> %0, ptr %ptr, align 64
   ret void
 }
 
 ; xxmtacc
 declare <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1>)
 define void @int_xxmtacc(ptr %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: int_xxmtacc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor vs3, v2, v2
-; CHECK-NEXT:    xxlor vs2, v2, v2
-; CHECK-NEXT:    xxlor vs0, vs2, vs2
-; CHECK-NEXT:    xxlor vs1, vs3, vs3
+; CHECK-NEXT:    xxlor vs1, v2, v2
+; CHECK-NEXT:    xxlor vs0, v2, v2
+; CHECK-NEXT:    xxlor vs2, vs0, vs0
+; CHECK-NEXT:    xxlor vs3, vs1, vs1
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
 ; CHECK-NEXT:    stxv vs2, 16(r3)
 ; CHECK-NEXT:    stxv vs3, 0(r3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: int_xxmtacc:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxlor vs3, v2, v2
-; CHECK-BE-NEXT:    xxlor vs2, v2, v2
-; CHECK-BE-NEXT:    xxlor vs0, vs2, vs2
-; CHECK-BE-NEXT:    xxlor vs1, vs3, vs3
+; CHECK-BE-NEXT:    xxlor vs1, v2, v2
+; CHECK-BE-NEXT:    xxlor vs0, v2, v2
+; CHECK-BE-NEXT:    xxlor vs2, vs0, vs0
+; CHECK-BE-NEXT:    xxlor vs3, vs1, vs1
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
 ; One xxmtacc is generated from the call to assemble.acc then one xxmtacc is
 ; generated from the call to xxmtacc then one xxmfacc is generated for the store
   %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
   %1 = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> %0)
   store <512 x i1> %1, ptr %ptr, align 64
   ret void
 }
 
 ; xxmfacc
 declare <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1>)
 define void @int_xxmfacc(ptr %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: int_xxmfacc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor vs3, v2, v2
-; CHECK-NEXT:    xxlor vs2, v2, v2
-; CHECK-NEXT:    xxlor vs0, vs2, vs2
-; CHECK-NEXT:    xxlor vs1, vs3, vs3
+; CHECK-NEXT:    xxlor vs1, v2, v2
+; CHECK-NEXT:    xxlor vs0, v2, v2
+; CHECK-NEXT:    xxlor vs2, vs0, vs0
+; CHECK-NEXT:    xxlor vs3, vs1, vs1
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
 ; CHECK-NEXT:    stxv vs2, 16(r3)
 ; CHECK-NEXT:    stxv vs3, 0(r3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: int_xxmfacc:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxlor vs3, v2, v2
-; CHECK-BE-NEXT:    xxlor vs2, v2, v2
-; CHECK-BE-NEXT:    xxlor vs0, vs2, vs2
-; CHECK-BE-NEXT:    xxlor vs1, vs3, vs3
+; CHECK-BE-NEXT:    xxlor vs1, v2, v2
+; CHECK-BE-NEXT:    xxlor vs0, v2, v2
+; CHECK-BE-NEXT:    xxlor vs2, vs0, vs0
+; CHECK-BE-NEXT:    xxlor vs3, vs1, vs1
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
 ; One xxmtacc is generated from the call to assemble.acc then one xxmfacc is
 ; generated from the call to xxmfacc then one xxmfacc is generated for the store

llvm/test/CodeGen/PowerPC/mma-outer-product.ll

 ; CHECK-NEXT:    lxv v2, 0(r3)
 ; CHECK-NEXT:    lxv v3, 0(r4)
 ; CHECK-NEXT:    xxlor vs0, v2, v2
 ; CHECK-NEXT:    lxv v4, 0(r5)
 ; CHECK-NEXT:    lxv v5, 0(r6)
 ; CHECK-NEXT:    xxlor vs1, v3, v3
 ; CHECK-NEXT:    xxlor vs2, v4, v4
 ; CHECK-NEXT:    xxlor vs3, v5, v5
-; CHECK-NEXT:    vmr v1, v2
-; CHECK-NEXT:    vmr v0, v5
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    xvi8ger4pp acc0, v2, v3
 ; CHECK-NEXT:    xvf16ger2pn acc0, v2, v4
+; CHECK-NEXT:    vmr v4, v5
 ; CHECK-NEXT:    pmxvf32gernn acc0, v3, v5, 0, 0
-; CHECK-NEXT:    pmxvf64gernn acc0, vsp32, v2, 0, 0
+; CHECK-NEXT:    vmr v5, v2
+; CHECK-NEXT:    pmxvf64gernn acc0, vsp36, v2, 0, 0
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs3, 0(r3)
 ; CHECK-NEXT:    stxv vs2, 0(r4)
 ; CHECK-NEXT:    stxv vs1, 0(r5)
 ; CHECK-NEXT:    stxv vs0, 0(r6)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: intrinsics2:
 ; CHECK-BE:       # %bb.0:
 ; CHECK-BE-NEXT:    lxv v2, 0(r3)
 ; CHECK-BE-NEXT:    lxv v3, 0(r4)
 ; CHECK-BE-NEXT:    xxlor vs0, v2, v2
 ; CHECK-BE-NEXT:    lxv v4, 0(r5)
 ; CHECK-BE-NEXT:    lxv v5, 0(r6)
 ; CHECK-BE-NEXT:    xxlor vs1, v3, v3
 ; CHECK-BE-NEXT:    xxlor vs2, v4, v4
 ; CHECK-BE-NEXT:    xxlor vs3, v5, v5
-; CHECK-BE-NEXT:    vmr v1, v2
-; CHECK-BE-NEXT:    vmr v0, v5
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    xvi8ger4pp acc0, v2, v3
 ; CHECK-BE-NEXT:    xvf16ger2pn acc0, v2, v4
+; CHECK-BE-NEXT:    vmr v4, v5
 ; CHECK-BE-NEXT:    pmxvf32gernn acc0, v3, v5, 0, 0
-; CHECK-BE-NEXT:    pmxvf64gernn acc0, vsp32, v2, 0, 0
+; CHECK-BE-NEXT:    vmr v5, v2
+; CHECK-BE-NEXT:    pmxvf64gernn acc0, vsp36, v2, 0, 0
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs1, 0(r4)
 ; CHECK-BE-NEXT:    stxv vs2, 0(r5)
 ; CHECK-BE-NEXT:    stxv vs3, 0(r6)
 ; CHECK-BE-NEXT:    blr
   %vc1 = load <16 x i8>, ptr %ptr1, align 16
   %vc2 = load <16 x i8>, ptr %ptr2, align 16

llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll

 ; CHECK-NEXT:    .cfi_offset v29, -64
 ; CHECK-NEXT:    .cfi_offset v30, -48
 ; CHECK-NEXT:    .cfi_offset v31, -32
 ; CHECK-NEXT:    stxv v28, 96(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    stxv v29, 112(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    stxv v30, 128(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    stxv v31, 144(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    vmr v31, v5
-; CHECK-NEXT:    vmr v29, v3
 ; CHECK-NEXT:    vmr v30, v4
+; CHECK-NEXT:    vmr v29, v3
 ; CHECK-NEXT:    vmr v28, v2
 ; CHECK-NEXT:    std r30, 160(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    ld r30, 272(r1)
 ; CHECK-NEXT:    dmxxinstfdmr512 wacc0, vsp60, vsp62, 0
 ; CHECK-NEXT:    xvf16ger2pp wacc0, v2, v4
 ; CHECK-NEXT:    dmxxextfdmr512 wacc0, vsp36, vsp34, 0
 ; CHECK-NEXT:    stxvp vsp36, 64(r1)
 ; CHECK-NEXT:    stxvp vsp34, 32(r1)

 ; CHECK-BE-NEXT:    .cfi_offset v29, -64
 ; CHECK-BE-NEXT:    .cfi_offset v30, -48
 ; CHECK-BE-NEXT:    .cfi_offset v31, -32
 ; CHECK-BE-NEXT:    stxv v28, 176(r1) # 16-byte Folded Spill
 ; CHECK-BE-NEXT:    stxv v29, 192(r1) # 16-byte Folded Spill
 ; CHECK-BE-NEXT:    stxv v30, 208(r1) # 16-byte Folded Spill
 ; CHECK-BE-NEXT:    stxv v31, 224(r1) # 16-byte Folded Spill
 ; CHECK-BE-NEXT:    vmr v31, v5
-; CHECK-BE-NEXT:    vmr v29, v3
 ; CHECK-BE-NEXT:    vmr v30, v4
+; CHECK-BE-NEXT:    vmr v29, v3
 ; CHECK-BE-NEXT:    vmr v28, v2
 ; CHECK-BE-NEXT:    std r30, 240(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    ld r30, 368(r1)
 ; CHECK-BE-NEXT:    dmxxinstfdmr512 wacc0, vsp60, vsp62, 0
 ; CHECK-BE-NEXT:    xvf16ger2pp wacc0, v2, v4
 ; CHECK-BE-NEXT:    dmxxextfdmr512 wacc0, vsp36, vsp34, 0
 ; CHECK-BE-NEXT:    stxvp vsp36, 112(r1)
 ; CHECK-BE-NEXT:    stxvp vsp34, 144(r1)

llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll

 ; CHECK-NEXT:    extswsli r3, r3, 3
 ; CHECK-NEXT:    xvmaddadp v1, v4, v1
 ; CHECK-NEXT:    lxvdsx v5, 0, r3
 ; CHECK-NEXT:    xvmaddadp v0, v5, v0
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_1: # %bb9
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    addi r6, r6, 2
-; CHECK-NEXT:    lxv vs0, 16(0)
 ; CHECK-NEXT:    lxv vs1, -64(r5)
+; CHECK-NEXT:    lxv vs0, 16(0)
 ; CHECK-NEXT:    xxlxor vs7, vs7, vs7
 ; CHECK-NEXT:    xxlor vs3, v0, v0
 ; CHECK-NEXT:    xxlxor vs2, vs2, vs2
 ; CHECK-NEXT:    xxlxor vs12, vs12, vs12
-; CHECK-NEXT:    mulld r6, r6, r3
+; CHECK-NEXT:    lxv vs4, -16(r5)
 ; CHECK-NEXT:    xxlor vs10, v2, v2
-; CHECK-NEXT:    xxlor vs4, v2, v2
 ; CHECK-NEXT:    xxlor vs8, vs10, vs10
 ; CHECK-NEXT:    xxlor vs10, v1, v1
+; CHECK-NEXT:    mulld r6, r6, r3
 ; CHECK-NEXT:    xvmaddadp vs7, vs0, v5
 ; CHECK-NEXT:    xvmuldp vs6, vs0, v2
-; CHECK-NEXT:    lxv vs0, -16(r5)
 ; CHECK-NEXT:    xvmaddadp vs3, vs1, v2
 ; CHECK-NEXT:    xvmaddadp vs2, vs1, vs2
+; CHECK-NEXT:    xvmaddadp vs12, vs4, vs12
+; CHECK-NEXT:    xxlor vs0, v2, v2
 ; CHECK-NEXT:    lxvdsx v6, r6, r4
 ; CHECK-NEXT:    li r6, 0
 ; CHECK-NEXT:    xvmaddadp vs7, v2, v2
 ; CHECK-NEXT:    xvmaddadp vs6, v2, v2
-; CHECK-NEXT:    xvmaddadp vs12, vs0, vs12
+; CHECK-NEXT:    xxlor vs14, vs12, vs12
+; CHECK-NEXT:    xxlor vs12, v2, v2
 ; CHECK-NEXT:    xvmuldp v3, vs1, v6
 ; CHECK-NEXT:    xvmuldp vs11, v4, v6
-; CHECK-NEXT:    xvmuldp vs13, vs0, v6
+; CHECK-NEXT:    xvmuldp vs13, vs4, v6
 ; CHECK-NEXT:    xvmuldp vs5, v6, v2
-; CHECK-NEXT:    xxlor vs0, v2, v2
-; CHECK-NEXT:    xxlor vs14, vs12, vs12
-; CHECK-NEXT:    xxlor vs12, v2, v2
+; CHECK-NEXT:    xxlor vs4, v2, v2
 ; CHECK-NEXT:    xxlor vs1, v3, v3
 ; CHECK-NEXT:    xxlor vs9, vs11, vs11
 ; CHECK-NEXT:    xxlor vs15, vs13, vs13
 ; CHECK-NEXT:    xxmtacc acc1
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    xxmtacc acc2
 ; CHECK-NEXT:    xxmtacc acc3
 ; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0

 ; TRACKLIVE-NEXT:    extswsli r3, r3, 3
 ; TRACKLIVE-NEXT:    xvmaddadp v1, v4, v1
 ; TRACKLIVE-NEXT:    lxvdsx v5, 0, r3
 ; TRACKLIVE-NEXT:    xvmaddadp v0, v5, v0
 ; TRACKLIVE-NEXT:    .p2align 4
 ; TRACKLIVE-NEXT:  .LBB0_1: # %bb9
 ; TRACKLIVE-NEXT:    #
 ; TRACKLIVE-NEXT:    addi r6, r6, 2
-; TRACKLIVE-NEXT:    lxv vs0, 16(0)
 ; TRACKLIVE-NEXT:    lxv vs1, -64(r5)
+; TRACKLIVE-NEXT:    lxv vs0, 16(0)
 ; TRACKLIVE-NEXT:    xxlxor vs7, vs7, vs7
 ; TRACKLIVE-NEXT:    xxlor vs3, v0, v0
 ; TRACKLIVE-NEXT:    xxlxor vs2, vs2, vs2
 ; TRACKLIVE-NEXT:    xxlxor vs12, vs12, vs12
-; TRACKLIVE-NEXT:    mulld r6, r6, r3
+; TRACKLIVE-NEXT:    lxv vs4, -16(r5)
 ; TRACKLIVE-NEXT:    xxlor vs10, v2, v2
-; TRACKLIVE-NEXT:    xxlor vs4, v2, v2
 ; TRACKLIVE-NEXT:    xxlor vs8, vs10, vs10
 ; TRACKLIVE-NEXT:    xxlor vs10, v1, v1
+; TRACKLIVE-NEXT:    mulld r6, r6, r3
 ; TRACKLIVE-NEXT:    xvmaddadp vs7, vs0, v5
 ; TRACKLIVE-NEXT:    xvmuldp vs6, vs0, v2
-; TRACKLIVE-NEXT:    lxv vs0, -16(r5)
 ; TRACKLIVE-NEXT:    xvmaddadp vs3, vs1, v2
 ; TRACKLIVE-NEXT:    xvmaddadp vs2, vs1, vs2
+; TRACKLIVE-NEXT:    xvmaddadp vs12, vs4, vs12
+; TRACKLIVE-NEXT:    xxlor vs0, v2, v2
 ; TRACKLIVE-NEXT:    lxvdsx v6, r6, r4
 ; TRACKLIVE-NEXT:    li r6, 0
 ; TRACKLIVE-NEXT:    xvmaddadp vs7, v2, v2
 ; TRACKLIVE-NEXT:    xvmaddadp vs6, v2, v2
-; TRACKLIVE-NEXT:    xvmaddadp vs12, vs0, vs12
+; TRACKLIVE-NEXT:    xxlor vs14, vs12, vs12
+; TRACKLIVE-NEXT:    xxlor vs12, v2, v2
 ; TRACKLIVE-NEXT:    xvmuldp v3, vs1, v6
 ; TRACKLIVE-NEXT:    xvmuldp vs11, v4, v6
-; TRACKLIVE-NEXT:    xvmuldp vs13, vs0, v6
+; TRACKLIVE-NEXT:    xvmuldp vs13, vs4, v6
 ; TRACKLIVE-NEXT:    xvmuldp vs5, v6, v2
-; TRACKLIVE-NEXT:    xxlor vs0, v2, v2
-; TRACKLIVE-NEXT:    xxlor vs14, vs12, vs12
-; TRACKLIVE-NEXT:    xxlor vs12, v2, v2
+; TRACKLIVE-NEXT:    xxlor vs4, v2, v2
 ; TRACKLIVE-NEXT:    xxlor vs1, v3, v3
 ; TRACKLIVE-NEXT:    xxlor vs9, vs11, vs11
 ; TRACKLIVE-NEXT:    xxlor vs15, vs13, vs13
 ; TRACKLIVE-NEXT:    xxmtacc acc1
 ; TRACKLIVE-NEXT:    xxmtacc acc0
 ; TRACKLIVE-NEXT:    xxmtacc acc2
 ; TRACKLIVE-NEXT:    xxmtacc acc3
 ; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0