[PowerPC] Propagate undef from MMA assemble

[qiucf]

Summary

Unlike ordinary vector instructions, MMA/Pair are built and operated through intrinsics, so we can't automatically propagate undef information from some of the source vectors. This brings problem if enabling ppc-track-subreg-liveness.

[lkail]

llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll

4

I don't quite understand you both add a new option and change the IR. The IR is legal and if adding this new option leads to a crash, I think we should seek the reason behind it. Changing IR might be a workaround, but not addressing the root cause.

[qiucf]

llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll

4

I manually skipped removing xxmtacc-xxmfacc in pre-emit peephole, which satisfies machine verifier.

bb.0.dmblvi_entry:
  renamable $vsl3 = XXLXORz
  renamable $vsl0 = XXLXORz
  renamable $acc0 = XXMTACC killed renamable $acc0(tied-def 0)
  renamable $acc0 = XXMFACC killed renamable $acc0(tied-def 0)
  STXV killed renamable $vsl1, 0, $zero8 :: (store (s128) into `<16 x i8>* null`, align 1)

Here stxv is not error because acc0 is partially defined. Is that an expected state?

Anyway, here vsl1 is undefined, so it should be removed as if it's stxv undef, ... if we can track its state.

[qiucf]

I think we can abandon this since D109302 is created.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

     if (Subtarget.isPPC64())
       return DAG.getRegister(PPC::X13, MVT::i64);
     return DAG.getRegister(PPC::R2, MVT::i32);
 
   case Intrinsic::ppc_mma_disassemble_acc:
   case Intrinsic::ppc_vsx_disassemble_pair: {
     int NumVecs = 2;
     SDValue WideVec = Op.getOperand(1);
+
+    bool FromAssemble = false;
+    if (auto *VecIntrinsic = dyn_cast<ConstantSDNode>(WideVec.getOperand(0)))
+      if (VecIntrinsic->getZExtValue() == Intrinsic::ppc_mma_assemble_acc ||
+          VecIntrinsic->getZExtValue() == Intrinsic::ppc_vsx_assemble_pair)
+        FromAssemble = true;
+
     if (IntrinsicID == Intrinsic::ppc_mma_disassemble_acc) {
       NumVecs = 4;
       WideVec = DAG.getNode(PPCISD::XXMFACC, dl, MVT::v512i1, WideVec);
     }
     SmallVector<SDValue, 4> RetOps;
     for (int VecNo = 0; VecNo < NumVecs; VecNo++) {
+      // Propagate undef values if the source is just an assemble, otherwise
+      // we'll get incorrect code for subreg tracking.
+      if (FromAssemble) {
+        SDValue Assembler = (NumVecs == 4) ? WideVec.getOperand(0) : WideVec;
+        if (Assembler.getOperand(VecNo + 1).isUndef()) {
+          RetOps.push_back(DAG.getUNDEF(MVT::v16i8));
+          continue;
+        }
+      }
       SDValue Extract = DAG.getNode(
           PPCISD::EXTRACT_VSX_REG, dl, MVT::v16i8, WideVec,
           DAG.getConstant(Subtarget.isLittleEndian() ? NumVecs - 1 - VecNo
                                                      : VecNo,
                           dl, getPointerTy(DAG.getDataLayout())));
       RetOps.push_back(Extract);
     }
     return DAG.getMergeValues(RetOps, dl);

llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
-; RUN:    | FileCheck %s
+; RUN:     -ppc-track-subreg-liveness | FileCheck %s
 
 define void @copy_novsrp() local_unnamed_addr {
 ; CHECK-LABEL: copy_novsrp:
 ; CHECK:       # %bb.0: # %dmblvi_entry
-; CHECK-NEXT:    xxlxor v2, v2, v2
+; CHECK-NEXT:    xxlxor vs3, vs3, vs3
 ; CHECK-NEXT:    xxlxor vs0, vs0, vs0
-; CHECK-NEXT:    xxlor vs3, v2, v2
-; CHECK-NEXT:    stxv vs1, 0(0)
+; CHECK-NEXT:    stxv vs3, 0(0)
 dmblvi_entry:
   %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> undef, <16 x i8> undef, <16 x i8> zeroinitializer)
   %1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)
   %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2
+  %3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0
   store <16 x i8> %2, <16 x i8>* null, align 1
+  store <16 x i8> %3, <16 x i8>* null, align 1
   unreachable
 }
 
 declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
 declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)