[RISCV] Add test cases showing inefficient materialization for stores of immediates. NFC

[craig.topper]

Summary

DAGCombiner::visitStore can call GetDemandedBits which will remove
upper bits from immediates. The upper bits are important for good
materialization of negative constants on RISCV. GetDemandedBits is a
different mechanism than SimplifyDemandedBits so
TargetShrinkDemandedConstant can't block it.

As far as I know this behavior is unique to stores.

I think we can fix this in isel using a concept similar to D107658.

[frasercrmck]

Oh for a second I thought "bad" meant "incorrect". Perhaps something like "inefficient" is clearer?

[craig.topper]

In D107860#2939623, @frasercrmck wrote:

Oh for a second I thought "bad" meant "incorrect". Perhaps something like "inefficient" is clearer?

Fixed

[frasercrmck]

Cheers, LGTM

llvm/test/CodeGen/RISCV/imm.ll

 ; RV64I-NEXT:    addi a0, a0, 9
 ; RV64I-NEXT:    slli a0, a0, 13
 ; RV64I-NEXT:    addi a0, a0, 837
 ; RV64I-NEXT:    slli a0, a0, 12
 ; RV64I-NEXT:    addi a0, a0, 1656
 ; RV64I-NEXT:    ret
   ret i64 -1152921504301427080 ; 0xF000_0000_1234_5678
 }
+
+; FIXME: This should use a single ADDI for the immediate.
+define void @imm_store_i16_neg1(i16* %p) nounwind {
+; RV32I-LABEL: imm_store_i16_neg1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 16
+; RV32I-NEXT:    addi a1, a1, -1
+; RV32I-NEXT:    sh a1, 0(a0)
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: imm_store_i16_neg1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 16
+; RV64I-NEXT:    addiw a1, a1, -1
+; RV64I-NEXT:    sh a1, 0(a0)
+; RV64I-NEXT:    ret
+  store i16 -1, i16* %p
+  ret void
+}
+
+; FIXME: This should use a single ADDI for the immediate.
+define void @imm_store_i32_neg1(i32* %p) nounwind {
+; RV32I-LABEL: imm_store_i32_neg1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, -1
+; RV32I-NEXT:    sw a1, 0(a0)
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: imm_store_i32_neg1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, -1
+; RV64I-NEXT:    srli a1, a1, 32
+; RV64I-NEXT:    sw a1, 0(a0)
+; RV64I-NEXT:    ret
+  store i32 -1, i32* %p
+  ret void
+}