[VPlan] Use defined and ops VPValues to print VPInterleaveRecipe.

[fhahn]

Summary

This patch updates VPInterleaveRecipe::print to print the actual defined
VPValues for load groups and the store VPValue operands for store
groups.

The IR references may become outdated while transforming the VPlan and
the defined and stored VPValues always are up-to-date.

[Ayal]

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

9552

Would have been nice to iterate over the recipe's operands and/or def VPValues, instead of calling getOperand()/getVPValue() for each, but the former does not tell where the gaps are.

llvm/lib/Transforms/Vectorize/VPlan.h

1330

How about checking instead if the number of store operands is positive using
int getNumStoreOperands() const { return getNumOperands() - (HasMask ? 2 : 1); }
This can also serve getStoredValues(), so that isStore() isn't only an ifndef NDEBUG thing for printing.
Can alternatively have the constructor initialize a constant field, as the number of store operands does not change.

[fhahn]

Replace isStore with getNumStoreOperands as suggested by Ayal, thanks!

[Ayal]

Looks good to me, thanks!

[fhahn]

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

9552

Agreed! Perhaps it would be worth adding that information to the recipe, removing the requirement to reference the interleave group?

[Ayal]

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

9552

Agreed! It would be better to have the recipe record that information (and avoid keeping IG altogether), rather than rely on whether IG->getMember(i) returns an Instruction* or null, but refrain from using that Instruction.

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

void VPInterleaveRecipe::print(raw_ostream &O, const Twine &Indent,
   IG->getInsertPos()->printAsOperand(O, false);
   O << ", ";
   getAddr()->printAsOperand(O, SlotTracker);
   VPValue *Mask = getMask();
   if (Mask) {
     O << ", ";
     Mask->printAsOperand(O, SlotTracker);
   }
-  for (unsigned i = 0; i < IG->getFactor(); ++i)
-    if (Instruction *I = IG->getMember(i))
-      O << "\n" << Indent << "  " << VPlanIngredient(I) << " " << i;
+
+  unsigned OpIdx = 0;
+  for (unsigned i = 0; i < IG->getFactor(); ++i) {
+    if (!IG->getMember(i))
+      continue;
+    if (getNumStoreOperands() > 0) {
+      O << "\n" << Indent << "  store ";
+      getOperand(1 + OpIdx)->printAsOperand(O, SlotTracker);
+      O << " to index " << i;
+    } else {
+      O << "\n" << Indent << "  ";
+      getVPValue(OpIdx)->printAsOperand(O, SlotTracker);
+      O << " = load from index " << i;
+    }
+    ++OpIdx;
+  }
 }
 #endif
 
 void VPWidenCallRecipe::execute(VPTransformState &State) {
   State.ILV->widenCallInstruction(*cast<CallInst>(getUnderlyingInstr()), this,
                                   *this, State);
 }
 

llvm/lib/Transforms/Vectorize/VPlan.h

public:
   }
 
   /// Return the VPValues stored by this interleave group. If it is a load
   /// interleave group, return an empty ArrayRef.
   ArrayRef<VPValue *> getStoredValues() const {
     // The first operand is the address, followed by the stored values, followed
     // by an optional mask.
     return ArrayRef<VPValue *>(op_begin(), getNumOperands())
-        .slice(1, getNumOperands() - (HasMask ? 2 : 1));
+        .slice(1, getNumStoreOperands());
   }
 
   /// Generate the wide load or store, and shuffles.
   void execute(VPTransformState &State) override;
 
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
   /// Print the recipe.
   void print(raw_ostream &O, const Twine &Indent,
              VPSlotTracker &SlotTracker) const override;
 #endif
 
   const InterleaveGroup<Instruction> *getInterleaveGroup() { return IG; }
+
+  /// Returns the number of stored operands of this interleave group. Returns 0
+  /// for load interleave groups.
+  unsigned getNumStoreOperands() const {
+    return getNumOperands() - (HasMask ? 2 : 1);
+  }
 };
 
 /// A recipe to represent inloop reduction operations, performing a reduction on
 /// a vector operand into a scalar value, and adding the result to a chain.
 /// The Operands are {ChainOp, VecOp, [Condition]}.
 class VPReductionRecipe : public VPRecipeBase, public VPValue {
   /// The recurrence decriptor for the reduction in question.
   RecurrenceDescriptor *RdxDesc;

llvm/test/Transforms/LoopVectorize/vplan-printing.ll

 
 define void @print_interleave_groups(i32 %C, i32 %D) {
 ; CHECK-LABEL: Checking a loop in "print_interleave_groups"
 ; CHECK:       VPlan 'Initial VPlan for VF={4},UF>=1' {
 ; CHECK-NEXT:  for.body:
 ; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi 0, %iv.next
 ; CHECK-NEXT:   CLONE ir<%gep.AB.0> = getelementptr ir<@AB>, ir<0>, ir<%iv>
 ; CHECK-NEXT:   INTERLEAVE-GROUP with factor 4 at %AB.0, ir<%gep.AB.0>
-; CHECK-NEXT:     %AB.0 = load %gep.AB.0 0
-; CHECK-NEXT:     %AB.1 = load %gep.AB.1 1
-; CHECK-NEXT:     %AB.3 = load %gep.AB.3 3
+; CHECK-NEXT:     ir<%AB.0> = load from index 0
+; CHECK-NEXT:     ir<%AB.1> = load from index 1
+; CHECK-NEXT:     ir<%AB.3> = load from index 3
 ; CHECK-NEXT:   CLONE ir<%iv.plus.1> = add ir<%iv>, ir<1>
 ; CHECK-NEXT:   CLONE ir<%gep.AB.1> = getelementptr ir<@AB>, ir<0>, ir<%iv.plus.1>
 ; CHECK-NEXT:   CLONE ir<%iv.plus.2> = add ir<%iv>, ir<2>
 ; CHECK-NEXT:   CLONE ir<%iv.plus.3> = add ir<%iv>, ir<3>
 ; CHECK-NEXT:   CLONE ir<%gep.AB.3> = getelementptr ir<@AB>, ir<0>, ir<%iv.plus.3>
 ; CHECK-NEXT:   WIDEN ir<%add> = add ir<%AB.0>, ir<%AB.1>
 ; CHECK-NEXT:   CLONE ir<%gep.CD.0> = getelementptr ir<@CD>, ir<0>, ir<%iv>
 ; CHECK-NEXT:   CLONE ir<%gep.CD.1> = getelementptr ir<@CD>, ir<0>, ir<%iv.plus.1>
 ; CHECK-NEXT:   CLONE ir<%gep.CD.2> = getelementptr ir<@CD>, ir<0>, ir<%iv.plus.2>
 ; CHECK-NEXT:   CLONE ir<%gep.CD.3> = getelementptr ir<@CD>, ir<0>, ir<%iv.plus.3>
 ; CHECK-NEXT:   INTERLEAVE-GROUP with factor 4 at <badref>, ir<%gep.CD.3>
-; CHECK-NEXT:     store %add, %gep.CD.0 0
-; CHECK-NEXT:     store 1, %gep.CD.1 1
-; CHECK-NEXT:     store 2, %gep.CD.2 2
-; CHECK-NEXT:     store %AB.3, %gep.CD.3 3
+; CHECK-NEXT:     store ir<%add> to index 0
+; CHECK-NEXT:     store ir<1> to index 1
+; CHECK-NEXT:     store ir<2> to index 2
+; CHECK-NEXT:     store ir<%AB.3> to index 3
 ; CHECK-NEXT: No successors
 ; CHECK-NEXT: }
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]