[ARM][llvm-objdump] Annotate PC-relative memory operands of VLDR instructions

[ikudrin]

Summary

This extends D105979 and adds support for VLDR instructions.

[ikudrin]

• Fix Lint warnings

Ping.

[MaskRay]

llvm/test/tools/llvm-objdump/ELF/ARM/literal-vldr-thumb2.s

5

llvm-objdump can detect the triple, so you can omit --triple

[ikudrin]

llvm/test/tools/llvm-objdump/ELF/ARM/literal-vldr-thumb2.s

5

For some reason, if --triple is omitted, llvm-objdump fails to disassemble some instructions. In this test file, it can't handle nop, which breaks all instructions that follow.

llvm/include/llvm/MC/MCInstrAnalysis.h

public:
   /// Given a branch instruction try to get the address the branch
   /// targets. Return true on success, and the address in Target.
   virtual bool
   evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
                  uint64_t &Target) const;
 
   /// Given an instruction tries to get the address of a memory operand. Returns
   /// the address on success.
-  virtual Optional<uint64_t> evaluateMemoryOperandAddress(const MCInst &Inst,
-                                                          uint64_t Addr,
-                                                          uint64_t Size) const;
+  virtual Optional<uint64_t>
+  evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI,
+                               uint64_t Addr, uint64_t Size) const;
 
   /// Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
   virtual std::vector<std::pair<uint64_t, uint64_t>>
   findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
                  uint64_t GotPltSectionVA, const Triple &TargetTriple) const {
     return {};
   }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_MC_MCINSTRANALYSIS_H

llvm/lib/MC/MCInstrAnalysis.cpp

 }
 
 bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
                                      uint64_t /*Size*/,
                                      uint64_t & /*Target*/) const {
   return false;
 }
 
-Optional<uint64_t>
-MCInstrAnalysis::evaluateMemoryOperandAddress(const MCInst &Inst, uint64_t Addr,
-                                              uint64_t Size) const {
+Optional<uint64_t> MCInstrAnalysis::evaluateMemoryOperandAddress(
+    const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
   return None;
 }

llvm/lib/Target/ARM/ARMInstrInfo.td

 
 def addrmode5_pre : AddrMode5 {
    let PrintMethod = "printAddrMode5Operand<true>";
 }
 
 // addrmode5fp16 := reg +/- imm8*2
 //
 def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; }
-class AddrMode5FP16 : Operand<i32>,
+class AddrMode5FP16 : MemOperand,
                       ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> {
   let EncoderMethod = "getAddrMode5FP16OpValue";
   let DecoderMethod = "DecodeAddrMode5FP16Operand";
   let ParserMatchClass = AddrMode5FP16AsmOperand;
   let MIOperandInfo = (ops GPR:$base, i32imm);
 }
 
 def addrmode5fp16 : AddrMode5FP16 {

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

for (unsigned OpNum = 0; OpNum < Desc.getNumOperands(); ++OpNum) {
         Target = ARM_MC::evaluateBranchTarget(Desc, Addr, Imm);
         return true;
       }
     }
     return false;
   }
 
   Optional<uint64_t> evaluateMemoryOperandAddress(const MCInst &Inst,
+                                                  const MCSubtargetInfo *STI,
                                                   uint64_t Addr,
                                                   uint64_t Size) const override;
 };
 
 } // namespace
 
 static Optional<uint64_t>
 // NOLINTNEXTLINE(readability-identifier-naming)
static Optional<uint64_t> evaluateMemOpAddrForAddrMode5(const MCInst &Inst,
   ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm());
 
   if (Op == ARM_AM::sub)
     return Addr - ImmOffs * 4;
   return Addr + ImmOffs * 4;
 }
 
 static Optional<uint64_t>
+evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc,
+                                  unsigned MemOpIndex, uint64_t Addr) {
+  if (MemOpIndex + 1 >= Desc.getNumOperands())
+    return None;
+
+  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
+  const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
+  if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
+    return None;
+
+  unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm());
+  ARM_AM::AddrOpc Op = ARM_AM::getAM5FP16Op(MO2.getImm());
+
+  if (Op == ARM_AM::sub)
+    return Addr - ImmOffs * 2;
+  return Addr + ImmOffs * 2;
+}
+
+static Optional<uint64_t>
 // NOLINTNEXTLINE(readability-identifier-naming)
 evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc,
                                     unsigned MemOpIndex, uint64_t Addr) {
   if (MemOpIndex + 1 >= Desc.getNumOperands())
     return None;
 
   const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
   const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);

 static Optional<uint64_t>
 // NOLINTNEXTLINE(readability-identifier-naming)
 evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc,
                                  unsigned MemOpIndex, uint64_t Addr) {
   return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, MemOpIndex, Addr);
 }
 
 Optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress(
-    const MCInst &Inst, uint64_t Addr, uint64_t Size) const {
+    const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
+    uint64_t Size) const {
   const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
 
   // Only load instructions can have PC-relative memory addressing.
   if (!Desc.mayLoad())
     return None;
 
   // PC-relative addressing does not update the base register.
   uint64_t TSFlags = Desc.TSFlags;
Optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress(
   // is 4 bytes.
   switch (Desc.TSFlags & ARMII::FormMask) {
   default:
     Addr += 8;
     break;
   case ARMII::ThumbFrm:
     Addr += 4;
     break;
+  // VLDR* instructions share the same opcode (and thus the same form) for Arm
+  // and Thumb. Use a bit longer route through STI in that case.
+  case ARMII::VFPLdStFrm:
+    Addr += STI->getFeatureBits()[ARM::ModeThumb] ? 4 : 8;
+    break;
   }
 
   // Eveluate the address depending on the addressing mode
   unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
   switch (AddrMode) {
   default:
     return None;
   case ARMII::AddrMode_i12:
     return evaluateMemOpAddrForAddrMode_i12(Inst, Desc, OpIndex, Addr);
   case ARMII::AddrMode3:
     return evaluateMemOpAddrForAddrMode3(Inst, Desc, OpIndex, Addr);
   case ARMII::AddrMode5:
     return evaluateMemOpAddrForAddrMode5(Inst, Desc, OpIndex, Addr);
+  case ARMII::AddrMode5FP16:
+    return evaluateMemOpAddrForAddrMode5FP16(Inst, Desc, OpIndex, Addr);
   case ARMII::AddrModeT2_i8s4:
     return evaluateMemOpAddrForAddrModeT2_i8s4(Inst, Desc, OpIndex, Addr);
   case ARMII::AddrModeT2_pc:
     return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, OpIndex, Addr);
   case ARMII::AddrModeT1_s:
     return evaluateMemOpAddrForAddrModeT1_s(Inst, Desc, OpIndex, Addr);
   }
 }

llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp

 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
                                           raw_ostream &O) {
   // Do not print the exact form of the memory operand if it references a known
   // binary object.
   if (SymbolizeOperands && MIA) {
     uint64_t Target;
     if (MIA->evaluateBranch(*MI, 0, 0, Target))
       return;
-    if (MIA->evaluateMemoryOperandAddress(*MI, 0, 0))
+    if (MIA->evaluateMemoryOperandAddress(*MI, /*STI=*/nullptr, 0, 0))
       return;
   }
 
   const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
   const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
   const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp);
 
   O << markup("<mem:");

llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp

 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
                                             raw_ostream &O) {
   // Do not print the exact form of the memory operand if it references a known
   // binary object.
   if (SymbolizeOperands && MIA) {
     uint64_t Target;
     if (MIA->evaluateBranch(*MI, 0, 0, Target))
       return;
-    if (MIA->evaluateMemoryOperandAddress(*MI, 0, 0))
+    if (MIA->evaluateMemoryOperandAddress(*MI, /*STI=*/nullptr, 0, 0))
       return;
   }
   const MCOperand &BaseReg  = MI->getOperand(Op+X86::AddrBaseReg);
   unsigned ScaleVal         = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
   const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
   const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
 
   // If this has a segment register, print it.

llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

#include "X86GenSubtargetInfo.inc"
   std::vector<std::pair<uint64_t, uint64_t>>
   findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
                  uint64_t GotSectionVA,
                  const Triple &TargetTriple) const override;
 
   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
                       uint64_t &Target) const override;
   Optional<uint64_t> evaluateMemoryOperandAddress(const MCInst &Inst,
+                                                  const MCSubtargetInfo *STI,
                                                   uint64_t Addr,
                                                   uint64_t Size) const override;
 };
 
 #define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
 #include "X86GenSubtargetInfo.inc"
 
 bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI,
bool X86MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
   if (Inst.getNumOperands() == 0 ||
       Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
     return false;
   Target = Addr + Size + Inst.getOperand(0).getImm();
   return true;
 }
 
 Optional<uint64_t> X86MCInstrAnalysis::evaluateMemoryOperandAddress(
-    const MCInst &Inst, uint64_t Addr, uint64_t Size) const {
+    const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
+    uint64_t Size) const {
   const MCInstrDesc &MCID = Info->get(Inst.getOpcode());
   int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags);
   if (MemOpStart == -1)
     return None;
   MemOpStart += X86II::getOperandBias(MCID);
 
   const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg);
   const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg);

llvm/test/tools/llvm-objdump/ELF/ARM/literal-vldr-arm.s

+@@ Check that PC-relative memory addressing is annotated
+
+@ RUN: llvm-mc %s -triple=armv8a --mattr=+fullfp16 -filetype=obj | \
+@ RUN:   llvm-objdump -d --no-show-raw-insn --triple=armv8a --mattr=+fullfp16 - | \
+@ RUN:   FileCheck %s
+
+.text
+foo:
+@ CHECK:      00000000 <foo>:
+  .short 0x0102
+foo2:
+@ CHECK:      00000002 <foo2>:
+  .short 0x0304
+
+_start:
+@ CHECK:      00000004 <_start>:
+@@ Check AddrMode5 instructions, with positive and negative immediates
+  vldr d0, foo
+  vldr s0, bar
+@ CHECK-NEXT:    4: vldr    d0, [pc, #-12]          @ 0x0 <foo>
+@ CHECK-NEXT:    8: vldr    s0, [pc, #20]           @ 0x24 <bar>
+
+@@ Check that AddrMode5 instructions which do not use PC-relative addressing are
+@@ not annotated
+  vldr d0, [r1, #8]
+@ CHECK-NEXT:    c: vldr    d0, [r1, #8]{{$}}
+
+@@ Check AddrMode5FP16 instructions, with positive and negative immediates
+  vldr.16 s0, foo
+  vldr.16 s0, foo2
+  vldr.16 s1, bar
+  vldr.16 s1, bar2
+@ CHECK-NEXT:   10: vldr.16 s0, [pc, #-24]          @ 0x0 <foo>
+@ CHECK-NEXT:   14: vldr.16 s0, [pc, #-26]          @ 0x2 <foo2>
+@ CHECK-NEXT:   18: vldr.16 s1, [pc, #4]            @ 0x24 <bar>
+@ CHECK-NEXT:   1c: vldr.16 s1, [pc, #2]            @ 0x26 <bar2>
+
+@@ Check that AddrMode5FP16 instructions which do not use PC-relative addressing
+@@ are not annotated
+  vldr.16 s0, [r1, #8]
+@ CHECK-NEXT:   20: vldr.16 s0, [r1, #8]{{$}}
+
+bar:
+@ CHECK:      00000024 <bar>:
+  .short 0x0102
+bar2:
+@ CHECK:      00000026 <bar2>:
+  .short 0x0304

llvm/test/tools/llvm-objdump/ELF/ARM/literal-vldr-thumb2.s

+@@ Check that PC-relative memory addressing is annotated
+
+@ RUN: llvm-mc %s -triple=thumbv8a --mattr=+fullfp16 -filetype=obj | \
+@ RUN:   llvm-objdump -d --no-show-raw-insn --triple=thumbv8a --mattr=+fullfp16 - | \
+@ RUN:   FileCheck %s
+
+.text
+foo:
+@ CHECK:      00000000 <foo>:
+  .short 0x0102
+foo2:
+@ CHECK:      00000002 <foo2>:
+  .short 0x0304
+
+_start:
+@@ Check AddrMode5 instructions, with positive and negative immediates
+  .balign 4
+  vldr d0, foo
+  vldr s0, bar
+@ CHECK:         4: vldr      d0, [pc, #-8]           @ 0x0 <foo>
+@ CHECK-NEXT:    8: vldr      s0, [pc, #56]           @ 0x44 <bar>
+
+@@ Same instructions, but the addresses are not 4-byte aligned
+  nop
+  vldr d0, foo
+  vldr s0, bar
+@ CHECK:          e: vldr     d0, [pc, #-16]          @ 0x0 <foo>
+@ CHECK-NEXT:    12: vldr     s0, [pc, #48]           @ 0x44 <bar>
+
+@@ Check that AddrMode5 instructions which do not use PC-relative addressing are not annotated
+  vldr d0, [r1, #8]
+@ CHECK:         16: vldr     d0, [r1, #8]{{$}}
+
+@@ Check AddrMode5FP16 instructions, with positive and negative immediates
+  .balign 4
+  vldr.16 s0, foo
+  vldr.16 s0, foo2
+  vldr.16 s1, bar
+  vldr.16 s1, bar2
+@ CHECK:         1c: vldr.16  s0, [pc, #-32]          @ 0x0 <foo>
+@ CHECK-NEXT:    20: vldr.16  s0, [pc, #-34]          @ 0x2 <foo2>
+@ CHECK-NEXT:    24: vldr.16  s1, [pc, #28]           @ 0x44 <bar>
+@ CHECK-NEXT:    28: vldr.16  s1, [pc, #26]           @ 0x46 <bar2>
+
+@@ Same instructions, but the addresses are not 4-byte aligned
+  nop
+  vldr.16 s0, foo
+  vldr.16 s0, foo2
+  vldr.16 s1, bar
+  vldr.16 s1, bar2
+@ CHECK:         2e: vldr.16  s0, [pc, #-48]          @ 0x0 <foo>
+@ CHECK-NEXT:    32: vldr.16  s0, [pc, #-50]          @ 0x2 <foo2>
+@ CHECK-NEXT:    36: vldr.16  s1, [pc, #12]           @ 0x44 <bar>
+@ CHECK-NEXT:    3a: vldr.16  s1, [pc, #10]           @ 0x46 <bar2>
+
+@@ Check that AddrMode5FP16 instructions which do not use PC-relative addressing are not annotated
+  vldr.16 s0, [r1, #8]
+@ CHECK:         3e: vldr.16  s0, [r1, #8]{{$}}
+
+  .balign 4
+bar:
+@ CHECK:      00000044 <bar>:
+  .short 0x0102
+bar2:
+@ CHECK:      00000046 <bar2>:
+  .short 0x0304

llvm/tools/llvm-objdump/llvm-objdump.cpp

for (unsigned SI = 0, SE = Symbols.size(); SI != SE; ++SI) {
             // Branch targets are printed just after the instructions.
             llvm::raw_ostream *TargetOS = &FOS;
             uint64_t Target;
             bool PrintTarget =
                 MIA->evaluateBranch(Inst, SectionAddr + Index, Size, Target);
             if (!PrintTarget)
               if (Optional<uint64_t> MaybeTarget =
                       MIA->evaluateMemoryOperandAddress(
-                          Inst, SectionAddr + Index, Size)) {
+                          Inst, STI, SectionAddr + Index, Size)) {
                 Target = *MaybeTarget;
                 PrintTarget = true;
                 // Do not print real address when symbolizing.
                 if (!SymbolizeOperands) {
                   // Memory operand addresses are printed as comments.
                   TargetOS = &CommentStream;
                   *TargetOS << "0x" << Twine::utohexstr(Target);
                 }