[SelectionDAG] Check use before combining into USUBSAT

[qiucf]

Summary

(The test part in this patch is not applicable since it's not pre-committed yet)

[RKSimon]

LGTM - cheers

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

     return SDValue();
 
   EVT SubVT = N->getValueType(0);
   SDValue Op0 = N->getOperand(0);
   SDValue Op1 = N->getOperand(1);
 
   // Try to find umax(a,b) - b or a - umin(a,b) patterns
   // they may be converted to usubsat(a,b).
-  if (Op0.getOpcode() == ISD::UMAX) {
+  if (Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) {
     SDValue MaxLHS = Op0.getOperand(0);
     SDValue MaxRHS = Op0.getOperand(1);
     if (MaxLHS == Op1)
       return getTruncatedUSUBSAT(DstVT, SubVT, MaxRHS, Op1, DAG, SDLoc(N));
     if (MaxRHS == Op1)
       return getTruncatedUSUBSAT(DstVT, SubVT, MaxLHS, Op1, DAG, SDLoc(N));
   }
 
-  if (Op1.getOpcode() == ISD::UMIN) {
+  if (Op1.getOpcode() == ISD::UMIN && Op1.hasOneUse()) {
     SDValue MinLHS = Op1.getOperand(0);
     SDValue MinRHS = Op1.getOperand(1);
     if (MinLHS == Op0)
       return getTruncatedUSUBSAT(DstVT, SubVT, Op0, MinRHS, DAG, SDLoc(N));
     if (MinRHS == Op0)
       return getTruncatedUSUBSAT(DstVT, SubVT, Op0, MinLHS, DAG, SDLoc(N));
   }
 
   // sub(a,trunc(umin(zext(a),b))) -> usubsat(a,trunc(umin(b,SatLimit)))
   if (Op1.getOpcode() == ISD::TRUNCATE &&
-      Op1.getOperand(0).getOpcode() == ISD::UMIN) {
+      Op1.getOperand(0).getOpcode() == ISD::UMIN &&
+      Op1.getOperand(0).hasOneUse()) {
     SDValue MinLHS = Op1.getOperand(0).getOperand(0);
     SDValue MinRHS = Op1.getOperand(0).getOperand(1);
     if (MinLHS.getOpcode() == ISD::ZERO_EXTEND && MinLHS.getOperand(0) == Op0)
       return getTruncatedUSUBSAT(DstVT, MinLHS.getValueType(), MinLHS, MinRHS,
                                  DAG, SDLoc(N));
     if (MinRHS.getOpcode() == ISD::ZERO_EXTEND && MinRHS.getOperand(0) == Op0)
       return getTruncatedUSUBSAT(DstVT, MinLHS.getValueType(), MinRHS, MinLHS,
                                  DAG, SDLoc(N));

llvm/test/CodeGen/PowerPC/sat-add.ll

; CHECK-NEXT:    blr
   ret i64 %sub
 }
 
 define i64 @unsigned_sat_constant_i64_with_multiple_use(i64 %x, i64 %y) {
 ; CHECK-LABEL: unsigned_sat_constant_i64_with_multiple_use:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 5, 4
 ; CHECK-NEXT:    cmpldi 3, 4
-; CHECK-NEXT:    addi 6, 3, -4
 ; CHECK-NEXT:    isellt 5, 3, 5
-; CHECK-NEXT:    cmpld 6, 3
-; CHECK-NEXT:    iselgt 3, 0, 6
+; CHECK-NEXT:    sub 3, 3, 5
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulld 3, 3, 4
 ; CHECK-NEXT:    blr
   %umin = call i64 @llvm.umin.i64(i64 %x, i64 4)
   %sub = sub i64 %x, %umin
   %add = add i64 %y, %umin
   %res = mul i64 %sub, %add
   ret i64 %res
 }
 
 declare i64 @llvm.umin.i64(i64, i64)