[SVE] Fix PromoteIntRes_TRUNCATE not to call getVectorNumElements

[sdesmalen]

The change looks fine to me, just have a nit for the test.

llvm/test/CodeGen/AArch64/sve-trunc.ll

196

nit: instead of using undef, can you add an extra argument to the function, i16 * %ptr? That way the test is more stable, since it always has to use x0 because of the ABI rules on parameter passing. For undef, the compiler is free to choose any value/register.

[sdesmalen]

LGTM, thanks @DylanFleming-arm

[CarolineConcatto]

Hey, is anyone else seeing:
Context not available.
In the files?

[Matt]

In D104115#2818870, @CarolineConcatto wrote:

Hey, is anyone else seeing:
Context not available.
In the files?

Yes for both llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp and llvm/test/CodeGen/AArch64/sve-trunc.ll.

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

case TargetLowering::TypeExpandInteger:
     Res = InOp;
     break;
   case TargetLowering::TypePromoteInteger:
     Res = GetPromotedInteger(InOp);
     break;
   case TargetLowering::TypeSplitVector: {
     EVT InVT = InOp.getValueType();
     assert(InVT.isVector() && "Cannot split scalar types");
-    unsigned NumElts = InVT.getVectorNumElements();
-    assert(NumElts == NVT.getVectorNumElements() &&
+    ElementCount NumElts = InVT.getVectorElementCount();
+    assert(NumElts == NVT.getVectorElementCount() &&
            "Dst and Src must have the same number of elements");
-    assert(isPowerOf2_32(NumElts) &&
+    assert(isPowerOf2_32(NumElts.getKnownMinValue()) &&
            "Promoted vector type must be a power of two");
 
     SDValue EOp1, EOp2;
     GetSplitVector(InOp, EOp1, EOp2);
 
     EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
-                                   NumElts/2);
+                                   NumElts.divideCoefficientBy(2));
     EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
     EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
 
     return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
   }
   case TargetLowering::TypeWidenVector: {
     SDValue WideInOp = GetWidenedVector(InOp);
 

llvm/test/CodeGen/AArch64/sve-trunc.ll

 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    and z0.b, z0.b, #0x1
 ; CHECK-NEXT:    cmpne p0.b, p0/z, z0.b, #0
 ; CHECK-NEXT:    ret
 entry:
   %out = trunc <vscale x 16 x i8> %in to <vscale x 16 x i1>
   ret <vscale x 16 x i1> %out
 }
+
+define void @trunc_promoteIntRes(<vscale x 4 x i64> %0, i16* %ptr) {
+; CHECK-LABEL: trunc_promoteIntRes:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uzp1 z0.s, z0.s, z1.s
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    st1h { z0.s }, p0, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %1 = trunc <vscale x 4 x i64> %0 to <vscale x 4 x i16>
+  %2 = bitcast i16* %ptr to <vscale x 4 x i16>*
+  store <vscale x 4 x i16> %1, <vscale x 4 x i16>* %2, align 2
+  ret void
+}
+