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[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
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Authored by critson on Jun 4 2021, 12:56 AM.

Details

Summary

Avoid having to round up to v8f32/VReg_256 when only 5 VGPRs are
required for a MIMG address operand.

Maintain _V8 instruction variants of pseudo instructions allowing
assembly prior to GFX10 to work as-is. Currently the validator
can tell for GFX10 what the correct size is, so will disallow
oversize address registers.

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Event Timeline

critson created this revision.Jun 4 2021, 12:56 AM
critson requested review of this revision.Jun 4 2021, 12:56 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 4 2021, 12:56 AM
foad added a reviewer: dp.Jun 4 2021, 3:09 AM

My only slight concern is if people have GFX10 disassemblies stored somewhere, they might find they can no longer reassemble them after your change. I don't know how serious that is.

Will there be a follow up patch to support v6f32/VReg_192? I think the register classes already exist for that.

My only slight concern is if people have GFX10 disassemblies stored somewhere, they might find they can no longer reassemble them after your change. I don't know how serious that is.

I believe we could allow these by changing the validator.

Will there be a follow up patch to support v6f32/VReg_192? I think the register classes already exist for that.

v6f32 is not actually defined in LLVM (MVT class), so I am not sure how possible this is. I realized this as I initially tried to include v6f32 support in this change.

rampitec accepted this revision.Jun 4 2021, 12:01 PM

I believe it was long needed.

This revision is now accepted and ready to land.Jun 4 2021, 12:01 PM
This revision was automatically updated to reflect the committed changes.