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[AMDGPU] Allow oversize vaddr in GFX10 MIMG assembly
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Authored by critson on Jun 4 2021, 7:33 PM.

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Summary

As a follow up to D103672, we should allow vaddr to be larger than
required when assembling GFX10 MIMG instructions.

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Event Timeline

critson created this revision.Jun 4 2021, 7:33 PM
critson requested review of this revision.Jun 4 2021, 7:33 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 4 2021, 7:33 PM
foad added a comment.Jun 7 2021, 3:05 AM

I think this needs some rationale in a comment explaining why the assembler is tolerant in this particular way.

dp added inline comments.Jun 7 2021, 3:20 AM
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
3459

To preserve backward compatibility with existing code it would be sufficient to allow size=8 when 5 is required. I'm not sure if we need to enable other cases.

As a minor note I think the code would be more readable if we do the following change:

VAddrSize -> ActualAddrSize
AddrSize -> ExpectedAddrSize
critson updated this revision to Diff 350240.Jun 7 2021, 4:11 AM
  • Address reviewer comments
dp accepted this revision.Jun 7 2021, 4:53 AM

LGTM

This revision is now accepted and ready to land.Jun 7 2021, 4:53 AM
This revision was automatically updated to reflect the committed changes.