[SelectionDAG] Extend FoldConstantVectorArithmetic to SPLAT_VECTOR

[frasercrmck]

Summary

This patch extends the SelectionDAG's ability to constant-fold vector
arithmetic to include support for SPLAT_VECTOR. This is not only for
scalable-vector types but also for fixed-length vector types, which
helps Hexagon in a couple of cases.

The original RISC-V test case was in fact an infinite DAGCombine loop.
The pattern and (truncate v1), (truncate v2) can be combined to
truncate (and v1, v2) but the truncate can similarly be combined back
to truncate (and v1, v2) (but, crucially, only when one of v1 or
v2 is a constant vector).

It wasn't exposed in on fixed-length types because a TRUNCATE of a
constant BUILD_VECTOR was folded into the BUILD_VECTOR itself, whereas
this did not happen for the equivalent (scalable-vector) SPLAT_VECTOR.

[RKSimon]

LGTM

[frasercrmck]

Thanks for the review, @RKSimon! I'm hoping to get someone like @kparzysz and @t.p.northover to review the changes in the other targets before I merge.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

5302

Why don't we need to check that the splat vector operand is constant/undef like we do for build_vector?

5374–5375

When I made similar changes to FoldConstantArithmetic, I was asked to create a splat vector if the input was splat vectors. Should we be consistent? Though maybe it's harder because you're dealing with more than 2 sources?

[frasercrmck]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

5302

Oh, good catch! I'm surprised nothing failed. I'll see to that.

5374–5375

Yeah that was my thinking, we may be dealing with mixed splat_vector and build_vector here. Hexagon would certainly exercise that path. We can't get it perfect here. We could certainly add heuristics like:

if all ScalarResults are equal, and:

1. if any Ops was a splat
2. if the majority of Ops were splats
3. splat is legal for this data type
4. splat is legal and custom for this data type

.. then produce a splat. Or a combination thereof. I'm not sure what's preferable. We could assume that the target would canonicalize any BUILD_VECTOR into SPLAT_VECTOR but I don't know if we can guarantee that either.

I'm also concerned that Hexagon seems to be the only target which uses SPLAT_VECTOR for fixed-length vectors and we don't have great coverage.

[frasercrmck]

• catch non-constant splat_vectors
• update rvv test checks

[frasercrmck]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

5302

I've updated to use ISD::isConstantSplatVector which isn't ideal but I didn't want to add yet-another method for checking these nodes.

[craig.topper]

LGTM

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

5374–5375

I believe there is a DAG combine that converts BUILD_VECTOR to SPLAT_VECTOR if it's legal/custom so it'll probably get taken care of.

It's kinda bold of Hexagon to use SPLAT_VECTOR with that DAG combine in there guaranteeing it will fold early with so many optimizations missing.

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

case ISD::FP_TO_FP16: {
       (void)V.convert(APFloat::IEEEhalf(),
                       APFloat::rmNearestTiesToEven, &Ignored);
       return getConstant(V.bitcastToAPInt().getZExtValue(), DL, VT);
     }
     }
   }
 
   // Constant fold unary operations with a vector integer or float operand.
-  if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Operand)) {
-    if (BV->isConstant()) {
-      switch (Opcode) {
-      default:
-        // FIXME: Entirely reasonable to perform folding of other unary
-        // operations here as the need arises.
-        break;
-      case ISD::FNEG:
-      case ISD::FABS:
-      case ISD::FCEIL:
-      case ISD::FTRUNC:
-      case ISD::FFLOOR:
-      case ISD::FP_EXTEND:
-      case ISD::FP_TO_SINT:
-      case ISD::FP_TO_UINT:
-      case ISD::TRUNCATE:
-      case ISD::ANY_EXTEND:
-      case ISD::ZERO_EXTEND:
-      case ISD::SIGN_EXTEND:
-      case ISD::UINT_TO_FP:
-      case ISD::SINT_TO_FP:
-      case ISD::ABS:
-      case ISD::BITREVERSE:
-      case ISD::BSWAP:
-      case ISD::CTLZ:
-      case ISD::CTLZ_ZERO_UNDEF:
-      case ISD::CTTZ:
-      case ISD::CTTZ_ZERO_UNDEF:
-      case ISD::CTPOP: {
-        SDValue Ops = { Operand };
-        if (SDValue Fold = FoldConstantVectorArithmetic(Opcode, DL, VT, Ops))
-          return Fold;
-      }
-      }
-    }
-  }
+    SDValue Ops = {Operand};
 
   unsigned OpOpcode = Operand.getNode()->getOpcode();
   switch (Opcode) {
   case ISD::STEP_VECTOR:
     assert(VT.isScalableVector() &&
            "STEP_VECTOR can only be used with scalable types");
     assert(VT.getScalarSizeInBits() >= 8 &&
            "STEP_VECTOR can only be used with vectors of integers that are at "
SDValue SelectionDAG::FoldConstantVectorArithmetic(unsigned Opcode,
 
   if (isUndef(Opcode, Ops))
     return getUNDEF(VT);
 
   // We can only fold vectors - maybe merge with FoldConstantArithmetic someday?
   if (!VT.isVector())
     return SDValue();
 
-  // TODO: All the folds below are performed lane-by-lane and assume a fixed
-  // vector width, however we should be able to do constant folds involving
-  // splat vector nodes too.
-  if (VT.isScalableVector())
-    return SDValue();
-
-  // From this point onwards all vectors are assumed to be fixed width.
-  unsigned NumElts = VT.getVectorNumElements();
+  ElementCount NumElts = VT.getVectorElementCount();
 
-  auto IsScalarOrSameVectorSize = [&](const SDValue &Op) {
+  auto IsScalarOrSameVectorSize = [NumElts](const SDValue &Op) {
     return !Op.getValueType().isVector() ||
-           Op.getValueType().getVectorNumElements() == NumElts;
+           Op.getValueType().getVectorElementCount() == NumElts;
   };
 
-  auto IsConstantBuildVectorOrUndef = [&](const SDValue &Op) {
+  auto IsConstantBuildVectorSplatVectorOrUndef = [](const SDValue &Op) {
+    APInt SplatVal;
     BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op);
-    return (Op.isUndef()) || (Op.getOpcode() == ISD::CONDCODE) ||
-           (BV && BV->isConstant());
+    return Op.isUndef() || Op.getOpcode() == ISD::CONDCODE ||
+           (BV && BV->isConstant()) ||
+           (Op.getOpcode() == ISD::SPLAT_VECTOR &&
+            ISD::isConstantSplatVector(Op.getNode(), SplatVal));
   };
 
   // All operands must be vector types with the same number of elements as
   // the result type and must be either UNDEF or a build vector of constant
   // or UNDEF scalars.
-  if (!llvm::all_of(Ops, IsConstantBuildVectorOrUndef) ||
+  if (!llvm::all_of(Ops, IsConstantBuildVectorSplatVectorOrUndef) ||
       !llvm::all_of(Ops, IsScalarOrSameVectorSize))
     return SDValue();
 
   // If we are comparing vectors, then the result needs to be a i1 boolean
   // that is then sign-extended back to the legal result type.
   EVT SVT = (Opcode == ISD::SETCC ? MVT::i1 : VT.getScalarType());
 
   // Find legal integer scalar type for constant promotion and
   // ensure that its scalar size is at least as large as source.
   EVT LegalSVT = VT.getScalarType();
   if (NewNodesMustHaveLegalTypes && LegalSVT.isInteger()) {
     LegalSVT = TLI->getTypeToTransformTo(*getContext(), LegalSVT);
     if (LegalSVT.bitsLT(VT.getScalarType()))
       return SDValue();
   }
 
+  // For scalable vector types we know we're dealing with SPLAT_VECTORs. We
+  // only have one operand to check. For fixed-length vector types we may have
+  // a combination of BUILD_VECTOR and SPLAT_VECTOR.
+  unsigned NumOperands = NumElts.isScalable() ? 1 : NumElts.getFixedValue();
+
   // Constant fold each scalar lane separately.
   SmallVector<SDValue, 4> ScalarResults;
-  for (unsigned i = 0; i != NumElts; i++) {
+  for (unsigned I = 0; I != NumOperands; I++) {
     SmallVector<SDValue, 4> ScalarOps;
     for (SDValue Op : Ops) {
       EVT InSVT = Op.getValueType().getScalarType();
-      BuildVectorSDNode *InBV = dyn_cast<BuildVectorSDNode>(Op);
-      if (!InBV) {
+      if (Op.getOpcode() != ISD::BUILD_VECTOR &&
+          Op.getOpcode() != ISD::SPLAT_VECTOR) {
         // We've checked that this is UNDEF or a constant of some kind.
         if (Op.isUndef())
           ScalarOps.push_back(getUNDEF(InSVT));
         else
           ScalarOps.push_back(Op);
         continue;
       }
 
-      SDValue ScalarOp = InBV->getOperand(i);
+      SDValue ScalarOp =
+          Op.getOperand(Op.getOpcode() == ISD::SPLAT_VECTOR ? 0 : I);
       EVT ScalarVT = ScalarOp.getValueType();
 
       // Build vector (integer) scalar operands may need implicit
       // truncation - do this before constant folding.
       if (ScalarVT.isInteger() && ScalarVT.bitsGT(InSVT))
         ScalarOp = getNode(ISD::TRUNCATE, DL, InSVT, ScalarOp);
 
       ScalarOps.push_back(ScalarOp);
     }
 
     // Constant fold the scalar operands.
     SDValue ScalarResult = getNode(Opcode, DL, SVT, ScalarOps, Flags);
 
     // Legalize the (integer) scalar constant if necessary.
     if (LegalSVT != SVT)
       ScalarResult = getNode(ISD::SIGN_EXTEND, DL, LegalSVT, ScalarResult);
 
     // Scalar folding only succeeded if the result is a constant or UNDEF.
     if (!ScalarResult.isUndef() && ScalarResult.getOpcode() != ISD::Constant &&
         ScalarResult.getOpcode() != ISD::ConstantFP)
       return SDValue();
     ScalarResults.push_back(ScalarResult);
   }
 
-  SDValue V = getBuildVector(VT, DL, ScalarResults);
+  SDValue V = NumElts.isScalable() ? getSplatVector(VT, DL, ScalarResults[0])
+                                   : getBuildVector(VT, DL, ScalarResults);
   NewSDValueDbgMsg(V, "New node fold constant vector: ", this);
   return V;
 }
 
 SDValue SelectionDAG::foldConstantFPMath(unsigned Opcode, const SDLoc &DL,
                                          EVT VT, SDValue N1, SDValue N2) {
   // TODO: We don't do any constant folding for strict FP opcodes here, but we
   //       should. That will require dealing with a potentially non-default

llvm/test/CodeGen/AArch64/sve-expand-div.ll

 ; UDIV
 ;
 
 define <vscale x 16 x i8> @udiv_i8(<vscale x 16 x i8> %a) #0 {
 ; CHECK-LABEL: udiv_i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z1.b, #-85 // =0xffffffffffffffab
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    mov z2.b, #1 // =0x1
-; CHECK-NEXT:    umulh z1.b, p0/m, z1.b, z0.b
-; CHECK-NEXT:    lsr z1.b, z1.b, #1
-; CHECK-NEXT:    cmpeq p0.b, p0/z, z2.b, #3
-; CHECK-NEXT:    sel z0.b, p0, z0.b, z1.b
+; CHECK-NEXT:    umulh z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT:    lsr z0.b, z0.b, #1
 ; CHECK-NEXT:    ret
   %div = udiv <vscale x 16 x i8> %a, shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 3, i32 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer)
   ret <vscale x 16 x i8> %div
 }
 
 define <vscale x 8 x i16> @udiv_i16(<vscale x 8 x i16> %a) #0 {
 ; CHECK-LABEL: udiv_i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #-21845
+; CHECK-NEXT:    mov z1.h, w8
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    mov z2.h, w8
-; CHECK-NEXT:    mov z1.h, #1 // =0x1
-; CHECK-NEXT:    umulh z2.h, p0/m, z2.h, z0.h
-; CHECK-NEXT:    lsr z2.h, z2.h, #1
-; CHECK-NEXT:    cmpeq p0.h, p0/z, z1.h, #3
-; CHECK-NEXT:    sel z0.h, p0, z0.h, z2.h
+; CHECK-NEXT:    umulh z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    lsr z0.h, z0.h, #1
 ; CHECK-NEXT:    ret
   %div = udiv <vscale x 8 x i16> %a, shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 3, i32 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer)
   ret <vscale x 8 x i16> %div
 }
 
 define <vscale x 4 x i32> @udiv_i32(<vscale x 4 x i32> %a) #0 {
 ; CHECK-LABEL: udiv_i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #43691
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
+; CHECK-NEXT:    mov z1.s, w8
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    mov z2.s, w8
-; CHECK-NEXT:    mov z1.s, #3 // =0x3
-; CHECK-NEXT:    umulh z2.s, p0/m, z2.s, z0.s
-; CHECK-NEXT:    lsr z2.s, z2.s, #1
-; CHECK-NEXT:    cmpeq p0.s, p0/z, z1.s, #1
-; CHECK-NEXT:    sel z0.s, p0, z0.s, z2.s
+; CHECK-NEXT:    umulh z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    lsr z0.s, z0.s, #1
 ; CHECK-NEXT:    ret
   %div = udiv <vscale x 4 x i32> %a, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 3, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
   ret <vscale x 4 x i32> %div
 }
 
 define <vscale x 2 x i64> @udiv_i64(<vscale x 2 x i64> %a) #0 {
 ; CHECK-LABEL: udiv_i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #-6148914691236517206
 ; CHECK-NEXT:    movk x8, #43691
+; CHECK-NEXT:    mov z1.d, x8
 ; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    mov z2.d, x8
-; CHECK-NEXT:    mov z1.d, #3 // =0x3
-; CHECK-NEXT:    umulh z2.d, p0/m, z2.d, z0.d
-; CHECK-NEXT:    lsr z2.d, z2.d, #1
-; CHECK-NEXT:    cmpeq p0.d, p0/z, z1.d, #1
-; CHECK-NEXT:    sel z0.d, p0, z0.d, z2.d
+; CHECK-NEXT:    umulh z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT:    lsr z0.d, z0.d, #1
 ; CHECK-NEXT:    ret
   %div = udiv <vscale x 2 x i64> %a, shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 3, i32 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer)
   ret <vscale x 2 x i64> %div
 }
 
 attributes #0 = { "target-features"="+sve" }

llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll

 
 define i32 @f1(<4 x i1>* %a0, <4 x i8> %a1) #0 {
 ; CHECK-LABEL: f1:
 ; CHECK:       // %bb.0: // %b0
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     r0 = memub(r0+#0)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r2 = #0
+; CHECK-NEXT:     r3:2 = combine(#0,#0)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     r5:4 = vsxtbh(r1)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r3:2 = vsxtbh(r2)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
 ; CHECK-NEXT:     p0 = r0
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     r1:0 = vmux(p0,r5:4,r3:2)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     r0 = vtrunehb(r1:0)
 ; CHECK-NEXT:    }
b0:
   store <8 x i1> %v1, <8 x i1>* %a0, align 1
   ret void
 }
 
 define void @f5(<4 x i1>* %a0, i32 %a1) #0 {
 ; CHECK-LABEL: f5:
 ; CHECK:       // %bb.0: // %b0
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r2 = #0
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     r5:4 = vsxtbh(r1)
+; CHECK-NEXT:     r3:2 = vsxtbh(r1)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r3:2 = vsxtbh(r2)
+; CHECK-NEXT:     r5:4 = combine(#0,#0)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     p0 = vcmph.eq(r5:4,r3:2)
+; CHECK-NEXT:     p0 = vcmph.eq(r3:2,r5:4)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     r1 = mux(p0,#0,#1)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     memb(r0+#0) = r1
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {

llvm/test/CodeGen/RISCV/rvv/constant-folding.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
+
+; These tests check that the scalable-vector version of this series of
+; instructions does not get into an infinite DAGCombine loop. This was
+; originally exposing an infinite loop between an 'and' of two truncates being promoted
+; to the larger value type, then that 'truncate' being split back up into an
+; 'and' of two truncates.
+; This didn't happen in the fixed-length test because a truncate of the
+; constant BUILD_VECTOR is folded into the BUILD_VECTOR itself. The truncate of
+; a constant SPLAT_VECTOR didn't follow suit.
+
+define <2 x i16> @fixedlen(<2 x i32> %x) {
+; RV32-LABEL: fixedlen:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
+; RV32-NEXT:    vsrl.vi v25, v8, 16
+; RV32-NEXT:    lui a0, 1048568
+; RV32-NEXT:    vand.vx v25, v25, a0
+; RV32-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
+; RV32-NEXT:    vnsrl.wi v8, v25, 0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: fixedlen:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
+; RV64-NEXT:    vsrl.vi v25, v8, 16
+; RV64-NEXT:    lui a0, 32
+; RV64-NEXT:    addiw a0, a0, -1
+; RV64-NEXT:    slli a0, a0, 15
+; RV64-NEXT:    vand.vx v25, v25, a0
+; RV64-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
+; RV64-NEXT:    vnsrl.wi v8, v25, 0
+; RV64-NEXT:    ret
+  %v41 = insertelement <2 x i32> undef, i32 16, i32 0
+  %v42 = shufflevector <2 x i32> %v41, <2 x i32> undef, <2 x i32> zeroinitializer
+  %v43 = lshr <2 x i32> %x, %v42
+  %v44 = trunc <2 x i32> %v43 to <2 x i16>
+  %v45 =  insertelement <2 x i32> undef, i32 -32768, i32 0
+  %v46 = shufflevector <2 x i32> %v45, <2 x i32> undef, <2 x i32> zeroinitializer
+  %v47 = trunc <2 x i32> %v46 to <2 x i16>
+  %v48 = and <2 x i16> %v44, %v47
+  ret <2 x i16> %v48
+}
+
+define <vscale x 2 x i16> @scalable(<vscale x 2 x i32> %x) {
+; CHECK-LABEL: scalable:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsrl.vi v25, v8, 16
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wi v25, v25, 0
+; CHECK-NEXT:    lui a0, 1048568
+; CHECK-NEXT:    vand.vx v8, v25, a0
+; CHECK-NEXT:    ret
+  %v41 = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
+  %v42 = shufflevector <vscale x 2 x i32> %v41, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %v43 = lshr <vscale x 2 x i32> %x, %v42
+  %v44 = trunc <vscale x 2 x i32> %v43 to <vscale x 2 x i16>
+  %v45 =  insertelement <vscale x 2 x i32> undef, i32 -32768, i32 0
+  %v46 = shufflevector <vscale x 2 x i32> %v45, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %v47 = trunc <vscale x 2 x i32> %v46 to <vscale x 2 x i16>
+  %v48 = and <vscale x 2 x i16> %v44, %v47
+  ret <vscale x 2 x i16> %v48
+}

llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll

 ; Check a setcc with two constant splats, which would previously get stuck in
 ; an infinite loop. DAGCombine isn't clever enough to constant-fold
 ; splat_vectors but could continuously swap the operands, trying to put the
 ; splat on the RHS.
 define <vscale x 8 x i1> @icmp_eq_ii_nxv8i8() {
 ; CHECK-LABEL: icmp_eq_ii_nxv8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vmv.v.i v25, 5
-; CHECK-NEXT:    vmseq.vi v0, v25, 2
+; CHECK-NEXT:    vmclr.m v0
 ; CHECK-NEXT:    ret
   %heada = insertelement <vscale x 8 x i8> undef, i8 5, i32 0
   %splata = shufflevector <vscale x 8 x i8> %heada, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %headb = insertelement <vscale x 8 x i8> undef, i8 2, i32 0
   %splatb = shufflevector <vscale x 8 x i8> %headb, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = icmp eq <vscale x 8 x i8> %splata, %splatb
   ret <vscale x 8 x i1> %vc
 }
 

llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll

 }
 
 define <vscale x 1 x i8> @vdivu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
-; CHECK-NEXT:    vsrl.vi v25, v25, 5
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v25, 5
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 ; Test V/1 to see if we can optimize it away for scalable vectors.

 }
 
 define <vscale x 2 x i8> @vdivu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
-; CHECK-NEXT:    vsrl.vi v25, v25, 5
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v25, 5
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vdivu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {

 }
 
 define <vscale x 4 x i8> @vdivu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
-; CHECK-NEXT:    vsrl.vi v25, v25, 5
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v25, 5
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vdivu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {

 }
 
 define <vscale x 8 x i8> @vdivu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
-; CHECK-NEXT:    vsrl.vi v25, v25, 5
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v25, 5
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vdivu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {

 }
 
 define <vscale x 16 x i8> @vdivu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
-; CHECK-NEXT:    vsrl.vi v26, v26, 5
-; CHECK-NEXT:    vmv.v.i v28, 1
-; CHECK-NEXT:    vmseq.vi v0, v28, -7
-; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v26, 5
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vdivu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {

 }
 
 define <vscale x 32 x i8> @vdivu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
-; CHECK-NEXT:    vsrl.vi v28, v28, 5
-; CHECK-NEXT:    vmv.v.i v12, 1
-; CHECK-NEXT:    vmseq.vi v0, v12, -7
-; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v28, 5
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = udiv <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vdivu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-NEXT:    ret
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vdivu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vmulhu.vx v16, v8, a0
-; CHECK-NEXT:    vsrl.vi v16, v16, 5
-; CHECK-NEXT:    vmv.v.i v24, 1
-; CHECK-NEXT:    vmseq.vi v0, v24, -7
-; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 5
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = udiv <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 1 x i16> @vdivu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {

 
 define <vscale x 1 x i16> @vdivu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
-; CHECK-NEXT:    vsrl.vi v25, v25, 13
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v25, 13
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vdivu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {

 
 define <vscale x 2 x i16> @vdivu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
-; CHECK-NEXT:    vsrl.vi v25, v25, 13
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v25, 13
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vdivu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {

 
 define <vscale x 4 x i16> @vdivu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
-; CHECK-NEXT:    vsrl.vi v25, v25, 13
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v25, 13
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vdivu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {

 
 define <vscale x 8 x i16> @vdivu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
-; CHECK-NEXT:    vsrl.vi v26, v26, 13
-; CHECK-NEXT:    vmv.v.i v28, 1
-; CHECK-NEXT:    vmseq.vi v0, v28, -7
-; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v26, 13
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vdivu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {

 
 define <vscale x 16 x i16> @vdivu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
-; CHECK-NEXT:    vsrl.vi v28, v28, 13
-; CHECK-NEXT:    vmv.v.i v12, 1
-; CHECK-NEXT:    vmseq.vi v0, v12, -7
-; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v28, 13
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vdivu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {

 }
 
 define <vscale x 32 x i16> @vdivu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vmulhu.vx v16, v8, a0
-; CHECK-NEXT:    vsrl.vi v16, v16, 13
-; CHECK-NEXT:    vmv.v.i v24, 1
-; CHECK-NEXT:    vmseq.vi v0, v24, -7
-; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 13
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = udiv <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 1 x i32> @vdivu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 1 x i32> @vdivu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vmv.v.i v25, -7
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v26, v8, a0
-; CHECK-NEXT:    vsrl.vi v26, v26, 29
-; CHECK-NEXT:    vmseq.vi v0, v25, 1
-; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v25, 29
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vdivu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vdivu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vmv.v.i v25, -7
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v26, v8, a0
-; CHECK-NEXT:    vsrl.vi v26, v26, 29
-; CHECK-NEXT:    vmseq.vi v0, v25, 1
-; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v25, 29
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vdivu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vdivu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vmv.v.i v26, -7
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v28, v8, a0
-; CHECK-NEXT:    vsrl.vi v28, v28, 29
-; CHECK-NEXT:    vmseq.vi v0, v26, 1
-; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v26, 29
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vdivu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vdivu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vmv.v.i v28, -7
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v12, v8, a0
-; CHECK-NEXT:    vsrl.vi v12, v12, 29
-; CHECK-NEXT:    vmseq.vi v0, v28, 1
-; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v28, 29
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vdivu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vdivu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vmv.v.i v16, -7
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v24, v8, a0
-; CHECK-NEXT:    vsrl.vi v24, v24, 29
-; CHECK-NEXT:    vmseq.vi v0, v16, 1
-; CHECK-NEXT:    vmerge.vvm v8, v24, v8, v0
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 29
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vdivu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-NEXT:    ret
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vdivu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    sw a0, 12(sp)
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v25, (a0), zero
-; CHECK-NEXT:    vmv.v.i v26, -7
 ; CHECK-NEXT:    vmulhu.vv v25, v8, v25
 ; CHECK-NEXT:    addi a0, zero, 61
-; CHECK-NEXT:    vsrl.vx v25, v25, a0
-; CHECK-NEXT:    vmseq.vi v0, v26, 1
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vx v8, v25, a0
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
; CHECK-NEXT:    ret
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vdivu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    sw a0, 12(sp)
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v26, (a0), zero
-; CHECK-NEXT:    vmv.v.i v28, -7
 ; CHECK-NEXT:    vmulhu.vv v26, v8, v26
 ; CHECK-NEXT:    addi a0, zero, 61
-; CHECK-NEXT:    vsrl.vx v26, v26, a0
-; CHECK-NEXT:    vmseq.vi v0, v28, 1
-; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
+; CHECK-NEXT:    vsrl.vx v8, v26, a0
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
; CHECK-NEXT:    ret
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vdivu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    sw a0, 12(sp)
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v28, (a0), zero
-; CHECK-NEXT:    vmv.v.i v12, -7
 ; CHECK-NEXT:    vmulhu.vv v28, v8, v28
 ; CHECK-NEXT:    addi a0, zero, 61
-; CHECK-NEXT:    vsrl.vx v28, v28, a0
-; CHECK-NEXT:    vmseq.vi v0, v12, 1
-; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
+; CHECK-NEXT:    vsrl.vx v8, v28, a0
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
; CHECK-NEXT:    ret
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vdivu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    sw a0, 12(sp)
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v16, (a0), zero
-; CHECK-NEXT:    vmv.v.i v24, -7
-; CHECK-NEXT:    vmulhu.vv v16, v8, v16
+; CHECK-NEXT:    vmulhu.vv v8, v8, v16
 ; CHECK-NEXT:    addi a0, zero, 61
-; CHECK-NEXT:    vsrl.vx v16, v16, a0
-; CHECK-NEXT:    vmseq.vi v0, v24, 1
-; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
+; CHECK-NEXT:    vsrl.vx v8, v8, a0
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 

llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll

 }
 
 define <vscale x 1 x i8> @vdivu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
-; CHECK-NEXT:    vsrl.vi v25, v25, 5
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v25, 5
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vdivu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {

 }
 
 define <vscale x 2 x i8> @vdivu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
-; CHECK-NEXT:    vsrl.vi v25, v25, 5
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v25, 5
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vdivu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {

 }
 
 define <vscale x 4 x i8> @vdivu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
-; CHECK-NEXT:    vsrl.vi v25, v25, 5
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v25, 5
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vdivu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {

 }
 
 define <vscale x 8 x i8> @vdivu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
-; CHECK-NEXT:    vsrl.vi v25, v25, 5
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v25, 5
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vdivu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {

 }
 
 define <vscale x 16 x i8> @vdivu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
-; CHECK-NEXT:    vsrl.vi v26, v26, 5
-; CHECK-NEXT:    vmv.v.i v28, 1
-; CHECK-NEXT:    vmseq.vi v0, v28, -7
-; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v26, 5
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vdivu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {

 }
 
 define <vscale x 32 x i8> @vdivu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
-; CHECK-NEXT:    vsrl.vi v28, v28, 5
-; CHECK-NEXT:    vmv.v.i v12, 1
-; CHECK-NEXT:    vmseq.vi v0, v12, -7
-; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v28, 5
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = udiv <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vdivu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-NEXT:    ret
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vdivu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vmulhu.vx v16, v8, a0
-; CHECK-NEXT:    vsrl.vi v16, v16, 5
-; CHECK-NEXT:    vmv.v.i v24, 1
-; CHECK-NEXT:    vmseq.vi v0, v24, -7
-; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 5
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = udiv <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 1 x i16> @vdivu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {

 
 define <vscale x 1 x i16> @vdivu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
-; CHECK-NEXT:    vsrl.vi v25, v25, 13
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v25, 13
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vdivu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {

 
 define <vscale x 2 x i16> @vdivu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
-; CHECK-NEXT:    vsrl.vi v25, v25, 13
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v25, 13
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vdivu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {

 
 define <vscale x 4 x i16> @vdivu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
-; CHECK-NEXT:    vsrl.vi v25, v25, 13
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v25, 13
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vdivu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {

 
 define <vscale x 8 x i16> @vdivu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
-; CHECK-NEXT:    vsrl.vi v26, v26, 13
-; CHECK-NEXT:    vmv.v.i v28, 1
-; CHECK-NEXT:    vmseq.vi v0, v28, -7
-; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v26, 13
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vdivu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {

 
 define <vscale x 16 x i16> @vdivu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
-; CHECK-NEXT:    vsrl.vi v28, v28, 13
-; CHECK-NEXT:    vmv.v.i v12, 1
-; CHECK-NEXT:    vmseq.vi v0, v12, -7
-; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v28, 13
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vdivu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {

 }
 
 define <vscale x 32 x i16> @vdivu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vmulhu.vx v16, v8, a0
-; CHECK-NEXT:    vsrl.vi v16, v16, 13
-; CHECK-NEXT:    vmv.v.i v24, 1
-; CHECK-NEXT:    vmseq.vi v0, v24, -7
-; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 13
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = udiv <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 1 x i32> @vdivu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {

 
 define <vscale x 1 x i32> @vdivu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
-; CHECK-NEXT:    vsrl.vi v25, v25, 29
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v25, 29
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vdivu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {

 
 define <vscale x 2 x i32> @vdivu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
-; CHECK-NEXT:    vsrl.vi v25, v25, 29
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v25, 29
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vdivu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {

 
 define <vscale x 4 x i32> @vdivu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
-; CHECK-NEXT:    vsrl.vi v26, v26, 29
-; CHECK-NEXT:    vmv.v.i v28, 1
-; CHECK-NEXT:    vmseq.vi v0, v28, -7
-; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v26, 29
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vdivu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {

 
 define <vscale x 8 x i32> @vdivu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
-; CHECK-NEXT:    vsrl.vi v28, v28, 29
-; CHECK-NEXT:    vmv.v.i v12, 1
-; CHECK-NEXT:    vmseq.vi v0, v12, -7
-; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
+; CHECK-NEXT:    vsrl.vi v8, v28, 29
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vdivu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {

 }
 
 define <vscale x 16 x i32> @vdivu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vmulhu.vx v16, v8, a0
-; CHECK-NEXT:    vsrl.vi v16, v16, 29
-; CHECK-NEXT:    vmv.v.i v24, 1
-; CHECK-NEXT:    vmseq.vi v0, v24, -7
-; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 29
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vdivu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vdivu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vmv.v.i v25, -7
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    slli a0, a0, 61
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 61
-; CHECK-NEXT:    vsrl.vx v26, v26, a0
-; CHECK-NEXT:    vmseq.vi v0, v25, 1
-; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
+; CHECK-NEXT:    vsrl.vx v8, v25, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vdivu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vdivu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vmv.v.i v26, -7
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    slli a0, a0, 61
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 61
-; CHECK-NEXT:    vsrl.vx v28, v28, a0
-; CHECK-NEXT:    vmseq.vi v0, v26, 1
-; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
+; CHECK-NEXT:    vsrl.vx v8, v26, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vdivu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vdivu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vmv.v.i v28, -7
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    slli a0, a0, 61
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v12, v8, a0
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 61
-; CHECK-NEXT:    vsrl.vx v12, v12, a0
-; CHECK-NEXT:    vmseq.vi v0, v28, 1
-; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
+; CHECK-NEXT:    vsrl.vx v8, v28, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vdivu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vdivu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vmv.v.i v16, -7
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    slli a0, a0, 61
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v24, v8, a0
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 61
-; CHECK-NEXT:    vsrl.vx v24, v24, a0
-; CHECK-NEXT:    vmseq.vi v0, v16, 1
-; CHECK-NEXT:    vmerge.vvm v8, v24, v8, v0
+; CHECK-NEXT:    vsrl.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 

llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll

 
 define <vscale x 1 x i8> @vremu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 5
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc

 
 define <vscale x 2 x i8> @vremu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 5
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc

 
 define <vscale x 4 x i8> @vremu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 5
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc

 
 define <vscale x 8 x i8> @vremu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 5
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc

 
 define <vscale x 16 x i8> @vremu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
 ; CHECK-NEXT:    vsrl.vi v26, v26, 5
-; CHECK-NEXT:    vmv.v.i v28, 1
-; CHECK-NEXT:    vmseq.vi v0, v28, -7
-; CHECK-NEXT:    vmerge.vvm v26, v26, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc

 
 define <vscale x 32 x i8> @vremu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
 ; CHECK-NEXT:    vsrl.vi v28, v28, 5
-; CHECK-NEXT:    vmv.v.i v12, 1
-; CHECK-NEXT:    vmseq.vi v0, v12, -7
-; CHECK-NEXT:    vmerge.vvm v28, v28, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc

 
 define <vscale x 64 x i8> @vremu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v16, v8, a0
 ; CHECK-NEXT:    vsrl.vi v16, v16, 5
-; CHECK-NEXT:    vmv.v.i v24, 1
-; CHECK-NEXT:    vmseq.vi v0, v24, -7
-; CHECK-NEXT:    vmerge.vvm v16, v16, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = urem <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc

 define <vscale x 1 x i16> @vremu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 13
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc

 define <vscale x 2 x i16> @vremu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 13
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc

 define <vscale x 4 x i16> @vremu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 13
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc

 define <vscale x 8 x i16> @vremu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
 ; CHECK-NEXT:    vsrl.vi v26, v26, 13
-; CHECK-NEXT:    vmv.v.i v28, 1
-; CHECK-NEXT:    vmseq.vi v0, v28, -7
-; CHECK-NEXT:    vmerge.vvm v26, v26, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc

 define <vscale x 16 x i16> @vremu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
 ; CHECK-NEXT:    vsrl.vi v28, v28, 13
-; CHECK-NEXT:    vmv.v.i v12, 1
-; CHECK-NEXT:    vmseq.vi v0, v12, -7
-; CHECK-NEXT:    vmerge.vvm v28, v28, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc

 define <vscale x 32 x i16> @vremu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v16, v8, a0
 ; CHECK-NEXT:    vsrl.vi v16, v16, 13
-; CHECK-NEXT:    vmv.v.i v24, 1
-; CHECK-NEXT:    vmseq.vi v0, v24, -7
-; CHECK-NEXT:    vmerge.vvm v16, v16, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 1 x i32> @vremu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vmv.v.i v25, -7
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v26, v8, a0
-; CHECK-NEXT:    vsrl.vi v26, v26, 29
-; CHECK-NEXT:    vmseq.vi v0, v25, 1
-; CHECK-NEXT:    vmerge.vvm v25, v26, v8, v0
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 29
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vremu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vmv.v.i v25, -7
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v26, v8, a0
-; CHECK-NEXT:    vsrl.vi v26, v26, 29
-; CHECK-NEXT:    vmseq.vi v0, v25, 1
-; CHECK-NEXT:    vmerge.vvm v25, v26, v8, v0
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 29
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vremu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vmv.v.i v26, -7
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v28, v8, a0
-; CHECK-NEXT:    vsrl.vi v28, v28, 29
-; CHECK-NEXT:    vmseq.vi v0, v26, 1
-; CHECK-NEXT:    vmerge.vvm v26, v28, v8, v0
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 29
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vremu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vmv.v.i v28, -7
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v12, v8, a0
-; CHECK-NEXT:    vsrl.vi v12, v12, 29
-; CHECK-NEXT:    vmseq.vi v0, v28, 1
-; CHECK-NEXT:    vmerge.vvm v28, v12, v8, v0
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 29
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vremu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vmv.v.i v16, -7
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v24, v8, a0
-; CHECK-NEXT:    vsrl.vi v24, v24, 29
-; CHECK-NEXT:    vmseq.vi v0, v16, 1
-; CHECK-NEXT:    vmerge.vvm v16, v24, v8, v0
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 29
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
; CHECK-NEXT:    ret
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    sw a0, 12(sp)
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v25, (a0), zero
-; CHECK-NEXT:    vmv.v.i v26, -7
 ; CHECK-NEXT:    vmulhu.vv v25, v8, v25
 ; CHECK-NEXT:    addi a0, zero, 61
 ; CHECK-NEXT:    vsrl.vx v25, v25, a0
-; CHECK-NEXT:    vmseq.vi v0, v26, 1
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i64> %va, %splat
; CHECK-NEXT:    ret
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    sw a0, 12(sp)
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v26, (a0), zero
-; CHECK-NEXT:    vmv.v.i v28, -7
 ; CHECK-NEXT:    vmulhu.vv v26, v8, v26
 ; CHECK-NEXT:    addi a0, zero, 61
 ; CHECK-NEXT:    vsrl.vx v26, v26, a0
-; CHECK-NEXT:    vmseq.vi v0, v28, 1
-; CHECK-NEXT:    vmerge.vvm v26, v26, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i64> %va, %splat
; CHECK-NEXT:    ret
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    sw a0, 12(sp)
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v28, (a0), zero
-; CHECK-NEXT:    vmv.v.i v12, -7
 ; CHECK-NEXT:    vmulhu.vv v28, v8, v28
 ; CHECK-NEXT:    addi a0, zero, 61
 ; CHECK-NEXT:    vsrl.vx v28, v28, a0
-; CHECK-NEXT:    vmseq.vi v0, v12, 1
-; CHECK-NEXT:    vmerge.vvm v28, v28, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i64> %va, %splat
; CHECK-NEXT:    ret
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vremu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    sw a0, 12(sp)
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v16, (a0), zero
-; CHECK-NEXT:    vmv.v.i v24, -7
 ; CHECK-NEXT:    vmulhu.vv v16, v8, v16
 ; CHECK-NEXT:    addi a0, zero, 61
 ; CHECK-NEXT:    vsrl.vx v16, v16, a0
-; CHECK-NEXT:    vmseq.vi v0, v24, 1
-; CHECK-NEXT:    vmerge.vvm v16, v16, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }

llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll

 
 define <vscale x 1 x i8> @vremu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 5
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc

 
 define <vscale x 2 x i8> @vremu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 5
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc

 
 define <vscale x 4 x i8> @vremu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 5
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc

 
 define <vscale x 8 x i8> @vremu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 5
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc

 
 define <vscale x 16 x i8> @vremu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
 ; CHECK-NEXT:    vsrl.vi v26, v26, 5
-; CHECK-NEXT:    vmv.v.i v28, 1
-; CHECK-NEXT:    vmseq.vi v0, v28, -7
-; CHECK-NEXT:    vmerge.vvm v26, v26, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc

 
 define <vscale x 32 x i8> @vremu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
 ; CHECK-NEXT:    vsrl.vi v28, v28, 5
-; CHECK-NEXT:    vmv.v.i v12, 1
-; CHECK-NEXT:    vmseq.vi v0, v12, -7
-; CHECK-NEXT:    vmerge.vvm v28, v28, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc

 
 define <vscale x 64 x i8> @vremu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v16, v8, a0
 ; CHECK-NEXT:    vsrl.vi v16, v16, 5
-; CHECK-NEXT:    vmv.v.i v24, 1
-; CHECK-NEXT:    vmseq.vi v0, v24, -7
-; CHECK-NEXT:    vmerge.vvm v16, v16, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = urem <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc

 define <vscale x 1 x i16> @vremu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 13
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc

 define <vscale x 2 x i16> @vremu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 13
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc

 define <vscale x 4 x i16> @vremu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 13
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc

 define <vscale x 8 x i16> @vremu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
 ; CHECK-NEXT:    vsrl.vi v26, v26, 13
-; CHECK-NEXT:    vmv.v.i v28, 1
-; CHECK-NEXT:    vmseq.vi v0, v28, -7
-; CHECK-NEXT:    vmerge.vvm v26, v26, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc

 define <vscale x 16 x i16> @vremu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
 ; CHECK-NEXT:    vsrl.vi v28, v28, 13
-; CHECK-NEXT:    vmv.v.i v12, 1
-; CHECK-NEXT:    vmseq.vi v0, v12, -7
-; CHECK-NEXT:    vmerge.vvm v28, v28, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc

 define <vscale x 32 x i16> @vremu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 2
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v16, v8, a0
 ; CHECK-NEXT:    vsrl.vi v16, v16, 13
-; CHECK-NEXT:    vmv.v.i v24, 1
-; CHECK-NEXT:    vmseq.vi v0, v24, -7
-; CHECK-NEXT:    vmerge.vvm v16, v16, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc

 define <vscale x 1 x i32> @vremu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 29
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc

 define <vscale x 2 x i32> @vremu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    vsrl.vi v25, v25, 29
-; CHECK-NEXT:    vmv.v.i v26, 1
-; CHECK-NEXT:    vmseq.vi v0, v26, -7
-; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc

 define <vscale x 4 x i32> @vremu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v26, v8, a0
 ; CHECK-NEXT:    vsrl.vi v26, v26, 29
-; CHECK-NEXT:    vmv.v.i v28, 1
-; CHECK-NEXT:    vmseq.vi v0, v28, -7
-; CHECK-NEXT:    vmerge.vvm v26, v26, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc

 define <vscale x 8 x i32> @vremu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v28, v8, a0
 ; CHECK-NEXT:    vsrl.vi v28, v28, 29
-; CHECK-NEXT:    vmv.v.i v12, 1
-; CHECK-NEXT:    vmseq.vi v0, v12, -7
-; CHECK-NEXT:    vmerge.vvm v28, v28, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc

 define <vscale x 16 x i32> @vremu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 131072
 ; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vmulhu.vx v16, v8, a0
 ; CHECK-NEXT:    vsrl.vi v16, v16, 29
-; CHECK-NEXT:    vmv.v.i v24, 1
-; CHECK-NEXT:    vmseq.vi v0, v24, -7
-; CHECK-NEXT:    vmerge.vvm v16, v16, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vmv.v.i v25, -7
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    slli a0, a0, 61
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 61
-; CHECK-NEXT:    vsrl.vx v26, v26, a0
-; CHECK-NEXT:    vmseq.vi v0, v25, 1
-; CHECK-NEXT:    vmerge.vvm v25, v26, v8, v0
+; CHECK-NEXT:    vsrl.vx v25, v25, a0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vmv.v.i v26, -7
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    slli a0, a0, 61
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 61
-; CHECK-NEXT:    vsrl.vx v28, v28, a0
-; CHECK-NEXT:    vmseq.vi v0, v26, 1
-; CHECK-NEXT:    vmerge.vvm v26, v28, v8, v0
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vmv.v.i v28, -7
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    slli a0, a0, 61
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v12, v8, a0
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 61
-; CHECK-NEXT:    vsrl.vx v12, v12, a0
-; CHECK-NEXT:    vmseq.vi v0, v28, 1
-; CHECK-NEXT:    vmerge.vvm v28, v12, v8, v0
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vremu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vmv.v.i v16, -7
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    slli a0, a0, 61
 ; CHECK-NEXT:    addi a0, a0, 1
-; CHECK-NEXT:    vmulhu.vx v24, v8, a0
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
 ; CHECK-NEXT:    addi a0, zero, 61
-; CHECK-NEXT:    vsrl.vx v24, v24, a0
-; CHECK-NEXT:    vmseq.vi v0, v16, 1
-; CHECK-NEXT:    vmerge.vvm v16, v24, v8, v0
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }