[XCOFF][AIX] Peephole optimization for small code model TocData transformations

[sfertile]

Summary

This patch is a followup to D101178.

In the patch, we enable peephole optimization (when possible) for the toc data transformation.

For example, with this patch would allow for the following assembly code:

la 4, i[TD](2) 
stw 3, 0(4)

to be transformed to the following instead:

stw 3, i[TD](2)

This patch can only be merged in after D101178 has been accepted and merged into LLVM.

[sfertile]

Awesome work Sidarth, patch looks really good. I've got one initial comment.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

7539

This flag represents emitting a specific relocation (ie producing an object file) or a specific relocation specifier (if producing assembly) in this case it means emitting sym@toc@l which means the low 16-bits of the offset from the toc-pointer to 'sym'. Our symbol reference on the ADDItoc doesn't need any flags to modify it.

[sidbav]

Address Review comments

[sidbav]

fix some formatting issues

[sfertile]

rebase patch and update the testing.

[stefanp]

Note that I have reviewed this patch along with https://reviews.llvm.org/D118718. The following comment applies to both patches.

There is one concern with respect to alignment.
I've created the following test case:

define i64 @read() {
  %1  = load i32, i32* @i1, align 1
  %2  = sext i32 %1 to i64
  ret i64 %2
}

The assembly we create (using llc -mtriple powerpc64-ibm-aix-xcoff test.ll) is as follows:

.read:
# %bb.0:
	lwa 3, i1[TD](2)
	blr

The issue is that the original ADDI instruction is a D-Form and so no alignment is required. However, LWA is DS form and if the alignment for i1 is not a multiple of 4 then the linker won't have a way to fill in that value.

llvm/test/CodeGen/PowerPC/toc-data-const.ll

4

nit:
Forgot the : after the RUN.

[sfertile]

Combined both 32-bit and 64-bit patches and addressed Stephans comment about the under-aligned DS-form instructions.

[stefanp]

I have one minor nit and that's it. Otherwise LGTM.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

7651

nit:
Just add a comment here to say that PPC::ADDItoc and PPC::ADDItoc8 are only used for AIX small code model.
It's not obvious from the name of the pseudo instruction so this tripped me up initially.

[hubert.reinterpretcast]

I believe https://github.com/llvm/llvm-project/issues/63927 is related to this patch.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

case PPC::ADDI:
       break;
     case PPC::ADDIdtprelL:
       Flags = PPCII::MO_DTPREL_LO;
       break;
     case PPC::ADDItlsldL:
       Flags = PPCII::MO_TLSLD_LO;
       break;
     case PPC::ADDItocL:
       Flags = PPCII::MO_TOC_LO;
       break;
+    case PPC::ADDItoc:
+    case PPC::ADDItoc8:
+      if (RequiresMod4Offset) {
+        if (GlobalAddressSDNode *GA =
+                dyn_cast<GlobalAddressSDNode>(Base.getOperand(0))) {
+          const GlobalValue *GV = GA->getGlobal();
+          Align Alignment = GV->getPointerAlignment(CurDAG->getDataLayout());
+          // XMC_TD global that is underaligned being accessed with a DS form
+          // instruction.
+          if (Alignment < 4)
+            continue;
+        }
+      }
+      break;
     }
 
     SDValue ImmOpnd = Base.getOperand(1);
 
     // On PPC64, the TOC base pointer is guaranteed by the ABI only to have
     // 8-byte alignment, and so we can only use offsets less than 8 (otherwise,
     // we might have needed different @ha relocation values for the offset
     // pointers).
if (ReplaceFlags) {
       } else if (ConstantPoolSDNode *CP =
                  dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
         const Constant *C = CP->getConstVal();
         ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64, CP->getAlign(),
                                                 Offset, Flags);
       }
     }
 
+    const unsigned BaseOpcode = Base.getMachineOpcode();
+    const bool OpcodeIsAIXTocData =
+        BaseOpcode == PPC::ADDItoc || BaseOpcode == PPC::ADDItoc8;
+
     if (FirstOp == 1) // Store
+      if (OpcodeIsAIXTocData)
+        (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0),
+                                         Base.getOperand(0), Base.getOperand(1),
+                                         N->getOperand(3));
+      else
         (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
                                          Base.getOperand(0), N->getOperand(3));
     else // Load
+      if (OpcodeIsAIXTocData)
+        (void)CurDAG->UpdateNodeOperands(N, Base.getOperand(0),
+                                         Base.getOperand(1), N->getOperand(2));
+      else
         (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
                                          N->getOperand(2));
 
     if (UpdateHBase)
       (void)CurDAG->UpdateNodeOperands(HBase.getNode(), HBase.getOperand(0),
                                        ImmOpnd);
 
     // The add-immediate may now be dead, in which case remove it.
     if (Base.getNode()->use_empty())
       CurDAG->RemoveDeadNode(Base.getNode());

llvm/lib/Target/PowerPC/PPCMCInstLower.cpp

static MCSymbol *GetSymbolFromOperand(const MachineOperand &MO,
   MCContext &Ctx = AP.OutContext;
 
   SmallString<128> Name;
   if (!MO.isGlobal()) {
     assert(MO.isSymbol() && "Isn't a symbol reference");
     Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL);
   } else {
     const GlobalValue *GV = MO.getGlobal();
+    if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
+      if (GVar->hasAttribute("toc-data"))
+        return TM.getSymbol(GV);
+
     TM.getNameWithPrefix(Name, GV, Mang);
   }
 
   MCSymbol *Sym = Ctx.getOrCreateSymbol(Name);
 
   return Sym;
 }
 

llvm/test/CodeGen/PowerPC/toc-data-const.ll

-; RUN: llc -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s --check-prefix CHECK
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s --check-prefix CHECK
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -O0 < %s | FileCheck %s --check-prefixes=CHECK,CHECK32,NOOPT
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -O0 < %s | FileCheck %s --check-prefixes=CHECK,CHECK64,NOOPT
+
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s --check-prefixes=CHECK,CHECK32,OPT
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s --check-prefixes=CHECK,CHECK64,OPT
 
 ; RUN: llc -filetype=obj -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s -o %t32.o
 ; RUN: llvm-readobj %t32.o --syms --relocs | FileCheck %s --check-prefix=OBJ32
 ; RUN: llvm-objdump %t32.o -dr | FileCheck %s --check-prefix=DIS32
 
 ; RUN: llc -filetype=obj -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s -o %t64.o
 ; RUN: llvm-readobj %t64.o --syms --relocs | FileCheck %s --check-prefix=OBJ64
 ; RUN: llvm-objdump %t64.o -dr | FileCheck %s --check-prefix=DIS64
 
 @i1 = external constant i32 #0
 @i2 = constant ptr @i1 #0
 
 define i32 @read() {
   %1  = load i32, ptr @i1, align 4
   ret i32 %1
 }
 
 define ptr @retptr() {
   ret ptr @i2
 }
 
 attributes #0 = { "toc-data" }
 
-; CHECK:       .read:
-; CHECK:        la 3, i1[TD](2)
+; CHECK-LABEL: .read:
+; NOOPT:         la 3, i1[TD](2)
+; NOOPT:         lwz 3, 0(3)
+; OPT:           lwz 3, i1[TD](2)
 
-; CHECK:       .retptr:
-; CHECK:        la 3, i2[TD](2)
+; CHECK-LABEL: .retptr:
+; CHECK:         la 3, i2[TD](2)
+; CHECK-NEXT:    blr
 
 ; CHECK-DAG:   .toc
 ; CHECK:         .extern i1[TD]
-; CHECK:         .csect i2[TD]
+; CHECK32:       .csect i2[TD],2
+; CHECK64:       .csect i2[TD],3
 
 ; OBJ32:      Relocations [
 ; OBJ32-NEXT:   Section (index: 1) .text {
 ; OBJ32-NEXT:     0x2 R_TOC i1(1) 0xF
-; OBJ32-NEXT:     0x26 R_TOC i2(15) 0xF
+; OBJ32-NEXT:     0x22 R_TOC i2(15) 0xF
 ; OBJ32-NEXT:   }
 ; OBJ32-NEXT:   Section (index: 2) .data {
-; OBJ32-NEXT:     0x44 R_POS .read(5) 0x1F
-; OBJ32-NEXT:     0x48 R_POS TOC(13) 0x1F
-; OBJ32-NEXT:     0x50 R_POS .retptr(7) 0x1F
-; OBJ32-NEXT:     0x54 R_POS TOC(13) 0x1F
-; OBJ32-NEXT:     0x5C R_POS i1(1) 0x1F
+; OBJ32-NEXT:     0x40 R_POS .read(5) 0x1F
+; OBJ32-NEXT:     0x44 R_POS TOC(13) 0x1F
+; OBJ32-NEXT:     0x4C R_POS .retptr(7) 0x1F
+; OBJ32-NEXT:     0x50 R_POS TOC(13) 0x1F
+; OBJ32-NEXT:     0x58 R_POS i1(1) 0x1F
 ; OBJ32-NEXT:   }
 ; OBJ32-NEXT: ]
 
 ; OBJ32:      Symbol {
 ; OBJ32:        Index: 1
 ; OBJ32-NEXT:   Name: i1
 ; OBJ32-NEXT:   Value (RelocatableAddress): 0x0
 ; OBJ32-NEXT:   Section: N_UNDEF

 ; OBJ32-NEXT:     StorageMappingClass: XMC_TD (0x10)
 ; OBJ32-NEXT:     StabInfoIndex: 0x0
 ; OBJ32-NEXT:     StabSectNum: 0x0
 ; OBJ32-NEXT:   }
 ; OBJ32-NEXT: }
 ; OBJ32:      Symbol {
 ; OBJ32:        Index: 13
 ; OBJ32-NEXT:   Name: TOC
-; OBJ32-NEXT:   Value (RelocatableAddress): 0x5C
+; OBJ32-NEXT:   Value (RelocatableAddress): 0x58
 ; OBJ32-NEXT:   Section: .data
 ; OBJ32-NEXT:   Type: 0x0
 ; OBJ32-NEXT:   StorageClass: C_HIDEXT (0x6B)
 ; OBJ32-NEXT:   NumberOfAuxEntries: 1
 ; OBJ32-NEXT:   CSECT Auxiliary Entry {
 ; OBJ32-NEXT:     Index: 14
 ; OBJ32-NEXT:     SectionLen: 0
 ; OBJ32-NEXT:     ParameterHashIndex: 0x0
 ; OBJ32-NEXT:     TypeChkSectNum: 0x0
 ; OBJ32-NEXT:     SymbolAlignmentLog2: 2
 ; OBJ32-NEXT:     SymbolType: XTY_SD (0x1)
 ; OBJ32-NEXT:     StorageMappingClass: XMC_TC0 (0xF)
 ; OBJ32-NEXT:     StabInfoIndex: 0x0
 ; OBJ32-NEXT:     StabSectNum: 0x0
 ; OBJ32-NEXT:   }
 ; OBJ32-NEXT: }
 ; OBJ32:      Symbol {
 ; OBJ32:        Index: 15
 ; OBJ32-NEXT:   Name: i2
-; OBJ32-NEXT:   Value (RelocatableAddress): 0x5C
+; OBJ32-NEXT:   Value (RelocatableAddress): 0x58
 ; OBJ32-NEXT:   Section: .data
 ; OBJ32-NEXT:   Type: 0x0
 ; OBJ32-NEXT:   StorageClass: C_EXT (0x2)
 ; OBJ32-NEXT:   NumberOfAuxEntries: 1
 ; OBJ32-NEXT:   CSECT Auxiliary Entry {
 ; OBJ32-NEXT:     Index: 16
 ; OBJ32-NEXT:     SectionLen: 4
 ; OBJ32-NEXT:     ParameterHashIndex: 0x0
 ; OBJ32-NEXT:     TypeChkSectNum: 0x0
 ; OBJ32-NEXT:     SymbolAlignmentLog2: 2
 ; OBJ32-NEXT:     SymbolType: XTY_SD (0x1)
 ; OBJ32-NEXT:     StorageMappingClass: XMC_TD (0x10)
 ; OBJ32-NEXT:     StabInfoIndex: 0x0
 ; OBJ32-NEXT:     StabSectNum: 0x0
 ; OBJ32-NEXT:   }
 ; OBJ32-NEXT: }
 
 ; OBJ64:      Relocations [
 ; OBJ64-NEXT:   Section (index: 1) .text {
 ; OBJ64-NEXT:     0x2 R_TOC i1(1) 0xF
-; OBJ64-NEXT:     0x26 R_TOC i2(15) 0xF
+; OBJ64-NEXT:     0x22 R_TOC i2(15) 0xF
 ; OBJ64-NEXT:   }
 ; OBJ64-NEXT:   Section (index: 2) .data {
-; OBJ64-NEXT:     0x48 R_POS .read(5) 0x3F
-; OBJ64-NEXT:     0x50 R_POS TOC(13) 0x3F
-; OBJ64-NEXT:     0x60 R_POS .retptr(7) 0x3F
-; OBJ64-NEXT:     0x68 R_POS TOC(13) 0x3F
-; OBJ64-NEXT:     0x78 R_POS i1(1) 0x3F
+; OBJ64-NEXT:     0x40 R_POS .read(5) 0x3F
+; OBJ64-NEXT:     0x48 R_POS TOC(13) 0x3F
+; OBJ64-NEXT:     0x58 R_POS .retptr(7) 0x3F
+; OBJ64-NEXT:     0x60 R_POS TOC(13) 0x3F
+; OBJ64-NEXT:     0x70 R_POS i1(1) 0x3F
 ; OBJ64-NEXT:   }
 ; OBJ64-NEXT: ]
 
 ; OBJ64:      Symbol {
 ; OBJ64:        Index: 1
 ; OBJ64-NEXT:   Name: i1
 ; OBJ64-NEXT:   Value (RelocatableAddress): 0x0
 ; OBJ64-NEXT:   Section: N_UNDEF

 ; OBJ64-NEXT:     SymbolType: XTY_ER (0x0)
 ; OBJ64-NEXT:     StorageMappingClass: XMC_TD (0x10)
 ; OBJ64-NEXT:     Auxiliary Type: AUX_CSECT (0xFB)
 ; OBJ64-NEXT:   }
 ; OBJ64-NEXT: }
 ; OBJ64:      Symbol {
 ; OBJ64:        Index: 13
 ; OBJ64-NEXT:   Name: TOC
-; OBJ64-NEXT:   Value (RelocatableAddress): 0x78
+; OBJ64-NEXT:   Value (RelocatableAddress): 0x70
 ; OBJ64-NEXT:   Section: .data
 ; OBJ64-NEXT:   Type: 0x0
 ; OBJ64-NEXT:   StorageClass: C_HIDEXT (0x6B)
 ; OBJ64-NEXT:   NumberOfAuxEntries: 1
 ; OBJ64-NEXT:   CSECT Auxiliary Entry {
 ; OBJ64-NEXT:     Index: 14
 ; OBJ64-NEXT:     SectionLen: 0
 ; OBJ64-NEXT:     ParameterHashIndex: 0x0
 ; OBJ64-NEXT:     TypeChkSectNum: 0x0
 ; OBJ64-NEXT:     SymbolAlignmentLog2: 2
 ; OBJ64-NEXT:     SymbolType: XTY_SD (0x1)
 ; OBJ64-NEXT:     StorageMappingClass: XMC_TC0 (0xF)
 ; OBJ64-NEXT:     Auxiliary Type: AUX_CSECT (0xFB)
 ; OBJ64-NEXT:   }
 ; OBJ64-NEXT: }
 ; OBJ64:      Symbol {
 ; OBJ64:        Index: 15
 ; OBJ64-NEXT:   Name: i2
-; OBJ64-NEXT:   Value (RelocatableAddress): 0x78
+; OBJ64-NEXT:   Value (RelocatableAddress): 0x70
 ; OBJ64-NEXT:   Section: .data
 ; OBJ64-NEXT:   Type: 0x0
 ; OBJ64-NEXT:   StorageClass: C_EXT (0x2)
 ; OBJ64-NEXT:   NumberOfAuxEntries: 1
 ; OBJ64-NEXT:   CSECT Auxiliary Entry {
 ; OBJ64-NEXT:     Index: 16
 ; OBJ64-NEXT:     SectionLen: 8
 ; OBJ64-NEXT:     ParameterHashIndex: 0x0
 ; OBJ64-NEXT:     TypeChkSectNum: 0x0
 ; OBJ64-NEXT:     SymbolAlignmentLog2: 3
 ; OBJ64-NEXT:     SymbolType: XTY_SD (0x1)
 ; OBJ64-NEXT:     StorageMappingClass: XMC_TD (0x10)
 ; OBJ64-NEXT:     Auxiliary Type: AUX_CSECT (0xFB)
 ; OBJ64-NEXT:   }
 ; OBJ64-NEXT: }
 
 ; DIS32:      00000000 <.read>:
-; DIS32-NEXT:        0: 38 62 00 00   addi 3, 2, 0
+; DIS32-NEXT:        0: 80 62 00 00   lwz 3, 0(2)
 ; DIS32-NEXT:                         00000002:  R_TOC  i1
-; DIS32:      00000024 <.retptr>:
-; DIS32-NEXT:       24: 38 62 00 00   addi 3, 2, 0
-; DIS32-NEXT:                         00000026:  R_TOC  i2
+; DIS32:      00000020 <.retptr>:
+; DIS32-NEXT:       20: 38 62 00 00   addi 3, 2, 0
+; DIS32-NEXT:                         00000022:  R_TOC  i2
 
 ; DIS64:      0000000000000000 <.read>:
-; DIS64-NEXT:        0: 38 62 00 00   addi 3, 2, 0
+; DIS64-NEXT:        0: 80 62 00 00   lwz 3, 0(2)
 ; DIS64-NEXT:                         0000000000000002:  R_TOC  i1
-; DIS64:      0000000000000024 <.retptr>:
-; DIS64-NEXT:       24: 38 62 00 00   addi 3, 2, 0
-; DIS64-NEXT:                         0000000000000026:  R_TOC  i2
+; DIS64:      0000000000000020 <.retptr>:
+; DIS64-NEXT:       20: 38 62 00 00   addi 3, 2, 0
+; DIS64-NEXT:                         0000000000000022:  R_TOC  i2

llvm/test/CodeGen/PowerPC/toc-data-peephole-aligment.ll

+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s
+
+@underaligned = dso_local global i32 123, align 1 #0
+
+define i64 @read() {
+entry:
+  %0  = load i32, ptr @underaligned, align 1
+  %1 = sext i32 %0 to i64
+  ret i64 %1
+}
+
+attributes #0 = { "toc-data"  }
+
+; CHECK-LABEL: .read
+; CHECK:       la [[DEF:[0-9]+]], underaligned[TD](2)
+; CHCEK:       lwa {{[0-9]+}}, 0([[DEF]])

llvm/test/CodeGen/PowerPC/toc-data.ll

 ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s \
-; RUN:     -stop-before=ppc-vsx-copy | FileCheck %s --check-prefix CHECK32
+; RUN:     -stop-before=ppc-vsx-copy | FileCheck %s --check-prefixes=CHECK32,OPT32
 ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s \
 ; RUN:     -stop-before=ppc-vsx-copy | FileCheck %s --check-prefix CHECK64
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s --check-prefix TEST32
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s --check-prefix TEST64
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s --check-prefixes=TEST32,ASMOPT32
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s --check-prefixes=TEST64,ASMOPT64
 
 ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s \
-; RUN:     -stop-before=ppc-vsx-copy -O0  | FileCheck %s --check-prefix CHECK32
+; RUN:     -stop-before=ppc-vsx-copy -O0  | FileCheck %s --check-prefixes=CHECK32,NOOPT32
 ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s \
 ; RUN:     -stop-before=ppc-vsx-copy -O0 | FileCheck %s --check-prefix CHECK64-NOOPT
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs -O0 < %s | FileCheck %s --check-prefix TEST32
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs -O0 < %s | FileCheck %s --check-prefix TEST64
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs -O0 < %s | FileCheck %s --check-prefixes=TEST32,ASMNOOPT32
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs -O0 < %s | FileCheck %s --check-prefixes=TEST64,ASMNOOPT64
 
 @i = dso_local global i32 0, align 4 #0
 @d = dso_local local_unnamed_addr global double 3.141590e+00, align 8
 @f = dso_local local_unnamed_addr global float 0x4005BE76C0000000, align 4 #0
 @ll = dso_local local_unnamed_addr global i64 55, align 8
 @ilocal = internal global i32 0, align 4
 
 define dso_local void @write_int(i32 signext %in) {
   entry:
     store i32 %in, ptr @i, align 4
     ret void
 }
 ; CHECK32: name:            write_int
-; CHECK32:      %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc @i, $r2
-; CHECK32-NEXT: STW %{{[0-9]+}}, 0, killed %[[SCRATCH]] :: (store (s32) into @i)
+; NOOPT32:      %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc @i, $r2
+; NOOPT32-NEXT: STW %{{[0-9]+}}, 0, killed %[[SCRATCH]] :: (store (s32) into @i)
+; OPT32:        STW %{{[0-9]+}}, @i, $r2 :: (store (s32) into @i)
 
 ; TEST32:         .write_int:
-; TEST32:           la 4, i[TD](2)
-; TEST32-NEXT:      stw 3, 0(4)
+; ASMNOOPT32:       la 4, i[TD](2)
+; ASMNOOPT32-NEXT:  stw 3, 0(4)
+; ASMOPT32:         stw 3, i[TD](2)
 
 ; CHECK64: name:            write_int
-; CHECK64:      %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @i, $x2
-; CHECK64-NEXT: STW8 %{{[0-9]+}}, 0, killed %[[SCRATCH]] :: (store (s32) into @i)
+; CHECK64:      STW8 %{{[0-9]+}}, @i, $x2  :: (store (s32) into @i)
 
 ; CHECK64-NOOPT:  name: write_int
 ; CHECK64-NOOPT:    %[[SUBREG:[0-9]+]]:gprc = COPY %{{[0-9]}}.sub_32
 ; CHECK64-NOOPT:    %[[ADDR:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @i, $x2 :: (load (s64) from got)
 ; CHECK64-NOOPT:    STW %[[SUBREG]], 0, killed %[[ADDR]] :: (store (s32) into @i)
 
 ; TEST64:         .write_int:
-; TEST64:           la 4, i[TD](2)
-; TEST64-NEXT:      stw 3, 0(4)
-
+; ASMNOOPT64:       la 4, i[TD](2)
+; ASMNOOPT64-NEXT:  stw 3, 0(4)
+; ASMOPT64:         stw 3, i[TD](2)
 
 define dso_local i64 @read_ll() {
   entry:
     %0 = load i64, ptr @ll, align 8
     ret i64 %0
 }
 ; CHECK32: name:            read_ll
 ; CHECK32: LWZtoc @ll, $r2 :: (load (s32) from got)

 
 
 define dso_local float @read_float() {
   entry:
     %0 = load float, ptr @f, align 4
     ret float %0
 }
 ; CHECK32: name:            read_float
-; CHECK32: %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc @f, $r2
-; CHECK32: %{{[0-9]+}}:f4rc = LFS 0, killed %[[SCRATCH]] :: (dereferenceable load (s32) from @f)
+; NOOPT32: %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc @f, $r2
+; NOOPT32: %{{[0-9]+}}:f4rc = LFS 0, killed %[[SCRATCH]] :: (dereferenceable load (s32) from @f)
+; OPT32:   %{{[0-9]+}}:f4rc = LFS @f, $r2 :: (dereferenceable load (s32) from @f)
 
-; TEST32:       .read_float:
-; TEST32:         la 3, f[TD](2)
-; TEST32-NEXT:    lfs 1, 0(3)
+; TEST32:           .read_float:
+; ASMNOOPT32:         la 3, f[TD](2)
+; ASMNOOPT32-NEXT:    lfs 1, 0(3)
+; ASMOPT32:           lfs 1, f[TD](2)
 
 ; CHECK64: name:            read_float
-; CHECK64: %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @f, $x2
-; CHECK64: %{{[0-9]+}}:f4rc = LFS 0, killed %[[SCRATCH]] :: (dereferenceable load (s32) from @f)
+; CHECK64: %{{[0-9]+}}:f4rc = LFS @f, $x2 :: (dereferenceable load (s32) from @f)
 
 ; CHECK64-NOOPT: name:            read_float
 ; CHECK64-NOOPT:   %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @f, $x2
 ; CHECK64-NOOPT:   %{{[0-9]+}}:f4rc = LFS 0, killed %[[SCRATCH]]
 
-; TEST64:       .read_float:
-; TEST64:         la 3, f[TD](2)
-; TEST64-NEXT:    lfs 1, 0(3)
-
+; TEST64:          .read_float:
+; ASMNOOPT64:        la 3, f[TD](2)
+; ASMNOOPT64-NEXT:   lfs 1, 0(3)
+; ASMOPT64:          lfs 1, f[TD](2)
 
 define dso_local void @write_double(double %in) {
   entry:
     store double %in, ptr @d, align 8
     ret void
 }
 ; CHECK32: name:            write_double
 ; CHECK32: LWZtoc @d, $r2 :: (load (s32) from got)