This is an archive of the discontinued LLVM Phabricator instance.

[XCOFF][AIX] Peephole optimization for small code model TocData transformations
ClosedPublic

Authored by sfertile on Apr 28 2021, 9:28 AM.

Details

Summary

This patch is a followup to D101178.

In the patch, we enable peephole optimization (when possible) for the toc data transformation.

For example, with this patch would allow for the following assembly code:

la 4, i[TD](2) 
stw 3, 0(4)

to be transformed to the following instead:

stw 3, i[TD](2)

This patch can only be merged in after D101178 has been accepted and merged into LLVM.

Diff Detail

Event Timeline

sidbav created this revision.Apr 28 2021, 9:28 AM
sidbav requested review of this revision.Apr 28 2021, 9:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 28 2021, 9:28 AM

Awesome work Sidarth, patch looks really good. I've got one initial comment.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
7096

This flag represents emitting a specific relocation (ie producing an object file) or a specific relocation specifier (if producing assembly) in this case it means emitting sym@toc@l which means the low 16-bits of the offset from the toc-pointer to 'sym'. Our symbol reference on the ADDItoc doesn't need any flags to modify it.

sidbav updated this revision to Diff 341640.Apr 29 2021, 2:22 PM

Address Review comments

sidbav marked an inline comment as done.Apr 29 2021, 2:22 PM
sidbav updated this revision to Diff 341642.Apr 29 2021, 2:24 PM

fix some formatting issues

sfertile commandeered this revision.Jun 15 2021, 3:59 PM
sfertile edited reviewers, added: sidbav; removed: sfertile.
sfertile updated this revision to Diff 403745.Jan 27 2022, 12:02 PM

rebase patch and update the testing.

sfertile retitled this revision from [XCOFF][AIX] Peephole optimization in TocData transformation to [XCOFF][AIX] Peephole optimization in 32-bit TocData transformation.Feb 1 2022, 8:55 AM

Note that I have reviewed this patch along with https://reviews.llvm.org/D118718. The following comment applies to both patches.

There is one concern with respect to alignment.
I've created the following test case:

define i64 @read() {
  %1  = load i32, i32* @i1, align 1
  %2  = sext i32 %1 to i64
  ret i64 %2
}

The assembly we create (using llc -mtriple powerpc64-ibm-aix-xcoff test.ll) is as follows:

.read:
# %bb.0:
	lwa 3, i1[TD](2)
	blr

The issue is that the original ADDI instruction is a D-Form and so no alignment is required. However, LWA is DS form and if the alignment for i1 is not a multiple of 4 then the linker won't have a way to fill in that value.

llvm/test/CodeGen/PowerPC/toc-data-const.ll
4 ↗(On Diff #403745)

nit:
Forgot the : after the RUN.

shchenz added a subscriber: shchenz.Jul 4 2022, 3:33 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 4 2022, 3:33 AM
sfertile updated this revision to Diff 528832.Jun 6 2023, 6:41 AM

Combined both 32-bit and 64-bit patches and addressed Stephans comment about the under-aligned DS-form instructions.

sfertile retitled this revision from [XCOFF][AIX] Peephole optimization in 32-bit TocData transformation to [XCOFF][AIX] Peephole optimization for small code model TocData transformations.Jun 6 2023, 6:43 AM
stefanp accepted this revision.Jun 9 2023, 8:11 AM

I have one minor nit and that's it. Otherwise LGTM.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
7194

nit:
Just add a comment here to say that PPC::ADDItoc and PPC::ADDItoc8 are only used for AIX small code model.
It's not obvious from the name of the pseudo instruction so this tripped me up initially.

This revision is now accepted and ready to land.Jun 9 2023, 8:11 AM
This revision was automatically updated to reflect the committed changes.