[XCOFF][AIX] Peephole optimization for small code model TocData transformations

[sfertile]

Summary

This patch is a followup to D101178.

In the patch, we enable peephole optimization (when possible) for the toc data transformation.

For example, with this patch would allow for the following assembly code:

la 4, i[TD](2) 
stw 3, 0(4)

to be transformed to the following instead:

stw 3, i[TD](2)

This patch can only be merged in after D101178 has been accepted and merged into LLVM.

[sfertile]

Awesome work Sidarth, patch looks really good. I've got one initial comment.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

7096

This flag represents emitting a specific relocation (ie producing an object file) or a specific relocation specifier (if producing assembly) in this case it means emitting sym@toc@l which means the low 16-bits of the offset from the toc-pointer to 'sym'. Our symbol reference on the ADDItoc doesn't need any flags to modify it.

[sidbav]

Address Review comments

[sidbav]

fix some formatting issues

[sfertile]

rebase patch and update the testing.

[stefanp]

Note that I have reviewed this patch along with https://reviews.llvm.org/D118718. The following comment applies to both patches.

There is one concern with respect to alignment.
I've created the following test case:

define i64 @read() {
  %1  = load i32, i32* @i1, align 1
  %2  = sext i32 %1 to i64
  ret i64 %2
}

The assembly we create (using llc -mtriple powerpc64-ibm-aix-xcoff test.ll) is as follows:

.read:
# %bb.0:
	lwa 3, i1[TD](2)
	blr

The issue is that the original ADDI instruction is a D-Form and so no alignment is required. However, LWA is DS form and if the alignment for i1 is not a multiple of 4 then the linker won't have a way to fill in that value.

llvm/test/CodeGen/PowerPC/toc-data-const.ll

4 ↗

(On Diff #403745)

nit:
Forgot the : after the RUN.

[sfertile]

Combined both 32-bit and 64-bit patches and addressed Stephans comment about the under-aligned DS-form instructions.

[stefanp]

I have one minor nit and that's it. Otherwise LGTM.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

7194

nit:
Just add a comment here to say that PPC::ADDItoc and PPC::ADDItoc8 are only used for AIX small code model.
It's not obvious from the name of the pseudo instruction so this tripped me up initially.

[hubert.reinterpretcast]

I believe https://github.com/llvm/llvm-project/issues/63927 is related to this patch.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

case PPC::ADDI:
       break;
     case PPC::ADDIdtprelL:
       Flags = PPCII::MO_DTPREL_LO;
       break;
     case PPC::ADDItlsldL:
       Flags = PPCII::MO_TLSLD_LO;
       break;
     case PPC::ADDItocL:
+    case PPC::ADDItoc:
       Flags = PPCII::MO_TOC_LO;
       break;
     }
 
     SDValue ImmOpnd = Base.getOperand(1);
 
     // On PPC64, the TOC base pointer is guaranteed by the ABI only to have
     // 8-byte alignment, and so we can only use offsets less than 8 (otherwise,
     // we might have needed different @ha relocation values for the offset
if (ReplaceFlags) {
                  dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
         const Constant *C = CP->getConstVal();
         ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64, CP->getAlign(),
                                                 Offset, Flags);
       }
     }
 
     if (FirstOp == 1) // Store
+      if (Base.getMachineOpcode() == PPC::ADDItoc)
+        (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0),
+                                         Base.getOperand(0), Base.getOperand(1),
+                                         N->getOperand(3));
+      else
         (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
                                          Base.getOperand(0), N->getOperand(3));
     else // Load
+        if (Base.getMachineOpcode() == PPC::ADDItoc)
+      (void)CurDAG->UpdateNodeOperands(N, Base.getOperand(0),
+                                       Base.getOperand(1), N->getOperand(2));
+    else
       (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
                                        N->getOperand(2));
 
     if (UpdateHBase)
       (void)CurDAG->UpdateNodeOperands(HBase.getNode(), HBase.getOperand(0),
                                        ImmOpnd);
 
     // The add-immediate may now be dead, in which case remove it.

llvm/lib/Target/PowerPC/PPCMCInstLower.cpp

static MCSymbol *GetSymbolFromOperand(const MachineOperand &MO,
   MCContext &Ctx = AP.OutContext;
 
   SmallString<128> Name;
   if (!MO.isGlobal()) {
     assert(MO.isSymbol() && "Isn't a symbol reference");
     Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL);
   } else {
     const GlobalValue *GV = MO.getGlobal();
+
+    if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
+      if (GVar->hasAttribute("toc-data"))
+        return AP.getSymbol(GV);
+
     TM.getNameWithPrefix(Name, GV, Mang);
   }
 
   MCSymbol *Sym = Ctx.getOrCreateSymbol(Name);
 
   return Sym;
 }
 

llvm/test/CodeGen/PowerPC/toc-data.ll

 ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s \
 ; RUN:     -stop-before=ppc-ctr-loops-verify | FileCheck %s
 ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s --check-prefix TEST
 
 @i = dso_local global i32 0, align 4 #0
 @d = dso_local local_unnamed_addr global double 3.141590e+00, align 8
 @f = dso_local local_unnamed_addr global float 0x4005BE76C0000000, align 4 #0
 @ll = dso_local local_unnamed_addr global i64 55, align 8
 @ilocal = internal global i32 0, align 4
 
 define dso_local void @write_int(i32 signext %in) {
   entry:
     store i32 %in, i32* @i, align 4
     ret void
 }
 ; CHECK: name:            write_int
-; CHECK:      %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc @i, $r2
-; CHECK-NEXT: STW %{{[0-9]+}}, 0, killed %[[SCRATCH]] :: (store 4 into @i)
+; CHECK:      %[[SCRATCH:[0-9]+]]:gprc  = COPY $r3
+; CHECK-NEXT: STW %{{[0-9]+}}, @i, $r2 :: (store 4 into @i)
 
 ; TEST:         .write_int:
-; TEST:         la 4, i[TD](2)
-; TEST-NEXT:    stw 3, 0(4)
+; TEST:    stw 3, i[TD](2)
 
 define dso_local i64 @read_ll() {
   entry:
     %0 = load i64, i64* @ll, align 8
     ret i64 %0
 }
 ; CHECK: name:            read_ll
 ; CHECK: LWZtoc @ll, $r2 :: (load 4 from got)
 
 ; TEST:       .read_ll:
 ; TEST:       lwz 4, L..C0(2)
 ; TEST-NEXT:  lwz 3, 0(4)
 ; TEST-NEXT:  lwz 4, 4(4)
 
 define dso_local float @read_float() {
   entry:
     %0 = load float, float* @f, align 4
     ret float %0
 }
 ; CHECK: name:            read_float
-; CHECK: %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc @f, $r2
-; CHECK: %{{[0-9]+}}:f4rc = LFS 0, killed %[[SCRATCH]] :: (dereferenceable load 4 from @f)
+; CHECK: %{{[0-9]+}}:f4rc = LFS @f, $r2 :: (dereferenceable load 4 from @f)
 
 ; TEST:       .read_float:
-; TEST:       la 3, f[TD](2)
-; TEST-NEXT:  lfs 1, 0(3)
+; TEST:  lfs 1, f[TD](2)
 
 define dso_local void @write_double(double %in) {
   entry:
     store double %in, double* @d, align 8
     ret void
 }
 ; CHECK: name:            write_double
 ; CHECK: LWZtoc @d, $r2 :: (load 4 from got)

 ; TEST:       la 3, i[TD](2)
 
 define dso_local i32 @read_i32_linkage() {
   entry:
     %0 = load i32, i32* @ilocal, align 4
     ret i32 %0
 }
 ; CHECK: name:            read_i32_linkage
-; CHECK: LWZtoc @ilocal, $r2 :: (load 4 from got)
+; CHECK:      %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = LWZtoc @ilocal, $r2 :: (load 4 from got)
+; CHECK-NEXT: LWZ 0, killed %[[SCRATCH]] :: (dereferenceable load 4 from @ilocal)
 
 ; TEST:       .read_i32_linkage:
 ; TEST:       lwz 3, L..C2(2)
 ; TEST-NEXT:  lwz 3, 0(3)
 
 attributes #0 = { "toc-data" }