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Differential D100280

[RISCV] Implement COPY for Zvlsseg registers
ClosedPublic

Authored by arcbbb on Apr 11 2021, 8:07 PM.

Details

Reviewers
craig.topper
frasercrmck
HsiangKai
rogfer01
jrtc27
Commits
rGd5e962f1f20c: [RISCV] Implement COPY for Zvlsseg registers
Summary

When copying Zvlsseg register tuples, we split the COPY into NF whole register moves
as below:

    
$v10m2_v12m2 = COPY $v4m2_v6m2 # NF = 2

>

$v10m2 = PseudoVMV2R_V $v4m2
$v12m2 = PseudoVMV2R_V $v6m2

This patch copies forwardCopyWillClobberTuple from AArch64 to check
register overlapping.

Diff Detail

Event Timeline

arcbbb created this revision.Apr 11 2021, 8:07 PM
Herald added subscribers: vkmr, evandro, luismarques and 23 others. · View Herald TranscriptApr 11 2021, 8:07 PM
arcbbb requested review of this revision.Apr 11 2021, 8:07 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 11 2021, 8:07 PM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B98201: Diff 336730.Apr 11 2021, 9:02 PM
HsiangKai added inline comments.Apr 12 2021, 2:45 AM
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
132–133

Registers for Zvlsseg are also scalable vector. How about to set IsScalableVector to true by default and turn it off for scalar register classes. (Refer to storeRegToStackSlot()).

212–213

How about

If (IsScalableVector) {
  if (NF == 1) {
    // processing scalable vector registers.
  } else {
    // processing Zvlsseg registers.
  }
} else {
  // processing scalar registers
}
arcbbb updated this revision to Diff 336807.Apr 12 2021, 5:05 AM

Address HsiangKai's comment.

Harbormaster completed remote builds in B98257: Diff 336807.Apr 12 2021, 5:41 AM
craig.topper added inline comments.Apr 12 2021, 10:21 AM
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
146

Consistently use curly braces on all the blocks.

214

Put curly braces on this to match the else.

235

Curly braces around this else to match the if

arcbbb updated this revision to Diff 337011.Apr 12 2021, 6:07 PM

Address Craig's comment.

Harbormaster completed remote builds in B98398: Diff 337011.Apr 12 2021, 6:40 PM
frasercrmck accepted this revision.Apr 13 2021, 2:30 AM

LGTM

This revision is now accepted and ready to land.Apr 13 2021, 2:30 AM
Closed by commit rGd5e962f1f20c: [RISCV] Implement COPY for Zvlsseg registers (authored by arcbbb). · Explain WhyApr 13 2021, 6:56 PM
This revision was automatically updated to reflect the committed changes.
arcbbb added a commit: rGd5e962f1f20c: [RISCV] Implement COPY for Zvlsseg registers.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
113 lines
test/
CodeGen/
RISCV/
rvv/
282 lines

Diff 337308

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Lines if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0) { MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex(); FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg(); return MI.getOperand(0).getReg();
} }
return 0; return 0;
} }
static bool forwardCopyWillClobberTuple(unsigned DstReg, unsigned SrcReg,
unsigned NumRegs) {
// We really want the positive remainder mod 32 here, that happens to be
// easily obtainable with a mask.
return ((DstReg - SrcReg) & 0x1f) < NumRegs;
}
void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DstReg, const DebugLoc &DL, MCRegister DstReg,
MCRegister SrcReg, bool KillSrc) const { MCRegister SrcReg, bool KillSrc) const {
if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) { if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg) BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
.addReg(SrcReg, getKillRegState(KillSrc)) .addReg(SrcReg, getKillRegState(KillSrc))
.addImm(0); .addImm(0);
return; return;
} }
// FPR->FPR copies and VR->VR copies. // FPR->FPR copies and VR->VR copies.
unsigned Opc; unsigned Opc;
bool IsScalableVector = false; bool IsScalableVector = true;
HsiangKaiUnsubmitted
Not Done
ReplyInline Actions

Registers for Zvlsseg are also scalable vector. How about to set IsScalableVector to true by default and turn it off for scalar register classes. (Refer to storeRegToStackSlot()).

HsiangKai: Registers for Zvlsseg are also scalable vector. How about to set `IsScalableVector` to true by…
if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) unsigned NF = 1;
unsigned LMul = 1;
unsigned SubRegIdx = RISCV::sub_vrm1_0;
if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) {
Opc = RISCV::FSGNJ_H; Opc = RISCV::FSGNJ_H;
else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) IsScalableVector = false;
} else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) {
Opc = RISCV::FSGNJ_S; Opc = RISCV::FSGNJ_S;
else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) IsScalableVector = false;
} else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) {
Opc = RISCV::FSGNJ_D; Opc = RISCV::FSGNJ_D;
else if (RISCV::VRRegClass.contains(DstReg, SrcReg)) { IsScalableVector = false;
} else if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Consistently use curly braces on all the blocks.

craig.topper: Consistently use curly braces on all the blocks.
Opc = RISCV::PseudoVMV1R_V; Opc = RISCV::PseudoVMV1R_V;
IsScalableVector = true;
} else if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) { } else if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
Opc = RISCV::PseudoVMV2R_V; Opc = RISCV::PseudoVMV2R_V;
IsScalableVector = true;
} else if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) { } else if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {
Opc = RISCV::PseudoVMV4R_V; Opc = RISCV::PseudoVMV4R_V;
IsScalableVector = true;
} else if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) { } else if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {
Opc = RISCV::PseudoVMV8R_V; Opc = RISCV::PseudoVMV8R_V;
IsScalableVector = true; } else if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) {
} else Opc = RISCV::PseudoVMV1R_V;
SubRegIdx = RISCV::sub_vrm1_0;
NF = 2;
LMul = 1;
} else if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) {
Opc = RISCV::PseudoVMV2R_V;
SubRegIdx = RISCV::sub_vrm2_0;
NF = 2;
LMul = 2;
} else if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) {
Opc = RISCV::PseudoVMV4R_V;
SubRegIdx = RISCV::sub_vrm4_0;
NF = 2;
LMul = 4;
} else if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) {
Opc = RISCV::PseudoVMV1R_V;
SubRegIdx = RISCV::sub_vrm1_0;
NF = 3;
LMul = 1;
} else if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) {
Opc = RISCV::PseudoVMV2R_V;
SubRegIdx = RISCV::sub_vrm2_0;
NF = 3;
LMul = 2;
} else if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) {
Opc = RISCV::PseudoVMV1R_V;
SubRegIdx = RISCV::sub_vrm1_0;
NF = 4;
LMul = 1;
} else if (RISCV::VRN4M2RegClass.contains(DstReg, SrcReg)) {
Opc = RISCV::PseudoVMV2R_V;
SubRegIdx = RISCV::sub_vrm2_0;
NF = 4;
LMul = 2;
} else if (RISCV::VRN5M1RegClass.contains(DstReg, SrcReg)) {
Opc = RISCV::PseudoVMV1R_V;
SubRegIdx = RISCV::sub_vrm1_0;
NF = 5;
LMul = 1;
} else if (RISCV::VRN6M1RegClass.contains(DstReg, SrcReg)) {
Opc = RISCV::PseudoVMV1R_V;
SubRegIdx = RISCV::sub_vrm1_0;
NF = 6;
LMul = 1;
} else if (RISCV::VRN7M1RegClass.contains(DstReg, SrcReg)) {
Opc = RISCV::PseudoVMV1R_V;
SubRegIdx = RISCV::sub_vrm1_0;
NF = 7;
LMul = 1;
} else if (RISCV::VRN8M1RegClass.contains(DstReg, SrcReg)) {
Opc = RISCV::PseudoVMV1R_V;
SubRegIdx = RISCV::sub_vrm1_0;
NF = 8;
LMul = 1;
} else {
llvm_unreachable("Impossible reg-to-reg copy"); llvm_unreachable("Impossible reg-to-reg copy");
}
if (IsScalableVector) if (IsScalableVector) {
HsiangKaiUnsubmitted
Not Done
ReplyInline Actions

How about

If (IsScalableVector) {
  if (NF == 1) {
    // processing scalable vector registers.
  } else {
    // processing Zvlsseg registers.
  }
} else {
  // processing scalar registers
}
HsiangKai: How about ``` If (IsScalableVector) { if (NF == 1) { // processing scalable vector…
if (NF == 1) {
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Put curly braces on this to match the else.

craig.topper: Put curly braces on this to match the else.
BuildMI(MBB, MBBI, DL, get(Opc), DstReg) BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
.addReg(SrcReg, getKillRegState(KillSrc)); .addReg(SrcReg, getKillRegState(KillSrc));
else } else {
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
int I = 0, End = NF, Incr = 1;
unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
unsigned DstEncoding = TRI->getEncodingValue(DstReg);
if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMul)) {
I = NF - 1;
End = -1;
Incr = -1;
}
for (; I != End; I += Incr) {
BuildMI(MBB, MBBI, DL, get(Opc), TRI->getSubReg(DstReg, SubRegIdx + I))
.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),
getKillRegState(KillSrc));
}
}
} else {
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Curly braces around this else to match the if

craig.topper: Curly braces around this else to match the if
BuildMI(MBB, MBBI, DL, get(Opc), DstReg) BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
.addReg(SrcReg, getKillRegState(KillSrc)) .addReg(SrcReg, getKillRegState(KillSrc))
.addReg(SrcReg, getKillRegState(KillSrc)); .addReg(SrcReg, getKillRegState(KillSrc));
} }
}
void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
Register SrcReg, bool IsKill, int FI, Register SrcReg, bool IsKill, int FI,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const { const TargetRegisterInfo *TRI) const {
DebugLoc DL; DebugLoc DL;
if (I != MBB.end()) if (I != MBB.end())
▲ Show 20 Lines • Show All 1,162 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -verify-machineinstrs -mtriple riscv64 -run-pass=postrapseudos %s -o - | FileCheck %s
...
---
name: copy_zvlsseg_N2
body: |
bb.0:
; CHECK-LABEL: name: copy_zvlsseg_N2
; CHECK: $v2 = PseudoVMV1R_V $v4
; CHECK: $v3 = PseudoVMV1R_V $v5
; CHECK: $v3 = PseudoVMV1R_V $v4
; CHECK: $v4 = PseudoVMV1R_V $v5
; CHECK: $v6 = PseudoVMV1R_V $v5
; CHECK: $v5 = PseudoVMV1R_V $v4
; CHECK: $v6 = PseudoVMV1R_V $v4
; CHECK: $v7 = PseudoVMV1R_V $v5
; CHECK: $v0m2 = PseudoVMV2R_V $v4m2
; CHECK: $v2m2 = PseudoVMV2R_V $v6m2
; CHECK: $v2m2 = PseudoVMV2R_V $v4m2
; CHECK: $v4m2 = PseudoVMV2R_V $v6m2
; CHECK: $v8m2 = PseudoVMV2R_V $v6m2
; CHECK: $v6m2 = PseudoVMV2R_V $v4m2
; CHECK: $v8m2 = PseudoVMV2R_V $v4m2
; CHECK: $v10m2 = PseudoVMV2R_V $v6m2
; CHECK: $v0m4 = PseudoVMV4R_V $v8m4
; CHECK: $v4m4 = PseudoVMV4R_V $v12m4
; CHECK: $v4m4 = PseudoVMV4R_V $v8m4
; CHECK: $v8m4 = PseudoVMV4R_V $v12m4
; CHECK: $v16m4 = PseudoVMV4R_V $v12m4
; CHECK: $v12m4 = PseudoVMV4R_V $v8m4
; CHECK: $v16m4 = PseudoVMV4R_V $v8m4
; CHECK: $v20m4 = PseudoVMV4R_V $v12m4
$v2_v3 = COPY $v4_v5
$v3_v4 = COPY $v4_v5
$v5_v6 = COPY $v4_v5
$v6_v7 = COPY $v4_v5
$v0m2_v2m2 = COPY $v4m2_v6m2
$v2m2_v4m2 = COPY $v4m2_v6m2
$v6m2_v8m2 = COPY $v4m2_v6m2
$v8m2_v10m2 = COPY $v4m2_v6m2
$v0m4_v4m4 = COPY $v8m4_v12m4
$v4m4_v8m4 = COPY $v8m4_v12m4
$v12m4_v16m4 = COPY $v8m4_v12m4
$v16m4_v20m4 = COPY $v8m4_v12m4
...
---
name: copy_zvlsseg_N3
body: |
bb.0:
; CHECK-LABEL: name: copy_zvlsseg_N3
; CHECK: $v2 = PseudoVMV1R_V $v5
; CHECK: $v3 = PseudoVMV1R_V $v6
; CHECK: $v4 = PseudoVMV1R_V $v7
; CHECK: $v3 = PseudoVMV1R_V $v5
; CHECK: $v4 = PseudoVMV1R_V $v6
; CHECK: $v5 = PseudoVMV1R_V $v7
; CHECK: $v4 = PseudoVMV1R_V $v5
; CHECK: $v5 = PseudoVMV1R_V $v6
; CHECK: $v6 = PseudoVMV1R_V $v7
; CHECK: $v9 = PseudoVMV1R_V $v7
; CHECK: $v8 = PseudoVMV1R_V $v6
; CHECK: $v7 = PseudoVMV1R_V $v5
; CHECK: $v9 = PseudoVMV1R_V $v5
; CHECK: $v10 = PseudoVMV1R_V $v6
; CHECK: $v11 = PseudoVMV1R_V $v7
; CHECK: $v0m2 = PseudoVMV2R_V $v6m2
; CHECK: $v2m2 = PseudoVMV2R_V $v8m2
; CHECK: $v4m2 = PseudoVMV2R_V $v10m2
; CHECK: $v2m2 = PseudoVMV2R_V $v6m2
; CHECK: $v4m2 = PseudoVMV2R_V $v8m2
; CHECK: $v6m2 = PseudoVMV2R_V $v10m2
; CHECK: $v14m2 = PseudoVMV2R_V $v10m2
; CHECK: $v12m2 = PseudoVMV2R_V $v8m2
; CHECK: $v10m2 = PseudoVMV2R_V $v6m2
; CHECK: $v12m2 = PseudoVMV2R_V $v6m2
; CHECK: $v14m2 = PseudoVMV2R_V $v8m2
; CHECK: $v16m2 = PseudoVMV2R_V $v10m2
$v2_v3_v4 = COPY $v5_v6_v7
$v3_v4_v5 = COPY $v5_v6_v7
$v4_v5_v6 = COPY $v5_v6_v7
$v7_v8_v9 = COPY $v5_v6_v7
$v9_v10_v11 = COPY $v5_v6_v7
$v0m2_v2m2_v4m2 = COPY $v6m2_v8m2_v10m2
$v2m2_v4m2_v6m2 = COPY $v6m2_v8m2_v10m2
$v10m2_v12m2_v14m2 = COPY $v6m2_v8m2_v10m2
$v12m2_v14m2_v16m2 = COPY $v6m2_v8m2_v10m2
...
---
name: copy_zvlsseg_N4
body: |
bb.0:
; CHECK-LABEL: name: copy_zvlsseg_N4
; CHECK: $v6 = PseudoVMV1R_V $v10
; CHECK: $v7 = PseudoVMV1R_V $v11
; CHECK: $v8 = PseudoVMV1R_V $v12
; CHECK: $v9 = PseudoVMV1R_V $v13
; CHECK: $v7 = PseudoVMV1R_V $v10
; CHECK: $v8 = PseudoVMV1R_V $v11
; CHECK: $v9 = PseudoVMV1R_V $v12
; CHECK: $v10 = PseudoVMV1R_V $v13
; CHECK: $v16 = PseudoVMV1R_V $v13
; CHECK: $v15 = PseudoVMV1R_V $v12
; CHECK: $v14 = PseudoVMV1R_V $v11
; CHECK: $v13 = PseudoVMV1R_V $v10
; CHECK: $v14 = PseudoVMV1R_V $v10
; CHECK: $v15 = PseudoVMV1R_V $v11
; CHECK: $v16 = PseudoVMV1R_V $v12
; CHECK: $v17 = PseudoVMV1R_V $v13
; CHECK: $v2m2 = PseudoVMV2R_V $v10m2
; CHECK: $v4m2 = PseudoVMV2R_V $v12m2
; CHECK: $v6m2 = PseudoVMV2R_V $v14m2
; CHECK: $v8m2 = PseudoVMV2R_V $v16m2
; CHECK: $v4m2 = PseudoVMV2R_V $v10m2
; CHECK: $v6m2 = PseudoVMV2R_V $v12m2
; CHECK: $v8m2 = PseudoVMV2R_V $v14m2
; CHECK: $v10m2 = PseudoVMV2R_V $v16m2
; CHECK: $v22m2 = PseudoVMV2R_V $v16m2
; CHECK: $v20m2 = PseudoVMV2R_V $v14m2
; CHECK: $v18m2 = PseudoVMV2R_V $v12m2
; CHECK: $v16m2 = PseudoVMV2R_V $v10m2
; CHECK: $v18m2 = PseudoVMV2R_V $v10m2
; CHECK: $v20m2 = PseudoVMV2R_V $v12m2
; CHECK: $v22m2 = PseudoVMV2R_V $v14m2
; CHECK: $v24m2 = PseudoVMV2R_V $v16m2
$v6_v7_v8_v9 = COPY $v10_v11_v12_v13
$v7_v8_v9_v10 = COPY $v10_v11_v12_v13
$v13_v14_v15_v16 = COPY $v10_v11_v12_v13
$v14_v15_v16_v17 = COPY $v10_v11_v12_v13
$v2m2_v4m2_v6m2_v8m2 = COPY $v10m2_v12m2_v14m2_v16m2
$v4m2_v6m2_v8m2_v10m2 = COPY $v10m2_v12m2_v14m2_v16m2
$v16m2_v18m2_v20m2_v22m2 = COPY $v10m2_v12m2_v14m2_v16m2
$v18m2_v20m2_v22m2_v24m2 = COPY $v10m2_v12m2_v14m2_v16m2
...
---
name: copy_zvlsseg_N5
body: |
bb.0:
; CHECK-LABEL: name: copy_zvlsseg_N5
; CHECK: $v5 = PseudoVMV1R_V $v10
; CHECK: $v6 = PseudoVMV1R_V $v11
; CHECK: $v7 = PseudoVMV1R_V $v12
; CHECK: $v8 = PseudoVMV1R_V $v13
; CHECK: $v9 = PseudoVMV1R_V $v14
; CHECK: $v6 = PseudoVMV1R_V $v10
; CHECK: $v7 = PseudoVMV1R_V $v11
; CHECK: $v8 = PseudoVMV1R_V $v12
; CHECK: $v9 = PseudoVMV1R_V $v13
; CHECK: $v10 = PseudoVMV1R_V $v14
; CHECK: $v18 = PseudoVMV1R_V $v14
; CHECK: $v17 = PseudoVMV1R_V $v13
; CHECK: $v16 = PseudoVMV1R_V $v12
; CHECK: $v15 = PseudoVMV1R_V $v11
; CHECK: $v14 = PseudoVMV1R_V $v10
; CHECK: $v15 = PseudoVMV1R_V $v10
; CHECK: $v16 = PseudoVMV1R_V $v11
; CHECK: $v17 = PseudoVMV1R_V $v12
; CHECK: $v18 = PseudoVMV1R_V $v13
; CHECK: $v19 = PseudoVMV1R_V $v14
$v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14
$v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14
$v14_v15_v16_v17_v18 = COPY $v10_v11_v12_v13_v14
$v15_v16_v17_v18_v19 = COPY $v10_v11_v12_v13_v14
...
---
name: copy_zvlsseg_N6
body: |
bb.0:
; CHECK-LABEL: name: copy_zvlsseg_N6
; CHECK: $v4 = PseudoVMV1R_V $v10
; CHECK: $v5 = PseudoVMV1R_V $v11
; CHECK: $v6 = PseudoVMV1R_V $v12
; CHECK: $v7 = PseudoVMV1R_V $v13
; CHECK: $v8 = PseudoVMV1R_V $v14
; CHECK: $v9 = PseudoVMV1R_V $v15
; CHECK: $v5 = PseudoVMV1R_V $v10
; CHECK: $v6 = PseudoVMV1R_V $v11
; CHECK: $v7 = PseudoVMV1R_V $v12
; CHECK: $v8 = PseudoVMV1R_V $v13
; CHECK: $v9 = PseudoVMV1R_V $v14
; CHECK: $v10 = PseudoVMV1R_V $v15
; CHECK: $v20 = PseudoVMV1R_V $v15
; CHECK: $v19 = PseudoVMV1R_V $v14
; CHECK: $v18 = PseudoVMV1R_V $v13
; CHECK: $v17 = PseudoVMV1R_V $v12
; CHECK: $v16 = PseudoVMV1R_V $v11
; CHECK: $v15 = PseudoVMV1R_V $v10
; CHECK: $v16 = PseudoVMV1R_V $v10
; CHECK: $v17 = PseudoVMV1R_V $v11
; CHECK: $v18 = PseudoVMV1R_V $v12
; CHECK: $v19 = PseudoVMV1R_V $v13
; CHECK: $v20 = PseudoVMV1R_V $v14
; CHECK: $v21 = PseudoVMV1R_V $v15
$v4_v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14_v15
$v5_v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14_v15
$v15_v16_v17_v18_v19_v20 = COPY $v10_v11_v12_v13_v14_v15
$v16_v17_v18_v19_v20_v21 = COPY $v10_v11_v12_v13_v14_v15
...
---
name: copy_zvlsseg_N7
body: |
bb.0:
; CHECK-LABEL: name: copy_zvlsseg_N7
; CHECK: $v3 = PseudoVMV1R_V $v10
; CHECK: $v4 = PseudoVMV1R_V $v11
; CHECK: $v5 = PseudoVMV1R_V $v12
; CHECK: $v6 = PseudoVMV1R_V $v13
; CHECK: $v7 = PseudoVMV1R_V $v14
; CHECK: $v8 = PseudoVMV1R_V $v15
; CHECK: $v9 = PseudoVMV1R_V $v16
; CHECK: $v4 = PseudoVMV1R_V $v10
; CHECK: $v5 = PseudoVMV1R_V $v11
; CHECK: $v6 = PseudoVMV1R_V $v12
; CHECK: $v7 = PseudoVMV1R_V $v13
; CHECK: $v8 = PseudoVMV1R_V $v14
; CHECK: $v9 = PseudoVMV1R_V $v15
; CHECK: $v10 = PseudoVMV1R_V $v16
; CHECK: $v22 = PseudoVMV1R_V $v16
; CHECK: $v21 = PseudoVMV1R_V $v15
; CHECK: $v20 = PseudoVMV1R_V $v14
; CHECK: $v19 = PseudoVMV1R_V $v13
; CHECK: $v18 = PseudoVMV1R_V $v12
; CHECK: $v17 = PseudoVMV1R_V $v11
; CHECK: $v16 = PseudoVMV1R_V $v10
; CHECK: $v17 = PseudoVMV1R_V $v10
; CHECK: $v18 = PseudoVMV1R_V $v11
; CHECK: $v19 = PseudoVMV1R_V $v12
; CHECK: $v20 = PseudoVMV1R_V $v13
; CHECK: $v21 = PseudoVMV1R_V $v14
; CHECK: $v22 = PseudoVMV1R_V $v15
; CHECK: $v23 = PseudoVMV1R_V $v16
$v3_v4_v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14_v15_v16
$v4_v5_v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14_v15_v16
$v16_v17_v18_v19_v20_v21_v22 = COPY $v10_v11_v12_v13_v14_v15_v16
$v17_v18_v19_v20_v21_v22_v23 = COPY $v10_v11_v12_v13_v14_v15_v16
...
---
name: copy_zvlsseg_N8
body: |
bb.0:
; CHECK-LABEL: name: copy_zvlsseg_N8
; CHECK: $v2 = PseudoVMV1R_V $v10
; CHECK: $v3 = PseudoVMV1R_V $v11
; CHECK: $v4 = PseudoVMV1R_V $v12
; CHECK: $v5 = PseudoVMV1R_V $v13
; CHECK: $v6 = PseudoVMV1R_V $v14
; CHECK: $v7 = PseudoVMV1R_V $v15
; CHECK: $v8 = PseudoVMV1R_V $v16
; CHECK: $v9 = PseudoVMV1R_V $v17
; CHECK: $v3 = PseudoVMV1R_V $v10
; CHECK: $v4 = PseudoVMV1R_V $v11
; CHECK: $v5 = PseudoVMV1R_V $v12
; CHECK: $v6 = PseudoVMV1R_V $v13
; CHECK: $v7 = PseudoVMV1R_V $v14
; CHECK: $v8 = PseudoVMV1R_V $v15
; CHECK: $v9 = PseudoVMV1R_V $v16
; CHECK: $v10 = PseudoVMV1R_V $v17
; CHECK: $v24 = PseudoVMV1R_V $v17
; CHECK: $v23 = PseudoVMV1R_V $v16
; CHECK: $v22 = PseudoVMV1R_V $v15
; CHECK: $v21 = PseudoVMV1R_V $v14
; CHECK: $v20 = PseudoVMV1R_V $v13
; CHECK: $v19 = PseudoVMV1R_V $v12
; CHECK: $v18 = PseudoVMV1R_V $v11
; CHECK: $v17 = PseudoVMV1R_V $v10
; CHECK: $v18 = PseudoVMV1R_V $v10
; CHECK: $v19 = PseudoVMV1R_V $v11
; CHECK: $v20 = PseudoVMV1R_V $v12
; CHECK: $v21 = PseudoVMV1R_V $v13
; CHECK: $v22 = PseudoVMV1R_V $v14
; CHECK: $v23 = PseudoVMV1R_V $v15
; CHECK: $v24 = PseudoVMV1R_V $v16
; CHECK: $v25 = PseudoVMV1R_V $v17
$v2_v3_v4_v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14_v15_v16_v17
$v3_v4_v5_v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14_v15_v16_v17
$v17_v18_v19_v20_v21_v22_v23_v24 = COPY $v10_v11_v12_v13_v14_v15_v16_v17
$v18_v19_v20_v21_v22_v23_v24_v25 = COPY $v10_v11_v12_v13_v14_v15_v16_v17
...