[SYCL] Add design document for SYCL mode

[bader]

Summary

Initial version of the document covers high level details of overall
design and SYCL mode support in the front-end compiler.

[keryell]

Great to have some design documentation!
Just a feedback on the first 20%...

clang/docs/SYCLSupport.md

24

SPIR-V is just an example

36

49

56

57

58

61

Should we add somewhere other back-ends like PTX?

70

81

96

109

115

119

126

We need to introduce USM too somehow...

128

To be generalized to non OpenCL case.

140

To generalize to non SPIR & non OpenCL

141

It is not about overcoming some OpenCL limitations but just to use OpenCL as a back-end.

156

"OpenCL extensions" is probably misleading here and the sentence should be clarified.

173

Where is it?
I guess it is to be landed some day from https://github.com/intel/llvm/blob/sycl/sycl/doc/KernelParameterPassing.md ?

[bader]

Apply most of the comments from Ronan.

[bader]

@keryell, thanks for the feedback.

I applied your suggestions with two exceptions:

1. I'm not sure if other back-ends need special processing for kernel function parameters we apply for SPIR kernels.
2. I'm looking for suggestions on "OpenCL extensions" clarification.

clang/docs/SYCLSupport.md

128

@Naghasan, do you know if CUDA has similar limitation?

[bader]

clang/docs/SYCLSupport.md

141

I replaced "overcome OpenCL limitations" to "use OpenCL as a back-end", but I don't see the difference between these two options.

156

"OpenCL extensions" are two keywords: __kernel and global.

Do you have a suggestion how to improve it?

[keryell]

! In D99190#2650326, @bader wrote:

2. I'm looking for suggestions on "OpenCL extensions" clarification.

I said that "OpenCL extensions" are misleading because it can be understood as either extensions inside OpenCL (cl_khr_ext...) or extensions to C/C++ with specific OpenCL features (like kernel or global).

[bader]

Resolve "OpenCL extensions" ambiguity.

[bader]

In D99190#2652054, @keryell wrote:

! In D99190#2650326, @bader wrote:

2. I'm looking for suggestions on "OpenCL extensions" clarification.

I said that "OpenCL extensions" are misleading because it can be understood as either extensions inside OpenCL (cl_khr_ext...) or extensions to C/C++ with specific OpenCL features (like kernel or global).

Thanks for clarification. I replaced "using OpenCL extensions" with "in OpenCL-like pseudo-code". Hopefully this resolves the ambiguity.

[bader]

Add links to SYCL specification with address space behavior description.

[Anastasia]

clang/docs/SYCLSupport.md

858

FYI OpenCL also deduced private and global address spaces. I suggest you change this to something like:

SYCL doesn't perform address space qualifier inference detailed in v3.0 s6.7.8: https://www.khronos.org/registry/OpenCL/specs/3.0-unified/html/OpenCL_C.html#addr-spaces-inference`.

Since the inference happens in the parsing as a final step (during CodeGen) instead, it would be good to add that certain variables are bind to the physical global memory segments i.e. globals, static locals, etc. You already have some info at the end of the paragraph.

860

I think this implied from the statement above i.e. the address spaces are not inferred.

What might be important to describe is where other objects are bound to i.e. non-globals are bound to a private memory? You could consider refering to OpenCL spec on that since I feel it might be fairly similar?

862

Ok this is an implementation details but from the language sematic it would be good to describe what logic you are expecting.

So Default address space is primarily used for C/C++ flat memory which means everything in standard C or C++ will be in Default and this is where the local memory is allocated too.

When not specified otherwise, objects are allocated by default in a generic address space, which corresponds to the single address space of ISO/IEC 9899:1999.

I am guessing this doesn't entirely apply to SYCL? I think this would be important to clarify so it is clear what your semantic of Default is. It would make sense to reference OpenCL generic address space or any other documentation if you want to be concise.

864

Ok, I suggested to lift this to where you describe the inference. It would be good to elaborate on what objects are bound to what memory segments. You might also refer to OpenCL spec since I believe the memory segments are fairly similar.

Can you explain this point a bit more and pointers to them are cast to generic? Having an example might help too.

865

Ok, I would put the design goals to the top.

Btw I am not sure this is the case "keeps the type system consistent with C++" since your semantic of default address spaces is different to C++. Perhaps you can elaborate more what it means...

887

I don't understand what is the message of this paragraph. The example compiles in accordance with OpenCL language semantic... Perhaps you can elaborate more.

907

I would suggest to move this table to the top and also as an introduction to make references to OpenCL memory model and address space qualifiers to make it clear that this is reused from OpenCL.

920

I am not sure what limited means? I would suggest being more specific and state something like that there is no binding to the constant memory region. Unless this is something that you intend to support later?

923

It would also be good to see some clarifications regarding your address space overlapping rules and the implicit/explicit conversions and whether there is any behavior that doesn't comply to embedded C/OpenCL C: https://www.khronos.org/registry/OpenCL/specs/3.0-unified/html/OpenCL_C.html#addr-spaces-conversions

Also do you have any constraints on variable initialization wrt address spaces?

[bader]

Move address space handling section to https://reviews.llvm.org/D99488 to address https://reviews.llvm.org/D89909#2653452.

[Naghasan]

Added comment for the front end support part.

I think the document present to much at once, front-end, driver, tool chains, SPIR-V backend, compiler-runtime bindings etc.
It is good to have everything eventually, but it would be beneficial to split this patch into more focus ones.
Having a link to the main document in your github would still allow one to get the big picture.

I see the address space bit has already been split, that's better to keep things focused I guess.

In D99190#2650326, @bader wrote:

@keryell, thanks for the feedback.

I applied your suggestions with two exceptions:

1. I'm not sure if other back-ends need special processing for kernel function parameters we apply for SPIR kernels.

I'm not sure TBH, but passing just the object as a whole is not helping DAE passes. So either way, it is not a bad thing to have that processing.

clang/docs/SYCLSupport.md

51

Do you plan on upstreaming your integration header approach ? Even if it is useful in some situations and speeds up the creation of a prototype, it comes with its complications.

An integration header creates a by-product then used as input for another compilation phase. I haven't at the upstream driver capabilities for awhile, but I don't think you can model 2 outputs yet. Are you planing on adding this capability ?
If not, wouldn't that forces you to trigger a compilation step just for the generation of that files ? If so that puts a strong burden on the compilation speed as you now have to process 3 times your input C++ file.

73

First, it must be possible to use any host compiler

I don't understand the link with the integration header. SYCL being implementable as a library is a design principle of the specs but it doesn't means the clang host compiler has to remain a vanilla C++ compiler.

information provided in the integration header is used (included) by the SYCL runtime implementation, so the header must be available before the host compilation starts

Another approach to the integration header would be for clang as the host compiler to generate the used type traits.

123

OpenMP offload uses a similar approach isn't it? Might be worth to describe how the 2 relates to each other and where they diverge.

128

I find "shared" ambiguous, to CUDA developer shared memory is the OpenCL local memory. "Unified" is less prone misinterpretation (and matches the U of USM :).

130

Raw pointers map to kernel parameters one-to-one without additional transformations

Is this true ? I thought they should be passed as "pointer to global memory" (under the OpenCL or CUDA model).

131

132

Won't be better to refer to SPIR or SPIR-V kernels rather than OpenCL ?

Or even SPIR-like or SPIR-defacto to be even less normative.

134

This is a bit ambiguous and leaves the impression you can't objects pass by value.

140

SYCL's mechanism isn't special, just its way to.

Making an analogy with another programming model is I think a good way to describe it, but I would suggest to use a single source programming model. To that end, I think CUDA would be a better programming model to use here.

144

A PTX / cuda backend would use the exact same lowering logic. The generated LLVM IR will look a bit different (as the identification of PTX kernels is different), but this section also applies.

161

This is missing the template instantiation that will eventually lead to that lowering.

I would also suggest to split code block in 2 as to mark what is in header and source file (SYCL code) and what is compiler generated (that pseudo OpenCL).

Might be good to also mention the glue generated in the integration header as this is what allows arguments to be set by the runtime (bridge between the structure in C++ and the SPIR-like kernel arguments).

[bader]

@Anastasia, I've addressed the comments for the address space section in https://reviews.llvm.org/D99488. Let's move discussion there.

clang/docs/SYCLSupport.md

862

I hope that the language semantics defined by the SYCL specification is clear enough. Please, see https://www.khronos.org/registry/SYCL/specs/sycl-2020/html/sycl-2020.html#_address_space_deduction for details. The only thing left for implementation to define is address space assignment for namespace scope variables. I've added a clarification for that at the end of the paragraph.

864

This is a description of how CodeGen library implements Target hooks like getGlobalVarAddressSpace/getASTAllocaAddressSpace. As it's not related to SYCL, I just removed this confusing sentence.

865

Moved right after the links to SYCL specification.

Btw I am not sure this is the case "keeps the type system consistent with C++" your semantic of default address spaces is different to C++

The point here is that SYCL compiler doesn't change standard C++ types by assigning non-default address space attribute implicitly. That way C++ types not using extensions are left intact.

887

This example demonstrates the problem with compiling C++ code when address space type qualifiers are inferred.

The example compiles in accordance with OpenCL language semantic...

https://godbolt.org/z/9jzxK5xc4 - ToT clang doesn't compile this example.

920

I removed this confusing section. It describes the functionality, which is not being considered for upstream yet.

923

Added.

I don't have anything in addition to SYCL and SPIR constraints.

[bader]

Apply code review comments from @Naghasan.

Reduced the scope of this patch to front-end compiler part.

[bader]

clang/docs/SYCLSupport.md

73

First, it must be possible to use any host compiler

I don't understand the link with the integration header. SYCL being implementable as a library is a design principle of the specs but it doesn't means the clang host compiler has to remain a vanilla C++ compiler.

information provided in the integration header is used (included) by the SYCL runtime implementation, so the header must be available before the host compilation starts

Another approach to the integration header would be for clang as the host compiler to generate the used type traits.

If there are no objections from @keryell, I'd like to prototype this approach for SYCL first to make sure there are no blocking issues.
This option seems to be worth to explore considering integration header approach disadvantages.

123

Do you mean the approach OpenMP compiler uses to outline single-source code parts to offload?
To be honest, I'm not sure... @ABataev, is there any description how OpenMP compiler outlines device code?
https://clang.llvm.org/docs/OpenMPSupport.html doesn't provide much details unfortunately.

130

Good catch. I'll adjust the wording.

132

Is it okay if I refer to OpenCL SPIR-V environment specification:
https://www.khronos.org/registry/OpenCL/specs/3.0-unified/html/OpenCL_Env.html#_kernels?

134

Agree. Removed.

161

This is missing the template instantiation that will eventually lead to that lowering.
I would also suggest to split code block in 2 as to mark what is in header and source file (SYCL code) and what is compiler generated (that pseudo OpenCL).

Do you suggest to sketch an SYCL kernel invocation API usage example with the complete implementation of these methods to demonstrate the full stack? I was trying to avoid runtime/header part of implementation in this section and describe only API compiler relies on or provides for the runtime library. I think these details were in this document before, but moved to https://github.com/intel/llvm/blob/sycl/sycl/doc/KernelParameterPassing.md referenced below.

Might be good to also mention the glue generated in the integration header as this is what allows arguments to be set by the runtime (bridge between the structure in C++ and the SPIR-like kernel arguments).

I've mentioned that, but I hope KernelParameterPassing.md document provides the rest of the details.
Is that okay?

[ABataev]

clang/docs/SYCLSupport.md

123

I don't think we have anything like this. Moreover, currently, there are 2 different models, one with outlining by the frontend and another one with the outlining by the LLVM.

[tschuett]

The OMPIRBuilder is the modern version of late outlining:
https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
You may consider to go that way with SYCL as well.

[bader]

Convert document from Markdown to ReST format.

[keryell]

In D99190#2659571, @tschuett wrote:

The OMPIRBuilder is the modern version of late outlining:
https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
You may consider to go that way with SYCL as well.

triSYCL had a late outlining version, giving different trade-offs. https://github.com/triSYCL/llvm/blob/sycl/master/lib/SYCL/SYCLKernelFilter.cpp
Now we are just using the early outliner of oneAPI DPC++ because there are quite more developers working on it. :-)

[keryell]

clang/docs/SYCLSupport.md

73

First, it must be possible to use any host compiler

I don't understand the link with the integration header. SYCL being implementable as a library is a design principle of the specs but it doesn't means the clang host compiler has to remain a vanilla C++ compiler.

information provided in the integration header is used (included) by the SYCL runtime implementation, so the header must be available before the host compilation starts

Another approach to the integration header would be for clang as the host compiler to generate the used type traits.

Type traits are somehow misleading and probably implementation details.
I guess what this means is a meta-representation of the kernels and their API/ABI.

If there are no objections from @keryell, I'd like to prototype this approach for SYCL first to make sure there are no blocking issues.
This option seems to be worth to explore considering integration header approach disadvantages.

No objection.
triSYCL did not have this integration header since we were using Clang as the host compiler and were able to generate directly the kernel call on the host https://github.com/triSYCL/llvm/blob/sycl/master/lib/SYCL/SYCLSerializeArguments.cpp and the kernel stub on device https://github.com/triSYCL/llvm/blob/sycl/master/lib/SYCL/SYCLSerializeArgumentsInside.cpp

Obviously, it was in the context of late outlining in LLVM but it can work with early outlining in Clang.

[Naghasan]

clang/docs/SYCLSupport.md

123

I mentioned that as I know there is some support for CUDA and the clang driver openmp offload works with multiple frontend passes.
If the model(s) is too different then there is no point going further here.

Moreover, currently, there are 2 different models, one with outlining by the frontend and another one with the outlining by the LLVM.

I do recall some brief conversations about that. Are they meant to work in pair or one aims to replace the other ?

161

Do you suggest to sketch an SYCL kernel invocation API usage example with the complete implementation of these methods to demonstrate the full stack?

Not the full stack, I agree that would be too much. Just the bare minimal that can show where the global int* a comes from and help connecting the dots. I agree details should be kept in the kernel param passing document.

So maybe consider adding something of those lines:

class MyObj {
  accessor<int> _ptr; // accessor<int> contains a pointer to the global address space.
public:

  void operator()(); // Body of the kernel
};

[...]
MyObj Obj{/*some init*/};
sycl_kernel_function<MyObj>(Obj);

This shows the instanciation and one can make the relation between this and the pseudo OpenCL kernel.

[bader]

Applied code review suggestions from @Naghasan.

clang/docs/SYCLSupport.md

123

What do say if add a TODO here (or in a separate TODO document) to study more about differences between SYCL/OpenMP-offload/CUDA implementation designs?
It seems to be useful to understanding if we want to re-use other programming model experience with implementing common tasks like device code outlining.

[Naghasan]

clang/docs/SYCLSupport.md

123

fine by me :)

clang/docs/SYCLSupport.rst

198 ↗

(On Diff #334680)

Oups sorry, I just noticed I made a mistake in my suggestion, that's more in line with the statement KernelFuncObj.A.__init(a); in the pseudo opencl

[bader]

Added simplified accessor declaration to the example and TODO section.

[bader]

Fixed a typo in the code example.

[bader]

clang/docs/SYCLSupport.md

123

I've added a TODO section to the document.

clang/docs/SYCLSupport.rst

198 ↗

(On Diff #334680)

Thanks. Fixed.

[bader]

clang/docs/SYCLSupport.md

51

It looks like Mike addressed this issue with https://github.com/intel/llvm/pull/3471. :)

[Naghasan]

LGTM

[bader]

Rebased on ToT to resolve merge conflicts.

clang/docs/SYCLSupport.md

+# SYCL Compiler and Runtime architecture design
+
+## Introduction
+
+This document describes the architecture of the SYCL compiler and runtime
+library.
+
+## SYCL Compiler architecture
+
+SYCL application compilation flow for `spir`/`spir64` target:
+
+![High level component diagram for SYCL Compiler](images/Compiler-HLD.svg)
+
+*Diagram 1. Application build flow.*
+
+SYCL compiler logically can be split into the host compiler and a number of
+device compilers—one per each supported target. Clang driver orchestrates the
+compilation process, it will invoke the device compiler once per each requested
+target, then it will invoke the host compiler to compile the host part of a
+SYCL source. In the simplest case, when compilation and linkage are done in one
+compiler driver invocation, once compilation is finished, the device object
+files (which are really LLVM IR files) are linked with the `llvm-link` tool.
+The resulting LLVM IR module can additionally processed to get program format
+suitable for execution by specific back-end. For instance, `llvm-spirv` tool
+translates LLVM bitcode to SPIR-V module for OpenCL back-end or `ptxas`/`fatbin`
+tools prepare LLVM for execution via CUDA back-end. After that
+`clang-offload-wrapper` tool wraps device module in a host object file. Once all
+the host object files and the wrapped object with device code are ready, the
+driver invokes the usual platform linker and the final executable called "fat
+binary" is produced. This is a host executable or library with embedded linked
+images for each target specified at the command line.
+
+There are many variations of the compilation process depending on whether user
+chose to do one or more of the following:
+
+- perform compilation separately from linkage
+- compile the device module ahead-of-time for one or more targets
+- perform device code splitting so that device code is distributed across
+  multiple modules rather than enclosed in a single one
+- perform linkage of static device libraries
+Sections below provide more details on some of those scenarios.
+
+SYCL sources can be also compiled as a regular C++ code, in this mode there is
+no "device part" of the code — everything is executed on the host.
+
+Device compiler is further split into the following major components:
+
+- **Front-end** - parses input source, "outlines" device part of the code,
+applies additional restrictions on the device code (e.g. no exceptions or
+virtual calls), generates LLVM IR for the device code only and an "integration
+header" which provides information like kernel name, parameters order and data
+type for the runtime library.
+- **Middle-end** - transforms the initial LLVM IR to get consumed by the
+back-end. Today middle-end transformations include subset of LLVM standard
+passes:
+  - Any LLVM IR transformation can be applied with only one limitation:
+    the back-end compiler should be able to handle the transformed LLVM IR.
+    NOTE: the performance impact of transformation passes depends on accurate
+    target information, so it makes sense to disable such transformation for
+    "virtual" targets like SPIR.
+  - Optionally: Address space inference pass
+  - Optionally: LLVM IR -> SPIR-V translator or LLVM -> PTX.
+- **Back-end** - produces native "device" code. It is shown as
+"Target-specific LLVM compiler" box on Diagram 1. It is invoked either at
+compile time (in ahead-of-time compilation scenario) or at runtime
+(in just-in-time compilation scenario).
+
+*Design note: in current design we use SYCL device front-end compiler to produce
+the integration header for two reasons. First, it must be possible to use any
+host compiler to produce SYCL heterogeneous applications. Second, even if the
+same Clang compiler is used for the host compilation, information provided in
+the integration header is used (included) by the SYCL runtime implementation, so
+the header must be available before the host compilation starts.*
+
+### SYCL support in Clang front-end
+
+SYCL support in Clang front-end can be split into the following components:
+
+- Device code outlining. This component is responsible for identifying and
+outlining "device code" in the single source.
+- SYCL kernel function object (functor or lambda) lowering. This component
+creates a SPIR kernel function interface for SYCL kernels.
+- Device code diagnostics. This component enforces language restrictions on
+device code.
+- Integration header generation. This component emits information required for
+binding host and device parts of the SYCL code.
+
+#### Device code outlining
+
+Here is a code example of a SYCL program that demonstrates compiler outlining
+work:
+
+```C++
+int foo(int x) { return ++x; }
+int bar(int x) { throw std::exception{"CPU code only!"}; }
+...
+using namespace sycl;
+queue Q;
+buffer<int, 1> a{range<1>{1024}};
+Q.submit([&](handler& cgh) {
+      auto A = a.get_access<access::mode::write>(cgh);
+      cgh.parallel_for<init_a>(range<1>{1024}, [=](id<1> index) {
+        A[index] = index[0] * 2 + foo(42);
+      });
+    }
+...
+```
+
+In this example, the compiler needs to compile the lambda expression passed
+to the `sycl::handler::parallel_for` method, as well as the function `foo`
+called from the lambda expression for the device.
+
+The compiler must also ignore the `bar` function when we compile the
+"device" part of the single source code, as it's unused inside the device
+portion of the source code (the contents of the lambda expression passed to the
+`sycl::handler::parallel_for` and any function called from this lambda
+expression).
+
+The current approach is to use the SYCL kernel attribute in the runtime to
+mark code passed to `sycl::handler::parallel_for` as "kernel functions". The
+runtime library can't mark foo as "device" code - this is a compiler job: to
+traverse all symbols accessible from kernel functions and add them to the
+"device part" of the code marking them with the new SYCL device attribute.
+
+#### Lowering of lambda function objects and named function objects
+
+SYCL memory objects shared between host and device can be accessed either
+through raw pointers (to "shared" memory allocated using USM methods) or special
+`accessor` classes. Raw pointers map to kernel parameters one-to-one without
+additional transformations. `accessor` classes require additional processing as
+The "device" implementation of this class contains pointers to the device memory
+as a class member. OpenCL doesn't allow passing structures with pointer type
+members as kernel parameters. All memory objects shared between host and device
+must be passed to the kernel as raw pointers.
+
+SYCL also has a special mechanism for passing kernel arguments from host to
+the device. In OpenCL kernel arguments are set by calling `clSetKernelArg`
+function for each kernel argument, meanwhile in SYCL all the kernel arguments
+are fields of "SYCL kernel function" which can be defined as a lambda function
+or a named function object and passed as an argument to SYCL function for
+invoking kernels (such as `parallel_for` or `single_task`). For example, in the
+previous code snippet above `accessor` `A` is one such captured kernel argument.
+
+To facilitate the mapping of SYCL kernel data members to SPIR kernel arguments
+and use OpenCL as a back-end we added the generation of an SPIR kernel
+function inside the compiler. A SPIR kernel function contains the body of the
+SYCL kernel function, receives OpenCL-like parameters and additionally does some
+manipulation to initialize SYCL kernel data members with these parameters. In
+some pseudo code the SPIR kernel function for the previous code snippet above
+looks like this:
+
+```C++
+// SYCL kernel is defined in SYCL headers:
+template <typename KernelName, typename KernelType/*, ...*/>
+__attribute__((sycl_kernel)) void sycl_kernel_function(KernelType KernelFuncObj) {
+  // ...
+  KernelFuncObj();
+}
+
+// Generated kernel function (expressed in OpenCL-like pseudo-code)
+__kernel KernelName(global int* a) {
+  KernelType KernelFuncObj; // Actually kernel function object declaration
+  // doesn't have a name in AST.
+  // Let the kernel function object have one captured field - accessor A.
+  // We need to init it with global pointer from arguments:
+  KernelFuncObj.A.__init(a);
+  // Body of the SYCL kernel from SYCL headers:
+  {
+    KernelFuncObj();
+  }
+}
+```
+
+Kernel function is generated by the compiler from Sema library using AST
+nodes. Additional details of kernel parameter passing may be found in the
+document
+[SYCL Kernel Parameter Handling and Array Support](https://github.com/intel/llvm/blob/sycl/sycl/doc/KernelParameterPassing.md).
+
+[//]: # (TODO: move KernelParameterPassing.md to llvm-project)
+
+### SYCL support in the driver
+
+SYCL offload support in the driver is based on the clang driver concepts and
+defines:
+
+- target triple and a native tool chain for each target (including "virtual"
+targets like SPIR).
+- SYCL offload action based on generic offload action.
+
+SYCL compilation pipeline has a peculiarity compared to other compilation
+scenarios - some of the actions in the pipeline may output multiple "clusters"
+of files, consumed later by other actions. For example, each device binary maybe
+accompanied by a symbol table and a specialization constant map - additional
+information used by the SYCL runtime library - and it needs to be stored into
+the device binary descriptor by the offload wrapper tool. With device code
+splitting feature enabled, there can be multiple such sets (clusters) of files -
+one per each separate device binary.
+
+Current design of clang driver doesn't allow to model that, namely:
+
+1. Multiple inputs/outputs in the action graph.
+2. Logical grouping of multiple inputs/outputs. For example, an input or output
+can consist of multiple pairs of files, where each pair represents information
+for a single device code module: [a file with device code, a file with exported
+symbols].
+
+To support this, SYCL introduces the `file-table-tform` tool. This tool can
+transform file tables following commands passed as input arguments. Each row
+in the table represents a file cluster, each column - a type of data associated
+with a cluster. The tool can replace and extract columns. For example, the
+`sycl-post-link` tool can output two file clusters and the following file
+table referencing all the files in the clusters:
+
+```
+  [Code|Symbols|Properties]
+  a_0.bc|a_0.sym|a_0.props
+  a_1.bc|a_1.sym|a_1.props
+```
+
+When participating in the action graph this tool inputs a file table
+(`TY_Tempfiletable` clang input type) and/or a file list (`TY_Tempfilelist`),
+performs requested transformations and outputs a file table or list. From the
+clang design standpoint there is still single input and output, even though in
+reality there are multiple.
+
+For example, depending on compilation options, files from the "Code" column
+above may need to undergo AOT compilation after the device code splitting step,
+performed as a part of the code transformation sequence done by the
+`sycl-post-link` tool. The driver will then:
+
+- Use the `file-table-tform` to extract the code files and produce a file
+  list:
+
+```
+a_0.bc
+a_1.bc
+```
+
+- Pass this file list to the `llvm-foreach` tool along with AOT compilation
+command to invoke it on every file in the list. This will result in another
+file list
+
+```
+a_0.bin
+a_1.bin
+```
+
+- Then `file-table-tform` is invoked again to replace `.bc` with `.bin` in
+the filetable to get a new filetable:
+
+```
+  [Code|Symbols|Properties]
+  a_0.bin|a_0.sym|a_0.props
+  a_1.bin|a_1.sym|a_1.props
+```
+
+- Finally, this filetable is passed to the `clang-offload-wrapper` tool to
+construct a wrapper object which embeds all those files.
+
+Note that the graph does not change when more rows (clusters) or columns
+(e.g. a "manifest" file) are added to the table.
+
+#### Enable SYCL offload
+
+To enable compilation following single-source multiple compiler-passes (SMCP)
+technique which is described in the SYCL specification, a special option
+must be passed to the clang driver:
+
+`-fsycl`
+
+With this option specified, the driver will invoke the host compiler and a
+number of SYCL device compilers for targets specified in the `-fsycl-targets`
+option. If `-fsycl-targets` is not specified, then single SPIR-V target is
+assumed, and single device compiler for this target is invoked.
+
+The option `-sycl-std` allows specifying which version of
+the SYCL standard will be used for the compilation.
+The default value for this option is `1.2.1`.
+
+#### Ahead of time (AOT) compilation
+
+Ahead-of-time compilation is the process of invoking the back-end at compile
+time to produce the final binary, as opposed to just-in-time (JIT) compilation
+when final code generation is deferred until application runtime time.
+
+AOT compilation reduces application execution time by skipping JIT compilation
+and final device code can be tested before deploying.
+
+JIT compilation provides portability of device code and target specific
+optimizations.
+
+#### List of native targets
+
+The ahead-of-time compilation mode implies that there must be a way to specify
+a set of target architectures for which to compile device code. By default, the
+compiler generates SPIR-V and device JIT compiler produces native target binary.
+
+To produce binaries for target architectures identified by target triples
+`triple1` and `triple2`, the following SYCL compiler options are used:
+
+`-fsycl-targets=triple1,triple2`
+
+will produce binaries from SYCL kernels for devices identified by the two
+target triples. This basically tells the driver which device compilers must be
+invoked to compile the SYCL kernel code. By default, the JIT compilation
+approach is assumed and device code is compiled for a single target triple -
+`[spir,spir64]-*-*`.
+
+#### Device code formats
+
+Each target may support a number of code forms, each device compiler defines
+and understands mnemonics designating a particular code form, for example
+"`visa:3.3`" could designate virtual ISA version 3.3 for Intel GPU target (Gen
+architecture). User can specify desired code format using the target-specific
+option mechanism, similar to OpenMP.
+
+`-Xsycl-target-backend=<triple> "arg1 arg2 ..."`
+
+For example, to support offload to Gen9/vISA3.3, the following options would be
+used:
+
+`-fsycl -fsycl-targets=spir64_gen-unknown-unknown-sycldevice -Xsycl-target-backend "-device skl"`
+
+The driver passes the `-device skl` parameter directly to the Gen device backend
+compiler `ocloc` without parsing it.
+
+**TBD:** Having multiple code forms for the same target in the fat binary might
+mean invoking device compiler multiple times. Multiple invocations are not
+needed if these forms can be dumped at various compilation stages by the single
+device compilation, like SPIR-V → visa → ISA. But if e.g. `gen9:visa3.2` and
+`gen9:visa3.3` are needed at the same time, then some mechanism is needed.
+Should it be a dedicated target triple for each needed visa version or Gen
+generation?
+
+#### Separate Compilation and Linking
+
+The compiler supports such features as
+
+- linking of device code obtained from different source files before generating
+  the final SPIR-V to be fed to the back-end.
+- splitting application build into separate compile and link steps.
+
+Overall build flow changes compared to the one shown on the Diagram 1
+above in the following way.
+**Compilation step** ends with engaging the offload
+bundler to generate so-called "fat object" for each
+<host object, device code IR> pair produced from the same heterogeneous source.
+The fat object files become the result of compilation similar to object
+files with usual non-offload compiler.
+**Link step** starts with breaking the input fat objects back into their
+constituents, then continue the same way as on the Diagram 1 - link host code
+and device code separately and finally produce a "fat binary".
+
+The diagram below illustrates the changes in the build flow. The offload
+bundler/unbundler actions are basically inserted between the `llvm-link` and
+the `linker` invocations as shown on the Diagram 1.
+
+![Multi source compilation flow](images/SplitCompileAndLink.svg)
+*Diagram 2. Split compilation and linkage.*
+
+*Current implementation uses LLVM IR as a default device binary format for `fat
+objects` and translates "linked LLVM IR" to SPIR-V. One of the reasons for this
+decision is that SPIR-V doesn't support linking template functions, which could
+be defined in multiple modules and linker must resolve multiple definitions.
+LLVM IR uses function attributes to satisfy "one definition rule", which have
+no counterparts in SPIR-V.*
+
+#### Fat binary creation details
+
+"Fat binary" is a result of the final host linking step - this is a host binary
+with device binary(s) embedded. When run, it automatically registers
+all available device binaries within the SYCL runtime library. This section
+describes how this is achieved.
+
+The output fat binary is created with usual linker - e.g. `ld` on Linux and
+`link.exe` on Windows. For the linker to be able to embed the device binaries,
+they are first "wrapped" into a host object file called "wrapper object". Then
+this wrapper object is linked normally with the rest of host objects and/or
+libraries.
+
+The wrapper object is created by the `clang-offload-wrapper` tool, or simply
+"offload wrapper". The created wrapper object has two main components:
+
+1. Global symbol - offload descriptor - pointing to a special data structure
+put into in the object's data section. It encompasses all needed information
+about the wrapped device binaries - number of binaries, symbols each binary
+defines, etc. - as well as the binaries themselves.
+2. Registration/unregistration functions. The first one is put into a special
+section so that it is invoked when the parent fat binary is loaded into a
+process at runtime, the second one is put into another section to be invoked
+when the parent fat binary is unloaded. The registration function basically
+takes the pointer to the offload descriptor and invokes SYCL runtime library's
+registration function passing it as a parameter.
+
+The offload descriptor type hierarchy is described in the `pi.h` header. The
+top-level structure is `pi_device_binaries_struct`.
+
+#### Device Link
+
+The -fsycl-link flag instructs the compiler to fully link device code without
+fully linking host code. The result of such a compile is a fat object that
+contains a fully linked device binary. The primary motivation for this flow
+is to allow users to save re-compile time when making changes that only affect
+their host code. In the case where device image generation takes a long time
+(e.g. FPGA), this savings can be significant.
+
+For example, if the user separated source code into four files: dev_a.cpp,
+dev_b.cpp, host_a.cpp and host_b.cpp where only dev_a.cpp and dev_b.cpp contain
+device code, they can divide the compilation process into three steps:
+
+1. Device link: dev_a.cpp dev_b.cpp -> dev_image.o (contain device image)
+2. Host Compile (c): host_a.cpp -> host_a.o; host_b.cpp -> host_b.o
+3. Linking: dev_image.o host_a.o host_b.o -> executable
+
+Step 1 can take hours for some targets. But if the user wishes to recompile
+after modifying only host_a.cpp and host_b.cpp, they can simply run steps 2 and
+3 without rerunning the expensive step 1.
+
+The compiler is responsible for verifying that the user provided all the
+relevant files to the device link step. There are 2 cases that have to be
+checked:
+
+1. Missing symbols referenced by the kernels present in the device link step
+(e.g. functions called by or global variables used by the known kernels).
+2. Missing kernels.
+
+Case 1 can be identified in the device binary generation stage (step 1) by
+scanning the known kernels. Case 2 must be verified by the driver by checking
+for newly introduced kernels in the final link stage (step 3).
+
+The llvm-no-spir-kernel tool was introduced to facilitate checking for case 2 in
+the driver. It detects if a module includes kernels and is invoked as follows:
+
+```bash
+llvm-no-spir-kernel host.bc
+```
+
+It returns 0 if no kernels are present and 1 otherwise.
+
+#### Device code post-link step
+
+At link time all the device code is always linked into a single LLVM IR module.
+`sycl-post-link` tool performs a number of final transformations on this LLVM IR
+module before handing it off to the offload wrapper. Those include:
+
+- device code splitting
+- symbol table generation
+- specialization constants lowering
+
+Depending on options, `sycl-post-link` can output either a single LLVM IR file,
+or multiple files plus a file table referencing all of them. See the
+"SYCL support in the driver" section for overall description of file table. The
+diagram below shows possible clang action graphs which compilation process will
+follow from the single linked LLVM IR module to creating the wrapper object.
+There are multiple possible variants of the graph depending on:
+
+- specific target requirements
+- device code splitting
+- AOT compilation
+
+![Multi source compilation flow](images/DeviceLinkAndWrap.svg)
+
+*Diagram 3. Device code link flows.*
+
+Colors of the graph's edges show which paths are taken depending on the above
+factors. Each edge is also annotated with the input/output file type.
+The diagram does not show the `llvm-foreach` tool invocations for clarity.
+This tool invokes given command line over each file in a file list. In this
+diagram the tool is applied to `llvm-spirv` and AOT backend whenever the
+input/output type is `TY_tempfilelist`. The second invocation of the
+`file-table-tform` takes two inputs - the file table and a file list coming
+either from `llvm-spirv` or from the AOT backend.
+
+##### Device code splitting
+
+Putting all device code into a single SPIR-V module does not work well in the
+following cases:
+
+1. There are thousands of kernels defined and only small part of them is used at
+run-time. Having them all in one SPIR-V module significantly increases JIT time.
+2. Device code can be specialized for different devices. For example, kernels
+that are supposed to be executed only on FPGA can use extensions available for
+FPGA only. This will cause JIT compilation failure on other devices even if this
+particular kernel is never called on them.
+
+To resolve these problems the compiler can split a single module into smaller
+ones. The following features is supported:
+
+- Emitting a separate module for source (translation unit)
+- Emitting a separate module for each kernel
+
+The current approach is:
+
+- Generate special meta-data with translation unit ID for each kernel in SYCL
+front-end. This ID will be used to group kernels on per-translation unit basis
+- Link all device LLVM modules using llvm-link
+- Perform split on a fully linked module
+- Generate a symbol table (list of kernels) for each produced device module for
+proper module selection in runtime
+- Perform SPIR-V translation and AOT compilation (if requested) on each produced
+module separately
+- Add information about presented kernels to a wrapping object for each device
+image
+
+Device code splitting process:
+![Device code splitting](images/DeviceCodeSplit.svg)
+
+The "split" box is implemented as functionality of the dedicated tool
+`sycl-post-link`. The tool runs a set of LLVM passes to split input module and
+generates a symbol table (list of kernels) for each produced device module.
+
+To enable device code split, a special option must be passed to the clang
+driver:
+
+`-fsycl-device-code-split=<value>`
+
+There are three possible values for this option:
+
+- `per_source` - enables emitting a separate module for each source (translation
+unit)
+- `per_kernel` - enables emitting a separate module for each kernel
+- `off` - disables device code split
+
+##### Symbol table generation
+
+TBD
+
+##### Specialization constants lowering
+
+See [corresponding documentation](SpecializationConstants.md)
+
+#### CUDA support
+
+The driver supports compilation to NVPTX when the
+`nvptx64-nvidia-cuda-sycldevice` is passed to `-fsycl-targets`.
+
+Unlike other AOT targets, the bitcode module linked from intermediate compiled
+objects never goes through SPIR-V. Instead it is passed directly in bitcode form
+down to the NVPTX Back End. All produced bitcode depends on two libraries,
+`libdevice.bc` (provided by the CUDA SDK) and `libspirv-nvptx64--nvidiacl.bc`
+(built by the libclc project).
+
+##### Device code post-link step for CUDA
+
+During the "PTX target processing" in the device linking step [Device
+code post-link step](#device-code-post-link-step), the llvm bitcode
+objects for the CUDA target are linked together alongside
+`libspirv-nvptx64--nvidiacl.bc` and `libdevice.bc`, compiled to PTX
+using the NVPTX backend and assembled into a cubin using the `ptxas`
+tool (part of the CUDA SDK). The PTX file and cubin are assembled
+together using `fatbinary` to produce a CUDA fatbin. The CUDA fatbin
+is then passed to the offload wrapper tool.
+
+![NVPTX AOT build](images/DevicePTXProcessing.svg)
+
+##### Checking if the compiler is targeting NVPTX
+
+When the SYCL compiler is in device mode and targeting the NVPTX backend,
+compiler defines the macro `__SYCL_NVPTX__`.
+This macro can safely be used to enable NVPTX specific code path in SYCL
+kernels.
+
+*Note: this macro is defined only during the device compilation phase.*
+
+##### NVPTX Builtins
+
+When the SYCL compiler is in device mode and targeting the NVPTX backend, the
+compiler exposes NVPTX builtins supported by clang.
+
+*Note: this enable NVPTX specific features which cannot be supported by other
+targets or the host.*
+
+Example:
+
+```cpp
+double my_min(double x, double y) {
+#ifdef __SYCL_NVPTX__
+  // Only available if in device mode and
+  // while compiling for the NVPTX target.
+  return __nvvm_fmin_d(x, y);
+#else
+  return x < y ? x : y;
+#endif
+}
+```
+
+##### Local memory support
+
+In CUDA, users can only allocate one chunk of host allocated shared memory
+(which maps to SYCL's local accessors). This chunk of memory is allocated as an
+array `extern __shared__ <type> <name>[];` which LLVM represents as an external
+global symbol to the CUDA shared memory address space. The NVPTX backend then
+lowers this into a `.extern .shared .align 4 .b8` PTX instruction.
+
+In SYCL, users can allocate multiple local accessors and pass them as kernel
+parameters. When the SYCL frontend lowers the SYCL kernel invocation into an
+SPIR-V compliant kernel entry, it lowers local accessors into a pointer to
+SPIR-V Workgroup storage class memory (CUDA shared memory) but this is not legal
+for CUDA kernels.
+
+To legalize the SYCL lowering for CUDA, a SYCL for CUDA specific pass will do
+the following:
+
+- Create a global symbol to the CUDA shared memory address space
+- Transform all pointers to CUDA shared memory into a 32 bit integer
+  representing the offset in bytes to use with the global symbol
+- Replace all uses of the transformed pointers by the address to global symbol
+  offset by the value of the integer passed as parameter
+
+As an example, the following kernel:
+
+```LLVM
+define void @SYCL_generated_kernel(i64 addrspace(3)* nocapture %local_ptr, i32 %arg, i64 addrspace(3)* nocapture %local_ptr2) {
+  %0 = load i64, i64 addrspace(3)* %local_ptr
+  %1 = load i64, i64 addrspace(3)* %local_ptr2
+}
+```
+
+Is transformed into this kernel when targeting CUDA:
+
+```LLVM
+@SYCL_generated_kernel.shared_mem = external dso_local local_unnamed_addr addrspace(3) global [0 x i8], align 4
+
+define void @SYCL_generated_kernel(i32 %local_ptr_offset, i32 %arg, i32 %local_ptr_offset2) {
+  %new_local_ptr = getelementptr inbounds [0 x i8], [0 x i8] addrspace(3)* @SYCL_generated_kernel.shared_mem, i32 0, i32 %local_ptr_offset
+  %new_local_ptr2 = getelementptr inbounds [0 x i8], [0 x i8] addrspace(3)* @SYCL_generated_kernel.shared_mem, i32 0, i32 %local_ptr_offset2
+  %0 = load i32, i32 addrspace(3)* %new_local_ptr
+  %1 = load i64, i64 addrspace(3)* %new_local_ptr2
+}
+```
+
+On the runtime side, when setting local memory arguments, the CUDA PI
+implementation will internally set the argument as the offset with respect to
+the accumulated size of used local memory. This approach preserves the existing
+PI interface.
+
+##### Global offset support
+
+The CUDA API does not natively support the global offset parameter
+expected by the SYCL.
+
+In order to emulate this and make generated kernel compliant, an
+intrinsic `llvm.nvvm.implicit.offset` (clang builtin
+`__builtin_ptx_implicit_offset`) was introduced materializing the use
+of this implicit parameter for the NVPTX backend. The intrinsic returns
+a pointer to `i32` referring to a 3 elements array.
+
+Each non-kernel function reaching the implicit offset intrinsic in the
+call graph is augmented with an extra implicit parameter of type
+pointer to `i32`. Kernels calling one of these functions using
+this intrinsic are cloned:
+
+- the original kernel initializes an array of 3 `i32` to 0 and passes
+  the pointer to this array to each function with the implicit
+  parameter;
+- the cloned function type is augmented with an implicit parameter of
+  type array of 3 `i32`. The pointer to this array is then passed each
+  function with the implicit parameter.
+
+The runtime will query both kernels and call the appropriate one based
+on the following logic:
+
+- If the 2 versions exist, the original kernel is called if global
+  offset is 0 otherwise it will call the cloned one and pass the
+  offset by value;
+- If only 1 function exist, it is assumed that the kernel makes no use
+  of this parameter and therefore ignores it.
+
+As an example, the following code:
+
+```LLVM
+declare i32* @llvm.nvvm.implicit.offset()
+
+define weak_odr dso_local i64 @other_function() {
+  %1 = tail call i32* @llvm.nvvm.implicit.offset()
+  %2 = getelementptr inbounds i32, i32* %1, i64 2
+  %3 = load i32, i32* %2, align 4
+  %4 = zext i32 %3 to i64
+  ret i64 %4
+}
+
+define weak_odr dso_local void @other_function2() {
+  ret
+}
+
+define weak_odr dso_local void @example_kernel() {
+entry:
+  %0 = call i64 @other_function()
+  call void @other_function2()
+  ret void
+}
+```
+
+Is transformed into this in the `sycldevice` environment:
+
+```LLVM
+define weak_odr dso_local i64 @other_function(i32* %0) {
+  %2 = getelementptr inbounds i32, i32* %0, i64 2
+  %3 = load i32, i32* %2, align 4
+  %4 = zext i32 %3 to i64
+
+  ret i64 %4
+}
+
+define weak_odr dso_local void @example_kernel() {
+entry:
+  %0 = alloca [3 x i32], align 4
+  %1 = bitcast [3 x i32]* %0 to i8*
+  call void @llvm.memset.p0i8.i64(i8* nonnull align 4 dereferenceable(12) %1, i8 0, i64 12, i1 false)
+  %2 = getelementptr inbounds [3 x i32], [3 x i32]* %0, i32 0, i32 0
+  %3 = call i64 @other_function(i32* %2)
+  call void @other_function2()
+  ret void
+}
+
+define weak_odr dso_local void @example_kernel_with_offset([3 x i32]* byval([3 x i32]) %0) {
+entry:
+  %1 = bitcast [3 x i32]* %0 to i32*
+  %2 = call i64 @other_function(i32* %1)
+  call void @other_function2()
+  ret void
+}
+```
+
+Note: Kernel naming is not fully stable for now.
+
+### Integration with SPIR-V format
+
+This section explains how to generate SPIR-V specific types and operations from
+C++ classes and functions.
+
+Translation of SYCL C++ programs to the code executable on heterogeneous
+systems can be considered as three step process:
+
+1) translation of SYCL C++ programs into LLVM IR
+1) translation from LLVM IR to SPIR-V
+1) translation from SPIR-V to machine code
+
+LLVM-IR to SPIR-V translation is performed by a dedicated tool -
+[translator](https://github.com/KhronosGroup/SPIRV-LLVM-Translator).
+This tool correctly translates most of regular LLVM IR types/operations/etc to
+SPIR-V.
+
+For example:
+
+- Type: `i32` → `OpTypeInt`
+- Operation: `load` → `OpLoad`
+- Calls: `call` → `OpFunctionCall`
+
+SPIR-V defines special built-in types and operations that do not have
+corresponding equivalents in LLVM IR. E.g.
+
+- Type: ??? → `OpTypeEvent`
+- Operation: ??? → `OpGroupAsyncCopy`
+
+Translation from LLVM IR to SPIR-V for special types is also supported, but
+such LLVM IR must comply to some special requirements. Unfortunately, there is
+no canonical form of special built-in types and operations in LLVM IR, moreover
+we can't re-use existing representation generated by OpenCL C front-end
+compiler. For instance, here is how `OpGroupAsyncCopy` operation looks in LLVM
+IR produced by OpenCL C front-end compiler.
+
+```LLVM
+@_Z21async_work_group_copyPU3AS3fPU3AS1Kfjj(float addrspace(3)*, float addrspace(1)*, i32, i32)
+```
+
+It's a regular function, which can conflict with user code produced from C++
+source.
+
+Our solution re-uses OpenCL data types like sampler, event, image types, etc,
+but we use different spelling to avoid potential conflicts with C++ code.
+Spelling convention for the OpenCL types enabled in SYCL mode is:
+
+```C++
+__ocl_<OpenCL_type_name> // e.g. __ocl_sampler_t, __ocl_event_t
+```
+
+Operations using OpenCL types use special naming convention described in this
+[document](https://github.com/KhronosGroup/SPIRV-LLVM-Translator/blob/master/docs/SPIRVRepresentationInLLVM.rst).
+This solution allows us avoid SYCL specialization in SPIR-V translator and
+leverage clang infrastructure developed for OpenCL types.
+
+SPIR-V operations that do not have LLVM equivalents are **declared**
+(but not defined) in the headers and satisfy following requirements:
+
+- the operation is expressed in C++ as `extern` function not throwing C++
+  exceptions
+- the operation must not have the actual definition in C++ program
+
+For example, the following C++ code is successfully recognized and translated
+into SPIR-V operation `OpGroupAsyncCopy`:
+
+```C++
+template <typename dataT>
+extern __ocl_event_t
+__spirv_OpGroupAsyncCopy(int32_t Scope, __local dataT *Dest,
+                         __global dataT *Src, size_t NumElements,
+                         size_t Stride, __ocl_event_t E) noexcept;
+
+__ocl_event_t e =
+  __spirv_OpGroupAsyncCopy(cl::__spirv::Scope::Workgroup,
+                           dst, src, numElements, 1, E);
+```
+
+#### Some details and agreements on using SPIR-V special types and operations
+
+The SPIR-V specific C++ enumerators and classes are declared in the file:
+`sycl/include/CL/__spirv/spirv_types.hpp`.
+
+The SPIR-V specific C++ function declarations are in the file:
+`sycl/include/CL/__spirv/spirv_ops.hpp`.
+
+The SPIR-V specific functions are implemented in for the SYCL host device here:
+`sycl/source/spirv_ops.cpp`.
+
+### Compiler/Runtime interface
+
+## SYCL Runtime architecture
+
+*TBD*

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+    <g id="shape12-9" v:mID="12" v:groupContext="shape" transform="translate(127.559,-716.762)">
+      <title>Rounded Rectangle.12</title>
+      <desc>void a() {…}</desc>
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+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
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+    <g id="shape13-17" v:mID="13" v:groupContext="shape" transform="translate(127.559,-736.202)">
+      <title>Rounded Rectangle.13</title>
+      <desc>Kernel x() {b();}</desc>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
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+      <text x="26" y="835.98" class="st4" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Kernel x() {b();}</text>   </g>
+    <g id="shape14-24" v:mID="14" v:groupContext="shape" transform="translate(263.622,-711.093)">
+      <title>Rounded Rectangle.14</title>
+      <desc>S2.cpp</desc>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
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+      <title>Rounded Rectangle.15</title>
+      <desc>void b() {…}</desc>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
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+    <g id="shape16-38" v:mID="16" v:groupContext="shape" transform="translate(263.622,-736.202)">
+      <title>Rounded Rectangle.16</title>
+      <desc>Kernel y() {a();}</desc>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
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+      <text x="26.14" y="835.98" class="st4" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Kernel y() {a();}</text>    </g>
+    <g id="shape18-45" v:mID="18" v:groupContext="shape" transform="translate(144.567,-674.646)">
+      <title>Rectangle</title>
+      <desc>Front-end</desc>
+      <v:userDefs>
+        <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+      </v:userDefs>
+      <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
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+      <rect x="0" y="824.076" width="79.3701" height="17.814" class="st6"/>
+      <text x="19.43" y="835.98" class="st4" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Front-end</text>    </g>
+    <g id="shape19-53" v:mID="19" v:groupContext="shape" transform="translate(280.63,-674.646)">
+      <title>Rectangle.19</title>
+      <desc>Front-end</desc>
+      <v:userDefs>
+        <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+      </v:userDefs>
+      <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
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+      <rect x="0" y="824.076" width="79.3701" height="17.814" class="st6"/>
+      <text x="19.43" y="835.98" class="st4" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Front-end</text>    </g>
+    <g id="shape20-60" v:mID="20" v:groupContext="shape" v:layerMember="1" transform="translate(313.228,-711.093)">
+      <title>Dynamic connector</title>
+      <path d="M7.09 841.89 L7.09 854.36" class="st7"/>
+    </g>
+    <g id="shape21-66" v:mID="21" v:groupContext="shape" v:layerMember="1" transform="translate(177.165,-711.093)">
+      <title>Dynamic connector.21</title>
+      <path d="M7.09 841.89 L7.09 854.36" class="st7"/>
+    </g>
+    <g id="shape22-71" v:mID="22" v:groupContext="shape" transform="translate(127.559,-590.412)">
+      <title>Rounded Rectangle.22</title>
+      <desc>S1.bc</desc>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
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+      <title>Rounded Rectangle.23</title>
+      <desc>void a() {…}</desc>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
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+      <desc>Kernel x() {b();} ‘S1’</desc>
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+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
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+    <g id="shape25-96" v:mID="25" v:groupContext="shape" transform="translate(263.622,-590.412)">
+      <title>Rounded Rectangle.25</title>
+      <desc>S2.bc</desc>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
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+      <title>Rounded Rectangle.26</title>
+      <desc>void b() {…}</desc>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
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+    <g id="shape27-110" v:mID="27" v:groupContext="shape" transform="translate(263.622,-614.305)">
+      <title>Rounded Rectangle.27</title>
+      <desc>Kernel y() {a();} ‘S2’</desc>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
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+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
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+      <title>Dynamic connector.28</title>
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+    <g id="shape29-126" v:mID="29" v:groupContext="shape" v:layerMember="1" transform="translate(313.228,-674.646)">
+      <title>Dynamic connector.29</title>
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+    <g id="shape30-131" v:mID="30" v:groupContext="shape" transform="translate(212.598,-552.353)">
+      <title>Rectangle.30</title>
+      <desc>llvm-link</desc>
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+    <g id="shape33-148" v:mID="33" v:groupContext="shape" transform="translate(195.591,-425.197)">
+      <title>Rounded Rectangle.33</title>
+      <desc>S1S2.bc</desc>
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+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
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+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
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+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
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+      <title>Rounded Rectangle.36</title>
+      <desc>Kernel x() {b();} ‘S1’</desc>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
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+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
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+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
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+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
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+      <text x="17.54" y="835.98" class="st4" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Kernel x() {b();} <tspan
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+    <g id="shape37-166" v:mID="37" v:groupContext="shape" transform="translate(195.591,-469.745)">
+      <title>Rounded Rectangle.37</title>
+      <desc>Kernel y() {a();} ‘S2’</desc>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
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+      <g id="shadow37-167" v:groupContext="shadow" v:shadowOffsetX="1.83842E-016" v:shadowOffsetY="-3.00236" v:shadowType="1"
+          transform="matrix(1,0,0,1,0,3.00236)" class="st1">
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+      <path d="M8.91 841.89 L104.48 841.89 A8.90683 8.90683 -180 0 0 113.39 832.98 A8.90683 8.90683 -180 0 0 104.48 824.08
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+      <text x="17.68" y="835.98" class="st4" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Kernel y() {a();} <tspan
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+    <g id="shape38-177" v:mID="38" v:groupContext="shape" transform="translate(195.591,-450.306)">
+      <title>Rounded Rectangle.38</title>
+      <desc>void a() {…}</desc>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
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+      <path d="M8.91 841.89 L104.48 841.89 A8.90683 8.90683 -180 0 0 113.39 832.98 A8.90683 8.90683 -180 0 0 104.48 824.08
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+      <text x="34.87" y="835.98" class="st4" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>void a() {…}</text>   </g>
+    <g id="shape39-184" v:mID="39" v:groupContext="shape" transform="translate(195.591,-430.06)">
+      <title>Rounded Rectangle.39</title>
+      <desc>void b() {…}</desc>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+      </v:userDefs>
+      <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
+      <v:textRect cx="56.6929" cy="832.983" width="113.39" height="17.814"/>
+      <g id="shadow39-185" v:groupContext="shadow" v:shadowOffsetX="1.83842E-016" v:shadowOffsetY="-3.00236" v:shadowType="1"
+          transform="matrix(1,0,0,1,0,3.00236)" class="st1">
+        <path d="M8.91 841.89 L104.48 841.89 A8.90683 8.90683 -180 0 0 113.39 832.98 A8.90683 8.90683 -180 0 0 104.48 824.08
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+      <text x="34.64" y="835.98" class="st4" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>void b() {…}</text>   </g>
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+      <title>Dynamic connector.40</title>
+      <path d="M7.09 841.89 L7.09 855.98" class="st7"/>
+    </g>
+    <g id="shape41-196" v:mID="41" v:groupContext="shape" transform="translate(212.598,-385.512)">
+      <title>Rectangle.41</title>
+      <desc>split</desc>
+      <v:userDefs>
+        <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+      </v:userDefs>
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+      <rect x="0" y="824.076" width="79.3701" height="17.814" class="st6"/>
+      <text x="31.13" y="835.98" class="st10" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>split</text>   </g>
+    <g id="shape44-203" v:mID="44" v:groupContext="shape" v:layerMember="1" transform="translate(245.197,-425.197)">
+      <title>Dynamic connector.44</title>
+      <path d="M7.09 841.89 L7.09 857.6" class="st7"/>
+    </g>
+    <g id="shape55-208" v:mID="55" v:groupContext="shape" transform="translate(42.5197,-289.134)">
+      <title>Rounded Rectangle.55</title>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.28346456692913):1"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.28346456692913):1"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.28346456692913):1"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.28346456692913):1"/>
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+    <g id="shape57-210" v:mID="57" v:groupContext="shape" transform="translate(122.337,-293.184)">
+      <title>Rounded Rectangle.57</title>
+      <desc>S1.bc</desc>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
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+    <g id="shape58-217" v:mID="58" v:groupContext="shape" transform="translate(122.337,-298.854)">
+      <title>Rounded Rectangle.58</title>
+      <desc>void b() {…}</desc>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
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+    <g id="shape59-224" v:mID="59" v:groupContext="shape" transform="translate(122.337,-318.293)">
+      <title>Rounded Rectangle.59</title>
+      <desc>Kernel x() {b();}</desc>
+      <v:userDefs>
+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
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+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
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+      <title>Rounded Rectangle.60</title>
+      <desc>S1.txt</desc>
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+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
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+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
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+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
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+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
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+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
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+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
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+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
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+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
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+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
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+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
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+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.28346456692913):1"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.28346456692913):1"/>
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+    <g id="shape63-247" v:mID="63" v:groupContext="shape" transform="translate(343.44,-292.781)">
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+      <desc>S2.bc</desc>
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+        <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
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+      <title>Rounded Rectangle.64</title>
+      <desc>void a() {…}</desc>
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+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
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+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
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+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
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+      <title>Rounded Rectangle.65</title>
+      <desc>Kernel y() {a();}</desc>
+      <v:userDefs>
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+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.123708024321):1"/>
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+    <g id="shape66-268" v:mID="66" v:groupContext="shape" transform="translate(273.655,-293.184)">
+      <title>Rounded Rectangle.66</title>
+      <desc>S2.txt</desc>
+      <v:userDefs>
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+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+        <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
+        <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15748031496063):24"/>
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+        <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.090240364691256):1"/>
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+      <title>Rounded Rectangle.67</title>
+      <desc>“y”</desc>
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+        <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+        <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
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