User Details
- User Since
- Apr 10 2013, 11:30 AM (546 w, 2 d)
Tue, Sep 12
Thanks for the clarifications.
Fri, Sep 1
Aug 8 2023
Jul 25 2023
Interesting.
Jul 24 2023
Jul 14 2023
Apr 8 2023
Feb 28 2023
Dec 18 2022
I wonder whether we could not factorize some code/attribute/logic with AMDGPU or SYCL.
Is the use case to have for example CUDA+HIP+SYCL in the same TU and thus there is a need for different attributes
Mar 22 2022
Yes, your comment idea looks good and helpful to me.
Thanks.
Mar 18 2022
Jan 24 2022
That looks good.
Nov 18 2021
Sep 17 2021
Sep 13 2021
While it might be possible to extend arbitrarily C++, I have the feeling that having just 1 destructor and having a different code path-code according to the address space could be enough.
It could be possible to write:
Mar 31 2021
Mar 26 2021
An FPGA programmer is hitting this issue from your unit test:
c++ signed _ExtInt(1) m; // expected-error{{signed _ExtInt must have a bit size of at least 2}}
Why do you not allow a type able to represent {-1, 0}?
Mar 25 2021
! In D99190#2650326, @bader wrote:
- I'm looking for suggestions on "OpenCL extensions" clarification.
By looking at this, did we forgot about adding some documentation along what we have for https://clang.llvm.org/docs/ClangOffloadBundler.html ?
Mar 24 2021
Great to have some design documentation!
Just a feedback on the first 20%...
Mar 1 2021
Dec 10 2020
Nov 2 2020
Oct 15 2020
Oct 12 2020
Enabling this feature only with SYCL seems like an easy and quick mitigation, as SYCL compilers downstream can easily update their runtime to the new builtin name.
Otherwise, just removing a feature used for almost 6 months will cause some kind of forking pain...
Anyway, improving the feature and implementation at the same time with an RFC for a wider usage looks like a great idea.
Oct 10 2020
@erichkeane @alexandre.isoard @Naghasan: any feedback in the context of SYCL & HLS C++ about this feature extension?
Oct 9 2020
Great feature for all the weird pieces of hardware all around the world! :-)
Oct 2 2020
Sep 28 2020
Be lazy
Jul 14 2020
The idea of this _ExtInt is to have some extensions.
Since it is an extension, why preventing its use?
For example if I want my 18 bit FPGA BRAM to be accessed atomically?
Or is there an assumption that atomic access can be enabled back with some other mode, such as SYCL or HLS C++?
Jul 6 2020
Adding Tyker (Gauthier Harnisch) because of SYCL similarity
Apr 2 2020
Feb 28 2020
Feb 27 2020
Feb 18 2020
Feb 6 2020
Jan 31 2020
Dec 10 2019
Jul 9 2019
Good improvement!
Jun 19 2019
May 30 2019
May 7 2019
May 3 2019
May 1 2019
Apr 18 2019
Apr 17 2019
It would be better to rename clang/test/SemaSYCL/device-attrubutes.cpp to clang/test/SemaSYCL/device-attributes.cpp
Apr 15 2019
Apr 9 2019
While we are thinking about recycling some attributes across languages, we have to think about the fact that real applications are often made from various languages, such as SYCL + OpenMP 5 or whatever.
It would be nice not to forbid such a combination inside the same TU by design.
Mar 23 2019
Mar 20 2019
I was a little bit worried about
Feb 15 2019
LGTM.
Feb 5 2019
That looks good. Thanks.
Nov 2 2018
Nov 1 2018
Oct 30 2018
We could submit to the standard an OpenCL C++ extension to accept the OpenCL C syntax...
Nov 19 2016
+1
Please do not remove anything, since it may be useful in some contexts.