[M68k] Implement Disassembler

[ricky26]

Summary

This is a work-in-progress implementation of a disassembler for M68k. There are not yet any
new tests for the disassembler. I've left them until there's a general consensus that the structure
of this change is acceptable.

Questions I'm aware of:

• Should this use Motorola or gas syntax? (At the moment it uses Motorola syntax.)
• The disassembler produces a table at runtime for disassembly generated from the code beads. Is this okay? (This is less than ideal but as I mentioned in my llvm-dev post, it's quite complicated to write a table-gen parser for code beads.)

[ricky26]

I've marked this 'Ready for Review' since otherwise notifications don't happen. To be clear though, this is not ready to merge.

[ricky26]

Rebased, fixed some bugs & added some tests.

[RKSimon]

Minor fly-by coding style comment

llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp

63

(style) Don't re-evaluate a fixed array length.

for (unsigned I = 0, E = Buffer.size(); I != E; ++I) {`

Alternatively, AFAICT you might be able to use a for-range loop:

for (const auto &BufferValue : Buffer)

[ricky26]

Improve code style, add encoding tests to instructions.s.

[ricky26]

I think this is now ready for review proper.

I've done a pass tidying up the code style and I've added some encoding checks to the MC test added in the assembler.

llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp

63

I did go through all of the loops and I only found one case where I wasn't doing something funny with the iterator (clamping the length for arrays, stepping by 2, for ex.). If I've missed any please, shout!

[ricky26]

Add loop changes missed from previous diff.

[myhsu]

First of all, good job :-)
Though I only scanned over the patch, I'm a little concerned about the adoption of code beads here because ideally, we are going to remove code beads from LLVM in the future. As stated in one of my comments, can we get any help from the disassembler table generated by TableGen?

Also can you split any changes regarding assembly syntax into a separate patch?

llvm/lib/Target/M68k/CMakeLists.txt

14

Do we use this table anywhere? If not, is there any reason we can't use it?

llvm/lib/Target/M68k/Disassembler/CMakeLists.txt

5

Since you use getTheM68kTarget here, please explicitly link M68kInfo. I bumped into a related problem in M68kAsmParser where the linker is unable to find getTheM68kTarget symbol if you build LLVM libraries as shared objects.

llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp

310

Is there any specific reason to use a single-case switch rather than if-statement here?

381

Can we use explicit type here

402

ditto

llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.cpp

196 ↗

(On Diff #337434)

Can we put these changes into a separate patch (possibility combined with your changes on tests below)?
If the changes here affect the disassembler test, then maybe you can put it (the separate patch) as the dependency for the current disassembler patch.

llvm/test/MC/M68k/instructions.s

11 ↗

(On Diff #337434)

Test directives related to instruction encoding is irrelevant to disassembler. Please remove them from this patch.

36 ↗

(On Diff #337434)

Can we put changes on tests into a separate patch?

[ricky26]

Apply review feedback.

[ricky26]

Shorten switch to a single assert.

[ricky26]

In D98540#2690082, @myhsu wrote:

First of all, good job :-)
Though I only scanned over the patch, I'm a little concerned about the adoption of code beads here because ideally, we are going to remove code beads from LLVM in the future.

I agree but this is the path of least resistance and I don't think it's too much 'wasted work'. I'm hoping when the encoding mechanism is changed, it will be staged (introduce new encoding in table-gen, start moving components over in later patches). In which case I don't think the disassembler will get in the way. The benefit being that with this quite shallow approach (using the beads to build bitmasks) we get the extra functioning surface area of the disassembler in the mean time (and at least some of the disassembler won't need to be changed with the encoding rework).

If you think it's better to try and solve the encoding setup first, I have no qualms. I'm pretty interested in helping with the encoding rework too if I can. :)

As stated in one of my comments, can we get any help from the disassembler table generated by TableGen?

I forgot I included this. I had a look when I initially started poking around the disassembler but it looks like it is generated for instructions with the Inst field set.

There are some overrides (X86 being notable) and I considered writing an M68k extension but there're a fair few pieces of information that aren't available in table-gen which we need to parse the beads and produce a disassembly table. I figured that we would migrate over to using that (probably still with a bit of a custom extension) once we reworked the encoding.

[ricky26]

Fix up the other switch statement that I somehow missed.

[myhsu]

In D98540#2696459, @ricky26 wrote:

In D98540#2690082, @myhsu wrote:

First of all, good job :-)
Though I only scanned over the patch, I'm a little concerned about the adoption of code beads here because ideally, we are going to remove code beads from LLVM in the future.

I agree but this is the path of least resistance and I don't think it's too much 'wasted work'. I'm hoping when the encoding mechanism is changed, it will be staged (introduce new encoding in table-gen, start moving components over in later patches). In which case I don't think the disassembler will get in the way. The benefit being that with this quite shallow approach (using the beads to build bitmasks) we get the extra functioning surface area of the disassembler in the mean time (and at least some of the disassembler won't need to be changed with the encoding rework).

If you think it's better to try and solve the encoding setup first, I have no qualms. I'm pretty interested in helping with the encoding rework too if I can. :)

Nah, let's sort out the disassembler first.

As stated in one of my comments, can we get any help from the disassembler table generated by TableGen?

I forgot I included this. I had a look when I initially started poking around the disassembler but it looks like it is generated for instructions with the Inst field set.

There are some overrides (X86 being notable) and I considered writing an M68k extension but there're a fair few pieces of information that aren't available in table-gen which we need to parse the beads and produce a disassembly table. I figured that we would migrate over to using that (probably still with a bit of a custom extension) once we reworked the encoding.

You're right, it's probably better to consider this option after the encoding rework

[myhsu]

conditionally LGTM.
Please fix the formatting issues before committing it. I think all of them are related to this coding style rule.

llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp

210

remove curly braces since there is only one statement in the body

219

ditto

239

remove curly braces since there is only one statement in the body

255

ditto

336

remove curly braces since there is only one statement in the body

340

ditto

389

remove curly braces since there is only one statement in the body

410

remove curly braces since there is only one statement in the body

424

remove curly braces since there is only one statement in the body

432

ditto

472

remove curly braces since there is only one statement in the body

480

ditto

493

ditto

570

remove curly braces since there is only one statement in the body

[ricky26]

Fixed up code style.

[ricky26]

Fixup one missed instance of the "don't use braces" rule.

[RKSimon]

llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp

448

@ricky26 coverity is warning that the NumToRead = 32 case results in UB when shifting Scratch.

Could this be:

Scratch = NumRead >= 32 ? 0 : (Scratch << NumToRead);
Scratch |= Reader.readBits(NumToRead);

[ricky26]

llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp

448

Thanks, I always forget that shifting the full width is UB. (Is coverity something I should be watching for my changes?)

Does LLVM support host compilers with non-32-bit ints? If so, the logic will need to be more complicated.

Something like Scratch = (NumRead < (sizeof(unsigned) * 8)) ? (Scratch << NumToRead) : 0;?

If this isn't high priority I'll try and land a patch for it sometime over the coming week.

Thanks!

[RKSimon]

llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp

448

I don't think LLVM would survive building on non-32-bit int target......

Its not high priority, but I do try to keep an eye on static analysis reports as they do sometimes raise interesting issues. Potential out of range shift amount warnings are quite common in the llvm codebase.

You can request access to the coverity reports via: https://scan.coverity.com/projects/llvm

llvm/lib/Target/M68k/CMakeLists.txt

 add_llvm_component_group(M68k)
 
 set(LLVM_TARGET_DEFINITIONS M68k.td)
 
 tablegen(LLVM M68kGenRegisterInfo.inc     -gen-register-info)
 tablegen(LLVM M68kGenInstrInfo.inc        -gen-instr-info)
 tablegen(LLVM M68kGenSubtargetInfo.inc    -gen-subtarget)
 tablegen(LLVM M68kGenMCCodeBeads.inc      -gen-code-beads)
 tablegen(LLVM M68kGenMCPseudoLowering.inc -gen-pseudo-lowering)
 tablegen(LLVM M68kGenDAGISel.inc          -gen-dag-isel)
 tablegen(LLVM M68kGenCallingConv.inc      -gen-callingconv)
 tablegen(LLVM M68kGenAsmWriter.inc        -gen-asm-writer)
 tablegen(LLVM M68kGenAsmMatcher.inc       -gen-asm-matcher)
 
 add_public_tablegen_target(M68kCommonTableGen)
 
 add_llvm_target(M68kCodeGen
   M68kAsmPrinter.cpp
   M68kCollapseMOVEMPass.cpp
   M68kExpandPseudo.cpp
   M68kFrameLowering.cpp
   M68kInstrInfo.cpp
add_llvm_target(M68kCodeGen
 
   ADD_TO_COMPONENT
   M68k
 )
 
 add_subdirectory(TargetInfo)
 add_subdirectory(MCTargetDesc)
 add_subdirectory(AsmParser)
+add_subdirectory(Disassembler)

llvm/lib/Target/M68k/Disassembler/CMakeLists.txt

+add_llvm_component_library(LLVMM68kDisassembler
+        M68kDisassembler.cpp
+
+  LINK_COMPONENTS
+  M68kInfo
+  MCDisassembler
+  Support
+
+  ADD_TO_COMPONENT
+  M68k
+)
+

llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp

+//===- M68kDisassembler.cpp - Disassembler for M68k -------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is part of the M68k Disassembler.
+//
+//===----------------------------------------------------------------------===//
+
+#include "M68k.h"
+#include "M68kRegisterInfo.h"
+#include "M68kSubtarget.h"
+#include "MCTargetDesc/M68kMCCodeEmitter.h"
+#include "MCTargetDesc/M68kMCTargetDesc.h"
+#include "TargetInfo/M68kTargetInfo.h"
+
+#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCDisassembler/MCDisassembler.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/Support/TargetRegistry.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "m68k-disassembler"
+
+typedef MCDisassembler::DecodeStatus DecodeStatus;
+
+namespace {
+constexpr unsigned MaxInstructionWords = 11;
+
+class M68kInstructionBuffer {
+  typedef SmallVector<uint16_t, MaxInstructionWords> BufferType;
+  BufferType Buffer;
+
+public:
+  M68kInstructionBuffer() {}
+
+  template <typename TIt>
+  M68kInstructionBuffer(TIt Start, TIt End) : Buffer(Start, End) {}
+
+  unsigned size() const { return Buffer.size(); }
+
+  BufferType::const_iterator begin() const { return Buffer.begin(); }
+  BufferType::const_iterator end() const { return Buffer.end(); }
+
+  uint16_t operator[](unsigned Index) const {
+    assert((Index < Buffer.size()) && "tried to read out of bounds word");
+    return Buffer[Index];
+  }
+
+  void truncate(unsigned NewLength) {
+    assert((NewLength <= Buffer.size()) &&
+           "instruction buffer too short to truncate");
+    Buffer.resize(NewLength);
+  }
+
+  void dump() const;
+
+  static M68kInstructionBuffer fill(ArrayRef<uint8_t> Bytes);
+};
+
+class M68kInstructionReader {
+  M68kInstructionBuffer Buffer;
+  unsigned NumRead;
+
+public:
+  M68kInstructionReader(M68kInstructionBuffer Buf) : Buffer(Buf), NumRead(0) {}
+
+  unsigned size() const { return (Buffer.size() * 16) - NumRead; }
+
+  uint64_t readBits(unsigned NumBits);
+};
+
+struct M68kInstructionLookup {
+  unsigned OpCode;
+  M68kInstructionBuffer Mask;
+  M68kInstructionBuffer Value;
+
+  unsigned size() const { return Mask.size(); }
+
+  // Check whether this instruction could possibly match the given bytes.
+  bool matches(const M68kInstructionBuffer &Test) const;
+  void dump() const;
+};
+
+class M68kInstructionLookupBuilder {
+  std::array<uint16_t, MaxInstructionWords> Mask;
+  std::array<uint16_t, MaxInstructionWords> Value;
+  unsigned NumWritten;
+
+public:
+  M68kInstructionLookupBuilder() : NumWritten(0) {
+    Mask.fill(0);
+    Value.fill(0);
+  }
+
+  unsigned numWords() const {
+    assert(!(NumWritten & 0xf) && "instructions must be whole words");
+    return NumWritten >> 4;
+  }
+
+  bool isValid() const;
+  M68kInstructionLookup build(unsigned OpCode);
+  void addBits(unsigned N, uint64_t Bits);
+  void skipBits(unsigned N);
+};
+
+/// A disassembler class for M68k.
+class M68kDisassembler : public MCDisassembler {
+  MCInstrInfo *MCII;
+  std::vector<M68kInstructionLookup> Lookups;
+
+public:
+  M68kDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
+                   MCInstrInfo *MCII)
+      : MCDisassembler(STI, Ctx), MCII(MCII) {
+    buildBeadTable();
+  }
+  virtual ~M68kDisassembler() {}
+
+  void buildBeadTable();
+  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
+                              ArrayRef<uint8_t> Bytes, uint64_t Address,
+                              raw_ostream &CStream) const override;
+  void decodeReg(MCInst &Instr, unsigned int Bead,
+                 M68kInstructionReader &Reader, unsigned &Scratch) const;
+  void decodeImm(MCInst &Instr, unsigned int Bead,
+                 M68kInstructionReader &Reader, unsigned &Scratch) const;
+  unsigned int getRegOperandIndex(MCInst &Instr, unsigned int Bead) const;
+  unsigned int getImmOperandIndex(MCInst &Instr, unsigned int Bead) const;
+};
+} // namespace
+
+static unsigned RegisterDecode[] = {
+    M68k::A0, M68k::A1, M68k::A2, M68k::A3, M68k::A4, M68k::A5,
+    M68k::A6, M68k::SP, M68k::D0, M68k::D1, M68k::D2, M68k::D3,
+    M68k::D4, M68k::D5, M68k::D6, M68k::D7,
+};
+
+void M68kInstructionBuffer::dump() const {
+  for (auto Word : Buffer) {
+    for (unsigned B = 0; B < 16; ++B) {
+      uint16_t Bit = (1 << (16 - B - 1));
+      unsigned IsClear = !(Word & Bit);
+
+      if (B == 8)
+        dbgs() << " ";
+
+      char Ch = IsClear ? '0' : '1';
+      dbgs() << Ch;
+    }
+
+    dbgs() << " ";
+  }
+
+  dbgs() << "\n";
+}
+
+M68kInstructionBuffer M68kInstructionBuffer::fill(ArrayRef<uint8_t> Bytes) {
+  SmallVector<uint16_t, MaxInstructionWords> Buffer;
+  Buffer.resize(std::min(Bytes.size() / 2, Buffer.max_size()));
+
+  for (unsigned I = 0, E = Buffer.size(); I < E; ++I) {
+    unsigned Offset = I * 2;
+    uint64_t Hi = Bytes[Offset];
+    uint64_t Lo = Bytes[Offset + 1];
+    uint64_t Word = (Hi << 8) | Lo;
+    Buffer[I] = Word;
+
+    LLVM_DEBUG(
+        errs() << format("Read word %x (%d)\n", (unsigned)Word, Buffer.size()));
+  }
+
+  return M68kInstructionBuffer(Buffer.begin(), Buffer.end());
+}
+
+uint64_t M68kInstructionReader::readBits(unsigned NumBits) {
+  assert((size() >= NumBits) && "not enough bits to read");
+
+  // We have to read the bits in 16-bit chunks because we read them as
+  // 16-bit words but they're actually written in big-endian. If a read
+  // crosses a word boundary we have to be careful.
+
+  uint64_t Value = 0;
+  unsigned BitsRead = 0;
+
+  while (BitsRead < NumBits) {
+    unsigned AvailableThisWord = 16 - (NumRead & 0xf);
+    unsigned ToRead = std::min(NumBits, AvailableThisWord);
+
+    unsigned WordIndex = NumRead >> 4;
+    uint64_t ThisWord = Buffer[WordIndex] >> (NumRead & 0xf);
+    uint64_t Mask = (1 << ToRead) - 1;
+    Value |= (ThisWord & Mask) << BitsRead;
+    NumRead += ToRead;
+    BitsRead += ToRead;
+  }
+  return Value;
+}
+
+bool M68kInstructionLookup::matches(const M68kInstructionBuffer &Test) const {
+  if (Test.size() < Value.size())
+    return false;
+
+  for (unsigned I = 0, E = Value.size(); I < E; ++I) {
+    uint16_t Have = Test[I];
+    uint16_t Need = Value[I];
+    uint16_t WordMask = Mask[I];
+
+    if ((Have & WordMask) != Need)
+      return false;
+  }
+
+  return true;
+}
+
+void M68kInstructionLookup::dump() const {
+  dbgs() << "M68kInstructionLookup " << OpCode << " ";
+
+  for (unsigned I = 0, E = Mask.size(); I < E; ++I) {
+    uint16_t WordMask = Mask[I];
+    uint16_t WordValue = Value[I];
+
+    for (unsigned B = 0; B < 16; ++B) {
+      uint16_t Bit = (1 << (15 - B));
+      unsigned IsMasked = !(WordMask & Bit);
+      unsigned IsClear = !(WordValue & Bit);
+
+      if (B == 8)
+        dbgs() << " ";
+
+      char Ch = IsMasked ? '?' : (IsClear ? '0' : '1');
+      dbgs() << Ch;
+    }
+
+    dbgs() << " ";
+  }
+
+  dbgs() << "\n";
+}
+
+bool M68kInstructionLookupBuilder::isValid() const {
+  for (unsigned I = 0, E = numWords(); I < E; ++I)
+    if (Mask[I])
+      return true;
+
+  return false;
+}
+
+M68kInstructionLookup M68kInstructionLookupBuilder::build(unsigned OpCode) {
+  unsigned NumWords = numWords();
+  M68kInstructionBuffer MaskBuffer(Mask.begin(), Mask.begin() + NumWords);
+  M68kInstructionBuffer ValueBuffer(Value.begin(), Value.begin() + NumWords);
+  M68kInstructionLookup Ret;
+  Ret.OpCode = OpCode;
+  Ret.Mask = MaskBuffer;
+  Ret.Value = ValueBuffer;
+  return Ret;
+}
+
+void M68kInstructionLookupBuilder::addBits(unsigned N, uint64_t Bits) {
+  while (N > 0) {
+    unsigned WordIndex = NumWritten >> 4;
+    unsigned WordOffset = NumWritten & 0xf;
+    unsigned AvailableThisWord = 16 - WordOffset;
+    unsigned ToWrite = std::min(AvailableThisWord, N);
+
+    uint16_t WordMask = (1 << ToWrite) - 1;
+    uint16_t BitsToWrite = Bits & WordMask;
+
+    Value[WordIndex] |= (BitsToWrite << WordOffset);
+    Mask[WordIndex] |= (WordMask << WordOffset);
+
+    Bits >>= ToWrite;
+    N -= ToWrite;
+    NumWritten += ToWrite;
+  }
+}
+
+void M68kInstructionLookupBuilder::skipBits(unsigned N) { NumWritten += N; }
+
+// This is a bit of a hack: we can't generate this table at table-gen time
+// because some of the definitions are in our platform.
+void M68kDisassembler::buildBeadTable() {
+  const unsigned NumInstr = M68k::INSTRUCTION_LIST_END;
+  Lookups.reserve(NumInstr);
+
+  for (unsigned I = 0; I < NumInstr; ++I) {
+    M68kInstructionLookupBuilder Builder;
+
+    for (const uint8_t *PartPtr = M68k::getMCInstrBeads(I); *PartPtr;
+         ++PartPtr) {
+      uint8_t Bead = *PartPtr;
+      unsigned Ext = Bead >> 4;
+      unsigned Op = Bead & 0xf;
+
+      switch (Op) {
+      case M68kBeads::Ctrl:
+        // Term will have already been skipped by the loop.
+        assert((Ext == M68kBeads::Ignore) && "unexpected command bead");
+        break;
+
+      case M68kBeads::Bits1:
+        Builder.addBits(1, Ext);
+        break;
+
+      case M68kBeads::Bits2:
+        Builder.addBits(2, Ext);
+        break;
+
+      case M68kBeads::Bits3:
+        Builder.addBits(3, Ext);
+        break;
+
+      case M68kBeads::Bits4:
+        Builder.addBits(4, Ext);
+        break;
+
+      case M68kBeads::DAReg:
+      case M68kBeads::DA:
+      case M68kBeads::DReg:
+      case M68kBeads::Reg:
+        if (Op != M68kBeads::DA)
+          Builder.skipBits(3);
+
+        if (Op != M68kBeads::Reg && Op != M68kBeads::DReg)
+          Builder.skipBits(1);
+
+        break;
+
+      case M68kBeads::Disp8:
+        Builder.skipBits(8);
+        break;
+
+      case M68kBeads::Imm8:
+      case M68kBeads::Imm16:
+        Builder.skipBits(16);
+        break;
+
+      case M68kBeads::Imm32:
+        Builder.skipBits(32);
+        break;
+
+      case M68kBeads::Imm3:
+        Builder.skipBits(3);
+        break;
+
+      default:
+        llvm_unreachable("unhandled bead type");
+      }
+    }
+
+    // Ignore instructions which are unmatchable (usually pseudo instructions).
+    if (!Builder.isValid())
+      continue;
+
+    Lookups.push_back(Builder.build(I));
+  }
+}
+
+unsigned M68kDisassembler::getRegOperandIndex(MCInst &Instr,
+                                              unsigned Bead) const {
+  unsigned Ext = Bead >> 4;
+
+  const MCInstrDesc &Desc = MCII->get(Instr.getOpcode());
+  auto MIOpIdx = M68k::getLogicalOperandIdx(Instr.getOpcode(), Ext & 7);
+
+  if (M68kII::hasMultiMIOperands(Instr.getOpcode(), Ext & 7)) {
+    bool IsPCRel = Desc.OpInfo[MIOpIdx].OperandType == MCOI::OPERAND_PCREL;
+    if (IsPCRel)
+      MIOpIdx += M68k::PCRelIndex;
+    else if (Ext & 8)
+      MIOpIdx += M68k::MemIndex;
+    else
+      MIOpIdx += M68k::MemBase;
+  }
+
+  return MIOpIdx;
+}
+
+unsigned M68kDisassembler::getImmOperandIndex(MCInst &Instr,
+                                              unsigned Bead) const {
+  unsigned Ext = Bead >> 4;
+
+  const MCInstrDesc &Desc = MCII->get(Instr.getOpcode());
+  auto MIOpIdx = M68k::getLogicalOperandIdx(Instr.getOpcode(), Ext & 7);
+
+  if (M68kII::hasMultiMIOperands(Instr.getOpcode(), Ext & 7)) {
+    bool IsPCRel = Desc.OpInfo[MIOpIdx].OperandType == MCOI::OPERAND_PCREL;
+    if (IsPCRel)
+      MIOpIdx += M68k::PCRelDisp;
+    else if (Ext & 8)
+      MIOpIdx += M68k::MemOuter;
+    else
+      MIOpIdx += M68k::MemDisp;
+  }
+
+  return MIOpIdx;
+}
+
+void M68kDisassembler::decodeReg(MCInst &Instr, unsigned Bead,
+                                 M68kInstructionReader &Reader,
+                                 unsigned &Scratch) const {
+  unsigned Op = Bead & 0xf;
+  LLVM_DEBUG(errs() << format("decodeReg %x\n", Bead));
+
+  if (Op != M68kBeads::DA)
+    Scratch = (Scratch & ~7) | Reader.readBits(3);
+
+  if (Op != M68kBeads::Reg) {
+    bool DA = (Op != M68kBeads::DReg) && Reader.readBits(1);
+    if (!DA)
+      Scratch |= 8;
+    else
+      Scratch &= ~8;
+  }
+}
+
+void M68kDisassembler::decodeImm(MCInst &Instr, unsigned Bead,
+                                 M68kInstructionReader &Reader,
+                                 unsigned &Scratch) const {
+  unsigned Op = Bead & 0xf;
+  LLVM_DEBUG(errs() << format("decodeImm %x\n", Bead));
+
+  unsigned NumToRead;
+  switch (Op) {
+  case M68kBeads::Disp8:
+    NumToRead = 8;
+    break;
+  case M68kBeads::Imm8:
+  case M68kBeads::Imm16:
+    NumToRead = 16;
+    break;
+  case M68kBeads::Imm32:
+    NumToRead = 32;
+    break;
+  case M68kBeads::Imm3:
+    NumToRead = 3;
+    break;
+  default:
+    llvm_unreachable("invalid imm");
+  }
+
+  Scratch = (Scratch << NumToRead) | Reader.readBits(NumToRead);
+}
+
+DecodeStatus M68kDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
+                                              ArrayRef<uint8_t> Bytes,
+                                              uint64_t Address,
+                                              raw_ostream &CStream) const {
+  // Read and shift the input (fetch as much as we can for now).
+  auto Buffer = M68kInstructionBuffer::fill(Bytes);
+  if (Buffer.size() == 0)
+    return Fail;
+
+  // Check through our lookup table.
+  bool Found = false;
+  for (unsigned I = 0, E = Lookups.size(); I < E; ++I) {
+    const M68kInstructionLookup &Lookup = Lookups[I];
+    if (!Lookup.matches(Buffer))
+      continue;
+
+    Found = true;
+    Size = Lookup.size() * 2;
+    Buffer.truncate(Lookup.size());
+    Instr.setOpcode(Lookup.OpCode);
+    LLVM_DEBUG(errs() << "decoding instruction " << MCII->getName(Lookup.OpCode)
+                      << "\n");
+    break;
+  }
+
+  if (!Found)
+    return Fail;
+
+  M68kInstructionReader Reader(Buffer);
+  const MCInstrDesc &Desc = MCII->get(Instr.getOpcode());
+  unsigned NumOperands = Desc.NumOperands;
+
+  // Now use the beads to decode the operands.
+  enum class OperandType {
+    Invalid,
+    Reg,
+    Imm,
+  };
+
+  SmallVector<OperandType, 6> OpType(NumOperands, OperandType::Invalid);
+  SmallVector<unsigned, 6> Scratch(NumOperands, 0);
+  for (const uint8_t *PartPtr = M68k::getMCInstrBeads(Instr.getOpcode());
+       *PartPtr; ++PartPtr) {
+    uint8_t Bead = *PartPtr;
+    unsigned Ext = Bead >> 4;
+    unsigned Op = Bead & 0xf;
+    unsigned MIOpIdx;
+
+    switch (Op) {
+    case M68kBeads::Ctrl:
+      // Term will have already been skipped by the loop.
+      assert((Ext == M68kBeads::Ignore) && "unexpected command bead");
+      break;
+
+      // These bits are constant - if we're here we've already matched them.
+    case M68kBeads::Bits1:
+      Reader.readBits(1);
+      break;
+    case M68kBeads::Bits2:
+      Reader.readBits(2);
+      break;
+    case M68kBeads::Bits3:
+      Reader.readBits(3);
+      break;
+    case M68kBeads::Bits4:
+      Reader.readBits(4);
+      break;
+
+    case M68kBeads::DAReg:
+    case M68kBeads::DA:
+    case M68kBeads::DReg:
+    case M68kBeads::Reg:
+      MIOpIdx = getRegOperandIndex(Instr, Bead);
+      assert(((OpType[MIOpIdx] == OperandType::Invalid) ||
+              (OpType[MIOpIdx] == OperandType::Reg)) &&
+             "operands cannot change type");
+      OpType[MIOpIdx] = OperandType::Reg;
+      decodeReg(Instr, Bead, Reader, Scratch[MIOpIdx]);
+      break;
+
+    case M68kBeads::Disp8:
+    case M68kBeads::Imm8:
+    case M68kBeads::Imm16:
+    case M68kBeads::Imm32:
+    case M68kBeads::Imm3:
+      MIOpIdx = getImmOperandIndex(Instr, Bead);
+      assert(((OpType[MIOpIdx] == OperandType::Invalid) ||
+              (OpType[MIOpIdx] == OperandType::Imm)) &&
+             "operands cannot change type");
+      OpType[MIOpIdx] = OperandType::Imm;
+      decodeImm(Instr, Bead, Reader, Scratch[MIOpIdx]);
+      break;
+
+    default:
+      llvm_unreachable("unhandled bead type");
+    }
+  }
+
+  // Copy constrained operands.
+  for (unsigned DstMIOpIdx = 0; DstMIOpIdx < NumOperands; ++DstMIOpIdx) {
+    int TiedTo = Desc.getOperandConstraint(DstMIOpIdx, MCOI::TIED_TO);
+    if (TiedTo < 0)
+      continue;
+
+    unsigned SrcMIOpIdx = TiedTo;
+
+    unsigned OpCount = 0;
+    for (unsigned I = 0;; ++I) {
+      unsigned Offset = M68k::getLogicalOperandIdx(Instr.getOpcode(), I);
+      assert(Offset <= SrcMIOpIdx && "missing logical operand");
+      if (Offset == SrcMIOpIdx) {
+        OpCount = M68k::getLogicalOperandSize(Instr.getOpcode(), I);
+        break;
+      }
+    }
+    assert(OpCount != 0 && "operand count not found");
+
+    for (unsigned I = 0; I < OpCount; ++I) {
+      assert(OpType[DstMIOpIdx + I] == OperandType::Invalid &&
+             "tried to stomp over operand whilst applying constraints");
+      OpType[DstMIOpIdx + I] = OpType[SrcMIOpIdx + I];
+      Scratch[DstMIOpIdx + I] = Scratch[SrcMIOpIdx + I];
+    }
+  }
+
+  // Create the operands from our scratch space.
+  for (unsigned O = 0; O < NumOperands; ++O) {
+    switch (OpType[O]) {
+    case OperandType::Invalid:
+      assert(false && "operand not parsed");
+
+    case OperandType::Imm:
+      Instr.addOperand(MCOperand::createImm(Scratch[O]));
+      break;
+
+    case OperandType::Reg:
+      Instr.addOperand(MCOperand::createReg(RegisterDecode[Scratch[O]]));
+      break;
+    }
+  }
+
+  assert((Reader.size() == 0) && "wrong number of bits consumed");
+  return Success;
+}
+
+static MCDisassembler *createM68kDisassembler(const Target &T,
+                                              const MCSubtargetInfo &STI,
+                                              MCContext &Ctx) {
+  return new M68kDisassembler(STI, Ctx, T.createMCInstrInfo());
+}
+
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kDisassembler() {
+  // Register the disassembler.
+  TargetRegistry::RegisterMCDisassembler(getTheM68kTarget(),
+                                         createM68kDisassembler);
+}

llvm/test/MC/Disassembler/M68k/instructions.txt

+# RUN: llvm-mc -disassemble -triple m68k %s | FileCheck %s
+
+# CHECK: move.l %a1, %a0
+0x20 0x49
+# CHECK: add.l %a0, %a1
+0xd3 0xc8
+# CHECK: sub.w %d3, %d1
+0x92 0x43
+# CHECK: cmp.w %d1, %d0
+0xb0 0x41
+# CHECK: neg.w %d0
+0x44 0x40
+# CHECK: btst #0, %d3
+0x08 0x03 0x00 0x00
+# CHECK: bra $0
+0x60 0x00 0x00 0x00
+# CHECK: jsr $0
+0x4e 0xb9 0x00 0x00 0x00 0x00
+# CHECK: seq %d0
+0x57 0xc0
+# CHECK: sgt %d0
+0x5e 0xc0
+# CHECK: lea (50,%a0), %a1
+0x43 0xe8 0x00 0x32
+# CHECK: lsl.l #5, %d1
+0xeb 0x89
+# CHECK: lsr.l #5, %d1
+0xea 0x89
+# CHECK: asr.l #5, %d1
+0xea 0x81
+# CHECK: rol.l #5, %d1
+0xeb 0x99
+# CHECK: ror.l #5, %d1
+0xea 0x99
+# CHECK: nop
+0x4e 0x71
+# CHECK: rts
+0x4e 0x75

llvm/test/MC/Disassembler/M68k/lit.local.cfg

+if not 'M68k' in config.root.targets:
+    config.unsupported = True