[M68k] Convert register Aliases to AltNames

[ricky26]

Summary

This makes it simpler to determine when two registers are actually the same vs aliasing.

The only real caveat is that there is no longer any record of which 'logical' register it is.
(i.e. parsing assembly and then printing it can result in the register name changing.)

[myhsu]

Are you trying to distinguish the sub-register use cases from alternative naming (e.g. a5 & bp)?

[myhsu]

llvm/lib/Target/M68k/M68kRegisterInfo.td

18–19

the second template argument for Register can be used to assign AltNames

[ricky26]

In D98536#2627583, @myhsu wrote:

Are you trying to distinguish the sub-register use cases from alternative naming (e.g. a5 & bp)?

Kind of. I was running into a number of cases where I had to handle A7/SP separately (for example). I was worried this was eventually going to lead to significant code duplication and/or errors. AltNames seemed to make the most sense. SP/etc are really only used to make assembly more readable. (For that reason, I actually made SP the default rendering of A7.)

[ricky26]

Use Register second parameter instead of an extra 'let'

[myhsu]

In D98536#2630147, @ricky26 wrote:

In D98536#2627583, @myhsu wrote:

Are you trying to distinguish the sub-register use cases from alternative naming (e.g. a5 & bp)?

Kind of. I was running into a number of cases where I had to handle A7/SP separately (for example). I was worried this was eventually going to lead to significant code duplication and/or errors. AltNames seemed to make the most sense. SP/etc are really only used to make assembly more readable. (For that reason, I actually made SP the default rendering of A7.)

That make sense. I only have few syntax comments inlined below.

llvm/lib/Target/M68k/M68kRegisterInfo.td

95

Is there any reason to expand these registers rather than using the original syntax (i.e. using sequence)?

127

ditto the same question above

[ricky26]

Change explicit register lists back into sequences where possible.

[ricky26]

Yep, converted those back into sequences. Thanks.

[myhsu]

LGTM

llvm/lib/Target/M68k/M68kRegisterInfo.td

 /// This file describes the M68k Register file, defining the registers
 /// aliases between the registers, and the register classes built out of the
 /// registers.
 ///
 //===----------------------------------------------------------------------===//
 
 class MxReg<string N, bits<16> ENC,
             list<Register> SUBREGS = [], list<SubRegIndex> SUBIDX,
-            list<int> DWREGS = []>
-    : Register<N>, DwarfRegNum<DWREGS> {
+            list<int> DWREGS = [], list<string> ALTNAMES = []>
+    : Register<N, ALTNAMES>, DwarfRegNum<DWREGS> {
   let Namespace     = "M68k";
   let HWEncoding    = ENC;
   let SubRegs       = SUBREGS;
   let SubRegIndices = SUBIDX;
 }
 
 // Subregister indices.
 let Namespace = "M68k" in {
   def MxSubRegIndex8Lo  : SubRegIndex<8, 0>;
   def MxSubRegIndex16Lo : SubRegIndex<16, 0>;
 }
 
-// Generate Data registers and theirs smaller variants
-foreach Index = 0-7 in {
-  def "BD"#Index : MxReg<"d"#Index, Index, [], [], [Index]>;
-
-  def "WD"#Index
-    : MxReg<"d"#Index, Index,
-            [!cast<Register>("BD"#Index)], [MxSubRegIndex8Lo],
-            [Index]>;
-
-  def "D"#Index
-    : MxReg<"d"#Index, Index,
-            [!cast<Register>("WD"#Index)], [MxSubRegIndex16Lo],
-            [Index]>;
-
-} // foreach
-
-// Generate Address registers and theirs smaller variants
-foreach Index = 0-7 in {
-  def "WA"#Index
-     : MxReg<"a"#Index, Index, [], [], [!add(8,Index)]>;
-
-  def "A"#Index
-     : MxReg<"a"#Index, Index,
-             [!cast<Register>("WA"#Index)], [MxSubRegIndex16Lo],
-             [!add(8,Index)]>;
-}
-
-// Alias Registers
-class MxAliasReg<string N, MxReg REG>
-    : MxReg<N, REG.HWEncoding, [], [], REG.DwarfNumbers> {
-  let Aliases = [REG];
-}
-
-def BP  : MxAliasReg<"bp",  A5>;
-def FP  : MxAliasReg<"fp",  A6>;
-def SP : MxAliasReg<"sp", A7>;
-
-def USP : MxAliasReg<"usp", A7>;
-def SSP : MxAliasReg<"ssp", A7>;
-def ISP : MxAliasReg<"isp", A7>;
+multiclass MxDataRegister<int INDEX, string REG_NAME, list<string> ALTNAMES = []> {
+  def "B"#NAME : MxReg<REG_NAME, INDEX, [], [], [INDEX], ALTNAMES>;
+  def "W"#NAME
+    : MxReg<REG_NAME, INDEX,
+            [!cast<Register>("B"#NAME)], [MxSubRegIndex8Lo],
+            [INDEX], ALTNAMES>;
+  def NAME
+    : MxReg<REG_NAME, INDEX,
+            [!cast<Register>("W"#NAME)], [MxSubRegIndex16Lo],
+            [INDEX], ALTNAMES>;
+}
+
+multiclass MxAddressRegister<int INDEX, string REG_NAME, list<string> ALTNAMES = []> {
+  def "W"#NAME
+    : MxReg<REG_NAME, INDEX, [], [], [!add(8,INDEX)], ALTNAMES>;
+  def NAME
+    : MxReg<REG_NAME, INDEX,
+            [!cast<Register>("W"#NAME)], [MxSubRegIndex16Lo],
+            [!add(8,INDEX)], ALTNAMES>;
+}
+
+defm D0 : MxDataRegister<0, "d0">;
+defm D1 : MxDataRegister<1, "d1">;
+defm D2 : MxDataRegister<2, "d2">;
+defm D3 : MxDataRegister<3, "d3">;
+defm D4 : MxDataRegister<4, "d4">;
+defm D5 : MxDataRegister<5, "d5">;
+defm D6 : MxDataRegister<6, "d6">;
+defm D7 : MxDataRegister<7, "d7">;
+
+defm A0 : MxAddressRegister<0, "a0">;
+defm A1 : MxAddressRegister<1, "a1">;
+defm A2 : MxAddressRegister<2, "a2">;
+defm A3 : MxAddressRegister<3, "a3">;
+defm A4 : MxAddressRegister<4, "a4">;
+defm A5 : MxAddressRegister<5, "a5", ["bp"]>;
+defm A6 : MxAddressRegister<6, "a6", ["fp"]>;
+defm SP : MxAddressRegister<7, "sp", ["usp", "ssp", "isp", "a7"]>;
+
 
 // Pseudo Registers
 class MxPseudoReg<string N, list<Register> SUBREGS = [], list<SubRegIndex> SUBIDX = []>
     : MxReg<N, 0, SUBREGS, SUBIDX>;
 
 def CCR : MxPseudoReg<"ccr">;
 def SR  : MxPseudoReg<"sr">;
 
 def PC  : MxPseudoReg<"pc">;
 
 //===----------------------------------------------------------------------===//
 // Register Classes
 //===----------------------------------------------------------------------===//
 
 class MxRegClass<list<ValueType> regTypes, int alignment, dag regList>
     : RegisterClass<"M68k", regTypes, alignment, regList>;
 
 // Data Registers
 def DR8  : MxRegClass<[i8],  16, (sequence "BD%u", 0, 7)>;
 def DR16 : MxRegClass<[i16], 16, (sequence "WD%u", 0, 7)>;
 def DR32 : MxRegClass<[i32], 32, (sequence "D%u",  0, 7)>;
 
 // Address Registers
-def AR16 : MxRegClass<[i16], 16, (sequence "WA%u", 0, 6)>;
+def AR16 : MxRegClass<[i16], 16, (add (sequence "WA%u", 0, 6), WSP)>;
 def AR32 : MxRegClass<[i32], 32, (add (sequence "A%u", 0, 6), SP)>;
 
-def AR32_NOSP : MxRegClass<[i32], 32, (add (sequence "A%u", 0, 6))>;
+def AR32_NOSP : MxRegClass<[i32], 32, (sequence "A%u", 0, 6)>;
 
 // Index Register Classes
 // FIXME try alternative ordering like `D0, D1, A0, A1, ...`
 def XR16 : MxRegClass<[i16], 16, (add DR16, AR16)>;
 def XR32 : MxRegClass<[i32], 32, (add DR32, AR32)>;
 
 def SPC  : MxRegClass<[i32], 32, (add SP)>;
 

 
 def AR16_TC : MxRegClass<[i16], 16, (add A0, A1)>;
 def AR32_TC : MxRegClass<[i32], 32, (add A0, A1)>;
 
 def XR16_TC : MxRegClass<[i16], 16, (add DR16_TC, AR16_TC)>;
 def XR32_TC : MxRegClass<[i32], 32, (add DR32_TC, AR32_TC)>;
 
 // These classes provide spill/restore order if used with MOVEM instruction
-def SPILL   : MxRegClass<[i32], 32, (add (add (sequence "D%u", 0, 7),
-                                              (sequence "A%u", 0, 6)), SP)>;
-def SPILL_R : MxRegClass<[i32], 32, (add SP, (add (sequence "A%u", 6, 0),
-                                                  (sequence "D%u", 7, 0)))>;
+def SPILL   : MxRegClass<[i32], 32, (add XR32)>;
+def SPILL_R : MxRegClass<[i32], 32, (add SP, (sequence "A%u", 6, 0), (sequence "D%u", 7, 0))>;

llvm/lib/Target/M68k/MCTargetDesc/M68kBaseInfo.h

static inline bool isAddressRegister(unsigned RegNo) {
   switch (RegNo) {
   case M68k::WA0:
   case M68k::WA1:
   case M68k::WA2:
   case M68k::WA3:
   case M68k::WA4:
   case M68k::WA5:
   case M68k::WA6:
-  case M68k::WA7:
+  case M68k::WSP:
   case M68k::A0:
   case M68k::A1:
   case M68k::A2:
   case M68k::A3:
   case M68k::A4:
   case M68k::A5:
   case M68k::A6:
-  case M68k::A7:
   case M68k::SP:
     return true;
   default:
     return false;
   }
 }
 
 static inline bool hasMultiMIOperands(unsigned Op, unsigned LogicalOpIdx) {
case 11:
     return M68k::A3;
   case 12:
     return M68k::A4;
   case 13:
     return M68k::A5;
   case 14:
     return M68k::A6;
   case 15:
-    return M68k::A7;
+    return M68k::SP;
   }
 }
 
 } // namespace M68kII
 
 } // namespace llvm
 
 #endif