[M68k] Introduce DReg bead

[ricky26]

Summary

This is required in order to determine during disassembly whether a
Reg bead without associated DA bead is referring to a data register.

[myhsu]

Does the remaining Reg (Beads) always mean address register? If that's the case, can we just rename it into AReg? Also, is it possible to just get rid of the DA Beads since we have separate DReg and AReg?

[ricky26]

It acts like a default when decoding (in one of the later patches). The DA bead is still needed since it's used for instructions where it can be either an address or data register.

As it stands, I could rename it but it might be a bit misleading. (Existing cases which don't need a specific register kind would all use AReg.)

Alternatively, perhaps I could add AReg and enforce that DReg/AReg cannot be combined with DA and keep Reg separate, solely for use with DA. I didn't think of that at the time.

[myhsu]

In D98534#2630064, @ricky26 wrote:

It acts like a default when decoding (in one of the later patches). The DA bead is still needed since it's used for instructions where it can be either an address or data register.

As it stands, I could rename it but it might be a bit misleading. (Existing cases which don't need a specific register kind would all use AReg.)

Ahh I see

Alternatively, perhaps I could add AReg and enforce that DReg/AReg cannot be combined with DA and keep Reg separate, solely for use with DA. I didn't think of that at the time.

Let's keep your current plan (i.e. only add DReg) for now. Since if Reg and DA are really needed I don't see a good reason to add another AReg if that doesn't really make implementing MCCodeEmitter or AsmParser easier.

[myhsu]

llvm/lib/Target/M68k/M68kInstrArithmetic.td

548

Can you move this and related changes to a separate patch? This seems irrelevant to the topic

[ricky26]

Remove operand type changes. (These will appear in another differential shortly.)

[ricky26]

Fix one superfluous DReg: the rr arithmetic includes the DA bit for the operand already.

[myhsu]

LGTM

llvm/lib/Target/M68k/M68kInstrArithmetic.td

 
 /// Encoding for Normal forms
 /// ----------------------------------------------------
 ///  F  E  D  C | B  A  9 | 8  7  6 | 5  4  3 | 2  1  0
 /// ----------------------------------------------------
 ///             |         |         | EFFECTIVE ADDRESS
 ///  x  x  x  x |   REG   | OP MODE |   MODE  |   REG
 /// ----------------------------------------------------
-class MxArithEncoding<MxBead4Bits CMD, MxEncOpMode OPMODE, MxBeadReg REG,
+class MxArithEncoding<MxBead4Bits CMD, MxEncOpMode OPMODE, MxBead REG,
                       MxEncEA EA, MxEncExt EXT>
     : MxEncoding<EA.Reg, EA.DA, EA.Mode, OPMODE.B0, OPMODE.B1, OPMODE.B2, REG,
                  CMD,EXT.Imm, EXT.B8, EXT.Scale, EXT.WL, EXT.DAReg>;
 
 /// Encoding for Extended forms
 /// ------------------------------------------------------
 ///  F  E  D  C | B  A  9 | 8 | 7  6 | 5  4 | 3 | 2  1  0
 /// ------------------------------------------------------
 ///  x  x  x  x |  REG Rx | 1 | SIZE | 0  0 | M |  REG Ry
 /// ------------------------------------------------------
 /// Rx - destination
 /// Ry - source
 /// M  - address mode switch
 class MxArithXEncoding<MxBead4Bits CMD, MxEncSize SIZE, MxBead1Bit MODE,
-                       MxBeadReg SRC, MxBeadReg DST>
+                       MxBeadDReg SRC, MxBeadDReg DST>
     : MxEncoding<SRC, MODE, MxBead2Bits<0b00>, SIZE, MxBead1Bit<0b1>, DST, CMD>;
 
 /// Encoding for Immediate forms
 /// ---------------------------------------------------
 ///  F  E  D  C  B  A  9  8 | 7  6 | 5  4  3 | 2  1  0
 /// ---------------------------------------------------
 ///                         |      | EFFECTIVE ADDRESS
 ///  x  x  x  x  x  x  x  x | SIZE |   MODE  |   REG

 //===----------------------------------------------------------------------===//
 // Add/Sub
 //===----------------------------------------------------------------------===//
 
 let Defs = [CCR] in {
 let Constraints = "$src = $dst" in {
 
 // $reg, $ccr <- $reg op $reg
-class MxBiArOp_RFRR_xEA<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
+class MxBiArOp_RFRR_xEA<string MN, SDNode NODE, MxType TYPE, bits<4> CMD, MxBead REG>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd),
            MN#"."#TYPE.Prefix#"\t$opd, $dst",
            [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))],
            MxArithEncoding<MxBead4Bits<CMD>,
                            !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
-                           MxBeadReg<0>,
+                           REG,
                            !cast<MxEncEA>("MxEncEA"#TYPE.RLet#"_2"),
                            MxExtEmpty>>;
 
 /// This Op is similar to the one above except it uses reversed opmode, some
 /// commands(e.g. eor) do not support dEA or rEA modes and require EAd for
 /// register only operations.
 /// NOTE when using dd commands it is irrelevant which opmode to use(as it seems)
 /// but some opcodes support address register and some do not which creates this
 /// mess.
 class MxBiArOp_RFRR_EAd<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd),
            MN#"."#TYPE.Prefix#"\t$opd, $dst",
            [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))],
            MxArithEncoding<MxBead4Bits<CMD>,
                            !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"EAd"),
-                           MxBeadReg<2>, MxEncEAd_0, MxExtEmpty>>;
+                           MxBeadDReg<2>, MxEncEAd_0, MxExtEmpty>>;
 
 // $reg <- $reg op $imm
 class MxBiArOp_RFRI_xEA<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.IOp:$opd),
               MN#"."#TYPE.Prefix#"\t$opd, $dst",
               [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))],
               MxArithEncoding<MxBead4Bits<CMD>,
                               !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
-                              MxBeadReg<0>, MxEncEAi,
+                              MxBeadDReg<0>, MxEncEAi,
                               !cast<MxEncExt>("MxExtI"#TYPE.Size#"_2")>>;
 
 // Again, there are two ways to write an immediate to Dn register either dEA
 // opmode or using *I encoding, and again some instrucitons also support address
 // registers some do not.
 class MxBiArOp_RFRI<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.IOp:$opd),
               MN#"i."#TYPE.Prefix#"\t$opd, $dst",
               [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))],
               MxArithImmEncoding<MxBead4Bits<CMD>, !cast<MxEncSize>("MxEncSize"#TYPE.Size),
                    !cast<MxEncEA>("MxEncEA"#TYPE.RLet#"_0"), MxExtEmpty,
                    !cast<MxEncExt>("MxExtI"#TYPE.Size#"_2")>>;
 
 let mayLoad = 1 in
 class MxBiArOp_RFRM<string MN, SDNode NODE, MxType TYPE, MxOperand OPD, ComplexPattern PAT,
                     bits<4> CMD, MxEncEA EA, MxEncExt EXT>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, OPD:$opd),
            MN#"."#TYPE.Prefix#"\t$opd, $dst",
            [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, (TYPE.Load PAT:$opd)))],
            MxArithEncoding<MxBead4Bits<CMD>,
                            !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
-                           MxBeadReg<0>, EA, EXT>>;
+                           MxBeadDReg<0>, EA, EXT>>;
 
 } // Constraints
 
 let mayLoad = 1, mayStore = 1 in {
 
 // FIXME MxBiArOp_FMR/FMI cannot consume CCR from MxAdd/MxSub which leads for
 // MxAdd to survive the match and subsequent mismatch.
 class MxBiArOp_FMR<string MN, SDNode NODE, MxType TYPE,
                    MxOperand MEMOpd, ComplexPattern MEMPat,
                    bits<4> CMD, MxEncEA EA, MxEncExt EXT>
     : MxInst<(outs), (ins MEMOpd:$dst, TYPE.ROp:$opd),
         MN#"."#TYPE.Prefix#"\t$opd, $dst",
         [],
         MxArithEncoding<MxBead4Bits<CMD>,
                         !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"EA"#TYPE.RLet),
-                        MxBeadReg<1>, EA, EXT>>;
+                        MxBeadDReg<1>, EA, EXT>>;
 
 class MxBiArOp_FMI<string MN, SDNode NODE, MxType TYPE,
                    MxOperand MEMOpd, ComplexPattern MEMPat,
                    bits<4> CMD, MxEncEA MEMEA, MxEncExt MEMExt>
     : MxInst<(outs), (ins MEMOpd:$dst, TYPE.IOp:$opd),
         MN#"."#TYPE.Prefix#"\t$opd, $dst",
         [],
         MxArithImmEncoding<MxBead4Bits<CMD>,
def NAME#"8ji"  : MxBiArOp_FMI<MN, NODE, MxType8,  MxType8.JOp,  MxType8.JPat,
                                  CMDI, MxEncEAj_0, MxExtEmpty>;
   def NAME#"16ji" : MxBiArOp_FMI<MN, NODE, MxType16, MxType16.JOp, MxType16.JPat,
                                  CMDI, MxEncEAj_0, MxExtEmpty>;
   def NAME#"32ji" : MxBiArOp_FMI<MN, NODE, MxType32, MxType32.JOp, MxType32.JPat,
                                  CMDI, MxEncEAj_0, MxExtEmpty>;
 
   let isCommutable = isComm in {
 
-    def NAME#"8dd"  : MxBiArOp_RFRR_xEA<MN, NODE, MxType8d,  CMD>;
-    def NAME#"16dd" : MxBiArOp_RFRR_xEA<MN, NODE, MxType16d, CMD>;
-    def NAME#"32dd" : MxBiArOp_RFRR_xEA<MN, NODE, MxType32d, CMD>;
+    def NAME#"8dd"  : MxBiArOp_RFRR_xEA<MN, NODE, MxType8d,  CMD, MxBeadDReg<0>>;
+    def NAME#"16dd" : MxBiArOp_RFRR_xEA<MN, NODE, MxType16d, CMD, MxBeadDReg<0>>;
+    def NAME#"32dd" : MxBiArOp_RFRR_xEA<MN, NODE, MxType32d, CMD, MxBeadDReg<0>>;
 
   } // isComm
 
 } // MxBiArOp_DF
 
 
 // These special snowflakes allowed to match address registers but since *A
 // operations do not produce CCR we should not match them against Mx nodes that
def NAME#"32rf" : MxBiArOp_RFRM<MN, NODE, MxType32r, MxType32.FOp, MxType32.FPat,
                                   CMD, MxEncEAf_2, MxExtBrief_2>;
   def NAME#"32rp" : MxBiArOp_RFRM<MN, NODE, MxType32r, MxType32.POp, MxType32.PPat,
                                   CMD, MxEncEAp_2, MxExtI16_2>;
   def NAME#"32rj" : MxBiArOp_RFRM<MN, NODE, MxType32r, MxType32.JOp, MxType32.JPat,
                                   CMD, MxEncEAj_2, MxExtEmpty>;
   def NAME#"32ri" : MxBiArOp_RFRI_xEA<MN, NODE, MxType32r, CMD>;
 
   let isCommutable = isComm in
-  def NAME#"32rr" : MxBiArOp_RFRR_xEA<MN, NODE, MxType32r, CMD>;
+  def NAME#"32rr" : MxBiArOp_RFRR_xEA<MN, NODE, MxType32r, CMD, MxBeadReg<0>>;
 
 } // MxBiArOp_AF
 
 // NOTE These naturally produce CCR
 
 defm ADD : MxBiArOp_DF<"add", MxAdd, 1, 0xD, 0x6>;
 defm ADD : MxBiArOp_AF<"add", MxAdd, 1, 0xD, 0x6>;
 defm SUB : MxBiArOp_DF<"sub", MxSub, 0, 0x9, 0x4>;
 defm SUB : MxBiArOp_AF<"sub", MxSub, 0, 0x9, 0x4>;
 
 
 let Uses = [CCR], Defs = [CCR] in {
 let Constraints = "$src = $dst" in {
 
 // $reg, ccr <- $reg op $reg op ccr
 class MxBiArOp_RFRRF<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd),
              MN#"."#TYPE.Prefix#"\t$opd, $dst",
              [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd, CCR))],
              MxArithXEncoding<MxBead4Bits<CMD>,
                               !cast<MxEncSize>("MxEncSize"#TYPE.Size),
-                              MxBead1Bit<0>, MxBeadReg<2>, MxBeadReg<0>>>;
+                              MxBead1Bit<0>, MxBeadDReg<2>, MxBeadDReg<0>>>;
 
 } // Constraints
 } // Uses, Defs
 
 multiclass MxBiArOp_RFF<string MN, SDNode NODE, bit isComm, bits<4> CMD> {
 
 let isCommutable = isComm in {
 

 
 let Defs = [CCR] in {
 class MxCmp_RR<MxType TYPE>
     : MxInst<(outs), (ins TYPE.ROp:$lhs, TYPE.ROp:$rhs),
              "cmp."#TYPE.Prefix#"\t$lhs, $rhs",
              [(set CCR, (MxCmp TYPE.VT:$lhs, TYPE.VT:$rhs))],
              MxArithEncoding<MxBead4Bits<0xB>,
                              !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"dEA"),
-                             MxBeadReg<1>, MxEncEAd_0, MxExtEmpty>>;
+                             MxBeadDReg<1>, MxEncEAd_0, MxExtEmpty>>;
 
 class MxCmp_RI<MxType TYPE>
     : MxInst<(outs), (ins TYPE.IOp:$imm, TYPE.ROp:$reg),
              "cmpi."#TYPE.Prefix#"\t$imm, $reg",
              [(set CCR, (MxCmp TYPE.IPat:$imm, TYPE.VT:$reg))],
              MxArithImmEncoding<MxBead4Bits<0xC>,
                                 !cast<MxEncSize>("MxEncSize"#TYPE.Size),
                                 MxEncEAd_1, MxExtEmpty,

 
 class MxCmp_RM<MxType TYPE, MxOperand MEMOpd, ComplexPattern MEMPat,
                MxEncEA EA, MxEncExt EXT>
     : MxInst<(outs), (ins TYPE.ROp:$reg, MEMOpd:$mem),
              "cmp."#TYPE.Prefix#"\t$mem, $reg",
              [(set CCR, (MxCmp (load MEMPat:$mem), TYPE.ROp:$reg))],
              MxArithEncoding<MxBead4Bits<0xB>,
                              !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"dEA"),
-                             MxBeadReg<0>, EA, EXT>>;
+                             MxBeadDReg<0>, EA, EXT>>;
 } // let mayLoad = 1
 
 } // let Defs = [CCR]
 
 multiclass MMxCmp_RM<MxType TYPE> {
   def NAME#TYPE.KOp.Letter : MxCmp_RM<TYPE, TYPE.KOp, TYPE.KPat, MxEncEAk,
                                       MxExtBrief_1>;
   def NAME#TYPE.QOp.Letter : MxCmp_RM<TYPE, TYPE.QOp, TYPE.QPat, MxEncEAq,

 def MxExtOpmode_lb : MxBead3Bits<0b111>;
 
 /// ---------------------------------------------------
 ///  F  E  D  C  B  A  9 | 8  7  6 | 5  4  3 | 2  1  0
 /// ---------------------------------------------------
 ///  0  1  0  0  1  0  0 |  OPMODE | 0  0  0 |   REG
 /// ---------------------------------------------------
 class MxExtEncoding<MxBead3Bits OPMODE>
-    : MxEncoding<MxBeadReg<0>, MxBead3Bits<0b000>, OPMODE,
+    : MxEncoding<MxBeadDReg<0>, MxBead3Bits<0b000>, OPMODE,
                  MxBead3Bits<0b100>, MxBead4Bits<0b0100>>;
 
 let Defs = [CCR] in
 let Constraints = "$src = $dst" in
 class MxExt<MxType TO, MxType FROM>
     : MxInst<(outs TO.ROp:$dst), (ins TO.ROp:$src),
               "ext."#TO.Prefix#"\t$src", [],
               MxExtEncoding<!cast<MxBead3Bits>("MxExtOpmode_"#TO.Prefix#FROM.Prefix)>>;

 /// Word operation:
 /// ----------------------------------------------------
 ///  F  E  D  C | B  A  9 | 8  7  6 | 5  4  3 | 2  1  0
 /// ----------------------------------------------------
 ///             |         |         | EFFECTIVE ADDRESS
 ///  x  x  x  x |   REG   | OP MODE |   MODE  |   REG
 /// ----------------------------------------------------
 class MxDiMuEncoding<MxBead4Bits CMD, MxBead3Bits OPMODE, MxEncEA EA, MxEncExt EXT>
-    : MxEncoding<EA.Reg, EA.DA, EA.Mode, OPMODE, MxBeadReg<0>, CMD,
+    : MxEncoding<EA.Reg, EA.DA, EA.Mode, OPMODE, MxBeadDReg<0>, CMD,
                  EXT.Imm, EXT.B8, EXT.Scale, EXT.WL, EXT.DAReg>;
 
 let Defs = [CCR] in {
 let Constraints = "$src = $dst" in {
 // $reg <- $reg op $reg
 class MxDiMuOp_DD<string MN, bits<4> CMD, MxBead3Bits OPMODE,
                   MxOperand DST, MxOperand OPD>
     : MxInst<(outs DST:$dst), (ins DST:$src, OPD:$opd), MN#"\t$opd, $dst", [],
def "S"#NAME#"d32i16" : MxDiMuOp_DI<MN#"s", CMD, MxSDiMuOpmode, MxDRD32,
                                       Mxi16imm>;
   def "U"#NAME#"d32i16" : MxDiMuOp_DI<MN#"u", CMD, MxUDiMuOpmode, MxDRD32,
                                       Mxi16imm>;
 
 }
 
 defm DIV : MxDiMuOp<"div", 0x8>;
 
 // RR i8
 def : Pat<(sdiv i8:$dst, i8:$opd),
           (EXTRACT_SUBREG
             (SDIVd32d16 (MOVSXd32d8 $dst), (MOVSXd16d8 $opd)),
              MxSubRegIndex8Lo)>;
 
 def : Pat<(udiv i8:$dst, i8:$opd),
           (EXTRACT_SUBREG
             (UDIVd32d16 (MOVZXd32d8 $dst), (MOVZXd16d8 $opd)),

llvm/lib/Target/M68k/M68kInstrBits.td

 // BTST
 //===----------------------------------------------------------------------===//
 
 /// ------------+---------+---------+---------+---------
 ///  F  E  D  C | B  A  9 | 8  7  6 | 5  4  3 | 2  1  0
 /// ------------+---------+---------+---------+---------
 ///  0  0  0  0 |   REG   | 1  0  0 |   MODE  |   REG
 /// ------------+---------+---------+---------+---------
-class MxBTSTEnc_R<MxBeadReg REG, MxEncEA EA, MxEncExt EXT>
+class MxBTSTEnc_R<MxBeadDReg REG, MxEncEA EA, MxEncExt EXT>
     : MxEncoding<EA.Reg, EA.DA, EA.Mode, MxBead3Bits<0b100>, REG, MxBead4Bits<0b0000>,
                  EXT.Imm, EXT.B8, EXT.Scale, EXT.WL, EXT.DAReg>;
 
 /// -------------------------------+---------+---------
 ///  F  E  D  C  B  A  9  8 . 7  6 | 5  4  3 | 2  1  0
 /// -------------------------------+---------+---------
 ///  0  0  0  0  1  0  0  0 . 0  0 |   MODE  |   REG
 /// ------------------------+------+---------+---------
 ///  0  0  0  0  0  0  0  0 |        BIT NUMBER
 /// ------------------------+--------------------------
 class MxBTSTEnc_I<MxBead8Imm IMM, MxEncEA EA, MxEncExt EXT>
     : MxEncoding<EA.Reg, EA.DA, EA.Mode, MxBead2Bits<0b00>,
                  MxBead4Bits<0b1000>, MxBead4Bits<0b0000>, IMM,
                  EXT.Imm, EXT.B8, EXT.Scale, EXT.WL, EXT.DAReg>;
 
 let Defs = [CCR] in {
 class MxBTST_RR<MxType TYPE>
     : MxInst<(outs), (ins TYPE.ROp:$dst, TYPE.ROp:$bitno), "btst\t$bitno, $dst",
              [(set CCR, (MxBt TYPE.VT:$dst, TYPE.VT:$bitno))],
-             MxBTSTEnc_R<MxBeadReg<1>, MxEncEAd_0, MxExtEmpty>>;
+             MxBTSTEnc_R<MxBeadDReg<1>, MxEncEAd_0, MxExtEmpty>>;
 
 class MxBTST_RI<MxType TYPE>
     : MxInst<(outs), (ins TYPE.ROp:$dst, TYPE.IOp:$bitno), "btst\t$bitno, $dst",
              [(set CCR, (MxBt TYPE.VT:$dst, TYPE.IPat:$bitno))],
              MxBTSTEnc_I<MxBead8Imm<1>, MxEncEAd_0, MxExtEmpty>>;
 
 class MxBTST_MR<MxType TYPE, MxOperand MEMOpd, ComplexPattern MEMPat,
                 MxEncEA EA, MxEncExt EXT>
     : MxInst<(outs), (ins MEMOpd:$dst, TYPE.ROp:$bitno), "btst\t$bitno, $dst",
              [(set CCR, (MxBt (TYPE.Load MEMPat:$dst), TYPE.VT:$bitno))],
-             MxBTSTEnc_R<MxBeadReg<1>, EA, EXT>>;
+             MxBTSTEnc_R<MxBeadDReg<1>, EA, EXT>>;
 
 class MxBTST_MI<MxType TYPE, MxOperand MEMOpd, ComplexPattern MEMPat,
                 MxEncEA EA, MxEncExt EXT>
     : MxInst<(outs), (ins MEMOpd:$dst, TYPE.IOp:$bitno), "btst\t$bitno, $dst",
              [(set CCR, (MxBt (TYPE.Load MEMPat:$dst), TYPE.IPat:$bitno))],
              MxBTSTEnc_I<MxBead8Imm<1>, EA, EXT>>;
 } // Defs = [CCR]
 

llvm/lib/Target/M68k/M68kInstrFormats.td

 
 /// bits<3> o - operand number
 /// bit a     - use alternative, used to select index register or
 ///             outer displacement/immediate
 /// suffix NP means non-padded
 class MxBeadDAReg  <bits<3> o, bit a = 0> : MxBead<0x5, o{0}, o{1}, o{2}, a>;
 class MxBeadDA     <bits<3> o, bit a = 0> : MxBead<0x6, o{0}, o{1}, o{2}, a>;
 class MxBeadReg    <bits<3> o, bit a = 0> : MxBead<0x7, o{0}, o{1}, o{2}, a>;
-class MxBead8Disp  <bits<3> o, bit a = 0> : MxBead<0x8, o{0}, o{1}, o{2}, a>;
+class MxBeadDReg   <bits<3> o, bit a = 0> : MxBead<0x8, o{0}, o{1}, o{2}, a>;
+class MxBead8Disp  <bits<3> o, bit a = 0> : MxBead<0x9, o{0}, o{1}, o{2}, a>;
 
 /// Add Immediate to the instruction. 8-bit version is padded with zeros to fit
 /// the word.
-class MxBead8Imm   <bits<3> o, bit a = 0> : MxBead<0x9, o{0}, o{1}, o{2}, a>;
-class MxBead16Imm  <bits<3> o, bit a = 0> : MxBead<0xA, o{0}, o{1}, o{2}, a>;
-class MxBead32Imm  <bits<3> o, bit a = 0> : MxBead<0xB, o{0}, o{1}, o{2}, a>;
+class MxBead8Imm   <bits<3> o, bit a = 0> : MxBead<0xA, o{0}, o{1}, o{2}, a>;
+class MxBead16Imm  <bits<3> o, bit a = 0> : MxBead<0xB, o{0}, o{1}, o{2}, a>;
+class MxBead32Imm  <bits<3> o, bit a = 0> : MxBead<0xC, o{0}, o{1}, o{2}, a>;
 
 /// Encodes an immediate 0-7(alt. 1-8) into 3 bit field
-class MxBead3Imm   <bits<3> o, bit a = 0> : MxBead<0xC, o{0}, o{1}, o{2}, a>;
+class MxBead3Imm   <bits<3> o, bit a = 0> : MxBead<0xD, o{0}, o{1}, o{2}, a>;
 
 
 class MxEncoding<MxBead n0  = MxBeadTerm, MxBead n1  = MxBeadTerm,
                  MxBead n2  = MxBeadTerm, MxBead n3  = MxBeadTerm,
                  MxBead n4  = MxBeadTerm, MxBead n5  = MxBeadTerm,
                  MxBead n6  = MxBeadTerm, MxBead n7  = MxBeadTerm,
                  MxBead n8  = MxBeadTerm, MxBead n9  = MxBeadTerm,
                  MxBead n10 = MxBeadTerm, MxBead n11 = MxBeadTerm,
class MxEncEA<MxBead reg, MxBead mode, MxBead da = MxBeadIgnore> {
   MxBead Reg = reg;
   MxBead Mode = mode;
   MxBead DA = da;
 }
 
 // FIXME: Is there a way to factorize the addressing mode suffix (i.e.
 // 'r', 'd', 'a' etc.) and use something like multiclass to replace?
 def MxEncEAr_0: MxEncEA<MxBeadDAReg<0>, MxBead2Bits<0b00>>;
-def MxEncEAd_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b00>, MxBead1Bit<0>>;
+def MxEncEAd_0: MxEncEA<MxBeadDReg<0>, MxBead2Bits<0b00>, MxBead1Bit<0>>;
 def MxEncEAa_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b00>, MxBead1Bit<1>>;
 def MxEncEAj_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b01>, MxBead1Bit<0>>;
 def MxEncEAo_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b01>, MxBead1Bit<1>>;
 def MxEncEAe_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b10>, MxBead1Bit<0>>;
 def MxEncEAp_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b10>, MxBead1Bit<1>>;
 def MxEncEAf_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b11>, MxBead1Bit<0>>;
 
 def MxEncEAa_0_reflected : MxEncEA<MxBeadReg<0>, MxBead3Bits<0b001>>;
 def MxEncEAr_0_reflected : MxEncEA<MxBeadReg<0>, MxBead2Bits<0b00>, MxBeadDA<0>>;
 
 def MxEncEAr_1: MxEncEA<MxBeadDAReg<1>, MxBead2Bits<0b00>>;
-def MxEncEAd_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b00>, MxBead1Bit<0>>;
+def MxEncEAd_1: MxEncEA<MxBeadDReg<1>, MxBead2Bits<0b00>, MxBead1Bit<0>>;
 def MxEncEAa_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b00>, MxBead1Bit<1>>;
 def MxEncEAj_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b01>, MxBead1Bit<0>>;
 def MxEncEAo_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b01>, MxBead1Bit<1>>;
 def MxEncEAe_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b10>, MxBead1Bit<0>>;
 def MxEncEAp_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b10>, MxBead1Bit<1>>;
 def MxEncEAf_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b11>, MxBead1Bit<0>>;
 
 def MxEncEAr_2: MxEncEA<MxBeadDAReg<2>, MxBead2Bits<0b00>>;
-def MxEncEAd_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b00>, MxBead1Bit<0>>;
+def MxEncEAd_2: MxEncEA<MxBeadDReg<2>, MxBead2Bits<0b00>, MxBead1Bit<0>>;
 def MxEncEAa_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b00>, MxBead1Bit<1>>;
 def MxEncEAj_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b01>, MxBead1Bit<0>>;
 def MxEncEAo_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b01>, MxBead1Bit<1>>;
 def MxEncEAe_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b10>, MxBead1Bit<0>>;
 def MxEncEAp_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b10>, MxBead1Bit<1>>;
 def MxEncEAf_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b11>, MxBead1Bit<0>>;
 
 def MxEncEAb : MxEncEA<MxBead3Bits<0b001>, MxBead2Bits<0b11>, MxBead1Bit<1>>;

llvm/lib/Target/M68k/M68kInstrShiftRotate.td

 def MxROOP_RO  : MxBead2Bits<0b11>;
 
 /// ------------+---------+---+------+---+------+---------
 ///  F  E  D  C | B  A  9 | 8 | 7  6 | 5 | 4  3 | 2  1  0
 /// ------------+---------+---+------+---+------+---------
 ///  1  1  1  0 | REG/IMM | D | SIZE |R/I|  OP  |   REG
 /// ------------+---------+---+------+---+------+---------
 class MxSREncoding_R<MxBead1Bit DIRECTION, MxBead2Bits ROOP, MxEncSize SIZE>
-    : MxEncoding<MxBeadReg<0>, ROOP, MxBead1Bit<1>, SIZE, DIRECTION,
-                 MxBeadReg<2>, MxBead4Bits<0b1110>>;
+    : MxEncoding<MxBeadDReg<0>, ROOP, MxBead1Bit<1>, SIZE, DIRECTION,
+                 MxBeadDReg<2>, MxBead4Bits<0b1110>>;
 
 class MxSREncoding_I<MxBead1Bit DIRECTION, MxBead2Bits ROOP, MxEncSize SIZE>
-    : MxEncoding<MxBeadReg<0>, ROOP, MxBead1Bit<0>, SIZE, DIRECTION,
+    : MxEncoding<MxBeadDReg<0>, ROOP, MxBead1Bit<0>, SIZE, DIRECTION,
                  MxBead3Imm<2, 1>, MxBead4Bits<0b1110>>;
 
 // $reg <- $reg op $reg
 class MxSR_DD<string MN, MxType TYPE, SDNode NODE,
               MxBead1Bit RODI, MxBead2Bits ROOP>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd),
              MN#"."#TYPE.Prefix#"\t$opd, $dst",
              [(set TYPE.VT:$dst, (NODE TYPE.VT:$src, TYPE.VT:$opd))],

llvm/lib/Target/M68k/MCTargetDesc/M68kBaseInfo.h

enum {
   Ctrl = 0x0,
   Bits1 = 0x1,
   Bits2 = 0x2,
   Bits3 = 0x3,
   Bits4 = 0x4,
   DAReg = 0x5,
   DA = 0x6,
   Reg = 0x7,
-  Disp8 = 0x8,
-  Imm8 = 0x9,
-  Imm16 = 0xA,
-  Imm32 = 0xB,
-  Imm3 = 0xC,
+  DReg = 0x8,
+  Disp8 = 0x9,
+  Imm8 = 0xA,
+  Imm16 = 0xB,
+  Imm32 = 0xC,
+  Imm3 = 0xD,
 };
 
 // Ctrl payload
 enum {
   Term = 0x0,
   Ignore = 0x1,
 };
 } // namespace M68kBeads

llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp

unsigned M68kMCCodeEmitter::encodeReg(unsigned ThisByte, uint8_t Bead,
   case M68kBeads::DAReg:
     Reg = true;
     DA = true;
     break;
   case M68kBeads::DA:
     Reg = false;
     DA = true;
     break;
+  case M68kBeads::DReg:
   case M68kBeads::Reg:
     Reg = true;
     DA = false;
     break;
   }
 
   unsigned Op = (Bead & 0x70) >> 4;
   bool Alt = (Bead & 0x80);
for (uint8_t Bead = *Beads; Bead; Bead = *++Beads) {
     case M68kBeads::Bits2:
     case M68kBeads::Bits3:
     case M68kBeads::Bits4:
       Offset +=
           encodeBits(ThisByte, Bead, MI, Desc, Buffer, Offset, Fixups, STI);
       break;
     case M68kBeads::DAReg:
     case M68kBeads::DA:
+    case M68kBeads::DReg:
     case M68kBeads::Reg:
       Offset +=
           encodeReg(ThisByte, Bead, MI, Desc, Buffer, Offset, Fixups, STI);
       break;
     case M68kBeads::Disp8:
     case M68kBeads::Imm8:
     case M68kBeads::Imm16:
     case M68kBeads::Imm32: