[M68k] Implement AsmParser

[ricky26]

Summary

This is a work-in-progress implementation of an assembler for M68k.

Outstanding work:

• Updating existing tests assembly syntax
• Writing new tests for the assembler (and disassembler)

I've left those until there's consensus that this approach is okay (I hope that's okay!).

Questions I'm aware of:

• Should this use Motorola or gas syntax? (At the moment it uses Motorola syntax.)

Depends on D98519

Depends on D98532

Depends on D98534

Depends on D98535

Depends on D98536

[ricky26]

Move operand parser definitions into earlier patch

[myhsu]

Should this use Motorola or gas syntax? (At the moment it uses Motorola syntax.)

I spent some time dig into GCC and binutils's source. By default GCC generate assembly that conforms to Motorola's syntax (thus GAS should consume that syntax by default). Jessica has pointed out in the review for the 4-th patch that for some reason, (GNU) objdump doesn't conform to Motorola's syntax. Though I didn't know the full story but apparently objdump and GCC are using separate code base to print out assembly and for unknown reasons, the former just didn't want to adopt Motorola's syntax :-P (it doesn't have the option to switch between different syntaxes either)
The bottom line is that I would recommend to implement Motorola's syntax first. We can always add "GNU flavor" assembly printer if needed in the future, just like ATT/Intel syntax in X86 land.

P.S. Alternatively GCC can generate they called "MIT syntax" which -- I have no idea what that is tbh --is probably closer to conventional GNU assembly syntax. But that syntax is only enabled if you're building cross-compile m68k gcc for openbsd

[ricky26]

I've marked this 'Ready for Review' since otherwise notifications don't happen. To be clear though, this is not ready to merge.

In D98537#2625355, @myhsu wrote:

Should this use Motorola or gas syntax? (At the moment it uses Motorola syntax.)

I spent some time dig into GCC and binutils's source. By default GCC generate assembly that conforms to Motorola's syntax (thus GAS should consume that syntax by default). Jessica has pointed out in the review for the 4-th patch that for some reason, (GNU) objdump doesn't conform to Motorola's syntax. Though I didn't know the full story but apparently objdump and GCC are using separate code base to print out assembly and for unknown reasons, the former just didn't want to adopt Motorola's syntax :-P (it doesn't have the option to switch between different syntaxes either)
The bottom line is that I would recommend to implement Motorola's syntax first. We can always add "GNU flavor" assembly printer if needed in the future, just like ATT/Intel syntax in X86 land.

P.S. Alternatively GCC can generate they called "MIT syntax" which -- I have no idea what that is tbh --is probably closer to conventional GNU assembly syntax. But that syntax is only enabled if you're building cross-compile m68k gcc for openbsd

The MIT syntax appears to be the default documented syntax in the as manual (http://web.mit.edu/gnu/doc/html/as_16.html#SEC189, a mirror but it seems up to date). Their logic seems sensible to me: we should support both addressing syntaxes and it should be pretty sane to support both.

However, as' manual on Motorola Syntax still does something which doesn't match Motorola's manual: prefixing the registers with %. Does GCC do this? It looks like as supports bare registers, but it's behind a flag. (Motorola's assembly syntax uses % for binary numbers but we can support both with a bit of peeking.)

So, perhaps the strategy should be this:

• Change the assembler/disassembler to use %-prefixed registers in this patch
• Add support for parsing MIT operand syntax in a later patch
• Add support for emitting MIT operand syntax on a flag in a later patch
• Add support for the alternate assembly directive names in a later patch
• Add support for parsing register names without a prefix on a flag in a later patch

The last point worries me a little since it seems a very commonly referenced format but we'd be doing what as does, if I understand correctly.

[anirudhp]

Hi!

I came across the series of patches that are adding Motorola asm support. I have a quick question as I'm not too familiar with Motorola asm.

Are there any differences in how the input/output/clobber operands in a possible inline asm statement that is parsed, or do they follow the standard GNU asm format with just platform specific syntactical differences in the assembler text?

[ricky26]

In D98537#2659066, @anirudhp wrote:

Are there any differences in how the input/output/clobber operands in a possible inline asm statement that is parsed, or do they follow the standard GNU asm format with just platform specific syntactical differences in the assembler text?

The only difference should be in the actual assembly syntax itself, however, you raise an interesting point because in Motorola-flavour assembly %0/%1 would be parsed as a single-bit constant... Which I hadn't thought of.

I'll be honest: at this stage I've not tested inline assembly at all.

[anirudhp]

The only difference should be in the actual assembly syntax itself, however, you raise an interesting point because in Motorola-flavour assembly %0/%1 would be parsed as a single-bit constant... Which I hadn't thought of.

I'll be honest: at this stage I've not tested inline assembly at all.

Thank you for clarifying!

[ricky26]

Reworked parsing and added the first test

[ricky26]

Rebase onto latest main

[ricky26]

I've added a test (it uses many of the instructions which are defined with both Motorola & MIT operand syntax) and tidied everything up.

I think this is now ready for a real review.

[ricky26]

Remove header to appease clang-tidy

[glaubitz]

llvm/lib/Target/M68k/MCTargetDesc/M68kMCAsmInfo.cpp

34 ↗

(On Diff #334958)

This change is already part of D98519. Could you remove it from here or from D98519?

[ricky26]

Rebase onto changed AsmLexer patch

[ricky26]

llvm/lib/Target/M68k/MCTargetDesc/M68kMCAsmInfo.cpp

34 ↗

(On Diff #334958)

Yeah, I just needed to rebase. :)

[myhsu]

Thanks for this amazing efforts :-) I only have minor formatting comments inlined in the code.
I do have a more high-level question: It seems that you only support Motorola syntax right now, is that true? I'm totally fine if you don't add the MIT syntax in this patch, just want to make sure.
Now a bigger issue is the testing: Presumably we should rewrite all of our existing tests under test/CodeGen/M68k/Encoding into assembly and put it under test/MC/M68k. I believe this can give us a better testing coverage on all of our MC components including AsmParser.
On one hand I don't want to put those migrating changes into this patch because it will easily bloat the size. Not to mention those tests contains binary encoding tests, so if we need migrate both kinds of tests at once. On the other hand, I still need to make sure this patch reaches certain test coverage. Fortunately, the test you provided seemed to cover cases in each instruction classes. Can you add a comment in that test file to note our tests migration plan?

llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp

52

Should this be exposed as public method?

56

ditto for the above three. Ideally we should minimize the number of public methods

llvm/test/MC/M68k/instructions.s

2

-check-prefixes=CHECK is redundant

[ricky26]

In D98537#2669604, @myhsu wrote:

Thanks for this amazing efforts :-) I only have minor formatting comments inlined in the code.
I do have a more high-level question: It seems that you only support Motorola syntax right now, is that true? I'm totally fine if you don't add the MIT syntax in this patch, just want to make sure.
Now a bigger issue is the testing: Presumably we should rewrite all of our existing tests under test/CodeGen/M68k/Encoding into assembly and put it under test/MC/M68k. I believe this can give us a better testing coverage on all of our MC components including AsmParser.
On one hand I don't want to put those migrating changes into this patch because it will easily bloat the size. Not to mention those tests contains binary encoding tests, so if we need migrate both kinds of tests at once. On the other hand, I still need to make sure this patch reaches certain test coverage. Fortunately, the test you provided seemed to cover cases in each instruction classes. Can you add a comment in that test file to note our tests migration plan?

Thanks! I'm having fun and it's been nice to dip my toes into LLVM contribution. :)

For now, this only supports Motorola syntax (actually, MIT-style (offset, %reg) should parse correctly too). It also only supports _some_ operand formats (immediate, address, direct register, indirect and indirect with displacement).

I agree about the tests. I think the existing tests should be converted to Motorola syntax too (as that seems to be the canonical format), however, I'd argue that we should do those after the assembler & disassembler have landed (in my opinion, fleshing out that functionality is more pressing as it helps us write better tests more easily).

The included test covers the broad strokes of the supported syntax so far and should be enough to prevent code rot. As per the older comment it'll still need a fair few (smaller) revisions. In my opinion, it makes the most sense to add more tests as we go through and ensure the AsmParser actually supports everything it should. Perhaps it makes sense to add relevant Bugzilla bugs for the missing functionality as a prerequisite to landing this?

llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp

52

Hadn't thought much about this as the class is in an anonymous namespace but yes, makes sense, I'll sort them out properly.

[myhsu]

I agree about the tests. I think the existing tests should be converted to Motorola syntax too (as that seems to be the canonical format), however, I'd argue that we should do those after the assembler & disassembler have landed (in my opinion, fleshing out that functionality is more pressing as it helps us write better tests more easily).

Perfect, I'll start to rewrite the tests in parallel because we also need to solve several issues (e.g. try to get rid of extract-section command in the tests) alone the way so I can imagine it takes time.

The included test covers the broad strokes of the supported syntax so far and should be enough to prevent code rot. As per the older comment it'll still need a fair few (smaller) revisions. In my opinion, it makes the most sense to add more tests as we go through and ensure the AsmParser actually supports everything it should. Perhaps it makes sense to add relevant Bugzilla bugs for the missing functionality as a prerequisite to landing this?

For sure, please do it.

[ricky26]

• Hide private implementation details of M68kAsmParser
• Remove superfluous FileCheck parameter from test
• Add migration notice to test

[ricky26]

Use assembly comments in the assembly test rather than C++ comments

[ricky26]

@myhsu when you get a moment, can you check that this is all OK now? :)

[myhsu]

In D98537#2682808, @ricky26 wrote:

@myhsu when you get a moment, can you check that this is all OK now? :)

sorry I missed your last update. LGTM now

[glaubitz]

In D98537#2684910, @myhsu wrote:

In D98537#2682808, @ricky26 wrote:

@myhsu when you get a moment, can you check that this is all OK now? :)

sorry I missed your last update. LGTM now

Great to see such a major step forward already! Great work!

llvm/lib/Target/M68k/AsmParser/CMakeLists.txt

+add_llvm_component_library(LLVMM68kAsmParser
+        M68kAsmParser.cpp
+
+  LINK_COMPONENTS
+  MC
+  MCParser
+  Support
+  M68kCodeGen
+
+  ADD_TO_COMPONENT
+  M68k
+)

llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp

+//===---- M68kAsmParser.cpp - Parse M68k assembly to MCInst instructions --===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "M68kInstrInfo.h"
+#include "M68kRegisterInfo.h"
+#include "TargetInfo/M68kTargetInfo.h"
+
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
+#include "llvm/MC/MCParser/MCTargetAsmParser.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/Support/TargetRegistry.h"
+
+#include <sstream>
+
+#define DEBUG_TYPE "m68k-asm-parser"
+
+using namespace llvm;
+
+static cl::opt<bool> RegisterPrefixOptional(
+    "m68k-register-prefix-optional", cl::Hidden,
+    cl::desc("Enable specifying registers without the % prefix"),
+    cl::init(false));
+
+namespace {
+/// Parses M68k assembly from a stream.
+class M68kAsmParser : public MCTargetAsmParser {
+  const MCSubtargetInfo &STI;
+  MCAsmParser &Parser;
+  const MCRegisterInfo *MRI;
+
+#define GET_ASSEMBLER_HEADER
+#include "M68kGenAsmMatcher.inc"
+
+  // Helpers for Match&Emit.
+  bool invalidOperand(const SMLoc &Loc, const OperandVector &Operands,
+                      const uint64_t &ErrorInfo);
+  bool missingFeature(const SMLoc &Loc, const uint64_t &ErrorInfo);
+  bool emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const;
+  bool parseRegisterName(unsigned int &RegNo, SMLoc Loc,
+                         StringRef RegisterName);
+  OperandMatchResultTy parseRegister(unsigned int &RegNo);
+
+  // Parser functions.
+  void eatComma();
+
+  bool isExpr() const;
+  OperandMatchResultTy parseImm(OperandVector &Operands);
+  OperandMatchResultTy parseMemOp(OperandVector &Operands);
+
+public:
+  M68kAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
+                const MCInstrInfo &MII, const MCTargetOptions &Options)
+      : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
+    MCAsmParserExtension::Initialize(Parser);
+    MRI = getContext().getRegisterInfo();
+
+    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
+  }
+
+  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
+                                      unsigned Kind) override;
+  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
+  OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+                                        SMLoc &EndLoc) override;
+  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+                        SMLoc NameLoc, OperandVector &Operands) override;
+  bool ParseDirective(AsmToken DirectiveID) override;
+  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+                               OperandVector &Operands, MCStreamer &Out,
+                               uint64_t &ErrorInfo,
+                               bool MatchingInlineAsm) override;
+};
+
+struct M68kMemOp {
+  enum class Kind {
+    Addr,
+    Reg,
+    RegIndirect,
+    RegPostIncrement,
+    RegPreDecrement,
+    RegIndirectDisplacement,
+    RegIndirectDisplacementIndex,
+  };
+
+  // These variables are used for the following forms:
+  // Addr: (OuterDisp)
+  // Reg: %OuterReg
+  // RegIndirect: (%OuterReg)
+  // RegPostIncrement: (%OuterReg)+
+  // RegPreDecrement: -(%OuterReg)
+  // RegIndirectDisplacement: OuterDisp(%OuterReg)
+  // RegIndirectDisplacementIndex:
+  //   OuterDisp(%OuterReg, %InnerReg.Size * Scale, InnerDisp)
+
+  Kind Op;
+  unsigned OuterReg;
+  unsigned InnerReg;
+  const MCExpr *OuterDisp;
+  const MCExpr *InnerDisp;
+  uint8_t Size : 4;
+  uint8_t Scale : 4;
+  const MCExpr *Expr;
+
+  M68kMemOp() {}
+  M68kMemOp(Kind Op) : Op(Op) {}
+
+  void print(raw_ostream &OS) const;
+};
+
+/// An parsed M68k assembly operand.
+class M68kOperand : public MCParsedAsmOperand {
+  typedef MCParsedAsmOperand Base;
+
+  enum class Kind {
+    Invalid,
+    Token,
+    Imm,
+    MemOp,
+  };
+
+  Kind Kind;
+  SMLoc Start, End;
+  union {
+    StringRef Token;
+    int64_t Imm;
+    const MCExpr *Expr;
+    M68kMemOp MemOp;
+  };
+
+public:
+  M68kOperand(enum Kind Kind, SMLoc Start, SMLoc End)
+      : Base(), Kind(Kind), Start(Start), End(End) {}
+
+  SMLoc getStartLoc() const override { return Start; }
+  SMLoc getEndLoc() const override { return End; }
+
+  void print(raw_ostream &OS) const override;
+
+  bool isMem() const override { return false; }
+  bool isMemOp() const { return Kind == Kind::MemOp; }
+
+  static void addExpr(MCInst &Inst, const MCExpr *Expr);
+
+  // Reg
+  bool isReg() const override;
+  unsigned getReg() const override;
+  void addRegOperands(MCInst &Inst, unsigned N) const;
+
+  static std::unique_ptr<M68kOperand> createMemOp(M68kMemOp MemOp, SMLoc Start,
+                                                  SMLoc End);
+
+  // Token
+  bool isToken() const override;
+  StringRef getToken() const;
+  static std::unique_ptr<M68kOperand> createToken(StringRef Token, SMLoc Start,
+                                                  SMLoc End);
+
+  // Imm
+  bool isImm() const override;
+  void addImmOperands(MCInst &Inst, unsigned N) const;
+
+  static std::unique_ptr<M68kOperand> createImm(const MCExpr *Expr, SMLoc Start,
+                                                SMLoc End);
+
+  // Addr
+  bool isAddr() const;
+  void addAddrOperands(MCInst &Inst, unsigned N) const;
+
+  // ARI
+  bool isARI() const;
+  void addARIOperands(MCInst &Inst, unsigned N) const;
+
+  // ARID
+  bool isARID() const;
+  void addARIDOperands(MCInst &Inst, unsigned N) const;
+
+  // ARII
+  bool isARII() const;
+  void addARIIOperands(MCInst &Inst, unsigned N) const;
+
+  // ARIPD
+  bool isARIPD() const;
+  void addARIPDOperands(MCInst &Inst, unsigned N) const;
+
+  // ARIPI
+  bool isARIPI() const;
+  void addARIPIOperands(MCInst &Inst, unsigned N) const;
+
+  // PCD
+  bool isPCD() const;
+  void addPCDOperands(MCInst &Inst, unsigned N) const;
+
+  // PCI
+  bool isPCI() const;
+  void addPCIOperands(MCInst &Inst, unsigned N) const;
+};
+
+} // end anonymous namespace.
+
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kAsmParser() {
+  RegisterMCAsmParser<M68kAsmParser> X(getTheM68kTarget());
+}
+
+#define GET_MATCHER_IMPLEMENTATION
+#include "M68kGenAsmMatcher.inc"
+
+void M68kMemOp::print(raw_ostream &OS) const {
+  switch (Op) {
+  case Kind::Addr:
+    OS << OuterDisp;
+    break;
+  case Kind::Reg:
+    OS << '%' << OuterReg;
+    break;
+  case Kind::RegIndirect:
+    OS << "(%" << OuterReg << ')';
+    break;
+  case Kind::RegPostIncrement:
+    OS << "(%" << OuterReg << ")+";
+    break;
+  case Kind::RegPreDecrement:
+    OS << "-(%" << OuterReg << ")";
+    break;
+  case Kind::RegIndirectDisplacement:
+    OS << OuterDisp << "(%" << OuterReg << ")";
+    break;
+  case Kind::RegIndirectDisplacementIndex:
+    OS << OuterDisp << "(%" << OuterReg << ", " << InnerReg << "." << Size
+       << ", " << InnerDisp << ")";
+    break;
+  default:
+    llvm_unreachable("unknown MemOp kind");
+  }
+}
+
+void M68kOperand::addExpr(MCInst &Inst, const MCExpr *Expr) {
+  if (auto Const = dyn_cast<MCConstantExpr>(Expr)) {
+    Inst.addOperand(MCOperand::createImm(Const->getValue()));
+    return;
+  }
+
+  Inst.addOperand(MCOperand::createExpr(Expr));
+}
+
+// Reg
+bool M68kOperand::isReg() const {
+  return Kind == Kind::MemOp && MemOp.Op == M68kMemOp::Kind::Reg;
+}
+
+unsigned M68kOperand::getReg() const {
+  assert(isReg());
+  return MemOp.OuterReg;
+}
+
+void M68kOperand::addRegOperands(MCInst &Inst, unsigned N) const {
+  assert(isReg() && "wrong operand kind");
+  assert((N == 1) && "can only handle one register operand");
+
+  Inst.addOperand(MCOperand::createReg(getReg()));
+}
+
+std::unique_ptr<M68kOperand> M68kOperand::createMemOp(M68kMemOp MemOp,
+                                                      SMLoc Start, SMLoc End) {
+  auto Op = std::make_unique<M68kOperand>(Kind::MemOp, Start, End);
+  Op->MemOp = MemOp;
+  return Op;
+}
+
+// Token
+bool M68kOperand::isToken() const { return Kind == Kind::Token; }
+StringRef M68kOperand::getToken() const {
+  assert(isToken());
+  return Token;
+}
+
+std::unique_ptr<M68kOperand> M68kOperand::createToken(StringRef Token,
+                                                      SMLoc Start, SMLoc End) {
+  auto Op = std::make_unique<M68kOperand>(Kind::Token, Start, End);
+  Op->Token = Token;
+  return Op;
+}
+
+// Imm
+bool M68kOperand::isImm() const { return Kind == Kind::Imm; }
+void M68kOperand::addImmOperands(MCInst &Inst, unsigned N) const {
+  assert(isImm() && "wrong oeprand kind");
+  assert((N == 1) && "can only handle one register operand");
+
+  M68kOperand::addExpr(Inst, Expr);
+}
+
+std::unique_ptr<M68kOperand> M68kOperand::createImm(const MCExpr *Expr,
+                                                    SMLoc Start, SMLoc End) {
+  auto Op = std::make_unique<M68kOperand>(Kind::Imm, Start, End);
+  Op->Expr = Expr;
+  return Op;
+}
+
+// Addr
+bool M68kOperand::isAddr() const {
+  return isMemOp() && MemOp.Op == M68kMemOp::Kind::Addr;
+}
+void M68kOperand::addAddrOperands(MCInst &Inst, unsigned N) const {
+  M68kOperand::addExpr(Inst, MemOp.OuterDisp);
+}
+
+// ARI
+bool M68kOperand::isARI() const {
+  return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegIndirect &&
+         M68k::AR32RegClass.contains(MemOp.OuterReg);
+}
+void M68kOperand::addARIOperands(MCInst &Inst, unsigned N) const {
+  Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
+}
+
+// ARID
+bool M68kOperand::isARID() const {
+  return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegIndirectDisplacement &&
+         M68k::AR32RegClass.contains(MemOp.OuterReg);
+}
+void M68kOperand::addARIDOperands(MCInst &Inst, unsigned N) const {
+  M68kOperand::addExpr(Inst, MemOp.OuterDisp);
+  Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
+}
+
+// ARII
+bool M68kOperand::isARII() const {
+  return isMemOp() &&
+         MemOp.Op == M68kMemOp::Kind::RegIndirectDisplacementIndex &&
+         M68k::AR32RegClass.contains(MemOp.OuterReg);
+}
+void M68kOperand::addARIIOperands(MCInst &Inst, unsigned N) const {
+  M68kOperand::addExpr(Inst, MemOp.OuterDisp);
+  Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
+  Inst.addOperand(MCOperand::createReg(MemOp.InnerReg));
+}
+
+// ARIPD
+bool M68kOperand::isARIPD() const {
+  return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegPreDecrement &&
+         M68k::AR32RegClass.contains(MemOp.OuterReg);
+}
+void M68kOperand::addARIPDOperands(MCInst &Inst, unsigned N) const {
+  Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
+}
+
+// ARIPI
+bool M68kOperand::isARIPI() const {
+  return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegPostIncrement &&
+         M68k::AR32RegClass.contains(MemOp.OuterReg);
+}
+void M68kOperand::addARIPIOperands(MCInst &Inst, unsigned N) const {
+  Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
+}
+
+// PCD
+bool M68kOperand::isPCD() const {
+  return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegIndirectDisplacement &&
+         MemOp.OuterReg == M68k::PC;
+}
+void M68kOperand::addPCDOperands(MCInst &Inst, unsigned N) const {
+  M68kOperand::addExpr(Inst, MemOp.OuterDisp);
+}
+
+// PCI
+bool M68kOperand::isPCI() const {
+  return isMemOp() &&
+         MemOp.Op == M68kMemOp::Kind::RegIndirectDisplacementIndex &&
+         MemOp.OuterReg == M68k::PC;
+}
+void M68kOperand::addPCIOperands(MCInst &Inst, unsigned N) const {
+  M68kOperand::addExpr(Inst, MemOp.OuterDisp);
+  Inst.addOperand(MCOperand::createReg(MemOp.InnerReg));
+}
+
+static inline bool checkRegisterClass(unsigned RegNo, bool Data, bool Address,
+                                      bool SP) {
+  switch (RegNo) {
+  case M68k::A0:
+  case M68k::A1:
+  case M68k::A2:
+  case M68k::A3:
+  case M68k::A4:
+  case M68k::A5:
+  case M68k::A6:
+    return Address;
+
+  case M68k::SP:
+    return SP;
+
+  case M68k::D0:
+  case M68k::D1:
+  case M68k::D2:
+  case M68k::D3:
+  case M68k::D4:
+  case M68k::D5:
+  case M68k::D6:
+  case M68k::D7:
+    return Data;
+
+  case M68k::SR:
+  case M68k::CCR:
+    return false;
+
+  default:
+    llvm_unreachable("unexpected register type");
+    return false;
+  }
+}
+
+unsigned M68kAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
+                                                   unsigned Kind) {
+  M68kOperand &Operand = (M68kOperand &)Op;
+
+  switch (Kind) {
+  case MCK_XR16:
+  case MCK_SPILL:
+    if (Operand.isReg() &&
+        checkRegisterClass(Operand.getReg(), true, true, true)) {
+      return Match_Success;
+    }
+    break;
+
+  case MCK_AR16:
+  case MCK_AR32:
+    if (Operand.isReg() &&
+        checkRegisterClass(Operand.getReg(), false, true, true)) {
+      return Match_Success;
+    }
+    break;
+
+  case MCK_AR32_NOSP:
+    if (Operand.isReg() &&
+        checkRegisterClass(Operand.getReg(), false, true, false)) {
+      return Match_Success;
+    }
+    break;
+
+  case MCK_DR8:
+  case MCK_DR16:
+  case MCK_DR32:
+    if (Operand.isReg() &&
+        checkRegisterClass(Operand.getReg(), true, false, false)) {
+      return Match_Success;
+    }
+    break;
+
+  case MCK_AR16_TC:
+    if (Operand.isReg() &&
+        ((Operand.getReg() == M68k::A0) || (Operand.getReg() == M68k::A1))) {
+      return Match_Success;
+    }
+    break;
+
+  case MCK_DR16_TC:
+    if (Operand.isReg() &&
+        ((Operand.getReg() == M68k::D0) || (Operand.getReg() == M68k::D1))) {
+      return Match_Success;
+    }
+    break;
+
+  case MCK_XR16_TC:
+    if (Operand.isReg() &&
+        ((Operand.getReg() == M68k::D0) || (Operand.getReg() == M68k::D1) ||
+         (Operand.getReg() == M68k::A0) || (Operand.getReg() == M68k::A1))) {
+      return Match_Success;
+    }
+    break;
+  }
+
+  return Match_InvalidOperand;
+}
+
+bool M68kAsmParser::parseRegisterName(unsigned &RegNo, SMLoc Loc,
+                                      StringRef RegisterName) {
+  auto RegisterNameLower = RegisterName.lower();
+
+  // Parse simple general-purpose registers.
+  if (RegisterNameLower.size() == 2) {
+    static unsigned RegistersByIndex[] = {
+        M68k::D0, M68k::D1, M68k::D2, M68k::D3, M68k::D4, M68k::D5,
+        M68k::D6, M68k::D7, M68k::A0, M68k::A1, M68k::A2, M68k::A3,
+        M68k::A4, M68k::A5, M68k::A6, M68k::SP,
+    };
+
+    switch (RegisterNameLower[0]) {
+    case 'd':
+    case 'a': {
+      if (isdigit(RegisterNameLower[1])) {
+        unsigned IndexOffset = (RegisterNameLower[0] == 'a') ? 8 : 0;
+        unsigned RegIndex = (unsigned)(RegisterNameLower[1] - '0');
+        if (RegIndex < 8) {
+          RegNo = RegistersByIndex[IndexOffset + RegIndex];
+          return true;
+        }
+      }
+      break;
+    }
+
+    case 'c':
+      if (RegisterNameLower[1] == 'c' && RegisterNameLower[2] == 'r') {
+        RegNo = M68k::CCR;
+        return true;
+      }
+      break;
+
+    case 's':
+      if (RegisterNameLower[1] == 'p') {
+        RegNo = M68k::SP;
+        return true;
+      } else if (RegisterNameLower[1] == 'r') {
+        RegNo = M68k::SR;
+        return true;
+      }
+      break;
+
+    case 'p':
+      if (RegisterNameLower[1] == 'c') {
+        RegNo = M68k::PC;
+        return true;
+      }
+      break;
+    }
+  }
+
+  return false;
+}
+
+OperandMatchResultTy M68kAsmParser::parseRegister(unsigned &RegNo) {
+  bool HasPercent = false;
+  AsmToken PercentToken;
+
+  LLVM_DEBUG(dbgs() << "parseRegister "; getTok().dump(dbgs()); dbgs() << "\n");
+
+  if (getTok().is(AsmToken::Percent)) {
+    HasPercent = true;
+    PercentToken = Lex();
+  } else if (!RegisterPrefixOptional.getValue()) {
+    return MatchOperand_NoMatch;
+  }
+
+  if (!Parser.getTok().is(AsmToken::Identifier)) {
+    if (HasPercent) {
+      getLexer().UnLex(PercentToken);
+    }
+    return MatchOperand_NoMatch;
+  }
+
+  auto RegisterName = Parser.getTok().getString();
+  if (!parseRegisterName(RegNo, Parser.getLexer().getLoc(), RegisterName)) {
+    if (HasPercent) {
+      getLexer().UnLex(PercentToken);
+    }
+    return MatchOperand_NoMatch;
+  }
+
+  Parser.Lex();
+  return MatchOperand_Success;
+}
+
+bool M68kAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+                                  SMLoc &EndLoc) {
+  auto Result = tryParseRegister(RegNo, StartLoc, EndLoc);
+  if (Result != MatchOperand_Success) {
+    return Error(StartLoc, "expected register");
+  }
+
+  return false;
+}
+
+OperandMatchResultTy M68kAsmParser::tryParseRegister(unsigned &RegNo,
+                                                     SMLoc &StartLoc,
+                                                     SMLoc &EndLoc) {
+  StartLoc = getLexer().getLoc();
+  auto Result = parseRegister(RegNo);
+  EndLoc = getLexer().getLoc();
+  return Result;
+}
+
+bool M68kAsmParser::isExpr() const {
+  switch (Parser.getTok().getKind()) {
+  case AsmToken::Identifier:
+  case AsmToken::Integer:
+    return true;
+
+  default:
+    return false;
+  }
+}
+
+OperandMatchResultTy M68kAsmParser::parseImm(OperandVector &Operands) {
+  if (getLexer().isNot(AsmToken::Hash)) {
+    return MatchOperand_NoMatch;
+  }
+  SMLoc Start = getLexer().getLoc();
+  Parser.Lex();
+
+  SMLoc End;
+  const MCExpr *Expr;
+
+  if (getParser().parseExpression(Expr, End)) {
+    return MatchOperand_ParseFail;
+  }
+
+  Operands.push_back(M68kOperand::createImm(Expr, Start, End));
+  return MatchOperand_Success;
+}
+
+OperandMatchResultTy M68kAsmParser::parseMemOp(OperandVector &Operands) {
+  SMLoc Start = getLexer().getLoc();
+  bool IsPD = false;
+  M68kMemOp MemOp;
+
+  // Check for a plain register.
+  auto Result = parseRegister(MemOp.OuterReg);
+  if (Result == MatchOperand_Success) {
+    MemOp.Op = M68kMemOp::Kind::Reg;
+    Operands.push_back(
+        M68kOperand::createMemOp(MemOp, Start, getLexer().getLoc()));
+    return MatchOperand_Success;
+  }
+
+  if (Result == MatchOperand_ParseFail) {
+    return Result;
+  }
+
+  // Check for pre-decrement & outer displacement.
+  bool HasDisplacement = false;
+  if (getLexer().is(AsmToken::Minus)) {
+    IsPD = true;
+    Parser.Lex();
+  } else if (isExpr()) {
+    if (Parser.parseExpression(MemOp.OuterDisp)) {
+      return MatchOperand_ParseFail;
+    }
+    HasDisplacement = true;
+  }
+
+  if (getLexer().isNot(AsmToken::LParen)) {
+    if (HasDisplacement) {
+      MemOp.Op = M68kMemOp::Kind::Addr;
+      Operands.push_back(
+          M68kOperand::createMemOp(MemOp, Start, getLexer().getLoc()));
+      return MatchOperand_Success;
+    } else if (IsPD) {
+      Error(getLexer().getLoc(), "expected (");
+      return MatchOperand_ParseFail;
+    }
+
+    return MatchOperand_NoMatch;
+  }
+  Parser.Lex();
+
+  // Check for constant dereference & MIT-style displacement
+  if (!HasDisplacement && isExpr()) {
+    if (Parser.parseExpression(MemOp.OuterDisp)) {
+      return MatchOperand_ParseFail;
+    }
+    HasDisplacement = true;
+
+    // If we're not followed by a comma, we're a constant dereference.
+    if (getLexer().isNot(AsmToken::Comma)) {
+      MemOp.Op = M68kMemOp::Kind::Addr;
+      Operands.push_back(
+          M68kOperand::createMemOp(MemOp, Start, getLexer().getLoc()));
+      return MatchOperand_Success;
+    }
+
+    Parser.Lex();
+  }
+
+  Result = parseRegister(MemOp.OuterReg);
+  if (Result == MatchOperand_ParseFail) {
+    return MatchOperand_ParseFail;
+  }
+
+  if (Result != MatchOperand_Success) {
+    Error(getLexer().getLoc(), "expected register");
+    return MatchOperand_ParseFail;
+  }
+
+  // Check for Index.
+  bool HasIndex = false;
+  if (Parser.getTok().is(AsmToken::Comma)) {
+    Parser.Lex();
+
+    Result = parseRegister(MemOp.InnerReg);
+    if (Result == MatchOperand_ParseFail) {
+      return Result;
+    }
+
+    if (Result == MatchOperand_NoMatch) {
+      Error(getLexer().getLoc(), "expected register");
+      return MatchOperand_ParseFail;
+    }
+
+    // TODO: parse size, scale and inner displacement.
+    MemOp.Size = 4;
+    MemOp.Scale = 1;
+    MemOp.InnerDisp = MCConstantExpr::create(0, Parser.getContext(), true, 4);
+    HasIndex = true;
+  }
+
+  if (Parser.getTok().isNot(AsmToken::RParen)) {
+    Error(getLexer().getLoc(), "expected )");
+    return MatchOperand_ParseFail;
+  }
+  Parser.Lex();
+
+  bool IsPI = false;
+  if (!IsPD && Parser.getTok().is(AsmToken::Plus)) {
+    Parser.Lex();
+    IsPI = true;
+  }
+
+  SMLoc End = getLexer().getLoc();
+
+  unsigned OpCount = IsPD + IsPI + (HasIndex || HasDisplacement);
+  if (OpCount > 1) {
+    Error(Start, "only one of post-increment, pre-decrement or displacement "
+                 "can be used");
+    return MatchOperand_ParseFail;
+  }
+
+  if (IsPD) {
+    MemOp.Op = M68kMemOp::Kind::RegPreDecrement;
+  } else if (IsPI) {
+    MemOp.Op = M68kMemOp::Kind::RegPostIncrement;
+  } else if (HasIndex) {
+    MemOp.Op = M68kMemOp::Kind::RegIndirectDisplacementIndex;
+  } else if (HasDisplacement) {
+    MemOp.Op = M68kMemOp::Kind::RegIndirectDisplacement;
+  } else {
+    MemOp.Op = M68kMemOp::Kind::RegIndirect;
+  }
+
+  Operands.push_back(M68kOperand::createMemOp(MemOp, Start, End));
+  return MatchOperand_Success;
+}
+
+void M68kAsmParser::eatComma() {
+  if (Parser.getTok().is(AsmToken::Comma)) {
+    Parser.Lex();
+  }
+}
+
+bool M68kAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+                                     SMLoc NameLoc, OperandVector &Operands) {
+  SMLoc Start = getLexer().getLoc();
+  Operands.push_back(M68kOperand::createToken(Name, Start, Start));
+
+  bool First = true;
+  while (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
+    if (!First) {
+      eatComma();
+    } else {
+      First = false;
+    }
+
+    auto MatchResult = MatchOperandParserImpl(Operands, Name);
+    if (MatchResult == MatchOperand_Success) {
+      continue;
+    }
+
+    // Add custom operand formats here...
+    SMLoc Loc = getLexer().getLoc();
+    Parser.eatToEndOfStatement();
+    return Error(Loc, "unexpected token parsing operands");
+  }
+
+  // Eat EndOfStatement.
+  Parser.Lex();
+  return false;
+}
+
+bool M68kAsmParser::ParseDirective(AsmToken DirectiveID) { return true; }
+
+bool M68kAsmParser::invalidOperand(SMLoc const &Loc,
+                                   OperandVector const &Operands,
+                                   uint64_t const &ErrorInfo) {
+  SMLoc ErrorLoc = Loc;
+  char const *Diag = 0;
+
+  if (ErrorInfo != ~0U) {
+    if (ErrorInfo >= Operands.size()) {
+      Diag = "too few operands for instruction.";
+    } else {
+      auto const &Op = (M68kOperand const &)*Operands[ErrorInfo];
+      if (Op.getStartLoc() != SMLoc()) {
+        ErrorLoc = Op.getStartLoc();
+      }
+    }
+  }
+
+  if (!Diag) {
+    Diag = "invalid operand for instruction";
+  }
+
+  return Error(ErrorLoc, Diag);
+}
+
+bool M68kAsmParser::missingFeature(llvm::SMLoc const &Loc,
+                                   uint64_t const &ErrorInfo) {
+  return Error(Loc, "instruction requires a CPU feature not currently enabled");
+}
+
+bool M68kAsmParser::emit(MCInst &Inst, SMLoc const &Loc,
+                         MCStreamer &Out) const {
+  Inst.setLoc(Loc);
+  Out.emitInstruction(Inst, STI);
+
+  return false;
+}
+
+bool M68kAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
+                                            OperandVector &Operands,
+                                            MCStreamer &Out,
+                                            uint64_t &ErrorInfo,
+                                            bool MatchingInlineAsm) {
+  MCInst Inst;
+  unsigned MatchResult =
+      MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
+
+  switch (MatchResult) {
+  case Match_Success:
+    return emit(Inst, Loc, Out);
+  case Match_MissingFeature:
+    return missingFeature(Loc, ErrorInfo);
+  case Match_InvalidOperand:
+    return invalidOperand(Loc, Operands, ErrorInfo);
+  case Match_MnemonicFail:
+    return Error(Loc, "invalid instruction");
+  default:
+    return true;
+  }
+}
+
+void M68kOperand::print(raw_ostream &OS) const {
+  switch (Kind) {
+  case Kind::Invalid:
+    OS << "invalid";
+    break;
+
+  case Kind::Token:
+    OS << "token '" << Token << "'";
+    break;
+
+  case Kind::Imm:
+    OS << "immediate " << Imm;
+    break;
+
+  case Kind::MemOp:
+    MemOp.print(OS);
+    break;
+
+  default:
+    llvm_unreachable("unhandled operand kind");
+  }
+}

llvm/lib/Target/M68k/CMakeLists.txt

 add_llvm_component_group(M68k)
 
 set(LLVM_TARGET_DEFINITIONS M68k.td)
 
 tablegen(LLVM M68kGenRegisterInfo.inc     -gen-register-info)
 tablegen(LLVM M68kGenInstrInfo.inc        -gen-instr-info)
 tablegen(LLVM M68kGenSubtargetInfo.inc    -gen-subtarget)
 tablegen(LLVM M68kGenMCCodeBeads.inc      -gen-code-beads)
 tablegen(LLVM M68kGenMCPseudoLowering.inc -gen-pseudo-lowering)
 tablegen(LLVM M68kGenDAGISel.inc          -gen-dag-isel)
 tablegen(LLVM M68kGenCallingConv.inc      -gen-callingconv)
 tablegen(LLVM M68kGenAsmWriter.inc        -gen-asm-writer)
+tablegen(LLVM M68kGenAsmMatcher.inc       -gen-asm-matcher)
 
 add_public_tablegen_target(M68kCommonTableGen)
 
 add_llvm_target(M68kCodeGen
   M68kAsmPrinter.cpp
   M68kCollapseMOVEMPass.cpp
   M68kExpandPseudo.cpp
   M68kFrameLowering.cpp
add_llvm_target(M68kCodeGen
   M68kInfo
 
   ADD_TO_COMPONENT
   M68k
 )
 
 add_subdirectory(TargetInfo)
 add_subdirectory(MCTargetDesc)
+add_subdirectory(AsmParser)

llvm/lib/Target/M68k/M68k.td

 def M68kInstrInfo : InstrInfo;
 
 //===----------------------------------------------------------------------===//
 // Calling Conventions
 //===----------------------------------------------------------------------===//
 
 include "M68kCallingConv.td"
 
+//===---------------------------------------------------------------------===//
+// Assembly Printers
+//===---------------------------------------------------------------------===//
+
+def M68kAsmWriter : AsmWriter {
+ string AsmWriterClassName = "InstPrinter";
+ bit isMCAsmWriter = 1;
+}
+
+//===---------------------------------------------------------------------===//
+// Assembly Parsers
+//===---------------------------------------------------------------------===//
+
+def M68kAsmParser : AsmParser {
+  let ShouldEmitMatchRegisterName = 0;
+  let ShouldEmitMatchRegisterAltName = 0;
+}
+
+def M68kAsmParserVariant : AsmParserVariant {
+  int Variant = 0;
+}
+
 //===----------------------------------------------------------------------===//
 // Target
 //===----------------------------------------------------------------------===//
 
 def M68k : Target {
   let InstructionSet = M68kInstrInfo;
+  let AssemblyParsers = [M68kAsmParser];
+  let AssemblyWriters = [M68kAsmWriter];
 }

llvm/lib/Target/M68k/M68kInstrInfo.td

class MxSize<int num, string id, string full> {
   string Id = id;
   string Full = full;
 }
 
 def MxSize8  : MxSize<8,  "b", "byte">;
 def MxSize16 : MxSize<16, "w", "word">;
 def MxSize32 : MxSize<32, "l", "long">;
 
+class MxOpClass<string name> : AsmOperandClass {
+  let Name = name;
+  let ParserMethod = "parseMemOp";
+}
+
+def MxRegClass : MxOpClass<"Reg">;
+
 class MxOperand<ValueType vt, MxSize size, string letter, RegisterClass rc, dag pat = (null_frag)> {
   ValueType VT = vt;
   string Letter = letter;
   MxSize Size = size;
   RegisterClass RC = rc;
   dag Pat = pat;
 }
 
 class MxRegOp<ValueType vt,
               RegisterClass rc,
               MxSize size,
               string letter,
               string pm = "printOperand">
     : RegisterOperand<rc, pm>,
-      MxOperand<vt, size, letter, rc>;
+      MxOperand<vt, size, letter, rc> {
+  let ParserMatchClass = MxRegClass;
+}
 
 // REGISTER DIRECT. The operand is in the data register specified by
 // the effective address register field.
 def MxXRD16 : MxRegOp<i16, XR16, MxSize16, "r">;
 def MxXRD32 : MxRegOp<i32, XR32, MxSize32, "r">;
 
 def MxXRD16_TC : MxRegOp<i16, XR16_TC, MxSize16, "r">;
 def MxXRD32_TC : MxRegOp<i32, XR32_TC, MxSize32, "r">;

 // ADDRESS REGISTER DIRECT. The operand is in the address register specified by
 // the effective address register field.
 def MxARD16 : MxRegOp<i16, AR16, MxSize16, "a">;
 def MxARD32 : MxRegOp<i32, AR32, MxSize32, "a">;
 
 def MxARD16_TC : MxRegOp<i16, AR16_TC, MxSize16, "a">;
 def MxARD32_TC : MxRegOp<i32, AR32_TC, MxSize32, "a">;
 
-class MxOpClass<string name> : AsmOperandClass {
-  let Name = name;
-  let ParserMethod = "parse"#name;
-}
-
 class MxMemOp<dag ops, MxSize size, string letter,
               string printMethod = "printOperand",
               AsmOperandClass parserMatchClass = ImmAsmOperand>
     : Operand<iPTR>, MxOperand<iPTR, size, letter, ?> {
   let PrintMethod = printMethod;
   let MIOperandInfo = ops;
   let ParserMatchClass = parserMatchClass;
   let OperandType = "OPERAND_MEMORY";

 // word, and the contents of the index register.  The value in the program
 // counter is the address of the extension word. This reference is classified as
 // a program reference.
 def MxPCI8   : MxMemOp<(ops i8imm, XR32), MxSize8,  "k", "printPCI8Mem", MxPCI>;
 def MxPCI16  : MxMemOp<(ops i8imm, XR32), MxSize16, "k", "printPCI16Mem", MxPCI>;
 def MxPCI32  : MxMemOp<(ops i8imm, XR32), MxSize32, "k", "printPCI32Mem", MxPCI>;
 } // OPERAND_PCREL
 
-def MxImm : MxOpClass<"MxImm">;
+def MxImm : AsmOperandClass {
+  let Name = "MxImm";
+  let PredicateMethod = "isImm";
+  let RenderMethod = "addImmOperands";
+  let ParserMethod = "parseImm";
+}
 
 class MxOp<ValueType vt, MxSize size, string letter>
     : Operand<vt>,
       MxOperand<vt, size, letter, ?> {
   let ParserMatchClass = MxImm;
 }
 
 let OperandType = "OPERAND_IMMEDIATE",
     PrintMethod = "printImmediate" in {
 // IMMEDIATE DATA. This addressing mode requires either one or two words of
 // extension depending on the size of the operation.
 //     Byte Operation - operand is low order byte of extension word
 //     Word Operation - operand is extension word
 //     Long Word Operation - operand is in the two extension words,
 //                           high order 16 bits are in the first
 //                           extension word, low order 16 bits are
 //                           in the second extension word.
 def Mxi8imm  : MxOp<i8,  MxSize8,  "i">;
 def Mxi16imm : MxOp<i16, MxSize16, "i">;
 def Mxi32imm : MxOp<i32, MxSize32, "i">;
 } // OPERAND_IMMEDIATE
 
 let OperandType = "OPERAND_PCREL",
-    ParserMatchClass = MxImm,
+    ParserMatchClass = MxAddr,
     PrintMethod = "printPCRelImm" in {
 
 // Branch targets have OtherVT type and print as pc-relative values.
 def MxBrTarget8  : Operand<OtherVT>;
 def MxBrTarget16 : Operand<OtherVT>;
 def MxBrTarget32 : Operand<OtherVT>;
 
 } // OPERAND_PCREL
 
 // Used with MOVEM
 def MxMoveMask : MxOp<i16, MxSize16, "m"> {
   let OperandType = "OPERAND_IMMEDIATE";
   let PrintMethod = "printMoveMask";
 }
 
-
 //===----------------------------------------------------------------------===//
 // Predicates
 //===----------------------------------------------------------------------===//
 
 def SmallCode    : Predicate<"TM.getCodeModel() == CodeModel::Small">;
 def KernelCode   : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
 def FarData      : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
                              "TM.getCodeModel() != CodeModel::Kernel">;

llvm/test/MC/M68k/instructions.s

+; RUN: llvm-mc -triple m68k -show-encoding -motorola-integers %s | FileCheck %s
+
+; At the moment, all encoding tests for M68k live in llvm/test/CodeGen/M68k/.
+; This is the first test included as part of the AsmMatcher and lacks encoding checks.
+; The current migration plan is to consolidate all of the encoding tests in this
+; directory along with AsmMatcher/ Disassembler tests like the other platforms.
+; For more information and status updates see bug #49865.
+
+.global ext_fn
+
+; CHECK: move.l %a1, %a0
+move.l %a1, %a0
+; CHECK: add.l %a0, %a1
+add.l %a0, %a1
+; CHECK: addx.l %d1, %d2
+addx.l %d1, %d2
+; CHECK: sub.w #4, %d1
+sub.w #4, %d1
+; CHECK: cmp.w %a0, %d0
+cmp.w %a0, %d0
+; CHECK: neg.w %d0
+neg.w %d0
+; CHECK: btst #8, %d3
+btst #$8, %d3
+; CHECK: bra ext_fn
+bra ext_fn
+; CHECK: jsr ext_fn
+jsr ext_fn
+; CHECK: seq %d0
+seq %d0
+; CHECK: sgt %d0
+sgt %d0
+; CHECK: lea (80,%a0), %a1
+lea $50(%a0), %a1
+; CHECK: lsl.l #8, %a1
+lsl.l #8, %a1
+; CHECK: lsr.l #8, %a1
+lsr.l #8, %a1
+; CHECK: asr.l #8, %a1
+asr.l #8, %a1
+; CHECK: rol.l #8, %a1
+rol.l #8, %a1
+; CHECK: ror.l #8, %a1
+ror.l #8, %a1
+; CHECK: nop
+nop
+; CHECK: rts
+rts

llvm/test/MC/M68k/lit.local.cfg

+if not 'M68k' in config.root.targets:
+    config.unsupported = True