Diff 326967

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines	CallLowering::setArgFlags<Function>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
const DataLayout &DL,		const DataLayout &DL,
const Function &FuncInfo) const;		const Function &FuncInfo) const;

template void		template void
CallLowering::setArgFlags<CallBase>(CallLowering::ArgInfo &Arg, unsigned OpIdx,		CallLowering::setArgFlags<CallBase>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
const DataLayout &DL,		const DataLayout &DL,
const CallBase &FuncInfo) const;		const CallBase &FuncInfo) const;

Register CallLowering::packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy,		Register CallLowering::packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy,
		aemersonUnsubmitted Not Done Reply Inline Actions This was done in the other patch? aemerson: This was done in the other patch?
MachineIRBuilder &MIRBuilder) const {		MachineIRBuilder &MIRBuilder) const {
assert(SrcRegs.size() > 1 && "Nothing to pack");		assert(SrcRegs.size() > 1 && "Nothing to pack");

const DataLayout &DL = MIRBuilder.getMF().getDataLayout();		const DataLayout &DL = MIRBuilder.getMF().getDataLayout();
MachineRegisterInfo *MRI = MIRBuilder.getMRI();		MachineRegisterInfo *MRI = MIRBuilder.getMRI();

LLT PackedLLT = getLLTForType(*PackedTy, DL);		LLT PackedLLT = getLLTForType(*PackedTy, DL);

Show All 40 Lines	mergeVectorRegsToResultRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs,
// Deal with v3s16 split into v2s16		// Deal with v3s16 split into v2s16
LLT LCMTy = getLCMType(LLTy, PartLLT);		LLT LCMTy = getLCMType(LLTy, PartLLT);
if (LCMTy == LLTy) {		if (LCMTy == LLTy) {
// Common case where no padding is needed.		// Common case where no padding is needed.
assert(DstRegs.size() == 1);		assert(DstRegs.size() == 1);
return B.buildConcatVectors(DstRegs[0], SrcRegs);		return B.buildConcatVectors(DstRegs[0], SrcRegs);
}		}

		Register UnmergeSrcReg;
		if (LCMTy != PartLLT) {
const int NumWide = LCMTy.getSizeInBits() / PartLLT.getSizeInBits();		const int NumWide = LCMTy.getSizeInBits() / PartLLT.getSizeInBits();
Register Undef = B.buildUndef(PartLLT).getReg(0);		Register Undef = B.buildUndef(PartLLT).getReg(0);
		aemersonUnsubmitted Not Done Reply Inline Actions An example in a comment would be helpful here. aemerson: An example in a comment would be helpful here.

// Build vector of undefs.		// Build vector of undefs.
SmallVector<Register, 8> WidenedSrcs(NumWide, Undef);		SmallVector<Register, 8> WidenedSrcs(NumWide, Undef);

// Replace the first sources with the real registers.		// Replace the first sources with the real registers.
std::copy(SrcRegs.begin(), SrcRegs.end(), WidenedSrcs.begin());		std::copy(SrcRegs.begin(), SrcRegs.end(), WidenedSrcs.begin());
		UnmergeSrcReg = B.buildConcatVectors(LCMTy, WidenedSrcs).getReg(0);
		} else {
		// Handle widening a smaller vector to larger only.
		assert(SrcRegs.size() == 1);
		UnmergeSrcReg = SrcRegs[0];
		}

auto Widened = B.buildConcatVectors(LCMTy, WidenedSrcs);
int NumDst = LCMTy.getSizeInBits() / LLTy.getSizeInBits();		int NumDst = LCMTy.getSizeInBits() / LLTy.getSizeInBits();
		aemersonUnsubmitted Not Done Reply Inline Actions dead1 shouldn't be here? aemerson: dead1 shouldn't be here?

SmallVector<Register, 8> PadDstRegs(NumDst);		SmallVector<Register, 8> PadDstRegs(NumDst);
std::copy(DstRegs.begin(), DstRegs.end(), PadDstRegs.begin());		std::copy(DstRegs.begin(), DstRegs.end(), PadDstRegs.begin());

// Create the excess dead defs for the unmerge.		// Create the excess dead defs for the unmerge.
for (int I = DstRegs.size(); I != NumDst; ++I)		for (int I = DstRegs.size(); I != NumDst; ++I)
PadDstRegs[I] = MRI.createGenericVirtualRegister(LLTy);		PadDstRegs[I] = MRI.createGenericVirtualRegister(LLTy);

return B.buildUnmerge(PadDstRegs, Widened);		return B.buildUnmerge(PadDstRegs, UnmergeSrcReg);
}		}

/// Create a sequence of instructions to combine pieces split into register		/// Create a sequence of instructions to combine pieces split into register
/// typed values to the original IR value. \p OrigRegs contains the destination		/// typed values to the original IR value. \p OrigRegs contains the destination
/// value registers of type \p LLTy, and \p Regs contains the legalized pieces		/// value registers of type \p LLTy, and \p Regs contains the legalized pieces
/// with type \p PartLLT.		/// with type \p PartLLT.
static void buildCopyToParts(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,		static void buildCopyToParts(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,
ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT) {		ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT) {
MachineRegisterInfo &MRI = *B.getMRI();		MachineRegisterInfo &MRI = *B.getMRI();

		// We could just insert a regular copy, but this is unreachable at the moment.
		assert(LLTy != PartLLT && "identical part types shouldn't reach here");

		if (PartLLT.isVector() == LLTy.isVector() &&
		PartLLT.getScalarSizeInBits() > LLTy.getScalarSizeInBits()) {
		assert(OrigRegs.size() == 1 && Regs.size() == 1);
		B.buildTrunc(OrigRegs[0], Regs[0]);
		return;
		}

if (!LLTy.isVector() && !PartLLT.isVector()) {		if (!LLTy.isVector() && !PartLLT.isVector()) {
assert(OrigRegs.size() == 1);		assert(OrigRegs.size() == 1);
LLT OrigTy = MRI.getType(OrigRegs[0]);		LLT OrigTy = MRI.getType(OrigRegs[0]);

unsigned SrcSize = PartLLT.getSizeInBits() * Regs.size();		unsigned SrcSize = PartLLT.getSizeInBits() * Regs.size();
if (SrcSize == OrigTy.getSizeInBits())		if (SrcSize == OrigTy.getSizeInBits())
B.buildMerge(OrigRegs[0], Regs);		B.buildMerge(OrigRegs[0], Regs);
else {		else {
auto Widened = B.buildMerge(LLT::scalar(SrcSize), Regs);		auto Widened = B.buildMerge(LLT::scalar(SrcSize), Regs);
B.buildTrunc(OrigRegs[0], Widened);		B.buildTrunc(OrigRegs[0], Widened);
}		}

return;		return;
}		}

if (LLTy.isVector() && PartLLT.isVector()) {		if (PartLLT.isVector()) {
assert(OrigRegs.size() == 1);		assert(OrigRegs.size() == 1 &&
assert(LLTy.getElementType() == PartLLT.getElementType());		LLTy.getScalarType() == PartLLT.getElementType());
mergeVectorRegsToResultRegs(B, OrigRegs, Regs);		mergeVectorRegsToResultRegs(B, OrigRegs, Regs);
return;		return;
}		}

assert(LLTy.isVector() && !PartLLT.isVector());		assert(LLTy.isVector() && !PartLLT.isVector());

LLT DstEltTy = LLTy.getElementType();		LLT DstEltTy = LLTy.getElementType();

Show All 33 Lines	if (DstEltTy == PartLLT) {
// Vector was split, and elements promoted to a wider type.		// Vector was split, and elements promoted to a wider type.
// FIXME: Should handle floating point promotions.		// FIXME: Should handle floating point promotions.
LLT BVType = LLT::vector(LLTy.getNumElements(), PartLLT);		LLT BVType = LLT::vector(LLTy.getNumElements(), PartLLT);
auto BV = B.buildBuildVector(BVType, Regs);		auto BV = B.buildBuildVector(BVType, Regs);
B.buildTrunc(OrigRegs[0], BV);		B.buildTrunc(OrigRegs[0], BV);
}		}
}		}

		static void buildCopyFromParts(MachineIRBuilder &B, ArrayRef<Register> DstRegs,
		aemersonUnsubmitted Not Done Reply Inline Actions Document this? aemerson: Document this?
		Register SrcReg, LLT SrcTy, LLT PartTy) {
		// We could just insert a regular copy, but this is unreachable at the moment.
		assert(SrcTy != PartTy && "identical part types shouldn't reach here");

		const unsigned PartSize = PartTy.getSizeInBits();

		if (PartTy.isVector() == SrcTy.isVector() &&
		PartTy.getScalarSizeInBits() > SrcTy.getScalarSizeInBits()) {
		assert(DstRegs.size() == 1);
		B.buildAnyExt(DstRegs[0], SrcReg);
		return;
		}

		if (SrcTy.isVector() && !PartTy.isVector() &&
		PartSize > SrcTy.getElementType().getSizeInBits()) {
		// Vector was scalarized, and the elements extended.
		auto UnmergeToEltTy = B.buildUnmerge(SrcTy.getElementType(), SrcReg);
		for (int i = 0, e = DstRegs.size(); i != e; ++i)
		Lint: Pre-merge checks Inline Actions clang-tidy: warning: invalid case style for variable 'i' [readability-identifier-naming] not useful clang-tidy: warning: invalid case style for variable 'e' [readability-identifier-naming] not useful Lint: Pre-merge checks: clang-tidy: warning: invalid case style for variable 'i' [readability-identifier-naming]…
		B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i));
		return;
		}

		LLT GCDTy = getGCDType(SrcTy, PartTy);
		if (GCDTy == PartTy) {
		// If this already evenly divisible, we can create a simple unmerge.
		B.buildUnmerge(DstRegs, SrcReg);
		return;
		}

		MachineRegisterInfo &MRI = *B.getMRI();
		LLT DstTy = MRI.getType(DstRegs[0]);
		LLT LCMTy = getLCMType(SrcTy, PartTy);

		const unsigned LCMSize = LCMTy.getSizeInBits();
		const unsigned DstSize = DstTy.getSizeInBits();
		const unsigned SrcSize = SrcTy.getSizeInBits();

		Register UnmergeSrc = SrcReg;
		if (LCMSize != SrcSize) {
		// Widen to the common type.
		Register Undef = B.buildUndef(SrcTy).getReg(0);
		SmallVector<Register, 8> MergeParts(1, SrcReg);
		for (unsigned Size = SrcSize; Size != LCMSize; Size += SrcSize)
		MergeParts.push_back(Undef);

		UnmergeSrc = B.buildMerge(LCMTy, MergeParts).getReg(0);
		}

		// Unmerge to the original registers and pad with dead defs.
		SmallVector<Register, 8> UnmergeResults(DstRegs.begin(), DstRegs.end());
		for (unsigned Size = DstSize * DstRegs.size(); Size != LCMSize;
		Size += DstSize) {
		UnmergeResults.push_back(MRI.createGenericVirtualRegister(DstTy));
		}

		B.buildUnmerge(UnmergeResults, UnmergeSrc);
		}

bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,		bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,
SmallVectorImpl<ArgInfo> &Args,		SmallVectorImpl<ArgInfo> &Args,
ValueHandler &Handler,		ValueHandler &Handler,
CallingConv::ID CallConv, bool IsVarArg,		CallingConv::ID CallConv, bool IsVarArg,
Register ThisReturnReg) const {		Register ThisReturnReg) const {
MachineFunction &MF = MIRBuilder.getMF();		MachineFunction &MF = MIRBuilder.getMF();
const Function &F = MF.getFunction();		const Function &F = MF.getFunction();
SmallVector<CCValAssign, 16> ArgLocs;		SmallVector<CCValAssign, 16> ArgLocs;

CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, F.getContext());		CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, F.getContext());
return handleAssignments(CCInfo, ArgLocs, MIRBuilder, Args, Handler,		return handleAssignments(CCInfo, ArgLocs, MIRBuilder, Args, Handler,
ThisReturnReg);		ThisReturnReg);
}		}

bool CallLowering::handleAssignments(CCState &CCInfo,		bool CallLowering::handleAssignments(CCState &CCInfo,
SmallVectorImpl<CCValAssign> &ArgLocs,		SmallVectorImpl<CCValAssign> &ArgLocs,
MachineIRBuilder &MIRBuilder,		MachineIRBuilder &MIRBuilder,
SmallVectorImpl<ArgInfo> &Args,		SmallVectorImpl<ArgInfo> &Args,
ValueHandler &Handler,		ValueHandler &Handler,
Register ThisReturnReg) const {		Register ThisReturnReg) const {
MachineFunction &MF = MIRBuilder.getMF();		MachineFunction &MF = MIRBuilder.getMF();
		MachineRegisterInfo &MRI = MF.getRegInfo();
const Function &F = MF.getFunction();		const Function &F = MF.getFunction();
const DataLayout &DL = F.getParent()->getDataLayout();		const DataLayout &DL = F.getParent()->getDataLayout();

unsigned NumArgs = Args.size();		unsigned NumArgs = Args.size();
for (unsigned i = 0; i != NumArgs; ++i) {		for (unsigned i = 0; i != NumArgs; ++i) {
EVT CurVT = EVT::getEVT(Args[i].Ty);		EVT CurVT = EVT::getEVT(Args[i].Ty);
if (CurVT.isSimple() &&		if (CurVT.isSimple() &&
!Handler.assignArg(i, CurVT.getSimpleVT(), CurVT.getSimpleVT(),		!Handler.assignArg(i, CurVT.getSimpleVT(), CurVT.getSimpleVT(),
Show All 9 Lines	for (unsigned i = 0; i != NumArgs; ++i) {
unsigned NumParts = TLI->getNumRegistersForCallingConv(		unsigned NumParts = TLI->getNumRegistersForCallingConv(
F.getContext(), CCInfo.getCallingConv(), CurVT);		F.getContext(), CCInfo.getCallingConv(), CurVT);

if (NumParts == 1) {		if (NumParts == 1) {
// Try to use the register type if we couldn't assign the VT.		// Try to use the register type if we couldn't assign the VT.
if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full, Args[i],		if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full, Args[i],
Args[i].Flags[0], CCInfo))		Args[i].Flags[0], CCInfo))
return false;		return false;

		// If we couldn't directly assign this part, some casting may be
		// necessary. Create the new register, but defer inserting the conversion
		// instructions.
		assert(Args[i].OrigRegs.empty());
		Args[i].OrigRegs.push_back(Args[i].Regs[0]);
		assert(Args[i].Regs.size() == 1);

		const LLT VATy(NewVT);
		Args[i].Regs[0] = MRI.createGenericVirtualRegister(VATy);
continue;		continue;
}		}

assert(NumParts > 1);		const LLT NewLLT(NewVT);

// For incoming arguments (physregs to vregs), we could have values in		// For incoming arguments (physregs to vregs), we could have values in
// physregs (or memlocs) which we want to extract and copy to vregs.		// physregs (or memlocs) which we want to extract and copy to vregs.
// During this, we might have to deal with the LLT being split across		// During this, we might have to deal with the LLT being split across
// multiple regs, so we have to record this information for later.		// multiple regs, so we have to record this information for later.
//		//
// If we have outgoing args, then we have the opposite case. We have a		// If we have outgoing args, then we have the opposite case. We have a
// vreg with an LLT which we want to assign to a physical location, and		// vreg with an LLT which we want to assign to a physical location, and
// we might have to record that the value has to be split later.		// we might have to record that the value has to be split later.
if (Handler.isIncomingArgumentHandler()) {		if (Handler.isIncomingArgumentHandler()) {
// We're handling an incoming arg which is split over multiple regs.		// We're handling an incoming arg which is split over multiple regs.
// E.g. passing an s128 on AArch64.		// E.g. passing an s128 on AArch64.
ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0];		ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0];
Args[i].OrigRegs.push_back(Args[i].Regs[0]);		Args[i].OrigRegs.push_back(Args[i].Regs[0]);
Args[i].Regs.clear();		Args[i].Regs.clear();
Args[i].Flags.clear();		Args[i].Flags.clear();
LLT NewLLT = getLLTForMVT(NewVT);
// For each split register, create and assign a vreg that will store		// For each split register, create and assign a vreg that will store
// the incoming component of the larger value. These will later be		// the incoming component of the larger value. These will later be
// merged to form the final vreg.		// merged to form the final vreg.
for (unsigned Part = 0; Part < NumParts; ++Part) {		for (unsigned Part = 0; Part < NumParts; ++Part) {
Register Reg =		Register Reg = MRI.createGenericVirtualRegister(NewLLT);
MIRBuilder.getMRI()->createGenericVirtualRegister(NewLLT);
ISD::ArgFlagsTy Flags = OrigFlags;		ISD::ArgFlagsTy Flags = OrigFlags;
if (Part == 0) {		if (Part == 0) {
Flags.setSplit();		Flags.setSplit();
} else {		} else {
Flags.setOrigAlign(Align(1));		Flags.setOrigAlign(Align(1));
if (Part == NumParts - 1)		if (Part == NumParts - 1)
Flags.setSplitEnd();		Flags.setSplitEnd();
}		}
Args[i].Regs.push_back(Reg);		Args[i].Regs.push_back(Reg);
Args[i].Flags.push_back(Flags);		Args[i].Flags.push_back(Flags);
if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full, Args[i],		if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full, Args[i],
Args[i].Flags[Part], CCInfo)) {		Args[i].Flags[Part], CCInfo)) {
// Still couldn't assign this smaller part type for some reason.		// Still couldn't assign this smaller part type for some reason.
return false;		return false;
}		}
}		}
} else {		} else {
		assert(Args[i].Regs.size() == 1);

// This type is passed via multiple registers in the calling convention.		// This type is passed via multiple registers in the calling convention.
// We need to extract the individual parts.		// We need to extract the individual parts.
Register LargeReg = Args[i].Regs[0];		assert(Args[i].OrigRegs.empty());
LLT SmallTy = LLT::scalar(NewVT.getSizeInBits());		Args[i].OrigRegs.push_back(Args[i].Regs[0]);
auto Unmerge = MIRBuilder.buildUnmerge(SmallTy, LargeReg);
assert(Unmerge->getNumOperands() == NumParts + 1);
ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0];		ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0];
// We're going to replace the regs and flags with the split ones.		// We're going to replace the regs and flags with the split ones.
Args[i].Regs.clear();		Args[i].Regs.clear();
Args[i].Flags.clear();		Args[i].Flags.clear();
for (unsigned PartIdx = 0; PartIdx < NumParts; ++PartIdx) {		for (unsigned PartIdx = 0; PartIdx < NumParts; ++PartIdx) {
ISD::ArgFlagsTy Flags = OrigFlags;		ISD::ArgFlagsTy Flags = OrigFlags;
if (PartIdx == 0) {		if (PartIdx == 0) {
Flags.setSplit();		Flags.setSplit();
} else {		} else {
Flags.setOrigAlign(Align(1));		Flags.setOrigAlign(Align(1));
if (PartIdx == NumParts - 1)		if (PartIdx == NumParts - 1)
Flags.setSplitEnd();		Flags.setSplitEnd();
}		}

// TODO: Also check if there is a valid extension that preserves the		// TODO: Also check if there is a valid extension that preserves the
// bits. However currently this call lowering doesn't support non-exact		// bits. However currently this call lowering doesn't support non-exact
// split parts, so that can't be tested.		// split parts, so that can't be tested.
if (OrigFlags.isReturned() &&		if (OrigFlags.isReturned() &&
(NumParts * NewVT.getSizeInBits() != CurVT.getSizeInBits())) {		(NumParts * NewVT.getSizeInBits() != CurVT.getSizeInBits())) {
Flags.setReturned(false);		Flags.setReturned(false);
}		}

Args[i].Regs.push_back(Unmerge.getReg(PartIdx));		Register NewReg = MRI.createGenericVirtualRegister(NewLLT);

		Args[i].Regs.push_back(NewReg);
Args[i].Flags.push_back(Flags);		Args[i].Flags.push_back(Flags);
if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full,		if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full,
Args[i], Args[i].Flags[PartIdx], CCInfo))		Args[i], Args[i].Flags[PartIdx], CCInfo))
return false;		return false;
}		}
}		}
}		}

for (unsigned i = 0, e = Args.size(), j = 0; i != e; ++i, ++j) {		for (unsigned i = 0, e = Args.size(), j = 0; i != e; ++i, ++j) {
assert(j < ArgLocs.size() && "Skipped too many arg locs");		assert(j < ArgLocs.size() && "Skipped too many arg locs");

CCValAssign &VA = ArgLocs[j];		CCValAssign &VA = ArgLocs[j];
assert(VA.getValNo() == i && "Location doesn't correspond to current arg");		assert(VA.getValNo() == i && "Location doesn't correspond to current arg");

if (VA.needsCustom()) {		if (VA.needsCustom()) {
unsigned NumArgRegs =		unsigned NumArgRegs =
Handler.assignCustomValue(Args[i], makeArrayRef(ArgLocs).slice(j));		Handler.assignCustomValue(Args[i], makeArrayRef(ArgLocs).slice(j));
if (!NumArgRegs)		if (!NumArgRegs)
return false;		return false;
j += NumArgRegs;		j += NumArgRegs;
continue;		continue;
}		}

EVT OrigVT = EVT::getEVT(Args[i].Ty);
EVT VAVT = VA.getValVT();		EVT VAVT = VA.getValVT();
const LLT OrigTy = getLLTForType(*Args[i].Ty, DL);		const LLT OrigTy = getLLTForType(*Args[i].Ty, DL);
const LLT VATy(VAVT.getSimpleVT());		const LLT VATy(VAVT.getSimpleVT());

// Expected to be multiple regs for a single incoming arg.		// Expected to be multiple regs for a single incoming arg.
// There should be Regs.size() ArgLocs per argument.		// There should be Regs.size() ArgLocs per argument.
unsigned NumArgRegs = Args[i].Regs.size();		unsigned NumArgRegs = Args[i].Regs.size();
MachineRegisterInfo &MRI = MF.getRegInfo();
assert((j + (NumArgRegs - 1)) < ArgLocs.size() &&		assert((j + (NumArgRegs - 1)) < ArgLocs.size() &&
"Too many regs for number of args");		"Too many regs for number of args");

		// Coerce into outgoing value types before register assignment.
		if (!Handler.isIncomingArgumentHandler() && OrigTy != VATy) {
		assert(Args[i].OrigRegs.size() == 1);
		buildCopyFromParts(MIRBuilder, Args[i].Regs, Args[i].OrigRegs[0], OrigTy,
		VATy);
		}

for (unsigned Part = 0; Part < NumArgRegs; ++Part) {		for (unsigned Part = 0; Part < NumArgRegs; ++Part) {
Register ArgReg = Args[i].Regs[Part];		Register ArgReg = Args[i].Regs[Part];
LLT ArgRegTy = MRI.getType(ArgReg);
// There should be Regs.size() ArgLocs per argument.		// There should be Regs.size() ArgLocs per argument.
VA = ArgLocs[j + Part];		VA = ArgLocs[j + Part];
if (VA.isMemLoc()) {		if (VA.isMemLoc()) {
// Individual pieces may have been spilled to the stack and others		// Individual pieces may have been spilled to the stack and others
// passed in registers.		// passed in registers.

// FIXME: Use correct address space for pointer size		// FIXME: Use correct address space for pointer size
EVT LocVT = VA.getValVT();		EVT LocVT = VA.getValVT();
Show All 11 Lines	for (unsigned Part = 0; Part < NumArgRegs; ++Part) {

if (i == 0 && ThisReturnReg.isValid() &&		if (i == 0 && ThisReturnReg.isValid() &&
Handler.isIncomingArgumentHandler() &&		Handler.isIncomingArgumentHandler() &&
isTypeIsValidForThisReturn(VAVT)) {		isTypeIsValidForThisReturn(VAVT)) {
Handler.assignValueToReg(Args[i].Regs[i], ThisReturnReg, VA);		Handler.assignValueToReg(Args[i].Regs[i], ThisReturnReg, VA);
continue;		continue;
}		}

// GlobalISel does not currently work for scalable vectors.		Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA);
if (OrigVT.getFixedSizeInBits() >= VAVT.getFixedSizeInBits() \|\|
!Handler.isIncomingArgumentHandler()) {
// This is an argument that might have been split. There should be
// Regs.size() ArgLocs per argument.

// Insert the argument copies. If VAVT < OrigVT, we'll insert the merge
// to the original register after handling all of the parts.
Handler.assignValueToReg(Args[i].Regs[Part], VA.getLocReg(), VA);
continue;
}		}

// This ArgLoc covers multiple pieces, so we need to split it.		// Now that all pieces have been assigned, re-pack the register typed values
Register NewReg = MRI.createGenericVirtualRegister(VATy);		// into the original value typed registers.
Handler.assignValueToReg(NewReg, VA.getLocReg(), VA);		if (Handler.isIncomingArgumentHandler() && OrigTy != VATy) {
// If it's a vector type, we either need to truncate the elements
// or do an unmerge to get the lower block of elements.
if (VATy.isVector() &&
VATy.getNumElements() > OrigVT.getVectorNumElements()) {
// Just handle the case where the VA type is a multiple of original
// type.
if (VATy.getNumElements() % OrigVT.getVectorNumElements() != 0) {
LLVM_DEBUG(dbgs() << "Incoming promoted vector arg elts is not a "
"multiple of orig type elt: "
<< VATy << " vs " << OrigTy);
return false;
}
SmallVector<Register, 4> DstRegs = {ArgReg};
unsigned NumParts =
VATy.getNumElements() / OrigVT.getVectorNumElements() - 1;
for (unsigned Idx = 0; Idx < NumParts; ++Idx)
DstRegs.push_back(
MIRBuilder.getMRI()->createGenericVirtualRegister(OrigTy));
MIRBuilder.buildUnmerge(DstRegs, {NewReg});
} else if (VATy.getScalarSizeInBits() > ArgRegTy.getScalarSizeInBits()) {
MIRBuilder.buildTrunc(ArgReg, {NewReg}).getReg(0);
} else {
MIRBuilder.buildCopy(ArgReg, NewReg);
}
}

// Now that all pieces have been handled, re-pack any arguments into any
// wider, original registers.
if (Handler.isIncomingArgumentHandler()) {
// Merge the split registers into the expected larger result vregs of		// Merge the split registers into the expected larger result vregs of
// the original call.		// the original call.

if (OrigTy != VATy && !Args[i].OrigRegs.empty()) {
buildCopyToParts(MIRBuilder, Args[i].OrigRegs, Args[i].Regs, OrigTy,		buildCopyToParts(MIRBuilder, Args[i].OrigRegs, Args[i].Regs, OrigTy,
VATy);		VATy);
}		}
}

j += NumArgRegs - 1;		j += NumArgRegs - 1;
}		}

return true;		return true;
}		}

void CallLowering::insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy,		void CallLowering::insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy,
▲ Show 20 Lines • Show All 314 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h

Show All 29 Lines	class AMDGPUCallLowering final : public CallLowering {

/// A function of this type is used to perform value split action.		/// A function of this type is used to perform value split action.
using SplitArgTy = std::function<void(ArrayRef<Register>, Register, LLT, LLT, int)>;		using SplitArgTy = std::function<void(ArrayRef<Register>, Register, LLT, LLT, int)>;

void splitToValueTypes(MachineIRBuilder &B, const ArgInfo &OrigArgInfo,		void splitToValueTypes(MachineIRBuilder &B, const ArgInfo &OrigArgInfo,
SmallVectorImpl<ArgInfo> &SplitArgs,		SmallVectorImpl<ArgInfo> &SplitArgs,
const DataLayout &DL, CallingConv::ID CallConv) const;		const DataLayout &DL, CallingConv::ID CallConv) const;

void processSplitArgs(MachineIRBuilder &B, const ArgInfo &OrigArgInfo,
const SmallVectorImpl<ArgInfo> &SplitArg,
SmallVectorImpl<ArgInfo> &SplitArgs,
const DataLayout &DL, CallingConv::ID CallConv,
bool IsOutgoing,
SplitArgTy PerformArgSplit) const;

bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv,		bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv,
SmallVectorImpl<BaseArgInfo> &Outs,		SmallVectorImpl<BaseArgInfo> &Outs,
bool IsVarArg) const override;		bool IsVarArg) const override;

bool lowerReturnVal(MachineIRBuilder &B, const Value *Val,		bool lowerReturnVal(MachineIRBuilder &B, const Value *Val,
ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;		ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;

public:		public:
Show All 26 Lines

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

Show First 20 Lines • Show All 313 Lines • ▼ Show 20 Lines	SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.Flags[0],
OrigArg.IsFixed);		OrigArg.IsFixed);
if (NeedsRegBlock)		if (NeedsRegBlock)
SplitArgs.back().Flags[0].setInConsecutiveRegs();		SplitArgs.back().Flags[0].setInConsecutiveRegs();
}		}

SplitArgs.back().Flags[0].setInConsecutiveRegsLast();		SplitArgs.back().Flags[0].setInConsecutiveRegsLast();
}		}

void AMDGPUCallLowering::processSplitArgs(
MachineIRBuilder &B, const ArgInfo &OrigArg,
const SmallVectorImpl<ArgInfo> &SplitArg,
SmallVectorImpl<ArgInfo> &SplitArgs, const DataLayout &DL,
CallingConv::ID CallConv, bool IsOutgoing,
SplitArgTy PerformArgSplit) const {
LLVMContext &Ctx = OrigArg.Ty->getContext();
const SITargetLowering &TLI = *getTLI<SITargetLowering>();

// FIXME: This is mostly nasty pre-processing before handleAssignments. Most
// of this should be performed by handleAssignments.

for (int SplitIdx = 0, e = SplitArg.size(); SplitIdx != e; ++SplitIdx) {
const ArgInfo &CurSplitArg = SplitArg[SplitIdx];
Register Reg = OrigArg.Regs[SplitIdx];
EVT VT = EVT::getEVT(CurSplitArg.Ty);
LLT LLTy = getLLTForType(*CurSplitArg.Ty, DL);

unsigned NumParts = TLI.getNumRegistersForCallingConv(Ctx, CallConv, VT);
MVT RegVT = TLI.getRegisterTypeForCallingConv(Ctx, CallConv, VT);

if (NumParts == 1) {
// No splitting to do, but we want to replace the original type (e.g. [1 x
// double] -> double).
SplitArgs.emplace_back(Reg, CurSplitArg.Ty, OrigArg.Flags,
OrigArg.IsFixed);
continue;
}

SmallVector<Register, 8> SplitRegs;
Type *PartTy = EVT(RegVT).getTypeForEVT(Ctx);
LLT PartLLT = getLLTForType(*PartTy, DL);
MachineRegisterInfo &MRI = *B.getMRI();

// FIXME: Should we be reporting all of the part registers for a single
// argument, and let handleAssignments take care of the repacking?
for (unsigned i = 0; i < NumParts; ++i) {
Register PartReg = MRI.createGenericVirtualRegister(PartLLT);
SplitRegs.push_back(PartReg);
SplitArgs.emplace_back(ArrayRef<Register>(PartReg), PartTy, OrigArg.Flags);
}

PerformArgSplit(SplitRegs, Reg, LLTy, PartLLT, SplitIdx);
}
}

// TODO: Move to generic code
static void unpackRegsToOrigType(MachineIRBuilder &B,
ArrayRef<Register> DstRegs,
Register SrcReg,
const CallLowering::ArgInfo &Info,
LLT SrcTy,
LLT PartTy) {
assert(DstRegs.size() > 1 && "Nothing to unpack");

const unsigned PartSize = PartTy.getSizeInBits();

if (SrcTy.isVector() && !PartTy.isVector() &&
PartSize > SrcTy.getElementType().getSizeInBits()) {
// Vector was scalarized, and the elements extended.
auto UnmergeToEltTy = B.buildUnmerge(SrcTy.getElementType(), SrcReg);
for (int i = 0, e = DstRegs.size(); i != e; ++i)
B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i));
return;
}

LLT GCDTy = getGCDType(SrcTy, PartTy);
if (GCDTy == PartTy) {
// If this already evenly divisible, we can create a simple unmerge.
B.buildUnmerge(DstRegs, SrcReg);
return;
}

MachineRegisterInfo &MRI = *B.getMRI();
LLT DstTy = MRI.getType(DstRegs[0]);
LLT LCMTy = getLCMType(SrcTy, PartTy);

const unsigned LCMSize = LCMTy.getSizeInBits();
const unsigned DstSize = DstTy.getSizeInBits();
const unsigned SrcSize = SrcTy.getSizeInBits();

Register UnmergeSrc = SrcReg;
if (LCMSize != SrcSize) {
// Widen to the common type.
Register Undef = B.buildUndef(SrcTy).getReg(0);
SmallVector<Register, 8> MergeParts(1, SrcReg);
for (unsigned Size = SrcSize; Size != LCMSize; Size += SrcSize)
MergeParts.push_back(Undef);

UnmergeSrc = B.buildMerge(LCMTy, MergeParts).getReg(0);
}

// Unmerge to the original registers and pad with dead defs.
SmallVector<Register, 8> UnmergeResults(DstRegs.begin(), DstRegs.end());
for (unsigned Size = DstSize * DstRegs.size(); Size != LCMSize;
Size += DstSize) {
UnmergeResults.push_back(MRI.createGenericVirtualRegister(DstTy));
}

B.buildUnmerge(UnmergeResults, UnmergeSrc);
}

bool AMDGPUCallLowering::canLowerReturn(MachineFunction &MF,		bool AMDGPUCallLowering::canLowerReturn(MachineFunction &MF,
CallingConv::ID CallConv,		CallingConv::ID CallConv,
SmallVectorImpl<BaseArgInfo> &Outs,		SmallVectorImpl<BaseArgInfo> &Outs,
bool IsVarArg) const {		bool IsVarArg) const {
// For shaders. Vector types should be explicitly handled by CC.		// For shaders. Vector types should be explicitly handled by CC.
if (AMDGPU::isEntryFunctionCC(CallConv))		if (AMDGPU::isEntryFunctionCC(CallConv))
return true;		return true;

Show All 22 Lines	bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B,
CallingConv::ID CC = F.getCallingConv();		CallingConv::ID CC = F.getCallingConv();
const SITargetLowering &TLI = *getTLI<SITargetLowering>();		const SITargetLowering &TLI = *getTLI<SITargetLowering>();

SmallVector<EVT, 8> SplitEVTs;		SmallVector<EVT, 8> SplitEVTs;
ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);		ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
assert(VRegs.size() == SplitEVTs.size() &&		assert(VRegs.size() == SplitEVTs.size() &&
"For each split Type there should be exactly one VReg.");		"For each split Type there should be exactly one VReg.");

// We pre-process the return value decomposed into EVTs.
SmallVector<ArgInfo, 8> PreSplitRetInfos;

// Further processing is applied to split the arguments from PreSplitRetInfos
// into 32-bit pieces in SplitRetInfos before passing off to
// handleAssignments.
SmallVector<ArgInfo, 8> SplitRetInfos;		SmallVector<ArgInfo, 8> SplitRetInfos;

for (unsigned i = 0; i < SplitEVTs.size(); ++i) {		for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
EVT VT = SplitEVTs[i];		EVT VT = SplitEVTs[i];
Register Reg = VRegs[i];		Register Reg = VRegs[i];
ArgInfo RetInfo(Reg, VT.getTypeForEVT(Ctx));		ArgInfo RetInfo(Reg, VT.getTypeForEVT(Ctx));
setArgFlags(RetInfo, AttributeList::ReturnIndex, DL, F);		setArgFlags(RetInfo, AttributeList::ReturnIndex, DL, F);

Show All 17 Lines	for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
}		}

if (Reg != RetInfo.Regs[0]) {		if (Reg != RetInfo.Regs[0]) {
RetInfo.Regs[0] = Reg;		RetInfo.Regs[0] = Reg;
// Reset the arg flags after modifying Reg.		// Reset the arg flags after modifying Reg.
setArgFlags(RetInfo, AttributeList::ReturnIndex, DL, F);		setArgFlags(RetInfo, AttributeList::ReturnIndex, DL, F);
}		}

splitToValueTypes(B, RetInfo, PreSplitRetInfos, DL, CC);		splitToValueTypes(B, RetInfo, SplitRetInfos, DL, CC);

// FIXME: This splitting should mostly be done by handleAssignments
processSplitArgs(B, RetInfo,
PreSplitRetInfos, SplitRetInfos, DL, CC, true,
[&](ArrayRef<Register> Regs, Register SrcReg, LLT LLTy,
LLT PartLLT, int VTSplitIdx) {
unpackRegsToOrigType(B, Regs, SrcReg,
PreSplitRetInfos[VTSplitIdx], LLTy,
PartLLT);
});
PreSplitRetInfos.clear();
}		}

CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(CC, F.isVarArg());		CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(CC, F.isVarArg());
AMDGPUOutgoingValueHandler RetHandler(B, *MRI, Ret, AssignFn);		AMDGPUOutgoingValueHandler RetHandler(B, *MRI, Ret, AssignFn);
return handleAssignments(B, SplitRetInfos, RetHandler, CC, F.isVarArg());		return handleAssignments(B, SplitRetInfos, RetHandler, CC, F.isVarArg());
}		}

bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &B, const Value *Val,		bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &B, const Value *Val,
▲ Show 20 Lines • Show All 588 Lines • ▼ Show 20 Lines	bool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
}		}

if (AMDGPU::isShader(CallConv)) {		if (AMDGPU::isShader(CallConv)) {
LLVM_DEBUG(dbgs() << "Unhandled call from graphics shader\n");		LLVM_DEBUG(dbgs() << "Unhandled call from graphics shader\n");
return false;		return false;
}		}

SmallVector<ArgInfo, 8> OutArgs;		SmallVector<ArgInfo, 8> OutArgs;
		for (auto &OrigArg : Info.OrigArgs)
SmallVector<ArgInfo, 8> SplitArg;		splitToValueTypes(MIRBuilder, OrigArg, OutArgs, DL, Info.CallConv);
for (auto &OrigArg : Info.OrigArgs) {
splitToValueTypes(MIRBuilder, OrigArg, SplitArg, DL, Info.CallConv);

processSplitArgs(
MIRBuilder, OrigArg, SplitArg, OutArgs, DL, Info.CallConv, true,
// FIXME: We should probably be passing multiple registers to
// handleAssignments to do this
[&](ArrayRef<Register> Regs, Register SrcReg, LLT LLTy, LLT PartLLT,
int VTSplitIdx) {
unpackRegsToOrigType(MIRBuilder, Regs, SrcReg, OrigArg, LLTy, PartLLT);
});

SplitArg.clear();
}

// If we can lower as a tail call, do that instead.		// If we can lower as a tail call, do that instead.
bool CanTailCallOpt = false;		bool CanTailCallOpt = false;

// We must emit a tail call if we have musttail.		// We must emit a tail call if we have musttail.
if (Info.IsMustTailCall && !CanTailCallOpt) {		if (Info.IsMustTailCall && !CanTailCallOpt) {
LLVM_DEBUG(dbgs() << "Failed to lower musttail call as tail call\n");		LLVM_DEBUG(dbgs() << "Failed to lower musttail call as tail call\n");
return false;		return false;
▲ Show 20 Lines • Show All 121 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll

	Show First 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
	define void @caller_s128(i128 *%ptr) {			define void @caller_s128(i128 *%ptr) {
	; CHECK-LABEL: name: caller_s128			; CHECK-LABEL: name: caller_s128
	; CHECK: bb.1 (%ir-block.0):			; CHECK: bb.1 (%ir-block.0):
	; CHECK: liveins: $x0			; CHECK: liveins: $x0
	; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0			; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
	; CHECK: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.ptr)			; CHECK: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.ptr)
	; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp			; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
	; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)			; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
	; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
	; CHECK: $x0 = COPY [[UV]](s64)			; CHECK: $x0 = COPY [[UV]](s64)
	; CHECK: $x1 = COPY [[UV1]](s64)			; CHECK: $x1 = COPY [[UV1]](s64)
				; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
	; CHECK: $x2 = COPY [[UV2]](s64)			; CHECK: $x2 = COPY [[UV2]](s64)
	; CHECK: $x3 = COPY [[UV3]](s64)			; CHECK: $x3 = COPY [[UV3]](s64)
	; CHECK: $x4 = COPY [[COPY]](p0)			; CHECK: $x4 = COPY [[COPY]](p0)
	; CHECK: BL @callee_s128, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4			; CHECK: BL @callee_s128, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4
	; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp			; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
	; CHECK: RET_ReallyLR			; CHECK: RET_ReallyLR
	%v = load i128, i128 *%ptr			%v = load i128, i128 *%ptr
	call void @callee_s128(i128 %v, i128 %v, i128 *%ptr)			call void @callee_s128(i128 %v, i128 %v, i128 *%ptr)
	▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll

Show All 13 Lines	define i8 @v1s8_add(<1 x i8> %a0) {
ret i8 %res		ret i8 %res
}		}

define i24 @test_v3i8(<3 x i8> %a) {		define i24 @test_v3i8(<3 x i8> %a) {
; CHECK-LABEL: name: test_v3i8		; CHECK-LABEL: name: test_v3i8
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $w0, $w1, $w2		; CHECK: liveins: $w0, $w1, $w2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0		; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w1		; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY3]](s32), [[COPY5]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(<3 x s8>) = G_TRUNC [[BUILD_VECTOR]](<3 x s32>)		; CHECK: [[TRUNC:%[0-9]+]]:_(<3 x s8>) = G_TRUNC [[BUILD_VECTOR]](<3 x s32>)
; CHECK: [[BITCAST:%[0-9]+]]:_(s24) = G_BITCAST [[TRUNC]](<3 x s8>)		; CHECK: [[BITCAST:%[0-9]+]]:_(s24) = G_BITCAST [[TRUNC]](<3 x s8>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](s24)		; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](s24)
; CHECK: $w0 = COPY [[ANYEXT]](s32)		; CHECK: $w0 = COPY [[ANYEXT]](s32)
; CHECK: RET_ReallyLR implicit $w0		; CHECK: RET_ReallyLR implicit $w0
%res = bitcast <3 x i8> %a to i24		%res = bitcast <3 x i8> %a to i24
ret i24 %res		ret i24 %res
}		}

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll

	Show All 21 Lines
	; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1			; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
	; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 8 from %fixed-stack.1)			; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 8 from %fixed-stack.1)
	; CHECK: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD]](s64), [[LOAD1]](s64)			; CHECK: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD]](s64), [[LOAD1]](s64)
	; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0			; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
	; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load 4 from %fixed-stack.0, align 16)			; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load 4 from %fixed-stack.0, align 16)
	; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0			; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
	; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp			; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
	; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV]](s128)			; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV]](s128)
	; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV1]](s128)
	; CHECK: $x0 = COPY [[UV]](s64)			; CHECK: $x0 = COPY [[UV]](s64)
	; CHECK: $x1 = COPY [[UV1]](s64)			; CHECK: $x1 = COPY [[UV1]](s64)
				; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV1]](s128)
	; CHECK: $x2 = COPY [[UV2]](s64)			; CHECK: $x2 = COPY [[UV2]](s64)
	; CHECK: $x3 = COPY [[UV3]](s64)			; CHECK: $x3 = COPY [[UV3]](s64)
	; CHECK: BL @use_s128, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3			; CHECK: BL @use_s128, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3
	; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp			; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
	; CHECK: $w0 = COPY [[C]](s32)			; CHECK: $w0 = COPY [[C]](s32)
	; CHECK: RET_ReallyLR implicit $w0			; CHECK: RET_ReallyLR implicit $w0
	define i32 @call_use_s128(i32 %p1, i128 %p2, i32 %p3, i32 %p4, i32 %p5, i128 %p6, i32 %p7) {			define i32 @call_use_s128(i32 %p1, i128 %p2, i32 %p3, i32 %p4, i32 %p5, i128 %p6, i32 %p7) {
	entry:			entry:
	call void @use_s128(i128 %p2, i128 %p6)			call void @use_s128(i128 %p2, i128 %p6)
	ret i32 0			ret i32 0
	}			}

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll

Show All 11 Lines	define i3 @bug47619(i64 %arg, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %arg5, i64 %arg6, i64 %arg7, i3 %arg8) {
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1		; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2		; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3		; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4		; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5		; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6		; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7		; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0		; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD:%[0-9]+]]:_(s3) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 1 from %fixed-stack.0, align 16)		; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 16)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s3)		; CHECK: [[TRUNC:%[0-9]+]]:_(s3) = G_TRUNC [[LOAD]](s32)
		; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s3)
; CHECK: $w0 = COPY [[ANYEXT]](s32)		; CHECK: $w0 = COPY [[ANYEXT]](s32)
; CHECK: RET_ReallyLR implicit $w0		; CHECK: RET_ReallyLR implicit $w0
bb:		bb:
ret i3 %arg8		ret i3 %arg8
}		}

llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir

Show All 23 Lines	bb.1 (%ir-block.0):
; CHECK-LABEL: name: udiv_test		; CHECK-LABEL: name: udiv_test
; CHECK: liveins: $x0, $x1		; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0		; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1		; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.v1ptr)		; CHECK: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.v1ptr)
; CHECK: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.v2ptr)		; CHECK: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.v2ptr)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp		; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)		; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD1]](s128)
; CHECK: $x0 = COPY [[UV]](s64)		; CHECK: $x0 = COPY [[UV]](s64)
; CHECK: $x1 = COPY [[UV1]](s64)		; CHECK: $x1 = COPY [[UV1]](s64)
		; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD1]](s128)
; CHECK: $x2 = COPY [[UV2]](s64)		; CHECK: $x2 = COPY [[UV2]](s64)
; CHECK: $x3 = COPY [[UV3]](s64)		; CHECK: $x3 = COPY [[UV3]](s64)
; CHECK: BL &__udivti3, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1		; CHECK: BL &__udivti3, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0		; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x1		; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)		; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK: G_STORE [[MV]](s128), [[COPY]](p0) :: (store 16 into %ir.v1ptr)		; CHECK: G_STORE [[MV]](s128), [[COPY]](p0) :: (store 16 into %ir.v1ptr)
Show All 22 Lines	bb.1 (%ir-block.0):
; CHECK-LABEL: name: sdiv_test		; CHECK-LABEL: name: sdiv_test
; CHECK: liveins: $x0, $x1		; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0		; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1		; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.v1ptr)		; CHECK: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.v1ptr)
; CHECK: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.v2ptr)		; CHECK: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.v2ptr)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp		; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)		; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD1]](s128)
; CHECK: $x0 = COPY [[UV]](s64)		; CHECK: $x0 = COPY [[UV]](s64)
; CHECK: $x1 = COPY [[UV1]](s64)		; CHECK: $x1 = COPY [[UV1]](s64)
		; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD1]](s128)
; CHECK: $x2 = COPY [[UV2]](s64)		; CHECK: $x2 = COPY [[UV2]](s64)
; CHECK: $x3 = COPY [[UV3]](s64)		; CHECK: $x3 = COPY [[UV3]](s64)
; CHECK: BL &__divti3, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1		; CHECK: BL &__divti3, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0		; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x1		; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)		; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK: G_STORE [[MV]](s128), [[COPY]](p0) :: (store 16 into %ir.v1ptr)		; CHECK: G_STORE [[MV]](s128), [[COPY]](p0) :: (store 16 into %ir.v1ptr)
Show All 10 Lines

llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll

	; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=irtranslator -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=irtranslator -o - %s \| FileCheck %s

	define <1 x float> @foo(<1 x float> %v) {			define <1 x float> @ret_v1f32(<1 x float> %v) {
	; CHECK-LABEL: name: foo			; CHECK-LABEL: name: ret_v1f32
	; CHECK: bb.1 (%ir-block.0):			; CHECK: bb.1 (%ir-block.0):
	; CHECK: liveins: $d0			; CHECK: liveins: $d0
	; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0			; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
	; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)			; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
	; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF			; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
	; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[DEF]](s32)			; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[DEF]](s32)
	; CHECK: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)			; CHECK: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
	; CHECK: RET_ReallyLR implicit $d0			; CHECK: RET_ReallyLR implicit $d0
	ret <1 x float> %v			ret <1 x float> %v
	}			}

				define <1 x i8> @ret_v1p0(<1 x i8> %v) {
				; CHECK-LABEL: name: ret_v1p0
				; CHECK: bb.1 (%ir-block.0):
				; CHECK: liveins: $d0
				; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $d0
				; CHECK: $d0 = COPY [[COPY]](p0)
				; CHECK: RET_ReallyLR implicit $d0
				ret <1 x i8*> %v
				}

				define <1 x i8 addrspace(1)> @ret_v1p1(<1 x i8 addrspace(1)> %v) {
				; CHECK-LABEL: name: ret_v1p1
				; CHECK: bb.1 (%ir-block.0):
				; CHECK: liveins: $d0
				; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $d0
				; CHECK: $d0 = COPY [[COPY]](p1)
				; CHECK: RET_ReallyLR implicit $d0
				ret <1 x i8 addrspace(1)*> %v
				}

llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll

Show First 20 Lines • Show All 357 Lines • ▼ Show 20 Lines	; GFX9-NEXT: ; return to shader part epilog
%cast.0 = bitcast <2 x i16> %and0 to i32		%cast.0 = bitcast <2 x i16> %and0 to i32
%cast.1 = bitcast <2 x i16> %and1 to i32		%cast.1 = bitcast <2 x i16> %and1 to i32
%insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0		%insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1		%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
ret { i32, i32 } %insert.1		ret { i32, i32 } %insert.1
}		}

define <2 x i16> @v_andn2_v2i16(<2 x i16> %src0, <2 x i16> %src1) {		define <2 x i16> @v_andn2_v2i16(<2 x i16> %src0, <2 x i16> %src1) {
; GFX6-LABEL: v_andn2_v2i16:		; GCN-LABEL: v_andn2_v2i16:
; GFX6: ; %bb.0:		; GCN: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_xor_b32_e32 v1, -1, v1		; GCN-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX6-NEXT: v_and_b32_e32 v0, v0, v1		; GCN-NEXT: v_and_b32_e32 v0, v0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0		; GCN-NEXT: s_setpc_b64 s[30:31]
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_andn2_v2i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX9-NEXT: v_and_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
%not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>		%not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>
%and = and <2 x i16> %src0, %not.src1		%and = and <2 x i16> %src0, %not.src1
ret <2 x i16> %and		ret <2 x i16> %and
}		}

; FIXME:		; FIXME:
; define amdgpu_ps i48 @s_andn2_v3i16(<3 x i16> inreg %src0, <3 x i16> inreg %src1) {		; define amdgpu_ps i48 @s_andn2_v3i16(<3 x i16> inreg %src0, <3 x i16> inreg %src1) {
; %not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -1>		; %not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -1>
▲ Show 20 Lines • Show All 225 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll

Show First 20 Lines • Show All 467 Lines • ▼ Show 20 Lines	; GFX9-NEXT: ; return to shader part epilog
%cast = bitcast i16 %result to half		%cast = bitcast i16 %result to half
ret half %cast		ret half %cast
}		}

define <2 x i16> @v_ashr_v2i16(<2 x i16> %value, <2 x i16> %amount) {		define <2 x i16> @v_ashr_v2i16(<2 x i16> %value, <2 x i16> %amount) {
; GFX6-LABEL: v_ashr_v2i16:		; GFX6-LABEL: v_ashr_v2i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v0, v1, v0		; GFX6-NEXT: v_ashrrev_i32_e32 v0, v1, v0
; GFX6-NEXT: v_bfe_i32 v1, v2, 0, 16		; GFX6-NEXT: v_bfe_i32 v1, v2, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v1, v3, v1		; GFX6-NEXT: v_ashrrev_i32_e32 v1, v3, v1
		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_ashr_v2i16:		; GFX8-LABEL: v_ashr_v2i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_ashrrev_i16_e32 v2, v1, v0		; GFX8-NEXT: v_ashrrev_i16_e32 v2, v1, v0
; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1		; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0		; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]		; GFX8-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX9-LABEL: v_ashr_v2i16:		; GFX9-LABEL: v_ashr_v2i16:
; GFX9: ; %bb.0:		; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_pk_ashrrev_i16 v0, v1, v0		; GFX9-NEXT: v_pk_ashrrev_i16 v0, v1, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]		; GFX9-NEXT: s_setpc_b64 s[30:31]
%result = ashr <2 x i16> %value, %amount		%result = ashr <2 x i16> %value, %amount
ret <2 x i16> %result		ret <2 x i16> %result
}		}

define <2 x i16> @v_ashr_v2i16_15(<2 x i16> %value) {		define <2 x i16> @v_ashr_v2i16_15(<2 x i16> %value) {
; GFX6-LABEL: v_ashr_v2i16_15:		; GFX6-LABEL: v_ashr_v2i16_15:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 15, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 15, v1		; GFX6-NEXT: v_ashrrev_i32_e32 v1, 15, v1
		; GFX6-NEXT: s_mov_b32 s4, 0xffff
		; GFX6-NEXT: v_ashrrev_i32_e32 v0, 15, v0
		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_ashr_v2i16_15:		; GFX8-LABEL: v_ashr_v2i16_15:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, 15		; GFX8-NEXT: v_mov_b32_e32 v2, 15
; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v0		; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v0
; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1		; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
▲ Show 20 Lines • Show All 722 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll

Show First 20 Lines • Show All 461 Lines • ▼ Show 20 Lines	; GFX9-NEXT: s_setpc_b64 s[30:31]
%zext = sext i16 %bswap to i32		%zext = sext i16 %bswap to i32
ret i32 %zext		ret i32 %zext
}		}

define <2 x i16> @v_bswap_v2i16(<2 x i16> %src) {		define <2 x i16> @v_bswap_v2i16(<2 x i16> %src) {
; GFX7-LABEL: v_bswap_v2i16:		; GFX7-LABEL: v_bswap_v2i16:
; GFX7: ; %bb.0:		; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_and_b32_e32 v3, 0xffff, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v0		; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v0
		; GFX7-NEXT: v_and_b32_e32 v3, 0xffff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 8, v0		; GFX7-NEXT: v_lshlrev_b32_e32 v2, 8, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 8, v3
; GFX7-NEXT: v_or_b32_e32 v2, v3, v2
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1		; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v0		; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v0
; GFX7-NEXT: v_or_b32_e32 v1, v0, v1		; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-NEXT: v_mov_b32_e32 v0, v2		; GFX7-NEXT: v_lshrrev_b32_e32 v3, 8, v3
		; GFX7-NEXT: v_bfe_u32 v0, v0, 0, 16
		; GFX7-NEXT: v_or_b32_e32 v2, v3, v2
		; GFX7-NEXT: v_bfe_u32 v1, v2, 0, 16
		; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
		; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]		; GFX7-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_bswap_v2i16:		; GFX8-LABEL: v_bswap_v2i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s4, 0x2030001		; GFX8-NEXT: s_mov_b32 s4, 0x2030001
; GFX8-NEXT: v_perm_b32 v0, 0, v0, s4		; GFX8-NEXT: v_perm_b32 v0, 0, v0, s4
; GFX8-NEXT: s_setpc_b64 s[30:31]		; GFX8-NEXT: s_setpc_b64 s[30:31]
▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines	define <2 x i16> @halfinsts_add_v2i16(<2 x i16> %arg0) #1 {
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)		; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)		; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)		; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)		; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]		; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)		; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY5]]		; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY5]]
		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)		; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
		; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)		; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
; CHECK: $vgpr0 = COPY [[COPY6]](s32)		; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; CHECK: $vgpr1 = COPY [[COPY7]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
		; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
		; CHECK: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; CHECK: [[COPY8:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]		; CHECK: [[COPY8:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
; CHECK: S_SETPC_B64_return [[COPY8]], implicit $vgpr0, implicit $vgpr1		; CHECK: S_SETPC_B64_return [[COPY8]], implicit $vgpr0
%add = add <2 x i16> %arg0, %arg0		%add = add <2 x i16> %arg0, %arg0
ret <2 x i16> %add		ret <2 x i16> %add
}		}

attributes #0 = { "target-features"="+vop3p" }		attributes #0 = { "target-features"="+vop3p" }
attributes #0 = { "target-features"="+16-bit-insts" }		attributes #0 = { "target-features"="+16-bit-insts" }

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll

	Show First 20 Lines • Show All 402 Lines • ▼ Show 20 Lines
	}			}

	define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) {			define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) {
	; GFX6-IEEE-LABEL: v_fdiv_v2f16:			; GFX6-IEEE-LABEL: v_fdiv_v2f16:
	; GFX6-IEEE: ; %bb.0:			; GFX6-IEEE: ; %bb.0:
	; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0			; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1			; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1
	; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
	; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1			; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
				; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2			; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2
	; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4			; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4
	; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2			; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2
				; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1
	; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0			; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0
	; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5			; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5
	; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5			; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5
	; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6			; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6
	; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7			; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7
	; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6			; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v6, v0			; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7
	; GFX6-IEEE-NEXT: v_div_fmas_f32 v0, v4, v5, v7			; GFX6-IEEE-NEXT: v_div_fixup_f32 v2, v4, v3, v2
	; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v0, v3, v2			; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
				; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
				; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
				; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2
				; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0
				; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4
				; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4
				; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5
				; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
				; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5
				; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6
				; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v1, v0
	; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v6			; GFX6-IEEE-NEXT: v_bfe_u32 v1, v2, 0, 16
	; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2			; GFX6-IEEE-NEXT: v_bfe_u32 v0, v0, 0, 16
	; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v6, v1, v6			; GFX6-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v0
	; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0			; GFX6-IEEE-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3
	; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
	; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v5, v4
	; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v3, v5
	; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
	; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
	; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, v6
	; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1
	; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]			; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX6-FLUSH-LABEL: v_fdiv_v2f16:			; GFX6-FLUSH-LABEL: v_fdiv_v2f16:
	; GFX6-FLUSH: ; %bb.0:			; GFX6-FLUSH: ; %bb.0:
	; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v1			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v1
	; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0
	; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v1, 16, v1			; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v1, 16, v1
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2			; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2
	; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4			; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2			; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
	; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0			; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0
	; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5			; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5
	; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5			; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5
	; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6			; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6
	; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7			; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7
	; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6			; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
	; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v5, v0
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1
	; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v3, v2			; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7
				; GFX6-FLUSH-NEXT: v_div_fixup_f32 v2, v4, v3, v2
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
	; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v5			; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
	; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2			; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v5, v1, v5			; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v3, 1.0			; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0
	; GFX6-FLUSH-NEXT: v_fma_f32 v3, v6, v3, v3			; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4
	; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v4, v3			; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4
	; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v4			; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v3, v6			; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6
	; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v4			; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
	; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v6			; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6
	; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, v5			; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v1, v0
	; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0
				; GFX6-FLUSH-NEXT: v_bfe_u32 v1, v2, 0, 16
				; GFX6-FLUSH-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v0
				; GFX6-FLUSH-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]			; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_fdiv_v2f16:			; GFX8-LABEL: v_fdiv_v2f16:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1			; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
	; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v1			; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v1
	; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v4			; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v4
	▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
	define <2 x half> @v_fdiv_v2f16_afn(<2 x half> %a, <2 x half> %b) {			define <2 x half> @v_fdiv_v2f16_afn(<2 x half> %a, <2 x half> %b) {
	; GFX6-LABEL: v_fdiv_v2f16_afn:			; GFX6-LABEL: v_fdiv_v2f16_afn:
	; GFX6: ; %bb.0:			; GFX6: ; %bb.0:
	; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v1			; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v1
	; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1			; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
	; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1			; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
	; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0			; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
	; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-NEXT: v_rcp_f32_e32 v3, v3
	; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2			; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
				; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-NEXT: v_rcp_f32_e32 v1, v1			; GFX6-NEXT: v_rcp_f32_e32 v1, v1
	; GFX6-NEXT: v_mul_f32_e32 v0, v0, v3			; GFX6-NEXT: v_rcp_f32_e32 v3, v3
	; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1			; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1
				; GFX6-NEXT: v_mul_f32_e32 v0, v0, v3
	; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
				; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
				; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_fdiv_v2f16_afn:			; GFX8-LABEL: v_fdiv_v2f16_afn:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_rcp_f16_e32 v2, v1			; GFX8-NEXT: v_rcp_f16_e32 v2, v1
	; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1			; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
	; GFX8-NEXT: v_mul_f16_e32 v2, v0, v2			; GFX8-NEXT: v_mul_f16_e32 v2, v0, v2
	Show All 18 Lines
	}			}

	define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) {			define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) {
	; GFX6-IEEE-LABEL: v_fdiv_v2f16_ulp25:			; GFX6-IEEE-LABEL: v_fdiv_v2f16_ulp25:
	; GFX6-IEEE: ; %bb.0:			; GFX6-IEEE: ; %bb.0:
	; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0			; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1			; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1
	; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
	; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1			; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
				; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2			; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2
	; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4			; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4
	; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2			; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2
				; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1
	; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0			; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0
	; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5			; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5
	; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5			; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5
	; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6			; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6
	; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7			; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7
	; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6			; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v6, v0			; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7
	; GFX6-IEEE-NEXT: v_div_fmas_f32 v0, v4, v5, v7			; GFX6-IEEE-NEXT: v_div_fixup_f32 v2, v4, v3, v2
	; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v0, v3, v2			; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
				; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
				; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
				; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2
				; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0
				; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4
				; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4
				; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5
				; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
				; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5
				; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6
				; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v1, v0
	; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v6			; GFX6-IEEE-NEXT: v_bfe_u32 v1, v2, 0, 16
	; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2			; GFX6-IEEE-NEXT: v_bfe_u32 v0, v0, 0, 16
	; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v6, v1, v6			; GFX6-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v0
	; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0			; GFX6-IEEE-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3
	; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
	; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v5, v4
	; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v3, v5
	; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
	; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
	; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, v6
	; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1
	; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]			; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX6-FLUSH-LABEL: v_fdiv_v2f16_ulp25:			; GFX6-FLUSH-LABEL: v_fdiv_v2f16_ulp25:
	; GFX6-FLUSH: ; %bb.0:			; GFX6-FLUSH: ; %bb.0:
	; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v1			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v1
	; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0
	; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v1, 16, v1			; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v1, 16, v1
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2			; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2
	; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4			; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2			; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
	; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0			; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0
	; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5			; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5
	; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5			; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5
	; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6			; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6
	; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7			; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7
	; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6			; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
	; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v5, v0
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1
	; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v3, v2			; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7
				; GFX6-FLUSH-NEXT: v_div_fixup_f32 v2, v4, v3, v2
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
	; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v5			; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
	; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2			; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v5, v1, v5			; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v3, 1.0			; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0
	; GFX6-FLUSH-NEXT: v_fma_f32 v3, v6, v3, v3			; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4
	; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v4, v3			; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4
	; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v4			; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v3, v6			; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6
	; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v4			; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
	; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v6			; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6
	; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, v5			; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v1, v0
	; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0
				; GFX6-FLUSH-NEXT: v_bfe_u32 v1, v2, 0, 16
				; GFX6-FLUSH-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v0
				; GFX6-FLUSH-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]			; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_fdiv_v2f16_ulp25:			; GFX8-LABEL: v_fdiv_v2f16_ulp25:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1			; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
	; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v1			; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v1
	; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v4			; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v4
	Show All 40 Lines

	define <2 x half> @v_rcp_v2f16(<2 x half> %x) {			define <2 x half> @v_rcp_v2f16(<2 x half> %x) {
	; GFX6-IEEE-LABEL: v_rcp_v2f16:			; GFX6-IEEE-LABEL: v_rcp_v2f16:
	; GFX6-IEEE: ; %bb.0:			; GFX6-IEEE: ; %bb.0:
	; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0			; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0			; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0
	; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0
				; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1			; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1
	; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3			; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
	; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1			; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1
	; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0			; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0
	; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4			; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4
	; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4			; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4
	; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5			; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5
	; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6			; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
	; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5			; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v5, v0			; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6
	; GFX6-IEEE-NEXT: v_div_fmas_f32 v0, v3, v4, v6			; GFX6-IEEE-NEXT: v_div_fixup_f32 v2, v3, v2, v1
	; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v0, v2, v1			; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v1
				; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
				; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v0, v1
				; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2
				; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0
				; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4
				; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4
				; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5
				; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
				; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5
				; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6
				; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v0, v1
	; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v5, v5, v1			; GFX6-IEEE-NEXT: v_bfe_u32 v1, v2, 0, 16
	; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2			; GFX6-IEEE-NEXT: v_bfe_u32 v0, v0, 0, 16
	; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v1, v5, v1			; GFX6-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v0
	; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v3, 1.0			; GFX6-IEEE-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX6-IEEE-NEXT: v_fma_f32 v3, v6, v3, v3
	; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v4, v3
	; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v6, v4
	; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v3, v6
	; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v6, v4
	; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v6
	; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v5, v1
	; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1
	; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]			; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX6-FLUSH-LABEL: v_rcp_v2f16:			; GFX6-FLUSH-LABEL: v_rcp_v2f16:
	; GFX6-FLUSH: ; %bb.0:			; GFX6-FLUSH: ; %bb.0:
	; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-FLUSH-NEXT: s_movk_i32 s6, 0x3c00			; GFX6-FLUSH-NEXT: s_movk_i32 s6, 0x3c00
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s6			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s6
	; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1			; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1
	; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3			; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1			; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0			; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0
	; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4			; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4
	; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4			; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4
	; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5			; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6			; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6
	; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5			; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
	; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6			; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v5, v0
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s6			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s6
	; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v2, v1			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0
				; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v3, v2, v1
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
	; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v5, v5, v4			; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v4
	; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v1			; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v4, v5, v4			; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v4, v0, v4
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v1, v2, 1.0			; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v3, 1.0
	; GFX6-FLUSH-NEXT: v_fma_f32 v2, v6, v2, v2			; GFX6-FLUSH-NEXT: v_fma_f32 v3, v6, v3, v3
	; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v3, v2			; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v3
	; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v1, v6, v3			; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v2, v6			; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v3, v6
	; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v6, v3			; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
	; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v6			; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v6
	; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v1, v5, v4			; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, v4
	; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0
				; GFX6-FLUSH-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-FLUSH-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v0
				; GFX6-FLUSH-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]			; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_rcp_v2f16:			; GFX8-LABEL: v_rcp_v2f16:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0			; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0
	; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v0			; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v0
	; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v2			; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v2
	Show All 36 Lines

	define <2 x half> @v_rcp_v2f16_arcp(<2 x half> %x) {			define <2 x half> @v_rcp_v2f16_arcp(<2 x half> %x) {
	; GFX6-IEEE-LABEL: v_rcp_v2f16_arcp:			; GFX6-IEEE-LABEL: v_rcp_v2f16_arcp:
	; GFX6-IEEE: ; %bb.0:			; GFX6-IEEE: ; %bb.0:
	; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0			; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0			; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0
	; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0
				; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1			; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1
	; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3			; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
	; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1			; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1
	; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0			; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0
	; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4			; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4
	; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4			; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4
	; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5			; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5
	; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6			; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
	; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5			; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v5, v0			; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6
	; GFX6-IEEE-NEXT: v_div_fmas_f32 v0, v3, v4, v6			; GFX6-IEEE-NEXT: v_div_fixup_f32 v2, v3, v2, v1
	; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v0, v2, v1			; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v1
				; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
				; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v0, v1
				; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2
				; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0
				; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4
				; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4
				; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5
				; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
				; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5
				; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6
				; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v0, v1
	; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v5, v5, v1			; GFX6-IEEE-NEXT: v_bfe_u32 v1, v2, 0, 16
	; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2			; GFX6-IEEE-NEXT: v_bfe_u32 v0, v0, 0, 16
	; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v1, v5, v1			; GFX6-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v0
	; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v3, 1.0			; GFX6-IEEE-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX6-IEEE-NEXT: v_fma_f32 v3, v6, v3, v3
	; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v4, v3
	; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v6, v4
	; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v3, v6
	; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v6, v4
	; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v6
	; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v5, v1
	; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1
	; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]			; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX6-FLUSH-LABEL: v_rcp_v2f16_arcp:			; GFX6-FLUSH-LABEL: v_rcp_v2f16_arcp:
	; GFX6-FLUSH: ; %bb.0:			; GFX6-FLUSH: ; %bb.0:
	; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-FLUSH-NEXT: s_movk_i32 s6, 0x3c00			; GFX6-FLUSH-NEXT: s_movk_i32 s6, 0x3c00
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s6			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s6
	; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1			; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1
	; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3			; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1			; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0			; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0
	; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4			; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4
	; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4			; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4
	; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5			; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6			; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6
	; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5			; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
	; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6			; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v5, v0
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s6			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s6
	; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v2, v1			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0
				; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v3, v2, v1
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
	; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v5, v5, v4			; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v4
	; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v1			; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v4, v5, v4			; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v4, v0, v4
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v1, v2, 1.0			; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v3, 1.0
	; GFX6-FLUSH-NEXT: v_fma_f32 v2, v6, v2, v2			; GFX6-FLUSH-NEXT: v_fma_f32 v3, v6, v3, v3
	; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v3, v2			; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v3
	; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v1, v6, v3			; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v2, v6			; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v3, v6
	; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v6, v3			; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
	; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v6			; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v6
	; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v1, v5, v4			; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, v4
	; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0
				; GFX6-FLUSH-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-FLUSH-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v0
				; GFX6-FLUSH-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]			; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_rcp_v2f16_arcp:			; GFX8-LABEL: v_rcp_v2f16_arcp:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0			; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0
	; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v0			; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v0
	; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v2			; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v2
	Show All 38 Lines
	; GFX6-LABEL: v_rcp_v2f16_arcp_afn:			; GFX6-LABEL: v_rcp_v2f16_arcp_afn:
	; GFX6: ; %bb.0:			; GFX6: ; %bb.0:
	; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0			; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0
	; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
	; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0			; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-NEXT: v_cvt_f32_f16_e32 v2, 1.0			; GFX6-NEXT: v_cvt_f32_f16_e32 v2, 1.0
	; GFX6-NEXT: v_rcp_f32_e32 v1, v1			; GFX6-NEXT: v_rcp_f32_e32 v1, v1
	; GFX6-NEXT: v_rcp_f32_e32 v3, v0			; GFX6-NEXT: v_rcp_f32_e32 v0, v0
	; GFX6-NEXT: v_mul_f32_e32 v0, v2, v1			; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1
	; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-NEXT: v_mul_f32_e32 v1, v2, v3
	; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
				; GFX6-NEXT: v_mul_f32_e32 v0, v2, v0
				; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
				; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
				; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_rcp_v2f16_arcp_afn:			; GFX8-LABEL: v_rcp_v2f16_arcp_afn:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1			; GFX8-NEXT: v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
	; GFX8-NEXT: v_rcp_f16_e32 v0, v0			; GFX8-NEXT: v_rcp_f16_e32 v0, v0
	; GFX8-NEXT: v_mov_b32_e32 v2, 16			; GFX8-NEXT: v_mov_b32_e32 v2, 16
	Show All 15 Lines

	define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) {			define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) {
	; GFX6-IEEE-LABEL: v_rcp_v2f16_ulp25:			; GFX6-IEEE-LABEL: v_rcp_v2f16_ulp25:
	; GFX6-IEEE: ; %bb.0:			; GFX6-IEEE: ; %bb.0:
	; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0			; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0			; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0
	; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0
				; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1			; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1
	; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3			; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
	; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1			; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1
	; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0			; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0
	; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4			; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4
	; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4			; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4
	; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5			; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5
	; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6			; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
	; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5			; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v5, v0			; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6
	; GFX6-IEEE-NEXT: v_div_fmas_f32 v0, v3, v4, v6			; GFX6-IEEE-NEXT: v_div_fixup_f32 v2, v3, v2, v1
	; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v0, v2, v1			; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v1
				; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
				; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v0, v1
				; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2
				; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0
				; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4
				; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4
				; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5
				; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
				; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5
				; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6
				; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v0, v1
	; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v5, v5, v1			; GFX6-IEEE-NEXT: v_bfe_u32 v1, v2, 0, 16
	; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2			; GFX6-IEEE-NEXT: v_bfe_u32 v0, v0, 0, 16
	; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v1, v5, v1			; GFX6-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v0
	; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v3, 1.0			; GFX6-IEEE-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX6-IEEE-NEXT: v_fma_f32 v3, v6, v3, v3
	; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v4, v3
	; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v6, v4
	; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v3, v6
	; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v6, v4
	; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v6
	; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v5, v1
	; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1
	; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]			; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX6-FLUSH-LABEL: v_rcp_v2f16_ulp25:			; GFX6-FLUSH-LABEL: v_rcp_v2f16_ulp25:
	; GFX6-FLUSH: ; %bb.0:			; GFX6-FLUSH: ; %bb.0:
	; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-FLUSH-NEXT: s_movk_i32 s6, 0x3c00			; GFX6-FLUSH-NEXT: s_movk_i32 s6, 0x3c00
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s6			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s6
	; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1			; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1
	; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3			; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1			; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0			; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0
	; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4			; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4
	; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4			; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4
	; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5			; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6			; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6
	; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5			; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
	; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6			; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v5, v0
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s6			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s6
	; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v2, v1			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0
				; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v3, v2, v1
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
	; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v5, v5, v4			; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v4
	; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v1			; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v4, v5, v4			; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v4, v0, v4
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v1, v2, 1.0			; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v3, 1.0
	; GFX6-FLUSH-NEXT: v_fma_f32 v2, v6, v2, v2			; GFX6-FLUSH-NEXT: v_fma_f32 v3, v6, v3, v3
	; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v3, v2			; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v3
	; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v1, v6, v3			; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v2, v6			; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v3, v6
	; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v6, v3			; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
	; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v6			; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v6
	; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v1, v5, v4			; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, v4
	; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0
				; GFX6-FLUSH-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-FLUSH-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v0
				; GFX6-FLUSH-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]			; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_rcp_v2f16_ulp25:			; GFX8-LABEL: v_rcp_v2f16_ulp25:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1			; GFX8-NEXT: v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
	; GFX8-NEXT: v_rcp_f16_e32 v0, v0			; GFX8-NEXT: v_rcp_f16_e32 v0, v0
	; GFX8-NEXT: v_mov_b32_e32 v2, 16			; GFX8-NEXT: v_mov_b32_e32 v2, 16
	Show All 16 Lines
	define <2 x half> @v_fdiv_v2f16_afn_ulp25(<2 x half> %a, <2 x half> %b) {			define <2 x half> @v_fdiv_v2f16_afn_ulp25(<2 x half> %a, <2 x half> %b) {
	; GFX6-LABEL: v_fdiv_v2f16_afn_ulp25:			; GFX6-LABEL: v_fdiv_v2f16_afn_ulp25:
	; GFX6: ; %bb.0:			; GFX6: ; %bb.0:
	; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v1			; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v1
	; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1			; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
	; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1			; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
	; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0			; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
	; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-NEXT: v_rcp_f32_e32 v3, v3
	; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2			; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
				; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-NEXT: v_rcp_f32_e32 v1, v1			; GFX6-NEXT: v_rcp_f32_e32 v1, v1
	; GFX6-NEXT: v_mul_f32_e32 v0, v0, v3			; GFX6-NEXT: v_rcp_f32_e32 v3, v3
	; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1			; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1
				; GFX6-NEXT: v_mul_f32_e32 v0, v0, v3
	; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
				; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
				; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_fdiv_v2f16_afn_ulp25:			; GFX8-LABEL: v_fdiv_v2f16_afn_ulp25:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_rcp_f16_e32 v2, v1			; GFX8-NEXT: v_rcp_f16_e32 v2, v1
	; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1			; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
	; GFX8-NEXT: v_mul_f16_e32 v2, v0, v2			; GFX8-NEXT: v_mul_f16_e32 v2, v0, v2
	Show All 18 Lines
	}			}

	define <2 x half> @v_fdiv_v2f16_arcp_ulp25(<2 x half> %a, <2 x half> %b) {			define <2 x half> @v_fdiv_v2f16_arcp_ulp25(<2 x half> %a, <2 x half> %b) {
	; GFX6-IEEE-LABEL: v_fdiv_v2f16_arcp_ulp25:			; GFX6-IEEE-LABEL: v_fdiv_v2f16_arcp_ulp25:
	; GFX6-IEEE: ; %bb.0:			; GFX6-IEEE: ; %bb.0:
	; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0			; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1			; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1
	; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
	; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1			; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
				; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2			; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2
	; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4			; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4
	; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2			; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2
				; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1
	; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0			; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0
	; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5			; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5
	; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5			; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5
	; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6			; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6
	; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7			; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7
	; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6			; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6
	; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v6, v0			; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7
	; GFX6-IEEE-NEXT: v_div_fmas_f32 v0, v4, v5, v7			; GFX6-IEEE-NEXT: v_div_fixup_f32 v2, v4, v3, v2
	; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v0, v3, v2			; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
				; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
				; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
				; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2
				; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0
				; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4
				; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4
				; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5
				; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
				; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5
				; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6
				; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v1, v0
	; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v6			; GFX6-IEEE-NEXT: v_bfe_u32 v1, v2, 0, 16
	; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2			; GFX6-IEEE-NEXT: v_bfe_u32 v0, v0, 0, 16
	; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v6, v1, v6			; GFX6-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v0
	; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0			; GFX6-IEEE-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3
	; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
	; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v5, v4
	; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v3, v5
	; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
	; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
	; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, v6
	; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1
	; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]			; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX6-FLUSH-LABEL: v_fdiv_v2f16_arcp_ulp25:			; GFX6-FLUSH-LABEL: v_fdiv_v2f16_arcp_ulp25:
	; GFX6-FLUSH: ; %bb.0:			; GFX6-FLUSH: ; %bb.0:
	; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v1			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v1
	; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0
	; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v1, 16, v1			; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v1, 16, v1
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2			; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2
	; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4			; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2			; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
	; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0			; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0
	; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5			; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5
	; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5			; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5
	; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6			; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6
	; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7			; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7
	; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6			; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
	; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v5, v0
	; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1			; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1
	; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v3, v2			; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7
				; GFX6-FLUSH-NEXT: v_div_fixup_f32 v2, v4, v3, v2
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
	; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v5			; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
	; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2			; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
	; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v5, v1, v5			; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v3, 1.0			; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0
	; GFX6-FLUSH-NEXT: v_fma_f32 v3, v6, v3, v3			; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4
	; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v4, v3			; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4
	; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v4			; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5
	; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v3, v6			; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6
	; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v4			; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5
	; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0			; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
	; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v6			; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6
	; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, v5			; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v1, v0
	; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0
				; GFX6-FLUSH-NEXT: v_bfe_u32 v1, v2, 0, 16
				; GFX6-FLUSH-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v0
				; GFX6-FLUSH-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]			; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_fdiv_v2f16_arcp_ulp25:			; GFX8-LABEL: v_fdiv_v2f16_arcp_ulp25:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1			; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
	; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v1			; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v1
	; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v4			; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v4
	▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
	define <2 x half> @v_fdiv_v2f16_arcp_afn_ulp25(<2 x half> %a, <2 x half> %b) {			define <2 x half> @v_fdiv_v2f16_arcp_afn_ulp25(<2 x half> %a, <2 x half> %b) {
	; GFX6-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:			; GFX6-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
	; GFX6: ; %bb.0:			; GFX6: ; %bb.0:
	; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v1			; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v1
	; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1			; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
	; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1			; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
	; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0			; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
	; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-NEXT: v_rcp_f32_e32 v3, v3
	; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2			; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
				; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-NEXT: v_rcp_f32_e32 v1, v1			; GFX6-NEXT: v_rcp_f32_e32 v1, v1
	; GFX6-NEXT: v_mul_f32_e32 v0, v0, v3			; GFX6-NEXT: v_rcp_f32_e32 v3, v3
	; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1			; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1
				; GFX6-NEXT: v_mul_f32_e32 v0, v0, v3
	; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
				; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
				; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:			; GFX8-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_rcp_f16_e32 v2, v1			; GFX8-NEXT: v_rcp_f16_e32 v2, v1
	; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1			; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
	; GFX8-NEXT: v_mul_f16_e32 v2, v0, v2			; GFX8-NEXT: v_mul_f16_e32 v2, v0, v2
	Show All 21 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll

	Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
	; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2			; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
	; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3			; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
	; GFX6-NEXT: v_cvt_f32_f16_e32 v4, v4			; GFX6-NEXT: v_cvt_f32_f16_e32 v4, v4
	; GFX6-NEXT: v_cvt_f32_f16_e32 v5, v5			; GFX6-NEXT: v_cvt_f32_f16_e32 v5, v5
	; GFX6-NEXT: v_fma_f32 v0, v0, v1, v2			; GFX6-NEXT: v_fma_f32 v0, v0, v1, v2
	; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-NEXT: v_fma_f32 v1, v3, v4, v5			; GFX6-NEXT: v_fma_f32 v1, v3, v4, v5
	; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
				; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_fma_v2f16:			; GFX8-LABEL: v_fma_v2f16:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0			; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0
	; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1			; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
	; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2			; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2
	Show All 26 Lines
	; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2			; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
	; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3			; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
	; GFX6-NEXT: v_cvt_f32_f16_e32 v4, v4			; GFX6-NEXT: v_cvt_f32_f16_e32 v4, v4
	; GFX6-NEXT: v_cvt_f32_f16_e32 v5, v5			; GFX6-NEXT: v_cvt_f32_f16_e32 v5, v5
	; GFX6-NEXT: v_fma_f32 v0, v0, v1, v2			; GFX6-NEXT: v_fma_f32 v0, v0, v1, v2
	; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-NEXT: v_fma_f32 v1, v3, v4, v5			; GFX6-NEXT: v_fma_f32 v1, v3, v4, v5
	; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
				; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_fma_v2f16_fneg_lhs:			; GFX8-LABEL: v_fma_v2f16_fneg_lhs:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0			; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
	; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0			; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0
	; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1			; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
	Show All 28 Lines
	; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2			; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
	; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3			; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
	; GFX6-NEXT: v_cvt_f32_f16_e32 v4, v4			; GFX6-NEXT: v_cvt_f32_f16_e32 v4, v4
	; GFX6-NEXT: v_cvt_f32_f16_e32 v5, v5			; GFX6-NEXT: v_cvt_f32_f16_e32 v5, v5
	; GFX6-NEXT: v_fma_f32 v0, v0, v1, v2			; GFX6-NEXT: v_fma_f32 v0, v0, v1, v2
	; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-NEXT: v_fma_f32 v1, v3, v4, v5			; GFX6-NEXT: v_fma_f32 v1, v3, v4, v5
	; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
				; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_fma_v2f16_fneg_rhs:			; GFX8-LABEL: v_fma_v2f16_fneg_rhs:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1			; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
	; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0			; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0
	; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1			; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
	Show All 30 Lines
	; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2			; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
	; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3			; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
	; GFX6-NEXT: v_cvt_f32_f16_e32 v4, v4			; GFX6-NEXT: v_cvt_f32_f16_e32 v4, v4
	; GFX6-NEXT: v_cvt_f32_f16_e32 v5, v5			; GFX6-NEXT: v_cvt_f32_f16_e32 v5, v5
	; GFX6-NEXT: v_fma_f32 v0, v0, v1, v2			; GFX6-NEXT: v_fma_f32 v0, v0, v1, v2
	; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-NEXT: v_fma_f32 v1, v3, v4, v5			; GFX6-NEXT: v_fma_f32 v1, v3, v4, v5
	; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
				; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_fma_v2f16_fneg_lhs_rhs:			; GFX8-LABEL: v_fma_v2f16_fneg_lhs_rhs:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: s_mov_b32 s4, 0x80008000			; GFX8-NEXT: s_mov_b32 s4, 0x80008000
	; GFX8-NEXT: v_xor_b32_e32 v0, s4, v0			; GFX8-NEXT: v_xor_b32_e32 v0, s4, v0
	; GFX8-NEXT: v_xor_b32_e32 v1, s4, v1			; GFX8-NEXT: v_xor_b32_e32 v1, s4, v1
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llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll

	Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
	; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3			; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
	; GFX6-NEXT: v_log_f32_e32 v2, v2			; GFX6-NEXT: v_log_f32_e32 v2, v2
	; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1			; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
	; GFX6-NEXT: v_exp_f32_e32 v0, v0			; GFX6-NEXT: v_exp_f32_e32 v0, v0
	; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v2, v3			; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v2, v3
	; GFX6-NEXT: v_exp_f32_e32 v1, v1			; GFX6-NEXT: v_exp_f32_e32 v1, v1
	; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
				; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_pow_v2f16:			; GFX8-LABEL: v_pow_v2f16:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_log_f16_e32 v2, v0			; GFX8-NEXT: v_log_f16_e32 v2, v0
	; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1			; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
	; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1			; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3			; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
	; GFX6-NEXT: v_log_f32_e32 v2, v2			; GFX6-NEXT: v_log_f32_e32 v2, v2
	; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1			; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
	; GFX6-NEXT: v_exp_f32_e32 v0, v0			; GFX6-NEXT: v_exp_f32_e32 v0, v0
	; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v2, v3			; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v2, v3
	; GFX6-NEXT: v_exp_f32_e32 v1, v1			; GFX6-NEXT: v_exp_f32_e32 v1, v1
	; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
				; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_pow_v2f16_fneg_lhs:			; GFX8-LABEL: v_pow_v2f16_fneg_lhs:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0			; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
	; GFX8-NEXT: v_log_f16_e32 v2, v0			; GFX8-NEXT: v_log_f16_e32 v2, v0
	; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1			; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
	▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
	; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3			; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
	; GFX6-NEXT: v_log_f32_e32 v2, v2			; GFX6-NEXT: v_log_f32_e32 v2, v2
	; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1			; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
	; GFX6-NEXT: v_exp_f32_e32 v0, v0			; GFX6-NEXT: v_exp_f32_e32 v0, v0
	; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v2, v3			; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v2, v3
	; GFX6-NEXT: v_exp_f32_e32 v1, v1			; GFX6-NEXT: v_exp_f32_e32 v1, v1
	; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
				; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_pow_v2f16_fneg_rhs:			; GFX8-LABEL: v_pow_v2f16_fneg_rhs:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_log_f16_e32 v2, v0			; GFX8-NEXT: v_log_f16_e32 v2, v0
	; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1			; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
	; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1			; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
	▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
	; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3			; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3
	; GFX6-NEXT: v_log_f32_e32 v2, v2			; GFX6-NEXT: v_log_f32_e32 v2, v2
	; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1			; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
	; GFX6-NEXT: v_exp_f32_e32 v0, v0			; GFX6-NEXT: v_exp_f32_e32 v0, v0
	; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v2, v3			; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v2, v3
	; GFX6-NEXT: v_exp_f32_e32 v1, v1			; GFX6-NEXT: v_exp_f32_e32 v1, v1
	; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
				; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_pow_v2f16_fneg_lhs_rhs:			; GFX8-LABEL: v_pow_v2f16_fneg_lhs_rhs:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: s_mov_b32 s4, 0x80008000			; GFX8-NEXT: s_mov_b32 s4, 0x80008000
	; GFX8-NEXT: v_xor_b32_e32 v0, s4, v0			; GFX8-NEXT: v_xor_b32_e32 v0, s4, v0
	; GFX8-NEXT: v_log_f16_e32 v2, v0			; GFX8-NEXT: v_log_f16_e32 v2, v0
	▲ Show 20 Lines • Show All 280 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll

Show First 20 Lines • Show All 205 Lines • ▼ Show 20 Lines	define amdgpu_kernel void @test_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX900: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GFX900: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GFX900: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; GFX900: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GFX900: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GFX900: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GFX900: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GFX900: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; GFX900: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; GFX900: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GFX900: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; GFX900: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX900: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)		; GFX900: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; GFX900: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)		; GFX900: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; GFX900: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<32 x s32>)
; GFX900: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GFX900: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GFX900: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v32i32		; GFX900: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v32i32
; GFX900: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GFX900: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GFX900: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GFX900: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GFX900: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; GFX900: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GFX900: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 20		; GFX900: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 20
; GFX900: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)		; GFX900: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)
; GFX900: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GFX900: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GFX900: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GFX900: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GFX900: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GFX900: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GFX900: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GFX900: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX900: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GFX900: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX900: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX900: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX900: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GFX900: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GFX900: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)		; GFX900: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
; GFX900: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; GFX900: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GFX900: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX900: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX900: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GFX900: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GFX900: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)		; GFX900: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
; GFX900: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GFX900: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; GFX900: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<32 x s32>)
; GFX900: $vgpr0 = COPY [[UV]](s32)		; GFX900: $vgpr0 = COPY [[UV]](s32)
; GFX900: $vgpr1 = COPY [[UV1]](s32)		; GFX900: $vgpr1 = COPY [[UV1]](s32)
; GFX900: $vgpr2 = COPY [[UV2]](s32)		; GFX900: $vgpr2 = COPY [[UV2]](s32)
; GFX900: $vgpr3 = COPY [[UV3]](s32)		; GFX900: $vgpr3 = COPY [[UV3]](s32)
; GFX900: $vgpr4 = COPY [[UV4]](s32)		; GFX900: $vgpr4 = COPY [[UV4]](s32)
; GFX900: $vgpr5 = COPY [[UV5]](s32)		; GFX900: $vgpr5 = COPY [[UV5]](s32)
; GFX900: $vgpr6 = COPY [[UV6]](s32)		; GFX900: $vgpr6 = COPY [[UV6]](s32)
; GFX900: $vgpr7 = COPY [[UV7]](s32)		; GFX900: $vgpr7 = COPY [[UV7]](s32)
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines	define amdgpu_kernel void @test_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX908: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GFX908: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GFX908: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; GFX908: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GFX908: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GFX908: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GFX908: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GFX908: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; GFX908: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; GFX908: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GFX908: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; GFX908: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX908: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)		; GFX908: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; GFX908: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)		; GFX908: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; GFX908: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<32 x s32>)
; GFX908: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GFX908: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GFX908: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v32i32		; GFX908: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v32i32
; GFX908: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GFX908: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GFX908: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GFX908: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GFX908: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; GFX908: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GFX908: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 20		; GFX908: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 20
; GFX908: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)		; GFX908: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)
; GFX908: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GFX908: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GFX908: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GFX908: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GFX908: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GFX908: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GFX908: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GFX908: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX908: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GFX908: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX908: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX908: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX908: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GFX908: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GFX908: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)		; GFX908: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
; GFX908: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; GFX908: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GFX908: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX908: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX908: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GFX908: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GFX908: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)		; GFX908: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
; GFX908: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GFX908: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; GFX908: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<32 x s32>)
; GFX908: $vgpr0 = COPY [[UV]](s32)		; GFX908: $vgpr0 = COPY [[UV]](s32)
; GFX908: $vgpr1 = COPY [[UV1]](s32)		; GFX908: $vgpr1 = COPY [[UV1]](s32)
; GFX908: $vgpr2 = COPY [[UV2]](s32)		; GFX908: $vgpr2 = COPY [[UV2]](s32)
; GFX908: $vgpr3 = COPY [[UV3]](s32)		; GFX908: $vgpr3 = COPY [[UV3]](s32)
; GFX908: $vgpr4 = COPY [[UV4]](s32)		; GFX908: $vgpr4 = COPY [[UV4]](s32)
; GFX908: $vgpr5 = COPY [[UV5]](s32)		; GFX908: $vgpr5 = COPY [[UV5]](s32)
; GFX908: $vgpr6 = COPY [[UV6]](s32)		; GFX908: $vgpr6 = COPY [[UV6]](s32)
; GFX908: $vgpr7 = COPY [[UV7]](s32)		; GFX908: $vgpr7 = COPY [[UV7]](s32)
▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines	define void @test_func_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX900: [[TRUNC30:%[0-9]+]]:_(s16) = G_TRUNC [[COPY23]](s32)		; GFX900: [[TRUNC30:%[0-9]+]]:_(s16) = G_TRUNC [[COPY23]](s32)
; GFX900: [[TRUNC31:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC30]](s16)		; GFX900: [[TRUNC31:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC30]](s16)
; GFX900: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr16		; GFX900: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr16
; GFX900: [[TRUNC32:%[0-9]+]]:_(s16) = G_TRUNC [[COPY24]](s32)		; GFX900: [[TRUNC32:%[0-9]+]]:_(s16) = G_TRUNC [[COPY24]](s32)
; GFX900: [[TRUNC33:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC32]](s16)		; GFX900: [[TRUNC33:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC32]](s16)
; GFX900: [[COPY25:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31		; GFX900: [[COPY25:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; GFX900: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; GFX900: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX900: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)		; GFX900: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; GFX900: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<32 x s32>)
; GFX900: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GFX900: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GFX900: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v32i32		; GFX900: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v32i32
; GFX900: [[COPY26:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GFX900: [[COPY26:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GFX900: [[COPY27:%[0-9]+]]:_(p4) = COPY [[COPY6]]		; GFX900: [[COPY27:%[0-9]+]]:_(p4) = COPY [[COPY6]]
; GFX900: [[COPY28:%[0-9]+]]:_(p4) = COPY [[COPY5]]		; GFX900: [[COPY28:%[0-9]+]]:_(p4) = COPY [[COPY5]]
; GFX900: [[COPY29:%[0-9]+]]:_(s64) = COPY [[COPY4]]		; GFX900: [[COPY29:%[0-9]+]]:_(s64) = COPY [[COPY4]]
; GFX900: [[COPY30:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GFX900: [[COPY30:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX900: [[COPY31:%[0-9]+]]:_(s32) = COPY [[COPY2]]		; GFX900: [[COPY31:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX900: [[COPY32:%[0-9]+]]:_(s32) = COPY [[COPY1]]		; GFX900: [[COPY32:%[0-9]+]]:_(s32) = COPY [[COPY1]]
; GFX900: [[COPY33:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX900: [[COPY33:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX900: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<32 x s32>)
; GFX900: $vgpr0 = COPY [[UV]](s32)		; GFX900: $vgpr0 = COPY [[UV]](s32)
; GFX900: $vgpr1 = COPY [[UV1]](s32)		; GFX900: $vgpr1 = COPY [[UV1]](s32)
; GFX900: $vgpr2 = COPY [[UV2]](s32)		; GFX900: $vgpr2 = COPY [[UV2]](s32)
; GFX900: $vgpr3 = COPY [[UV3]](s32)		; GFX900: $vgpr3 = COPY [[UV3]](s32)
; GFX900: $vgpr4 = COPY [[UV4]](s32)		; GFX900: $vgpr4 = COPY [[UV4]](s32)
; GFX900: $vgpr5 = COPY [[UV5]](s32)		; GFX900: $vgpr5 = COPY [[UV5]](s32)
; GFX900: $vgpr6 = COPY [[UV6]](s32)		; GFX900: $vgpr6 = COPY [[UV6]](s32)
; GFX900: $vgpr7 = COPY [[UV7]](s32)		; GFX900: $vgpr7 = COPY [[UV7]](s32)
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines	define void @test_func_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX908: [[TRUNC30:%[0-9]+]]:_(s16) = G_TRUNC [[COPY23]](s32)		; GFX908: [[TRUNC30:%[0-9]+]]:_(s16) = G_TRUNC [[COPY23]](s32)
; GFX908: [[TRUNC31:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC30]](s16)		; GFX908: [[TRUNC31:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC30]](s16)
; GFX908: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr16		; GFX908: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr16
; GFX908: [[TRUNC32:%[0-9]+]]:_(s16) = G_TRUNC [[COPY24]](s32)		; GFX908: [[TRUNC32:%[0-9]+]]:_(s16) = G_TRUNC [[COPY24]](s32)
; GFX908: [[TRUNC33:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC32]](s16)		; GFX908: [[TRUNC33:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC32]](s16)
; GFX908: [[COPY25:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31		; GFX908: [[COPY25:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; GFX908: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; GFX908: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX908: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)		; GFX908: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; GFX908: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<32 x s32>)
; GFX908: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GFX908: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GFX908: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v32i32		; GFX908: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v32i32
; GFX908: [[COPY26:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GFX908: [[COPY26:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GFX908: [[COPY27:%[0-9]+]]:_(p4) = COPY [[COPY6]]		; GFX908: [[COPY27:%[0-9]+]]:_(p4) = COPY [[COPY6]]
; GFX908: [[COPY28:%[0-9]+]]:_(p4) = COPY [[COPY5]]		; GFX908: [[COPY28:%[0-9]+]]:_(p4) = COPY [[COPY5]]
; GFX908: [[COPY29:%[0-9]+]]:_(s64) = COPY [[COPY4]]		; GFX908: [[COPY29:%[0-9]+]]:_(s64) = COPY [[COPY4]]
; GFX908: [[COPY30:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GFX908: [[COPY30:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GFX908: [[COPY31:%[0-9]+]]:_(s32) = COPY [[COPY2]]		; GFX908: [[COPY31:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; GFX908: [[COPY32:%[0-9]+]]:_(s32) = COPY [[COPY1]]		; GFX908: [[COPY32:%[0-9]+]]:_(s32) = COPY [[COPY1]]
; GFX908: [[COPY33:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX908: [[COPY33:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX908: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<32 x s32>)
; GFX908: $vgpr0 = COPY [[UV]](s32)		; GFX908: $vgpr0 = COPY [[UV]](s32)
; GFX908: $vgpr1 = COPY [[UV1]](s32)		; GFX908: $vgpr1 = COPY [[UV1]](s32)
; GFX908: $vgpr2 = COPY [[UV2]](s32)		; GFX908: $vgpr2 = COPY [[UV2]](s32)
; GFX908: $vgpr3 = COPY [[UV3]](s32)		; GFX908: $vgpr3 = COPY [[UV3]](s32)
; GFX908: $vgpr4 = COPY [[UV4]](s32)		; GFX908: $vgpr4 = COPY [[UV4]](s32)
; GFX908: $vgpr5 = COPY [[UV5]](s32)		; GFX908: $vgpr5 = COPY [[UV5]](s32)
; GFX908: $vgpr6 = COPY [[UV6]](s32)		; GFX908: $vgpr6 = COPY [[UV6]](s32)
; GFX908: $vgpr7 = COPY [[UV7]](s32)		; GFX908: $vgpr7 = COPY [[UV7]](s32)
▲ Show 20 Lines • Show All 666 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines	define amdgpu_gfx void @test_gfx_call_external_void_func_struct_i8_i32() #0 {
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `{ i8, i32 } addrspace(1)* addrspace(4)* undef`, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `{ i8, i32 } addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p1) :: (load 1 from %ir.ptr0, align 4, addrspace 1)		; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p1) :: (load 1 from %ir.ptr0, align 4, addrspace 1)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[LOAD]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[LOAD]], [[C]](s64)
; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load 4 from %ir.ptr0 + 4, addrspace 1)		; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load 4 from %ir.ptr0 + 4, addrspace 1)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_gfx_void_func_struct_i8_i32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_gfx_void_func_struct_i8_i32
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD1]](s8)		; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[LOAD1]](s8)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)		; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)
		; CHECK: $vgpr0 = COPY [[ANYEXT1]](s32)
; CHECK: $vgpr1 = COPY [[LOAD2]](s32)		; CHECK: $vgpr1 = COPY [[LOAD2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3		; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY1]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY1]](<4 x s32>)
; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_gfx_void_func_struct_i8_i32, csr_amdgpu_highregs, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3		; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_gfx_void_func_struct_i8_i32, csr_amdgpu_highregs, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]		; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY2]]		; CHECK: S_SETPC_B64_return [[COPY2]]
%ptr0 = load { i8, i32 } addrspace(1), { i8, i32 } addrspace(1) addrspace(4)* undef		%ptr0 = load { i8, i32 } addrspace(1), { i8, i32 } addrspace(1) addrspace(4)* undef
Show All 10 Lines	define amdgpu_gfx void @test_gfx_call_external_void_func_struct_i8_i32_inreg() #0 {
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `{ i8, i32 } addrspace(1)* addrspace(4)* undef`, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `{ i8, i32 } addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p1) :: (load 1 from %ir.ptr0, align 4, addrspace 1)		; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p1) :: (load 1 from %ir.ptr0, align 4, addrspace 1)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[LOAD]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[LOAD]], [[C]](s64)
; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load 4 from %ir.ptr0 + 4, addrspace 1)		; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load 4 from %ir.ptr0 + 4, addrspace 1)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_gfx_void_func_struct_i8_i32_inreg		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_gfx_void_func_struct_i8_i32_inreg
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD1]](s8)		; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[LOAD1]](s8)
; CHECK: $sgpr4 = COPY [[ANYEXT]](s32)		; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)
		; CHECK: $sgpr4 = COPY [[ANYEXT1]](s32)
; CHECK: $sgpr5 = COPY [[LOAD2]](s32)		; CHECK: $sgpr5 = COPY [[LOAD2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3		; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY1]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY1]](<4 x s32>)
; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_gfx_void_func_struct_i8_i32_inreg, csr_amdgpu_highregs, implicit $sgpr4, implicit $sgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3		; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_gfx_void_func_struct_i8_i32_inreg, csr_amdgpu_highregs, implicit $sgpr4, implicit $sgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]		; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY2]]		; CHECK: S_SETPC_B64_return [[COPY2]]
%ptr0 = load { i8, i32 } addrspace(1), { i8, i32 } addrspace(1) addrspace(4)* undef		%ptr0 = load { i8, i32 } addrspace(1), { i8, i32 } addrspace(1) addrspace(4)* undef
%val = load { i8, i32 }, { i8, i32 } addrspace(1)* %ptr0		%val = load { i8, i32 }, { i8, i32 } addrspace(1)* %ptr0
call amdgpu_gfx void @external_gfx_void_func_struct_i8_i32_inreg({ i8, i32 } inreg %val)		call amdgpu_gfx void @external_gfx_void_func_struct_i8_i32_inreg({ i8, i32 } inreg %val)
ret void		ret void
}		}

attributes #0 = { nounwind }		attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }		attributes #1 = { nounwind readnone }
attributes #2 = { nounwind noinline }		attributes #2 = { nounwind noinline }

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll

Show First 20 Lines • Show All 2,836 Lines • ▼ Show 20 Lines	define amdgpu_kernel void @test_call_external_v33i32_func_v33i32_i32(<33 x i32> addrspace(1)* %p, i32 %idx) #0 {
; GCN: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; GCN: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)		; GCN: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; GCN: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[INT]](p4) :: (dereferenceable invariant load 8 from %ir.p.kernarg.offset.cast, align 16, addrspace 4)		; GCN: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[INT]](p4) :: (dereferenceable invariant load 8 from %ir.p.kernarg.offset.cast, align 16, addrspace 4)
; GCN: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8		; GCN: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; GCN: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[INT]], [[C]](s64)		; GCN: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[INT]], [[C]](s64)
; GCN: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 4 from %ir.idx.kernarg.offset.cast, align 8, addrspace 4)		; GCN: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 4 from %ir.idx.kernarg.offset.cast, align 8, addrspace 4)
; GCN: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0		; GCN: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p1)
; GCN: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v33i32_func_v33i32_i32		; GCN: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v33i32_func_v33i32_i32
; GCN: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; GCN: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16		; GCN: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; GCN: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)		; GCN: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)
; GCN: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)		; GCN: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
; GCN: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; GCN: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)		; GCN: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
; GCN: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN: $vgpr0 = COPY [[FRAME_INDEX]](p5)		; GCN: $vgpr0 = COPY [[FRAME_INDEX]](p5)
		; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p1)
; GCN: $vgpr1 = COPY [[UV]](s32)		; GCN: $vgpr1 = COPY [[UV]](s32)
; GCN: $vgpr2 = COPY [[UV1]](s32)		; GCN: $vgpr2 = COPY [[UV1]](s32)
; GCN: $vgpr3 = COPY [[LOAD1]](s32)		; GCN: $vgpr3 = COPY [[LOAD1]](s32)
; GCN: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; GCN: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; GCN: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4)		; GCN: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4)
Show All 18 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll

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Show First 20 Lines • Show All 507 Lines • ▼ Show 20 Lines	define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s8)		; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[C]](s8)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)		; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)
		; CHECK: $vgpr0 = COPY [[ANYEXT1]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)		; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; CHECK: $sgpr12 = COPY [[COPY14]](s32)		; CHECK: $sgpr12 = COPY [[COPY14]](s32)
; CHECK: $sgpr13 = COPY [[COPY15]](s32)		; CHECK: $sgpr13 = COPY [[COPY15]](s32)
▲ Show 20 Lines • Show All 392 Lines • ▼ Show 20 Lines	define amdgpu_kernel void @test_call_external_void_func_i64_imm() #0 {
; CHECK: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16		; CHECK: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15		; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 123		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 123
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_i64		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_i64
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)		; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
Show All 19 Lines	define amdgpu_kernel void @test_call_external_void_func_v2i64() #0 {
; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15		; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[C]](p1) :: (load 16 from `<2 x i64> addrspace(1)* null`, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[C]](p1) :: (load 16 from `<2 x i64> addrspace(1)* null`, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s64>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v2i64		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v2i64
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s64>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
Show All 23 Lines	define amdgpu_kernel void @test_call_external_void_func_v2i64_imm() #0 {
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934593		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934593
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 17179869187		; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 17179869187
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C1]](s64)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C1]](s64)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s64>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v2i64		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v2i64
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C2]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C2]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s64>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
Show All 22 Lines	define amdgpu_kernel void @test_call_external_void_func_i48(i32) #0 {
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)		; CHECK: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; CHECK: [[LOAD:%[0-9]+]]:_(s48) = G_LOAD [[DEF]](p1) :: (volatile load 6 from `i48 addrspace(1)* undef`, align 8, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(s48) = G_LOAD [[DEF]](p1) :: (volatile load 6 from `i48 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[DEF1:%[0-9]+]]:_(s48) = G_IMPLICIT_DEF
; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[LOAD]](s48), [[DEF1]](s48)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s96)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_i48		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_i48
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[DEF1:%[0-9]+]]:_(s48) = G_IMPLICIT_DEF
		; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[LOAD]](s48), [[DEF1]](s48)
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s96)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)		; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
Show All 21 Lines	define amdgpu_kernel void @test_call_external_void_func_i48_signext(i32) #0 {
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)		; CHECK: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; CHECK: [[LOAD:%[0-9]+]]:_(s48) = G_LOAD [[DEF]](p1) :: (volatile load 6 from `i48 addrspace(1)* undef`, align 8, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(s48) = G_LOAD [[DEF]](p1) :: (volatile load 6 from `i48 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[DEF1:%[0-9]+]]:_(s48) = G_IMPLICIT_DEF
; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[LOAD]](s48), [[DEF1]](s48)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s96)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_i48_signext		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_i48_signext
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[DEF1:%[0-9]+]]:_(s48) = G_IMPLICIT_DEF
		; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[LOAD]](s48), [[DEF1]](s48)
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s96)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)		; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
Show All 21 Lines	define amdgpu_kernel void @test_call_external_void_func_i48_zeroext(i32) #0 {
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)		; CHECK: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; CHECK: [[LOAD:%[0-9]+]]:_(s48) = G_LOAD [[DEF]](p1) :: (volatile load 6 from `i48 addrspace(1)* undef`, align 8, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(s48) = G_LOAD [[DEF]](p1) :: (volatile load 6 from `i48 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[DEF1:%[0-9]+]]:_(s48) = G_IMPLICIT_DEF
; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[LOAD]](s48), [[DEF1]](s48)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s96)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_i48_zeroext		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_i48_zeroext
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[DEF1:%[0-9]+]]:_(s48) = G_IMPLICIT_DEF
		; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[LOAD]](s48), [[DEF1]](s48)
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s96)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)		; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
Show All 20 Lines	define amdgpu_kernel void @test_call_external_void_func_p0_imm(i8* %arg) #0 {
; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15		; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)		; CHECK: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[INT]](p4) :: (dereferenceable invariant load 8 from %ir.arg.kernarg.offset.cast, align 16, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[INT]](p4) :: (dereferenceable invariant load 8 from %ir.arg.kernarg.offset.cast, align 16, addrspace 4)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p0)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_p0		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_p0
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p0)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)		; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
Show All 19 Lines	define amdgpu_kernel void @test_call_external_void_func_v2p0() #0 {
; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15		; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
; CHECK: [[LOAD:%[0-9]+]]:_(<2 x p0>) = G_LOAD [[C]](p1) :: (load 16 from `<2 x i8> addrspace(1) null`, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(<2 x p0>) = G_LOAD [[C]](p1) :: (load 16 from `<2 x i8> addrspace(1) null`, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x p0>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v2p0		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v2p0
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x p0>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
Show All 26 Lines	define amdgpu_kernel void @test_call_external_void_func_v3i64() #0 {
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934593		; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934593
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[DEF]](s64)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[DEF]](s64)
; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[C]](p1) :: (load 16 from `<2 x i64> addrspace(1)* null`, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[C]](p1) :: (load 16 from `<2 x i64> addrspace(1)* null`, addrspace 1)
; CHECK: [[SHUF:%[0-9]+]]:_(<3 x s64>) = G_SHUFFLE_VECTOR [[LOAD]](<2 x s64>), [[BUILD_VECTOR]], shufflemask(0, 1, 2)		; CHECK: [[SHUF:%[0-9]+]]:_(<3 x s64>) = G_SHUFFLE_VECTOR [[LOAD]](<2 x s64>), [[BUILD_VECTOR]], shufflemask(0, 1, 2)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SHUF]](<3 x s64>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v3i64		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v3i64
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C2]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C2]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SHUF]](<3 x s64>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: $vgpr5 = COPY [[UV5]](s32)		; CHECK: $vgpr5 = COPY [[UV5]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
Show All 30 Lines	define amdgpu_kernel void @test_call_external_void_func_v4i64() #0 {
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934593		; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934593
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 17179869187		; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 17179869187
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C2]](s64)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C2]](s64)
; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[C]](p1) :: (load 16 from `<2 x i64> addrspace(1)* null`, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[C]](p1) :: (load 16 from `<2 x i64> addrspace(1)* null`, addrspace 1)
; CHECK: [[SHUF:%[0-9]+]]:_(<4 x s64>) = G_SHUFFLE_VECTOR [[LOAD]](<2 x s64>), [[BUILD_VECTOR]], shufflemask(0, 1, 2, 3)		; CHECK: [[SHUF:%[0-9]+]]:_(<4 x s64>) = G_SHUFFLE_VECTOR [[LOAD]](<2 x s64>), [[BUILD_VECTOR]], shufflemask(0, 1, 2, 3)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SHUF]](<4 x s64>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v4i64		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v4i64
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C3]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C3]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SHUF]](<4 x s64>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: $vgpr5 = COPY [[UV5]](s32)		; CHECK: $vgpr5 = COPY [[UV5]](s32)
; CHECK: $vgpr6 = COPY [[UV6]](s32)		; CHECK: $vgpr6 = COPY [[UV6]](s32)
; CHECK: $vgpr7 = COPY [[UV7]](s32)		; CHECK: $vgpr7 = COPY [[UV7]](s32)
▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines	define amdgpu_kernel void @test_call_external_void_func_v2f32_imm() #0 {
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00		; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v2f32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v2f32
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C2]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C2]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)		; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
Show All 21 Lines	define amdgpu_kernel void @test_call_external_void_func_v3f32_imm() #0 {
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00		; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v3f32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v3f32
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C3]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C3]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
Show All 24 Lines	define amdgpu_kernel void @test_call_external_void_func_v5f32_imm() #0 {
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00		; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<5 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v5f32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v5f32
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C5]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C5]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C6]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C6]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C7]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C7]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<5 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
Show All 21 Lines	define amdgpu_kernel void @test_call_external_void_func_f64_imm() #0 {
; CHECK: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16		; CHECK: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15		; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 4.000000e+00		; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 4.000000e+00
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_f64		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_f64
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)		; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
Show All 20 Lines	define amdgpu_kernel void @test_call_external_void_func_v2f64_imm() #0 {
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00		; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 4.000000e+00		; CHECK: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 4.000000e+00
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C1]](s64)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C1]](s64)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s64>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v2f64		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v2f64
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C2]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C2]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s64>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
Show All 23 Lines	define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 {
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00		; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 4.000000e+00		; CHECK: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 4.000000e+00
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 8.000000e+00		; CHECK: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 8.000000e+00
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C1]](s64), [[C2]](s64)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C1]](s64), [[C2]](s64)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s64>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v3f64		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v3f64
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C3]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C3]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s64>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: $vgpr5 = COPY [[UV5]](s32)		; CHECK: $vgpr5 = COPY [[UV5]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines	define amdgpu_kernel void @test_call_external_void_func_v3i16() #0 {
; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15		; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(<3 x s16>) = G_LOAD [[DEF]](p1) :: (load 6 from `<3 x i16> addrspace(1)* undef`, align 8, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(<3 x s16>) = G_LOAD [[DEF]](p1) :: (load 6 from `<3 x i16> addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[DEF1:%[0-9]+]]:_(<3 x s16>) = G_IMPLICIT_DEF
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[LOAD]](<3 x s16>), [[DEF1]](<3 x s16>)
; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v3i16		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v3i16
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[DEF1:%[0-9]+]]:_(<3 x s16>) = G_IMPLICIT_DEF
		; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[LOAD]](<3 x s16>), [[DEF1]](<3 x s16>)
		; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)		; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)
; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)		; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)		; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
Show All 20 Lines	define amdgpu_kernel void @test_call_external_void_func_v3f16() #0 {
; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15		; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(<3 x s16>) = G_LOAD [[DEF]](p1) :: (load 6 from `<3 x half> addrspace(1)* undef`, align 8, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(<3 x s16>) = G_LOAD [[DEF]](p1) :: (load 6 from `<3 x half> addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[DEF1:%[0-9]+]]:_(<3 x s16>) = G_IMPLICIT_DEF
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[LOAD]](<3 x s16>), [[DEF1]](<3 x s16>)
; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v3f16		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v3f16
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[DEF1:%[0-9]+]]:_(<3 x s16>) = G_IMPLICIT_DEF
		; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[LOAD]](<3 x s16>), [[DEF1]](<3 x s16>)
		; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)		; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)
; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)		; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)		; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
Show All 20 Lines	define amdgpu_kernel void @test_call_external_void_func_v4i16() #0 {
; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15		; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[DEF]](p1) :: (load 8 from `<4 x i16> addrspace(1)* undef`, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[DEF]](p1) :: (load 8 from `<4 x i16> addrspace(1)* undef`, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[LOAD]](<4 x s16>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v4i16		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v4i16
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[LOAD]](<4 x s16>)
; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)		; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)
; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)		; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)		; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
Show All 23 Lines	define amdgpu_kernel void @test_call_external_void_func_v4i16_imm() #0 {
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1		; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 2		; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 3		; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 3
; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 4		; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C1]](s16), [[C2]](s16), [[C3]](s16)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C1]](s16), [[C2]](s16), [[C3]](s16)
; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s16>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v4i16		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v4i16
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C4]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C4]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C5]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C5]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C6]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C6]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s16>)
; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)		; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)
; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)		; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)		; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
Show All 19 Lines	define amdgpu_kernel void @test_call_external_void_func_v5i16() #0 {
; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15		; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(<5 x s16>) = G_LOAD [[DEF]](p1) :: (load 10 from `<5 x i16> addrspace(1)* undef`, align 16, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(<5 x s16>) = G_LOAD [[DEF]](p1) :: (load 10 from `<5 x i16> addrspace(1)* undef`, align 16, addrspace 1)
; CHECK: [[DEF1:%[0-9]+]]:_(<5 x s16>) = G_IMPLICIT_DEF
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<10 x s16>) = G_CONCAT_VECTORS [[LOAD]](<5 x s16>), [[DEF1]](<5 x s16>)
; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<10 x s16>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v5i16		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v5i16
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[DEF1:%[0-9]+]]:_(<5 x s16>) = G_IMPLICIT_DEF
		; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<10 x s16>) = G_CONCAT_VECTORS [[LOAD]](<5 x s16>), [[DEF1]](<5 x s16>)
		; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<10 x s16>)
; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)		; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)
; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)		; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)
; CHECK: $vgpr2 = COPY [[UV2]](<2 x s16>)		; CHECK: $vgpr2 = COPY [[UV2]](<2 x s16>)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
Show All 21 Lines	define amdgpu_kernel void @test_call_external_void_func_v7i16() #0 {
; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15		; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(<7 x s16>) = G_LOAD [[DEF]](p1) :: (load 14 from `<7 x i16> addrspace(1)* undef`, align 16, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(<7 x s16>) = G_LOAD [[DEF]](p1) :: (load 14 from `<7 x i16> addrspace(1)* undef`, align 16, addrspace 1)
; CHECK: [[DEF1:%[0-9]+]]:_(<7 x s16>) = G_IMPLICIT_DEF
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<14 x s16>) = G_CONCAT_VECTORS [[LOAD]](<7 x s16>), [[DEF1]](<7 x s16>)
; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<14 x s16>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v7i16		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v7i16
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[DEF1:%[0-9]+]]:_(<7 x s16>) = G_IMPLICIT_DEF
		; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<14 x s16>) = G_CONCAT_VECTORS [[LOAD]](<7 x s16>), [[DEF1]](<7 x s16>)
		; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<14 x s16>)
; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)		; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)
; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)		; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)
; CHECK: $vgpr2 = COPY [[UV2]](<2 x s16>)		; CHECK: $vgpr2 = COPY [[UV2]](<2 x s16>)
; CHECK: $vgpr3 = COPY [[UV3]](<2 x s16>)		; CHECK: $vgpr3 = COPY [[UV3]](<2 x s16>)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
Show All 22 Lines	define amdgpu_kernel void @test_call_external_void_func_v63i16() #0 {
; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15		; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(<63 x s16>) = G_LOAD [[DEF]](p1) :: (load 126 from `<63 x i16> addrspace(1)* undef`, align 128, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(<63 x s16>) = G_LOAD [[DEF]](p1) :: (load 126 from `<63 x i16> addrspace(1)* undef`, align 128, addrspace 1)
; CHECK: [[DEF1:%[0-9]+]]:_(<63 x s16>) = G_IMPLICIT_DEF
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<126 x s16>) = G_CONCAT_VECTORS [[LOAD]](<63 x s16>), [[DEF1]](<63 x s16>)
; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>), [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>), [[UV14:%[0-9]+]]:_(<2 x s16>), [[UV15:%[0-9]+]]:_(<2 x s16>), [[UV16:%[0-9]+]]:_(<2 x s16>), [[UV17:%[0-9]+]]:_(<2 x s16>), [[UV18:%[0-9]+]]:_(<2 x s16>), [[UV19:%[0-9]+]]:_(<2 x s16>), [[UV20:%[0-9]+]]:_(<2 x s16>), [[UV21:%[0-9]+]]:_(<2 x s16>), [[UV22:%[0-9]+]]:_(<2 x s16>), [[UV23:%[0-9]+]]:_(<2 x s16>), [[UV24:%[0-9]+]]:_(<2 x s16>), [[UV25:%[0-9]+]]:_(<2 x s16>), [[UV26:%[0-9]+]]:_(<2 x s16>), [[UV27:%[0-9]+]]:_(<2 x s16>), [[UV28:%[0-9]+]]:_(<2 x s16>), [[UV29:%[0-9]+]]:_(<2 x s16>), [[UV30:%[0-9]+]]:_(<2 x s16>), [[UV31:%[0-9]+]]:_(<2 x s16>), [[UV32:%[0-9]+]]:_(<2 x s16>), [[UV33:%[0-9]+]]:_(<2 x s16>), [[UV34:%[0-9]+]]:_(<2 x s16>), [[UV35:%[0-9]+]]:_(<2 x s16>), [[UV36:%[0-9]+]]:_(<2 x s16>), [[UV37:%[0-9]+]]:_(<2 x s16>), [[UV38:%[0-9]+]]:_(<2 x s16>), [[UV39:%[0-9]+]]:_(<2 x s16>), [[UV40:%[0-9]+]]:_(<2 x s16>), [[UV41:%[0-9]+]]:_(<2 x s16>), [[UV42:%[0-9]+]]:_(<2 x s16>), [[UV43:%[0-9]+]]:_(<2 x s16>), [[UV44:%[0-9]+]]:_(<2 x s16>), [[UV45:%[0-9]+]]:_(<2 x s16>), [[UV46:%[0-9]+]]:_(<2 x s16>), [[UV47:%[0-9]+]]:_(<2 x s16>), [[UV48:%[0-9]+]]:_(<2 x s16>), [[UV49:%[0-9]+]]:_(<2 x s16>), [[UV50:%[0-9]+]]:_(<2 x s16>), [[UV51:%[0-9]+]]:_(<2 x s16>), [[UV52:%[0-9]+]]:_(<2 x s16>), [[UV53:%[0-9]+]]:_(<2 x s16>), [[UV54:%[0-9]+]]:_(<2 x s16>), [[UV55:%[0-9]+]]:_(<2 x s16>), [[UV56:%[0-9]+]]:_(<2 x s16>), [[UV57:%[0-9]+]]:_(<2 x s16>), [[UV58:%[0-9]+]]:_(<2 x s16>), [[UV59:%[0-9]+]]:_(<2 x s16>), [[UV60:%[0-9]+]]:_(<2 x s16>), [[UV61:%[0-9]+]]:_(<2 x s16>), [[UV62:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<126 x s16>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v63i16		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v63i16
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[DEF1:%[0-9]+]]:_(<63 x s16>) = G_IMPLICIT_DEF
		; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<126 x s16>) = G_CONCAT_VECTORS [[LOAD]](<63 x s16>), [[DEF1]](<63 x s16>)
		; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>), [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>), [[UV14:%[0-9]+]]:_(<2 x s16>), [[UV15:%[0-9]+]]:_(<2 x s16>), [[UV16:%[0-9]+]]:_(<2 x s16>), [[UV17:%[0-9]+]]:_(<2 x s16>), [[UV18:%[0-9]+]]:_(<2 x s16>), [[UV19:%[0-9]+]]:_(<2 x s16>), [[UV20:%[0-9]+]]:_(<2 x s16>), [[UV21:%[0-9]+]]:_(<2 x s16>), [[UV22:%[0-9]+]]:_(<2 x s16>), [[UV23:%[0-9]+]]:_(<2 x s16>), [[UV24:%[0-9]+]]:_(<2 x s16>), [[UV25:%[0-9]+]]:_(<2 x s16>), [[UV26:%[0-9]+]]:_(<2 x s16>), [[UV27:%[0-9]+]]:_(<2 x s16>), [[UV28:%[0-9]+]]:_(<2 x s16>), [[UV29:%[0-9]+]]:_(<2 x s16>), [[UV30:%[0-9]+]]:_(<2 x s16>), [[UV31:%[0-9]+]]:_(<2 x s16>), [[UV32:%[0-9]+]]:_(<2 x s16>), [[UV33:%[0-9]+]]:_(<2 x s16>), [[UV34:%[0-9]+]]:_(<2 x s16>), [[UV35:%[0-9]+]]:_(<2 x s16>), [[UV36:%[0-9]+]]:_(<2 x s16>), [[UV37:%[0-9]+]]:_(<2 x s16>), [[UV38:%[0-9]+]]:_(<2 x s16>), [[UV39:%[0-9]+]]:_(<2 x s16>), [[UV40:%[0-9]+]]:_(<2 x s16>), [[UV41:%[0-9]+]]:_(<2 x s16>), [[UV42:%[0-9]+]]:_(<2 x s16>), [[UV43:%[0-9]+]]:_(<2 x s16>), [[UV44:%[0-9]+]]:_(<2 x s16>), [[UV45:%[0-9]+]]:_(<2 x s16>), [[UV46:%[0-9]+]]:_(<2 x s16>), [[UV47:%[0-9]+]]:_(<2 x s16>), [[UV48:%[0-9]+]]:_(<2 x s16>), [[UV49:%[0-9]+]]:_(<2 x s16>), [[UV50:%[0-9]+]]:_(<2 x s16>), [[UV51:%[0-9]+]]:_(<2 x s16>), [[UV52:%[0-9]+]]:_(<2 x s16>), [[UV53:%[0-9]+]]:_(<2 x s16>), [[UV54:%[0-9]+]]:_(<2 x s16>), [[UV55:%[0-9]+]]:_(<2 x s16>), [[UV56:%[0-9]+]]:_(<2 x s16>), [[UV57:%[0-9]+]]:_(<2 x s16>), [[UV58:%[0-9]+]]:_(<2 x s16>), [[UV59:%[0-9]+]]:_(<2 x s16>), [[UV60:%[0-9]+]]:_(<2 x s16>), [[UV61:%[0-9]+]]:_(<2 x s16>), [[UV62:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<126 x s16>)
; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)		; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)
; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)		; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)
; CHECK: $vgpr2 = COPY [[UV2]](<2 x s16>)		; CHECK: $vgpr2 = COPY [[UV2]](<2 x s16>)
; CHECK: $vgpr3 = COPY [[UV3]](<2 x s16>)		; CHECK: $vgpr3 = COPY [[UV3]](<2 x s16>)
; CHECK: $vgpr4 = COPY [[UV4]](<2 x s16>)		; CHECK: $vgpr4 = COPY [[UV4]](<2 x s16>)
; CHECK: $vgpr5 = COPY [[UV5]](<2 x s16>)		; CHECK: $vgpr5 = COPY [[UV5]](<2 x s16>)
; CHECK: $vgpr6 = COPY [[UV6]](<2 x s16>)		; CHECK: $vgpr6 = COPY [[UV6]](<2 x s16>)
; CHECK: $vgpr7 = COPY [[UV7]](<2 x s16>)		; CHECK: $vgpr7 = COPY [[UV7]](<2 x s16>)
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines	define amdgpu_kernel void @test_call_external_void_func_v65i16() #0 {
; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15		; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(<65 x s16>) = G_LOAD [[DEF]](p1) :: (load 130 from `<65 x i16> addrspace(1)* undef`, align 256, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(<65 x s16>) = G_LOAD [[DEF]](p1) :: (load 130 from `<65 x i16> addrspace(1)* undef`, align 256, addrspace 1)
; CHECK: [[DEF1:%[0-9]+]]:_(<65 x s16>) = G_IMPLICIT_DEF
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<130 x s16>) = G_CONCAT_VECTORS [[LOAD]](<65 x s16>), [[DEF1]](<65 x s16>)
; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>), [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>), [[UV14:%[0-9]+]]:_(<2 x s16>), [[UV15:%[0-9]+]]:_(<2 x s16>), [[UV16:%[0-9]+]]:_(<2 x s16>), [[UV17:%[0-9]+]]:_(<2 x s16>), [[UV18:%[0-9]+]]:_(<2 x s16>), [[UV19:%[0-9]+]]:_(<2 x s16>), [[UV20:%[0-9]+]]:_(<2 x s16>), [[UV21:%[0-9]+]]:_(<2 x s16>), [[UV22:%[0-9]+]]:_(<2 x s16>), [[UV23:%[0-9]+]]:_(<2 x s16>), [[UV24:%[0-9]+]]:_(<2 x s16>), [[UV25:%[0-9]+]]:_(<2 x s16>), [[UV26:%[0-9]+]]:_(<2 x s16>), [[UV27:%[0-9]+]]:_(<2 x s16>), [[UV28:%[0-9]+]]:_(<2 x s16>), [[UV29:%[0-9]+]]:_(<2 x s16>), [[UV30:%[0-9]+]]:_(<2 x s16>), [[UV31:%[0-9]+]]:_(<2 x s16>), [[UV32:%[0-9]+]]:_(<2 x s16>), [[UV33:%[0-9]+]]:_(<2 x s16>), [[UV34:%[0-9]+]]:_(<2 x s16>), [[UV35:%[0-9]+]]:_(<2 x s16>), [[UV36:%[0-9]+]]:_(<2 x s16>), [[UV37:%[0-9]+]]:_(<2 x s16>), [[UV38:%[0-9]+]]:_(<2 x s16>), [[UV39:%[0-9]+]]:_(<2 x s16>), [[UV40:%[0-9]+]]:_(<2 x s16>), [[UV41:%[0-9]+]]:_(<2 x s16>), [[UV42:%[0-9]+]]:_(<2 x s16>), [[UV43:%[0-9]+]]:_(<2 x s16>), [[UV44:%[0-9]+]]:_(<2 x s16>), [[UV45:%[0-9]+]]:_(<2 x s16>), [[UV46:%[0-9]+]]:_(<2 x s16>), [[UV47:%[0-9]+]]:_(<2 x s16>), [[UV48:%[0-9]+]]:_(<2 x s16>), [[UV49:%[0-9]+]]:_(<2 x s16>), [[UV50:%[0-9]+]]:_(<2 x s16>), [[UV51:%[0-9]+]]:_(<2 x s16>), [[UV52:%[0-9]+]]:_(<2 x s16>), [[UV53:%[0-9]+]]:_(<2 x s16>), [[UV54:%[0-9]+]]:_(<2 x s16>), [[UV55:%[0-9]+]]:_(<2 x s16>), [[UV56:%[0-9]+]]:_(<2 x s16>), [[UV57:%[0-9]+]]:_(<2 x s16>), [[UV58:%[0-9]+]]:_(<2 x s16>), [[UV59:%[0-9]+]]:_(<2 x s16>), [[UV60:%[0-9]+]]:_(<2 x s16>), [[UV61:%[0-9]+]]:_(<2 x s16>), [[UV62:%[0-9]+]]:_(<2 x s16>), [[UV63:%[0-9]+]]:_(<2 x s16>), [[UV64:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<130 x s16>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v65i16		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v65i16
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[DEF1:%[0-9]+]]:_(<65 x s16>) = G_IMPLICIT_DEF
		; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<130 x s16>) = G_CONCAT_VECTORS [[LOAD]](<65 x s16>), [[DEF1]](<65 x s16>)
		; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>), [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>), [[UV14:%[0-9]+]]:_(<2 x s16>), [[UV15:%[0-9]+]]:_(<2 x s16>), [[UV16:%[0-9]+]]:_(<2 x s16>), [[UV17:%[0-9]+]]:_(<2 x s16>), [[UV18:%[0-9]+]]:_(<2 x s16>), [[UV19:%[0-9]+]]:_(<2 x s16>), [[UV20:%[0-9]+]]:_(<2 x s16>), [[UV21:%[0-9]+]]:_(<2 x s16>), [[UV22:%[0-9]+]]:_(<2 x s16>), [[UV23:%[0-9]+]]:_(<2 x s16>), [[UV24:%[0-9]+]]:_(<2 x s16>), [[UV25:%[0-9]+]]:_(<2 x s16>), [[UV26:%[0-9]+]]:_(<2 x s16>), [[UV27:%[0-9]+]]:_(<2 x s16>), [[UV28:%[0-9]+]]:_(<2 x s16>), [[UV29:%[0-9]+]]:_(<2 x s16>), [[UV30:%[0-9]+]]:_(<2 x s16>), [[UV31:%[0-9]+]]:_(<2 x s16>), [[UV32:%[0-9]+]]:_(<2 x s16>), [[UV33:%[0-9]+]]:_(<2 x s16>), [[UV34:%[0-9]+]]:_(<2 x s16>), [[UV35:%[0-9]+]]:_(<2 x s16>), [[UV36:%[0-9]+]]:_(<2 x s16>), [[UV37:%[0-9]+]]:_(<2 x s16>), [[UV38:%[0-9]+]]:_(<2 x s16>), [[UV39:%[0-9]+]]:_(<2 x s16>), [[UV40:%[0-9]+]]:_(<2 x s16>), [[UV41:%[0-9]+]]:_(<2 x s16>), [[UV42:%[0-9]+]]:_(<2 x s16>), [[UV43:%[0-9]+]]:_(<2 x s16>), [[UV44:%[0-9]+]]:_(<2 x s16>), [[UV45:%[0-9]+]]:_(<2 x s16>), [[UV46:%[0-9]+]]:_(<2 x s16>), [[UV47:%[0-9]+]]:_(<2 x s16>), [[UV48:%[0-9]+]]:_(<2 x s16>), [[UV49:%[0-9]+]]:_(<2 x s16>), [[UV50:%[0-9]+]]:_(<2 x s16>), [[UV51:%[0-9]+]]:_(<2 x s16>), [[UV52:%[0-9]+]]:_(<2 x s16>), [[UV53:%[0-9]+]]:_(<2 x s16>), [[UV54:%[0-9]+]]:_(<2 x s16>), [[UV55:%[0-9]+]]:_(<2 x s16>), [[UV56:%[0-9]+]]:_(<2 x s16>), [[UV57:%[0-9]+]]:_(<2 x s16>), [[UV58:%[0-9]+]]:_(<2 x s16>), [[UV59:%[0-9]+]]:_(<2 x s16>), [[UV60:%[0-9]+]]:_(<2 x s16>), [[UV61:%[0-9]+]]:_(<2 x s16>), [[UV62:%[0-9]+]]:_(<2 x s16>), [[UV63:%[0-9]+]]:_(<2 x s16>), [[UV64:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<130 x s16>)
; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)		; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)
; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)		; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)
; CHECK: $vgpr2 = COPY [[UV2]](<2 x s16>)		; CHECK: $vgpr2 = COPY [[UV2]](<2 x s16>)
; CHECK: $vgpr3 = COPY [[UV3]](<2 x s16>)		; CHECK: $vgpr3 = COPY [[UV3]](<2 x s16>)
; CHECK: $vgpr4 = COPY [[UV4]](<2 x s16>)		; CHECK: $vgpr4 = COPY [[UV4]](<2 x s16>)
; CHECK: $vgpr5 = COPY [[UV5]](<2 x s16>)		; CHECK: $vgpr5 = COPY [[UV5]](<2 x s16>)
; CHECK: $vgpr6 = COPY [[UV6]](<2 x s16>)		; CHECK: $vgpr6 = COPY [[UV6]](<2 x s16>)
; CHECK: $vgpr7 = COPY [[UV7]](<2 x s16>)		; CHECK: $vgpr7 = COPY [[UV7]](<2 x s16>)
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines	define amdgpu_kernel void @test_call_external_void_func_v66i16() #0 {
; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15		; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(<66 x s16>) = G_LOAD [[DEF]](p1) :: (load 132 from `<66 x i16> addrspace(1)* undef`, align 256, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(<66 x s16>) = G_LOAD [[DEF]](p1) :: (load 132 from `<66 x i16> addrspace(1)* undef`, align 256, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>), [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>), [[UV14:%[0-9]+]]:_(<2 x s16>), [[UV15:%[0-9]+]]:_(<2 x s16>), [[UV16:%[0-9]+]]:_(<2 x s16>), [[UV17:%[0-9]+]]:_(<2 x s16>), [[UV18:%[0-9]+]]:_(<2 x s16>), [[UV19:%[0-9]+]]:_(<2 x s16>), [[UV20:%[0-9]+]]:_(<2 x s16>), [[UV21:%[0-9]+]]:_(<2 x s16>), [[UV22:%[0-9]+]]:_(<2 x s16>), [[UV23:%[0-9]+]]:_(<2 x s16>), [[UV24:%[0-9]+]]:_(<2 x s16>), [[UV25:%[0-9]+]]:_(<2 x s16>), [[UV26:%[0-9]+]]:_(<2 x s16>), [[UV27:%[0-9]+]]:_(<2 x s16>), [[UV28:%[0-9]+]]:_(<2 x s16>), [[UV29:%[0-9]+]]:_(<2 x s16>), [[UV30:%[0-9]+]]:_(<2 x s16>), [[UV31:%[0-9]+]]:_(<2 x s16>), [[UV32:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[LOAD]](<66 x s16>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v66i16		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v66i16
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>), [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>), [[UV14:%[0-9]+]]:_(<2 x s16>), [[UV15:%[0-9]+]]:_(<2 x s16>), [[UV16:%[0-9]+]]:_(<2 x s16>), [[UV17:%[0-9]+]]:_(<2 x s16>), [[UV18:%[0-9]+]]:_(<2 x s16>), [[UV19:%[0-9]+]]:_(<2 x s16>), [[UV20:%[0-9]+]]:_(<2 x s16>), [[UV21:%[0-9]+]]:_(<2 x s16>), [[UV22:%[0-9]+]]:_(<2 x s16>), [[UV23:%[0-9]+]]:_(<2 x s16>), [[UV24:%[0-9]+]]:_(<2 x s16>), [[UV25:%[0-9]+]]:_(<2 x s16>), [[UV26:%[0-9]+]]:_(<2 x s16>), [[UV27:%[0-9]+]]:_(<2 x s16>), [[UV28:%[0-9]+]]:_(<2 x s16>), [[UV29:%[0-9]+]]:_(<2 x s16>), [[UV30:%[0-9]+]]:_(<2 x s16>), [[UV31:%[0-9]+]]:_(<2 x s16>), [[UV32:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[LOAD]](<66 x s16>)
; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)		; CHECK: $vgpr0 = COPY [[UV]](<2 x s16>)
; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)		; CHECK: $vgpr1 = COPY [[UV1]](<2 x s16>)
; CHECK: $vgpr2 = COPY [[UV2]](<2 x s16>)		; CHECK: $vgpr2 = COPY [[UV2]](<2 x s16>)
; CHECK: $vgpr3 = COPY [[UV3]](<2 x s16>)		; CHECK: $vgpr3 = COPY [[UV3]](<2 x s16>)
; CHECK: $vgpr4 = COPY [[UV4]](<2 x s16>)		; CHECK: $vgpr4 = COPY [[UV4]](<2 x s16>)
; CHECK: $vgpr5 = COPY [[UV5]](<2 x s16>)		; CHECK: $vgpr5 = COPY [[UV5]](<2 x s16>)
; CHECK: $vgpr6 = COPY [[UV6]](<2 x s16>)		; CHECK: $vgpr6 = COPY [[UV6]](<2 x s16>)
; CHECK: $vgpr7 = COPY [[UV7]](<2 x s16>)		; CHECK: $vgpr7 = COPY [[UV7]](<2 x s16>)
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines	define amdgpu_kernel void @test_call_external_void_func_v2i32() #0 {
; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15		; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[DEF]](p1) :: (load 8 from `<2 x i32> addrspace(1)* undef`, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[DEF]](p1) :: (load 8 from `<2 x i32> addrspace(1)* undef`, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v2i32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v2i32
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)		; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
Show All 21 Lines	define amdgpu_kernel void @test_call_external_void_func_v2i32_imm() #0 {
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1		; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v2i32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v2i32
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C2]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C2]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)		; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
Show All 22 Lines	define amdgpu_kernel void @test_call_external_void_func_v3i32_imm(i32) #0 {
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3		; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 5		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32)
; CHECK: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)		; CHECK: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v3i32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v3i32
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4		; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C3]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C3]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
Show All 24 Lines	define amdgpu_kernel void @test_call_external_void_func_v3i32_i32(i32) #0 {
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3		; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 5		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 6		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; CHECK: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)		; CHECK: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v3i32_i32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v3i32_i32
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4		; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C4]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C4]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C5]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C5]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C6]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C6]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[C3]](s32)		; CHECK: $vgpr3 = COPY [[C3]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
Show All 21 Lines	define amdgpu_kernel void @test_call_external_void_func_v4i32() #0 {
; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15		; CHECK: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[DEF]](p1) :: (load 16 from `<4 x i32> addrspace(1)* undef`, addrspace 1)		; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[DEF]](p1) :: (load 16 from `<4 x i32> addrspace(1)* undef`, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<4 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v4i32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v4i32
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<4 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
Show All 25 Lines	define amdgpu_kernel void @test_call_external_void_func_v4i32_imm() #0 {
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1		; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v4i32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v4i32
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C4]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C4]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C5]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C5]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C6]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C6]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
Show All 25 Lines	define amdgpu_kernel void @test_call_external_void_func_v5i32_imm() #0 {
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1		; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<5 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v5i32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v5i32
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C5]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C5]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C6]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C6]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C7]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C7]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<5 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
Show All 23 Lines	define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 {
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<8 x i32> addrspace(1)* addrspace(4)* undef`, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<8 x i32> addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[LOAD]](p1) :: (load 32 from %ir.ptr, addrspace 1)		; CHECK: [[LOAD1:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[LOAD]](p1) :: (load 32 from %ir.ptr, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<8 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v8i32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v8i32
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<8 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: $vgpr5 = COPY [[UV5]](s32)		; CHECK: $vgpr5 = COPY [[UV5]](s32)
; CHECK: $vgpr6 = COPY [[UV6]](s32)		; CHECK: $vgpr6 = COPY [[UV6]](s32)
; CHECK: $vgpr7 = COPY [[UV7]](s32)		; CHECK: $vgpr7 = COPY [[UV7]](s32)
Show All 34 Lines	define amdgpu_kernel void @test_call_external_void_func_v8i32_imm() #0 {
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 6		; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 7		; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8		; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32), [[C5]](s32), [[C6]](s32), [[C7]](s32)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32), [[C5]](s32), [[C6]](s32), [[C7]](s32)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v8i32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v8i32
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C8]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C8]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C9]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C9]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C10]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C10]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: $vgpr5 = COPY [[UV5]](s32)		; CHECK: $vgpr5 = COPY [[UV5]](s32)
; CHECK: $vgpr6 = COPY [[UV6]](s32)		; CHECK: $vgpr6 = COPY [[UV6]](s32)
; CHECK: $vgpr7 = COPY [[UV7]](s32)		; CHECK: $vgpr7 = COPY [[UV7]](s32)
Show All 26 Lines	define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<16 x i32> addrspace(1)* addrspace(4)* undef`, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<16 x i32> addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[LOAD]](p1) :: (load 64 from %ir.ptr, addrspace 1)		; CHECK: [[LOAD1:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[LOAD]](p1) :: (load 64 from %ir.ptr, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<16 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v16i32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v16i32
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<16 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: $vgpr5 = COPY [[UV5]](s32)		; CHECK: $vgpr5 = COPY [[UV5]](s32)
; CHECK: $vgpr6 = COPY [[UV6]](s32)		; CHECK: $vgpr6 = COPY [[UV6]](s32)
; CHECK: $vgpr7 = COPY [[UV7]](s32)		; CHECK: $vgpr7 = COPY [[UV7]](s32)
Show All 36 Lines	define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 {
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<32 x i32> addrspace(1)* addrspace(4)* undef`, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<32 x i32> addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[LOAD]](p1) :: (load 128 from %ir.ptr, addrspace 1)		; CHECK: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[LOAD]](p1) :: (load 128 from %ir.ptr, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<32 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v32i32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v32i32
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<32 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: $vgpr5 = COPY [[UV5]](s32)		; CHECK: $vgpr5 = COPY [[UV5]](s32)
; CHECK: $vgpr6 = COPY [[UV6]](s32)		; CHECK: $vgpr6 = COPY [[UV6]](s32)
; CHECK: $vgpr7 = COPY [[UV7]](s32)		; CHECK: $vgpr7 = COPY [[UV7]](s32)
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines	define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)		; CHECK: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<32 x i32> addrspace(1)* addrspace(4)* undef`, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<32 x i32> addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[LOAD]](p1) :: (load 128 from %ir.ptr0, addrspace 1)		; CHECK: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[LOAD]](p1) :: (load 128 from %ir.ptr0, addrspace 1)
; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[DEF1]](p1) :: (load 4 from `i32 addrspace(1)* undef`, addrspace 1)		; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[DEF1]](p1) :: (load 4 from `i32 addrspace(1)* undef`, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<32 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v32i32_i32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v32i32_i32
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<32 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: $vgpr5 = COPY [[UV5]](s32)		; CHECK: $vgpr5 = COPY [[UV5]](s32)
; CHECK: $vgpr6 = COPY [[UV6]](s32)		; CHECK: $vgpr6 = COPY [[UV6]](s32)
; CHECK: $vgpr7 = COPY [[UV7]](s32)		; CHECK: $vgpr7 = COPY [[UV7]](s32)
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines	define amdgpu_kernel void @test_call_external_void_func_v32i32_i8_i8_i16() #0 {
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[COPY10:%[0-9]+]]:_(p1) = COPY [[DEF1]](p1)		; CHECK: [[COPY10:%[0-9]+]]:_(p1) = COPY [[DEF1]](p1)
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<32 x i32> addrspace(1)* addrspace(4)* undef`, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<32 x i32> addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[LOAD]](p1) :: (load 128 from %ir.ptr0, addrspace 1)		; CHECK: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[LOAD]](p1) :: (load 128 from %ir.ptr0, addrspace 1)
; CHECK: [[LOAD2:%[0-9]+]]:_(s8) = G_LOAD [[DEF1]](p1) :: (load 1 from `i8 addrspace(1)* undef`, addrspace 1)		; CHECK: [[LOAD2:%[0-9]+]]:_(s8) = G_LOAD [[DEF1]](p1) :: (load 1 from `i8 addrspace(1)* undef`, addrspace 1)
; CHECK: [[LOAD3:%[0-9]+]]:_(s16) = G_LOAD [[COPY10]](p1) :: (load 2 from `i16 addrspace(1)* undef`, addrspace 1)		; CHECK: [[LOAD3:%[0-9]+]]:_(s16) = G_LOAD [[COPY10]](p1) :: (load 2 from `i16 addrspace(1)* undef`, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<32 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v32i32_i8_i8_i16		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v32i32_i8_i8_i16
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY13]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY13]], [[C]](s64)
; CHECK: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[SHL]]
; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<32 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: $vgpr5 = COPY [[UV5]](s32)		; CHECK: $vgpr5 = COPY [[UV5]](s32)
; CHECK: $vgpr6 = COPY [[UV6]](s32)		; CHECK: $vgpr6 = COPY [[UV6]](s32)
; CHECK: $vgpr7 = COPY [[UV7]](s32)		; CHECK: $vgpr7 = COPY [[UV7]](s32)
Show All 19 Lines	define amdgpu_kernel void @test_call_external_void_func_v32i32_i8_i8_i16() #0 {
; CHECK: $vgpr27 = COPY [[UV27]](s32)		; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32)		; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32)		; CHECK: $vgpr29 = COPY [[UV29]](s32)
; CHECK: $vgpr30 = COPY [[UV30]](s32)		; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: [[COPY21:%[0-9]+]]:_(p5) = COPY $sp_reg		; CHECK: [[COPY21:%[0-9]+]]:_(p5) = COPY $sp_reg
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C3]](s32)		; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C3]](s32)
; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack, align 16, addrspace 5)		; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack, align 16, addrspace 5)
		; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[LOAD2]](s8)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C4]](s32)		; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C4]](s32)
; CHECK: G_STORE [[LOAD2]](s8), [[PTR_ADD2]](p5) :: (store 1 into stack + 4, align 4, addrspace 5)		; CHECK: G_STORE [[ANYEXT]](s16), [[PTR_ADD2]](p5) :: (store 2 into stack + 4, align 4, addrspace 5)
		; CHECK: [[COPY22:%[0-9]+]]:_(s16) = COPY [[ANYEXT]](s16)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8		; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C5]](s32)		; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C5]](s32)
; CHECK: G_STORE [[LOAD2]](s8), [[PTR_ADD3]](p5) :: (store 1 into stack + 8, align 8, addrspace 5)		; CHECK: G_STORE [[COPY22]](s16), [[PTR_ADD3]](p5) :: (store 2 into stack + 8, align 8, addrspace 5)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 12		; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C6]](s32)		; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C6]](s32)
; CHECK: G_STORE [[LOAD3]](s16), [[PTR_ADD4]](p5) :: (store 2 into stack + 12, align 4, addrspace 5)		; CHECK: G_STORE [[LOAD3]](s16), [[PTR_ADD4]](p5) :: (store 2 into stack + 12, align 4, addrspace 5)
; CHECK: [[COPY22:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY23:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY22]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY23]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY11]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY11]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY12]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY12]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY14]](s64)		; CHECK: $sgpr10_sgpr11 = COPY [[COPY14]](s64)
; CHECK: $sgpr12 = COPY [[COPY15]](s32)		; CHECK: $sgpr12 = COPY [[COPY15]](s32)
; CHECK: $sgpr13 = COPY [[COPY16]](s32)		; CHECK: $sgpr13 = COPY [[COPY16]](s32)
; CHECK: $sgpr14 = COPY [[COPY17]](s32)		; CHECK: $sgpr14 = COPY [[COPY17]](s32)
; CHECK: $vgpr31 = COPY [[OR1]](s32)		; CHECK: $vgpr31 = COPY [[OR1]](s32)
Show All 25 Lines	define amdgpu_kernel void @test_call_external_void_func_v32i32_p3_p5() #0 {
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[COPY10:%[0-9]+]]:_(p1) = COPY [[DEF1]](p1)		; CHECK: [[COPY10:%[0-9]+]]:_(p1) = COPY [[DEF1]](p1)
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<32 x i32> addrspace(1)* addrspace(4)* undef`, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<32 x i32> addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[LOAD]](p1) :: (load 128 from %ir.ptr0, addrspace 1)		; CHECK: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[LOAD]](p1) :: (load 128 from %ir.ptr0, addrspace 1)
; CHECK: [[LOAD2:%[0-9]+]]:_(p3) = G_LOAD [[DEF1]](p1) :: (load 4 from `i8 addrspace(3)* addrspace(1)* undef`, addrspace 1)		; CHECK: [[LOAD2:%[0-9]+]]:_(p3) = G_LOAD [[DEF1]](p1) :: (load 4 from `i8 addrspace(3)* addrspace(1)* undef`, addrspace 1)
; CHECK: [[LOAD3:%[0-9]+]]:_(p5) = G_LOAD [[COPY10]](p1) :: (load 4 from `i8 addrspace(5)* addrspace(1)* undef`, addrspace 1)		; CHECK: [[LOAD3:%[0-9]+]]:_(p5) = G_LOAD [[COPY10]](p1) :: (load 4 from `i8 addrspace(5)* addrspace(1)* undef`, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<32 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v32i32_p3_p5		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v32i32_p3_p5
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY13]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY13]], [[C]](s64)
; CHECK: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[SHL]]
; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<32 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: $vgpr5 = COPY [[UV5]](s32)		; CHECK: $vgpr5 = COPY [[UV5]](s32)
; CHECK: $vgpr6 = COPY [[UV6]](s32)		; CHECK: $vgpr6 = COPY [[UV6]](s32)
; CHECK: $vgpr7 = COPY [[UV7]](s32)		; CHECK: $vgpr7 = COPY [[UV7]](s32)
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines	define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD1]](s8)		; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[LOAD1]](s8)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)		; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)
		; CHECK: $vgpr0 = COPY [[ANYEXT1]](s32)
; CHECK: $vgpr1 = COPY [[LOAD2]](s32)		; CHECK: $vgpr1 = COPY [[LOAD2]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4)		; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)		; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; CHECK: $sgpr12 = COPY [[COPY14]](s32)		; CHECK: $sgpr12 = COPY [[COPY14]](s32)
Show All 17 Lines	define amdgpu_gfx void @test_gfx_call_external_void_func_struct_i8_i32() #0 {
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `{ i8, i32 } addrspace(1)* addrspace(4)* undef`, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `{ i8, i32 } addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p1) :: (load 1 from %ir.ptr0, align 4, addrspace 1)		; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p1) :: (load 1 from %ir.ptr0, align 4, addrspace 1)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[LOAD]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[LOAD]], [[C]](s64)
; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load 4 from %ir.ptr0 + 4, addrspace 1)		; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load 4 from %ir.ptr0 + 4, addrspace 1)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_gfx_void_func_struct_i8_i32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_gfx_void_func_struct_i8_i32
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD1]](s8)		; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[LOAD1]](s8)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)		; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)
		; CHECK: $vgpr0 = COPY [[ANYEXT1]](s32)
; CHECK: $vgpr1 = COPY [[LOAD2]](s32)		; CHECK: $vgpr1 = COPY [[LOAD2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3		; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY1]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY1]](<4 x s32>)
; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_gfx_void_func_struct_i8_i32, csr_amdgpu_highregs, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3		; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_gfx_void_func_struct_i8_i32, csr_amdgpu_highregs, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]		; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY2]]		; CHECK: S_SETPC_B64_return [[COPY2]]
%ptr0 = load { i8, i32 } addrspace(1), { i8, i32 } addrspace(1) addrspace(4)* undef		%ptr0 = load { i8, i32 } addrspace(1), { i8, i32 } addrspace(1) addrspace(4)* undef
Show All 10 Lines	define amdgpu_gfx void @test_gfx_call_external_void_func_struct_i8_i32_inreg() #0 {
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `{ i8, i32 } addrspace(1)* addrspace(4)* undef`, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `{ i8, i32 } addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p1) :: (load 1 from %ir.ptr0, align 4, addrspace 1)		; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p1) :: (load 1 from %ir.ptr0, align 4, addrspace 1)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[LOAD]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[LOAD]], [[C]](s64)
; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load 4 from %ir.ptr0 + 4, addrspace 1)		; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load 4 from %ir.ptr0 + 4, addrspace 1)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_gfx_void_func_struct_i8_i32_inreg		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_gfx_void_func_struct_i8_i32_inreg
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD1]](s8)		; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[LOAD1]](s8)
; CHECK: $sgpr4 = COPY [[ANYEXT]](s32)		; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)
		; CHECK: $sgpr4 = COPY [[ANYEXT1]](s32)
; CHECK: $sgpr5 = COPY [[LOAD2]](s32)		; CHECK: $sgpr5 = COPY [[LOAD2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3		; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY1]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY1]](<4 x s32>)
; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_gfx_void_func_struct_i8_i32_inreg, csr_amdgpu_highregs, implicit $sgpr4, implicit $sgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3		; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_gfx_void_func_struct_i8_i32_inreg, csr_amdgpu_highregs, implicit $sgpr4, implicit $sgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]		; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY2]]		; CHECK: S_SETPC_B64_return [[COPY2]]
%ptr0 = load { i8, i32 } addrspace(1), { i8, i32 } addrspace(1) addrspace(4)* undef		%ptr0 = load { i8, i32 } addrspace(1), { i8, i32 } addrspace(1) addrspace(4)* undef
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines	define amdgpu_kernel void @test_call_external_void_func_v2i8() #0 {
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<2 x i8> addrspace(1)* addrspace(4)* undef`, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<2 x i8> addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(<2 x s8>) = G_LOAD [[LOAD]](p1) :: (load 2 from %ir.ptr, addrspace 1)		; CHECK: [[LOAD1:%[0-9]+]]:_(<2 x s8>) = G_LOAD [[LOAD]](p1) :: (load 2 from %ir.ptr, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[LOAD1]](<2 x s8>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v2i8		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v2i8
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[LOAD1]](<2 x s8>)
		; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)
		; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)		; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT2]](s32)		; CHECK: $vgpr0 = COPY [[ANYEXT2]](s32)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](s16)		; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](s16)
; CHECK: $vgpr1 = COPY [[ANYEXT3]](s32)		; CHECK: $vgpr1 = COPY [[ANYEXT3]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
Show All 24 Lines	define amdgpu_kernel void @test_call_external_void_func_v3i8() #0 {
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<3 x i8> addrspace(1)* addrspace(4)* undef`, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<3 x i8> addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(<3 x s8>) = G_LOAD [[LOAD]](p1) :: (load 3 from %ir.ptr, align 4, addrspace 1)		; CHECK: [[LOAD1:%[0-9]+]]:_(<3 x s8>) = G_LOAD [[LOAD]](p1) :: (load 3 from %ir.ptr, align 4, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[LOAD1]](<3 x s8>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v3i8		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v3i8
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[LOAD1]](<3 x s8>)
		; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)
		; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)
		; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)		; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT3]](s32)		; CHECK: $vgpr0 = COPY [[ANYEXT3]](s32)
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](s16)		; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](s16)
; CHECK: $vgpr1 = COPY [[ANYEXT4]](s32)		; CHECK: $vgpr1 = COPY [[ANYEXT4]](s32)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](s16)		; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](s16)
; CHECK: $vgpr2 = COPY [[ANYEXT5]](s32)		; CHECK: $vgpr2 = COPY [[ANYEXT5]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
Show All 26 Lines	define amdgpu_kernel void @test_call_external_void_func_v4i8() #0 {
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<4 x i8> addrspace(1)* addrspace(4)* undef`, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<4 x i8> addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(<4 x s8>) = G_LOAD [[LOAD]](p1) :: (load 4 from %ir.ptr, addrspace 1)		; CHECK: [[LOAD1:%[0-9]+]]:_(<4 x s8>) = G_LOAD [[LOAD]](p1) :: (load 4 from %ir.ptr, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[LOAD1]](<4 x s8>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV3]](s8)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v4i8		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v4i8
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[LOAD1]](<4 x s8>)
		; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)
		; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)
		; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8)
		; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV3]](s8)
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)		; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT4]](s32)		; CHECK: $vgpr0 = COPY [[ANYEXT4]](s32)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](s16)		; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](s16)
; CHECK: $vgpr1 = COPY [[ANYEXT5]](s32)		; CHECK: $vgpr1 = COPY [[ANYEXT5]](s32)
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](s16)		; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](s16)
; CHECK: $vgpr2 = COPY [[ANYEXT6]](s32)		; CHECK: $vgpr2 = COPY [[ANYEXT6]](s32)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT3]](s16)		; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT3]](s16)
; CHECK: $vgpr3 = COPY [[ANYEXT7]](s32)		; CHECK: $vgpr3 = COPY [[ANYEXT7]](s32)
Show All 28 Lines	define amdgpu_kernel void @test_call_external_void_func_v8i8() #0 {
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<8 x i8> addrspace(1)* addrspace(4)* undef`, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<8 x i8> addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[LOAD]](p1) :: (load 8 from %ir.ptr, addrspace 1)		; CHECK: [[LOAD1:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[LOAD]](p1) :: (load 8 from %ir.ptr, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[LOAD1]](<8 x s8>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV3]](s8)
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s16) = G_ANYEXT [[UV4]](s8)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s16) = G_ANYEXT [[UV5]](s8)
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s16) = G_ANYEXT [[UV6]](s8)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s16) = G_ANYEXT [[UV7]](s8)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v8i8		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v8i8
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[LOAD1]](<8 x s8>)
		; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)
		; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)
		; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8)
		; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV3]](s8)
		; CHECK: [[ANYEXT4:%[0-9]+]]:_(s16) = G_ANYEXT [[UV4]](s8)
		; CHECK: [[ANYEXT5:%[0-9]+]]:_(s16) = G_ANYEXT [[UV5]](s8)
		; CHECK: [[ANYEXT6:%[0-9]+]]:_(s16) = G_ANYEXT [[UV6]](s8)
		; CHECK: [[ANYEXT7:%[0-9]+]]:_(s16) = G_ANYEXT [[UV7]](s8)
; CHECK: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)		; CHECK: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT8]](s32)		; CHECK: $vgpr0 = COPY [[ANYEXT8]](s32)
; CHECK: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](s16)		; CHECK: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](s16)
; CHECK: $vgpr1 = COPY [[ANYEXT9]](s32)		; CHECK: $vgpr1 = COPY [[ANYEXT9]](s32)
; CHECK: [[ANYEXT10:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](s16)		; CHECK: [[ANYEXT10:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](s16)
; CHECK: $vgpr2 = COPY [[ANYEXT10]](s32)		; CHECK: $vgpr2 = COPY [[ANYEXT10]](s32)
; CHECK: [[ANYEXT11:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT3]](s16)		; CHECK: [[ANYEXT11:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT3]](s16)
; CHECK: $vgpr3 = COPY [[ANYEXT11]](s32)		; CHECK: $vgpr3 = COPY [[ANYEXT11]](s32)
Show All 36 Lines	define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; CHECK: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11		; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<16 x i8> addrspace(1)* addrspace(4)* undef`, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (load 8 from `<16 x i8> addrspace(1)* addrspace(4)* undef`, addrspace 4)
; CHECK: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[LOAD]](p1) :: (load 16 from %ir.ptr, addrspace 1)		; CHECK: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[LOAD]](p1) :: (load 16 from %ir.ptr, addrspace 1)
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8), [[UV12:%[0-9]+]]:_(s8), [[UV13:%[0-9]+]]:_(s8), [[UV14:%[0-9]+]]:_(s8), [[UV15:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[LOAD1]](<16 x s8>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV3]](s8)
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s16) = G_ANYEXT [[UV4]](s8)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s16) = G_ANYEXT [[UV5]](s8)
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s16) = G_ANYEXT [[UV6]](s8)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s16) = G_ANYEXT [[UV7]](s8)
; CHECK: [[ANYEXT8:%[0-9]+]]:_(s16) = G_ANYEXT [[UV8]](s8)
; CHECK: [[ANYEXT9:%[0-9]+]]:_(s16) = G_ANYEXT [[UV9]](s8)
; CHECK: [[ANYEXT10:%[0-9]+]]:_(s16) = G_ANYEXT [[UV10]](s8)
; CHECK: [[ANYEXT11:%[0-9]+]]:_(s16) = G_ANYEXT [[UV11]](s8)
; CHECK: [[ANYEXT12:%[0-9]+]]:_(s16) = G_ANYEXT [[UV12]](s8)
; CHECK: [[ANYEXT13:%[0-9]+]]:_(s16) = G_ANYEXT [[UV13]](s8)
; CHECK: [[ANYEXT14:%[0-9]+]]:_(s16) = G_ANYEXT [[UV14]](s8)
; CHECK: [[ANYEXT15:%[0-9]+]]:_(s16) = G_ANYEXT [[UV15]](s8)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v16i8		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_v16i8
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8), [[UV12:%[0-9]+]]:_(s8), [[UV13:%[0-9]+]]:_(s8), [[UV14:%[0-9]+]]:_(s8), [[UV15:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[LOAD1]](<16 x s8>)
		; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)
		; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)
		; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8)
		; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV3]](s8)
		; CHECK: [[ANYEXT4:%[0-9]+]]:_(s16) = G_ANYEXT [[UV4]](s8)
		; CHECK: [[ANYEXT5:%[0-9]+]]:_(s16) = G_ANYEXT [[UV5]](s8)
		; CHECK: [[ANYEXT6:%[0-9]+]]:_(s16) = G_ANYEXT [[UV6]](s8)
		; CHECK: [[ANYEXT7:%[0-9]+]]:_(s16) = G_ANYEXT [[UV7]](s8)
		; CHECK: [[ANYEXT8:%[0-9]+]]:_(s16) = G_ANYEXT [[UV8]](s8)
		; CHECK: [[ANYEXT9:%[0-9]+]]:_(s16) = G_ANYEXT [[UV9]](s8)
		; CHECK: [[ANYEXT10:%[0-9]+]]:_(s16) = G_ANYEXT [[UV10]](s8)
		; CHECK: [[ANYEXT11:%[0-9]+]]:_(s16) = G_ANYEXT [[UV11]](s8)
		; CHECK: [[ANYEXT12:%[0-9]+]]:_(s16) = G_ANYEXT [[UV12]](s8)
		; CHECK: [[ANYEXT13:%[0-9]+]]:_(s16) = G_ANYEXT [[UV13]](s8)
		; CHECK: [[ANYEXT14:%[0-9]+]]:_(s16) = G_ANYEXT [[UV14]](s8)
		; CHECK: [[ANYEXT15:%[0-9]+]]:_(s16) = G_ANYEXT [[UV15]](s8)
; CHECK: [[ANYEXT16:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)		; CHECK: [[ANYEXT16:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT16]](s32)		; CHECK: $vgpr0 = COPY [[ANYEXT16]](s32)
; CHECK: [[ANYEXT17:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](s16)		; CHECK: [[ANYEXT17:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](s16)
; CHECK: $vgpr1 = COPY [[ANYEXT17]](s32)		; CHECK: $vgpr1 = COPY [[ANYEXT17]](s32)
; CHECK: [[ANYEXT18:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](s16)		; CHECK: [[ANYEXT18:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](s16)
; CHECK: $vgpr2 = COPY [[ANYEXT18]](s32)		; CHECK: $vgpr2 = COPY [[ANYEXT18]](s32)
; CHECK: [[ANYEXT19:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT3]](s16)		; CHECK: [[ANYEXT19:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT3]](s16)
; CHECK: $vgpr3 = COPY [[ANYEXT19]](s32)		; CHECK: $vgpr3 = COPY [[ANYEXT19]](s32)
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines	define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, double %tmp) #0 {
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; CHECK: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)		; CHECK: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; CHECK: [[LOAD:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[INT]](p4) :: (dereferenceable invariant load 128 from %ir.val.kernarg.offset.cast, align 16, addrspace 4)		; CHECK: [[LOAD:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[INT]](p4) :: (dereferenceable invariant load 128 from %ir.val.kernarg.offset.cast, align 16, addrspace 4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 128		; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 128
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[INT]], [[C]](s64)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[INT]], [[C]](s64)
; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8 from %ir.tmp.kernarg.offset.cast, align 16, addrspace 4)		; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8 from %ir.tmp.kernarg.offset.cast, align 16, addrspace 4)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<32 x s32>)
; CHECK: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](s64)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @stack_passed_f64_arg		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @stack_passed_f64_arg
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)		; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 136		; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 136
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)		; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64)
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<32 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: $vgpr5 = COPY [[UV5]](s32)		; CHECK: $vgpr5 = COPY [[UV5]](s32)
; CHECK: $vgpr6 = COPY [[UV6]](s32)		; CHECK: $vgpr6 = COPY [[UV6]](s32)
; CHECK: $vgpr7 = COPY [[UV7]](s32)		; CHECK: $vgpr7 = COPY [[UV7]](s32)
Show All 19 Lines	define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, double %tmp) #0 {
; CHECK: $vgpr27 = COPY [[UV27]](s32)		; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32)		; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32)		; CHECK: $vgpr29 = COPY [[UV29]](s32)
; CHECK: $vgpr30 = COPY [[UV30]](s32)		; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg		; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C4]](s32)		; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C4]](s32)
; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack, align 16, addrspace 5)		; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack, align 16, addrspace 5)
		; CHECK: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](s64)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4		; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C5]](s32)		; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C5]](s32)
; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 4, addrspace 5)		; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 4, addrspace 5)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8		; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C6]](s32)		; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C6]](s32)
; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 8, align 8, addrspace 5)		; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 8, align 8, addrspace 5)
; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)		; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines	define void @stack_12xv3i32() #0 {
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 11		; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 12		; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[BUILD_VECTOR10:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C10]](s32), [[C11]](s32), [[C12]](s32)		; CHECK: [[BUILD_VECTOR10:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C10]](s32), [[C11]](s32), [[C12]](s32)
; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 13		; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 14		; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 15		; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[BUILD_VECTOR11:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C13]](s32), [[C14]](s32), [[C15]](s32)		; CHECK: [[BUILD_VECTOR11:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C13]](s32), [[C14]](s32), [[C15]](s32)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)
; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<3 x s32>)
; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<3 x s32>)
; CHECK: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR3]](<3 x s32>)
; CHECK: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR4]](<3 x s32>)
; CHECK: [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR5]](<3 x s32>)
; CHECK: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR6]](<3 x s32>)
; CHECK: [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR7]](<3 x s32>)
; CHECK: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR8]](<3 x s32>)
; CHECK: [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR9]](<3 x s32>)
; CHECK: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR10]](<3 x s32>)
; CHECK: [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR11]](<3 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_12xv3i32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_12xv3i32
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY6]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY6]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY5]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY5]]
; CHECK: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY4]]		; CHECK: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY4]]
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY2]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY1]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY1]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
		; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<3 x s32>)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: $vgpr5 = COPY [[UV5]](s32)		; CHECK: $vgpr5 = COPY [[UV5]](s32)
		; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<3 x s32>)
; CHECK: $vgpr6 = COPY [[UV6]](s32)		; CHECK: $vgpr6 = COPY [[UV6]](s32)
; CHECK: $vgpr7 = COPY [[UV7]](s32)		; CHECK: $vgpr7 = COPY [[UV7]](s32)
; CHECK: $vgpr8 = COPY [[UV8]](s32)		; CHECK: $vgpr8 = COPY [[UV8]](s32)
		; CHECK: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR3]](<3 x s32>)
; CHECK: $vgpr9 = COPY [[UV9]](s32)		; CHECK: $vgpr9 = COPY [[UV9]](s32)
; CHECK: $vgpr10 = COPY [[UV10]](s32)		; CHECK: $vgpr10 = COPY [[UV10]](s32)
; CHECK: $vgpr11 = COPY [[UV11]](s32)		; CHECK: $vgpr11 = COPY [[UV11]](s32)
		; CHECK: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR4]](<3 x s32>)
; CHECK: $vgpr12 = COPY [[UV12]](s32)		; CHECK: $vgpr12 = COPY [[UV12]](s32)
; CHECK: $vgpr13 = COPY [[UV13]](s32)		; CHECK: $vgpr13 = COPY [[UV13]](s32)
; CHECK: $vgpr14 = COPY [[UV14]](s32)		; CHECK: $vgpr14 = COPY [[UV14]](s32)
		; CHECK: [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR5]](<3 x s32>)
; CHECK: $vgpr15 = COPY [[UV15]](s32)		; CHECK: $vgpr15 = COPY [[UV15]](s32)
; CHECK: $vgpr16 = COPY [[UV16]](s32)		; CHECK: $vgpr16 = COPY [[UV16]](s32)
; CHECK: $vgpr17 = COPY [[UV17]](s32)		; CHECK: $vgpr17 = COPY [[UV17]](s32)
		; CHECK: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR6]](<3 x s32>)
; CHECK: $vgpr18 = COPY [[UV18]](s32)		; CHECK: $vgpr18 = COPY [[UV18]](s32)
; CHECK: $vgpr19 = COPY [[UV19]](s32)		; CHECK: $vgpr19 = COPY [[UV19]](s32)
; CHECK: $vgpr20 = COPY [[UV20]](s32)		; CHECK: $vgpr20 = COPY [[UV20]](s32)
		; CHECK: [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR7]](<3 x s32>)
; CHECK: $vgpr21 = COPY [[UV21]](s32)		; CHECK: $vgpr21 = COPY [[UV21]](s32)
; CHECK: $vgpr22 = COPY [[UV22]](s32)		; CHECK: $vgpr22 = COPY [[UV22]](s32)
; CHECK: $vgpr23 = COPY [[UV23]](s32)		; CHECK: $vgpr23 = COPY [[UV23]](s32)
		; CHECK: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR8]](<3 x s32>)
; CHECK: $vgpr24 = COPY [[UV24]](s32)		; CHECK: $vgpr24 = COPY [[UV24]](s32)
; CHECK: $vgpr25 = COPY [[UV25]](s32)		; CHECK: $vgpr25 = COPY [[UV25]](s32)
; CHECK: $vgpr26 = COPY [[UV26]](s32)		; CHECK: $vgpr26 = COPY [[UV26]](s32)
		; CHECK: [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR9]](<3 x s32>)
; CHECK: $vgpr27 = COPY [[UV27]](s32)		; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32)		; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32)		; CHECK: $vgpr29 = COPY [[UV29]](s32)
		; CHECK: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR10]](<3 x s32>)
; CHECK: $vgpr30 = COPY [[UV30]](s32)		; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: [[COPY17:%[0-9]+]]:_(p5) = COPY $sgpr32		; CHECK: [[COPY17:%[0-9]+]]:_(p5) = COPY $sgpr32
; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C16]](s32)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C16]](s32)
; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, align 16, addrspace 5)		; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, align 16, addrspace 5)
; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4		; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C17]](s32)		; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C17]](s32)
; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack + 4, addrspace 5)		; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack + 4, addrspace 5)
		; CHECK: [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR11]](<3 x s32>)
; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8		; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C18]](s32)		; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C18]](s32)
; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 8, align 8, addrspace 5)		; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 8, align 8, addrspace 5)
; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12		; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C19]](s32)		; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C19]](s32)
; CHECK: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 12, addrspace 5)		; CHECK: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 12, addrspace 5)
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C20]](s32)		; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C20]](s32)
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines	define void @stack_12xv3f32() #0 {
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+01		; CHECK: [[C10:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+01
; CHECK: [[C11:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.100000e+01		; CHECK: [[C11:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.100000e+01
; CHECK: [[C12:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.200000e+01		; CHECK: [[C12:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.200000e+01
; CHECK: [[BUILD_VECTOR10:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C10]](s32), [[C11]](s32), [[C12]](s32)		; CHECK: [[BUILD_VECTOR10:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C10]](s32), [[C11]](s32), [[C12]](s32)
; CHECK: [[C13:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.300000e+01		; CHECK: [[C13:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.300000e+01
; CHECK: [[C14:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.400000e+01		; CHECK: [[C14:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.400000e+01
; CHECK: [[C15:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.500000e+01		; CHECK: [[C15:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.500000e+01
; CHECK: [[BUILD_VECTOR11:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C13]](s32), [[C14]](s32), [[C15]](s32)		; CHECK: [[BUILD_VECTOR11:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C13]](s32), [[C14]](s32), [[C15]](s32)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)
; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<3 x s32>)
; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<3 x s32>)
; CHECK: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR3]](<3 x s32>)
; CHECK: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR4]](<3 x s32>)
; CHECK: [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR5]](<3 x s32>)
; CHECK: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR6]](<3 x s32>)
; CHECK: [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR7]](<3 x s32>)
; CHECK: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR8]](<3 x s32>)
; CHECK: [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR9]](<3 x s32>)
; CHECK: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR10]](<3 x s32>)
; CHECK: [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR11]](<3 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_12xv3f32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_12xv3f32
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY6]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY6]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY5]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY5]]
; CHECK: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY4]]		; CHECK: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY4]]
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY2]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY1]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY1]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
		; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<3 x s32>)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
; CHECK: $vgpr5 = COPY [[UV5]](s32)		; CHECK: $vgpr5 = COPY [[UV5]](s32)
		; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<3 x s32>)
; CHECK: $vgpr6 = COPY [[UV6]](s32)		; CHECK: $vgpr6 = COPY [[UV6]](s32)
; CHECK: $vgpr7 = COPY [[UV7]](s32)		; CHECK: $vgpr7 = COPY [[UV7]](s32)
; CHECK: $vgpr8 = COPY [[UV8]](s32)		; CHECK: $vgpr8 = COPY [[UV8]](s32)
		; CHECK: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR3]](<3 x s32>)
; CHECK: $vgpr9 = COPY [[UV9]](s32)		; CHECK: $vgpr9 = COPY [[UV9]](s32)
; CHECK: $vgpr10 = COPY [[UV10]](s32)		; CHECK: $vgpr10 = COPY [[UV10]](s32)
; CHECK: $vgpr11 = COPY [[UV11]](s32)		; CHECK: $vgpr11 = COPY [[UV11]](s32)
		; CHECK: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR4]](<3 x s32>)
; CHECK: $vgpr12 = COPY [[UV12]](s32)		; CHECK: $vgpr12 = COPY [[UV12]](s32)
; CHECK: $vgpr13 = COPY [[UV13]](s32)		; CHECK: $vgpr13 = COPY [[UV13]](s32)
; CHECK: $vgpr14 = COPY [[UV14]](s32)		; CHECK: $vgpr14 = COPY [[UV14]](s32)
		; CHECK: [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR5]](<3 x s32>)
; CHECK: $vgpr15 = COPY [[UV15]](s32)		; CHECK: $vgpr15 = COPY [[UV15]](s32)
; CHECK: $vgpr16 = COPY [[UV16]](s32)		; CHECK: $vgpr16 = COPY [[UV16]](s32)
; CHECK: $vgpr17 = COPY [[UV17]](s32)		; CHECK: $vgpr17 = COPY [[UV17]](s32)
		; CHECK: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR6]](<3 x s32>)
; CHECK: $vgpr18 = COPY [[UV18]](s32)		; CHECK: $vgpr18 = COPY [[UV18]](s32)
; CHECK: $vgpr19 = COPY [[UV19]](s32)		; CHECK: $vgpr19 = COPY [[UV19]](s32)
; CHECK: $vgpr20 = COPY [[UV20]](s32)		; CHECK: $vgpr20 = COPY [[UV20]](s32)
		; CHECK: [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR7]](<3 x s32>)
; CHECK: $vgpr21 = COPY [[UV21]](s32)		; CHECK: $vgpr21 = COPY [[UV21]](s32)
; CHECK: $vgpr22 = COPY [[UV22]](s32)		; CHECK: $vgpr22 = COPY [[UV22]](s32)
; CHECK: $vgpr23 = COPY [[UV23]](s32)		; CHECK: $vgpr23 = COPY [[UV23]](s32)
		; CHECK: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR8]](<3 x s32>)
; CHECK: $vgpr24 = COPY [[UV24]](s32)		; CHECK: $vgpr24 = COPY [[UV24]](s32)
; CHECK: $vgpr25 = COPY [[UV25]](s32)		; CHECK: $vgpr25 = COPY [[UV25]](s32)
; CHECK: $vgpr26 = COPY [[UV26]](s32)		; CHECK: $vgpr26 = COPY [[UV26]](s32)
		; CHECK: [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR9]](<3 x s32>)
; CHECK: $vgpr27 = COPY [[UV27]](s32)		; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32)		; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32)		; CHECK: $vgpr29 = COPY [[UV29]](s32)
		; CHECK: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR10]](<3 x s32>)
; CHECK: $vgpr30 = COPY [[UV30]](s32)		; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: [[COPY17:%[0-9]+]]:_(p5) = COPY $sgpr32		; CHECK: [[COPY17:%[0-9]+]]:_(p5) = COPY $sgpr32
; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C16]](s32)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C16]](s32)
; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, align 16, addrspace 5)		; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, align 16, addrspace 5)
; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4		; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C17]](s32)		; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C17]](s32)
; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack + 4, addrspace 5)		; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack + 4, addrspace 5)
		; CHECK: [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR11]](<3 x s32>)
; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8		; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C18]](s32)		; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C18]](s32)
; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 8, align 8, addrspace 5)		; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 8, align 8, addrspace 5)
; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12		; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C19]](s32)		; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C19]](s32)
; CHECK: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 12, addrspace 5)		; CHECK: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 12, addrspace 5)
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C20]](s32)		; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C20]](s32)
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines	define void @stack_8xv5i32() #0 {
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[BUILD_VECTOR6:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C6]](s32), [[C7]](s32), [[C8]](s32), [[C9]](s32), [[C10]](s32)		; CHECK: [[BUILD_VECTOR6:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C6]](s32), [[C7]](s32), [[C8]](s32), [[C9]](s32), [[C10]](s32)
; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 11		; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 12		; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 13		; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 14		; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 15		; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[BUILD_VECTOR7:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C11]](s32), [[C12]](s32), [[C13]](s32), [[C14]](s32), [[C15]](s32)		; CHECK: [[BUILD_VECTOR7:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C11]](s32), [[C12]](s32), [[C13]](s32), [[C14]](s32), [[C15]](s32)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<5 x s32>)
; CHECK: [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<5 x s32>)
; CHECK: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<5 x s32>)
; CHECK: [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR3]](<5 x s32>)
; CHECK: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR4]](<5 x s32>)
; CHECK: [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR5]](<5 x s32>)
; CHECK: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR6]](<5 x s32>)
; CHECK: [[UV35:%[0-9]+]]:_(s32), [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32), [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR7]](<5 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_8xv5i32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_8xv5i32
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY6]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY6]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY5]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY5]]
; CHECK: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY4]]		; CHECK: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY4]]
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY2]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY1]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY1]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<5 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
		; CHECK: [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<5 x s32>)
; CHECK: $vgpr5 = COPY [[UV5]](s32)		; CHECK: $vgpr5 = COPY [[UV5]](s32)
; CHECK: $vgpr6 = COPY [[UV6]](s32)		; CHECK: $vgpr6 = COPY [[UV6]](s32)
; CHECK: $vgpr7 = COPY [[UV7]](s32)		; CHECK: $vgpr7 = COPY [[UV7]](s32)
; CHECK: $vgpr8 = COPY [[UV8]](s32)		; CHECK: $vgpr8 = COPY [[UV8]](s32)
; CHECK: $vgpr9 = COPY [[UV9]](s32)		; CHECK: $vgpr9 = COPY [[UV9]](s32)
		; CHECK: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<5 x s32>)
; CHECK: $vgpr10 = COPY [[UV10]](s32)		; CHECK: $vgpr10 = COPY [[UV10]](s32)
; CHECK: $vgpr11 = COPY [[UV11]](s32)		; CHECK: $vgpr11 = COPY [[UV11]](s32)
; CHECK: $vgpr12 = COPY [[UV12]](s32)		; CHECK: $vgpr12 = COPY [[UV12]](s32)
; CHECK: $vgpr13 = COPY [[UV13]](s32)		; CHECK: $vgpr13 = COPY [[UV13]](s32)
; CHECK: $vgpr14 = COPY [[UV14]](s32)		; CHECK: $vgpr14 = COPY [[UV14]](s32)
		; CHECK: [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR3]](<5 x s32>)
; CHECK: $vgpr15 = COPY [[UV15]](s32)		; CHECK: $vgpr15 = COPY [[UV15]](s32)
; CHECK: $vgpr16 = COPY [[UV16]](s32)		; CHECK: $vgpr16 = COPY [[UV16]](s32)
; CHECK: $vgpr17 = COPY [[UV17]](s32)		; CHECK: $vgpr17 = COPY [[UV17]](s32)
; CHECK: $vgpr18 = COPY [[UV18]](s32)		; CHECK: $vgpr18 = COPY [[UV18]](s32)
; CHECK: $vgpr19 = COPY [[UV19]](s32)		; CHECK: $vgpr19 = COPY [[UV19]](s32)
		; CHECK: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR4]](<5 x s32>)
; CHECK: $vgpr20 = COPY [[UV20]](s32)		; CHECK: $vgpr20 = COPY [[UV20]](s32)
; CHECK: $vgpr21 = COPY [[UV21]](s32)		; CHECK: $vgpr21 = COPY [[UV21]](s32)
; CHECK: $vgpr22 = COPY [[UV22]](s32)		; CHECK: $vgpr22 = COPY [[UV22]](s32)
; CHECK: $vgpr23 = COPY [[UV23]](s32)		; CHECK: $vgpr23 = COPY [[UV23]](s32)
; CHECK: $vgpr24 = COPY [[UV24]](s32)		; CHECK: $vgpr24 = COPY [[UV24]](s32)
		; CHECK: [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR5]](<5 x s32>)
; CHECK: $vgpr25 = COPY [[UV25]](s32)		; CHECK: $vgpr25 = COPY [[UV25]](s32)
; CHECK: $vgpr26 = COPY [[UV26]](s32)		; CHECK: $vgpr26 = COPY [[UV26]](s32)
; CHECK: $vgpr27 = COPY [[UV27]](s32)		; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32)		; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32)		; CHECK: $vgpr29 = COPY [[UV29]](s32)
		; CHECK: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR6]](<5 x s32>)
; CHECK: $vgpr30 = COPY [[UV30]](s32)		; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: [[COPY17:%[0-9]+]]:_(p5) = COPY $sgpr32		; CHECK: [[COPY17:%[0-9]+]]:_(p5) = COPY $sgpr32
; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C16]](s32)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C16]](s32)
; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, align 16, addrspace 5)		; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, align 16, addrspace 5)
; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4		; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C17]](s32)		; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C17]](s32)
; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack + 4, addrspace 5)		; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack + 4, addrspace 5)
; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8		; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C18]](s32)		; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C18]](s32)
; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 8, align 8, addrspace 5)		; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 8, align 8, addrspace 5)
; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12		; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C19]](s32)		; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C19]](s32)
; CHECK: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 12, addrspace 5)		; CHECK: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 12, addrspace 5)
		; CHECK: [[UV35:%[0-9]+]]:_(s32), [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32), [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR7]](<5 x s32>)
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C20]](s32)		; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C20]](s32)
; CHECK: G_STORE [[UV35]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 16, align 16, addrspace 5)		; CHECK: G_STORE [[UV35]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 16, align 16, addrspace 5)
; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[PTR_ADD5:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C21]](s32)		; CHECK: [[PTR_ADD5:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C21]](s32)
; CHECK: G_STORE [[UV36]](s32), [[PTR_ADD5]](p5) :: (store 4 into stack + 20, addrspace 5)		; CHECK: G_STORE [[UV36]](s32), [[PTR_ADD5]](p5) :: (store 4 into stack + 20, addrspace 5)
; CHECK: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 24		; CHECK: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C22]](s32)		; CHECK: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C22]](s32)
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines	define void @stack_8xv5f32() #0 {
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+01		; CHECK: [[C10:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+01
; CHECK: [[BUILD_VECTOR6:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C6]](s32), [[C7]](s32), [[C8]](s32), [[C9]](s32), [[C10]](s32)		; CHECK: [[BUILD_VECTOR6:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C6]](s32), [[C7]](s32), [[C8]](s32), [[C9]](s32), [[C10]](s32)
; CHECK: [[C11:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.100000e+01		; CHECK: [[C11:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.100000e+01
; CHECK: [[C12:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.200000e+01		; CHECK: [[C12:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.200000e+01
; CHECK: [[C13:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.300000e+01		; CHECK: [[C13:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.300000e+01
; CHECK: [[C14:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.400000e+01		; CHECK: [[C14:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.400000e+01
; CHECK: [[C15:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.500000e+01		; CHECK: [[C15:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.500000e+01
; CHECK: [[BUILD_VECTOR7:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C11]](s32), [[C12]](s32), [[C13]](s32), [[C14]](s32), [[C15]](s32)		; CHECK: [[BUILD_VECTOR7:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C11]](s32), [[C12]](s32), [[C13]](s32), [[C14]](s32), [[C15]](s32)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<5 x s32>)
; CHECK: [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<5 x s32>)
; CHECK: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<5 x s32>)
; CHECK: [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR3]](<5 x s32>)
; CHECK: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR4]](<5 x s32>)
; CHECK: [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR5]](<5 x s32>)
; CHECK: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR6]](<5 x s32>)
; CHECK: [[UV35:%[0-9]+]]:_(s32), [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32), [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR7]](<5 x s32>)
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc		; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_8xv5f32		; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_8xv5f32
; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY6]]		; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY6]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY5]]		; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY5]]
; CHECK: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY4]]		; CHECK: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY4]]
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY2]]		; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY1]]		; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY1]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<5 x s32>)
; CHECK: $vgpr0 = COPY [[UV]](s32)		; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32)		; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32)		; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32)		; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: $vgpr4 = COPY [[UV4]](s32)		; CHECK: $vgpr4 = COPY [[UV4]](s32)
		; CHECK: [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<5 x s32>)
; CHECK: $vgpr5 = COPY [[UV5]](s32)		; CHECK: $vgpr5 = COPY [[UV5]](s32)
; CHECK: $vgpr6 = COPY [[UV6]](s32)		; CHECK: $vgpr6 = COPY [[UV6]](s32)
; CHECK: $vgpr7 = COPY [[UV7]](s32)		; CHECK: $vgpr7 = COPY [[UV7]](s32)
; CHECK: $vgpr8 = COPY [[UV8]](s32)		; CHECK: $vgpr8 = COPY [[UV8]](s32)
; CHECK: $vgpr9 = COPY [[UV9]](s32)		; CHECK: $vgpr9 = COPY [[UV9]](s32)
		; CHECK: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<5 x s32>)
; CHECK: $vgpr10 = COPY [[UV10]](s32)		; CHECK: $vgpr10 = COPY [[UV10]](s32)
; CHECK: $vgpr11 = COPY [[UV11]](s32)		; CHECK: $vgpr11 = COPY [[UV11]](s32)
; CHECK: $vgpr12 = COPY [[UV12]](s32)		; CHECK: $vgpr12 = COPY [[UV12]](s32)
; CHECK: $vgpr13 = COPY [[UV13]](s32)		; CHECK: $vgpr13 = COPY [[UV13]](s32)
; CHECK: $vgpr14 = COPY [[UV14]](s32)		; CHECK: $vgpr14 = COPY [[UV14]](s32)
		; CHECK: [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR3]](<5 x s32>)
; CHECK: $vgpr15 = COPY [[UV15]](s32)		; CHECK: $vgpr15 = COPY [[UV15]](s32)
; CHECK: $vgpr16 = COPY [[UV16]](s32)		; CHECK: $vgpr16 = COPY [[UV16]](s32)
; CHECK: $vgpr17 = COPY [[UV17]](s32)		; CHECK: $vgpr17 = COPY [[UV17]](s32)
; CHECK: $vgpr18 = COPY [[UV18]](s32)		; CHECK: $vgpr18 = COPY [[UV18]](s32)
; CHECK: $vgpr19 = COPY [[UV19]](s32)		; CHECK: $vgpr19 = COPY [[UV19]](s32)
		; CHECK: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR4]](<5 x s32>)
; CHECK: $vgpr20 = COPY [[UV20]](s32)		; CHECK: $vgpr20 = COPY [[UV20]](s32)
; CHECK: $vgpr21 = COPY [[UV21]](s32)		; CHECK: $vgpr21 = COPY [[UV21]](s32)
; CHECK: $vgpr22 = COPY [[UV22]](s32)		; CHECK: $vgpr22 = COPY [[UV22]](s32)
; CHECK: $vgpr23 = COPY [[UV23]](s32)		; CHECK: $vgpr23 = COPY [[UV23]](s32)
; CHECK: $vgpr24 = COPY [[UV24]](s32)		; CHECK: $vgpr24 = COPY [[UV24]](s32)
		; CHECK: [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR5]](<5 x s32>)
; CHECK: $vgpr25 = COPY [[UV25]](s32)		; CHECK: $vgpr25 = COPY [[UV25]](s32)
; CHECK: $vgpr26 = COPY [[UV26]](s32)		; CHECK: $vgpr26 = COPY [[UV26]](s32)
; CHECK: $vgpr27 = COPY [[UV27]](s32)		; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32)		; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32)		; CHECK: $vgpr29 = COPY [[UV29]](s32)
		; CHECK: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR6]](<5 x s32>)
; CHECK: $vgpr30 = COPY [[UV30]](s32)		; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: [[COPY17:%[0-9]+]]:_(p5) = COPY $sgpr32		; CHECK: [[COPY17:%[0-9]+]]:_(p5) = COPY $sgpr32
; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C16]](s32)		; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C16]](s32)
; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, align 16, addrspace 5)		; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, align 16, addrspace 5)
; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4		; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C17]](s32)		; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C17]](s32)
; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack + 4, addrspace 5)		; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack + 4, addrspace 5)
; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8		; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C18]](s32)		; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C18]](s32)
; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 8, align 8, addrspace 5)		; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 8, align 8, addrspace 5)
; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12		; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C19]](s32)		; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C19]](s32)
; CHECK: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 12, addrspace 5)		; CHECK: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 12, addrspace 5)
		; CHECK: [[UV35:%[0-9]+]]:_(s32), [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32), [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR7]](<5 x s32>)
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C20]](s32)		; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C20]](s32)
; CHECK: G_STORE [[UV35]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 16, align 16, addrspace 5)		; CHECK: G_STORE [[UV35]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 16, align 16, addrspace 5)
; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[PTR_ADD5:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C21]](s32)		; CHECK: [[PTR_ADD5:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C21]](s32)
; CHECK: G_STORE [[UV36]](s32), [[PTR_ADD5]](p5) :: (store 4 into stack + 20, addrspace 5)		; CHECK: G_STORE [[UV36]](s32), [[PTR_ADD5]](p5) :: (store 4 into stack + 20, addrspace 5)
; CHECK: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 24		; CHECK: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C22]](s32)		; CHECK: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C22]](s32)
Show All 37 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll

Show First 20 Lines • Show All 1,861 Lines • ▼ Show 20 Lines	define void @void_func_v32i32_i1_i8_i16(<32 x i32> %arg0, i1 %arg1, i8 %arg2, i16 %arg3, half %arg4) #0 {
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28		; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29		; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30		; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31		; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3		; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3
; CHECK: [[LOAD:%[0-9]+]]:_(s1) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 1 from %fixed-stack.3, align 16, addrspace 5)		; CHECK: [[LOAD:%[0-9]+]]:_(s1) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 1 from %fixed-stack.3, align 16, addrspace 5)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2		; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 1 from %fixed-stack.2, align 4, addrspace 5)		; CHECK: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 2 from %fixed-stack.2, align 4, addrspace 5)
		; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[LOAD1]](s16)
; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1		; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 2 from %fixed-stack.1, align 8, addrspace 5)		; CHECK: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 2 from %fixed-stack.1, align 8, addrspace 5)
; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0		; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD3:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 2 from %fixed-stack.0, align 4, addrspace 5)		; CHECK: [[LOAD3:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 2 from %fixed-stack.0, align 4, addrspace 5)
; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31		; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)		; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; CHECK: [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)		; CHECK: [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; CHECK: [[COPY35:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)		; CHECK: [[COPY35:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; CHECK: [[COPY36:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)		; CHECK: [[COPY36:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; CHECK: G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)		; CHECK: G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)
; CHECK: G_STORE [[LOAD]](s1), [[COPY33]](p1) :: (volatile store 1 into `i1 addrspace(1)* undef`, addrspace 1)		; CHECK: G_STORE [[LOAD]](s1), [[COPY33]](p1) :: (volatile store 1 into `i1 addrspace(1)* undef`, addrspace 1)
; CHECK: G_STORE [[LOAD1]](s8), [[COPY34]](p1) :: (volatile store 1 into `i8 addrspace(1)* undef`, addrspace 1)		; CHECK: G_STORE [[TRUNC]](s8), [[COPY34]](p1) :: (volatile store 1 into `i8 addrspace(1)* undef`, addrspace 1)
; CHECK: G_STORE [[LOAD2]](s16), [[COPY35]](p1) :: (volatile store 2 into `i16 addrspace(1)* undef`, addrspace 1)		; CHECK: G_STORE [[LOAD2]](s16), [[COPY35]](p1) :: (volatile store 2 into `i16 addrspace(1)* undef`, addrspace 1)
; CHECK: G_STORE [[LOAD3]](s16), [[COPY36]](p1) :: (volatile store 2 into `half addrspace(1)* undef`, addrspace 1)		; CHECK: G_STORE [[LOAD3]](s16), [[COPY36]](p1) :: (volatile store 2 into `half addrspace(1)* undef`, addrspace 1)
; CHECK: [[COPY37:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]		; CHECK: [[COPY37:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
; CHECK: S_SETPC_B64_return [[COPY37]]		; CHECK: S_SETPC_B64_return [[COPY37]]
store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef		store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef
store volatile i1 %arg1, i1 addrspace(1)* undef		store volatile i1 %arg1, i1 addrspace(1)* undef
store volatile i8 %arg2, i8 addrspace(1)* undef		store volatile i8 %arg2, i8 addrspace(1)* undef
store volatile i16 %arg3, i16 addrspace(1)* undef		store volatile i16 %arg3, i16 addrspace(1)* undef
▲ Show 20 Lines • Show All 727 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll

	Show First 20 Lines • Show All 485 Lines • ▼ Show 20 Lines
	; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-NEXT: s_mov_b32 s4, 0xffff			; GFX6-NEXT: s_mov_b32 s4, 0xffff
	; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0			; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
	; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1			; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
	; GFX6-NEXT: v_and_b32_e32 v1, s4, v1			; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
	; GFX6-NEXT: v_and_b32_e32 v0, s4, v0			; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
	; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0			; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0
	; GFX6-NEXT: v_lshrrev_b32_e32 v1, v3, v2			; GFX6-NEXT: v_lshrrev_b32_e32 v1, v3, v2
				; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_lshr_v2i16:			; GFX8-LABEL: v_lshr_v2i16:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_lshrrev_b16_e32 v2, v1, v0			; GFX8-NEXT: v_lshrrev_b16_e32 v2, v1, v0
	; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_or_b32_e32 v0, v2, v0			; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX9-LABEL: v_lshr_v2i16:			; GFX9-LABEL: v_lshr_v2i16:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_pk_lshrrev_b16 v0, v1, v0			; GFX9-NEXT: v_pk_lshrrev_b16 v0, v1, v0
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	%result = lshr <2 x i16> %value, %amount			%result = lshr <2 x i16> %value, %amount
	ret <2 x i16> %result			ret <2 x i16> %result
	}			}

	define <2 x i16> @v_lshr_v2i16_15(<2 x i16> %value) {			define <2 x i16> @v_lshr_v2i16_15(<2 x i16> %value) {
	; GFX6-LABEL: v_lshr_v2i16_15:			; GFX6-LABEL: v_lshr_v2i16_15:
	; GFX6: ; %bb.0:			; GFX6: ; %bb.0:
	; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v0			; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v0
	; GFX6-NEXT: v_lshrrev_b32_e32 v2, 15, v1			; GFX6-NEXT: v_lshrrev_b32_e32 v0, 31, v0
	; GFX6-NEXT: v_lshrrev_b32_e32 v1, 31, v0			; GFX6-NEXT: v_lshrrev_b32_e32 v1, 15, v1
	; GFX6-NEXT: v_mov_b32_e32 v0, v2			; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
				; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_lshr_v2i16_15:			; GFX8-LABEL: v_lshr_v2i16_15:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_mov_b32_e32 v2, 15			; GFX8-NEXT: v_mov_b32_e32 v2, 15
	; GFX8-NEXT: v_lshrrev_b16_e32 v1, 15, v0			; GFX8-NEXT: v_lshrrev_b16_e32 v1, 15, v0
	; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1			; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
	▲ Show 20 Lines • Show All 677 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll

Show First 20 Lines • Show All 357 Lines • ▼ Show 20 Lines	; GFX9-NEXT: ; return to shader part epilog
%cast.0 = bitcast <2 x i16> %or0 to i32		%cast.0 = bitcast <2 x i16> %or0 to i32
%cast.1 = bitcast <2 x i16> %or1 to i32		%cast.1 = bitcast <2 x i16> %or1 to i32
%insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0		%insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1		%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
ret { i32, i32 } %insert.1		ret { i32, i32 } %insert.1
}		}

define <2 x i16> @v_orn2_v2i16(<2 x i16> %src0, <2 x i16> %src1) {		define <2 x i16> @v_orn2_v2i16(<2 x i16> %src0, <2 x i16> %src1) {
; GFX6-LABEL: v_orn2_v2i16:		; GCN-LABEL: v_orn2_v2i16:
; GFX6: ; %bb.0:		; GCN: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_xor_b32_e32 v1, -1, v1		; GCN-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GCN-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0		; GCN-NEXT: s_setpc_b64 s[30:31]
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_orn2_v2i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
%not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>		%not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>
%or = or <2 x i16> %src0, %not.src1		%or = or <2 x i16> %src0, %not.src1
ret <2 x i16> %or		ret <2 x i16> %or
}		}

; FIXME:		; FIXME:
; define amdgpu_ps i48 @s_orn2_v3i16(<3 x i16> inreg %src0, <3 x i16> inreg %src1) {		; define amdgpu_ps i48 @s_orn2_v3i16(<3 x i16> inreg %src0, <3 x i16> inreg %src1) {
; %not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -1>		; %not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -1>
▲ Show 20 Lines • Show All 225 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll

	Show First 20 Lines • Show All 172 Lines • ▼ Show 20 Lines
	}			}

	define <2 x half> @v_roundeven_v2f16(<2 x half> %x) {			define <2 x half> @v_roundeven_v2f16(<2 x half> %x) {
	; GFX6-LABEL: v_roundeven_v2f16:			; GFX6-LABEL: v_roundeven_v2f16:
	; GFX6: ; %bb.0:			; GFX6: ; %bb.0:
	; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0			; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0
	; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
	; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v0			; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-NEXT: v_rndne_f32_e32 v0, v1			; GFX6-NEXT: v_rndne_f32_e32 v1, v1
	; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-NEXT: v_rndne_f32_e32 v1, v2
	; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
				; GFX6-NEXT: v_rndne_f32_e32 v0, v0
				; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
				; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
				; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX7-LABEL: v_roundeven_v2f16:			; GFX7-LABEL: v_roundeven_v2f16:
	; GFX7: ; %bb.0:			; GFX7: ; %bb.0:
	; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v0			; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v0
	; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
	; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v0			; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX7-NEXT: v_rndne_f32_e32 v0, v1			; GFX7-NEXT: v_rndne_f32_e32 v1, v1
	; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX7-NEXT: v_rndne_f32_e32 v1, v2
	; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1
				; GFX7-NEXT: v_rndne_f32_e32 v0, v0
				; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
				; GFX7-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX7-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
				; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX7-NEXT: s_setpc_b64 s[30:31]			; GFX7-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_roundeven_v2f16:			; GFX8-LABEL: v_roundeven_v2f16:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_rndne_f16_e32 v1, v0			; GFX8-NEXT: v_rndne_f16_e32 v1, v0
	; GFX8-NEXT: v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1			; GFX8-NEXT: v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
	; GFX8-NEXT: v_mov_b32_e32 v2, 16			; GFX8-NEXT: v_mov_b32_e32 v2, 16
	Show All 15 Lines

	define <2 x half> @v_roundeven_v2f16_fneg(<2 x half> %x) {			define <2 x half> @v_roundeven_v2f16_fneg(<2 x half> %x) {
	; GFX6-LABEL: v_roundeven_v2f16_fneg:			; GFX6-LABEL: v_roundeven_v2f16_fneg:
	; GFX6: ; %bb.0:			; GFX6: ; %bb.0:
	; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0			; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
	; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0			; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0
	; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
	; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v0			; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX6-NEXT: v_rndne_f32_e32 v0, v1			; GFX6-NEXT: v_rndne_f32_e32 v1, v1
	; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX6-NEXT: v_rndne_f32_e32 v1, v2
	; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
				; GFX6-NEXT: v_rndne_f32_e32 v0, v0
				; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
				; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
				; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX7-LABEL: v_roundeven_v2f16_fneg:			; GFX7-LABEL: v_roundeven_v2f16_fneg:
	; GFX7: ; %bb.0:			; GFX7: ; %bb.0:
	; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX7-NEXT: v_xor_b32_e32 v0, 0x80008000, v0			; GFX7-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
	; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v0			; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v0
	; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0			; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
	; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v0			; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
	; GFX7-NEXT: v_rndne_f32_e32 v0, v1			; GFX7-NEXT: v_rndne_f32_e32 v1, v1
	; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX7-NEXT: v_rndne_f32_e32 v1, v2
	; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1			; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1
				; GFX7-NEXT: v_rndne_f32_e32 v0, v0
				; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
				; GFX7-NEXT: v_bfe_u32 v1, v1, 0, 16
				; GFX7-NEXT: v_bfe_u32 v0, v0, 0, 16
				; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
				; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX7-NEXT: s_setpc_b64 s[30:31]			; GFX7-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_roundeven_v2f16_fneg:			; GFX8-LABEL: v_roundeven_v2f16_fneg:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0			; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
	; GFX8-NEXT: v_rndne_f16_e32 v1, v0			; GFX8-NEXT: v_rndne_f16_e32 v1, v0
	; GFX8-NEXT: v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1			; GFX8-NEXT: v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
	▲ Show 20 Lines • Show All 308 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 2,718 Lines • ▼ Show 20 Lines
	; GFX6-NEXT: v_min_i32_e32 v4, 0, v1			; GFX6-NEXT: v_min_i32_e32 v4, 0, v1
	; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3			; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
	; GFX6-NEXT: v_max_i32_e32 v3, 0, v1			; GFX6-NEXT: v_max_i32_e32 v3, 0, v1
	; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s5, v4			; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s5, v4
	; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v3			; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v3
	; GFX6-NEXT: v_max_i32_e32 v2, v4, v2			; GFX6-NEXT: v_max_i32_e32 v2, v4, v2
	; GFX6-NEXT: v_min_i32_e32 v2, v2, v3			; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
	; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2			; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
	; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
	; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1			; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
				; GFX6-NEXT: s_mov_b32 s4, 0xffff
				; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
				; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
				; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
				; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_saddsat_v2i16:			; GFX8-LABEL: v_saddsat_v2i16:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: s_movk_i32 s5, 0x8000			; GFX8-NEXT: s_movk_i32 s5, 0x8000
	; GFX8-NEXT: v_min_i16_e32 v4, 0, v0			; GFX8-NEXT: v_min_i16_e32 v4, 0, v0
	; GFX8-NEXT: v_sub_u16_e32 v4, s5, v4			; GFX8-NEXT: v_sub_u16_e32 v4, s5, v4
	▲ Show 20 Lines • Show All 4,069 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll

Show First 20 Lines • Show All 479 Lines • ▼ Show 20 Lines	; GFX9-NEXT: ; return to shader part epilog
%cast = bitcast i16 %result to half		%cast = bitcast i16 %result to half
ret half %cast		ret half %cast
}		}

define <2 x i16> @v_shl_v2i16(<2 x i16> %value, <2 x i16> %amount) {		define <2 x i16> @v_shl_v2i16(<2 x i16> %value, <2 x i16> %amount) {
; GFX6-LABEL: v_shl_v2i16:		; GFX6-LABEL: v_shl_v2i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v1, v0		; GFX6-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v3, v2		; GFX6-NEXT: v_lshlrev_b32_e32 v1, v3, v2
		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_shl_v2i16:		; GFX8-LABEL: v_shl_v2i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b16_e32 v2, v1, v0		; GFX8-NEXT: v_lshlrev_b16_e32 v2, v1, v0
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1		; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0		; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
Show All 9 Lines
}		}

define <2 x i16> @v_shl_v2i16_15(<2 x i16> %value) {		define <2 x i16> @v_shl_v2i16_15(<2 x i16> %value) {
; GFX6-LABEL: v_shl_v2i16_15:		; GFX6-LABEL: v_shl_v2i16_15:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 15, v0		; GFX6-NEXT: v_lshlrev_b32_e32 v0, 15, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 15, v1		; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 31, v1
		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_shl_v2i16_15:		; GFX8-LABEL: v_shl_v2i16_15:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, 15		; GFX8-NEXT: v_mov_b32_e32 v2, 15
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 15, v0		; GFX8-NEXT: v_lshlrev_b16_e32 v1, 15, v0
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1		; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
▲ Show 20 Lines • Show All 663 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 2,698 Lines • ▼ Show 20 Lines
	; GFX6-NEXT: v_min_i32_e32 v5, -1, v0			; GFX6-NEXT: v_min_i32_e32 v5, -1, v0
	; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v5			; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v5
	; GFX6-NEXT: v_max_i32_e32 v1, v4, v1			; GFX6-NEXT: v_max_i32_e32 v1, v4, v1
	; GFX6-NEXT: v_min_i32_e32 v1, v1, v5			; GFX6-NEXT: v_min_i32_e32 v1, v1, v5
	; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1			; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
	; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v2			; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v2
	; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3			; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
	; GFX6-NEXT: v_max_i32_e32 v3, -1, v1			; GFX6-NEXT: v_max_i32_e32 v3, -1, v1
	; GFX6-NEXT: v_min_i32_e32 v4, -1, v1
	; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3			; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3
				; GFX6-NEXT: v_min_i32_e32 v4, -1, v1
	; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v4			; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v4
	; GFX6-NEXT: v_max_i32_e32 v2, v3, v2			; GFX6-NEXT: v_max_i32_e32 v2, v3, v2
	; GFX6-NEXT: v_min_i32_e32 v2, v2, v4			; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
	; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2			; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
	; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
	; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1			; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
				; GFX6-NEXT: s_mov_b32 s4, 0xffff
				; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
				; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
				; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
				; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_ssubsat_v2i16:			; GFX8-LABEL: v_ssubsat_v2i16:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: s_movk_i32 s4, 0x7fff			; GFX8-NEXT: s_movk_i32 s4, 0x7fff
	; GFX8-NEXT: v_max_i16_e32 v3, -1, v0			; GFX8-NEXT: v_max_i16_e32 v3, -1, v0
	; GFX8-NEXT: v_subrev_u16_e32 v3, s4, v3			; GFX8-NEXT: v_subrev_u16_e32 v3, s4, v3
	▲ Show 20 Lines • Show All 4,069 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll

	Show First 20 Lines • Show All 1,754 Lines • ▼ Show 20 Lines
	; GFX6-NEXT: v_xor_b32_e32 v4, -1, v0			; GFX6-NEXT: v_xor_b32_e32 v4, -1, v0
	; GFX6-NEXT: v_min_u32_e32 v1, v4, v1			; GFX6-NEXT: v_min_u32_e32 v1, v4, v1
	; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1			; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
	; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v2			; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v2
	; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3			; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
	; GFX6-NEXT: v_xor_b32_e32 v3, -1, v1			; GFX6-NEXT: v_xor_b32_e32 v3, -1, v1
	; GFX6-NEXT: v_min_u32_e32 v2, v3, v2			; GFX6-NEXT: v_min_u32_e32 v2, v3, v2
	; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2			; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
	; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
	; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1			; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
				; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_uaddsat_v2i16:			; GFX8-LABEL: v_uaddsat_v2i16:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_add_u16_e64 v2, v0, v1 clamp			; GFX8-NEXT: v_add_u16_e64 v2, v0, v1 clamp
	; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_mov_b32_e32 v1, 16			; GFX8-NEXT: v_mov_b32_e32 v1, 16
	▲ Show 20 Lines • Show All 2,057 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll

	Show First 20 Lines • Show All 1,666 Lines • ▼ Show 20 Lines
	; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0			; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
	; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1			; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
	; GFX6-NEXT: v_min_u32_e32 v1, v0, v1			; GFX6-NEXT: v_min_u32_e32 v1, v0, v1
	; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1			; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
	; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v2			; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v2
	; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3			; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
	; GFX6-NEXT: v_min_u32_e32 v2, v1, v2			; GFX6-NEXT: v_min_u32_e32 v2, v1, v2
	; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2			; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
	; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
	; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1			; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
				; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
				; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_usubsat_v2i16:			; GFX8-LABEL: v_usubsat_v2i16:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_sub_u16_e64 v2, v0, v1 clamp			; GFX8-NEXT: v_sub_u16_e64 v2, v0, v1 clamp
	; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_mov_b32_e32 v1, 16			; GFX8-NEXT: v_mov_b32_e32 v1, 16
	▲ Show 20 Lines • Show All 2,015 Lines • Show Last 20 Lines

llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

Show First 20 Lines • Show All 1,982 Lines • ▼ Show 20 Lines	TEST_F(AArch64GISelMITest, LibcallSRem) {
CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT		CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT
CHECK: $w0 = COPY [[TRUNC]]		CHECK: $w0 = COPY [[TRUNC]]
CHECK: $w1 = COPY [[TRUNC]]		CHECK: $w1 = COPY [[TRUNC]]
CHECK: BL &__modsi3		CHECK: BL &__modsi3
CHECK: $x0 = COPY [[COPY]]		CHECK: $x0 = COPY [[COPY]]
CHECK: $x1 = COPY [[COPY]]		CHECK: $x1 = COPY [[COPY]]
CHECK: BL &__moddi3		CHECK: BL &__moddi3
CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]		CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
CHECK: $x0 = COPY [[UV]]		CHECK: $x0 = COPY [[UV]]
CHECK: $x1 = COPY [[UV1]]		CHECK: $x1 = COPY [[UV1]]
		CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
CHECK: $x2 = COPY [[UV2]]		CHECK: $x2 = COPY [[UV2]]
CHECK: $x3 = COPY [[UV3]]		CHECK: $x3 = COPY [[UV3]]
CHECK: BL &__modti3		CHECK: BL &__modti3
)";		)";

// Check		// Check
EXPECT_TRUE(CheckMachineFunction(MF, CheckStr)) << MF;		EXPECT_TRUE(CheckMachineFunction(MF, CheckStr)) << MF;
}		}
Show All 38 Lines	TEST_F(AArch64GISelMITest, LibcallURem) {
CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT		CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT
CHECK: $w0 = COPY [[TRUNC]]		CHECK: $w0 = COPY [[TRUNC]]
CHECK: $w1 = COPY [[TRUNC]]		CHECK: $w1 = COPY [[TRUNC]]
CHECK: BL &__umodsi3		CHECK: BL &__umodsi3
CHECK: $x0 = COPY [[COPY]]		CHECK: $x0 = COPY [[COPY]]
CHECK: $x1 = COPY [[COPY]]		CHECK: $x1 = COPY [[COPY]]
CHECK: BL &__umoddi3		CHECK: BL &__umoddi3
CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]		CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
CHECK: $x0 = COPY [[UV]]		CHECK: $x0 = COPY [[UV]]
CHECK: $x1 = COPY [[UV1]]		CHECK: $x1 = COPY [[UV1]]
		CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
CHECK: $x2 = COPY [[UV2]]		CHECK: $x2 = COPY [[UV2]]
CHECK: $x3 = COPY [[UV3]]		CHECK: $x3 = COPY [[UV3]]
CHECK: BL &__umodti3		CHECK: BL &__umodti3
)";		)";

// Check		// Check
EXPECT_TRUE(CheckMachineFunction(MF, CheckStr)) << MF;		EXPECT_TRUE(CheckMachineFunction(MF, CheckStr)) << MF;
}		}
▲ Show 20 Lines • Show All 1,711 Lines • Show Last 20 Lines

This is an archive of the discontinued LLVM Phabricator instance.

GlobalISel: Merge and cleanup more AMDGPU call lowering code
ClosedPublic

Details

Diff Detail

Unit TestsFailed

Event Timeline

Revision Contents

Diff 326967

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll

llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll

llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir

llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll

llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

This is an archive of the discontinued LLVM Phabricator instance.

GlobalISel: Merge and cleanup more AMDGPU call lowering codeClosedPublic

Details

Diff Detail

Unit TestsFailed

Event Timeline

Revision Contents

Diff 326967

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll

llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll

llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir

llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll

llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

GlobalISel: Merge and cleanup more AMDGPU call lowering code
ClosedPublic