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Differential D97303

[AArch64] Use CMTST for != 0 vector compares (vnot (CMEQz A)).
ClosedPublic

Authored by fhahn on Feb 23 2021, 9:15 AM.

Details

Reviewers
dmgreen
SjoerdMeijer
aemerson
paquette
Commits
rG5c74c6be3c29: [AArch64] Use CMTST for != 0 vector compares (vnot (CMEQz A)).
Summary

(CMTST A, A) will only set elements to 0 if the element is 0 in A. Use
it for != 0 compares, which currently use (vnot (CMEQz A)). This saves a
mvn instruction.

Diff Detail

Event Timeline

fhahn created this revision.Feb 23 2021, 9:15 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald TranscriptFeb 23 2021, 9:15 AM
fhahn requested review of this revision.Feb 23 2021, 9:15 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 23 2021, 9:15 AM
Harbormaster completed remote builds in B90417: Diff 325811.Feb 23 2021, 9:15 AM
dmgreen accepted this revision.Feb 23 2021, 9:56 AM

LGTM. Looks like a nice extension to the existing AArch64cmtst pattern.

This revision is now accepted and ready to land.Feb 23 2021, 9:56 AM
fhahn mentioned this in rGfd03e359ddbb: [AArch64] Regenerate check lines for neon-compare-instructions.ll..Feb 23 2021, 11:40 AM
This revision was landed with ongoing or failed builds.Feb 24 2021, 1:39 AM
Closed by commit rG5c74c6be3c29: [AArch64] Use CMTST for != 0 vector compares (vnot (CMEQz A)). (authored by fhahn). · Explain Why
This revision was automatically updated to reflect the committed changes.
fhahn added a commit: rG5c74c6be3c29: [AArch64] Use CMTST for != 0 vector compares (vnot (CMEQz A))..
fhahn added a comment.Feb 24 2021, 1:49 AM
In D97303#2582373, @dmgreen wrote:

LGTM. Looks like a nice extension to the existing AArch64cmtst pattern.

Thanks, once I found the right place to add it fit in quite nicely :)

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
3 lines
test/
CodeGen/
AArch64/
21 lines
58 lines

Diff 326018

llvm/lib/Target/AArch64/AArch64InstrInfo.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>; defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>; defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>; defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>; defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>; defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>; defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>; defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>; defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
foreach VT = [ v8i8, v16i8, v4i16, v8i16, v2i32, v4i32, v2i64 ] in {
def : Pat<(vnot (AArch64cmeqz VT:$Rn)), (!cast<Instruction>("CMTST"#VT) VT:$Rn, VT:$Rn)>;
}
defm FABD : SIMDThreeSameVectorFP<1,1,0b010,"fabd", int_aarch64_neon_fabd>; defm FABD : SIMDThreeSameVectorFP<1,1,0b010,"fabd", int_aarch64_neon_fabd>;
let Predicates = [HasNEON] in { let Predicates = [HasNEON] in {
foreach VT = [ v2f32, v4f32, v2f64 ] in foreach VT = [ v2f32, v4f32, v2f64 ] in
def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>; def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>;
} }
let Predicates = [HasNEON, HasFullFP16] in { let Predicates = [HasNEON, HasFullFP16] in {
foreach VT = [ v4f16, v8f16 ] in foreach VT = [ v4f16, v8f16 ] in
def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>; def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>;
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llvm/test/CodeGen/AArch64/neon-compare-instructions.ll

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%tmp3 = icmp slt <2 x i64> %A, zeroinitializer; %tmp3 = icmp slt <2 x i64> %A, zeroinitializer;
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64> %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4 ret <2 x i64> %tmp4
} }
define <8 x i8> @cmneqz8xi8(<8 x i8> %A) { define <8 x i8> @cmneqz8xi8(<8 x i8> %A) {
; CHECK-LABEL: cmneqz8xi8: ; CHECK-LABEL: cmneqz8xi8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmeq v0.8b, v0.8b, #0 ; CHECK-NEXT: cmtst v0.8b, v0.8b, v0.8b
; CHECK-NEXT: mvn v0.8b, v0.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = icmp ne <8 x i8> %A, zeroinitializer; %tmp3 = icmp ne <8 x i8> %A, zeroinitializer;
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8> %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4 ret <8 x i8> %tmp4
} }
define <16 x i8> @cmneqz16xi8(<16 x i8> %A) { define <16 x i8> @cmneqz16xi8(<16 x i8> %A) {
; CHECK-LABEL: cmneqz16xi8: ; CHECK-LABEL: cmneqz16xi8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmeq v0.16b, v0.16b, #0 ; CHECK-NEXT: cmtst v0.16b, v0.16b, v0.16b
; CHECK-NEXT: mvn v0.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = icmp ne <16 x i8> %A, zeroinitializer; %tmp3 = icmp ne <16 x i8> %A, zeroinitializer;
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8> %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4 ret <16 x i8> %tmp4
} }
define <4 x i16> @cmneqz4xi16(<4 x i16> %A) { define <4 x i16> @cmneqz4xi16(<4 x i16> %A) {
; CHECK-LABEL: cmneqz4xi16: ; CHECK-LABEL: cmneqz4xi16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmeq v0.4h, v0.4h, #0 ; CHECK-NEXT: cmtst v0.4h, v0.4h, v0.4h
; CHECK-NEXT: mvn v0.8b, v0.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = icmp ne <4 x i16> %A, zeroinitializer; %tmp3 = icmp ne <4 x i16> %A, zeroinitializer;
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16> %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4 ret <4 x i16> %tmp4
} }
define <8 x i16> @cmneqz8xi16(<8 x i16> %A) { define <8 x i16> @cmneqz8xi16(<8 x i16> %A) {
; CHECK-LABEL: cmneqz8xi16: ; CHECK-LABEL: cmneqz8xi16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmeq v0.8h, v0.8h, #0 ; CHECK-NEXT: cmtst v0.8h, v0.8h, v0.8h
; CHECK-NEXT: mvn v0.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = icmp ne <8 x i16> %A, zeroinitializer; %tmp3 = icmp ne <8 x i16> %A, zeroinitializer;
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16> %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4 ret <8 x i16> %tmp4
} }
define <2 x i32> @cmneqz2xi32(<2 x i32> %A) { define <2 x i32> @cmneqz2xi32(<2 x i32> %A) {
; CHECK-LABEL: cmneqz2xi32: ; CHECK-LABEL: cmneqz2xi32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmeq v0.2s, v0.2s, #0 ; CHECK-NEXT: cmtst v0.2s, v0.2s, v0.2s
; CHECK-NEXT: mvn v0.8b, v0.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = icmp ne <2 x i32> %A, zeroinitializer; %tmp3 = icmp ne <2 x i32> %A, zeroinitializer;
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32> %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4 ret <2 x i32> %tmp4
} }
define <4 x i32> @cmneqz4xi32(<4 x i32> %A) { define <4 x i32> @cmneqz4xi32(<4 x i32> %A) {
; CHECK-LABEL: cmneqz4xi32: ; CHECK-LABEL: cmneqz4xi32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: cmtst v0.4s, v0.4s, v0.4s
; CHECK-NEXT: mvn v0.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = icmp ne <4 x i32> %A, zeroinitializer; %tmp3 = icmp ne <4 x i32> %A, zeroinitializer;
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32> %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4 ret <4 x i32> %tmp4
} }
define <2 x i64> @cmneqz2xi64(<2 x i64> %A) { define <2 x i64> @cmneqz2xi64(<2 x i64> %A) {
; CHECK-LABEL: cmneqz2xi64: ; CHECK-LABEL: cmneqz2xi64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmeq v0.2d, v0.2d, #0 ; CHECK-NEXT: cmtst v0.2d, v0.2d, v0.2d
; CHECK-NEXT: mvn v0.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = icmp ne <2 x i64> %A, zeroinitializer; %tmp3 = icmp ne <2 x i64> %A, zeroinitializer;
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64> %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4 ret <2 x i64> %tmp4
} }
define <8 x i8> @cmhsz8xi8(<8 x i8> %A) { define <8 x i8> @cmhsz8xi8(<8 x i8> %A) {
; CHECK-LABEL: cmhsz8xi8: ; CHECK-LABEL: cmhsz8xi8:
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llvm/test/CodeGen/AArch64/vec_umulo.ll

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declare {<4 x i1>, <4 x i1>} @llvm.umul.with.overflow.v4i1(<4 x i1>, <4 x i1>) declare {<4 x i1>, <4 x i1>} @llvm.umul.with.overflow.v4i1(<4 x i1>, <4 x i1>)
declare {<2 x i128>, <2 x i1>} @llvm.umul.with.overflow.v2i128(<2 x i128>, <2 x i128>) declare {<2 x i128>, <2 x i1>} @llvm.umul.with.overflow.v2i128(<2 x i128>, <2 x i128>)
define <1 x i32> @umulo_v1i32(<1 x i32> %a0, <1 x i32> %a1, <1 x i32>* %p2) nounwind { define <1 x i32> @umulo_v1i32(<1 x i32> %a0, <1 x i32> %a1, <1 x i32>* %p2) nounwind {
; CHECK-LABEL: umulo_v1i32: ; CHECK-LABEL: umulo_v1i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s ; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s
; CHECK-NEXT: shrn v0.2s, v1.2d, #32 ; CHECK-NEXT: shrn v0.2s, v1.2d, #32
; CHECK-NEXT: cmeq v0.2s, v0.2s, #0 ; CHECK-NEXT: cmtst v0.2s, v0.2s, v0.2s
; CHECK-NEXT: mvn v0.8b, v0.8b
; CHECK-NEXT: xtn v1.2s, v1.2d ; CHECK-NEXT: xtn v1.2s, v1.2d
; CHECK-NEXT: str s1, [x0] ; CHECK-NEXT: str s1, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<1 x i32>, <1 x i1>} @llvm.umul.with.overflow.v1i32(<1 x i32> %a0, <1 x i32> %a1) %t = call {<1 x i32>, <1 x i1>} @llvm.umul.with.overflow.v1i32(<1 x i32> %a0, <1 x i32> %a1)
%val = extractvalue {<1 x i32>, <1 x i1>} %t, 0 %val = extractvalue {<1 x i32>, <1 x i1>} %t, 0
%obit = extractvalue {<1 x i32>, <1 x i1>} %t, 1 %obit = extractvalue {<1 x i32>, <1 x i1>} %t, 1
%res = sext <1 x i1> %obit to <1 x i32> %res = sext <1 x i1> %obit to <1 x i32>
store <1 x i32> %val, <1 x i32>* %p2 store <1 x i32> %val, <1 x i32>* %p2
ret <1 x i32> %res ret <1 x i32> %res
} }
define <2 x i32> @umulo_v2i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32>* %p2) nounwind { define <2 x i32> @umulo_v2i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32>* %p2) nounwind {
; CHECK-LABEL: umulo_v2i32: ; CHECK-LABEL: umulo_v2i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s ; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s
; CHECK-NEXT: shrn v0.2s, v1.2d, #32 ; CHECK-NEXT: shrn v0.2s, v1.2d, #32
; CHECK-NEXT: cmeq v0.2s, v0.2s, #0 ; CHECK-NEXT: cmtst v0.2s, v0.2s, v0.2s
; CHECK-NEXT: mvn v0.8b, v0.8b
; CHECK-NEXT: xtn v1.2s, v1.2d ; CHECK-NEXT: xtn v1.2s, v1.2d
; CHECK-NEXT: str d1, [x0] ; CHECK-NEXT: str d1, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<2 x i32>, <2 x i1>} @llvm.umul.with.overflow.v2i32(<2 x i32> %a0, <2 x i32> %a1) %t = call {<2 x i32>, <2 x i1>} @llvm.umul.with.overflow.v2i32(<2 x i32> %a0, <2 x i32> %a1)
%val = extractvalue {<2 x i32>, <2 x i1>} %t, 0 %val = extractvalue {<2 x i32>, <2 x i1>} %t, 0
%obit = extractvalue {<2 x i32>, <2 x i1>} %t, 1 %obit = extractvalue {<2 x i32>, <2 x i1>} %t, 1
%res = sext <2 x i1> %obit to <2 x i32> %res = sext <2 x i1> %obit to <2 x i32>
store <2 x i32> %val, <2 x i32>* %p2 store <2 x i32> %val, <2 x i32>* %p2
ret <2 x i32> %res ret <2 x i32> %res
} }
define <3 x i32> @umulo_v3i32(<3 x i32> %a0, <3 x i32> %a1, <3 x i32>* %p2) nounwind { define <3 x i32> @umulo_v3i32(<3 x i32> %a0, <3 x i32> %a1, <3 x i32>* %p2) nounwind {
; CHECK-LABEL: umulo_v3i32: ; CHECK-LABEL: umulo_v3i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s ; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s
; CHECK-NEXT: umull v3.2d, v0.2s, v1.2s ; CHECK-NEXT: umull v3.2d, v0.2s, v1.2s
; CHECK-NEXT: mul v1.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v1.4s, v0.4s, v1.4s
; CHECK-NEXT: uzp2 v0.4s, v3.4s, v2.4s ; CHECK-NEXT: uzp2 v0.4s, v3.4s, v2.4s
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-NEXT: add x8, x0, #8 // =8 ; CHECK-NEXT: add x8, x0, #8 // =8
; CHECK-NEXT: mvn v0.16b, v0.16b ; CHECK-NEXT: cmtst v0.4s, v0.4s, v0.4s
; CHECK-NEXT: st1 { v1.s }[2], [x8] ; CHECK-NEXT: st1 { v1.s }[2], [x8]
; CHECK-NEXT: str d1, [x0] ; CHECK-NEXT: str d1, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<3 x i32>, <3 x i1>} @llvm.umul.with.overflow.v3i32(<3 x i32> %a0, <3 x i32> %a1) %t = call {<3 x i32>, <3 x i1>} @llvm.umul.with.overflow.v3i32(<3 x i32> %a0, <3 x i32> %a1)
%val = extractvalue {<3 x i32>, <3 x i1>} %t, 0 %val = extractvalue {<3 x i32>, <3 x i1>} %t, 0
%obit = extractvalue {<3 x i32>, <3 x i1>} %t, 1 %obit = extractvalue {<3 x i32>, <3 x i1>} %t, 1
%res = sext <3 x i1> %obit to <3 x i32> %res = sext <3 x i1> %obit to <3 x i32>
store <3 x i32> %val, <3 x i32>* %p2 store <3 x i32> %val, <3 x i32>* %p2
ret <3 x i32> %res ret <3 x i32> %res
} }
define <4 x i32> @umulo_v4i32(<4 x i32> %a0, <4 x i32> %a1, <4 x i32>* %p2) nounwind { define <4 x i32> @umulo_v4i32(<4 x i32> %a0, <4 x i32> %a1, <4 x i32>* %p2) nounwind {
; CHECK-LABEL: umulo_v4i32: ; CHECK-LABEL: umulo_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s ; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s
; CHECK-NEXT: umull v3.2d, v0.2s, v1.2s ; CHECK-NEXT: umull v3.2d, v0.2s, v1.2s
; CHECK-NEXT: uzp2 v2.4s, v3.4s, v2.4s ; CHECK-NEXT: uzp2 v2.4s, v3.4s, v2.4s
; CHECK-NEXT: cmeq v2.4s, v2.4s, #0 ; CHECK-NEXT: cmtst v2.4s, v2.4s, v2.4s
; CHECK-NEXT: mvn v2.16b, v2.16b
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<4 x i32>, <4 x i1>} @llvm.umul.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> %a1) %t = call {<4 x i32>, <4 x i1>} @llvm.umul.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> %a1)
%val = extractvalue {<4 x i32>, <4 x i1>} %t, 0 %val = extractvalue {<4 x i32>, <4 x i1>} %t, 0
%obit = extractvalue {<4 x i32>, <4 x i1>} %t, 1 %obit = extractvalue {<4 x i32>, <4 x i1>} %t, 1
%res = sext <4 x i1> %obit to <4 x i32> %res = sext <4 x i1> %obit to <4 x i32>
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; CHECK-NEXT: umull2 v4.2d, v1.4s, v0.4s ; CHECK-NEXT: umull2 v4.2d, v1.4s, v0.4s
; CHECK-NEXT: umull v5.2d, v1.2s, v0.2s ; CHECK-NEXT: umull v5.2d, v1.2s, v0.2s
; CHECK-NEXT: mul v0.4s, v1.4s, v0.4s ; CHECK-NEXT: mul v0.4s, v1.4s, v0.4s
; CHECK-NEXT: uzp2 v1.4s, v5.4s, v4.4s ; CHECK-NEXT: uzp2 v1.4s, v5.4s, v4.4s
; CHECK-NEXT: str d0, [x11, #16] ; CHECK-NEXT: str d0, [x11, #16]
; CHECK-NEXT: umull2 v0.2d, v3.4s, v2.4s ; CHECK-NEXT: umull2 v0.2d, v3.4s, v2.4s
; CHECK-NEXT: umull v4.2d, v3.2s, v2.2s ; CHECK-NEXT: umull v4.2d, v3.2s, v2.2s
; CHECK-NEXT: uzp2 v0.4s, v4.4s, v0.4s ; CHECK-NEXT: uzp2 v0.4s, v4.4s, v0.4s
; CHECK-NEXT: cmeq v1.4s, v1.4s, #0 ; CHECK-NEXT: cmtst v1.4s, v1.4s, v1.4s
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: cmtst v0.4s, v0.4s, v0.4s
; CHECK-NEXT: mvn v1.16b, v1.16b
; CHECK-NEXT: mvn v0.16b, v0.16b
; CHECK-NEXT: mul v2.4s, v3.4s, v2.4s ; CHECK-NEXT: mul v2.4s, v3.4s, v2.4s
; CHECK-NEXT: mov w5, v1.s[1] ; CHECK-NEXT: mov w5, v1.s[1]
; CHECK-NEXT: mov w1, v0.s[1] ; CHECK-NEXT: mov w1, v0.s[1]
; CHECK-NEXT: mov w2, v0.s[2] ; CHECK-NEXT: mov w2, v0.s[2]
; CHECK-NEXT: mov w3, v0.s[3] ; CHECK-NEXT: mov w3, v0.s[3]
; CHECK-NEXT: fmov w4, s1 ; CHECK-NEXT: fmov w4, s1
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: str q2, [x11] ; CHECK-NEXT: str q2, [x11]
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; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umull2 v4.2d, v0.4s, v2.4s ; CHECK-NEXT: umull2 v4.2d, v0.4s, v2.4s
; CHECK-NEXT: umull v5.2d, v0.2s, v2.2s ; CHECK-NEXT: umull v5.2d, v0.2s, v2.2s
; CHECK-NEXT: umull2 v6.2d, v1.4s, v3.4s ; CHECK-NEXT: umull2 v6.2d, v1.4s, v3.4s
; CHECK-NEXT: mul v2.4s, v0.4s, v2.4s ; CHECK-NEXT: mul v2.4s, v0.4s, v2.4s
; CHECK-NEXT: umull v0.2d, v1.2s, v3.2s ; CHECK-NEXT: umull v0.2d, v1.2s, v3.2s
; CHECK-NEXT: mul v3.4s, v1.4s, v3.4s ; CHECK-NEXT: mul v3.4s, v1.4s, v3.4s
; CHECK-NEXT: uzp2 v1.4s, v5.4s, v4.4s ; CHECK-NEXT: uzp2 v1.4s, v5.4s, v4.4s
; CHECK-NEXT: uzp2 v0.4s, v0.4s, v6.4s ; CHECK-NEXT: uzp2 v4.4s, v0.4s, v6.4s
; CHECK-NEXT: cmeq v1.4s, v1.4s, #0 ; CHECK-NEXT: cmtst v0.4s, v1.4s, v1.4s
; CHECK-NEXT: cmeq v4.4s, v0.4s, #0 ; CHECK-NEXT: cmtst v1.4s, v4.4s, v4.4s
; CHECK-NEXT: mvn v0.16b, v1.16b
; CHECK-NEXT: mvn v1.16b, v4.16b
; CHECK-NEXT: stp q2, q3, [x0] ; CHECK-NEXT: stp q2, q3, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<8 x i32>, <8 x i1>} @llvm.umul.with.overflow.v8i32(<8 x i32> %a0, <8 x i32> %a1) %t = call {<8 x i32>, <8 x i1>} @llvm.umul.with.overflow.v8i32(<8 x i32> %a0, <8 x i32> %a1)
%val = extractvalue {<8 x i32>, <8 x i1>} %t, 0 %val = extractvalue {<8 x i32>, <8 x i1>} %t, 0
%obit = extractvalue {<8 x i32>, <8 x i1>} %t, 1 %obit = extractvalue {<8 x i32>, <8 x i1>} %t, 1
%res = sext <8 x i1> %obit to <8 x i32> %res = sext <8 x i1> %obit to <8 x i32>
store <8 x i32> %val, <8 x i32>* %p2 store <8 x i32> %val, <8 x i32>* %p2
ret <8 x i32> %res ret <8 x i32> %res
} }
define <16 x i32> @umulo_v16i8(<16 x i8> %a0, <16 x i8> %a1, <16 x i8>* %p2) nounwind { define <16 x i32> @umulo_v16i8(<16 x i8> %a0, <16 x i8> %a1, <16 x i8>* %p2) nounwind {
; CHECK-LABEL: umulo_v16i8: ; CHECK-LABEL: umulo_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umull2 v2.8h, v0.16b, v1.16b ; CHECK-NEXT: umull2 v2.8h, v0.16b, v1.16b
; CHECK-NEXT: umull v3.8h, v0.8b, v1.8b ; CHECK-NEXT: umull v3.8h, v0.8b, v1.8b
; CHECK-NEXT: mul v4.16b, v0.16b, v1.16b ; CHECK-NEXT: mul v4.16b, v0.16b, v1.16b
; CHECK-NEXT: uzp2 v0.16b, v3.16b, v2.16b ; CHECK-NEXT: uzp2 v0.16b, v3.16b, v2.16b
; CHECK-NEXT: cmeq v0.16b, v0.16b, #0 ; CHECK-NEXT: cmtst v0.16b, v0.16b, v0.16b
; CHECK-NEXT: mvn v0.16b, v0.16b
; CHECK-NEXT: zip1 v1.8b, v0.8b, v0.8b ; CHECK-NEXT: zip1 v1.8b, v0.8b, v0.8b
; CHECK-NEXT: zip2 v2.8b, v0.8b, v0.8b ; CHECK-NEXT: zip2 v2.8b, v0.8b, v0.8b
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: ushll v1.4s, v1.4h, #0 ; CHECK-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-NEXT: ushll v2.4s, v2.4h, #0 ; CHECK-NEXT: ushll v2.4s, v2.4h, #0
; CHECK-NEXT: zip1 v3.8b, v0.8b, v0.8b ; CHECK-NEXT: zip1 v3.8b, v0.8b, v0.8b
; CHECK-NEXT: zip2 v0.8b, v0.8b, v0.8b ; CHECK-NEXT: zip2 v0.8b, v0.8b, v0.8b
; CHECK-NEXT: shl v1.4s, v1.4s, #31 ; CHECK-NEXT: shl v1.4s, v1.4s, #31
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define <8 x i32> @umulo_v8i16(<8 x i16> %a0, <8 x i16> %a1, <8 x i16>* %p2) nounwind { define <8 x i32> @umulo_v8i16(<8 x i16> %a0, <8 x i16> %a1, <8 x i16>* %p2) nounwind {
; CHECK-LABEL: umulo_v8i16: ; CHECK-LABEL: umulo_v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umull2 v2.4s, v0.8h, v1.8h ; CHECK-NEXT: umull2 v2.4s, v0.8h, v1.8h
; CHECK-NEXT: umull v3.4s, v0.4h, v1.4h ; CHECK-NEXT: umull v3.4s, v0.4h, v1.4h
; CHECK-NEXT: mul v4.8h, v0.8h, v1.8h ; CHECK-NEXT: mul v4.8h, v0.8h, v1.8h
; CHECK-NEXT: uzp2 v0.8h, v3.8h, v2.8h ; CHECK-NEXT: uzp2 v0.8h, v3.8h, v2.8h
; CHECK-NEXT: cmeq v0.8h, v0.8h, #0 ; CHECK-NEXT: cmtst v0.8h, v0.8h, v0.8h
; CHECK-NEXT: mvn v0.16b, v0.16b
; CHECK-NEXT: xtn v0.8b, v0.8h ; CHECK-NEXT: xtn v0.8b, v0.8h
; CHECK-NEXT: zip1 v1.8b, v0.8b, v0.8b ; CHECK-NEXT: zip1 v1.8b, v0.8b, v0.8b
; CHECK-NEXT: zip2 v0.8b, v0.8b, v0.8b ; CHECK-NEXT: zip2 v0.8b, v0.8b, v0.8b
; CHECK-NEXT: ushll v1.4s, v1.4h, #0 ; CHECK-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-NEXT: shl v1.4s, v1.4s, #31 ; CHECK-NEXT: shl v1.4s, v1.4s, #31
; CHECK-NEXT: shl v2.4s, v0.4s, #31 ; CHECK-NEXT: shl v2.4s, v0.4s, #31
; CHECK-NEXT: sshr v0.4s, v1.4s, #31 ; CHECK-NEXT: sshr v0.4s, v1.4s, #31
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; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: uzp2 v1.4s, v3.4s, v2.4s ; CHECK-NEXT: uzp2 v1.4s, v3.4s, v2.4s
; CHECK-NEXT: ushr v2.4s, v0.4s, #24 ; CHECK-NEXT: ushr v2.4s, v0.4s, #24
; CHECK-NEXT: mov w8, v0.s[3] ; CHECK-NEXT: mov w8, v0.s[3]
; CHECK-NEXT: mov w9, v0.s[2] ; CHECK-NEXT: mov w9, v0.s[2]
; CHECK-NEXT: mov w10, v0.s[1] ; CHECK-NEXT: mov w10, v0.s[1]
; CHECK-NEXT: fmov w11, s0 ; CHECK-NEXT: fmov w11, s0
; CHECK-NEXT: cmeq v0.4s, v1.4s, #0 ; CHECK-NEXT: cmeq v0.4s, v1.4s, #0
; CHECK-NEXT: cmeq v1.4s, v2.4s, #0 ; CHECK-NEXT: cmtst v1.4s, v2.4s, v2.4s
; CHECK-NEXT: sturh w8, [x0, #9] ; CHECK-NEXT: sturh w8, [x0, #9]
; CHECK-NEXT: lsr w8, w8, #16 ; CHECK-NEXT: lsr w8, w8, #16
; CHECK-NEXT: mvn v1.16b, v1.16b
; CHECK-NEXT: strh w9, [x0, #6] ; CHECK-NEXT: strh w9, [x0, #6]
; CHECK-NEXT: sturh w10, [x0, #3] ; CHECK-NEXT: sturh w10, [x0, #3]
; CHECK-NEXT: lsr w9, w9, #16 ; CHECK-NEXT: lsr w9, w9, #16
; CHECK-NEXT: lsr w10, w10, #16 ; CHECK-NEXT: lsr w10, w10, #16
; CHECK-NEXT: strb w8, [x0, #11]
; CHECK-NEXT: orn v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orn v0.16b, v1.16b, v0.16b
; CHECK-NEXT: strb w8, [x0, #11]
; CHECK-NEXT: lsr w8, w11, #16 ; CHECK-NEXT: lsr w8, w11, #16
; CHECK-NEXT: strh w11, [x0] ; CHECK-NEXT: strh w11, [x0]
; CHECK-NEXT: strb w9, [x0, #8] ; CHECK-NEXT: strb w9, [x0, #8]
; CHECK-NEXT: strb w10, [x0, #5] ; CHECK-NEXT: strb w10, [x0, #5]
; CHECK-NEXT: strb w8, [x0, #2] ; CHECK-NEXT: strb w8, [x0, #2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<4 x i24>, <4 x i1>} @llvm.umul.with.overflow.v4i24(<4 x i24> %a0, <4 x i24> %a1) %t = call {<4 x i24>, <4 x i1>} @llvm.umul.with.overflow.v4i24(<4 x i24> %a0, <4 x i24> %a1)
%val = extractvalue {<4 x i24>, <4 x i1>} %t, 0 %val = extractvalue {<4 x i24>, <4 x i1>} %t, 0
%obit = extractvalue {<4 x i24>, <4 x i1>} %t, 1 %obit = extractvalue {<4 x i24>, <4 x i1>} %t, 1
%res = sext <4 x i1> %obit to <4 x i32> %res = sext <4 x i1> %obit to <4 x i32>
store <4 x i24> %val, <4 x i24>* %p2 store <4 x i24> %val, <4 x i24>* %p2
ret <4 x i32> %res ret <4 x i32> %res
} }
define <4 x i32> @umulo_v4i1(<4 x i1> %a0, <4 x i1> %a1, <4 x i1>* %p2) nounwind { define <4 x i32> @umulo_v4i1(<4 x i1> %a0, <4 x i1> %a1, <4 x i1>* %p2) nounwind {
; CHECK-LABEL: umulo_v4i1: ; CHECK-LABEL: umulo_v4i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.4h, #1 ; CHECK-NEXT: movi v2.4h, #1
; CHECK-NEXT: and v1.8b, v1.8b, v2.8b ; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b ; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
; CHECK-NEXT: umull v0.4s, v0.4h, v1.4h ; CHECK-NEXT: umull v0.4s, v0.4h, v1.4h
; CHECK-NEXT: shrn v1.4h, v0.4s, #16 ; CHECK-NEXT: xtn v2.4h, v0.4s
; CHECK-NEXT: xtn v0.4h, v0.4s ; CHECK-NEXT: umov w9, v2.h[1]
; CHECK-NEXT: umov w9, v0.h[1] ; CHECK-NEXT: umov w8, v2.h[0]
; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: and w9, w9, #0x1 ; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: shrn v1.4h, v0.4s, #16
; CHECK-NEXT: bfi w8, w9, #1, #1 ; CHECK-NEXT: bfi w8, w9, #1, #1
; CHECK-NEXT: umov w9, v0.h[2] ; CHECK-NEXT: umov w9, v2.h[2]
; CHECK-NEXT: ushr v2.4h, v0.4h, #1 ; CHECK-NEXT: cmeq v0.4h, v1.4h, #0
; CHECK-NEXT: ushr v1.4h, v2.4h, #1
; CHECK-NEXT: and w9, w9, #0x1 ; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: cmtst v1.4h, v1.4h, v1.4h
; CHECK-NEXT: bfi w8, w9, #2, #1 ; CHECK-NEXT: bfi w8, w9, #2, #1
; CHECK-NEXT: umov w9, v0.h[3] ; CHECK-NEXT: umov w9, v2.h[3]
; CHECK-NEXT: cmeq v0.4h, v2.4h, #0 ; CHECK-NEXT: orn v0.8b, v1.8b, v0.8b
; CHECK-NEXT: cmeq v1.4h, v1.4h, #0
; CHECK-NEXT: mvn v0.8b, v0.8b
; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
; CHECK-NEXT: bfi w8, w9, #3, #29 ; CHECK-NEXT: bfi w8, w9, #3, #29
; CHECK-NEXT: sshll v0.4s, v0.4h, #0 ; CHECK-NEXT: sshll v0.4s, v0.4h, #0
; CHECK-NEXT: and w8, w8, #0xf ; CHECK-NEXT: and w8, w8, #0xf
; CHECK-NEXT: strb w8, [x0] ; CHECK-NEXT: strb w8, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<4 x i1>, <4 x i1>} @llvm.umul.with.overflow.v4i1(<4 x i1> %a0, <4 x i1> %a1) %t = call {<4 x i1>, <4 x i1>} @llvm.umul.with.overflow.v4i1(<4 x i1> %a0, <4 x i1> %a1)
%val = extractvalue {<4 x i1>, <4 x i1>} %t, 0 %val = extractvalue {<4 x i1>, <4 x i1>} %t, 0
%obit = extractvalue {<4 x i1>, <4 x i1>} %t, 1 %obit = extractvalue {<4 x i1>, <4 x i1>} %t, 1
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