[RISCV] Initial support for insert/extract subvector

[arcbbb]

Summary

This patch handles cast-like insert_subvector & extract_subvector
in which case:

1. index starts from 0.
2. inserting a fixed-width vector into a scalable vector, or extracting a fixed-width vector from a scalable vector.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

33

Line this up with first argument on the previous line

38

Would it be simpler to get the LMUL from the size of the fixed part of the scalable type? We don't need subtarget for that.

850

This can be Node->getConstantOperandVal(2) != 0

862

Is this line more than 80 columns? It looks long to me.

863

Just use SDValue. auto doesn't save much here.

[arcbbb]

updates:

1. clang-formatted.
2. address Craig's comments.

[arcbbb]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

38

I was considering it was possible to insert/extract an M1 fixed-width vector into/from an M2 scalable vector, so I get the LMUL from the fixed-width one.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

38

If that happened. I think we would need to create an EXTRACT_SUBREG/INSERT_SUBREG for the register allocator to make sense of it.

850

I'm not sure what this is checking now. cast should return a pointer, and this is checking that the pointer isn't null I think? Which it shouldn't be null so now I"m not sure how this code passes.

My suggestion was to use "Node->getConstantOperandVal(2) != 0"

866

This should probably also not use auto. At the very least it needs to have the * so its obvious it is a pointer as clang-tidy is suggesting.

873

Node->getConstantOperandVal(2) != 0

[arcbbb]

Updates.

1. Fixed use of ConstantOperandVal()
2. Fixed auto.
3. Changed getRegClassIDForFixedLengthVector to getRegClassIDForLMUL

[arcbbb]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

38

Got it! I changed it to getRegClassIDForLMUL.

[craig.topper]

LGTM

[frasercrmck]

LGTM also.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 using namespace llvm;
 
 #define DEBUG_TYPE "riscv-isel"
 
 void RISCVDAGToDAGISel::PostprocessISelDAG() {
   doPeepholeLoadStoreADDI();
 }
 
+static unsigned
+getRegClassIDForFixedLengthVector(const SelectionDAG *DAG, MVT VT,
+                                  const RISCVSubtarget *Subtarget) {
+  assert(VT.isFixedLengthVector() &&
+         DAG->getTargetLoweringInfo().isTypeLegal(VT) &&
+         "Expected legal fixed length vector!");
+
+  unsigned LMul = Subtarget->getLMULForFixedLengthVector(VT);
+  unsigned RCID;
+  if (LMul == 1)
+    RCID = RISCV::VRRegClassID;
+  else if (LMul == 2)
+    RCID = RISCV::VRM2RegClassID;
+  else if (LMul == 4)
+    RCID = RISCV::VRM4RegClassID;
+  else if (LMul == 8)
+    RCID = RISCV::VRM8RegClassID;
+  else
+    llvm_unreachable("Unexpected LMul!");
+  return RCID;
+}
+
 static SDNode *selectImm(SelectionDAG *CurDAG, const SDLoc &DL, int64_t Imm,
                          MVT XLenVT) {
   RISCVMatInt::InstSeq Seq;
   RISCVMatInt::generateInstSeq(Imm, XLenVT == MVT::i64, Seq);
 
   SDNode *Result = nullptr;
   SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT);
   for (RISCVMatInt::Inst &Inst : Seq) {
case ISD::INTRINSIC_VOID: {
     case Intrinsic::riscv_vsuxseg7_mask:
     case Intrinsic::riscv_vsuxseg8_mask: {
       selectVSXSEGMask(Node, IntNo);
       return;
     }
     }
     break;
   }
+  case ISD::INSERT_SUBVECTOR: {
+    // Bail when not a "cast" like insert_subvector.
+    if (cast<ConstantSDNode>(Node->getOperand(2)) != 0)
+      break;
+    if (!Node->getOperand(0).isUndef())
+      break;
+
+    // Bail when normal isel should do the job.
+    EVT InVT = Node->getOperand(1).getValueType();
+    if (VT.isFixedLengthVector() || InVT.isScalableVector())
+      break;
+
+    SDValue V = Node->getOperand(1);
+    SDLoc DL(V);
+    unsigned RegClassID = getRegClassIDForFixedLengthVector(
+        CurDAG, V.getSimpleValueType(), Subtarget);
+    SDValue RC =
+        CurDAG->getTargetConstant(RegClassID, DL, Subtarget->getXLenVT());
+    auto NewNode =
+        CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, DL, VT, V, RC);
+    ReplaceNode(Node, NewNode);
+    return;
+  }
+  case ISD::EXTRACT_SUBVECTOR: {
+    // Bail when not a "cast" like extract_subvector.
+    if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue() != 0)
+      break;
+
+    // Bail when normal isel can do the job.
+    EVT InVT = Node->getOperand(0).getValueType();
+    if (VT.isScalableVector() || InVT.isFixedLengthVector())
+      break;
+
+    SDValue V = Node->getOperand(0);
+    SDLoc DL(V);
+    unsigned RegClassID =
+        getRegClassIDForFixedLengthVector(CurDAG, VT, Subtarget);
+    SDValue RC =
+        CurDAG->getTargetConstant(RegClassID, DL, Subtarget->getXLenVT());
+    auto NewNode =
+        CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, DL, VT, V, RC);
+    ReplaceNode(Node, NewNode);
+    return;
+  }
   }
 
   // Select the default instruction.
   SelectCode(Node);
 }
 
 bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
     const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

 ; LMULMAX1-RV64-NEXT:    vse64.v v26, (a2)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = load <4 x i64>, <4 x i64>* %x
   %b = load <4 x i64>, <4 x i64>* %y
   %c = urem <4 x i64> %a, %b
   store <4 x i64> %c, <4 x i64>* %x
   ret void
 }
+
+define void @extract_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
+; LMULMAX2-LABEL: extract_v4i64:
+; LMULMAX2:       # %bb.0:
+; LMULMAX2-NEXT:    addi a2, zero, 4
+; LMULMAX2-NEXT:    vsetvli a3, a2, e64,m2,ta,mu
+; LMULMAX2-NEXT:    vle64.v v26, (a0)
+; LMULMAX2-NEXT:    vle64.v v28, (a1)
+; LMULMAX2-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; LMULMAX2-NEXT:    vadd.vv v26, v26, v28
+; LMULMAX2-NEXT:    vse64.v v26, (a0)
+; LMULMAX2-NEXT:    ret
+;
+; LMULMAX1-RV32-LABEL: extract_v4i64:
+; LMULMAX1-RV32:       # %bb.0:
+; LMULMAX1-RV32-NEXT:    addi a2, zero, 2
+; LMULMAX1-RV32-NEXT:    vsetvli a3, a2, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT:    addi a3, a0, 16
+; LMULMAX1-RV32-NEXT:    vle64.v v26, (a3)
+; LMULMAX1-RV32-NEXT:    vle64.v v27, (a1)
+; LMULMAX1-RV32-NEXT:    addi a1, a1, 16
+; LMULMAX1-RV32-NEXT:    vle64.v v28, (a1)
+; LMULMAX1-RV32-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vadd.vv v26, v26, v28
+; LMULMAX1-RV32-NEXT:    vadd.vv v25, v25, v27
+; LMULMAX1-RV32-NEXT:    vse64.v v25, (a0)
+; LMULMAX1-RV32-NEXT:    vse64.v v26, (a3)
+; LMULMAX1-RV32-NEXT:    ret
+;
+; LMULMAX1-RV64-LABEL: extract_v4i64:
+; LMULMAX1-RV64:       # %bb.0:
+; LMULMAX1-RV64-NEXT:    addi a2, zero, 2
+; LMULMAX1-RV64-NEXT:    vsetvli a3, a2, e64,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    addi a3, a0, 16
+; LMULMAX1-RV64-NEXT:    vle64.v v26, (a3)
+; LMULMAX1-RV64-NEXT:    vle64.v v27, (a1)
+; LMULMAX1-RV64-NEXT:    addi a1, a1, 16
+; LMULMAX1-RV64-NEXT:    vle64.v v28, (a1)
+; LMULMAX1-RV64-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vadd.vv v26, v26, v28
+; LMULMAX1-RV64-NEXT:    vadd.vv v25, v25, v27
+; LMULMAX1-RV64-NEXT:    vse64.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    vse64.v v26, (a3)
+; LMULMAX1-RV64-NEXT:    ret
+  %a = load <4 x i64>, <4 x i64>* %x
+  %b = load <4 x i64>, <4 x i64>* %y
+  br label %"compute"
+"compute":
+  %c = add <4 x i64> %a, %b
+  store <4 x i64> %c, <4 x i64>* %x
+  ret void
+}